drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 #define INTEL_P2_NUM                  2
  63 typedef struct intel_limit intel_limit_t;
  64 struct intel_limit {
  65         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  66         intel_p2_t          p2;
  67 };
  68
  69 /* FDI */
  70 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t intel_limits_vlv_dp = {
 340         .dot = { .min = 25000, .max = 270000 },
 341         .vco = { .min = 4000000, .max = 6000000 },
 342         .n = { .min = 1, .max = 7 },
 343         .m = { .min = 22, .max = 450 },
 344         .m1 = { .min = 2, .max = 3 },
 345         .m2 = { .min = 11, .max = 156 },
 346         .p = { .min = 10, .max = 30 },
 347         .p1 = { .min = 1, .max = 3 },
 348         .p2 = { .dot_limit = 270000,
 349                 .p2_slow = 2, .p2_fast = 20 },
 350 };
 351
 352 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 353                                                 int refclk)
 354 {
 355         struct drm_device *dev = crtc->dev;
 356         const intel_limit_t *limit;
 357
 358         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 359                 if (intel_is_dual_link_lvds(dev)) {
 360                         if (refclk == 100000)
 361                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 362                         else
 363                                 limit = &intel_limits_ironlake_dual_lvds;
 364                 } else {
 365                         if (refclk == 100000)
 366                                 limit = &intel_limits_ironlake_single_lvds_100m;
 367                         else
 368                                 limit = &intel_limits_ironlake_single_lvds;
 369                 }
 370         } else
 371                 limit = &intel_limits_ironlake_dac;
 372
 373         return limit;
 374 }
 375
 376 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev))
 383                         limit = &intel_limits_g4x_dual_channel_lvds;
 384                 else
 385                         limit = &intel_limits_g4x_single_channel_lvds;
 386         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 387                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 388                 limit = &intel_limits_g4x_hdmi;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 390                 limit = &intel_limits_g4x_sdvo;
 391         } else /* The option is for other outputs */
 392                 limit = &intel_limits_i9xx_sdvo;
 393
 394         return limit;
 395 }
 396
 397 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 398 {
 399         struct drm_device *dev = crtc->dev;
 400         const intel_limit_t *limit;
 401
 402         if (HAS_PCH_SPLIT(dev))
 403                 limit = intel_ironlake_limit(crtc, refclk);
 404         else if (IS_G4X(dev)) {
 405                 limit = intel_g4x_limit(crtc);
 406         } else if (IS_PINEVIEW(dev)) {
 407                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 408                         limit = &intel_limits_pineview_lvds;
 409                 else
 410                         limit = &intel_limits_pineview_sdvo;
 411         } else if (IS_VALLEYVIEW(dev)) {
 412                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 413                         limit = &intel_limits_vlv_dac;
 414                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 415                         limit = &intel_limits_vlv_hdmi;
 416                 else
 417                         limit = &intel_limits_vlv_dp;
 418         } else if (!IS_GEN2(dev)) {
 419                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 420                         limit = &intel_limits_i9xx_lvds;
 421                 else
 422                         limit = &intel_limits_i9xx_sdvo;
 423         } else {
 424                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 425                         limit = &intel_limits_i8xx_lvds;
 426                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 427                         limit = &intel_limits_i8xx_dvo;
 428                 else
 429                         limit = &intel_limits_i8xx_dac;
 430         }
 431         return limit;
 432 }
 433
 434 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 435 static void pineview_clock(int refclk, intel_clock_t *clock)
 436 {
 437         clock->m = clock->m2 + 2;
 438         clock->p = clock->p1 * clock->p2;
 439         clock->vco = refclk * clock->m / clock->n;
 440         clock->dot = clock->vco / clock->p;
 441 }
 442
 443 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 444 {
 445         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 446 }
 447
 448 static void i9xx_clock(int refclk, intel_clock_t *clock)
 449 {
 450         clock->m = i9xx_dpll_compute_m(clock);
 451         clock->p = clock->p1 * clock->p2;
 452         clock->vco = refclk * clock->m / (clock->n + 2);
 453         clock->dot = clock->vco / clock->p;
 454 }
 455
 456 /**
 457  * Returns whether any output on the specified pipe is of the specified type
 458  */
 459 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 460 {
 461         struct drm_device *dev = crtc->dev;
 462         struct intel_encoder *encoder;
 463
 464         for_each_encoder_on_crtc(dev, crtc, encoder)
 465                 if (encoder->type == type)
 466                         return true;
 467
 468         return false;
 469 }
 470
 471 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 472 /**
 473  * Returns whether the given set of divisors are valid for a given refclk with
 474  * the given connectors.
 475  */
 476
 477 static bool intel_PLL_is_valid(struct drm_device *dev,
 478                                const intel_limit_t *limit,
 479                                const intel_clock_t *clock)
 480 {
 481         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 482                 INTELPllInvalid("p1 out of range\n");
 483         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 484                 INTELPllInvalid("p out of range\n");
 485         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 486                 INTELPllInvalid("m2 out of range\n");
 487         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 488                 INTELPllInvalid("m1 out of range\n");
 489         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 490                 INTELPllInvalid("m1 <= m2\n");
 491         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 492                 INTELPllInvalid("m out of range\n");
 493         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 494                 INTELPllInvalid("n out of range\n");
 495         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 496                 INTELPllInvalid("vco out of range\n");
 497         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 498          * connector, etc., rather than just a single range.
 499          */
 500         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 501                 INTELPllInvalid("dot out of range\n");
 502
 503         return true;
 504 }
 505
 506 static bool
 507 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 508                     int target, int refclk, intel_clock_t *match_clock,
 509                     intel_clock_t *best_clock)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         intel_clock_t clock;
 513         int err = target;
 514
 515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 516                 /*
 517                  * For LVDS just rely on its current settings for dual-channel.
 518                  * We haven't figured out how to reliably set up different
 519                  * single/dual channel state, if we even can.
 520                  */
 521                 if (intel_is_dual_link_lvds(dev))
 522                         clock.p2 = limit->p2.p2_fast;
 523                 else
 524                         clock.p2 = limit->p2.p2_slow;
 525         } else {
 526                 if (target < limit->p2.dot_limit)
 527                         clock.p2 = limit->p2.p2_slow;
 528                 else
 529                         clock.p2 = limit->p2.p2_fast;
 530         }
 531
 532         memset(best_clock, 0, sizeof(*best_clock));
 533
 534         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 535              clock.m1++) {
 536                 for (clock.m2 = limit->m2.min;
 537                      clock.m2 <= limit->m2.max; clock.m2++) {
 538                         if (clock.m2 >= clock.m1)
 539                                 break;
 540                         for (clock.n = limit->n.min;
 541                              clock.n <= limit->n.max; clock.n++) {
 542                                 for (clock.p1 = limit->p1.min;
 543                                         clock.p1 <= limit->p1.max; clock.p1++) {
 544                                         int this_err;
 545
 546                                         i9xx_clock(refclk, &clock);
 547                                         if (!intel_PLL_is_valid(dev, limit,
 548                                                                 &clock))
 549                                                 continue;
 550                                         if (match_clock &&
 551                                             clock.p != match_clock->p)
 552                                                 continue;
 553
 554                                         this_err = abs(clock.dot - target);
 555                                         if (this_err < err) {
 556                                                 *best_clock = clock;
 557                                                 err = this_err;
 558                                         }
 559                                 }
 560                         }
 561                 }
 562         }
 563
 564         return (err != target);
 565 }
 566
 567 static bool
 568 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 569                    int target, int refclk, intel_clock_t *match_clock,
 570                    intel_clock_t *best_clock)
 571 {
 572         struct drm_device *dev = crtc->dev;
 573         intel_clock_t clock;
 574         int err = target;
 575
 576         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 577                 /*
 578                  * For LVDS just rely on its current settings for dual-channel.
 579                  * We haven't figured out how to reliably set up different
 580                  * single/dual channel state, if we even can.
 581                  */
 582                 if (intel_is_dual_link_lvds(dev))
 583                         clock.p2 = limit->p2.p2_fast;
 584                 else
 585                         clock.p2 = limit->p2.p2_slow;
 586         } else {
 587                 if (target < limit->p2.dot_limit)
 588                         clock.p2 = limit->p2.p2_slow;
 589                 else
 590                         clock.p2 = limit->p2.p2_fast;
 591         }
 592
 593         memset(best_clock, 0, sizeof(*best_clock));
 594
 595         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 596              clock.m1++) {
 597                 for (clock.m2 = limit->m2.min;
 598                      clock.m2 <= limit->m2.max; clock.m2++) {
 599                         for (clock.n = limit->n.min;
 600                              clock.n <= limit->n.max; clock.n++) {
 601                                 for (clock.p1 = limit->p1.min;
 602                                         clock.p1 <= limit->p1.max; clock.p1++) {
 603                                         int this_err;
 604
 605                                         pineview_clock(refclk, &clock);
 606                                         if (!intel_PLL_is_valid(dev, limit,
 607                                                                 &clock))
 608                                                 continue;
 609                                         if (match_clock &&
 610                                             clock.p != match_clock->p)
 611                                                 continue;
 612
 613                                         this_err = abs(clock.dot - target);
 614                                         if (this_err < err) {
 615                                                 *best_clock = clock;
 616                                                 err = this_err;
 617                                         }
 618                                 }
 619                         }
 620                 }
 621         }
 622
 623         return (err != target);
 624 }
 625
 626 static bool
 627 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 628                    int target, int refclk, intel_clock_t *match_clock,
 629                    intel_clock_t *best_clock)
 630 {
 631         struct drm_device *dev = crtc->dev;
 632         intel_clock_t clock;
 633         int max_n;
 634         bool found;
 635         /* approximately equals target * 0.00585 */
 636         int err_most = (target >> 8) + (target >> 9);
 637         found = false;
 638
 639         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 640                 if (intel_is_dual_link_lvds(dev))
 641                         clock.p2 = limit->p2.p2_fast;
 642                 else
 643                         clock.p2 = limit->p2.p2_slow;
 644         } else {
 645                 if (target < limit->p2.dot_limit)
 646                         clock.p2 = limit->p2.p2_slow;
 647                 else
 648                         clock.p2 = limit->p2.p2_fast;
 649         }
 650
 651         memset(best_clock, 0, sizeof(*best_clock));
 652         max_n = limit->n.max;
 653         /* based on hardware requirement, prefer smaller n to precision */
 654         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 655                 /* based on hardware requirement, prefere larger m1,m2 */
 656                 for (clock.m1 = limit->m1.max;
 657                      clock.m1 >= limit->m1.min; clock.m1--) {
 658                         for (clock.m2 = limit->m2.max;
 659                              clock.m2 >= limit->m2.min; clock.m2--) {
 660                                 for (clock.p1 = limit->p1.max;
 661                                      clock.p1 >= limit->p1.min; clock.p1--) {
 662                                         int this_err;
 663
 664                                         i9xx_clock(refclk, &clock);
 665                                         if (!intel_PLL_is_valid(dev, limit,
 666                                                                 &clock))
 667                                                 continue;
 668
 669                                         this_err = abs(clock.dot - target);
 670                                         if (this_err < err_most) {
 671                                                 *best_clock = clock;
 672                                                 err_most = this_err;
 673                                                 max_n = clock.n;
 674                                                 found = true;
 675                                         }
 676                                 }
 677                         }
 678                 }
 679         }
 680         return found;
 681 }
 682
 683 static bool
 684 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 685                    int target, int refclk, intel_clock_t *match_clock,
 686                    intel_clock_t *best_clock)
 687 {
 688         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 689         u32 m, n, fastclk;
 690         u32 updrate, minupdate, fracbits, p;
 691         unsigned long bestppm, ppm, absppm;
 692         int dotclk, flag;
 693
 694         flag = 0;
 695         dotclk = target * 1000;
 696         bestppm = 1000000;
 697         ppm = absppm = 0;
 698         fastclk = dotclk / (2*100);
 699         updrate = 0;
 700         minupdate = 19200;
 701         fracbits = 1;
 702         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 703         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 704
 705         /* based on hardware requirement, prefer smaller n to precision */
 706         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 707                 updrate = refclk / n;
 708                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 709                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 710                                 if (p2 > 10)
 711                                         p2 = p2 - 1;
 712                                 p = p1 * p2;
 713                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 714                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 715                                         m2 = (((2*(fastclk * p * n / m1 )) +
 716                                                refclk) / (2*refclk));
 717                                         m = m1 * m2;
 718                                         vco = updrate * m;
 719                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 720                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 721                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 722                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 723                                                         bestppm = 0;
 724                                                         flag = 1;
 725                                                 }
 726                                                 if (absppm < bestppm - 10) {
 727                                                         bestppm = absppm;
 728                                                         flag = 1;
 729                                                 }
 730                                                 if (flag) {
 731                                                         bestn = n;
 732                                                         bestm1 = m1;
 733                                                         bestm2 = m2;
 734                                                         bestp1 = p1;
 735                                                         bestp2 = p2;
 736                                                         flag = 0;
 737                                                 }
 738                                         }
 739                                 }
 740                         }
 741                 }
 742         }
 743         best_clock->n = bestn;
 744         best_clock->m1 = bestm1;
 745         best_clock->m2 = bestm2;
 746         best_clock->p1 = bestp1;
 747         best_clock->p2 = bestp2;
 748
 749         return true;
 750 }
 751
 752 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 753                                              enum pipe pipe)
 754 {
 755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757
 758         return intel_crtc->config.cpu_transcoder;
 759 }
 760
 761 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 762 {
 763         struct drm_i915_private *dev_priv = dev->dev_private;
 764         u32 frame, frame_reg = PIPEFRAME(pipe);
 765
 766         frame = I915_READ(frame_reg);
 767
 768         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 769                 DRM_DEBUG_KMS("vblank wait timed out\n");
 770 }
 771
 772 /**
 773  * intel_wait_for_vblank - wait for vblank on a given pipe
 774  * @dev: drm device
 775  * @pipe: pipe to wait for
 776  *
 777  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 778  * mode setting code.
 779  */
 780 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 781 {
 782         struct drm_i915_private *dev_priv = dev->dev_private;
 783         int pipestat_reg = PIPESTAT(pipe);
 784
 785         if (INTEL_INFO(dev)->gen >= 5) {
 786                 ironlake_wait_for_vblank(dev, pipe);
 787                 return;
 788         }
 789
 790         /* Clear existing vblank status. Note this will clear any other
 791          * sticky status fields as well.
 792          *
 793          * This races with i915_driver_irq_handler() with the result
 794          * that either function could miss a vblank event.  Here it is not
 795          * fatal, as we will either wait upon the next vblank interrupt or
 796          * timeout.  Generally speaking intel_wait_for_vblank() is only
 797          * called during modeset at which time the GPU should be idle and
 798          * should *not* be performing page flips and thus not waiting on
 799          * vblanks...
 800          * Currently, the result of us stealing a vblank from the irq
 801          * handler is that a single frame will be skipped during swapbuffers.
 802          */
 803         I915_WRITE(pipestat_reg,
 804                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 805
 806         /* Wait for vblank interrupt bit to set */
 807         if (wait_for(I915_READ(pipestat_reg) &
 808                      PIPE_VBLANK_INTERRUPT_STATUS,
 809                      50))
 810                 DRM_DEBUG_KMS("vblank wait timed out\n");
 811 }
 812
 813 /*
 814  * intel_wait_for_pipe_off - wait for pipe to turn off
 815  * @dev: drm device
 816  * @pipe: pipe to wait for
 817  *
 818  * After disabling a pipe, we can't wait for vblank in the usual way,
 819  * spinning on the vblank interrupt status bit, since we won't actually
 820  * see an interrupt when the pipe is disabled.
 821  *
 822  * On Gen4 and above:
 823  *   wait for the pipe register state bit to turn off
 824  *
 825  * Otherwise:
 826  *   wait for the display line value to settle (it usually
 827  *   ends up stopping at the start of the next frame).
 828  *
 829  */
 830 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 834                                                                       pipe);
 835
 836         if (INTEL_INFO(dev)->gen >= 4) {
 837                 int reg = PIPECONF(cpu_transcoder);
 838
 839                 /* Wait for the Pipe State to go off */
 840                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 841                              100))
 842                         WARN(1, "pipe_off wait timed out\n");
 843         } else {
 844                 u32 last_line, line_mask;
 845                 int reg = PIPEDSL(pipe);
 846                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 847
 848                 if (IS_GEN2(dev))
 849                         line_mask = DSL_LINEMASK_GEN2;
 850                 else
 851                         line_mask = DSL_LINEMASK_GEN3;
 852
 853                 /* Wait for the display line to settle */
 854                 do {
 855                         last_line = I915_READ(reg) & line_mask;
 856                         mdelay(5);
 857                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 858                          time_after(timeout, jiffies));
 859                 if (time_after(jiffies, timeout))
 860                         WARN(1, "pipe_off wait timed out\n");
 861         }
 862 }
 863
 864 /*
 865  * ibx_digital_port_connected - is the specified port connected?
 866  * @dev_priv: i915 private structure
 867  * @port: the port to test
 868  *
 869  * Returns true if @port is connected, false otherwise.
 870  */
 871 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 872                                 struct intel_digital_port *port)
 873 {
 874         u32 bit;
 875
 876         if (HAS_PCH_IBX(dev_priv->dev)) {
 877                 switch(port->port) {
 878                 case PORT_B:
 879                         bit = SDE_PORTB_HOTPLUG;
 880                         break;
 881                 case PORT_C:
 882                         bit = SDE_PORTC_HOTPLUG;
 883                         break;
 884                 case PORT_D:
 885                         bit = SDE_PORTD_HOTPLUG;
 886                         break;
 887                 default:
 888                         return true;
 889                 }
 890         } else {
 891                 switch(port->port) {
 892                 case PORT_B:
 893                         bit = SDE_PORTB_HOTPLUG_CPT;
 894                         break;
 895                 case PORT_C:
 896                         bit = SDE_PORTC_HOTPLUG_CPT;
 897                         break;
 898                 case PORT_D:
 899                         bit = SDE_PORTD_HOTPLUG_CPT;
 900                         break;
 901                 default:
 902                         return true;
 903                 }
 904         }
 905
 906         return I915_READ(SDEISR) & bit;
 907 }
 908
 909 static const char *state_string(bool enabled)
 910 {
 911         return enabled ? "on" : "off";
 912 }
 913
 914 /* Only for pre-ILK configs */
 915 void assert_pll(struct drm_i915_private *dev_priv,
 916                 enum pipe pipe, bool state)
 917 {
 918         int reg;
 919         u32 val;
 920         bool cur_state;
 921
 922         reg = DPLL(pipe);
 923         val = I915_READ(reg);
 924         cur_state = !!(val & DPLL_VCO_ENABLE);
 925         WARN(cur_state != state,
 926              "PLL state assertion failure (expected %s, current %s)\n",
 927              state_string(state), state_string(cur_state));
 928 }
 929
 930 struct intel_shared_dpll *
 931 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 932 {
 933         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 934
 935         if (crtc->config.shared_dpll < 0)
 936                 return NULL;
 937
 938         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 939 }
 940
 941 /* For ILK+ */
 942 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 943                         struct intel_shared_dpll *pll,
 944                         bool state)
 945 {
 946         bool cur_state;
 947         struct intel_dpll_hw_state hw_state;
 948
 949         if (HAS_PCH_LPT(dev_priv->dev)) {
 950                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 951                 return;
 952         }
 953
 954         if (WARN (!pll,
 955                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 956                 return;
 957
 958         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 959         WARN(cur_state != state,
 960              "%s assertion failure (expected %s, current %s)\n",
 961              pll->name, state_string(state), state_string(cur_state));
 962 }
 963
 964 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 965                           enum pipe pipe, bool state)
 966 {
 967         int reg;
 968         u32 val;
 969         bool cur_state;
 970         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 971                                                                       pipe);
 972
 973         if (HAS_DDI(dev_priv->dev)) {
 974                 /* DDI does not have a specific FDI_TX register */
 975                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 976                 val = I915_READ(reg);
 977                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 978         } else {
 979                 reg = FDI_TX_CTL(pipe);
 980                 val = I915_READ(reg);
 981                 cur_state = !!(val & FDI_TX_ENABLE);
 982         }
 983         WARN(cur_state != state,
 984              "FDI TX state assertion failure (expected %s, current %s)\n",
 985              state_string(state), state_string(cur_state));
 986 }
 987 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 988 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 989
 990 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 991                           enum pipe pipe, bool state)
 992 {
 993         int reg;
 994         u32 val;
 995         bool cur_state;
 996
 997         reg = FDI_RX_CTL(pipe);
 998         val = I915_READ(reg);
 999         cur_state = !!(val & FDI_RX_ENABLE);
1000         WARN(cur_state != state,
1001              "FDI RX state assertion failure (expected %s, current %s)\n",
1002              state_string(state), state_string(cur_state));
1003 }
1004 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008                                       enum pipe pipe)
1009 {
1010         int reg;
1011         u32 val;
1012
1013         /* ILK FDI PLL is always enabled */
1014         if (dev_priv->info->gen == 5)
1015                 return;
1016
1017         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1018         if (HAS_DDI(dev_priv->dev))
1019                 return;
1020
1021         reg = FDI_TX_CTL(pipe);
1022         val = I915_READ(reg);
1023         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024 }
1025
1026 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027                        enum pipe pipe, bool state)
1028 {
1029         int reg;
1030         u32 val;
1031         bool cur_state;
1032
1033         reg = FDI_RX_CTL(pipe);
1034         val = I915_READ(reg);
1035         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036         WARN(cur_state != state,
1037              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038              state_string(state), state_string(cur_state));
1039 }
1040
1041 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042                                   enum pipe pipe)
1043 {
1044         int pp_reg, lvds_reg;
1045         u32 val;
1046         enum pipe panel_pipe = PIPE_A;
1047         bool locked = true;
1048
1049         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050                 pp_reg = PCH_PP_CONTROL;
1051                 lvds_reg = PCH_LVDS;
1052         } else {
1053                 pp_reg = PP_CONTROL;
1054                 lvds_reg = LVDS;
1055         }
1056
1057         val = I915_READ(pp_reg);
1058         if (!(val & PANEL_POWER_ON) ||
1059             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060                 locked = false;
1061
1062         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063                 panel_pipe = PIPE_B;
1064
1065         WARN(panel_pipe == pipe && locked,
1066              "panel assertion failure, pipe %c regs locked\n",
1067              pipe_name(pipe));
1068 }
1069
1070 void assert_pipe(struct drm_i915_private *dev_priv,
1071                  enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         /* if we need the pipe A quirk it must be always on */
1080         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081                 state = true;
1082
1083         if (!intel_display_power_enabled(dev_priv->dev,
1084                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1085                 cur_state = false;
1086         } else {
1087                 reg = PIPECONF(cpu_transcoder);
1088                 val = I915_READ(reg);
1089                 cur_state = !!(val & PIPECONF_ENABLE);
1090         }
1091
1092         WARN(cur_state != state,
1093              "pipe %c assertion failure (expected %s, current %s)\n",
1094              pipe_name(pipe), state_string(state), state_string(cur_state));
1095 }
1096
1097 static void assert_plane(struct drm_i915_private *dev_priv,
1098                          enum plane plane, bool state)
1099 {
1100         int reg;
1101         u32 val;
1102         bool cur_state;
1103
1104         reg = DSPCNTR(plane);
1105         val = I915_READ(reg);
1106         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107         WARN(cur_state != state,
1108              "plane %c assertion failure (expected %s, current %s)\n",
1109              plane_name(plane), state_string(state), state_string(cur_state));
1110 }
1111
1112 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
1115 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116                                    enum pipe pipe)
1117 {
1118         struct drm_device *dev = dev_priv->dev;
1119         int reg, i;
1120         u32 val;
1121         int cur_pipe;
1122
1123         /* Primary planes are fixed to pipes on gen4+ */
1124         if (INTEL_INFO(dev)->gen >= 4) {
1125                 reg = DSPCNTR(pipe);
1126                 val = I915_READ(reg);
1127                 WARN((val & DISPLAY_PLANE_ENABLE),
1128                      "plane %c assertion failure, should be disabled but not\n",
1129                      plane_name(pipe));
1130                 return;
1131         }
1132
1133         /* Need to check both planes against the pipe */
1134         for_each_pipe(i) {
1135                 reg = DSPCNTR(i);
1136                 val = I915_READ(reg);
1137                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138                         DISPPLANE_SEL_PIPE_SHIFT;
1139                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1140                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141                      plane_name(i), pipe_name(pipe));
1142         }
1143 }
1144
1145 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146                                     enum pipe pipe)
1147 {
1148         struct drm_device *dev = dev_priv->dev;
1149         int reg, i;
1150         u32 val;
1151
1152         if (IS_VALLEYVIEW(dev)) {
1153                 for (i = 0; i < dev_priv->num_plane; i++) {
1154                         reg = SPCNTR(pipe, i);
1155                         val = I915_READ(reg);
1156                         WARN((val & SP_ENABLE),
1157                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158                              sprite_name(pipe, i), pipe_name(pipe));
1159                 }
1160         } else if (INTEL_INFO(dev)->gen >= 7) {
1161                 reg = SPRCTL(pipe);
1162                 val = I915_READ(reg);
1163                 WARN((val & SPRITE_ENABLE),
1164                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1165                      plane_name(pipe), pipe_name(pipe));
1166         } else if (INTEL_INFO(dev)->gen >= 5) {
1167                 reg = DVSCNTR(pipe);
1168                 val = I915_READ(reg);
1169                 WARN((val & DVS_ENABLE),
1170                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1171                      plane_name(pipe), pipe_name(pipe));
1172         }
1173 }
1174
1175 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176 {
1177         u32 val;
1178         bool enabled;
1179
1180         if (HAS_PCH_LPT(dev_priv->dev)) {
1181                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182                 return;
1183         }
1184
1185         val = I915_READ(PCH_DREF_CONTROL);
1186         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187                             DREF_SUPERSPREAD_SOURCE_MASK));
1188         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189 }
1190
1191 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192                                            enum pipe pipe)
1193 {
1194         int reg;
1195         u32 val;
1196         bool enabled;
1197
1198         reg = PCH_TRANSCONF(pipe);
1199         val = I915_READ(reg);
1200         enabled = !!(val & TRANS_ENABLE);
1201         WARN(enabled,
1202              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203              pipe_name(pipe));
1204 }
1205
1206 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207                             enum pipe pipe, u32 port_sel, u32 val)
1208 {
1209         if ((val & DP_PORT_EN) == 0)
1210                 return false;
1211
1212         if (HAS_PCH_CPT(dev_priv->dev)) {
1213                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216                         return false;
1217         } else {
1218                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219                         return false;
1220         }
1221         return true;
1222 }
1223
1224 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225                               enum pipe pipe, u32 val)
1226 {
1227         if ((val & SDVO_ENABLE) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1232                         return false;
1233         } else {
1234                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1235                         return false;
1236         }
1237         return true;
1238 }
1239
1240 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241                               enum pipe pipe, u32 val)
1242 {
1243         if ((val & LVDS_PORT_EN) == 0)
1244                 return false;
1245
1246         if (HAS_PCH_CPT(dev_priv->dev)) {
1247                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248                         return false;
1249         } else {
1250                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251                         return false;
1252         }
1253         return true;
1254 }
1255
1256 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257                               enum pipe pipe, u32 val)
1258 {
1259         if ((val & ADPA_DAC_ENABLE) == 0)
1260                 return false;
1261         if (HAS_PCH_CPT(dev_priv->dev)) {
1262                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263                         return false;
1264         } else {
1265                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266                         return false;
1267         }
1268         return true;
1269 }
1270
1271 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe, int reg, u32 port_sel)
1273 {
1274         u32 val = I915_READ(reg);
1275         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1276              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1277              reg, pipe_name(pipe));
1278
1279         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280              && (val & DP_PIPEB_SELECT),
1281              "IBX PCH dp port still using transcoder B\n");
1282 }
1283
1284 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285                                      enum pipe pipe, int reg)
1286 {
1287         u32 val = I915_READ(reg);
1288         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1289              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290              reg, pipe_name(pipe));
1291
1292         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1293              && (val & SDVO_PIPE_B_SELECT),
1294              "IBX PCH hdmi port still using transcoder B\n");
1295 }
1296
1297 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298                                       enum pipe pipe)
1299 {
1300         int reg;
1301         u32 val;
1302
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1306
1307         reg = PCH_ADPA;
1308         val = I915_READ(reg);
1309         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1310              "PCH VGA enabled on transcoder %c, should be disabled\n",
1311              pipe_name(pipe));
1312
1313         reg = PCH_LVDS;
1314         val = I915_READ(reg);
1315         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1316              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1317              pipe_name(pipe));
1318
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1322 }
1323
1324 static void vlv_enable_pll(struct intel_crtc *crtc)
1325 {
1326         struct drm_device *dev = crtc->base.dev;
1327         struct drm_i915_private *dev_priv = dev->dev_private;
1328         int reg = DPLL(crtc->pipe);
1329         u32 dpll = crtc->config.dpll_hw_state.dpll;
1330
1331         assert_pipe_disabled(dev_priv, crtc->pipe);
1332
1333         /* No really, not for ILK+ */
1334         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1335
1336         /* PLL is protected by panel, make sure we can write it */
1337         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1338                 assert_panel_unlocked(dev_priv, crtc->pipe);
1339
1340         I915_WRITE(reg, dpll);
1341         POSTING_READ(reg);
1342         udelay(150);
1343
1344         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1345                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1346
1347         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1348         POSTING_READ(DPLL_MD(crtc->pipe));
1349
1350         /* We do this three times for luck */
1351         I915_WRITE(reg, dpll);
1352         POSTING_READ(reg);
1353         udelay(150); /* wait for warmup */
1354         I915_WRITE(reg, dpll);
1355         POSTING_READ(reg);
1356         udelay(150); /* wait for warmup */
1357         I915_WRITE(reg, dpll);
1358         POSTING_READ(reg);
1359         udelay(150); /* wait for warmup */
1360 }
1361
1362 static void i9xx_enable_pll(struct intel_crtc *crtc)
1363 {
1364         struct drm_device *dev = crtc->base.dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         int reg = DPLL(crtc->pipe);
1367         u32 dpll = crtc->config.dpll_hw_state.dpll;
1368
1369         assert_pipe_disabled(dev_priv, crtc->pipe);
1370
1371         /* No really, not for ILK+ */
1372         BUG_ON(dev_priv->info->gen >= 5);
1373
1374         /* PLL is protected by panel, make sure we can write it */
1375         if (IS_MOBILE(dev) && !IS_I830(dev))
1376                 assert_panel_unlocked(dev_priv, crtc->pipe);
1377
1378         I915_WRITE(reg, dpll);
1379
1380         /* Wait for the clocks to stabilize. */
1381         POSTING_READ(reg);
1382         udelay(150);
1383
1384         if (INTEL_INFO(dev)->gen >= 4) {
1385                 I915_WRITE(DPLL_MD(crtc->pipe),
1386                            crtc->config.dpll_hw_state.dpll_md);
1387         } else {
1388                 /* The pixel multiplier can only be updated once the
1389                  * DPLL is enabled and the clocks are stable.
1390                  *
1391                  * So write it again.
1392                  */
1393                 I915_WRITE(reg, dpll);
1394         }
1395
1396         /* We do this three times for luck */
1397         I915_WRITE(reg, dpll);
1398         POSTING_READ(reg);
1399         udelay(150); /* wait for warmup */
1400         I915_WRITE(reg, dpll);
1401         POSTING_READ(reg);
1402         udelay(150); /* wait for warmup */
1403         I915_WRITE(reg, dpll);
1404         POSTING_READ(reg);
1405         udelay(150); /* wait for warmup */
1406 }
1407
1408 /**
1409  * i9xx_disable_pll - disable a PLL
1410  * @dev_priv: i915 private structure
1411  * @pipe: pipe PLL to disable
1412  *
1413  * Disable the PLL for @pipe, making sure the pipe is off first.
1414  *
1415  * Note!  This is for pre-ILK only.
1416  */
1417 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1418 {
1419         /* Don't disable pipe A or pipe A PLLs if needed */
1420         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1421                 return;
1422
1423         /* Make sure the pipe isn't still relying on us */
1424         assert_pipe_disabled(dev_priv, pipe);
1425
1426         I915_WRITE(DPLL(pipe), 0);
1427         POSTING_READ(DPLL(pipe));
1428 }
1429
1430 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431 {
1432         u32 port_mask;
1433
1434         if (!port)
1435                 port_mask = DPLL_PORTB_READY_MASK;
1436         else
1437                 port_mask = DPLL_PORTC_READY_MASK;
1438
1439         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441                      'B' + port, I915_READ(DPLL(0)));
1442 }
1443
1444 /**
1445  * ironlake_enable_shared_dpll - enable PCH PLL
1446  * @dev_priv: i915 private structure
1447  * @pipe: pipe PLL to enable
1448  *
1449  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450  * drives the transcoder clock.
1451  */
1452 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1453 {
1454         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1455         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1456
1457         /* PCH PLLs only available on ILK, SNB and IVB */
1458         BUG_ON(dev_priv->info->gen < 5);
1459         if (WARN_ON(pll == NULL))
1460                 return;
1461
1462         if (WARN_ON(pll->refcount == 0))
1463                 return;
1464
1465         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466                       pll->name, pll->active, pll->on,
1467                       crtc->base.base.id);
1468
1469         if (pll->active++) {
1470                 WARN_ON(!pll->on);
1471                 assert_shared_dpll_enabled(dev_priv, pll);
1472                 return;
1473         }
1474         WARN_ON(pll->on);
1475
1476         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1477         pll->enable(dev_priv, pll);
1478         pll->on = true;
1479 }
1480
1481 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1482 {
1483         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1484         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1485
1486         /* PCH only available on ILK+ */
1487         BUG_ON(dev_priv->info->gen < 5);
1488         if (WARN_ON(pll == NULL))
1489                return;
1490
1491         if (WARN_ON(pll->refcount == 0))
1492                 return;
1493
1494         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495                       pll->name, pll->active, pll->on,
1496                       crtc->base.base.id);
1497
1498         if (WARN_ON(pll->active == 0)) {
1499                 assert_shared_dpll_disabled(dev_priv, pll);
1500                 return;
1501         }
1502
1503         assert_shared_dpll_enabled(dev_priv, pll);
1504         WARN_ON(!pll->on);
1505         if (--pll->active)
1506                 return;
1507
1508         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1509         pll->disable(dev_priv, pll);
1510         pll->on = false;
1511 }
1512
1513 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1514                                            enum pipe pipe)
1515 {
1516         struct drm_device *dev = dev_priv->dev;
1517         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519         uint32_t reg, val, pipeconf_val;
1520
1521         /* PCH only available on ILK+ */
1522         BUG_ON(dev_priv->info->gen < 5);
1523
1524         /* Make sure PCH DPLL is enabled */
1525         assert_shared_dpll_enabled(dev_priv,
1526                                    intel_crtc_to_shared_dpll(intel_crtc));
1527
1528         /* FDI must be feeding us bits for PCH ports */
1529         assert_fdi_tx_enabled(dev_priv, pipe);
1530         assert_fdi_rx_enabled(dev_priv, pipe);
1531
1532         if (HAS_PCH_CPT(dev)) {
1533                 /* Workaround: Set the timing override bit before enabling the
1534                  * pch transcoder. */
1535                 reg = TRANS_CHICKEN2(pipe);
1536                 val = I915_READ(reg);
1537                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1538                 I915_WRITE(reg, val);
1539         }
1540
1541         reg = PCH_TRANSCONF(pipe);
1542         val = I915_READ(reg);
1543         pipeconf_val = I915_READ(PIPECONF(pipe));
1544
1545         if (HAS_PCH_IBX(dev_priv->dev)) {
1546                 /*
1547                  * make the BPC in transcoder be consistent with
1548                  * that in pipeconf reg.
1549                  */
1550                 val &= ~PIPECONF_BPC_MASK;
1551                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1552         }
1553
1554         val &= ~TRANS_INTERLACE_MASK;
1555         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1556                 if (HAS_PCH_IBX(dev_priv->dev) &&
1557                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1558                         val |= TRANS_LEGACY_INTERLACED_ILK;
1559                 else
1560                         val |= TRANS_INTERLACED;
1561         else
1562                 val |= TRANS_PROGRESSIVE;
1563
1564         I915_WRITE(reg, val | TRANS_ENABLE);
1565         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1566                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1567 }
1568
1569 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1570                                       enum transcoder cpu_transcoder)
1571 {
1572         u32 val, pipeconf_val;
1573
1574         /* PCH only available on ILK+ */
1575         BUG_ON(dev_priv->info->gen < 5);
1576
1577         /* FDI must be feeding us bits for PCH ports */
1578         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1579         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1580
1581         /* Workaround: set timing override bit. */
1582         val = I915_READ(_TRANSA_CHICKEN2);
1583         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1584         I915_WRITE(_TRANSA_CHICKEN2, val);
1585
1586         val = TRANS_ENABLE;
1587         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1588
1589         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1590             PIPECONF_INTERLACED_ILK)
1591                 val |= TRANS_INTERLACED;
1592         else
1593                 val |= TRANS_PROGRESSIVE;
1594
1595         I915_WRITE(LPT_TRANSCONF, val);
1596         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1597                 DRM_ERROR("Failed to enable PCH transcoder\n");
1598 }
1599
1600 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1601                                             enum pipe pipe)
1602 {
1603         struct drm_device *dev = dev_priv->dev;
1604         uint32_t reg, val;
1605
1606         /* FDI relies on the transcoder */
1607         assert_fdi_tx_disabled(dev_priv, pipe);
1608         assert_fdi_rx_disabled(dev_priv, pipe);
1609
1610         /* Ports must be off as well */
1611         assert_pch_ports_disabled(dev_priv, pipe);
1612
1613         reg = PCH_TRANSCONF(pipe);
1614         val = I915_READ(reg);
1615         val &= ~TRANS_ENABLE;
1616         I915_WRITE(reg, val);
1617         /* wait for PCH transcoder off, transcoder state */
1618         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1619                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1620
1621         if (!HAS_PCH_IBX(dev)) {
1622                 /* Workaround: Clear the timing override chicken bit again. */
1623                 reg = TRANS_CHICKEN2(pipe);
1624                 val = I915_READ(reg);
1625                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1626                 I915_WRITE(reg, val);
1627         }
1628 }
1629
1630 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1631 {
1632         u32 val;
1633
1634         val = I915_READ(LPT_TRANSCONF);
1635         val &= ~TRANS_ENABLE;
1636         I915_WRITE(LPT_TRANSCONF, val);
1637         /* wait for PCH transcoder off, transcoder state */
1638         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1639                 DRM_ERROR("Failed to disable PCH transcoder\n");
1640
1641         /* Workaround: clear timing override bit. */
1642         val = I915_READ(_TRANSA_CHICKEN2);
1643         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1644         I915_WRITE(_TRANSA_CHICKEN2, val);
1645 }
1646
1647 /**
1648  * intel_enable_pipe - enable a pipe, asserting requirements
1649  * @dev_priv: i915 private structure
1650  * @pipe: pipe to enable
1651  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1652  *
1653  * Enable @pipe, making sure that various hardware specific requirements
1654  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1655  *
1656  * @pipe should be %PIPE_A or %PIPE_B.
1657  *
1658  * Will wait until the pipe is actually running (i.e. first vblank) before
1659  * returning.
1660  */
1661 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1662                               bool pch_port)
1663 {
1664         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665                                                                       pipe);
1666         enum pipe pch_transcoder;
1667         int reg;
1668         u32 val;
1669
1670         assert_planes_disabled(dev_priv, pipe);
1671         assert_sprites_disabled(dev_priv, pipe);
1672
1673         if (HAS_PCH_LPT(dev_priv->dev))
1674                 pch_transcoder = TRANSCODER_A;
1675         else
1676                 pch_transcoder = pipe;
1677
1678         /*
1679          * A pipe without a PLL won't actually be able to drive bits from
1680          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1681          * need the check.
1682          */
1683         if (!HAS_PCH_SPLIT(dev_priv->dev))
1684                 assert_pll_enabled(dev_priv, pipe);
1685         else {
1686                 if (pch_port) {
1687                         /* if driving the PCH, we need FDI enabled */
1688                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1689                         assert_fdi_tx_pll_enabled(dev_priv,
1690                                                   (enum pipe) cpu_transcoder);
1691                 }
1692                 /* FIXME: assert CPU port conditions for SNB+ */
1693         }
1694
1695         reg = PIPECONF(cpu_transcoder);
1696         val = I915_READ(reg);
1697         if (val & PIPECONF_ENABLE)
1698                 return;
1699
1700         I915_WRITE(reg, val | PIPECONF_ENABLE);
1701         intel_wait_for_vblank(dev_priv->dev, pipe);
1702 }
1703
1704 /**
1705  * intel_disable_pipe - disable a pipe, asserting requirements
1706  * @dev_priv: i915 private structure
1707  * @pipe: pipe to disable
1708  *
1709  * Disable @pipe, making sure that various hardware specific requirements
1710  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1711  *
1712  * @pipe should be %PIPE_A or %PIPE_B.
1713  *
1714  * Will wait until the pipe has shut down before returning.
1715  */
1716 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1717                                enum pipe pipe)
1718 {
1719         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1720                                                                       pipe);
1721         int reg;
1722         u32 val;
1723
1724         /*
1725          * Make sure planes won't keep trying to pump pixels to us,
1726          * or we might hang the display.
1727          */
1728         assert_planes_disabled(dev_priv, pipe);
1729         assert_sprites_disabled(dev_priv, pipe);
1730
1731         /* Don't disable pipe A or pipe A PLLs if needed */
1732         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1733                 return;
1734
1735         reg = PIPECONF(cpu_transcoder);
1736         val = I915_READ(reg);
1737         if ((val & PIPECONF_ENABLE) == 0)
1738                 return;
1739
1740         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1741         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1742 }
1743
1744 /*
1745  * Plane regs are double buffered, going from enabled->disabled needs a
1746  * trigger in order to latch.  The display address reg provides this.
1747  */
1748 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1749                                       enum plane plane)
1750 {
1751         if (dev_priv->info->gen >= 4)
1752                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1753         else
1754                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1755 }
1756
1757 /**
1758  * intel_enable_plane - enable a display plane on a given pipe
1759  * @dev_priv: i915 private structure
1760  * @plane: plane to enable
1761  * @pipe: pipe being fed
1762  *
1763  * Enable @plane on @pipe, making sure that @pipe is running first.
1764  */
1765 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1766                                enum plane plane, enum pipe pipe)
1767 {
1768         int reg;
1769         u32 val;
1770
1771         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772         assert_pipe_enabled(dev_priv, pipe);
1773
1774         reg = DSPCNTR(plane);
1775         val = I915_READ(reg);
1776         if (val & DISPLAY_PLANE_ENABLE)
1777                 return;
1778
1779         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1780         intel_flush_display_plane(dev_priv, plane);
1781         intel_wait_for_vblank(dev_priv->dev, pipe);
1782 }
1783
1784 /**
1785  * intel_disable_plane - disable a display plane
1786  * @dev_priv: i915 private structure
1787  * @plane: plane to disable
1788  * @pipe: pipe consuming the data
1789  *
1790  * Disable @plane; should be an independent operation.
1791  */
1792 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1793                                 enum plane plane, enum pipe pipe)
1794 {
1795         int reg;
1796         u32 val;
1797
1798         reg = DSPCNTR(plane);
1799         val = I915_READ(reg);
1800         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1801                 return;
1802
1803         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1804         intel_flush_display_plane(dev_priv, plane);
1805         intel_wait_for_vblank(dev_priv->dev, pipe);
1806 }
1807
1808 static bool need_vtd_wa(struct drm_device *dev)
1809 {
1810 #ifdef CONFIG_INTEL_IOMMU
1811         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1812                 return true;
1813 #endif
1814         return false;
1815 }
1816
1817 int
1818 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1819                            struct drm_i915_gem_object *obj,
1820                            struct intel_ring_buffer *pipelined)
1821 {
1822         struct drm_i915_private *dev_priv = dev->dev_private;
1823         u32 alignment;
1824         int ret;
1825
1826         switch (obj->tiling_mode) {
1827         case I915_TILING_NONE:
1828                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1829                         alignment = 128 * 1024;
1830                 else if (INTEL_INFO(dev)->gen >= 4)
1831                         alignment = 4 * 1024;
1832                 else
1833                         alignment = 64 * 1024;
1834                 break;
1835         case I915_TILING_X:
1836                 /* pin() will align the object as required by fence */
1837                 alignment = 0;
1838                 break;
1839         case I915_TILING_Y:
1840                 /* Despite that we check this in framebuffer_init userspace can
1841                  * screw us over and change the tiling after the fact. Only
1842                  * pinned buffers can't change their tiling. */
1843                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1844                 return -EINVAL;
1845         default:
1846                 BUG();
1847         }
1848
1849         /* Note that the w/a also requires 64 PTE of padding following the
1850          * bo. We currently fill all unused PTE with the shadow page and so
1851          * we should always have valid PTE following the scanout preventing
1852          * the VT-d warning.
1853          */
1854         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1855                 alignment = 256 * 1024;
1856
1857         dev_priv->mm.interruptible = false;
1858         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1859         if (ret)
1860                 goto err_interruptible;
1861
1862         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863          * fence, whereas 965+ only requires a fence if using
1864          * framebuffer compression.  For simplicity, we always install
1865          * a fence as the cost is not that onerous.
1866          */
1867         ret = i915_gem_object_get_fence(obj);
1868         if (ret)
1869                 goto err_unpin;
1870
1871         i915_gem_object_pin_fence(obj);
1872
1873         dev_priv->mm.interruptible = true;
1874         return 0;
1875
1876 err_unpin:
1877         i915_gem_object_unpin(obj);
1878 err_interruptible:
1879         dev_priv->mm.interruptible = true;
1880         return ret;
1881 }
1882
1883 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1884 {
1885         i915_gem_object_unpin_fence(obj);
1886         i915_gem_object_unpin(obj);
1887 }
1888
1889 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890  * is assumed to be a power-of-two. */
1891 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1892                                              unsigned int tiling_mode,
1893                                              unsigned int cpp,
1894                                              unsigned int pitch)
1895 {
1896         if (tiling_mode != I915_TILING_NONE) {
1897                 unsigned int tile_rows, tiles;
1898
1899                 tile_rows = *y / 8;
1900                 *y %= 8;
1901
1902                 tiles = *x / (512/cpp);
1903                 *x %= 512/cpp;
1904
1905                 return tile_rows * pitch * 8 + tiles * 4096;
1906         } else {
1907                 unsigned int offset;
1908
1909                 offset = *y * pitch + *x * cpp;
1910                 *y = 0;
1911                 *x = (offset & 4095) / cpp;
1912                 return offset & -4096;
1913         }
1914 }
1915
1916 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1917                              int x, int y)
1918 {
1919         struct drm_device *dev = crtc->dev;
1920         struct drm_i915_private *dev_priv = dev->dev_private;
1921         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922         struct intel_framebuffer *intel_fb;
1923         struct drm_i915_gem_object *obj;
1924         int plane = intel_crtc->plane;
1925         unsigned long linear_offset;
1926         u32 dspcntr;
1927         u32 reg;
1928
1929         switch (plane) {
1930         case 0:
1931         case 1:
1932                 break;
1933         default:
1934                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1935                 return -EINVAL;
1936         }
1937
1938         intel_fb = to_intel_framebuffer(fb);
1939         obj = intel_fb->obj;
1940
1941         reg = DSPCNTR(plane);
1942         dspcntr = I915_READ(reg);
1943         /* Mask out pixel format bits in case we change it */
1944         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1945         switch (fb->pixel_format) {
1946         case DRM_FORMAT_C8:
1947                 dspcntr |= DISPPLANE_8BPP;
1948                 break;
1949         case DRM_FORMAT_XRGB1555:
1950         case DRM_FORMAT_ARGB1555:
1951                 dspcntr |= DISPPLANE_BGRX555;
1952                 break;
1953         case DRM_FORMAT_RGB565:
1954                 dspcntr |= DISPPLANE_BGRX565;
1955                 break;
1956         case DRM_FORMAT_XRGB8888:
1957         case DRM_FORMAT_ARGB8888:
1958                 dspcntr |= DISPPLANE_BGRX888;
1959                 break;
1960         case DRM_FORMAT_XBGR8888:
1961         case DRM_FORMAT_ABGR8888:
1962                 dspcntr |= DISPPLANE_RGBX888;
1963                 break;
1964         case DRM_FORMAT_XRGB2101010:
1965         case DRM_FORMAT_ARGB2101010:
1966                 dspcntr |= DISPPLANE_BGRX101010;
1967                 break;
1968         case DRM_FORMAT_XBGR2101010:
1969         case DRM_FORMAT_ABGR2101010:
1970                 dspcntr |= DISPPLANE_RGBX101010;
1971                 break;
1972         default:
1973                 BUG();
1974         }
1975
1976         if (INTEL_INFO(dev)->gen >= 4) {
1977                 if (obj->tiling_mode != I915_TILING_NONE)
1978                         dspcntr |= DISPPLANE_TILED;
1979                 else
1980                         dspcntr &= ~DISPPLANE_TILED;
1981         }
1982
1983         if (IS_G4X(dev))
1984                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1985
1986         I915_WRITE(reg, dspcntr);
1987
1988         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1989
1990         if (INTEL_INFO(dev)->gen >= 4) {
1991                 intel_crtc->dspaddr_offset =
1992                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1993                                                        fb->bits_per_pixel / 8,
1994                                                        fb->pitches[0]);
1995                 linear_offset -= intel_crtc->dspaddr_offset;
1996         } else {
1997                 intel_crtc->dspaddr_offset = linear_offset;
1998         }
1999
2000         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2002                       fb->pitches[0]);
2003         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2004         if (INTEL_INFO(dev)->gen >= 4) {
2005                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2006                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2007                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2008                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2009         } else
2010                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2011         POSTING_READ(reg);
2012
2013         return 0;
2014 }
2015
2016 static int ironlake_update_plane(struct drm_crtc *crtc,
2017                                  struct drm_framebuffer *fb, int x, int y)
2018 {
2019         struct drm_device *dev = crtc->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022         struct intel_framebuffer *intel_fb;
2023         struct drm_i915_gem_object *obj;
2024         int plane = intel_crtc->plane;
2025         unsigned long linear_offset;
2026         u32 dspcntr;
2027         u32 reg;
2028
2029         switch (plane) {
2030         case 0:
2031         case 1:
2032         case 2:
2033                 break;
2034         default:
2035                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2036                 return -EINVAL;
2037         }
2038
2039         intel_fb = to_intel_framebuffer(fb);
2040         obj = intel_fb->obj;
2041
2042         reg = DSPCNTR(plane);
2043         dspcntr = I915_READ(reg);
2044         /* Mask out pixel format bits in case we change it */
2045         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2046         switch (fb->pixel_format) {
2047         case DRM_FORMAT_C8:
2048                 dspcntr |= DISPPLANE_8BPP;
2049                 break;
2050         case DRM_FORMAT_RGB565:
2051                 dspcntr |= DISPPLANE_BGRX565;
2052                 break;
2053         case DRM_FORMAT_XRGB8888:
2054         case DRM_FORMAT_ARGB8888:
2055                 dspcntr |= DISPPLANE_BGRX888;
2056                 break;
2057         case DRM_FORMAT_XBGR8888:
2058         case DRM_FORMAT_ABGR8888:
2059                 dspcntr |= DISPPLANE_RGBX888;
2060                 break;
2061         case DRM_FORMAT_XRGB2101010:
2062         case DRM_FORMAT_ARGB2101010:
2063                 dspcntr |= DISPPLANE_BGRX101010;
2064                 break;
2065         case DRM_FORMAT_XBGR2101010:
2066         case DRM_FORMAT_ABGR2101010:
2067                 dspcntr |= DISPPLANE_RGBX101010;
2068                 break;
2069         default:
2070                 BUG();
2071         }
2072
2073         if (obj->tiling_mode != I915_TILING_NONE)
2074                 dspcntr |= DISPPLANE_TILED;
2075         else
2076                 dspcntr &= ~DISPPLANE_TILED;
2077
2078         /* must disable */
2079         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081         I915_WRITE(reg, dspcntr);
2082
2083         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2084         intel_crtc->dspaddr_offset =
2085                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2086                                                fb->bits_per_pixel / 8,
2087                                                fb->pitches[0]);
2088         linear_offset -= intel_crtc->dspaddr_offset;
2089
2090         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2092                       fb->pitches[0]);
2093         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2094         I915_MODIFY_DISPBASE(DSPSURF(plane),
2095                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2096         if (IS_HASWELL(dev)) {
2097                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2098         } else {
2099                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2100                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2101         }
2102         POSTING_READ(reg);
2103
2104         return 0;
2105 }
2106
2107 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2108 static int
2109 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110                            int x, int y, enum mode_set_atomic state)
2111 {
2112         struct drm_device *dev = crtc->dev;
2113         struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115         if (dev_priv->display.disable_fbc)
2116                 dev_priv->display.disable_fbc(dev);
2117         intel_increase_pllclock(crtc);
2118
2119         return dev_priv->display.update_plane(crtc, fb, x, y);
2120 }
2121
2122 void intel_display_handle_reset(struct drm_device *dev)
2123 {
2124         struct drm_i915_private *dev_priv = dev->dev_private;
2125         struct drm_crtc *crtc;
2126
2127         /*
2128          * Flips in the rings have been nuked by the reset,
2129          * so complete all pending flips so that user space
2130          * will get its events and not get stuck.
2131          *
2132          * Also update the base address of all primary
2133          * planes to the the last fb to make sure we're
2134          * showing the correct fb after a reset.
2135          *
2136          * Need to make two loops over the crtcs so that we
2137          * don't try to grab a crtc mutex before the
2138          * pending_flip_queue really got woken up.
2139          */
2140
2141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2142                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143                 enum plane plane = intel_crtc->plane;
2144
2145                 intel_prepare_page_flip(dev, plane);
2146                 intel_finish_page_flip_plane(dev, plane);
2147         }
2148
2149         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2150                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151
2152                 mutex_lock(&crtc->mutex);
2153                 if (intel_crtc->active)
2154                         dev_priv->display.update_plane(crtc, crtc->fb,
2155                                                        crtc->x, crtc->y);
2156                 mutex_unlock(&crtc->mutex);
2157         }
2158 }
2159
2160 static int
2161 intel_finish_fb(struct drm_framebuffer *old_fb)
2162 {
2163         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2164         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2165         bool was_interruptible = dev_priv->mm.interruptible;
2166         int ret;
2167
2168         /* Big Hammer, we also need to ensure that any pending
2169          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170          * current scanout is retired before unpinning the old
2171          * framebuffer.
2172          *
2173          * This should only fail upon a hung GPU, in which case we
2174          * can safely continue.
2175          */
2176         dev_priv->mm.interruptible = false;
2177         ret = i915_gem_object_finish_gpu(obj);
2178         dev_priv->mm.interruptible = was_interruptible;
2179
2180         return ret;
2181 }
2182
2183 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2184 {
2185         struct drm_device *dev = crtc->dev;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188
2189         if (!dev->primary->master)
2190                 return;
2191
2192         master_priv = dev->primary->master->driver_priv;
2193         if (!master_priv->sarea_priv)
2194                 return;
2195
2196         switch (intel_crtc->pipe) {
2197         case 0:
2198                 master_priv->sarea_priv->pipeA_x = x;
2199                 master_priv->sarea_priv->pipeA_y = y;
2200                 break;
2201         case 1:
2202                 master_priv->sarea_priv->pipeB_x = x;
2203                 master_priv->sarea_priv->pipeB_y = y;
2204                 break;
2205         default:
2206                 break;
2207         }
2208 }
2209
2210 static int
2211 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2212                     struct drm_framebuffer *fb)
2213 {
2214         struct drm_device *dev = crtc->dev;
2215         struct drm_i915_private *dev_priv = dev->dev_private;
2216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217         struct drm_framebuffer *old_fb;
2218         int ret;
2219
2220         /* no fb bound */
2221         if (!fb) {
2222                 DRM_ERROR("No FB bound\n");
2223                 return 0;
2224         }
2225
2226         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2227                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228                           plane_name(intel_crtc->plane),
2229                           INTEL_INFO(dev)->num_pipes);
2230                 return -EINVAL;
2231         }
2232
2233         mutex_lock(&dev->struct_mutex);
2234         ret = intel_pin_and_fence_fb_obj(dev,
2235                                          to_intel_framebuffer(fb)->obj,
2236                                          NULL);
2237         if (ret != 0) {
2238                 mutex_unlock(&dev->struct_mutex);
2239                 DRM_ERROR("pin & fence failed\n");
2240                 return ret;
2241         }
2242
2243         /* Update pipe size and adjust fitter if needed */
2244         if (i915_fastboot) {
2245                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2246                            ((crtc->mode.hdisplay - 1) << 16) |
2247                            (crtc->mode.vdisplay - 1));
2248                 if (!intel_crtc->config.pch_pfit.size &&
2249                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2250                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2251                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2253                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2254                 }
2255         }
2256
2257         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2258         if (ret) {
2259                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2260                 mutex_unlock(&dev->struct_mutex);
2261                 DRM_ERROR("failed to update base address\n");
2262                 return ret;
2263         }
2264
2265         old_fb = crtc->fb;
2266         crtc->fb = fb;
2267         crtc->x = x;
2268         crtc->y = y;
2269
2270         if (old_fb) {
2271                 if (intel_crtc->active && old_fb != fb)
2272                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2273                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2274         }
2275
2276         intel_update_fbc(dev);
2277         intel_edp_psr_update(dev);
2278         mutex_unlock(&dev->struct_mutex);
2279
2280         intel_crtc_update_sarea_pos(crtc, x, y);
2281
2282         return 0;
2283 }
2284
2285 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286 {
2287         struct drm_device *dev = crtc->dev;
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290         int pipe = intel_crtc->pipe;
2291         u32 reg, temp;
2292
2293         /* enable normal train */
2294         reg = FDI_TX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (IS_IVYBRIDGE(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2302         }
2303         I915_WRITE(reg, temp);
2304
2305         reg = FDI_RX_CTL(pipe);
2306         temp = I915_READ(reg);
2307         if (HAS_PCH_CPT(dev)) {
2308                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310         } else {
2311                 temp &= ~FDI_LINK_TRAIN_NONE;
2312                 temp |= FDI_LINK_TRAIN_NONE;
2313         }
2314         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316         /* wait one idle pattern time */
2317         POSTING_READ(reg);
2318         udelay(1000);
2319
2320         /* IVB wants error correction enabled */
2321         if (IS_IVYBRIDGE(dev))
2322                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323                            FDI_FE_ERRC_ENABLE);
2324 }
2325
2326 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2327 {
2328         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2329 }
2330
2331 static void ivb_modeset_global_resources(struct drm_device *dev)
2332 {
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *pipe_B_crtc =
2335                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2336         struct intel_crtc *pipe_C_crtc =
2337                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2338         uint32_t temp;
2339
2340         /*
2341          * When everything is off disable fdi C so that we could enable fdi B
2342          * with all lanes. Note that we don't care about enabled pipes without
2343          * an enabled pch encoder.
2344          */
2345         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2346             !pipe_has_enabled_pch(pipe_C_crtc)) {
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2348                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2349
2350                 temp = I915_READ(SOUTH_CHICKEN1);
2351                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2352                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2353                 I915_WRITE(SOUTH_CHICKEN1, temp);
2354         }
2355 }
2356
2357 /* The FDI link training functions for ILK/Ibexpeak. */
2358 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2359 {
2360         struct drm_device *dev = crtc->dev;
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2363         int pipe = intel_crtc->pipe;
2364         int plane = intel_crtc->plane;
2365         u32 reg, temp, tries;
2366
2367         /* FDI needs bits from pipe & plane first */
2368         assert_pipe_enabled(dev_priv, pipe);
2369         assert_plane_enabled(dev_priv, plane);
2370
2371         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2372            for train result */
2373         reg = FDI_RX_IMR(pipe);
2374         temp = I915_READ(reg);
2375         temp &= ~FDI_RX_SYMBOL_LOCK;
2376         temp &= ~FDI_RX_BIT_LOCK;
2377         I915_WRITE(reg, temp);
2378         I915_READ(reg);
2379         udelay(150);
2380
2381         /* enable CPU FDI TX and PCH FDI RX */
2382         reg = FDI_TX_CTL(pipe);
2383         temp = I915_READ(reg);
2384         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2385         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2386         temp &= ~FDI_LINK_TRAIN_NONE;
2387         temp |= FDI_LINK_TRAIN_PATTERN_1;
2388         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2389
2390         reg = FDI_RX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         temp &= ~FDI_LINK_TRAIN_NONE;
2393         temp |= FDI_LINK_TRAIN_PATTERN_1;
2394         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2395
2396         POSTING_READ(reg);
2397         udelay(150);
2398
2399         /* Ironlake workaround, enable clock pointer after FDI enable*/
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2401         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2402                    FDI_RX_PHASE_SYNC_POINTER_EN);
2403
2404         reg = FDI_RX_IIR(pipe);
2405         for (tries = 0; tries < 5; tries++) {
2406                 temp = I915_READ(reg);
2407                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409                 if ((temp & FDI_RX_BIT_LOCK)) {
2410                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2411                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2412                         break;
2413                 }
2414         }
2415         if (tries == 5)
2416                 DRM_ERROR("FDI train 1 fail!\n");
2417
2418         /* Train 2 */
2419         reg = FDI_TX_CTL(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_LINK_TRAIN_NONE;
2422         temp |= FDI_LINK_TRAIN_PATTERN_2;
2423         I915_WRITE(reg, temp);
2424
2425         reg = FDI_RX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_LINK_TRAIN_NONE;
2428         temp |= FDI_LINK_TRAIN_PATTERN_2;
2429         I915_WRITE(reg, temp);
2430
2431         POSTING_READ(reg);
2432         udelay(150);
2433
2434         reg = FDI_RX_IIR(pipe);
2435         for (tries = 0; tries < 5; tries++) {
2436                 temp = I915_READ(reg);
2437                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439                 if (temp & FDI_RX_SYMBOL_LOCK) {
2440                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2441                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2442                         break;
2443                 }
2444         }
2445         if (tries == 5)
2446                 DRM_ERROR("FDI train 2 fail!\n");
2447
2448         DRM_DEBUG_KMS("FDI train done\n");
2449
2450 }
2451
2452 static const int snb_b_fdi_train_param[] = {
2453         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2454         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2455         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2456         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2457 };
2458
2459 /* The FDI link training functions for SNB/Cougarpoint. */
2460 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461 {
2462         struct drm_device *dev = crtc->dev;
2463         struct drm_i915_private *dev_priv = dev->dev_private;
2464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465         int pipe = intel_crtc->pipe;
2466         u32 reg, temp, i, retry;
2467
2468         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469            for train result */
2470         reg = FDI_RX_IMR(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_RX_SYMBOL_LOCK;
2473         temp &= ~FDI_RX_BIT_LOCK;
2474         I915_WRITE(reg, temp);
2475
2476         POSTING_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487         /* SNB-B */
2488         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2490
2491         I915_WRITE(FDI_RX_MISC(pipe),
2492                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2493
2494         reg = FDI_RX_CTL(pipe);
2495         temp = I915_READ(reg);
2496         if (HAS_PCH_CPT(dev)) {
2497                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2499         } else {
2500                 temp &= ~FDI_LINK_TRAIN_NONE;
2501                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502         }
2503         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2504
2505         POSTING_READ(reg);
2506         udelay(150);
2507
2508         for (i = 0; i < 4; i++) {
2509                 reg = FDI_TX_CTL(pipe);
2510                 temp = I915_READ(reg);
2511                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512                 temp |= snb_b_fdi_train_param[i];
2513                 I915_WRITE(reg, temp);
2514
2515                 POSTING_READ(reg);
2516                 udelay(500);
2517
2518                 for (retry = 0; retry < 5; retry++) {
2519                         reg = FDI_RX_IIR(pipe);
2520                         temp = I915_READ(reg);
2521                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522                         if (temp & FDI_RX_BIT_LOCK) {
2523                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525                                 break;
2526                         }
2527                         udelay(50);
2528                 }
2529                 if (retry < 5)
2530                         break;
2531         }
2532         if (i == 4)
2533                 DRM_ERROR("FDI train 1 fail!\n");
2534
2535         /* Train 2 */
2536         reg = FDI_TX_CTL(pipe);
2537         temp = I915_READ(reg);
2538         temp &= ~FDI_LINK_TRAIN_NONE;
2539         temp |= FDI_LINK_TRAIN_PATTERN_2;
2540         if (IS_GEN6(dev)) {
2541                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542                 /* SNB-B */
2543                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544         }
2545         I915_WRITE(reg, temp);
2546
2547         reg = FDI_RX_CTL(pipe);
2548         temp = I915_READ(reg);
2549         if (HAS_PCH_CPT(dev)) {
2550                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552         } else {
2553                 temp &= ~FDI_LINK_TRAIN_NONE;
2554                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555         }
2556         I915_WRITE(reg, temp);
2557
2558         POSTING_READ(reg);
2559         udelay(150);
2560
2561         for (i = 0; i < 4; i++) {
2562                 reg = FDI_TX_CTL(pipe);
2563                 temp = I915_READ(reg);
2564                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565                 temp |= snb_b_fdi_train_param[i];
2566                 I915_WRITE(reg, temp);
2567
2568                 POSTING_READ(reg);
2569                 udelay(500);
2570
2571                 for (retry = 0; retry < 5; retry++) {
2572                         reg = FDI_RX_IIR(pipe);
2573                         temp = I915_READ(reg);
2574                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575                         if (temp & FDI_RX_SYMBOL_LOCK) {
2576                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578                                 break;
2579                         }
2580                         udelay(50);
2581                 }
2582                 if (retry < 5)
2583                         break;
2584         }
2585         if (i == 4)
2586                 DRM_ERROR("FDI train 2 fail!\n");
2587
2588         DRM_DEBUG_KMS("FDI train done.\n");
2589 }
2590
2591 /* Manual link training for Ivy Bridge A0 parts */
2592 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         int pipe = intel_crtc->pipe;
2598         u32 reg, temp, i;
2599
2600         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601            for train result */
2602         reg = FDI_RX_IMR(pipe);
2603         temp = I915_READ(reg);
2604         temp &= ~FDI_RX_SYMBOL_LOCK;
2605         temp &= ~FDI_RX_BIT_LOCK;
2606         I915_WRITE(reg, temp);
2607
2608         POSTING_READ(reg);
2609         udelay(150);
2610
2611         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2612                       I915_READ(FDI_RX_IIR(pipe)));
2613
2614         /* enable CPU FDI TX and PCH FDI RX */
2615         reg = FDI_TX_CTL(pipe);
2616         temp = I915_READ(reg);
2617         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2618         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2619         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2620         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2621         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2623         temp |= FDI_COMPOSITE_SYNC;
2624         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2625
2626         I915_WRITE(FDI_RX_MISC(pipe),
2627                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2628
2629         reg = FDI_RX_CTL(pipe);
2630         temp = I915_READ(reg);
2631         temp &= ~FDI_LINK_TRAIN_AUTO;
2632         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2634         temp |= FDI_COMPOSITE_SYNC;
2635         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2636
2637         POSTING_READ(reg);
2638         udelay(150);
2639
2640         for (i = 0; i < 4; i++) {
2641                 reg = FDI_TX_CTL(pipe);
2642                 temp = I915_READ(reg);
2643                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644                 temp |= snb_b_fdi_train_param[i];
2645                 I915_WRITE(reg, temp);
2646
2647                 POSTING_READ(reg);
2648                 udelay(500);
2649
2650                 reg = FDI_RX_IIR(pipe);
2651                 temp = I915_READ(reg);
2652                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654                 if (temp & FDI_RX_BIT_LOCK ||
2655                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2656                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2657                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2658                         break;
2659                 }
2660         }
2661         if (i == 4)
2662                 DRM_ERROR("FDI train 1 fail!\n");
2663
2664         /* Train 2 */
2665         reg = FDI_TX_CTL(pipe);
2666         temp = I915_READ(reg);
2667         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2668         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2669         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2671         I915_WRITE(reg, temp);
2672
2673         reg = FDI_RX_CTL(pipe);
2674         temp = I915_READ(reg);
2675         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2676         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2677         I915_WRITE(reg, temp);
2678
2679         POSTING_READ(reg);
2680         udelay(150);
2681
2682         for (i = 0; i < 4; i++) {
2683                 reg = FDI_TX_CTL(pipe);
2684                 temp = I915_READ(reg);
2685                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686                 temp |= snb_b_fdi_train_param[i];
2687                 I915_WRITE(reg, temp);
2688
2689                 POSTING_READ(reg);
2690                 udelay(500);
2691
2692                 reg = FDI_RX_IIR(pipe);
2693                 temp = I915_READ(reg);
2694                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695
2696                 if (temp & FDI_RX_SYMBOL_LOCK) {
2697                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2698                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2699                         break;
2700                 }
2701         }
2702         if (i == 4)
2703                 DRM_ERROR("FDI train 2 fail!\n");
2704
2705         DRM_DEBUG_KMS("FDI train done.\n");
2706 }
2707
2708 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2709 {
2710         struct drm_device *dev = intel_crtc->base.dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         int pipe = intel_crtc->pipe;
2713         u32 reg, temp;
2714
2715
2716         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2717         reg = FDI_RX_CTL(pipe);
2718         temp = I915_READ(reg);
2719         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2720         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2721         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2722         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2723
2724         POSTING_READ(reg);
2725         udelay(200);
2726
2727         /* Switch from Rawclk to PCDclk */
2728         temp = I915_READ(reg);
2729         I915_WRITE(reg, temp | FDI_PCDCLK);
2730
2731         POSTING_READ(reg);
2732         udelay(200);
2733
2734         /* Enable CPU FDI TX PLL, always on for Ironlake */
2735         reg = FDI_TX_CTL(pipe);
2736         temp = I915_READ(reg);
2737         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2738                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2739
2740                 POSTING_READ(reg);
2741                 udelay(100);
2742         }
2743 }
2744
2745 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2746 {
2747         struct drm_device *dev = intel_crtc->base.dev;
2748         struct drm_i915_private *dev_priv = dev->dev_private;
2749         int pipe = intel_crtc->pipe;
2750         u32 reg, temp;
2751
2752         /* Switch from PCDclk to Rawclk */
2753         reg = FDI_RX_CTL(pipe);
2754         temp = I915_READ(reg);
2755         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2756
2757         /* Disable CPU FDI TX PLL */
2758         reg = FDI_TX_CTL(pipe);
2759         temp = I915_READ(reg);
2760         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2761
2762         POSTING_READ(reg);
2763         udelay(100);
2764
2765         reg = FDI_RX_CTL(pipe);
2766         temp = I915_READ(reg);
2767         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2768
2769         /* Wait for the clocks to turn off. */
2770         POSTING_READ(reg);
2771         udelay(100);
2772 }
2773
2774 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2775 {
2776         struct drm_device *dev = crtc->dev;
2777         struct drm_i915_private *dev_priv = dev->dev_private;
2778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2779         int pipe = intel_crtc->pipe;
2780         u32 reg, temp;
2781
2782         /* disable CPU FDI tx and PCH FDI rx */
2783         reg = FDI_TX_CTL(pipe);
2784         temp = I915_READ(reg);
2785         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2786         POSTING_READ(reg);
2787
2788         reg = FDI_RX_CTL(pipe);
2789         temp = I915_READ(reg);
2790         temp &= ~(0x7 << 16);
2791         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2792         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2793
2794         POSTING_READ(reg);
2795         udelay(100);
2796
2797         /* Ironlake workaround, disable clock pointer after downing FDI */
2798         if (HAS_PCH_IBX(dev)) {
2799                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2800         }
2801
2802         /* still set train pattern 1 */
2803         reg = FDI_TX_CTL(pipe);
2804         temp = I915_READ(reg);
2805         temp &= ~FDI_LINK_TRAIN_NONE;
2806         temp |= FDI_LINK_TRAIN_PATTERN_1;
2807         I915_WRITE(reg, temp);
2808
2809         reg = FDI_RX_CTL(pipe);
2810         temp = I915_READ(reg);
2811         if (HAS_PCH_CPT(dev)) {
2812                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2814         } else {
2815                 temp &= ~FDI_LINK_TRAIN_NONE;
2816                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2817         }
2818         /* BPC in FDI rx is consistent with that in PIPECONF */
2819         temp &= ~(0x07 << 16);
2820         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2821         I915_WRITE(reg, temp);
2822
2823         POSTING_READ(reg);
2824         udelay(100);
2825 }
2826
2827 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2828 {
2829         struct drm_device *dev = crtc->dev;
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2832         unsigned long flags;
2833         bool pending;
2834
2835         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2836             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2837                 return false;
2838
2839         spin_lock_irqsave(&dev->event_lock, flags);
2840         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2841         spin_unlock_irqrestore(&dev->event_lock, flags);
2842
2843         return pending;
2844 }
2845
2846 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2847 {
2848         struct drm_device *dev = crtc->dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850
2851         if (crtc->fb == NULL)
2852                 return;
2853
2854         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2855
2856         wait_event(dev_priv->pending_flip_queue,
2857                    !intel_crtc_has_pending_flip(crtc));
2858
2859         mutex_lock(&dev->struct_mutex);
2860         intel_finish_fb(crtc->fb);
2861         mutex_unlock(&dev->struct_mutex);
2862 }
2863
2864 /* Program iCLKIP clock to the desired frequency */
2865 static void lpt_program_iclkip(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2870         u32 temp;
2871
2872         mutex_lock(&dev_priv->dpio_lock);
2873
2874         /* It is necessary to ungate the pixclk gate prior to programming
2875          * the divisors, and gate it back when it is done.
2876          */
2877         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2878
2879         /* Disable SSCCTL */
2880         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2881                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2882                                 SBI_SSCCTL_DISABLE,
2883                         SBI_ICLK);
2884
2885         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2886         if (crtc->mode.clock == 20000) {
2887                 auxdiv = 1;
2888                 divsel = 0x41;
2889                 phaseinc = 0x20;
2890         } else {
2891                 /* The iCLK virtual clock root frequency is in MHz,
2892                  * but the crtc->mode.clock in in KHz. To get the divisors,
2893                  * it is necessary to divide one by another, so we
2894                  * convert the virtual clock precision to KHz here for higher
2895                  * precision.
2896                  */
2897                 u32 iclk_virtual_root_freq = 172800 * 1000;
2898                 u32 iclk_pi_range = 64;
2899                 u32 desired_divisor, msb_divisor_value, pi_value;
2900
2901                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2902                 msb_divisor_value = desired_divisor / iclk_pi_range;
2903                 pi_value = desired_divisor % iclk_pi_range;
2904
2905                 auxdiv = 0;
2906                 divsel = msb_divisor_value - 2;
2907                 phaseinc = pi_value;
2908         }
2909
2910         /* This should not happen with any sane values */
2911         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2912                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2913         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2914                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2915
2916         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2917                         crtc->mode.clock,
2918                         auxdiv,
2919                         divsel,
2920                         phasedir,
2921                         phaseinc);
2922
2923         /* Program SSCDIVINTPHASE6 */
2924         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2925         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2926         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2927         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2928         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2929         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2930         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2931         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2932
2933         /* Program SSCAUXDIV */
2934         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2935         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2936         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2937         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2938
2939         /* Enable modulator and associated divider */
2940         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2941         temp &= ~SBI_SSCCTL_DISABLE;
2942         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2943
2944         /* Wait for initialization time */
2945         udelay(24);
2946
2947         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2948
2949         mutex_unlock(&dev_priv->dpio_lock);
2950 }
2951
2952 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2953                                                 enum pipe pch_transcoder)
2954 {
2955         struct drm_device *dev = crtc->base.dev;
2956         struct drm_i915_private *dev_priv = dev->dev_private;
2957         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2958
2959         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2960                    I915_READ(HTOTAL(cpu_transcoder)));
2961         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2962                    I915_READ(HBLANK(cpu_transcoder)));
2963         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2964                    I915_READ(HSYNC(cpu_transcoder)));
2965
2966         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2967                    I915_READ(VTOTAL(cpu_transcoder)));
2968         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2969                    I915_READ(VBLANK(cpu_transcoder)));
2970         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2971                    I915_READ(VSYNC(cpu_transcoder)));
2972         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2973                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2974 }
2975
2976 /*
2977  * Enable PCH resources required for PCH ports:
2978  *   - PCH PLLs
2979  *   - FDI training & RX/TX
2980  *   - update transcoder timings
2981  *   - DP transcoding bits
2982  *   - transcoder
2983  */
2984 static void ironlake_pch_enable(struct drm_crtc *crtc)
2985 {
2986         struct drm_device *dev = crtc->dev;
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2989         int pipe = intel_crtc->pipe;
2990         u32 reg, temp;
2991
2992         assert_pch_transcoder_disabled(dev_priv, pipe);
2993
2994         /* Write the TU size bits before fdi link training, so that error
2995          * detection works. */
2996         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2997                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2998
2999         /* For PCH output, training FDI link */
3000         dev_priv->display.fdi_link_train(crtc);
3001
3002         /* We need to program the right clock selection before writing the pixel
3003          * mutliplier into the DPLL. */
3004         if (HAS_PCH_CPT(dev)) {
3005                 u32 sel;
3006
3007                 temp = I915_READ(PCH_DPLL_SEL);
3008                 temp |= TRANS_DPLL_ENABLE(pipe);
3009                 sel = TRANS_DPLLB_SEL(pipe);
3010                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3011                         temp |= sel;
3012                 else
3013                         temp &= ~sel;
3014                 I915_WRITE(PCH_DPLL_SEL, temp);
3015         }
3016
3017         /* XXX: pch pll's can be enabled any time before we enable the PCH
3018          * transcoder, and we actually should do this to not upset any PCH
3019          * transcoder that already use the clock when we share it.
3020          *
3021          * Note that enable_shared_dpll tries to do the right thing, but
3022          * get_shared_dpll unconditionally resets the pll - we need that to have
3023          * the right LVDS enable sequence. */
3024         ironlake_enable_shared_dpll(intel_crtc);
3025
3026         /* set transcoder timing, panel must allow it */
3027         assert_panel_unlocked(dev_priv, pipe);
3028         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3029
3030         intel_fdi_normal_train(crtc);
3031
3032         /* For PCH DP, enable TRANS_DP_CTL */
3033         if (HAS_PCH_CPT(dev) &&
3034             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3035              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3036                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3037                 reg = TRANS_DP_CTL(pipe);
3038                 temp = I915_READ(reg);
3039                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3040                           TRANS_DP_SYNC_MASK |
3041                           TRANS_DP_BPC_MASK);
3042                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3043                          TRANS_DP_ENH_FRAMING);
3044                 temp |= bpc << 9; /* same format but at 11:9 */
3045
3046                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3047                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3048                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3049                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3050
3051                 switch (intel_trans_dp_port_sel(crtc)) {
3052                 case PCH_DP_B:
3053                         temp |= TRANS_DP_PORT_SEL_B;
3054                         break;
3055                 case PCH_DP_C:
3056                         temp |= TRANS_DP_PORT_SEL_C;
3057                         break;
3058                 case PCH_DP_D:
3059                         temp |= TRANS_DP_PORT_SEL_D;
3060                         break;
3061                 default:
3062                         BUG();
3063                 }
3064
3065                 I915_WRITE(reg, temp);
3066         }
3067
3068         ironlake_enable_pch_transcoder(dev_priv, pipe);
3069 }
3070
3071 static void lpt_pch_enable(struct drm_crtc *crtc)
3072 {
3073         struct drm_device *dev = crtc->dev;
3074         struct drm_i915_private *dev_priv = dev->dev_private;
3075         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3077
3078         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3079
3080         lpt_program_iclkip(crtc);
3081
3082         /* Set transcoder timing. */
3083         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3084
3085         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3086 }
3087
3088 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3089 {
3090         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3091
3092         if (pll == NULL)
3093                 return;
3094
3095         if (pll->refcount == 0) {
3096                 WARN(1, "bad %s refcount\n", pll->name);
3097                 return;
3098         }
3099
3100         if (--pll->refcount == 0) {
3101                 WARN_ON(pll->on);
3102                 WARN_ON(pll->active);
3103         }
3104
3105         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3106 }
3107
3108 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3109 {
3110         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3111         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3112         enum intel_dpll_id i;
3113
3114         if (pll) {
3115                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3116                               crtc->base.base.id, pll->name);
3117                 intel_put_shared_dpll(crtc);
3118         }
3119
3120         if (HAS_PCH_IBX(dev_priv->dev)) {
3121                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3122                 i = (enum intel_dpll_id) crtc->pipe;
3123                 pll = &dev_priv->shared_dplls[i];
3124
3125                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3126                               crtc->base.base.id, pll->name);
3127
3128                 goto found;
3129         }
3130
3131         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3132                 pll = &dev_priv->shared_dplls[i];
3133
3134                 /* Only want to check enabled timings first */
3135                 if (pll->refcount == 0)
3136                         continue;
3137
3138                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3139                            sizeof(pll->hw_state)) == 0) {
3140                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3141                                       crtc->base.base.id,
3142                                       pll->name, pll->refcount, pll->active);
3143
3144                         goto found;
3145                 }
3146         }
3147
3148         /* Ok no matching timings, maybe there's a free one? */
3149         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3150                 pll = &dev_priv->shared_dplls[i];
3151                 if (pll->refcount == 0) {
3152                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3153                                       crtc->base.base.id, pll->name);
3154                         goto found;
3155                 }
3156         }
3157
3158         return NULL;
3159
3160 found:
3161         crtc->config.shared_dpll = i;
3162         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3163                          pipe_name(crtc->pipe));
3164
3165         if (pll->active == 0) {
3166                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3167                        sizeof(pll->hw_state));
3168
3169                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3170                 WARN_ON(pll->on);
3171                 assert_shared_dpll_disabled(dev_priv, pll);
3172
3173                 pll->mode_set(dev_priv, pll);
3174         }
3175         pll->refcount++;
3176
3177         return pll;
3178 }
3179
3180 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3181 {
3182         struct drm_i915_private *dev_priv = dev->dev_private;
3183         int dslreg = PIPEDSL(pipe);
3184         u32 temp;
3185
3186         temp = I915_READ(dslreg);
3187         udelay(500);
3188         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3189                 if (wait_for(I915_READ(dslreg) != temp, 5))
3190                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3191         }
3192 }
3193
3194 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3195 {
3196         struct drm_device *dev = crtc->base.dev;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         int pipe = crtc->pipe;
3199
3200         if (crtc->config.pch_pfit.size) {
3201                 /* Force use of hard-coded filter coefficients
3202                  * as some pre-programmed values are broken,
3203                  * e.g. x201.
3204                  */
3205                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3206                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3207                                                  PF_PIPE_SEL_IVB(pipe));
3208                 else
3209                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3210                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3211                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3212         }
3213 }
3214
3215 static void intel_enable_planes(struct drm_crtc *crtc)
3216 {
3217         struct drm_device *dev = crtc->dev;
3218         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3219         struct intel_plane *intel_plane;
3220
3221         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3222                 if (intel_plane->pipe == pipe)
3223                         intel_plane_restore(&intel_plane->base);
3224 }
3225
3226 static void intel_disable_planes(struct drm_crtc *crtc)
3227 {
3228         struct drm_device *dev = crtc->dev;
3229         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3230         struct intel_plane *intel_plane;
3231
3232         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3233                 if (intel_plane->pipe == pipe)
3234                         intel_plane_disable(&intel_plane->base);
3235 }
3236
3237 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         struct intel_encoder *encoder;
3243         int pipe = intel_crtc->pipe;
3244         int plane = intel_crtc->plane;
3245
3246         WARN_ON(!crtc->enabled);
3247
3248         if (intel_crtc->active)
3249                 return;
3250
3251         intel_crtc->active = true;
3252
3253         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3254         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3255
3256         intel_update_watermarks(dev);
3257
3258         for_each_encoder_on_crtc(dev, crtc, encoder)
3259                 if (encoder->pre_enable)
3260                         encoder->pre_enable(encoder);
3261
3262         if (intel_crtc->config.has_pch_encoder) {
3263                 /* Note: FDI PLL enabling _must_ be done before we enable the
3264                  * cpu pipes, hence this is separate from all the other fdi/pch
3265                  * enabling. */
3266                 ironlake_fdi_pll_enable(intel_crtc);
3267         } else {
3268                 assert_fdi_tx_disabled(dev_priv, pipe);
3269                 assert_fdi_rx_disabled(dev_priv, pipe);
3270         }
3271
3272         ironlake_pfit_enable(intel_crtc);
3273
3274         /*
3275          * On ILK+ LUT must be loaded before the pipe is running but with
3276          * clocks enabled
3277          */
3278         intel_crtc_load_lut(crtc);
3279
3280         intel_enable_pipe(dev_priv, pipe,
3281                           intel_crtc->config.has_pch_encoder);
3282         intel_enable_plane(dev_priv, plane, pipe);
3283         intel_enable_planes(crtc);
3284         intel_crtc_update_cursor(crtc, true);
3285
3286         if (intel_crtc->config.has_pch_encoder)
3287                 ironlake_pch_enable(crtc);
3288
3289         mutex_lock(&dev->struct_mutex);
3290         intel_update_fbc(dev);
3291         mutex_unlock(&dev->struct_mutex);
3292
3293         for_each_encoder_on_crtc(dev, crtc, encoder)
3294                 encoder->enable(encoder);
3295
3296         if (HAS_PCH_CPT(dev))
3297                 cpt_verify_modeset(dev, intel_crtc->pipe);
3298
3299         /*
3300          * There seems to be a race in PCH platform hw (at least on some
3301          * outputs) where an enabled pipe still completes any pageflip right
3302          * away (as if the pipe is off) instead of waiting for vblank. As soon
3303          * as the first vblank happend, everything works as expected. Hence just
3304          * wait for one vblank before returning to avoid strange things
3305          * happening.
3306          */
3307         intel_wait_for_vblank(dev, intel_crtc->pipe);
3308 }
3309
3310 /* IPS only exists on ULT machines and is tied to pipe A. */
3311 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3312 {
3313         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3314 }
3315
3316 static void hsw_enable_ips(struct intel_crtc *crtc)
3317 {
3318         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3319
3320         if (!crtc->config.ips_enabled)
3321                 return;
3322
3323         /* We can only enable IPS after we enable a plane and wait for a vblank.
3324          * We guarantee that the plane is enabled by calling intel_enable_ips
3325          * only after intel_enable_plane. And intel_enable_plane already waits
3326          * for a vblank, so all we need to do here is to enable the IPS bit. */
3327         assert_plane_enabled(dev_priv, crtc->plane);
3328         I915_WRITE(IPS_CTL, IPS_ENABLE);
3329 }
3330
3331 static void hsw_disable_ips(struct intel_crtc *crtc)
3332 {
3333         struct drm_device *dev = crtc->base.dev;
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336         if (!crtc->config.ips_enabled)
3337                 return;
3338
3339         assert_plane_enabled(dev_priv, crtc->plane);
3340         I915_WRITE(IPS_CTL, 0);
3341
3342         /* We need to wait for a vblank before we can disable the plane. */
3343         intel_wait_for_vblank(dev, crtc->pipe);
3344 }
3345
3346 static void haswell_crtc_enable(struct drm_crtc *crtc)
3347 {
3348         struct drm_device *dev = crtc->dev;
3349         struct drm_i915_private *dev_priv = dev->dev_private;
3350         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351         struct intel_encoder *encoder;
3352         int pipe = intel_crtc->pipe;
3353         int plane = intel_crtc->plane;
3354
3355         WARN_ON(!crtc->enabled);
3356
3357         if (intel_crtc->active)
3358                 return;
3359
3360         intel_crtc->active = true;
3361
3362         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3363         if (intel_crtc->config.has_pch_encoder)
3364                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3365
3366         intel_update_watermarks(dev);
3367
3368         if (intel_crtc->config.has_pch_encoder)
3369                 dev_priv->display.fdi_link_train(crtc);
3370
3371         for_each_encoder_on_crtc(dev, crtc, encoder)
3372                 if (encoder->pre_enable)
3373                         encoder->pre_enable(encoder);
3374
3375         intel_ddi_enable_pipe_clock(intel_crtc);
3376
3377         ironlake_pfit_enable(intel_crtc);
3378
3379         /*
3380          * On ILK+ LUT must be loaded before the pipe is running but with
3381          * clocks enabled
3382          */
3383         intel_crtc_load_lut(crtc);
3384
3385         intel_ddi_set_pipe_settings(crtc);
3386         intel_ddi_enable_transcoder_func(crtc);
3387
3388         intel_enable_pipe(dev_priv, pipe,
3389                           intel_crtc->config.has_pch_encoder);
3390         intel_enable_plane(dev_priv, plane, pipe);
3391         intel_enable_planes(crtc);
3392         intel_crtc_update_cursor(crtc, true);
3393
3394         hsw_enable_ips(intel_crtc);
3395
3396         if (intel_crtc->config.has_pch_encoder)
3397                 lpt_pch_enable(crtc);
3398
3399         mutex_lock(&dev->struct_mutex);
3400         intel_update_fbc(dev);
3401         mutex_unlock(&dev->struct_mutex);
3402
3403         for_each_encoder_on_crtc(dev, crtc, encoder)
3404                 encoder->enable(encoder);
3405
3406         /*
3407          * There seems to be a race in PCH platform hw (at least on some
3408          * outputs) where an enabled pipe still completes any pageflip right
3409          * away (as if the pipe is off) instead of waiting for vblank. As soon
3410          * as the first vblank happend, everything works as expected. Hence just
3411          * wait for one vblank before returning to avoid strange things
3412          * happening.
3413          */
3414         intel_wait_for_vblank(dev, intel_crtc->pipe);
3415 }
3416
3417 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3418 {
3419         struct drm_device *dev = crtc->base.dev;
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         int pipe = crtc->pipe;
3422
3423         /* To avoid upsetting the power well on haswell only disable the pfit if
3424          * it's in use. The hw state code will make sure we get this right. */
3425         if (crtc->config.pch_pfit.size) {
3426                 I915_WRITE(PF_CTL(pipe), 0);
3427                 I915_WRITE(PF_WIN_POS(pipe), 0);
3428                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3429         }
3430 }
3431
3432 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3433 {
3434         struct drm_device *dev = crtc->dev;
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437         struct intel_encoder *encoder;
3438         int pipe = intel_crtc->pipe;
3439         int plane = intel_crtc->plane;
3440         u32 reg, temp;
3441
3442
3443         if (!intel_crtc->active)
3444                 return;
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 encoder->disable(encoder);
3448
3449         intel_crtc_wait_for_pending_flips(crtc);
3450         drm_vblank_off(dev, pipe);
3451
3452         if (dev_priv->fbc.plane == plane)
3453                 intel_disable_fbc(dev);
3454
3455         intel_crtc_update_cursor(crtc, false);
3456         intel_disable_planes(crtc);
3457         intel_disable_plane(dev_priv, plane, pipe);
3458
3459         if (intel_crtc->config.has_pch_encoder)
3460                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3461
3462         intel_disable_pipe(dev_priv, pipe);
3463
3464         ironlake_pfit_disable(intel_crtc);
3465
3466         for_each_encoder_on_crtc(dev, crtc, encoder)
3467                 if (encoder->post_disable)
3468                         encoder->post_disable(encoder);
3469
3470         if (intel_crtc->config.has_pch_encoder) {
3471                 ironlake_fdi_disable(crtc);
3472
3473                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3474                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3475
3476                 if (HAS_PCH_CPT(dev)) {
3477                         /* disable TRANS_DP_CTL */
3478                         reg = TRANS_DP_CTL(pipe);
3479                         temp = I915_READ(reg);
3480                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3481                                   TRANS_DP_PORT_SEL_MASK);
3482                         temp |= TRANS_DP_PORT_SEL_NONE;
3483                         I915_WRITE(reg, temp);
3484
3485                         /* disable DPLL_SEL */
3486                         temp = I915_READ(PCH_DPLL_SEL);
3487                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3488                         I915_WRITE(PCH_DPLL_SEL, temp);
3489                 }
3490
3491                 /* disable PCH DPLL */
3492                 intel_disable_shared_dpll(intel_crtc);
3493
3494                 ironlake_fdi_pll_disable(intel_crtc);
3495         }
3496
3497         intel_crtc->active = false;
3498         intel_update_watermarks(dev);
3499
3500         mutex_lock(&dev->struct_mutex);
3501         intel_update_fbc(dev);
3502         mutex_unlock(&dev->struct_mutex);
3503 }
3504
3505 static void haswell_crtc_disable(struct drm_crtc *crtc)
3506 {
3507         struct drm_device *dev = crtc->dev;
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3510         struct intel_encoder *encoder;
3511         int pipe = intel_crtc->pipe;
3512         int plane = intel_crtc->plane;
3513         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3514
3515         if (!intel_crtc->active)
3516                 return;
3517
3518         for_each_encoder_on_crtc(dev, crtc, encoder)
3519                 encoder->disable(encoder);
3520
3521         intel_crtc_wait_for_pending_flips(crtc);
3522         drm_vblank_off(dev, pipe);
3523
3524         /* FBC must be disabled before disabling the plane on HSW. */
3525         if (dev_priv->fbc.plane == plane)
3526                 intel_disable_fbc(dev);
3527
3528         hsw_disable_ips(intel_crtc);
3529
3530         intel_crtc_update_cursor(crtc, false);
3531         intel_disable_planes(crtc);
3532         intel_disable_plane(dev_priv, plane, pipe);
3533
3534         if (intel_crtc->config.has_pch_encoder)
3535                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536         intel_disable_pipe(dev_priv, pipe);
3537
3538         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3539
3540         ironlake_pfit_disable(intel_crtc);
3541
3542         intel_ddi_disable_pipe_clock(intel_crtc);
3543
3544         for_each_encoder_on_crtc(dev, crtc, encoder)
3545                 if (encoder->post_disable)
3546                         encoder->post_disable(encoder);
3547
3548         if (intel_crtc->config.has_pch_encoder) {
3549                 lpt_disable_pch_transcoder(dev_priv);
3550                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551                 intel_ddi_fdi_disable(crtc);
3552         }
3553
3554         intel_crtc->active = false;
3555         intel_update_watermarks(dev);
3556
3557         mutex_lock(&dev->struct_mutex);
3558         intel_update_fbc(dev);
3559         mutex_unlock(&dev->struct_mutex);
3560 }
3561
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 {
3564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565         intel_put_shared_dpll(intel_crtc);
3566 }
3567
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 {
3570         intel_ddi_put_crtc_pll(crtc);
3571 }
3572
3573 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3574 {
3575         if (!enable && intel_crtc->overlay) {
3576                 struct drm_device *dev = intel_crtc->base.dev;
3577                 struct drm_i915_private *dev_priv = dev->dev_private;
3578
3579                 mutex_lock(&dev->struct_mutex);
3580                 dev_priv->mm.interruptible = false;
3581                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3582                 dev_priv->mm.interruptible = true;
3583                 mutex_unlock(&dev->struct_mutex);
3584         }
3585
3586         /* Let userspace switch the overlay on again. In most cases userspace
3587          * has to recompute where to put it anyway.
3588          */
3589 }
3590
3591 /**
3592  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593  * cursor plane briefly if not already running after enabling the display
3594  * plane.
3595  * This workaround avoids occasional blank screens when self refresh is
3596  * enabled.
3597  */
3598 static void
3599 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3600 {
3601         u32 cntl = I915_READ(CURCNTR(pipe));
3602
3603         if ((cntl & CURSOR_MODE) == 0) {
3604                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3605
3606                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3607                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3608                 intel_wait_for_vblank(dev_priv->dev, pipe);
3609                 I915_WRITE(CURCNTR(pipe), cntl);
3610                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3611                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3612         }
3613 }
3614
3615 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3616 {
3617         struct drm_device *dev = crtc->base.dev;
3618         struct drm_i915_private *dev_priv = dev->dev_private;
3619         struct intel_crtc_config *pipe_config = &crtc->config;
3620
3621         if (!crtc->config.gmch_pfit.control)
3622                 return;
3623
3624         /*
3625          * The panel fitter should only be adjusted whilst the pipe is disabled,
3626          * according to register description and PRM.
3627          */
3628         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3629         assert_pipe_disabled(dev_priv, crtc->pipe);
3630
3631         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3632         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3633
3634         /* Border color in case we don't scale up to the full screen. Black by
3635          * default, change to something else for debugging. */
3636         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3637 }
3638
3639 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         struct intel_encoder *encoder;
3645         int pipe = intel_crtc->pipe;
3646         int plane = intel_crtc->plane;
3647
3648         WARN_ON(!crtc->enabled);
3649
3650         if (intel_crtc->active)
3651                 return;
3652
3653         intel_crtc->active = true;
3654         intel_update_watermarks(dev);
3655
3656         mutex_lock(&dev_priv->dpio_lock);
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 if (encoder->pre_pll_enable)
3660                         encoder->pre_pll_enable(encoder);
3661
3662         vlv_enable_pll(intel_crtc);
3663
3664         for_each_encoder_on_crtc(dev, crtc, encoder)
3665                 if (encoder->pre_enable)
3666                         encoder->pre_enable(encoder);
3667
3668         /* VLV wants encoder enabling _before_ the pipe is up. */
3669         for_each_encoder_on_crtc(dev, crtc, encoder)
3670                 encoder->enable(encoder);
3671
3672         i9xx_pfit_enable(intel_crtc);
3673
3674         intel_crtc_load_lut(crtc);
3675
3676         intel_enable_pipe(dev_priv, pipe, false);
3677         intel_enable_plane(dev_priv, plane, pipe);
3678         intel_enable_planes(crtc);
3679         intel_crtc_update_cursor(crtc, true);
3680
3681         intel_update_fbc(dev);
3682
3683         mutex_unlock(&dev_priv->dpio_lock);
3684 }
3685
3686 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3687 {
3688         struct drm_device *dev = crtc->dev;
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3691         struct intel_encoder *encoder;
3692         int pipe = intel_crtc->pipe;
3693         int plane = intel_crtc->plane;
3694
3695         WARN_ON(!crtc->enabled);
3696
3697         if (intel_crtc->active)
3698                 return;
3699
3700         intel_crtc->active = true;
3701         intel_update_watermarks(dev);
3702
3703         for_each_encoder_on_crtc(dev, crtc, encoder)
3704                 if (encoder->pre_enable)
3705                         encoder->pre_enable(encoder);
3706
3707         i9xx_enable_pll(intel_crtc);
3708
3709         i9xx_pfit_enable(intel_crtc);
3710
3711         intel_crtc_load_lut(crtc);
3712
3713         intel_enable_pipe(dev_priv, pipe, false);
3714         intel_enable_plane(dev_priv, plane, pipe);
3715         intel_enable_planes(crtc);
3716         /* The fixup needs to happen before cursor is enabled */
3717         if (IS_G4X(dev))
3718                 g4x_fixup_plane(dev_priv, pipe);
3719         intel_crtc_update_cursor(crtc, true);
3720
3721         /* Give the overlay scaler a chance to enable if it's on this pipe */
3722         intel_crtc_dpms_overlay(intel_crtc, true);
3723
3724         intel_update_fbc(dev);
3725
3726         for_each_encoder_on_crtc(dev, crtc, encoder)
3727                 encoder->enable(encoder);
3728 }
3729
3730 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3731 {
3732         struct drm_device *dev = crtc->base.dev;
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734
3735         if (!crtc->config.gmch_pfit.control)
3736                 return;
3737
3738         assert_pipe_disabled(dev_priv, crtc->pipe);
3739
3740         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3741                          I915_READ(PFIT_CONTROL));
3742         I915_WRITE(PFIT_CONTROL, 0);
3743 }
3744
3745 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3746 {
3747         struct drm_device *dev = crtc->dev;
3748         struct drm_i915_private *dev_priv = dev->dev_private;
3749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3750         struct intel_encoder *encoder;
3751         int pipe = intel_crtc->pipe;
3752         int plane = intel_crtc->plane;
3753
3754         if (!intel_crtc->active)
3755                 return;
3756
3757         for_each_encoder_on_crtc(dev, crtc, encoder)
3758                 encoder->disable(encoder);
3759
3760         /* Give the overlay scaler a chance to disable if it's on this pipe */
3761         intel_crtc_wait_for_pending_flips(crtc);
3762         drm_vblank_off(dev, pipe);
3763
3764         if (dev_priv->fbc.plane == plane)
3765                 intel_disable_fbc(dev);
3766
3767         intel_crtc_dpms_overlay(intel_crtc, false);
3768         intel_crtc_update_cursor(crtc, false);
3769         intel_disable_planes(crtc);
3770         intel_disable_plane(dev_priv, plane, pipe);
3771
3772         intel_disable_pipe(dev_priv, pipe);
3773
3774         i9xx_pfit_disable(intel_crtc);
3775
3776         for_each_encoder_on_crtc(dev, crtc, encoder)
3777                 if (encoder->post_disable)
3778                         encoder->post_disable(encoder);
3779
3780         i9xx_disable_pll(dev_priv, pipe);
3781
3782         intel_crtc->active = false;
3783         intel_update_fbc(dev);
3784         intel_update_watermarks(dev);
3785 }
3786
3787 static void i9xx_crtc_off(struct drm_crtc *crtc)
3788 {
3789 }
3790
3791 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3792                                     bool enabled)
3793 {
3794         struct drm_device *dev = crtc->dev;
3795         struct drm_i915_master_private *master_priv;
3796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797         int pipe = intel_crtc->pipe;
3798
3799         if (!dev->primary->master)
3800                 return;
3801
3802         master_priv = dev->primary->master->driver_priv;
3803         if (!master_priv->sarea_priv)
3804                 return;
3805
3806         switch (pipe) {
3807         case 0:
3808                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3809                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3810                 break;
3811         case 1:
3812                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3813                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3814                 break;
3815         default:
3816                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3817                 break;
3818         }
3819 }
3820
3821 /**
3822  * Sets the power management mode of the pipe and plane.
3823  */
3824 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         struct intel_encoder *intel_encoder;
3829         bool enable = false;
3830
3831         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3832                 enable |= intel_encoder->connectors_active;
3833
3834         if (enable)
3835                 dev_priv->display.crtc_enable(crtc);
3836         else
3837                 dev_priv->display.crtc_disable(crtc);
3838
3839         intel_crtc_update_sarea(crtc, enable);
3840 }
3841
3842 static void intel_crtc_disable(struct drm_crtc *crtc)
3843 {
3844         struct drm_device *dev = crtc->dev;
3845         struct drm_connector *connector;
3846         struct drm_i915_private *dev_priv = dev->dev_private;
3847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3848
3849         /* crtc should still be enabled when we disable it. */
3850         WARN_ON(!crtc->enabled);
3851
3852         dev_priv->display.crtc_disable(crtc);
3853         intel_crtc->eld_vld = false;
3854         intel_crtc_update_sarea(crtc, false);
3855         dev_priv->display.off(crtc);
3856
3857         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3858         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3859
3860         if (crtc->fb) {
3861                 mutex_lock(&dev->struct_mutex);
3862                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3863                 mutex_unlock(&dev->struct_mutex);
3864                 crtc->fb = NULL;
3865         }
3866
3867         /* Update computed state. */
3868         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3869                 if (!connector->encoder || !connector->encoder->crtc)
3870                         continue;
3871
3872                 if (connector->encoder->crtc != crtc)
3873                         continue;
3874
3875                 connector->dpms = DRM_MODE_DPMS_OFF;
3876                 to_intel_encoder(connector->encoder)->connectors_active = false;
3877         }
3878 }
3879
3880 void intel_modeset_disable(struct drm_device *dev)
3881 {
3882         struct drm_crtc *crtc;
3883
3884         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3885                 if (crtc->enabled)
3886                         intel_crtc_disable(crtc);
3887         }
3888 }
3889
3890 void intel_encoder_destroy(struct drm_encoder *encoder)
3891 {
3892         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3893
3894         drm_encoder_cleanup(encoder);
3895         kfree(intel_encoder);
3896 }
3897
3898 /* Simple dpms helper for encodres with just one connector, no cloning and only
3899  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3900  * state of the entire output pipe. */
3901 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3902 {
3903         if (mode == DRM_MODE_DPMS_ON) {
3904                 encoder->connectors_active = true;
3905
3906                 intel_crtc_update_dpms(encoder->base.crtc);
3907         } else {
3908                 encoder->connectors_active = false;
3909
3910                 intel_crtc_update_dpms(encoder->base.crtc);
3911         }
3912 }
3913
3914 /* Cross check the actual hw state with our own modeset state tracking (and it's
3915  * internal consistency). */
3916 static void intel_connector_check_state(struct intel_connector *connector)
3917 {
3918         if (connector->get_hw_state(connector)) {
3919                 struct intel_encoder *encoder = connector->encoder;
3920                 struct drm_crtc *crtc;
3921                 bool encoder_enabled;
3922                 enum pipe pipe;
3923
3924                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3925                               connector->base.base.id,
3926                               drm_get_connector_name(&connector->base));
3927
3928                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3929                      "wrong connector dpms state\n");
3930                 WARN(connector->base.encoder != &encoder->base,
3931                      "active connector not linked to encoder\n");
3932                 WARN(!encoder->connectors_active,
3933                      "encoder->connectors_active not set\n");
3934
3935                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3936                 WARN(!encoder_enabled, "encoder not enabled\n");
3937                 if (WARN_ON(!encoder->base.crtc))
3938                         return;
3939
3940                 crtc = encoder->base.crtc;
3941
3942                 WARN(!crtc->enabled, "crtc not enabled\n");
3943                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3944                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3945                      "encoder active on the wrong pipe\n");
3946         }
3947 }
3948
3949 /* Even simpler default implementation, if there's really no special case to
3950  * consider. */
3951 void intel_connector_dpms(struct drm_connector *connector, int mode)
3952 {
3953         struct intel_encoder *encoder = intel_attached_encoder(connector);
3954
3955         /* All the simple cases only support two dpms states. */
3956         if (mode != DRM_MODE_DPMS_ON)
3957                 mode = DRM_MODE_DPMS_OFF;
3958
3959         if (mode == connector->dpms)
3960                 return;
3961
3962         connector->dpms = mode;
3963
3964         /* Only need to change hw state when actually enabled */
3965         if (encoder->base.crtc)
3966                 intel_encoder_dpms(encoder, mode);
3967         else
3968                 WARN_ON(encoder->connectors_active != false);
3969
3970         intel_modeset_check_state(connector->dev);
3971 }
3972
3973 /* Simple connector->get_hw_state implementation for encoders that support only
3974  * one connector and no cloning and hence the encoder state determines the state
3975  * of the connector. */
3976 bool intel_connector_get_hw_state(struct intel_connector *connector)
3977 {
3978         enum pipe pipe = 0;
3979         struct intel_encoder *encoder = connector->encoder;
3980
3981         return encoder->get_hw_state(encoder, &pipe);
3982 }
3983
3984 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3985                                      struct intel_crtc_config *pipe_config)
3986 {
3987         struct drm_i915_private *dev_priv = dev->dev_private;
3988         struct intel_crtc *pipe_B_crtc =
3989                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3990
3991         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3992                       pipe_name(pipe), pipe_config->fdi_lanes);
3993         if (pipe_config->fdi_lanes > 4) {
3994                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3995                               pipe_name(pipe), pipe_config->fdi_lanes);
3996                 return false;
3997         }
3998
3999         if (IS_HASWELL(dev)) {
4000                 if (pipe_config->fdi_lanes > 2) {
4001                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4002                                       pipe_config->fdi_lanes);
4003                         return false;
4004                 } else {
4005                         return true;
4006                 }
4007         }
4008
4009         if (INTEL_INFO(dev)->num_pipes == 2)
4010                 return true;
4011
4012         /* Ivybridge 3 pipe is really complicated */
4013         switch (pipe) {
4014         case PIPE_A:
4015                 return true;
4016         case PIPE_B:
4017                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4018                     pipe_config->fdi_lanes > 2) {
4019                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020                                       pipe_name(pipe), pipe_config->fdi_lanes);
4021                         return false;
4022                 }
4023                 return true;
4024         case PIPE_C:
4025                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4026                     pipe_B_crtc->config.fdi_lanes <= 2) {
4027                         if (pipe_config->fdi_lanes > 2) {
4028                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4029                                               pipe_name(pipe), pipe_config->fdi_lanes);
4030                                 return false;
4031                         }
4032                 } else {
4033                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4034                         return false;
4035                 }
4036                 return true;
4037         default:
4038                 BUG();
4039         }
4040 }
4041
4042 #define RETRY 1
4043 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4044                                        struct intel_crtc_config *pipe_config)
4045 {
4046         struct drm_device *dev = intel_crtc->base.dev;
4047         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4048         int lane, link_bw, fdi_dotclock;
4049         bool setup_ok, needs_recompute = false;
4050
4051 retry:
4052         /* FDI is a binary signal running at ~2.7GHz, encoding
4053          * each output octet as 10 bits. The actual frequency
4054          * is stored as a divider into a 100MHz clock, and the
4055          * mode pixel clock is stored in units of 1KHz.
4056          * Hence the bw of each lane in terms of the mode signal
4057          * is:
4058          */
4059         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4060
4061         fdi_dotclock = adjusted_mode->clock;
4062         fdi_dotclock /= pipe_config->pixel_multiplier;
4063
4064         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4065                                            pipe_config->pipe_bpp);
4066
4067         pipe_config->fdi_lanes = lane;
4068
4069         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4070                                link_bw, &pipe_config->fdi_m_n);
4071
4072         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4073                                             intel_crtc->pipe, pipe_config);
4074         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4075                 pipe_config->pipe_bpp -= 2*3;
4076                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4077                               pipe_config->pipe_bpp);
4078                 needs_recompute = true;
4079                 pipe_config->bw_constrained = true;
4080
4081                 goto retry;
4082         }
4083
4084         if (needs_recompute)
4085                 return RETRY;
4086
4087         return setup_ok ? 0 : -EINVAL;
4088 }
4089
4090 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4091                                    struct intel_crtc_config *pipe_config)
4092 {
4093         pipe_config->ips_enabled = i915_enable_ips &&
4094                                    hsw_crtc_supports_ips(crtc) &&
4095                                    pipe_config->pipe_bpp == 24;
4096 }
4097
4098 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4099                                      struct intel_crtc_config *pipe_config)
4100 {
4101         struct drm_device *dev = crtc->base.dev;
4102         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4103
4104         if (HAS_PCH_SPLIT(dev)) {
4105                 /* FDI link clock is fixed at 2.7G */
4106                 if (pipe_config->requested_mode.clock * 3
4107                     > IRONLAKE_FDI_FREQ * 4)
4108                         return -EINVAL;
4109         }
4110
4111         /* All interlaced capable intel hw wants timings in frames. Note though
4112          * that intel_lvds_compute_config does some funny tricks with the crtc
4113          * timings, so we need to be careful not to clobber these.*/
4114         if (!pipe_config->timings_set)
4115                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4116
4117         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4118          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4119          */
4120         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4121                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4122                 return -EINVAL;
4123
4124         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4125                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4126         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4127                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4128                  * for lvds. */
4129                 pipe_config->pipe_bpp = 8*3;
4130         }
4131
4132         if (HAS_IPS(dev))
4133                 hsw_compute_ips_config(crtc, pipe_config);
4134
4135         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4136          * clock survives for now. */
4137         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4138                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4139
4140         if (pipe_config->has_pch_encoder)
4141                 return ironlake_fdi_compute_config(crtc, pipe_config);
4142
4143         return 0;
4144 }
4145
4146 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4147 {
4148         return 400000; /* FIXME */
4149 }
4150
4151 static int i945_get_display_clock_speed(struct drm_device *dev)
4152 {
4153         return 400000;
4154 }
4155
4156 static int i915_get_display_clock_speed(struct drm_device *dev)
4157 {
4158         return 333000;
4159 }
4160
4161 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4162 {
4163         return 200000;
4164 }
4165
4166 static int pnv_get_display_clock_speed(struct drm_device *dev)
4167 {
4168         u16 gcfgc = 0;
4169
4170         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4171
4172         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4173         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4174                 return 267000;
4175         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4176                 return 333000;
4177         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4178                 return 444000;
4179         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4180                 return 200000;
4181         default:
4182                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4183         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4184                 return 133000;
4185         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4186                 return 167000;
4187         }
4188 }
4189
4190 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4191 {
4192         u16 gcfgc = 0;
4193
4194         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4195
4196         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4197                 return 133000;
4198         else {
4199                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4200                 case GC_DISPLAY_CLOCK_333_MHZ:
4201                         return 333000;
4202                 default:
4203                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4204                         return 190000;
4205                 }
4206         }
4207 }
4208
4209 static int i865_get_display_clock_speed(struct drm_device *dev)
4210 {
4211         return 266000;
4212 }
4213
4214 static int i855_get_display_clock_speed(struct drm_device *dev)
4215 {
4216         u16 hpllcc = 0;
4217         /* Assume that the hardware is in the high speed state.  This
4218          * should be the default.
4219          */
4220         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4221         case GC_CLOCK_133_200:
4222         case GC_CLOCK_100_200:
4223                 return 200000;
4224         case GC_CLOCK_166_250:
4225                 return 250000;
4226         case GC_CLOCK_100_133:
4227                 return 133000;
4228         }
4229
4230         /* Shouldn't happen */
4231         return 0;
4232 }
4233
4234 static int i830_get_display_clock_speed(struct drm_device *dev)
4235 {
4236         return 133000;
4237 }
4238
4239 static void
4240 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4241 {
4242         while (*num > DATA_LINK_M_N_MASK ||
4243                *den > DATA_LINK_M_N_MASK) {
4244                 *num >>= 1;
4245                 *den >>= 1;
4246         }
4247 }
4248
4249 static void compute_m_n(unsigned int m, unsigned int n,
4250                         uint32_t *ret_m, uint32_t *ret_n)
4251 {
4252         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4253         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4254         intel_reduce_m_n_ratio(ret_m, ret_n);
4255 }
4256
4257 void
4258 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4259                        int pixel_clock, int link_clock,
4260                        struct intel_link_m_n *m_n)
4261 {
4262         m_n->tu = 64;
4263
4264         compute_m_n(bits_per_pixel * pixel_clock,
4265                     link_clock * nlanes * 8,
4266                     &m_n->gmch_m, &m_n->gmch_n);
4267
4268         compute_m_n(pixel_clock, link_clock,
4269                     &m_n->link_m, &m_n->link_n);
4270 }
4271
4272 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4273 {
4274         if (i915_panel_use_ssc >= 0)
4275                 return i915_panel_use_ssc != 0;
4276         return dev_priv->vbt.lvds_use_ssc
4277                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4278 }
4279
4280 static int vlv_get_refclk(struct drm_crtc *crtc)
4281 {
4282         struct drm_device *dev = crtc->dev;
4283         struct drm_i915_private *dev_priv = dev->dev_private;
4284         int refclk = 27000; /* for DP & HDMI */
4285
4286         return 100000; /* only one validated so far */
4287
4288         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4289                 refclk = 96000;
4290         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4291                 if (intel_panel_use_ssc(dev_priv))
4292                         refclk = 100000;
4293                 else
4294                         refclk = 96000;
4295         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4296                 refclk = 100000;
4297         }
4298
4299         return refclk;
4300 }
4301
4302 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4303 {
4304         struct drm_device *dev = crtc->dev;
4305         struct drm_i915_private *dev_priv = dev->dev_private;
4306         int refclk;
4307
4308         if (IS_VALLEYVIEW(dev)) {
4309                 refclk = vlv_get_refclk(crtc);
4310         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4311             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4312                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4313                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4314                               refclk / 1000);
4315         } else if (!IS_GEN2(dev)) {
4316                 refclk = 96000;
4317         } else {
4318                 refclk = 48000;
4319         }
4320
4321         return refclk;
4322 }
4323
4324 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4325 {
4326         return (1 << dpll->n) << 16 | dpll->m2;
4327 }
4328
4329 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4330 {
4331         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4332 }
4333
4334 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4335                                      intel_clock_t *reduced_clock)
4336 {
4337         struct drm_device *dev = crtc->base.dev;
4338         struct drm_i915_private *dev_priv = dev->dev_private;
4339         int pipe = crtc->pipe;
4340         u32 fp, fp2 = 0;
4341
4342         if (IS_PINEVIEW(dev)) {
4343                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4344                 if (reduced_clock)
4345                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4346         } else {
4347                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4348                 if (reduced_clock)
4349                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4350         }
4351
4352         I915_WRITE(FP0(pipe), fp);
4353         crtc->config.dpll_hw_state.fp0 = fp;
4354
4355         crtc->lowfreq_avail = false;
4356         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4357             reduced_clock && i915_powersave) {
4358                 I915_WRITE(FP1(pipe), fp2);
4359                 crtc->config.dpll_hw_state.fp1 = fp2;
4360                 crtc->lowfreq_avail = true;
4361         } else {
4362                 I915_WRITE(FP1(pipe), fp);
4363                 crtc->config.dpll_hw_state.fp1 = fp;
4364         }
4365 }
4366
4367 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4368 {
4369         u32 reg_val;
4370
4371         /*
4372          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4373          * and set it to a reasonable value instead.
4374          */
4375         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4376         reg_val &= 0xffffff00;
4377         reg_val |= 0x00000030;
4378         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4379
4380         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4381         reg_val &= 0x8cffffff;
4382         reg_val = 0x8c000000;
4383         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4384
4385         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4386         reg_val &= 0xffffff00;
4387         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4388
4389         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4390         reg_val &= 0x00ffffff;
4391         reg_val |= 0xb0000000;
4392         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4393 }
4394
4395 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4396                                          struct intel_link_m_n *m_n)
4397 {
4398         struct drm_device *dev = crtc->base.dev;
4399         struct drm_i915_private *dev_priv = dev->dev_private;
4400         int pipe = crtc->pipe;
4401
4402         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4403         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4404         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4405         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4406 }
4407
4408 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4409                                          struct intel_link_m_n *m_n)
4410 {
4411         struct drm_device *dev = crtc->base.dev;
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         int pipe = crtc->pipe;
4414         enum transcoder transcoder = crtc->config.cpu_transcoder;
4415
4416         if (INTEL_INFO(dev)->gen >= 5) {
4417                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4418                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4419                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4420                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4421         } else {
4422                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4423                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4424                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4425                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4426         }
4427 }
4428
4429 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4430 {
4431         if (crtc->config.has_pch_encoder)
4432                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4433         else
4434                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4435 }
4436
4437 static void vlv_update_pll(struct intel_crtc *crtc)
4438 {
4439         struct drm_device *dev = crtc->base.dev;
4440         struct drm_i915_private *dev_priv = dev->dev_private;
4441         int pipe = crtc->pipe;
4442         u32 dpll, mdiv;
4443         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4444         bool is_hdmi;
4445         u32 coreclk, reg_val, dpll_md;
4446
4447         mutex_lock(&dev_priv->dpio_lock);
4448
4449         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4450
4451         bestn = crtc->config.dpll.n;
4452         bestm1 = crtc->config.dpll.m1;
4453         bestm2 = crtc->config.dpll.m2;
4454         bestp1 = crtc->config.dpll.p1;
4455         bestp2 = crtc->config.dpll.p2;
4456
4457         /* See eDP HDMI DPIO driver vbios notes doc */
4458
4459         /* PLL B needs special handling */
4460         if (pipe)
4461                 vlv_pllb_recal_opamp(dev_priv);
4462
4463         /* Set up Tx target for periodic Rcomp update */
4464         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4465
4466         /* Disable target IRef on PLL */
4467         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4468         reg_val &= 0x00ffffff;
4469         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4470
4471         /* Disable fast lock */
4472         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4473
4474         /* Set idtafcrecal before PLL is enabled */
4475         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4476         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4477         mdiv |= ((bestn << DPIO_N_SHIFT));
4478         mdiv |= (1 << DPIO_K_SHIFT);
4479
4480         /*
4481          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4482          * but we don't support that).
4483          * Note: don't use the DAC post divider as it seems unstable.
4484          */
4485         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4486         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4487
4488         mdiv |= DPIO_ENABLE_CALIBRATION;
4489         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4490
4491         /* Set HBR and RBR LPF coefficients */
4492         if (crtc->config.port_clock == 162000 ||
4493             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4494             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4495                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4496                                  0x009f0003);
4497         else
4498                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4499                                  0x00d0000f);
4500
4501         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4502             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4503                 /* Use SSC source */
4504                 if (!pipe)
4505                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4506                                          0x0df40000);
4507                 else
4508                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4509                                          0x0df70000);
4510         } else { /* HDMI or VGA */
4511                 /* Use bend source */
4512                 if (!pipe)
4513                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4514                                          0x0df70000);
4515                 else
4516                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4517                                          0x0df40000);
4518         }
4519
4520         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4521         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4522         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4523             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4524                 coreclk |= 0x01000000;
4525         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4526
4527         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4528
4529         /* Enable DPIO clock input */
4530         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4531                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4532         if (pipe)
4533                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4534
4535         dpll |= DPLL_VCO_ENABLE;
4536         crtc->config.dpll_hw_state.dpll = dpll;
4537
4538         dpll_md = (crtc->config.pixel_multiplier - 1)
4539                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4540         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4541
4542         if (crtc->config.has_dp_encoder)
4543                 intel_dp_set_m_n(crtc);
4544
4545         mutex_unlock(&dev_priv->dpio_lock);
4546 }
4547
4548 static void i9xx_update_pll(struct intel_crtc *crtc,
4549                             intel_clock_t *reduced_clock,
4550                             int num_connectors)
4551 {
4552         struct drm_device *dev = crtc->base.dev;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         u32 dpll;
4555         bool is_sdvo;
4556         struct dpll *clock = &crtc->config.dpll;
4557
4558         i9xx_update_pll_dividers(crtc, reduced_clock);
4559
4560         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4561                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4562
4563         dpll = DPLL_VGA_MODE_DIS;
4564
4565         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4566                 dpll |= DPLLB_MODE_LVDS;
4567         else
4568                 dpll |= DPLLB_MODE_DAC_SERIAL;
4569
4570         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4571                 dpll |= (crtc->config.pixel_multiplier - 1)
4572                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4573         }
4574
4575         if (is_sdvo)
4576                 dpll |= DPLL_SDVO_HIGH_SPEED;
4577
4578         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4579                 dpll |= DPLL_SDVO_HIGH_SPEED;
4580
4581         /* compute bitmask from p1 value */
4582         if (IS_PINEVIEW(dev))
4583                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4584         else {
4585                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586                 if (IS_G4X(dev) && reduced_clock)
4587                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4588         }
4589         switch (clock->p2) {
4590         case 5:
4591                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4592                 break;
4593         case 7:
4594                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4595                 break;
4596         case 10:
4597                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4598                 break;
4599         case 14:
4600                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4601                 break;
4602         }
4603         if (INTEL_INFO(dev)->gen >= 4)
4604                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4605
4606         if (crtc->config.sdvo_tv_clock)
4607                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4608         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4609                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4611         else
4612                 dpll |= PLL_REF_INPUT_DREFCLK;
4613
4614         dpll |= DPLL_VCO_ENABLE;
4615         crtc->config.dpll_hw_state.dpll = dpll;
4616
4617         if (INTEL_INFO(dev)->gen >= 4) {
4618                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4619                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4620                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4621         }
4622
4623         if (crtc->config.has_dp_encoder)
4624                 intel_dp_set_m_n(crtc);
4625 }
4626
4627 static void i8xx_update_pll(struct intel_crtc *crtc,
4628                             intel_clock_t *reduced_clock,
4629                             int num_connectors)
4630 {
4631         struct drm_device *dev = crtc->base.dev;
4632         struct drm_i915_private *dev_priv = dev->dev_private;
4633         u32 dpll;
4634         struct dpll *clock = &crtc->config.dpll;
4635
4636         i9xx_update_pll_dividers(crtc, reduced_clock);
4637
4638         dpll = DPLL_VGA_MODE_DIS;
4639
4640         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4641                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4642         } else {
4643                 if (clock->p1 == 2)
4644                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4645                 else
4646                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4647                 if (clock->p2 == 4)
4648                         dpll |= PLL_P2_DIVIDE_BY_4;
4649         }
4650
4651         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4652                 dpll |= DPLL_DVO_2X_MODE;
4653
4654         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4655                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4656                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4657         else
4658                 dpll |= PLL_REF_INPUT_DREFCLK;
4659
4660         dpll |= DPLL_VCO_ENABLE;
4661         crtc->config.dpll_hw_state.dpll = dpll;
4662 }
4663
4664 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4665 {
4666         struct drm_device *dev = intel_crtc->base.dev;
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668         enum pipe pipe = intel_crtc->pipe;
4669         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4670         struct drm_display_mode *adjusted_mode =
4671                 &intel_crtc->config.adjusted_mode;
4672         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4673         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4674
4675         /* We need to be careful not to changed the adjusted mode, for otherwise
4676          * the hw state checker will get angry at the mismatch. */
4677         crtc_vtotal = adjusted_mode->crtc_vtotal;
4678         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4679
4680         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4681                 /* the chip adds 2 halflines automatically */
4682                 crtc_vtotal -= 1;
4683                 crtc_vblank_end -= 1;
4684                 vsyncshift = adjusted_mode->crtc_hsync_start
4685                              - adjusted_mode->crtc_htotal / 2;
4686         } else {
4687                 vsyncshift = 0;
4688         }
4689
4690         if (INTEL_INFO(dev)->gen > 3)
4691                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4692
4693         I915_WRITE(HTOTAL(cpu_transcoder),
4694                    (adjusted_mode->crtc_hdisplay - 1) |
4695                    ((adjusted_mode->crtc_htotal - 1) << 16));
4696         I915_WRITE(HBLANK(cpu_transcoder),
4697                    (adjusted_mode->crtc_hblank_start - 1) |
4698                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4699         I915_WRITE(HSYNC(cpu_transcoder),
4700                    (adjusted_mode->crtc_hsync_start - 1) |
4701                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4702
4703         I915_WRITE(VTOTAL(cpu_transcoder),
4704                    (adjusted_mode->crtc_vdisplay - 1) |
4705                    ((crtc_vtotal - 1) << 16));
4706         I915_WRITE(VBLANK(cpu_transcoder),
4707                    (adjusted_mode->crtc_vblank_start - 1) |
4708                    ((crtc_vblank_end - 1) << 16));
4709         I915_WRITE(VSYNC(cpu_transcoder),
4710                    (adjusted_mode->crtc_vsync_start - 1) |
4711                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4712
4713         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4714          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4715          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4716          * bits. */
4717         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4718             (pipe == PIPE_B || pipe == PIPE_C))
4719                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4720
4721         /* pipesrc controls the size that is scaled from, which should
4722          * always be the user's requested size.
4723          */
4724         I915_WRITE(PIPESRC(pipe),
4725                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4726 }
4727
4728 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4729                                    struct intel_crtc_config *pipe_config)
4730 {
4731         struct drm_device *dev = crtc->base.dev;
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4734         uint32_t tmp;
4735
4736         tmp = I915_READ(HTOTAL(cpu_transcoder));
4737         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4738         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4739         tmp = I915_READ(HBLANK(cpu_transcoder));
4740         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4741         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4742         tmp = I915_READ(HSYNC(cpu_transcoder));
4743         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4744         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4745
4746         tmp = I915_READ(VTOTAL(cpu_transcoder));
4747         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4748         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4749         tmp = I915_READ(VBLANK(cpu_transcoder));
4750         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4751         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4752         tmp = I915_READ(VSYNC(cpu_transcoder));
4753         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4754         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4755
4756         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4757                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4758                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4759                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4760         }
4761
4762         tmp = I915_READ(PIPESRC(crtc->pipe));
4763         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4764         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4765 }
4766
4767 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4768                                              struct intel_crtc_config *pipe_config)
4769 {
4770         struct drm_crtc *crtc = &intel_crtc->base;
4771
4772         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4773         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4774         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4775         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4776
4777         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4778         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4779         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4780         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4781
4782         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4783
4784         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4785         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4786 }
4787
4788 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4789 {
4790         struct drm_device *dev = intel_crtc->base.dev;
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         uint32_t pipeconf;
4793
4794         pipeconf = 0;
4795
4796         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4797                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4798                  * core speed.
4799                  *
4800                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4801                  * pipe == 0 check?
4802                  */
4803                 if (intel_crtc->config.requested_mode.clock >
4804                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4805                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4806         }
4807
4808         /* only g4x and later have fancy bpc/dither controls */
4809         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4810                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4811                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4812                         pipeconf |= PIPECONF_DITHER_EN |
4813                                     PIPECONF_DITHER_TYPE_SP;
4814
4815                 switch (intel_crtc->config.pipe_bpp) {
4816                 case 18:
4817                         pipeconf |= PIPECONF_6BPC;
4818                         break;
4819                 case 24:
4820                         pipeconf |= PIPECONF_8BPC;
4821                         break;
4822                 case 30:
4823                         pipeconf |= PIPECONF_10BPC;
4824                         break;
4825                 default:
4826                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4827                         BUG();
4828                 }
4829         }
4830
4831         if (HAS_PIPE_CXSR(dev)) {
4832                 if (intel_crtc->lowfreq_avail) {
4833                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4834                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4835                 } else {
4836                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4837                 }
4838         }
4839
4840         if (!IS_GEN2(dev) &&
4841             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4842                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4843         else
4844                 pipeconf |= PIPECONF_PROGRESSIVE;
4845
4846         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4847                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4848
4849         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4850         POSTING_READ(PIPECONF(intel_crtc->pipe));
4851 }
4852
4853 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4854                               int x, int y,
4855                               struct drm_framebuffer *fb)
4856 {
4857         struct drm_device *dev = crtc->dev;
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4861         int pipe = intel_crtc->pipe;
4862         int plane = intel_crtc->plane;
4863         int refclk, num_connectors = 0;
4864         intel_clock_t clock, reduced_clock;
4865         u32 dspcntr;
4866         bool ok, has_reduced_clock = false;
4867         bool is_lvds = false;
4868         struct intel_encoder *encoder;
4869         const intel_limit_t *limit;
4870         int ret;
4871
4872         for_each_encoder_on_crtc(dev, crtc, encoder) {
4873                 switch (encoder->type) {
4874                 case INTEL_OUTPUT_LVDS:
4875                         is_lvds = true;
4876                         break;
4877                 }
4878
4879                 num_connectors++;
4880         }
4881
4882         refclk = i9xx_get_refclk(crtc, num_connectors);
4883
4884         /*
4885          * Returns a set of divisors for the desired target clock with the given
4886          * refclk, or FALSE.  The returned values represent the clock equation:
4887          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4888          */
4889         limit = intel_limit(crtc, refclk);
4890         ok = dev_priv->display.find_dpll(limit, crtc,
4891                                          intel_crtc->config.port_clock,
4892                                          refclk, NULL, &clock);
4893         if (!ok && !intel_crtc->config.clock_set) {
4894                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4895                 return -EINVAL;
4896         }
4897
4898         /* Ensure that the cursor is valid for the new mode before changing... */
4899         intel_crtc_update_cursor(crtc, true);
4900
4901         if (is_lvds && dev_priv->lvds_downclock_avail) {
4902                 /*
4903                  * Ensure we match the reduced clock's P to the target clock.
4904                  * If the clocks don't match, we can't switch the display clock
4905                  * by using the FP0/FP1. In such case we will disable the LVDS
4906                  * downclock feature.
4907                 */
4908                 has_reduced_clock =
4909                         dev_priv->display.find_dpll(limit, crtc,
4910                                                     dev_priv->lvds_downclock,
4911                                                     refclk, &clock,
4912                                                     &reduced_clock);
4913         }
4914         /* Compat-code for transition, will disappear. */
4915         if (!intel_crtc->config.clock_set) {
4916                 intel_crtc->config.dpll.n = clock.n;
4917                 intel_crtc->config.dpll.m1 = clock.m1;
4918                 intel_crtc->config.dpll.m2 = clock.m2;
4919                 intel_crtc->config.dpll.p1 = clock.p1;
4920                 intel_crtc->config.dpll.p2 = clock.p2;
4921         }
4922
4923         if (IS_GEN2(dev))
4924                 i8xx_update_pll(intel_crtc,
4925                                 has_reduced_clock ? &reduced_clock : NULL,
4926                                 num_connectors);
4927         else if (IS_VALLEYVIEW(dev))
4928                 vlv_update_pll(intel_crtc);
4929         else
4930                 i9xx_update_pll(intel_crtc,
4931                                 has_reduced_clock ? &reduced_clock : NULL,
4932                                 num_connectors);
4933
4934         /* Set up the display plane register */
4935         dspcntr = DISPPLANE_GAMMA_ENABLE;
4936
4937         if (!IS_VALLEYVIEW(dev)) {
4938                 if (pipe == 0)
4939                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4940                 else
4941                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4942         }
4943
4944         intel_set_pipe_timings(intel_crtc);
4945
4946         /* pipesrc and dspsize control the size that is scaled from,
4947          * which should always be the user's requested size.
4948          */
4949         I915_WRITE(DSPSIZE(plane),
4950                    ((mode->vdisplay - 1) << 16) |
4951                    (mode->hdisplay - 1));
4952         I915_WRITE(DSPPOS(plane), 0);
4953
4954         i9xx_set_pipeconf(intel_crtc);
4955
4956         I915_WRITE(DSPCNTR(plane), dspcntr);
4957         POSTING_READ(DSPCNTR(plane));
4958
4959         ret = intel_pipe_set_base(crtc, x, y, fb);
4960
4961         intel_update_watermarks(dev);
4962
4963         return ret;
4964 }
4965
4966 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4967                                  struct intel_crtc_config *pipe_config)
4968 {
4969         struct drm_device *dev = crtc->base.dev;
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         uint32_t tmp;
4972
4973         tmp = I915_READ(PFIT_CONTROL);
4974         if (!(tmp & PFIT_ENABLE))
4975                 return;
4976
4977         /* Check whether the pfit is attached to our pipe. */
4978         if (INTEL_INFO(dev)->gen < 4) {
4979                 if (crtc->pipe != PIPE_B)
4980                         return;
4981         } else {
4982                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4983                         return;
4984         }
4985
4986         pipe_config->gmch_pfit.control = tmp;
4987         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4988         if (INTEL_INFO(dev)->gen < 5)
4989                 pipe_config->gmch_pfit.lvds_border_bits =
4990                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4991 }
4992
4993 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4994                                  struct intel_crtc_config *pipe_config)
4995 {
4996         struct drm_device *dev = crtc->base.dev;
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         uint32_t tmp;
4999
5000         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5001         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5002
5003         tmp = I915_READ(PIPECONF(crtc->pipe));
5004         if (!(tmp & PIPECONF_ENABLE))
5005                 return false;
5006
5007         intel_get_pipe_timings(crtc, pipe_config);
5008
5009         i9xx_get_pfit_config(crtc, pipe_config);
5010
5011         if (INTEL_INFO(dev)->gen >= 4) {
5012                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5013                 pipe_config->pixel_multiplier =
5014                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5015                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5016                 pipe_config->dpll_hw_state.dpll_md = tmp;
5017         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5018                 tmp = I915_READ(DPLL(crtc->pipe));
5019                 pipe_config->pixel_multiplier =
5020                         ((tmp & SDVO_MULTIPLIER_MASK)
5021                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5022         } else {
5023                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5024                  * port and will be fixed up in the encoder->get_config
5025                  * function. */
5026                 pipe_config->pixel_multiplier = 1;
5027         }
5028         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5029         if (!IS_VALLEYVIEW(dev)) {
5030                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5031                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5032         } else {
5033                 /* Mask out read-only status bits. */
5034                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5035                                                      DPLL_PORTC_READY_MASK |
5036                                                      DPLL_PORTB_READY_MASK);
5037         }
5038
5039         return true;
5040 }
5041
5042 static void ironlake_init_pch_refclk(struct drm_device *dev)
5043 {
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045         struct drm_mode_config *mode_config = &dev->mode_config;
5046         struct intel_encoder *encoder;
5047         u32 val, final;
5048         bool has_lvds = false;
5049         bool has_cpu_edp = false;
5050         bool has_panel = false;
5051         bool has_ck505 = false;
5052         bool can_ssc = false;
5053
5054         /* We need to take the global config into account */
5055         list_for_each_entry(encoder, &mode_config->encoder_list,
5056                             base.head) {
5057                 switch (encoder->type) {
5058                 case INTEL_OUTPUT_LVDS:
5059                         has_panel = true;
5060                         has_lvds = true;
5061                         break;
5062                 case INTEL_OUTPUT_EDP:
5063                         has_panel = true;
5064                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5065                                 has_cpu_edp = true;
5066                         break;
5067                 }
5068         }
5069
5070         if (HAS_PCH_IBX(dev)) {
5071                 has_ck505 = dev_priv->vbt.display_clock_mode;
5072                 can_ssc = has_ck505;
5073         } else {
5074                 has_ck505 = false;
5075                 can_ssc = true;
5076         }
5077
5078         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5079                       has_panel, has_lvds, has_ck505);
5080
5081         /* Ironlake: try to setup display ref clock before DPLL
5082          * enabling. This is only under driver's control after
5083          * PCH B stepping, previous chipset stepping should be
5084          * ignoring this setting.
5085          */
5086         val = I915_READ(PCH_DREF_CONTROL);
5087
5088         /* As we must carefully and slowly disable/enable each source in turn,
5089          * compute the final state we want first and check if we need to
5090          * make any changes at all.
5091          */
5092         final = val;
5093         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5094         if (has_ck505)
5095                 final |= DREF_NONSPREAD_CK505_ENABLE;
5096         else
5097                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5098
5099         final &= ~DREF_SSC_SOURCE_MASK;
5100         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5101         final &= ~DREF_SSC1_ENABLE;
5102
5103         if (has_panel) {
5104                 final |= DREF_SSC_SOURCE_ENABLE;
5105
5106                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5107                         final |= DREF_SSC1_ENABLE;
5108
5109                 if (has_cpu_edp) {
5110                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5111                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5112                         else
5113                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5114                 } else
5115                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5116         } else {
5117                 final |= DREF_SSC_SOURCE_DISABLE;
5118                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119         }
5120
5121         if (final == val)
5122                 return;
5123
5124         /* Always enable nonspread source */
5125         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5126
5127         if (has_ck505)
5128                 val |= DREF_NONSPREAD_CK505_ENABLE;
5129         else
5130                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5131
5132         if (has_panel) {
5133                 val &= ~DREF_SSC_SOURCE_MASK;
5134                 val |= DREF_SSC_SOURCE_ENABLE;
5135
5136                 /* SSC must be turned on before enabling the CPU output  */
5137                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5138                         DRM_DEBUG_KMS("Using SSC on panel\n");
5139                         val |= DREF_SSC1_ENABLE;
5140                 } else
5141                         val &= ~DREF_SSC1_ENABLE;
5142
5143                 /* Get SSC going before enabling the outputs */
5144                 I915_WRITE(PCH_DREF_CONTROL, val);
5145                 POSTING_READ(PCH_DREF_CONTROL);
5146                 udelay(200);
5147
5148                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5149
5150                 /* Enable CPU source on CPU attached eDP */
5151                 if (has_cpu_edp) {
5152                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5153                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5154                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5155                         }
5156                         else
5157                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5158                 } else
5159                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5160
5161                 I915_WRITE(PCH_DREF_CONTROL, val);
5162                 POSTING_READ(PCH_DREF_CONTROL);
5163                 udelay(200);
5164         } else {
5165                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5166
5167                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5168
5169                 /* Turn off CPU output */
5170                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5171
5172                 I915_WRITE(PCH_DREF_CONTROL, val);
5173                 POSTING_READ(PCH_DREF_CONTROL);
5174                 udelay(200);
5175
5176                 /* Turn off the SSC source */
5177                 val &= ~DREF_SSC_SOURCE_MASK;
5178                 val |= DREF_SSC_SOURCE_DISABLE;
5179
5180                 /* Turn off SSC1 */
5181                 val &= ~DREF_SSC1_ENABLE;
5182
5183                 I915_WRITE(PCH_DREF_CONTROL, val);
5184                 POSTING_READ(PCH_DREF_CONTROL);
5185                 udelay(200);
5186         }
5187
5188         BUG_ON(val != final);
5189 }
5190
5191 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5192 {
5193         uint32_t tmp;
5194
5195         tmp = I915_READ(SOUTH_CHICKEN2);
5196         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5197         I915_WRITE(SOUTH_CHICKEN2, tmp);
5198
5199         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5200                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5201                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5202
5203         tmp = I915_READ(SOUTH_CHICKEN2);
5204         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5205         I915_WRITE(SOUTH_CHICKEN2, tmp);
5206
5207         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5208                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5209                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5210 }
5211
5212 /* WaMPhyProgramming:hsw */
5213 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5214 {
5215         uint32_t tmp;
5216
5217         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218         tmp &= ~(0xFF << 24);
5219         tmp |= (0x12 << 24);
5220         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5221
5222         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5223         tmp |= (1 << 11);
5224         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5227         tmp |= (1 << 11);
5228         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5229
5230         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5231         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5232         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5233
5234         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5235         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5236         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5237
5238         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5239         tmp &= ~(7 << 13);
5240         tmp |= (5 << 13);
5241         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5242
5243         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5244         tmp &= ~(7 << 13);
5245         tmp |= (5 << 13);
5246         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5247
5248         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5249         tmp &= ~0xFF;
5250         tmp |= 0x1C;
5251         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5252
5253         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5254         tmp &= ~0xFF;
5255         tmp |= 0x1C;
5256         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5257
5258         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5259         tmp &= ~(0xFF << 16);
5260         tmp |= (0x1C << 16);
5261         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5262
5263         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5264         tmp &= ~(0xFF << 16);
5265         tmp |= (0x1C << 16);
5266         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5267
5268         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5269         tmp |= (1 << 27);
5270         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5271
5272         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5273         tmp |= (1 << 27);
5274         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5275
5276         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5277         tmp &= ~(0xF << 28);
5278         tmp |= (4 << 28);
5279         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5280
5281         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5282         tmp &= ~(0xF << 28);
5283         tmp |= (4 << 28);
5284         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5285 }
5286
5287 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5288  * Programming" based on the parameters passed:
5289  * - Sequence to enable CLKOUT_DP
5290  * - Sequence to enable CLKOUT_DP without spread
5291  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5292  */
5293 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5294                                  bool with_fdi)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         uint32_t reg, tmp;
5298
5299         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5300                 with_spread = true;
5301         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5302                  with_fdi, "LP PCH doesn't have FDI\n"))
5303                 with_fdi = false;
5304
5305         mutex_lock(&dev_priv->dpio_lock);
5306
5307         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5308         tmp &= ~SBI_SSCCTL_DISABLE;
5309         tmp |= SBI_SSCCTL_PATHALT;
5310         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5311
5312         udelay(24);
5313
5314         if (with_spread) {
5315                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5316                 tmp &= ~SBI_SSCCTL_PATHALT;
5317                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5318
5319                 if (with_fdi) {
5320                         lpt_reset_fdi_mphy(dev_priv);
5321                         lpt_program_fdi_mphy(dev_priv);
5322                 }
5323         }
5324
5325         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5326                SBI_GEN0 : SBI_DBUFF0;
5327         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5328         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5329         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5330
5331         mutex_unlock(&dev_priv->dpio_lock);
5332 }
5333
5334 /* Sequence to disable CLKOUT_DP */
5335 static void lpt_disable_clkout_dp(struct drm_device *dev)
5336 {
5337         struct drm_i915_private *dev_priv = dev->dev_private;
5338         uint32_t reg, tmp;
5339
5340         mutex_lock(&dev_priv->dpio_lock);
5341
5342         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5343                SBI_GEN0 : SBI_DBUFF0;
5344         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5345         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5346         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5347
5348         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5349         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5350                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5351                         tmp |= SBI_SSCCTL_PATHALT;
5352                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5353                         udelay(32);
5354                 }
5355                 tmp |= SBI_SSCCTL_DISABLE;
5356                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5357         }
5358
5359         mutex_unlock(&dev_priv->dpio_lock);
5360 }
5361
5362 static void lpt_init_pch_refclk(struct drm_device *dev)
5363 {
5364         struct drm_mode_config *mode_config = &dev->mode_config;
5365         struct intel_encoder *encoder;
5366         bool has_vga = false;
5367
5368         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5369                 switch (encoder->type) {
5370                 case INTEL_OUTPUT_ANALOG:
5371                         has_vga = true;
5372                         break;
5373                 }
5374         }
5375
5376         if (has_vga)
5377                 lpt_enable_clkout_dp(dev, true, true);
5378         else
5379                 lpt_disable_clkout_dp(dev);
5380 }
5381
5382 /*
5383  * Initialize reference clocks when the driver loads
5384  */
5385 void intel_init_pch_refclk(struct drm_device *dev)
5386 {
5387         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5388                 ironlake_init_pch_refclk(dev);
5389         else if (HAS_PCH_LPT(dev))
5390                 lpt_init_pch_refclk(dev);
5391 }
5392
5393 static int ironlake_get_refclk(struct drm_crtc *crtc)
5394 {
5395         struct drm_device *dev = crtc->dev;
5396         struct drm_i915_private *dev_priv = dev->dev_private;
5397         struct intel_encoder *encoder;
5398         int num_connectors = 0;
5399         bool is_lvds = false;
5400
5401         for_each_encoder_on_crtc(dev, crtc, encoder) {
5402                 switch (encoder->type) {
5403                 case INTEL_OUTPUT_LVDS:
5404                         is_lvds = true;
5405                         break;
5406                 }
5407                 num_connectors++;
5408         }
5409
5410         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5411                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5412                               dev_priv->vbt.lvds_ssc_freq);
5413                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5414         }
5415
5416         return 120000;
5417 }
5418
5419 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5420 {
5421         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5423         int pipe = intel_crtc->pipe;
5424         uint32_t val;
5425
5426         val = 0;
5427
5428         switch (intel_crtc->config.pipe_bpp) {
5429         case 18:
5430                 val |= PIPECONF_6BPC;
5431                 break;
5432         case 24:
5433                 val |= PIPECONF_8BPC;
5434                 break;
5435         case 30:
5436                 val |= PIPECONF_10BPC;
5437                 break;
5438         case 36:
5439                 val |= PIPECONF_12BPC;
5440                 break;
5441         default:
5442                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5443                 BUG();
5444         }
5445
5446         if (intel_crtc->config.dither)
5447                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5448
5449         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5450                 val |= PIPECONF_INTERLACED_ILK;
5451         else
5452                 val |= PIPECONF_PROGRESSIVE;
5453
5454         if (intel_crtc->config.limited_color_range)
5455                 val |= PIPECONF_COLOR_RANGE_SELECT;
5456
5457         I915_WRITE(PIPECONF(pipe), val);
5458         POSTING_READ(PIPECONF(pipe));
5459 }
5460
5461 /*
5462  * Set up the pipe CSC unit.
5463  *
5464  * Currently only full range RGB to limited range RGB conversion
5465  * is supported, but eventually this should handle various
5466  * RGB<->YCbCr scenarios as well.
5467  */
5468 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5469 {
5470         struct drm_device *dev = crtc->dev;
5471         struct drm_i915_private *dev_priv = dev->dev_private;
5472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5473         int pipe = intel_crtc->pipe;
5474         uint16_t coeff = 0x7800; /* 1.0 */
5475
5476         /*
5477          * TODO: Check what kind of values actually come out of the pipe
5478          * with these coeff/postoff values and adjust to get the best
5479          * accuracy. Perhaps we even need to take the bpc value into
5480          * consideration.
5481          */
5482
5483         if (intel_crtc->config.limited_color_range)
5484                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5485
5486         /*
5487          * GY/GU and RY/RU should be the other way around according
5488          * to BSpec, but reality doesn't agree. Just set them up in
5489          * a way that results in the correct picture.
5490          */
5491         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5492         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5493
5494         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5495         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5496
5497         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5498         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5499
5500         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5501         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5502         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5503
5504         if (INTEL_INFO(dev)->gen > 6) {
5505                 uint16_t postoff = 0;
5506
5507                 if (intel_crtc->config.limited_color_range)
5508                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5509
5510                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5511                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5512                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5513
5514                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5515         } else {
5516                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5517
5518                 if (intel_crtc->config.limited_color_range)
5519                         mode |= CSC_BLACK_SCREEN_OFFSET;
5520
5521                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5522         }
5523 }
5524
5525 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5526 {
5527         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5529         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5530         uint32_t val;
5531
5532         val = 0;
5533
5534         if (intel_crtc->config.dither)
5535                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5536
5537         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5538                 val |= PIPECONF_INTERLACED_ILK;
5539         else
5540                 val |= PIPECONF_PROGRESSIVE;
5541
5542         I915_WRITE(PIPECONF(cpu_transcoder), val);
5543         POSTING_READ(PIPECONF(cpu_transcoder));
5544
5545         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5546         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5547 }
5548
5549 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5550                                     intel_clock_t *clock,
5551                                     bool *has_reduced_clock,
5552                                     intel_clock_t *reduced_clock)
5553 {
5554         struct drm_device *dev = crtc->dev;
5555         struct drm_i915_private *dev_priv = dev->dev_private;
5556         struct intel_encoder *intel_encoder;
5557         int refclk;
5558         const intel_limit_t *limit;
5559         bool ret, is_lvds = false;
5560
5561         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5562                 switch (intel_encoder->type) {
5563                 case INTEL_OUTPUT_LVDS:
5564                         is_lvds = true;
5565                         break;
5566                 }
5567         }
5568
5569         refclk = ironlake_get_refclk(crtc);
5570
5571         /*
5572          * Returns a set of divisors for the desired target clock with the given
5573          * refclk, or FALSE.  The returned values represent the clock equation:
5574          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5575          */
5576         limit = intel_limit(crtc, refclk);
5577         ret = dev_priv->display.find_dpll(limit, crtc,
5578                                           to_intel_crtc(crtc)->config.port_clock,
5579                                           refclk, NULL, clock);
5580         if (!ret)
5581                 return false;
5582
5583         if (is_lvds && dev_priv->lvds_downclock_avail) {
5584                 /*
5585                  * Ensure we match the reduced clock's P to the target clock.
5586                  * If the clocks don't match, we can't switch the display clock
5587                  * by using the FP0/FP1. In such case we will disable the LVDS
5588                  * downclock feature.
5589                 */
5590                 *has_reduced_clock =
5591                         dev_priv->display.find_dpll(limit, crtc,
5592                                                     dev_priv->lvds_downclock,
5593                                                     refclk, clock,
5594                                                     reduced_clock);
5595         }
5596
5597         return true;
5598 }
5599
5600 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5601 {
5602         struct drm_i915_private *dev_priv = dev->dev_private;
5603         uint32_t temp;
5604
5605         temp = I915_READ(SOUTH_CHICKEN1);
5606         if (temp & FDI_BC_BIFURCATION_SELECT)
5607                 return;
5608
5609         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5610         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5611
5612         temp |= FDI_BC_BIFURCATION_SELECT;
5613         DRM_DEBUG_KMS("enabling fdi C rx\n");
5614         I915_WRITE(SOUTH_CHICKEN1, temp);
5615         POSTING_READ(SOUTH_CHICKEN1);
5616 }
5617
5618 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5619 {
5620         struct drm_device *dev = intel_crtc->base.dev;
5621         struct drm_i915_private *dev_priv = dev->dev_private;
5622
5623         switch (intel_crtc->pipe) {
5624         case PIPE_A:
5625                 break;
5626         case PIPE_B:
5627                 if (intel_crtc->config.fdi_lanes > 2)
5628                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5629                 else
5630                         cpt_enable_fdi_bc_bifurcation(dev);
5631
5632                 break;
5633         case PIPE_C:
5634                 cpt_enable_fdi_bc_bifurcation(dev);
5635
5636                 break;
5637         default:
5638                 BUG();
5639         }
5640 }
5641
5642 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5643 {
5644         /*
5645          * Account for spread spectrum to avoid
5646          * oversubscribing the link. Max center spread
5647          * is 2.5%; use 5% for safety's sake.
5648          */
5649         u32 bps = target_clock * bpp * 21 / 20;
5650         return bps / (link_bw * 8) + 1;
5651 }
5652
5653 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5654 {
5655         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5656 }
5657
5658 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5659                                       u32 *fp,
5660                                       intel_clock_t *reduced_clock, u32 *fp2)
5661 {
5662         struct drm_crtc *crtc = &intel_crtc->base;
5663         struct drm_device *dev = crtc->dev;
5664         struct drm_i915_private *dev_priv = dev->dev_private;
5665         struct intel_encoder *intel_encoder;
5666         uint32_t dpll;
5667         int factor, num_connectors = 0;
5668         bool is_lvds = false, is_sdvo = false;
5669
5670         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5671                 switch (intel_encoder->type) {
5672                 case INTEL_OUTPUT_LVDS:
5673                         is_lvds = true;
5674                         break;
5675                 case INTEL_OUTPUT_SDVO:
5676                 case INTEL_OUTPUT_HDMI:
5677                         is_sdvo = true;
5678                         break;
5679                 }
5680
5681                 num_connectors++;
5682         }
5683
5684         /* Enable autotuning of the PLL clock (if permissible) */
5685         factor = 21;
5686         if (is_lvds) {
5687                 if ((intel_panel_use_ssc(dev_priv) &&
5688                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5689                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5690                         factor = 25;
5691         } else if (intel_crtc->config.sdvo_tv_clock)
5692                 factor = 20;
5693
5694         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5695                 *fp |= FP_CB_TUNE;
5696
5697         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5698                 *fp2 |= FP_CB_TUNE;
5699
5700         dpll = 0;
5701
5702         if (is_lvds)
5703                 dpll |= DPLLB_MODE_LVDS;
5704         else
5705                 dpll |= DPLLB_MODE_DAC_SERIAL;
5706
5707         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5708                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5709
5710         if (is_sdvo)
5711                 dpll |= DPLL_SDVO_HIGH_SPEED;
5712         if (intel_crtc->config.has_dp_encoder)
5713                 dpll |= DPLL_SDVO_HIGH_SPEED;
5714
5715         /* compute bitmask from p1 value */
5716         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5717         /* also FPA1 */
5718         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5719
5720         switch (intel_crtc->config.dpll.p2) {
5721         case 5:
5722                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5723                 break;
5724         case 7:
5725                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5726                 break;
5727         case 10:
5728                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5729                 break;
5730         case 14:
5731                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5732                 break;
5733         }
5734
5735         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5736                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5737         else
5738                 dpll |= PLL_REF_INPUT_DREFCLK;
5739
5740         return dpll | DPLL_VCO_ENABLE;
5741 }
5742
5743 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5744                                   int x, int y,
5745                                   struct drm_framebuffer *fb)
5746 {
5747         struct drm_device *dev = crtc->dev;
5748         struct drm_i915_private *dev_priv = dev->dev_private;
5749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5750         int pipe = intel_crtc->pipe;
5751         int plane = intel_crtc->plane;
5752         int num_connectors = 0;
5753         intel_clock_t clock, reduced_clock;
5754         u32 dpll = 0, fp = 0, fp2 = 0;
5755         bool ok, has_reduced_clock = false;
5756         bool is_lvds = false;
5757         struct intel_encoder *encoder;
5758         struct intel_shared_dpll *pll;
5759         int ret;
5760
5761         for_each_encoder_on_crtc(dev, crtc, encoder) {
5762                 switch (encoder->type) {
5763                 case INTEL_OUTPUT_LVDS:
5764                         is_lvds = true;
5765                         break;
5766                 }
5767
5768                 num_connectors++;
5769         }
5770
5771         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5772              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5773
5774         ok = ironlake_compute_clocks(crtc, &clock,
5775                                      &has_reduced_clock, &reduced_clock);
5776         if (!ok && !intel_crtc->config.clock_set) {
5777                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5778                 return -EINVAL;
5779         }
5780         /* Compat-code for transition, will disappear. */
5781         if (!intel_crtc->config.clock_set) {
5782                 intel_crtc->config.dpll.n = clock.n;
5783                 intel_crtc->config.dpll.m1 = clock.m1;
5784                 intel_crtc->config.dpll.m2 = clock.m2;
5785                 intel_crtc->config.dpll.p1 = clock.p1;
5786                 intel_crtc->config.dpll.p2 = clock.p2;
5787         }
5788
5789         /* Ensure that the cursor is valid for the new mode before changing... */
5790         intel_crtc_update_cursor(crtc, true);
5791
5792         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5793         if (intel_crtc->config.has_pch_encoder) {
5794                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5795                 if (has_reduced_clock)
5796                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5797
5798                 dpll = ironlake_compute_dpll(intel_crtc,
5799                                              &fp, &reduced_clock,
5800                                              has_reduced_clock ? &fp2 : NULL);
5801
5802                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5803                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5804                 if (has_reduced_clock)
5805                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5806                 else
5807                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5808
5809                 pll = intel_get_shared_dpll(intel_crtc);
5810                 if (pll == NULL) {
5811                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5812                                          pipe_name(pipe));
5813                         return -EINVAL;
5814                 }
5815         } else
5816                 intel_put_shared_dpll(intel_crtc);
5817
5818         if (intel_crtc->config.has_dp_encoder)
5819                 intel_dp_set_m_n(intel_crtc);
5820
5821         if (is_lvds && has_reduced_clock && i915_powersave)
5822                 intel_crtc->lowfreq_avail = true;
5823         else
5824                 intel_crtc->lowfreq_avail = false;
5825
5826         if (intel_crtc->config.has_pch_encoder) {
5827                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5828
5829         }
5830
5831         intel_set_pipe_timings(intel_crtc);
5832
5833         if (intel_crtc->config.has_pch_encoder) {
5834                 intel_cpu_transcoder_set_m_n(intel_crtc,
5835                                              &intel_crtc->config.fdi_m_n);
5836         }
5837
5838         if (IS_IVYBRIDGE(dev))
5839                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5840
5841         ironlake_set_pipeconf(crtc);
5842
5843         /* Set up the display plane register */
5844         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5845         POSTING_READ(DSPCNTR(plane));
5846
5847         ret = intel_pipe_set_base(crtc, x, y, fb);
5848
5849         intel_update_watermarks(dev);
5850
5851         return ret;
5852 }
5853
5854 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5855                                         struct intel_crtc_config *pipe_config)
5856 {
5857         struct drm_device *dev = crtc->base.dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859         enum transcoder transcoder = pipe_config->cpu_transcoder;
5860
5861         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5862         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5863         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5864                                         & ~TU_SIZE_MASK;
5865         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5866         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5867                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5868 }
5869
5870 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5871                                      struct intel_crtc_config *pipe_config)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         uint32_t tmp;
5876
5877         tmp = I915_READ(PF_CTL(crtc->pipe));
5878
5879         if (tmp & PF_ENABLE) {
5880                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5881                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5882
5883                 /* We currently do not free assignements of panel fitters on
5884                  * ivb/hsw (since we don't use the higher upscaling modes which
5885                  * differentiates them) so just WARN about this case for now. */
5886                 if (IS_GEN7(dev)) {
5887                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5888                                 PF_PIPE_SEL_IVB(crtc->pipe));
5889                 }
5890         }
5891 }
5892
5893 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5894                                      struct intel_crtc_config *pipe_config)
5895 {
5896         struct drm_device *dev = crtc->base.dev;
5897         struct drm_i915_private *dev_priv = dev->dev_private;
5898         uint32_t tmp;
5899
5900         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5901         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5902
5903         tmp = I915_READ(PIPECONF(crtc->pipe));
5904         if (!(tmp & PIPECONF_ENABLE))
5905                 return false;
5906
5907         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5908                 struct intel_shared_dpll *pll;
5909
5910                 pipe_config->has_pch_encoder = true;
5911
5912                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5913                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5914                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5915
5916                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5917
5918                 if (HAS_PCH_IBX(dev_priv->dev)) {
5919                         pipe_config->shared_dpll =
5920                                 (enum intel_dpll_id) crtc->pipe;
5921                 } else {
5922                         tmp = I915_READ(PCH_DPLL_SEL);
5923                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5924                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5925                         else
5926                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5927                 }
5928
5929                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5930
5931                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5932                                            &pipe_config->dpll_hw_state));
5933
5934                 tmp = pipe_config->dpll_hw_state.dpll;
5935                 pipe_config->pixel_multiplier =
5936                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5937                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5938         } else {
5939                 pipe_config->pixel_multiplier = 1;
5940         }
5941
5942         intel_get_pipe_timings(crtc, pipe_config);
5943
5944         ironlake_get_pfit_config(crtc, pipe_config);
5945
5946         return true;
5947 }
5948
5949 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5950 {
5951         struct drm_device *dev = dev_priv->dev;
5952         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5953         struct intel_crtc *crtc;
5954         unsigned long irqflags;
5955         uint32_t val, pch_hpd_mask;
5956
5957         pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5958         if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5959                 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5960
5961         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5962                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5963                      pipe_name(crtc->pipe));
5964
5965         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5966         WARN(plls->spll_refcount, "SPLL enabled\n");
5967         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5968         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5969         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5970         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5971              "CPU PWM1 enabled\n");
5972         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5973              "CPU PWM2 enabled\n");
5974         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5975              "PCH PWM1 enabled\n");
5976         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5977              "Utility pin enabled\n");
5978         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5979
5980         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5981         val = I915_READ(DEIMR);
5982         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5983              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5984         val = I915_READ(SDEIMR);
5985         WARN((val & ~pch_hpd_mask) != val,
5986              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5987         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5988 }
5989
5990 /*
5991  * This function implements pieces of two sequences from BSpec:
5992  * - Sequence for display software to disable LCPLL
5993  * - Sequence for display software to allow package C8+
5994  * The steps implemented here are just the steps that actually touch the LCPLL
5995  * register. Callers should take care of disabling all the display engine
5996  * functions, doing the mode unset, fixing interrupts, etc.
5997  */
5998 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5999                        bool switch_to_fclk, bool allow_power_down)
6000 {
6001         uint32_t val;
6002
6003         assert_can_disable_lcpll(dev_priv);
6004
6005         val = I915_READ(LCPLL_CTL);
6006
6007         if (switch_to_fclk) {
6008                 val |= LCPLL_CD_SOURCE_FCLK;
6009                 I915_WRITE(LCPLL_CTL, val);
6010
6011                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6012                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6013                         DRM_ERROR("Switching to FCLK failed\n");
6014
6015                 val = I915_READ(LCPLL_CTL);
6016         }
6017
6018         val |= LCPLL_PLL_DISABLE;
6019         I915_WRITE(LCPLL_CTL, val);
6020         POSTING_READ(LCPLL_CTL);
6021
6022         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6023                 DRM_ERROR("LCPLL still locked\n");
6024
6025         val = I915_READ(D_COMP);
6026         val |= D_COMP_COMP_DISABLE;
6027         I915_WRITE(D_COMP, val);
6028         POSTING_READ(D_COMP);
6029         ndelay(100);
6030
6031         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6032                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6033
6034         if (allow_power_down) {
6035                 val = I915_READ(LCPLL_CTL);
6036                 val |= LCPLL_POWER_DOWN_ALLOW;
6037                 I915_WRITE(LCPLL_CTL, val);
6038                 POSTING_READ(LCPLL_CTL);
6039         }
6040 }
6041
6042 /*
6043  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6044  * source.
6045  */
6046 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6047 {
6048         uint32_t val;
6049
6050         val = I915_READ(LCPLL_CTL);
6051
6052         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6053                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6054                 return;
6055
6056         if (val & LCPLL_POWER_DOWN_ALLOW) {
6057                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6058                 I915_WRITE(LCPLL_CTL, val);
6059         }
6060
6061         val = I915_READ(D_COMP);
6062         val |= D_COMP_COMP_FORCE;
6063         val &= ~D_COMP_COMP_DISABLE;
6064         I915_WRITE(D_COMP, val);
6065         I915_READ(D_COMP);
6066
6067         val = I915_READ(LCPLL_CTL);
6068         val &= ~LCPLL_PLL_DISABLE;
6069         I915_WRITE(LCPLL_CTL, val);
6070
6071         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6072                 DRM_ERROR("LCPLL not locked yet\n");
6073
6074         if (val & LCPLL_CD_SOURCE_FCLK) {
6075                 val = I915_READ(LCPLL_CTL);
6076                 val &= ~LCPLL_CD_SOURCE_FCLK;
6077                 I915_WRITE(LCPLL_CTL, val);
6078
6079                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6080                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6081                         DRM_ERROR("Switching back to LCPLL failed\n");
6082         }
6083 }
6084
6085 static void haswell_modeset_global_resources(struct drm_device *dev)
6086 {
6087         bool enable = false;
6088         struct intel_crtc *crtc;
6089
6090         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6091                 if (!crtc->base.enabled)
6092                         continue;
6093
6094                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6095                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6096                         enable = true;
6097         }
6098
6099         intel_set_power_well(dev, enable);
6100 }
6101
6102 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6103                                  int x, int y,
6104                                  struct drm_framebuffer *fb)
6105 {
6106         struct drm_device *dev = crtc->dev;
6107         struct drm_i915_private *dev_priv = dev->dev_private;
6108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6109         int plane = intel_crtc->plane;
6110         int ret;
6111
6112         if (!intel_ddi_pll_mode_set(crtc))
6113                 return -EINVAL;
6114
6115         /* Ensure that the cursor is valid for the new mode before changing... */
6116         intel_crtc_update_cursor(crtc, true);
6117
6118         if (intel_crtc->config.has_dp_encoder)
6119                 intel_dp_set_m_n(intel_crtc);
6120
6121         intel_crtc->lowfreq_avail = false;
6122
6123         intel_set_pipe_timings(intel_crtc);
6124
6125         if (intel_crtc->config.has_pch_encoder) {
6126                 intel_cpu_transcoder_set_m_n(intel_crtc,
6127                                              &intel_crtc->config.fdi_m_n);
6128         }
6129
6130         haswell_set_pipeconf(crtc);
6131
6132         intel_set_pipe_csc(crtc);
6133
6134         /* Set up the display plane register */
6135         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6136         POSTING_READ(DSPCNTR(plane));
6137
6138         ret = intel_pipe_set_base(crtc, x, y, fb);
6139
6140         intel_update_watermarks(dev);
6141
6142         return ret;
6143 }
6144
6145 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6146                                     struct intel_crtc_config *pipe_config)
6147 {
6148         struct drm_device *dev = crtc->base.dev;
6149         struct drm_i915_private *dev_priv = dev->dev_private;
6150         enum intel_display_power_domain pfit_domain;
6151         uint32_t tmp;
6152
6153         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6154         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6155
6156         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6157         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6158                 enum pipe trans_edp_pipe;
6159                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6160                 default:
6161                         WARN(1, "unknown pipe linked to edp transcoder\n");
6162                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6163                 case TRANS_DDI_EDP_INPUT_A_ON:
6164                         trans_edp_pipe = PIPE_A;
6165                         break;
6166                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6167                         trans_edp_pipe = PIPE_B;
6168                         break;
6169                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6170                         trans_edp_pipe = PIPE_C;
6171                         break;
6172                 }
6173
6174                 if (trans_edp_pipe == crtc->pipe)
6175                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6176         }
6177
6178         if (!intel_display_power_enabled(dev,
6179                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6180                 return false;
6181
6182         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6183         if (!(tmp & PIPECONF_ENABLE))
6184                 return false;
6185
6186         /*
6187          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6188          * DDI E. So just check whether this pipe is wired to DDI E and whether
6189          * the PCH transcoder is on.
6190          */
6191         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6192         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6193             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6194                 pipe_config->has_pch_encoder = true;
6195
6196                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6197                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6198                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6199
6200                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6201         }
6202
6203         intel_get_pipe_timings(crtc, pipe_config);
6204
6205         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6206         if (intel_display_power_enabled(dev, pfit_domain))
6207                 ironlake_get_pfit_config(crtc, pipe_config);
6208
6209         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6210                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6211
6212         pipe_config->pixel_multiplier = 1;
6213
6214         return true;
6215 }
6216
6217 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6218                                int x, int y,
6219                                struct drm_framebuffer *fb)
6220 {
6221         struct drm_device *dev = crtc->dev;
6222         struct drm_i915_private *dev_priv = dev->dev_private;
6223         struct intel_encoder *encoder;
6224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6226         int pipe = intel_crtc->pipe;
6227         int ret;
6228
6229         drm_vblank_pre_modeset(dev, pipe);
6230
6231         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6232
6233         drm_vblank_post_modeset(dev, pipe);
6234
6235         if (ret != 0)
6236                 return ret;
6237
6238         for_each_encoder_on_crtc(dev, crtc, encoder) {
6239                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6240                         encoder->base.base.id,
6241                         drm_get_encoder_name(&encoder->base),
6242                         mode->base.id, mode->name);
6243                 encoder->mode_set(encoder);
6244         }
6245
6246         return 0;
6247 }
6248
6249 static bool intel_eld_uptodate(struct drm_connector *connector,
6250                                int reg_eldv, uint32_t bits_eldv,
6251                                int reg_elda, uint32_t bits_elda,
6252                                int reg_edid)
6253 {
6254         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6255         uint8_t *eld = connector->eld;
6256         uint32_t i;
6257
6258         i = I915_READ(reg_eldv);
6259         i &= bits_eldv;
6260
6261         if (!eld[0])
6262                 return !i;
6263
6264         if (!i)
6265                 return false;
6266
6267         i = I915_READ(reg_elda);
6268         i &= ~bits_elda;
6269         I915_WRITE(reg_elda, i);
6270
6271         for (i = 0; i < eld[2]; i++)
6272                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6273                         return false;
6274
6275         return true;
6276 }
6277
6278 static void g4x_write_eld(struct drm_connector *connector,
6279                           struct drm_crtc *crtc)
6280 {
6281         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6282         uint8_t *eld = connector->eld;
6283         uint32_t eldv;
6284         uint32_t len;
6285         uint32_t i;
6286
6287         i = I915_READ(G4X_AUD_VID_DID);
6288
6289         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6290                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6291         else
6292                 eldv = G4X_ELDV_DEVCTG;
6293
6294         if (intel_eld_uptodate(connector,
6295                                G4X_AUD_CNTL_ST, eldv,
6296                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6297                                G4X_HDMIW_HDMIEDID))
6298                 return;
6299
6300         i = I915_READ(G4X_AUD_CNTL_ST);
6301         i &= ~(eldv | G4X_ELD_ADDR);
6302         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6303         I915_WRITE(G4X_AUD_CNTL_ST, i);
6304
6305         if (!eld[0])
6306                 return;
6307
6308         len = min_t(uint8_t, eld[2], len);
6309         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6310         for (i = 0; i < len; i++)
6311                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6312
6313         i = I915_READ(G4X_AUD_CNTL_ST);
6314         i |= eldv;
6315         I915_WRITE(G4X_AUD_CNTL_ST, i);
6316 }
6317
6318 static void haswell_write_eld(struct drm_connector *connector,
6319                                      struct drm_crtc *crtc)
6320 {
6321         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6322         uint8_t *eld = connector->eld;
6323         struct drm_device *dev = crtc->dev;
6324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325         uint32_t eldv;
6326         uint32_t i;
6327         int len;
6328         int pipe = to_intel_crtc(crtc)->pipe;
6329         int tmp;
6330
6331         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6332         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6333         int aud_config = HSW_AUD_CFG(pipe);
6334         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6335
6336
6337         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6338
6339         /* Audio output enable */
6340         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6341         tmp = I915_READ(aud_cntrl_st2);
6342         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6343         I915_WRITE(aud_cntrl_st2, tmp);
6344
6345         /* Wait for 1 vertical blank */
6346         intel_wait_for_vblank(dev, pipe);
6347
6348         /* Set ELD valid state */
6349         tmp = I915_READ(aud_cntrl_st2);
6350         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6351         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6352         I915_WRITE(aud_cntrl_st2, tmp);
6353         tmp = I915_READ(aud_cntrl_st2);
6354         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6355
6356         /* Enable HDMI mode */
6357         tmp = I915_READ(aud_config);
6358         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6359         /* clear N_programing_enable and N_value_index */
6360         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6361         I915_WRITE(aud_config, tmp);
6362
6363         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6364
6365         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6366         intel_crtc->eld_vld = true;
6367
6368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6369                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6370                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6371                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6372         } else
6373                 I915_WRITE(aud_config, 0);
6374
6375         if (intel_eld_uptodate(connector,
6376                                aud_cntrl_st2, eldv,
6377                                aud_cntl_st, IBX_ELD_ADDRESS,
6378                                hdmiw_hdmiedid))
6379                 return;
6380
6381         i = I915_READ(aud_cntrl_st2);
6382         i &= ~eldv;
6383         I915_WRITE(aud_cntrl_st2, i);
6384
6385         if (!eld[0])
6386                 return;
6387
6388         i = I915_READ(aud_cntl_st);
6389         i &= ~IBX_ELD_ADDRESS;
6390         I915_WRITE(aud_cntl_st, i);
6391         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6392         DRM_DEBUG_DRIVER("port num:%d\n", i);
6393
6394         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6395         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6396         for (i = 0; i < len; i++)
6397                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6398
6399         i = I915_READ(aud_cntrl_st2);
6400         i |= eldv;
6401         I915_WRITE(aud_cntrl_st2, i);
6402
6403 }
6404
6405 static void ironlake_write_eld(struct drm_connector *connector,
6406                                      struct drm_crtc *crtc)
6407 {
6408         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6409         uint8_t *eld = connector->eld;
6410         uint32_t eldv;
6411         uint32_t i;
6412         int len;
6413         int hdmiw_hdmiedid;
6414         int aud_config;
6415         int aud_cntl_st;
6416         int aud_cntrl_st2;
6417         int pipe = to_intel_crtc(crtc)->pipe;
6418
6419         if (HAS_PCH_IBX(connector->dev)) {
6420                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6421                 aud_config = IBX_AUD_CFG(pipe);
6422                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6423                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6424         } else {
6425                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6426                 aud_config = CPT_AUD_CFG(pipe);
6427                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6428                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6429         }
6430
6431         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6432
6433         i = I915_READ(aud_cntl_st);
6434         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6435         if (!i) {
6436                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6437                 /* operate blindly on all ports */
6438                 eldv = IBX_ELD_VALIDB;
6439                 eldv |= IBX_ELD_VALIDB << 4;
6440                 eldv |= IBX_ELD_VALIDB << 8;
6441         } else {
6442                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6443                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6444         }
6445
6446         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6447                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6448                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6449                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6450         } else
6451                 I915_WRITE(aud_config, 0);
6452
6453         if (intel_eld_uptodate(connector,
6454                                aud_cntrl_st2, eldv,
6455                                aud_cntl_st, IBX_ELD_ADDRESS,
6456                                hdmiw_hdmiedid))
6457                 return;
6458
6459         i = I915_READ(aud_cntrl_st2);
6460         i &= ~eldv;
6461         I915_WRITE(aud_cntrl_st2, i);
6462
6463         if (!eld[0])
6464                 return;
6465
6466         i = I915_READ(aud_cntl_st);
6467         i &= ~IBX_ELD_ADDRESS;
6468         I915_WRITE(aud_cntl_st, i);
6469
6470         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6471         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6472         for (i = 0; i < len; i++)
6473                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6474
6475         i = I915_READ(aud_cntrl_st2);
6476         i |= eldv;
6477         I915_WRITE(aud_cntrl_st2, i);
6478 }
6479
6480 void intel_write_eld(struct drm_encoder *encoder,
6481                      struct drm_display_mode *mode)
6482 {
6483         struct drm_crtc *crtc = encoder->crtc;
6484         struct drm_connector *connector;
6485         struct drm_device *dev = encoder->dev;
6486         struct drm_i915_private *dev_priv = dev->dev_private;
6487
6488         connector = drm_select_eld(encoder, mode);
6489         if (!connector)
6490                 return;
6491
6492         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6493                          connector->base.id,
6494                          drm_get_connector_name(connector),
6495                          connector->encoder->base.id,
6496                          drm_get_encoder_name(connector->encoder));
6497
6498         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6499
6500         if (dev_priv->display.write_eld)
6501                 dev_priv->display.write_eld(connector, crtc);
6502 }
6503
6504 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6505 void intel_crtc_load_lut(struct drm_crtc *crtc)
6506 {
6507         struct drm_device *dev = crtc->dev;
6508         struct drm_i915_private *dev_priv = dev->dev_private;
6509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6510         enum pipe pipe = intel_crtc->pipe;
6511         int palreg = PALETTE(pipe);
6512         int i;
6513         bool reenable_ips = false;
6514
6515         /* The clocks have to be on to load the palette. */
6516         if (!crtc->enabled || !intel_crtc->active)
6517                 return;
6518
6519         if (!HAS_PCH_SPLIT(dev_priv->dev))
6520                 assert_pll_enabled(dev_priv, pipe);
6521
6522         /* use legacy palette for Ironlake */
6523         if (HAS_PCH_SPLIT(dev))
6524                 palreg = LGC_PALETTE(pipe);
6525
6526         /* Workaround : Do not read or write the pipe palette/gamma data while
6527          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6528          */
6529         if (intel_crtc->config.ips_enabled &&
6530             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6531              GAMMA_MODE_MODE_SPLIT)) {
6532                 hsw_disable_ips(intel_crtc);
6533                 reenable_ips = true;
6534         }
6535
6536         for (i = 0; i < 256; i++) {
6537                 I915_WRITE(palreg + 4 * i,
6538                            (intel_crtc->lut_r[i] << 16) |
6539                            (intel_crtc->lut_g[i] << 8) |
6540                            intel_crtc->lut_b[i]);
6541         }
6542
6543         if (reenable_ips)
6544                 hsw_enable_ips(intel_crtc);
6545 }
6546
6547 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6548 {
6549         struct drm_device *dev = crtc->dev;
6550         struct drm_i915_private *dev_priv = dev->dev_private;
6551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6552         bool visible = base != 0;
6553         u32 cntl;
6554
6555         if (intel_crtc->cursor_visible == visible)
6556                 return;
6557
6558         cntl = I915_READ(_CURACNTR);
6559         if (visible) {
6560                 /* On these chipsets we can only modify the base whilst
6561                  * the cursor is disabled.
6562                  */
6563                 I915_WRITE(_CURABASE, base);
6564
6565                 cntl &= ~(CURSOR_FORMAT_MASK);
6566                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6567                 cntl |= CURSOR_ENABLE |
6568                         CURSOR_GAMMA_ENABLE |
6569                         CURSOR_FORMAT_ARGB;
6570         } else
6571                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6572         I915_WRITE(_CURACNTR, cntl);
6573
6574         intel_crtc->cursor_visible = visible;
6575 }
6576
6577 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6578 {
6579         struct drm_device *dev = crtc->dev;
6580         struct drm_i915_private *dev_priv = dev->dev_private;
6581         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6582         int pipe = intel_crtc->pipe;
6583         bool visible = base != 0;
6584
6585         if (intel_crtc->cursor_visible != visible) {
6586                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6587                 if (base) {
6588                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6589                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6590                         cntl |= pipe << 28; /* Connect to correct pipe */
6591                 } else {
6592                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6593                         cntl |= CURSOR_MODE_DISABLE;
6594                 }
6595                 I915_WRITE(CURCNTR(pipe), cntl);
6596
6597                 intel_crtc->cursor_visible = visible;
6598         }
6599         /* and commit changes on next vblank */
6600         I915_WRITE(CURBASE(pipe), base);
6601 }
6602
6603 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6604 {
6605         struct drm_device *dev = crtc->dev;
6606         struct drm_i915_private *dev_priv = dev->dev_private;
6607         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6608         int pipe = intel_crtc->pipe;
6609         bool visible = base != 0;
6610
6611         if (intel_crtc->cursor_visible != visible) {
6612                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6613                 if (base) {
6614                         cntl &= ~CURSOR_MODE;
6615                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6616                 } else {
6617                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6618                         cntl |= CURSOR_MODE_DISABLE;
6619                 }
6620                 if (IS_HASWELL(dev))
6621                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6622                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6623
6624                 intel_crtc->cursor_visible = visible;
6625         }
6626         /* and commit changes on next vblank */
6627         I915_WRITE(CURBASE_IVB(pipe), base);
6628 }
6629
6630 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6631 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6632                                      bool on)
6633 {
6634         struct drm_device *dev = crtc->dev;
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6637         int pipe = intel_crtc->pipe;
6638         int x = intel_crtc->cursor_x;
6639         int y = intel_crtc->cursor_y;
6640         u32 base, pos;
6641         bool visible;
6642
6643         pos = 0;
6644
6645         if (on && crtc->enabled && crtc->fb) {
6646                 base = intel_crtc->cursor_addr;
6647                 if (x > (int) crtc->fb->width)
6648                         base = 0;
6649
6650                 if (y > (int) crtc->fb->height)
6651                         base = 0;
6652         } else
6653                 base = 0;
6654
6655         if (x < 0) {
6656                 if (x + intel_crtc->cursor_width < 0)
6657                         base = 0;
6658
6659                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6660                 x = -x;
6661         }
6662         pos |= x << CURSOR_X_SHIFT;
6663
6664         if (y < 0) {
6665                 if (y + intel_crtc->cursor_height < 0)
6666                         base = 0;
6667
6668                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6669                 y = -y;
6670         }
6671         pos |= y << CURSOR_Y_SHIFT;
6672
6673         visible = base != 0;
6674         if (!visible && !intel_crtc->cursor_visible)
6675                 return;
6676
6677         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6678                 I915_WRITE(CURPOS_IVB(pipe), pos);
6679                 ivb_update_cursor(crtc, base);
6680         } else {
6681                 I915_WRITE(CURPOS(pipe), pos);
6682                 if (IS_845G(dev) || IS_I865G(dev))
6683                         i845_update_cursor(crtc, base);
6684                 else
6685                         i9xx_update_cursor(crtc, base);
6686         }
6687 }
6688
6689 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6690                                  struct drm_file *file,
6691                                  uint32_t handle,
6692                                  uint32_t width, uint32_t height)
6693 {
6694         struct drm_device *dev = crtc->dev;
6695         struct drm_i915_private *dev_priv = dev->dev_private;
6696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697         struct drm_i915_gem_object *obj;
6698         uint32_t addr;
6699         int ret;
6700
6701         /* if we want to turn off the cursor ignore width and height */
6702         if (!handle) {
6703                 DRM_DEBUG_KMS("cursor off\n");
6704                 addr = 0;
6705                 obj = NULL;
6706                 mutex_lock(&dev->struct_mutex);
6707                 goto finish;
6708         }
6709
6710         /* Currently we only support 64x64 cursors */
6711         if (width != 64 || height != 64) {
6712                 DRM_ERROR("we currently only support 64x64 cursors\n");
6713                 return -EINVAL;
6714         }
6715
6716         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6717         if (&obj->base == NULL)
6718                 return -ENOENT;
6719
6720         if (obj->base.size < width * height * 4) {
6721                 DRM_ERROR("buffer is to small\n");
6722                 ret = -ENOMEM;
6723                 goto fail;
6724         }
6725
6726         /* we only need to pin inside GTT if cursor is non-phy */
6727         mutex_lock(&dev->struct_mutex);
6728         if (!dev_priv->info->cursor_needs_physical) {
6729                 unsigned alignment;
6730
6731                 if (obj->tiling_mode) {
6732                         DRM_ERROR("cursor cannot be tiled\n");
6733                         ret = -EINVAL;
6734                         goto fail_locked;
6735                 }
6736
6737                 /* Note that the w/a also requires 2 PTE of padding following
6738                  * the bo. We currently fill all unused PTE with the shadow
6739                  * page and so we should always have valid PTE following the
6740                  * cursor preventing the VT-d warning.
6741                  */
6742                 alignment = 0;
6743                 if (need_vtd_wa(dev))
6744                         alignment = 64*1024;
6745
6746                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6747                 if (ret) {
6748                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6749                         goto fail_locked;
6750                 }
6751
6752                 ret = i915_gem_object_put_fence(obj);
6753                 if (ret) {
6754                         DRM_ERROR("failed to release fence for cursor");
6755                         goto fail_unpin;
6756                 }
6757
6758                 addr = i915_gem_obj_ggtt_offset(obj);
6759         } else {
6760                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6761                 ret = i915_gem_attach_phys_object(dev, obj,
6762                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6763                                                   align);
6764                 if (ret) {
6765                         DRM_ERROR("failed to attach phys object\n");
6766                         goto fail_locked;
6767                 }
6768                 addr = obj->phys_obj->handle->busaddr;
6769         }
6770
6771         if (IS_GEN2(dev))
6772                 I915_WRITE(CURSIZE, (height << 12) | width);
6773
6774  finish:
6775         if (intel_crtc->cursor_bo) {
6776                 if (dev_priv->info->cursor_needs_physical) {
6777                         if (intel_crtc->cursor_bo != obj)
6778                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6779                 } else
6780                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6781                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6782         }
6783
6784         mutex_unlock(&dev->struct_mutex);
6785
6786         intel_crtc->cursor_addr = addr;
6787         intel_crtc->cursor_bo = obj;
6788         intel_crtc->cursor_width = width;
6789         intel_crtc->cursor_height = height;
6790
6791         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6792
6793         return 0;
6794 fail_unpin:
6795         i915_gem_object_unpin(obj);
6796 fail_locked:
6797         mutex_unlock(&dev->struct_mutex);
6798 fail:
6799         drm_gem_object_unreference_unlocked(&obj->base);
6800         return ret;
6801 }
6802
6803 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6804 {
6805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6806
6807         intel_crtc->cursor_x = x;
6808         intel_crtc->cursor_y = y;
6809
6810         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6811
6812         return 0;
6813 }
6814
6815 /** Sets the color ramps on behalf of RandR */
6816 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6817                                  u16 blue, int regno)
6818 {
6819         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6820
6821         intel_crtc->lut_r[regno] = red >> 8;
6822         intel_crtc->lut_g[regno] = green >> 8;
6823         intel_crtc->lut_b[regno] = blue >> 8;
6824 }
6825
6826 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6827                              u16 *blue, int regno)
6828 {
6829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6830
6831         *red = intel_crtc->lut_r[regno] << 8;
6832         *green = intel_crtc->lut_g[regno] << 8;
6833         *blue = intel_crtc->lut_b[regno] << 8;
6834 }
6835
6836 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6837                                  u16 *blue, uint32_t start, uint32_t size)
6838 {
6839         int end = (start + size > 256) ? 256 : start + size, i;
6840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841
6842         for (i = start; i < end; i++) {
6843                 intel_crtc->lut_r[i] = red[i] >> 8;
6844                 intel_crtc->lut_g[i] = green[i] >> 8;
6845                 intel_crtc->lut_b[i] = blue[i] >> 8;
6846         }
6847
6848         intel_crtc_load_lut(crtc);
6849 }
6850
6851 /* VESA 640x480x72Hz mode to set on the pipe */
6852 static struct drm_display_mode load_detect_mode = {
6853         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6854                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6855 };
6856
6857 static struct drm_framebuffer *
6858 intel_framebuffer_create(struct drm_device *dev,
6859                          struct drm_mode_fb_cmd2 *mode_cmd,
6860                          struct drm_i915_gem_object *obj)
6861 {
6862         struct intel_framebuffer *intel_fb;
6863         int ret;
6864
6865         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6866         if (!intel_fb) {
6867                 drm_gem_object_unreference_unlocked(&obj->base);
6868                 return ERR_PTR(-ENOMEM);
6869         }
6870
6871         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6872         if (ret) {
6873                 drm_gem_object_unreference_unlocked(&obj->base);
6874                 kfree(intel_fb);
6875                 return ERR_PTR(ret);
6876         }
6877
6878         return &intel_fb->base;
6879 }
6880
6881 static u32
6882 intel_framebuffer_pitch_for_width(int width, int bpp)
6883 {
6884         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6885         return ALIGN(pitch, 64);
6886 }
6887
6888 static u32
6889 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6890 {
6891         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6892         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6893 }
6894
6895 static struct drm_framebuffer *
6896 intel_framebuffer_create_for_mode(struct drm_device *dev,
6897                                   struct drm_display_mode *mode,
6898                                   int depth, int bpp)
6899 {
6900         struct drm_i915_gem_object *obj;
6901         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6902
6903         obj = i915_gem_alloc_object(dev,
6904                                     intel_framebuffer_size_for_mode(mode, bpp));
6905         if (obj == NULL)
6906                 return ERR_PTR(-ENOMEM);
6907
6908         mode_cmd.width = mode->hdisplay;
6909         mode_cmd.height = mode->vdisplay;
6910         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6911                                                                 bpp);
6912         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6913
6914         return intel_framebuffer_create(dev, &mode_cmd, obj);
6915 }
6916
6917 static struct drm_framebuffer *
6918 mode_fits_in_fbdev(struct drm_device *dev,
6919                    struct drm_display_mode *mode)
6920 {
6921         struct drm_i915_private *dev_priv = dev->dev_private;
6922         struct drm_i915_gem_object *obj;
6923         struct drm_framebuffer *fb;
6924
6925         if (dev_priv->fbdev == NULL)
6926                 return NULL;
6927
6928         obj = dev_priv->fbdev->ifb.obj;
6929         if (obj == NULL)
6930                 return NULL;
6931
6932         fb = &dev_priv->fbdev->ifb.base;
6933         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6934                                                                fb->bits_per_pixel))
6935                 return NULL;
6936
6937         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6938                 return NULL;
6939
6940         return fb;
6941 }
6942
6943 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6944                                 struct drm_display_mode *mode,
6945                                 struct intel_load_detect_pipe *old)
6946 {
6947         struct intel_crtc *intel_crtc;
6948         struct intel_encoder *intel_encoder =
6949                 intel_attached_encoder(connector);
6950         struct drm_crtc *possible_crtc;
6951         struct drm_encoder *encoder = &intel_encoder->base;
6952         struct drm_crtc *crtc = NULL;
6953         struct drm_device *dev = encoder->dev;
6954         struct drm_framebuffer *fb;
6955         int i = -1;
6956
6957         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6958                       connector->base.id, drm_get_connector_name(connector),
6959                       encoder->base.id, drm_get_encoder_name(encoder));
6960
6961         /*
6962          * Algorithm gets a little messy:
6963          *
6964          *   - if the connector already has an assigned crtc, use it (but make
6965          *     sure it's on first)
6966          *
6967          *   - try to find the first unused crtc that can drive this connector,
6968          *     and use that if we find one
6969          */
6970
6971         /* See if we already have a CRTC for this connector */
6972         if (encoder->crtc) {
6973                 crtc = encoder->crtc;
6974
6975                 mutex_lock(&crtc->mutex);
6976
6977                 old->dpms_mode = connector->dpms;
6978                 old->load_detect_temp = false;
6979
6980                 /* Make sure the crtc and connector are running */
6981                 if (connector->dpms != DRM_MODE_DPMS_ON)
6982                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6983
6984                 return true;
6985         }
6986
6987         /* Find an unused one (if possible) */
6988         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6989                 i++;
6990                 if (!(encoder->possible_crtcs & (1 << i)))
6991                         continue;
6992                 if (!possible_crtc->enabled) {
6993                         crtc = possible_crtc;
6994                         break;
6995                 }
6996         }
6997
6998         /*
6999          * If we didn't find an unused CRTC, don't use any.
7000          */
7001         if (!crtc) {
7002                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7003                 return false;
7004         }
7005
7006         mutex_lock(&crtc->mutex);
7007         intel_encoder->new_crtc = to_intel_crtc(crtc);
7008         to_intel_connector(connector)->new_encoder = intel_encoder;
7009
7010         intel_crtc = to_intel_crtc(crtc);
7011         old->dpms_mode = connector->dpms;
7012         old->load_detect_temp = true;
7013         old->release_fb = NULL;
7014
7015         if (!mode)
7016                 mode = &load_detect_mode;
7017
7018         /* We need a framebuffer large enough to accommodate all accesses
7019          * that the plane may generate whilst we perform load detection.
7020          * We can not rely on the fbcon either being present (we get called
7021          * during its initialisation to detect all boot displays, or it may
7022          * not even exist) or that it is large enough to satisfy the
7023          * requested mode.
7024          */
7025         fb = mode_fits_in_fbdev(dev, mode);
7026         if (fb == NULL) {
7027                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7028                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7029                 old->release_fb = fb;
7030         } else
7031                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7032         if (IS_ERR(fb)) {
7033                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7034                 mutex_unlock(&crtc->mutex);
7035                 return false;
7036         }
7037
7038         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7039                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7040                 if (old->release_fb)
7041                         old->release_fb->funcs->destroy(old->release_fb);
7042                 mutex_unlock(&crtc->mutex);
7043                 return false;
7044         }
7045
7046         /* let the connector get through one full cycle before testing */
7047         intel_wait_for_vblank(dev, intel_crtc->pipe);
7048         return true;
7049 }
7050
7051 void intel_release_load_detect_pipe(struct drm_connector *connector,
7052                                     struct intel_load_detect_pipe *old)
7053 {
7054         struct intel_encoder *intel_encoder =
7055                 intel_attached_encoder(connector);
7056         struct drm_encoder *encoder = &intel_encoder->base;
7057         struct drm_crtc *crtc = encoder->crtc;
7058
7059         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7060                       connector->base.id, drm_get_connector_name(connector),
7061                       encoder->base.id, drm_get_encoder_name(encoder));
7062
7063         if (old->load_detect_temp) {
7064                 to_intel_connector(connector)->new_encoder = NULL;
7065                 intel_encoder->new_crtc = NULL;
7066                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7067
7068                 if (old->release_fb) {
7069                         drm_framebuffer_unregister_private(old->release_fb);
7070                         drm_framebuffer_unreference(old->release_fb);
7071                 }
7072
7073                 mutex_unlock(&crtc->mutex);
7074                 return;
7075         }
7076
7077         /* Switch crtc and encoder back off if necessary */
7078         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7079                 connector->funcs->dpms(connector, old->dpms_mode);
7080
7081         mutex_unlock(&crtc->mutex);
7082 }
7083
7084 /* Returns the clock of the currently programmed mode of the given pipe. */
7085 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7086                                 struct intel_crtc_config *pipe_config)
7087 {
7088         struct drm_device *dev = crtc->base.dev;
7089         struct drm_i915_private *dev_priv = dev->dev_private;
7090         int pipe = pipe_config->cpu_transcoder;
7091         u32 dpll = I915_READ(DPLL(pipe));
7092         u32 fp;
7093         intel_clock_t clock;
7094
7095         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7096                 fp = I915_READ(FP0(pipe));
7097         else
7098                 fp = I915_READ(FP1(pipe));
7099
7100         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7101         if (IS_PINEVIEW(dev)) {
7102                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7103                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7104         } else {
7105                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7106                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7107         }
7108
7109         if (!IS_GEN2(dev)) {
7110                 if (IS_PINEVIEW(dev))
7111                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7112                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7113                 else
7114                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7115                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7116
7117                 switch (dpll & DPLL_MODE_MASK) {
7118                 case DPLLB_MODE_DAC_SERIAL:
7119                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7120                                 5 : 10;
7121                         break;
7122                 case DPLLB_MODE_LVDS:
7123                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7124                                 7 : 14;
7125                         break;
7126                 default:
7127                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7128                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7129                         pipe_config->adjusted_mode.clock = 0;
7130                         return;
7131                 }
7132
7133                 if (IS_PINEVIEW(dev))
7134                         pineview_clock(96000, &clock);
7135                 else
7136                         i9xx_clock(96000, &clock);
7137         } else {
7138                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7139
7140                 if (is_lvds) {
7141                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7142                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7143                         clock.p2 = 14;
7144
7145                         if ((dpll & PLL_REF_INPUT_MASK) ==
7146                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7147                                 /* XXX: might not be 66MHz */
7148                                 i9xx_clock(66000, &clock);
7149                         } else
7150                                 i9xx_clock(48000, &clock);
7151                 } else {
7152                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7153                                 clock.p1 = 2;
7154                         else {
7155                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7156                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7157                         }
7158                         if (dpll & PLL_P2_DIVIDE_BY_4)
7159                                 clock.p2 = 4;
7160                         else
7161                                 clock.p2 = 2;
7162
7163                         i9xx_clock(48000, &clock);
7164                 }
7165         }
7166
7167         pipe_config->adjusted_mode.clock = clock.dot *
7168                 pipe_config->pixel_multiplier;
7169 }
7170
7171 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7172                                     struct intel_crtc_config *pipe_config)
7173 {
7174         struct drm_device *dev = crtc->base.dev;
7175         struct drm_i915_private *dev_priv = dev->dev_private;
7176         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7177         int link_freq, repeat;
7178         u64 clock;
7179         u32 link_m, link_n;
7180
7181         repeat = pipe_config->pixel_multiplier;
7182
7183         /*
7184          * The calculation for the data clock is:
7185          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7186          * But we want to avoid losing precison if possible, so:
7187          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7188          *
7189          * and the link clock is simpler:
7190          * link_clock = (m * link_clock * repeat) / n
7191          */
7192
7193         /*
7194          * We need to get the FDI or DP link clock here to derive
7195          * the M/N dividers.
7196          *
7197          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7198          * For DP, it's either 1.62GHz or 2.7GHz.
7199          * We do our calculations in 10*MHz since we don't need much precison.
7200          */
7201         if (pipe_config->has_pch_encoder)
7202                 link_freq = intel_fdi_link_freq(dev) * 10000;
7203         else
7204                 link_freq = pipe_config->port_clock;
7205
7206         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7207         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7208
7209         if (!link_m || !link_n)
7210                 return;
7211
7212         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7213         do_div(clock, link_n);
7214
7215         pipe_config->adjusted_mode.clock = clock;
7216 }
7217
7218 /** Returns the currently programmed mode of the given pipe. */
7219 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7220                                              struct drm_crtc *crtc)
7221 {
7222         struct drm_i915_private *dev_priv = dev->dev_private;
7223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7224         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7225         struct drm_display_mode *mode;
7226         struct intel_crtc_config pipe_config;
7227         int htot = I915_READ(HTOTAL(cpu_transcoder));
7228         int hsync = I915_READ(HSYNC(cpu_transcoder));
7229         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7230         int vsync = I915_READ(VSYNC(cpu_transcoder));
7231
7232         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7233         if (!mode)
7234                 return NULL;
7235
7236         /*
7237          * Construct a pipe_config sufficient for getting the clock info
7238          * back out of crtc_clock_get.
7239          *
7240          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7241          * to use a real value here instead.
7242          */
7243         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7244         pipe_config.pixel_multiplier = 1;
7245         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7246
7247         mode->clock = pipe_config.adjusted_mode.clock;
7248         mode->hdisplay = (htot & 0xffff) + 1;
7249         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7250         mode->hsync_start = (hsync & 0xffff) + 1;
7251         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7252         mode->vdisplay = (vtot & 0xffff) + 1;
7253         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7254         mode->vsync_start = (vsync & 0xffff) + 1;
7255         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7256
7257         drm_mode_set_name(mode);
7258
7259         return mode;
7260 }
7261
7262 static void intel_increase_pllclock(struct drm_crtc *crtc)
7263 {
7264         struct drm_device *dev = crtc->dev;
7265         drm_i915_private_t *dev_priv = dev->dev_private;
7266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7267         int pipe = intel_crtc->pipe;
7268         int dpll_reg = DPLL(pipe);
7269         int dpll;
7270
7271         if (HAS_PCH_SPLIT(dev))
7272                 return;
7273
7274         if (!dev_priv->lvds_downclock_avail)
7275                 return;
7276
7277         dpll = I915_READ(dpll_reg);
7278         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7279                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7280
7281                 assert_panel_unlocked(dev_priv, pipe);
7282
7283                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7284                 I915_WRITE(dpll_reg, dpll);
7285                 intel_wait_for_vblank(dev, pipe);
7286
7287                 dpll = I915_READ(dpll_reg);
7288                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7289                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7290         }
7291 }
7292
7293 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7294 {
7295         struct drm_device *dev = crtc->dev;
7296         drm_i915_private_t *dev_priv = dev->dev_private;
7297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7298
7299         if (HAS_PCH_SPLIT(dev))
7300                 return;
7301
7302         if (!dev_priv->lvds_downclock_avail)
7303                 return;
7304
7305         /*
7306          * Since this is called by a timer, we should never get here in
7307          * the manual case.
7308          */
7309         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7310                 int pipe = intel_crtc->pipe;
7311                 int dpll_reg = DPLL(pipe);
7312                 int dpll;
7313
7314                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7315
7316                 assert_panel_unlocked(dev_priv, pipe);
7317
7318                 dpll = I915_READ(dpll_reg);
7319                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7320                 I915_WRITE(dpll_reg, dpll);
7321                 intel_wait_for_vblank(dev, pipe);
7322                 dpll = I915_READ(dpll_reg);
7323                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7324                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7325         }
7326
7327 }
7328
7329 void intel_mark_busy(struct drm_device *dev)
7330 {
7331         i915_update_gfx_val(dev->dev_private);
7332 }
7333
7334 void intel_mark_idle(struct drm_device *dev)
7335 {
7336         struct drm_crtc *crtc;
7337
7338         if (!i915_powersave)
7339                 return;
7340
7341         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7342                 if (!crtc->fb)
7343                         continue;
7344
7345                 intel_decrease_pllclock(crtc);
7346         }
7347 }
7348
7349 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7350                         struct intel_ring_buffer *ring)
7351 {
7352         struct drm_device *dev = obj->base.dev;
7353         struct drm_crtc *crtc;
7354
7355         if (!i915_powersave)
7356                 return;
7357
7358         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7359                 if (!crtc->fb)
7360                         continue;
7361
7362                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7363                         continue;
7364
7365                 intel_increase_pllclock(crtc);
7366                 if (ring && intel_fbc_enabled(dev))
7367                         ring->fbc_dirty = true;
7368         }
7369 }
7370
7371 static void intel_crtc_destroy(struct drm_crtc *crtc)
7372 {
7373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7374         struct drm_device *dev = crtc->dev;
7375         struct intel_unpin_work *work;
7376         unsigned long flags;
7377
7378         spin_lock_irqsave(&dev->event_lock, flags);
7379         work = intel_crtc->unpin_work;
7380         intel_crtc->unpin_work = NULL;
7381         spin_unlock_irqrestore(&dev->event_lock, flags);
7382
7383         if (work) {
7384                 cancel_work_sync(&work->work);
7385                 kfree(work);
7386         }
7387
7388         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7389
7390         drm_crtc_cleanup(crtc);
7391
7392         kfree(intel_crtc);
7393 }
7394
7395 static void intel_unpin_work_fn(struct work_struct *__work)
7396 {
7397         struct intel_unpin_work *work =
7398                 container_of(__work, struct intel_unpin_work, work);
7399         struct drm_device *dev = work->crtc->dev;
7400
7401         mutex_lock(&dev->struct_mutex);
7402         intel_unpin_fb_obj(work->old_fb_obj);
7403         drm_gem_object_unreference(&work->pending_flip_obj->base);
7404         drm_gem_object_unreference(&work->old_fb_obj->base);
7405
7406         intel_update_fbc(dev);
7407         mutex_unlock(&dev->struct_mutex);
7408
7409         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7410         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7411
7412         kfree(work);
7413 }
7414
7415 static void do_intel_finish_page_flip(struct drm_device *dev,
7416                                       struct drm_crtc *crtc)
7417 {
7418         drm_i915_private_t *dev_priv = dev->dev_private;
7419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7420         struct intel_unpin_work *work;
7421         unsigned long flags;
7422
7423         /* Ignore early vblank irqs */
7424         if (intel_crtc == NULL)
7425                 return;
7426
7427         spin_lock_irqsave(&dev->event_lock, flags);
7428         work = intel_crtc->unpin_work;
7429
7430         /* Ensure we don't miss a work->pending update ... */
7431         smp_rmb();
7432
7433         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7434                 spin_unlock_irqrestore(&dev->event_lock, flags);
7435                 return;
7436         }
7437
7438         /* and that the unpin work is consistent wrt ->pending. */
7439         smp_rmb();
7440
7441         intel_crtc->unpin_work = NULL;
7442
7443         if (work->event)
7444                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7445
7446         drm_vblank_put(dev, intel_crtc->pipe);
7447
7448         spin_unlock_irqrestore(&dev->event_lock, flags);
7449
7450         wake_up_all(&dev_priv->pending_flip_queue);
7451
7452         queue_work(dev_priv->wq, &work->work);
7453
7454         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7455 }
7456
7457 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7458 {
7459         drm_i915_private_t *dev_priv = dev->dev_private;
7460         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7461
7462         do_intel_finish_page_flip(dev, crtc);
7463 }
7464
7465 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7466 {
7467         drm_i915_private_t *dev_priv = dev->dev_private;
7468         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7469
7470         do_intel_finish_page_flip(dev, crtc);
7471 }
7472
7473 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7474 {
7475         drm_i915_private_t *dev_priv = dev->dev_private;
7476         struct intel_crtc *intel_crtc =
7477                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7478         unsigned long flags;
7479
7480         /* NB: An MMIO update of the plane base pointer will also
7481          * generate a page-flip completion irq, i.e. every modeset
7482          * is also accompanied by a spurious intel_prepare_page_flip().
7483          */
7484         spin_lock_irqsave(&dev->event_lock, flags);
7485         if (intel_crtc->unpin_work)
7486                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7487         spin_unlock_irqrestore(&dev->event_lock, flags);
7488 }
7489
7490 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7491 {
7492         /* Ensure that the work item is consistent when activating it ... */
7493         smp_wmb();
7494         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7495         /* and that it is marked active as soon as the irq could fire. */
7496         smp_wmb();
7497 }
7498
7499 static int intel_gen2_queue_flip(struct drm_device *dev,
7500                                  struct drm_crtc *crtc,
7501                                  struct drm_framebuffer *fb,
7502                                  struct drm_i915_gem_object *obj)
7503 {
7504         struct drm_i915_private *dev_priv = dev->dev_private;
7505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7506         u32 flip_mask;
7507         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7508         int ret;
7509
7510         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7511         if (ret)
7512                 goto err;
7513
7514         ret = intel_ring_begin(ring, 6);
7515         if (ret)
7516                 goto err_unpin;
7517
7518         /* Can't queue multiple flips, so wait for the previous
7519          * one to finish before executing the next.
7520          */
7521         if (intel_crtc->plane)
7522                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7523         else
7524                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7525         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7526         intel_ring_emit(ring, MI_NOOP);
7527         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7528                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7529         intel_ring_emit(ring, fb->pitches[0]);
7530         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7531         intel_ring_emit(ring, 0); /* aux display base address, unused */
7532
7533         intel_mark_page_flip_active(intel_crtc);
7534         intel_ring_advance(ring);
7535         return 0;
7536
7537 err_unpin:
7538         intel_unpin_fb_obj(obj);
7539 err:
7540         return ret;
7541 }
7542
7543 static int intel_gen3_queue_flip(struct drm_device *dev,
7544                                  struct drm_crtc *crtc,
7545                                  struct drm_framebuffer *fb,
7546                                  struct drm_i915_gem_object *obj)
7547 {
7548         struct drm_i915_private *dev_priv = dev->dev_private;
7549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7550         u32 flip_mask;
7551         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7552         int ret;
7553
7554         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7555         if (ret)
7556                 goto err;
7557
7558         ret = intel_ring_begin(ring, 6);
7559         if (ret)
7560                 goto err_unpin;
7561
7562         if (intel_crtc->plane)
7563                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7564         else
7565                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7566         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7567         intel_ring_emit(ring, MI_NOOP);
7568         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7569                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7570         intel_ring_emit(ring, fb->pitches[0]);
7571         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7572         intel_ring_emit(ring, MI_NOOP);
7573
7574         intel_mark_page_flip_active(intel_crtc);
7575         intel_ring_advance(ring);
7576         return 0;
7577
7578 err_unpin:
7579         intel_unpin_fb_obj(obj);
7580 err:
7581         return ret;
7582 }
7583
7584 static int intel_gen4_queue_flip(struct drm_device *dev,
7585                                  struct drm_crtc *crtc,
7586                                  struct drm_framebuffer *fb,
7587                                  struct drm_i915_gem_object *obj)
7588 {
7589         struct drm_i915_private *dev_priv = dev->dev_private;
7590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7591         uint32_t pf, pipesrc;
7592         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7593         int ret;
7594
7595         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7596         if (ret)
7597                 goto err;
7598
7599         ret = intel_ring_begin(ring, 4);
7600         if (ret)
7601                 goto err_unpin;
7602
7603         /* i965+ uses the linear or tiled offsets from the
7604          * Display Registers (which do not change across a page-flip)
7605          * so we need only reprogram the base address.
7606          */
7607         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7608                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7609         intel_ring_emit(ring, fb->pitches[0]);
7610         intel_ring_emit(ring,
7611                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7612                         obj->tiling_mode);
7613
7614         /* XXX Enabling the panel-fitter across page-flip is so far
7615          * untested on non-native modes, so ignore it for now.
7616          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7617          */
7618         pf = 0;
7619         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7620         intel_ring_emit(ring, pf | pipesrc);
7621
7622         intel_mark_page_flip_active(intel_crtc);
7623         intel_ring_advance(ring);
7624         return 0;
7625
7626 err_unpin:
7627         intel_unpin_fb_obj(obj);
7628 err:
7629         return ret;
7630 }
7631
7632 static int intel_gen6_queue_flip(struct drm_device *dev,
7633                                  struct drm_crtc *crtc,
7634                                  struct drm_framebuffer *fb,
7635                                  struct drm_i915_gem_object *obj)
7636 {
7637         struct drm_i915_private *dev_priv = dev->dev_private;
7638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7639         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7640         uint32_t pf, pipesrc;
7641         int ret;
7642
7643         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7644         if (ret)
7645                 goto err;
7646
7647         ret = intel_ring_begin(ring, 4);
7648         if (ret)
7649                 goto err_unpin;
7650
7651         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7652                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7653         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7654         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7655
7656         /* Contrary to the suggestions in the documentation,
7657          * "Enable Panel Fitter" does not seem to be required when page
7658          * flipping with a non-native mode, and worse causes a normal
7659          * modeset to fail.
7660          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7661          */
7662         pf = 0;
7663         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7664         intel_ring_emit(ring, pf | pipesrc);
7665
7666         intel_mark_page_flip_active(intel_crtc);
7667         intel_ring_advance(ring);
7668         return 0;
7669
7670 err_unpin:
7671         intel_unpin_fb_obj(obj);
7672 err:
7673         return ret;
7674 }
7675
7676 /*
7677  * On gen7 we currently use the blit ring because (in early silicon at least)
7678  * the render ring doesn't give us interrpts for page flip completion, which
7679  * means clients will hang after the first flip is queued.  Fortunately the
7680  * blit ring generates interrupts properly, so use it instead.
7681  */
7682 static int intel_gen7_queue_flip(struct drm_device *dev,
7683                                  struct drm_crtc *crtc,
7684                                  struct drm_framebuffer *fb,
7685                                  struct drm_i915_gem_object *obj)
7686 {
7687         struct drm_i915_private *dev_priv = dev->dev_private;
7688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7689         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7690         uint32_t plane_bit = 0;
7691         int ret;
7692
7693         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7694         if (ret)
7695                 goto err;
7696
7697         switch(intel_crtc->plane) {
7698         case PLANE_A:
7699                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7700                 break;
7701         case PLANE_B:
7702                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7703                 break;
7704         case PLANE_C:
7705                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7706                 break;
7707         default:
7708                 WARN_ONCE(1, "unknown plane in flip command\n");
7709                 ret = -ENODEV;
7710                 goto err_unpin;
7711         }
7712
7713         ret = intel_ring_begin(ring, 4);
7714         if (ret)
7715                 goto err_unpin;
7716
7717         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7718         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7719         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7720         intel_ring_emit(ring, (MI_NOOP));
7721
7722         intel_mark_page_flip_active(intel_crtc);
7723         intel_ring_advance(ring);
7724         return 0;
7725
7726 err_unpin:
7727         intel_unpin_fb_obj(obj);
7728 err:
7729         return ret;
7730 }
7731
7732 static int intel_default_queue_flip(struct drm_device *dev,
7733                                     struct drm_crtc *crtc,
7734                                     struct drm_framebuffer *fb,
7735                                     struct drm_i915_gem_object *obj)
7736 {
7737         return -ENODEV;
7738 }
7739
7740 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7741                                 struct drm_framebuffer *fb,
7742                                 struct drm_pending_vblank_event *event)
7743 {
7744         struct drm_device *dev = crtc->dev;
7745         struct drm_i915_private *dev_priv = dev->dev_private;
7746         struct drm_framebuffer *old_fb = crtc->fb;
7747         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7748         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7749         struct intel_unpin_work *work;
7750         unsigned long flags;
7751         int ret;
7752
7753         /* Can't change pixel format via MI display flips. */
7754         if (fb->pixel_format != crtc->fb->pixel_format)
7755                 return -EINVAL;
7756
7757         /*
7758          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7759          * Note that pitch changes could also affect these register.
7760          */
7761         if (INTEL_INFO(dev)->gen > 3 &&
7762             (fb->offsets[0] != crtc->fb->offsets[0] ||
7763              fb->pitches[0] != crtc->fb->pitches[0]))
7764                 return -EINVAL;
7765
7766         work = kzalloc(sizeof *work, GFP_KERNEL);
7767         if (work == NULL)
7768                 return -ENOMEM;
7769
7770         work->event = event;
7771         work->crtc = crtc;
7772         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7773         INIT_WORK(&work->work, intel_unpin_work_fn);
7774
7775         ret = drm_vblank_get(dev, intel_crtc->pipe);
7776         if (ret)
7777                 goto free_work;
7778
7779         /* We borrow the event spin lock for protecting unpin_work */
7780         spin_lock_irqsave(&dev->event_lock, flags);
7781         if (intel_crtc->unpin_work) {
7782                 spin_unlock_irqrestore(&dev->event_lock, flags);
7783                 kfree(work);
7784                 drm_vblank_put(dev, intel_crtc->pipe);
7785
7786                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7787                 return -EBUSY;
7788         }
7789         intel_crtc->unpin_work = work;
7790         spin_unlock_irqrestore(&dev->event_lock, flags);
7791
7792         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7793                 flush_workqueue(dev_priv->wq);
7794
7795         ret = i915_mutex_lock_interruptible(dev);
7796         if (ret)
7797                 goto cleanup;
7798
7799         /* Reference the objects for the scheduled work. */
7800         drm_gem_object_reference(&work->old_fb_obj->base);
7801         drm_gem_object_reference(&obj->base);
7802
7803         crtc->fb = fb;
7804
7805         work->pending_flip_obj = obj;
7806
7807         work->enable_stall_check = true;
7808
7809         atomic_inc(&intel_crtc->unpin_work_count);
7810         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7811
7812         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7813         if (ret)
7814                 goto cleanup_pending;
7815
7816         intel_disable_fbc(dev);
7817         intel_mark_fb_busy(obj, NULL);
7818         mutex_unlock(&dev->struct_mutex);
7819
7820         trace_i915_flip_request(intel_crtc->plane, obj);
7821
7822         return 0;
7823
7824 cleanup_pending:
7825         atomic_dec(&intel_crtc->unpin_work_count);
7826         crtc->fb = old_fb;
7827         drm_gem_object_unreference(&work->old_fb_obj->base);
7828         drm_gem_object_unreference(&obj->base);
7829         mutex_unlock(&dev->struct_mutex);
7830
7831 cleanup:
7832         spin_lock_irqsave(&dev->event_lock, flags);
7833         intel_crtc->unpin_work = NULL;
7834         spin_unlock_irqrestore(&dev->event_lock, flags);
7835
7836         drm_vblank_put(dev, intel_crtc->pipe);
7837 free_work:
7838         kfree(work);
7839
7840         return ret;
7841 }
7842
7843 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7844         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7845         .load_lut = intel_crtc_load_lut,
7846 };
7847
7848 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7849                                   struct drm_crtc *crtc)
7850 {
7851         struct drm_device *dev;
7852         struct drm_crtc *tmp;
7853         int crtc_mask = 1;
7854
7855         WARN(!crtc, "checking null crtc?\n");
7856
7857         dev = crtc->dev;
7858
7859         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7860                 if (tmp == crtc)
7861                         break;
7862                 crtc_mask <<= 1;
7863         }
7864
7865         if (encoder->possible_crtcs & crtc_mask)
7866                 return true;
7867         return false;
7868 }
7869
7870 /**
7871  * intel_modeset_update_staged_output_state
7872  *
7873  * Updates the staged output configuration state, e.g. after we've read out the
7874  * current hw state.
7875  */
7876 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7877 {
7878         struct intel_encoder *encoder;
7879         struct intel_connector *connector;
7880
7881         list_for_each_entry(connector, &dev->mode_config.connector_list,
7882                             base.head) {
7883                 connector->new_encoder =
7884                         to_intel_encoder(connector->base.encoder);
7885         }
7886
7887         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7888                             base.head) {
7889                 encoder->new_crtc =
7890                         to_intel_crtc(encoder->base.crtc);
7891         }
7892 }
7893
7894 /**
7895  * intel_modeset_commit_output_state
7896  *
7897  * This function copies the stage display pipe configuration to the real one.
7898  */
7899 static void intel_modeset_commit_output_state(struct drm_device *dev)
7900 {
7901         struct intel_encoder *encoder;
7902         struct intel_connector *connector;
7903
7904         list_for_each_entry(connector, &dev->mode_config.connector_list,
7905                             base.head) {
7906                 connector->base.encoder = &connector->new_encoder->base;
7907         }
7908
7909         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7910                             base.head) {
7911                 encoder->base.crtc = &encoder->new_crtc->base;
7912         }
7913 }
7914
7915 static void
7916 connected_sink_compute_bpp(struct intel_connector * connector,
7917                            struct intel_crtc_config *pipe_config)
7918 {
7919         int bpp = pipe_config->pipe_bpp;
7920
7921         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7922                 connector->base.base.id,
7923                 drm_get_connector_name(&connector->base));
7924
7925         /* Don't use an invalid EDID bpc value */
7926         if (connector->base.display_info.bpc &&
7927             connector->base.display_info.bpc * 3 < bpp) {
7928                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7929                               bpp, connector->base.display_info.bpc*3);
7930                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7931         }
7932
7933         /* Clamp bpp to 8 on screens without EDID 1.4 */
7934         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7935                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7936                               bpp);
7937                 pipe_config->pipe_bpp = 24;
7938         }
7939 }
7940
7941 static int
7942 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7943                           struct drm_framebuffer *fb,
7944                           struct intel_crtc_config *pipe_config)
7945 {
7946         struct drm_device *dev = crtc->base.dev;
7947         struct intel_connector *connector;
7948         int bpp;
7949
7950         switch (fb->pixel_format) {
7951         case DRM_FORMAT_C8:
7952                 bpp = 8*3; /* since we go through a colormap */
7953                 break;
7954         case DRM_FORMAT_XRGB1555:
7955         case DRM_FORMAT_ARGB1555:
7956                 /* checked in intel_framebuffer_init already */
7957                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7958                         return -EINVAL;
7959         case DRM_FORMAT_RGB565:
7960                 bpp = 6*3; /* min is 18bpp */
7961                 break;
7962         case DRM_FORMAT_XBGR8888:
7963         case DRM_FORMAT_ABGR8888:
7964                 /* checked in intel_framebuffer_init already */
7965                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7966                         return -EINVAL;
7967         case DRM_FORMAT_XRGB8888:
7968         case DRM_FORMAT_ARGB8888:
7969                 bpp = 8*3;
7970                 break;
7971         case DRM_FORMAT_XRGB2101010:
7972         case DRM_FORMAT_ARGB2101010:
7973         case DRM_FORMAT_XBGR2101010:
7974         case DRM_FORMAT_ABGR2101010:
7975                 /* checked in intel_framebuffer_init already */
7976                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7977                         return -EINVAL;
7978                 bpp = 10*3;
7979                 break;
7980         /* TODO: gen4+ supports 16 bpc floating point, too. */
7981         default:
7982                 DRM_DEBUG_KMS("unsupported depth\n");
7983                 return -EINVAL;
7984         }
7985
7986         pipe_config->pipe_bpp = bpp;
7987
7988         /* Clamp display bpp to EDID value */
7989         list_for_each_entry(connector, &dev->mode_config.connector_list,
7990                             base.head) {
7991                 if (!connector->new_encoder ||
7992                     connector->new_encoder->new_crtc != crtc)
7993                         continue;
7994
7995                 connected_sink_compute_bpp(connector, pipe_config);
7996         }
7997
7998         return bpp;
7999 }
8000
8001 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8002                                    struct intel_crtc_config *pipe_config,
8003                                    const char *context)
8004 {
8005         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8006                       context, pipe_name(crtc->pipe));
8007
8008         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8009         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8010                       pipe_config->pipe_bpp, pipe_config->dither);
8011         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8012                       pipe_config->has_pch_encoder,
8013                       pipe_config->fdi_lanes,
8014                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8015                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8016                       pipe_config->fdi_m_n.tu);
8017         DRM_DEBUG_KMS("requested mode:\n");
8018         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8019         DRM_DEBUG_KMS("adjusted mode:\n");
8020         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8021         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8022                       pipe_config->gmch_pfit.control,
8023                       pipe_config->gmch_pfit.pgm_ratios,
8024                       pipe_config->gmch_pfit.lvds_border_bits);
8025         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8026                       pipe_config->pch_pfit.pos,
8027                       pipe_config->pch_pfit.size);
8028         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8029 }
8030
8031 static bool check_encoder_cloning(struct drm_crtc *crtc)
8032 {
8033         int num_encoders = 0;
8034         bool uncloneable_encoders = false;
8035         struct intel_encoder *encoder;
8036
8037         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8038                             base.head) {
8039                 if (&encoder->new_crtc->base != crtc)
8040                         continue;
8041
8042                 num_encoders++;
8043                 if (!encoder->cloneable)
8044                         uncloneable_encoders = true;
8045         }
8046
8047         return !(num_encoders > 1 && uncloneable_encoders);
8048 }
8049
8050 static struct intel_crtc_config *
8051 intel_modeset_pipe_config(struct drm_crtc *crtc,
8052                           struct drm_framebuffer *fb,
8053                           struct drm_display_mode *mode)
8054 {
8055         struct drm_device *dev = crtc->dev;
8056         struct intel_encoder *encoder;
8057         struct intel_crtc_config *pipe_config;
8058         int plane_bpp, ret = -EINVAL;
8059         bool retry = true;
8060
8061         if (!check_encoder_cloning(crtc)) {
8062                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8063                 return ERR_PTR(-EINVAL);
8064         }
8065
8066         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8067         if (!pipe_config)
8068                 return ERR_PTR(-ENOMEM);
8069
8070         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8071         drm_mode_copy(&pipe_config->requested_mode, mode);
8072         pipe_config->cpu_transcoder =
8073                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8074         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8075
8076         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8077          * plane pixel format and any sink constraints into account. Returns the
8078          * source plane bpp so that dithering can be selected on mismatches
8079          * after encoders and crtc also have had their say. */
8080         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8081                                               fb, pipe_config);
8082         if (plane_bpp < 0)
8083                 goto fail;
8084
8085 encoder_retry:
8086         /* Ensure the port clock defaults are reset when retrying. */
8087         pipe_config->port_clock = 0;
8088         pipe_config->pixel_multiplier = 1;
8089
8090         /* Pass our mode to the connectors and the CRTC to give them a chance to
8091          * adjust it according to limitations or connector properties, and also
8092          * a chance to reject the mode entirely.
8093          */
8094         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8095                             base.head) {
8096
8097                 if (&encoder->new_crtc->base != crtc)
8098                         continue;
8099
8100                 if (!(encoder->compute_config(encoder, pipe_config))) {
8101                         DRM_DEBUG_KMS("Encoder config failure\n");
8102                         goto fail;
8103                 }
8104         }
8105
8106         /* Set default port clock if not overwritten by the encoder. Needs to be
8107          * done afterwards in case the encoder adjusts the mode. */
8108         if (!pipe_config->port_clock)
8109                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8110
8111         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8112         if (ret < 0) {
8113                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8114                 goto fail;
8115         }
8116
8117         if (ret == RETRY) {
8118                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8119                         ret = -EINVAL;
8120                         goto fail;
8121                 }
8122
8123                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8124                 retry = false;
8125                 goto encoder_retry;
8126         }
8127
8128         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8129         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8130                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8131
8132         return pipe_config;
8133 fail:
8134         kfree(pipe_config);
8135         return ERR_PTR(ret);
8136 }
8137
8138 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8139  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8140 static void
8141 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8142                              unsigned *prepare_pipes, unsigned *disable_pipes)
8143 {
8144         struct intel_crtc *intel_crtc;
8145         struct drm_device *dev = crtc->dev;
8146         struct intel_encoder *encoder;
8147         struct intel_connector *connector;
8148         struct drm_crtc *tmp_crtc;
8149
8150         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8151
8152         /* Check which crtcs have changed outputs connected to them, these need
8153          * to be part of the prepare_pipes mask. We don't (yet) support global
8154          * modeset across multiple crtcs, so modeset_pipes will only have one
8155          * bit set at most. */
8156         list_for_each_entry(connector, &dev->mode_config.connector_list,
8157                             base.head) {
8158                 if (connector->base.encoder == &connector->new_encoder->base)
8159                         continue;
8160
8161                 if (connector->base.encoder) {
8162                         tmp_crtc = connector->base.encoder->crtc;
8163
8164                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8165                 }
8166
8167                 if (connector->new_encoder)
8168                         *prepare_pipes |=
8169                                 1 << connector->new_encoder->new_crtc->pipe;
8170         }
8171
8172         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8173                             base.head) {
8174                 if (encoder->base.crtc == &encoder->new_crtc->base)
8175                         continue;
8176
8177                 if (encoder->base.crtc) {
8178                         tmp_crtc = encoder->base.crtc;
8179
8180                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8181                 }
8182
8183                 if (encoder->new_crtc)
8184                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8185         }
8186
8187         /* Check for any pipes that will be fully disabled ... */
8188         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8189                             base.head) {
8190                 bool used = false;
8191
8192                 /* Don't try to disable disabled crtcs. */
8193                 if (!intel_crtc->base.enabled)
8194                         continue;
8195
8196                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8197                                     base.head) {
8198                         if (encoder->new_crtc == intel_crtc)
8199                                 used = true;
8200                 }
8201
8202                 if (!used)
8203                         *disable_pipes |= 1 << intel_crtc->pipe;
8204         }
8205
8206
8207         /* set_mode is also used to update properties on life display pipes. */
8208         intel_crtc = to_intel_crtc(crtc);
8209         if (crtc->enabled)
8210                 *prepare_pipes |= 1 << intel_crtc->pipe;
8211
8212         /*
8213          * For simplicity do a full modeset on any pipe where the output routing
8214          * changed. We could be more clever, but that would require us to be
8215          * more careful with calling the relevant encoder->mode_set functions.
8216          */
8217         if (*prepare_pipes)
8218                 *modeset_pipes = *prepare_pipes;
8219
8220         /* ... and mask these out. */
8221         *modeset_pipes &= ~(*disable_pipes);
8222         *prepare_pipes &= ~(*disable_pipes);
8223
8224         /*
8225          * HACK: We don't (yet) fully support global modesets. intel_set_config
8226          * obies this rule, but the modeset restore mode of
8227          * intel_modeset_setup_hw_state does not.
8228          */
8229         *modeset_pipes &= 1 << intel_crtc->pipe;
8230         *prepare_pipes &= 1 << intel_crtc->pipe;
8231
8232         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8233                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8234 }
8235
8236 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8237 {
8238         struct drm_encoder *encoder;
8239         struct drm_device *dev = crtc->dev;
8240
8241         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8242                 if (encoder->crtc == crtc)
8243                         return true;
8244
8245         return false;
8246 }
8247
8248 static void
8249 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8250 {
8251         struct intel_encoder *intel_encoder;
8252         struct intel_crtc *intel_crtc;
8253         struct drm_connector *connector;
8254
8255         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8256                             base.head) {
8257                 if (!intel_encoder->base.crtc)
8258                         continue;
8259
8260                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8261
8262                 if (prepare_pipes & (1 << intel_crtc->pipe))
8263                         intel_encoder->connectors_active = false;
8264         }
8265
8266         intel_modeset_commit_output_state(dev);
8267
8268         /* Update computed state. */
8269         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8270                             base.head) {
8271                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8272         }
8273
8274         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8275                 if (!connector->encoder || !connector->encoder->crtc)
8276                         continue;
8277
8278                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8279
8280                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8281                         struct drm_property *dpms_property =
8282                                 dev->mode_config.dpms_property;
8283
8284                         connector->dpms = DRM_MODE_DPMS_ON;
8285                         drm_object_property_set_value(&connector->base,
8286                                                          dpms_property,
8287                                                          DRM_MODE_DPMS_ON);
8288
8289                         intel_encoder = to_intel_encoder(connector->encoder);
8290                         intel_encoder->connectors_active = true;
8291                 }
8292         }
8293
8294 }
8295
8296 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8297                                     struct intel_crtc_config *new)
8298 {
8299         int clock1, clock2, diff;
8300
8301         clock1 = cur->adjusted_mode.clock;
8302         clock2 = new->adjusted_mode.clock;
8303
8304         if (clock1 == clock2)
8305                 return true;
8306
8307         if (!clock1 || !clock2)
8308                 return false;
8309
8310         diff = abs(clock1 - clock2);
8311
8312         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8313                 return true;
8314
8315         return false;
8316 }
8317
8318 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8319         list_for_each_entry((intel_crtc), \
8320                             &(dev)->mode_config.crtc_list, \
8321                             base.head) \
8322                 if (mask & (1 <<(intel_crtc)->pipe))
8323
8324 static bool
8325 intel_pipe_config_compare(struct drm_device *dev,
8326                           struct intel_crtc_config *current_config,
8327                           struct intel_crtc_config *pipe_config)
8328 {
8329 #define PIPE_CONF_CHECK_X(name) \
8330         if (current_config->name != pipe_config->name) { \
8331                 DRM_ERROR("mismatch in " #name " " \
8332                           "(expected 0x%08x, found 0x%08x)\n", \
8333                           current_config->name, \
8334                           pipe_config->name); \
8335                 return false; \
8336         }
8337
8338 #define PIPE_CONF_CHECK_I(name) \
8339         if (current_config->name != pipe_config->name) { \
8340                 DRM_ERROR("mismatch in " #name " " \
8341                           "(expected %i, found %i)\n", \
8342                           current_config->name, \
8343                           pipe_config->name); \
8344                 return false; \
8345         }
8346
8347 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8348         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8349                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8350                           "(expected %i, found %i)\n", \
8351                           current_config->name & (mask), \
8352                           pipe_config->name & (mask)); \
8353                 return false; \
8354         }
8355
8356 #define PIPE_CONF_QUIRK(quirk)  \
8357         ((current_config->quirks | pipe_config->quirks) & (quirk))
8358
8359         PIPE_CONF_CHECK_I(cpu_transcoder);
8360
8361         PIPE_CONF_CHECK_I(has_pch_encoder);
8362         PIPE_CONF_CHECK_I(fdi_lanes);
8363         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8364         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8365         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8366         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8367         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8368
8369         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8370         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8371         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8372         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8373         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8375
8376         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8377         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8378         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8379         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8380         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8381         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8382
8383         PIPE_CONF_CHECK_I(pixel_multiplier);
8384
8385         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8386                               DRM_MODE_FLAG_INTERLACE);
8387
8388         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8389                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390                                       DRM_MODE_FLAG_PHSYNC);
8391                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8392                                       DRM_MODE_FLAG_NHSYNC);
8393                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8394                                       DRM_MODE_FLAG_PVSYNC);
8395                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8396                                       DRM_MODE_FLAG_NVSYNC);
8397         }
8398
8399         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8400         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8401
8402         PIPE_CONF_CHECK_I(gmch_pfit.control);
8403         /* pfit ratios are autocomputed by the hw on gen4+ */
8404         if (INTEL_INFO(dev)->gen < 4)
8405                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8406         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8407         PIPE_CONF_CHECK_I(pch_pfit.pos);
8408         PIPE_CONF_CHECK_I(pch_pfit.size);
8409
8410         PIPE_CONF_CHECK_I(ips_enabled);
8411
8412         PIPE_CONF_CHECK_I(shared_dpll);
8413         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8414         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8415         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8416         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8417
8418 #undef PIPE_CONF_CHECK_X
8419 #undef PIPE_CONF_CHECK_I
8420 #undef PIPE_CONF_CHECK_FLAGS
8421 #undef PIPE_CONF_QUIRK
8422
8423         if (!IS_HASWELL(dev)) {
8424                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8425                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8426                                   current_config->adjusted_mode.clock,
8427                                   pipe_config->adjusted_mode.clock);
8428                         return false;
8429                 }
8430         }
8431
8432         return true;
8433 }
8434
8435 static void
8436 check_connector_state(struct drm_device *dev)
8437 {
8438         struct intel_connector *connector;
8439
8440         list_for_each_entry(connector, &dev->mode_config.connector_list,
8441                             base.head) {
8442                 /* This also checks the encoder/connector hw state with the
8443                  * ->get_hw_state callbacks. */
8444                 intel_connector_check_state(connector);
8445
8446                 WARN(&connector->new_encoder->base != connector->base.encoder,
8447                      "connector's staged encoder doesn't match current encoder\n");
8448         }
8449 }
8450
8451 static void
8452 check_encoder_state(struct drm_device *dev)
8453 {
8454         struct intel_encoder *encoder;
8455         struct intel_connector *connector;
8456
8457         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8458                             base.head) {
8459                 bool enabled = false;
8460                 bool active = false;
8461                 enum pipe pipe, tracked_pipe;
8462
8463                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8464                               encoder->base.base.id,
8465                               drm_get_encoder_name(&encoder->base));
8466
8467                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8468                      "encoder's stage crtc doesn't match current crtc\n");
8469                 WARN(encoder->connectors_active && !encoder->base.crtc,
8470                      "encoder's active_connectors set, but no crtc\n");
8471
8472                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8473                                     base.head) {
8474                         if (connector->base.encoder != &encoder->base)
8475                                 continue;
8476                         enabled = true;
8477                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8478                                 active = true;
8479                 }
8480                 WARN(!!encoder->base.crtc != enabled,
8481                      "encoder's enabled state mismatch "
8482                      "(expected %i, found %i)\n",
8483                      !!encoder->base.crtc, enabled);
8484                 WARN(active && !encoder->base.crtc,
8485                      "active encoder with no crtc\n");
8486
8487                 WARN(encoder->connectors_active != active,
8488                      "encoder's computed active state doesn't match tracked active state "
8489                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8490
8491                 active = encoder->get_hw_state(encoder, &pipe);
8492                 WARN(active != encoder->connectors_active,
8493                      "encoder's hw state doesn't match sw tracking "
8494                      "(expected %i, found %i)\n",
8495                      encoder->connectors_active, active);
8496
8497                 if (!encoder->base.crtc)
8498                         continue;
8499
8500                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8501                 WARN(active && pipe != tracked_pipe,
8502                      "active encoder's pipe doesn't match"
8503                      "(expected %i, found %i)\n",
8504                      tracked_pipe, pipe);
8505
8506         }
8507 }
8508
8509 static void
8510 check_crtc_state(struct drm_device *dev)
8511 {
8512         drm_i915_private_t *dev_priv = dev->dev_private;
8513         struct intel_crtc *crtc;
8514         struct intel_encoder *encoder;
8515         struct intel_crtc_config pipe_config;
8516
8517         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8518                             base.head) {
8519                 bool enabled = false;
8520                 bool active = false;
8521
8522                 memset(&pipe_config, 0, sizeof(pipe_config));
8523
8524                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8525                               crtc->base.base.id);
8526
8527                 WARN(crtc->active && !crtc->base.enabled,
8528                      "active crtc, but not enabled in sw tracking\n");
8529
8530                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8531                                     base.head) {
8532                         if (encoder->base.crtc != &crtc->base)
8533                                 continue;
8534                         enabled = true;
8535                         if (encoder->connectors_active)
8536                                 active = true;
8537                 }
8538
8539                 WARN(active != crtc->active,
8540                      "crtc's computed active state doesn't match tracked active state "
8541                      "(expected %i, found %i)\n", active, crtc->active);
8542                 WARN(enabled != crtc->base.enabled,
8543                      "crtc's computed enabled state doesn't match tracked enabled state "
8544                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8545
8546                 active = dev_priv->display.get_pipe_config(crtc,
8547                                                            &pipe_config);
8548
8549                 /* hw state is inconsistent with the pipe A quirk */
8550                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8551                         active = crtc->active;
8552
8553                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8554                                     base.head) {
8555                         if (encoder->base.crtc != &crtc->base)
8556                                 continue;
8557                         if (encoder->get_config)
8558                                 encoder->get_config(encoder, &pipe_config);
8559                 }
8560
8561                 if (dev_priv->display.get_clock)
8562                         dev_priv->display.get_clock(crtc, &pipe_config);
8563
8564                 WARN(crtc->active != active,
8565                      "crtc active state doesn't match with hw state "
8566                      "(expected %i, found %i)\n", crtc->active, active);
8567
8568                 if (active &&
8569                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8570                         WARN(1, "pipe state doesn't match!\n");
8571                         intel_dump_pipe_config(crtc, &pipe_config,
8572                                                "[hw state]");
8573                         intel_dump_pipe_config(crtc, &crtc->config,
8574                                                "[sw state]");
8575                 }
8576         }
8577 }
8578
8579 static void
8580 check_shared_dpll_state(struct drm_device *dev)
8581 {
8582         drm_i915_private_t *dev_priv = dev->dev_private;
8583         struct intel_crtc *crtc;
8584         struct intel_dpll_hw_state dpll_hw_state;
8585         int i;
8586
8587         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8588                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8589                 int enabled_crtcs = 0, active_crtcs = 0;
8590                 bool active;
8591
8592                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8593
8594                 DRM_DEBUG_KMS("%s\n", pll->name);
8595
8596                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8597
8598                 WARN(pll->active > pll->refcount,
8599                      "more active pll users than references: %i vs %i\n",
8600                      pll->active, pll->refcount);
8601                 WARN(pll->active && !pll->on,
8602                      "pll in active use but not on in sw tracking\n");
8603                 WARN(pll->on && !pll->active,
8604                      "pll in on but not on in use in sw tracking\n");
8605                 WARN(pll->on != active,
8606                      "pll on state mismatch (expected %i, found %i)\n",
8607                      pll->on, active);
8608
8609                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8610                                     base.head) {
8611                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8612                                 enabled_crtcs++;
8613                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8614                                 active_crtcs++;
8615                 }
8616                 WARN(pll->active != active_crtcs,
8617                      "pll active crtcs mismatch (expected %i, found %i)\n",
8618                      pll->active, active_crtcs);
8619                 WARN(pll->refcount != enabled_crtcs,
8620                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8621                      pll->refcount, enabled_crtcs);
8622
8623                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8624                                        sizeof(dpll_hw_state)),
8625                      "pll hw state mismatch\n");
8626         }
8627 }
8628
8629 void
8630 intel_modeset_check_state(struct drm_device *dev)
8631 {
8632         check_connector_state(dev);
8633         check_encoder_state(dev);
8634         check_crtc_state(dev);
8635         check_shared_dpll_state(dev);
8636 }
8637
8638 static int __intel_set_mode(struct drm_crtc *crtc,
8639                             struct drm_display_mode *mode,
8640                             int x, int y, struct drm_framebuffer *fb)
8641 {
8642         struct drm_device *dev = crtc->dev;
8643         drm_i915_private_t *dev_priv = dev->dev_private;
8644         struct drm_display_mode *saved_mode, *saved_hwmode;
8645         struct intel_crtc_config *pipe_config = NULL;
8646         struct intel_crtc *intel_crtc;
8647         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8648         int ret = 0;
8649
8650         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8651         if (!saved_mode)
8652                 return -ENOMEM;
8653         saved_hwmode = saved_mode + 1;
8654
8655         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8656                                      &prepare_pipes, &disable_pipes);
8657
8658         *saved_hwmode = crtc->hwmode;
8659         *saved_mode = crtc->mode;
8660
8661         /* Hack: Because we don't (yet) support global modeset on multiple
8662          * crtcs, we don't keep track of the new mode for more than one crtc.
8663          * Hence simply check whether any bit is set in modeset_pipes in all the
8664          * pieces of code that are not yet converted to deal with mutliple crtcs
8665          * changing their mode at the same time. */
8666         if (modeset_pipes) {
8667                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8668                 if (IS_ERR(pipe_config)) {
8669                         ret = PTR_ERR(pipe_config);
8670                         pipe_config = NULL;
8671
8672                         goto out;
8673                 }
8674                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8675                                        "[modeset]");
8676         }
8677
8678         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8679                 intel_crtc_disable(&intel_crtc->base);
8680
8681         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8682                 if (intel_crtc->base.enabled)
8683                         dev_priv->display.crtc_disable(&intel_crtc->base);
8684         }
8685
8686         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8687          * to set it here already despite that we pass it down the callchain.
8688          */
8689         if (modeset_pipes) {
8690                 crtc->mode = *mode;
8691                 /* mode_set/enable/disable functions rely on a correct pipe
8692                  * config. */
8693                 to_intel_crtc(crtc)->config = *pipe_config;
8694         }
8695
8696         /* Only after disabling all output pipelines that will be changed can we
8697          * update the the output configuration. */
8698         intel_modeset_update_state(dev, prepare_pipes);
8699
8700         if (dev_priv->display.modeset_global_resources)
8701                 dev_priv->display.modeset_global_resources(dev);
8702
8703         /* Set up the DPLL and any encoders state that needs to adjust or depend
8704          * on the DPLL.
8705          */
8706         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8707                 ret = intel_crtc_mode_set(&intel_crtc->base,
8708                                           x, y, fb);
8709                 if (ret)
8710                         goto done;
8711         }
8712
8713         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8714         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8715                 dev_priv->display.crtc_enable(&intel_crtc->base);
8716
8717         if (modeset_pipes) {
8718                 /* Store real post-adjustment hardware mode. */
8719                 crtc->hwmode = pipe_config->adjusted_mode;
8720
8721                 /* Calculate and store various constants which
8722                  * are later needed by vblank and swap-completion
8723                  * timestamping. They are derived from true hwmode.
8724                  */
8725                 drm_calc_timestamping_constants(crtc);
8726         }
8727
8728         /* FIXME: add subpixel order */
8729 done:
8730         if (ret && crtc->enabled) {
8731                 crtc->hwmode = *saved_hwmode;
8732                 crtc->mode = *saved_mode;
8733         }
8734
8735 out:
8736         kfree(pipe_config);
8737         kfree(saved_mode);
8738         return ret;
8739 }
8740
8741 int intel_set_mode(struct drm_crtc *crtc,
8742                      struct drm_display_mode *mode,
8743                      int x, int y, struct drm_framebuffer *fb)
8744 {
8745         int ret;
8746
8747         ret = __intel_set_mode(crtc, mode, x, y, fb);
8748
8749         if (ret == 0)
8750                 intel_modeset_check_state(crtc->dev);
8751
8752         return ret;
8753 }
8754
8755 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8756 {
8757         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8758 }
8759
8760 #undef for_each_intel_crtc_masked
8761
8762 static void intel_set_config_free(struct intel_set_config *config)
8763 {
8764         if (!config)
8765                 return;
8766
8767         kfree(config->save_connector_encoders);
8768         kfree(config->save_encoder_crtcs);
8769         kfree(config);
8770 }
8771
8772 static int intel_set_config_save_state(struct drm_device *dev,
8773                                        struct intel_set_config *config)
8774 {
8775         struct drm_encoder *encoder;
8776         struct drm_connector *connector;
8777         int count;
8778
8779         config->save_encoder_crtcs =
8780                 kcalloc(dev->mode_config.num_encoder,
8781                         sizeof(struct drm_crtc *), GFP_KERNEL);
8782         if (!config->save_encoder_crtcs)
8783                 return -ENOMEM;
8784
8785         config->save_connector_encoders =
8786                 kcalloc(dev->mode_config.num_connector,
8787                         sizeof(struct drm_encoder *), GFP_KERNEL);
8788         if (!config->save_connector_encoders)
8789                 return -ENOMEM;
8790
8791         /* Copy data. Note that driver private data is not affected.
8792          * Should anything bad happen only the expected state is
8793          * restored, not the drivers personal bookkeeping.
8794          */
8795         count = 0;
8796         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8797                 config->save_encoder_crtcs[count++] = encoder->crtc;
8798         }
8799
8800         count = 0;
8801         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8802                 config->save_connector_encoders[count++] = connector->encoder;
8803         }
8804
8805         return 0;
8806 }
8807
8808 static void intel_set_config_restore_state(struct drm_device *dev,
8809                                            struct intel_set_config *config)
8810 {
8811         struct intel_encoder *encoder;
8812         struct intel_connector *connector;
8813         int count;
8814
8815         count = 0;
8816         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8817                 encoder->new_crtc =
8818                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8819         }
8820
8821         count = 0;
8822         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8823                 connector->new_encoder =
8824                         to_intel_encoder(config->save_connector_encoders[count++]);
8825         }
8826 }
8827
8828 static bool
8829 is_crtc_connector_off(struct drm_mode_set *set)
8830 {
8831         int i;
8832
8833         if (set->num_connectors == 0)
8834                 return false;
8835
8836         if (WARN_ON(set->connectors == NULL))
8837                 return false;
8838
8839         for (i = 0; i < set->num_connectors; i++)
8840                 if (set->connectors[i]->encoder &&
8841                     set->connectors[i]->encoder->crtc == set->crtc &&
8842                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8843                         return true;
8844
8845         return false;
8846 }
8847
8848 static void
8849 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8850                                       struct intel_set_config *config)
8851 {
8852
8853         /* We should be able to check here if the fb has the same properties
8854          * and then just flip_or_move it */
8855         if (is_crtc_connector_off(set)) {
8856                 config->mode_changed = true;
8857         } else if (set->crtc->fb != set->fb) {
8858                 /* If we have no fb then treat it as a full mode set */
8859                 if (set->crtc->fb == NULL) {
8860                         struct intel_crtc *intel_crtc =
8861                                 to_intel_crtc(set->crtc);
8862
8863                         if (intel_crtc->active && i915_fastboot) {
8864                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8865                                 config->fb_changed = true;
8866                         } else {
8867                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8868                                 config->mode_changed = true;
8869                         }
8870                 } else if (set->fb == NULL) {
8871                         config->mode_changed = true;
8872                 } else if (set->fb->pixel_format !=
8873                            set->crtc->fb->pixel_format) {
8874                         config->mode_changed = true;
8875                 } else {
8876                         config->fb_changed = true;
8877                 }
8878         }
8879
8880         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8881                 config->fb_changed = true;
8882
8883         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8884                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8885                 drm_mode_debug_printmodeline(&set->crtc->mode);
8886                 drm_mode_debug_printmodeline(set->mode);
8887                 config->mode_changed = true;
8888         }
8889 }
8890
8891 static int
8892 intel_modeset_stage_output_state(struct drm_device *dev,
8893                                  struct drm_mode_set *set,
8894                                  struct intel_set_config *config)
8895 {
8896         struct drm_crtc *new_crtc;
8897         struct intel_connector *connector;
8898         struct intel_encoder *encoder;
8899         int count, ro;
8900
8901         /* The upper layers ensure that we either disable a crtc or have a list
8902          * of connectors. For paranoia, double-check this. */
8903         WARN_ON(!set->fb && (set->num_connectors != 0));
8904         WARN_ON(set->fb && (set->num_connectors == 0));
8905
8906         count = 0;
8907         list_for_each_entry(connector, &dev->mode_config.connector_list,
8908                             base.head) {
8909                 /* Otherwise traverse passed in connector list and get encoders
8910                  * for them. */
8911                 for (ro = 0; ro < set->num_connectors; ro++) {
8912                         if (set->connectors[ro] == &connector->base) {
8913                                 connector->new_encoder = connector->encoder;
8914                                 break;
8915                         }
8916                 }
8917
8918                 /* If we disable the crtc, disable all its connectors. Also, if
8919                  * the connector is on the changing crtc but not on the new
8920                  * connector list, disable it. */
8921                 if ((!set->fb || ro == set->num_connectors) &&
8922                     connector->base.encoder &&
8923                     connector->base.encoder->crtc == set->crtc) {
8924                         connector->new_encoder = NULL;
8925
8926                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8927                                 connector->base.base.id,
8928                                 drm_get_connector_name(&connector->base));
8929                 }
8930
8931
8932                 if (&connector->new_encoder->base != connector->base.encoder) {
8933                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8934                         config->mode_changed = true;
8935                 }
8936         }
8937         /* connector->new_encoder is now updated for all connectors. */
8938
8939         /* Update crtc of enabled connectors. */
8940         count = 0;
8941         list_for_each_entry(connector, &dev->mode_config.connector_list,
8942                             base.head) {
8943                 if (!connector->new_encoder)
8944                         continue;
8945
8946                 new_crtc = connector->new_encoder->base.crtc;
8947
8948                 for (ro = 0; ro < set->num_connectors; ro++) {
8949                         if (set->connectors[ro] == &connector->base)
8950                                 new_crtc = set->crtc;
8951                 }
8952
8953                 /* Make sure the new CRTC will work with the encoder */
8954                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8955                                            new_crtc)) {
8956                         return -EINVAL;
8957                 }
8958                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8959
8960                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8961                         connector->base.base.id,
8962                         drm_get_connector_name(&connector->base),
8963                         new_crtc->base.id);
8964         }
8965
8966         /* Check for any encoders that needs to be disabled. */
8967         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8968                             base.head) {
8969                 list_for_each_entry(connector,
8970                                     &dev->mode_config.connector_list,
8971                                     base.head) {
8972                         if (connector->new_encoder == encoder) {
8973                                 WARN_ON(!connector->new_encoder->new_crtc);
8974
8975                                 goto next_encoder;
8976                         }
8977                 }
8978                 encoder->new_crtc = NULL;
8979 next_encoder:
8980                 /* Only now check for crtc changes so we don't miss encoders
8981                  * that will be disabled. */
8982                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8983                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8984                         config->mode_changed = true;
8985                 }
8986         }
8987         /* Now we've also updated encoder->new_crtc for all encoders. */
8988
8989         return 0;
8990 }
8991
8992 static int intel_crtc_set_config(struct drm_mode_set *set)
8993 {
8994         struct drm_device *dev;
8995         struct drm_mode_set save_set;
8996         struct intel_set_config *config;
8997         int ret;
8998
8999         BUG_ON(!set);
9000         BUG_ON(!set->crtc);
9001         BUG_ON(!set->crtc->helper_private);
9002
9003         /* Enforce sane interface api - has been abused by the fb helper. */
9004         BUG_ON(!set->mode && set->fb);
9005         BUG_ON(set->fb && set->num_connectors == 0);
9006
9007         if (set->fb) {
9008                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9009                                 set->crtc->base.id, set->fb->base.id,
9010                                 (int)set->num_connectors, set->x, set->y);
9011         } else {
9012                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9013         }
9014
9015         dev = set->crtc->dev;
9016
9017         ret = -ENOMEM;
9018         config = kzalloc(sizeof(*config), GFP_KERNEL);
9019         if (!config)
9020                 goto out_config;
9021
9022         ret = intel_set_config_save_state(dev, config);
9023         if (ret)
9024                 goto out_config;
9025
9026         save_set.crtc = set->crtc;
9027         save_set.mode = &set->crtc->mode;
9028         save_set.x = set->crtc->x;
9029         save_set.y = set->crtc->y;
9030         save_set.fb = set->crtc->fb;
9031
9032         /* Compute whether we need a full modeset, only an fb base update or no
9033          * change at all. In the future we might also check whether only the
9034          * mode changed, e.g. for LVDS where we only change the panel fitter in
9035          * such cases. */
9036         intel_set_config_compute_mode_changes(set, config);
9037
9038         ret = intel_modeset_stage_output_state(dev, set, config);
9039         if (ret)
9040                 goto fail;
9041
9042         if (config->mode_changed) {
9043                 ret = intel_set_mode(set->crtc, set->mode,
9044                                      set->x, set->y, set->fb);
9045         } else if (config->fb_changed) {
9046                 intel_crtc_wait_for_pending_flips(set->crtc);
9047
9048                 ret = intel_pipe_set_base(set->crtc,
9049                                           set->x, set->y, set->fb);
9050         }
9051
9052         if (ret) {
9053                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9054                               set->crtc->base.id, ret);
9055 fail:
9056                 intel_set_config_restore_state(dev, config);
9057
9058                 /* Try to restore the config */
9059                 if (config->mode_changed &&
9060                     intel_set_mode(save_set.crtc, save_set.mode,
9061                                    save_set.x, save_set.y, save_set.fb))
9062                         DRM_ERROR("failed to restore config after modeset failure\n");
9063         }
9064
9065 out_config:
9066         intel_set_config_free(config);
9067         return ret;
9068 }
9069
9070 static const struct drm_crtc_funcs intel_crtc_funcs = {
9071         .cursor_set = intel_crtc_cursor_set,
9072         .cursor_move = intel_crtc_cursor_move,
9073         .gamma_set = intel_crtc_gamma_set,
9074         .set_config = intel_crtc_set_config,
9075         .destroy = intel_crtc_destroy,
9076         .page_flip = intel_crtc_page_flip,
9077 };
9078
9079 static void intel_cpu_pll_init(struct drm_device *dev)
9080 {
9081         if (HAS_DDI(dev))
9082                 intel_ddi_pll_init(dev);
9083 }
9084
9085 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9086                                       struct intel_shared_dpll *pll,
9087                                       struct intel_dpll_hw_state *hw_state)
9088 {
9089         uint32_t val;
9090
9091         val = I915_READ(PCH_DPLL(pll->id));
9092         hw_state->dpll = val;
9093         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9094         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9095
9096         return val & DPLL_VCO_ENABLE;
9097 }
9098
9099 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9100                                   struct intel_shared_dpll *pll)
9101 {
9102         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9103         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9104 }
9105
9106 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9107                                 struct intel_shared_dpll *pll)
9108 {
9109         /* PCH refclock must be enabled first */
9110         assert_pch_refclk_enabled(dev_priv);
9111
9112         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9113
9114         /* Wait for the clocks to stabilize. */
9115         POSTING_READ(PCH_DPLL(pll->id));
9116         udelay(150);
9117
9118         /* The pixel multiplier can only be updated once the
9119          * DPLL is enabled and the clocks are stable.
9120          *
9121          * So write it again.
9122          */
9123         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9124         POSTING_READ(PCH_DPLL(pll->id));
9125         udelay(200);
9126 }
9127
9128 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9129                                  struct intel_shared_dpll *pll)
9130 {
9131         struct drm_device *dev = dev_priv->dev;
9132         struct intel_crtc *crtc;
9133
9134         /* Make sure no transcoder isn't still depending on us. */
9135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9136                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9137                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9138         }
9139
9140         I915_WRITE(PCH_DPLL(pll->id), 0);
9141         POSTING_READ(PCH_DPLL(pll->id));
9142         udelay(200);
9143 }
9144
9145 static char *ibx_pch_dpll_names[] = {
9146         "PCH DPLL A",
9147         "PCH DPLL B",
9148 };
9149
9150 static void ibx_pch_dpll_init(struct drm_device *dev)
9151 {
9152         struct drm_i915_private *dev_priv = dev->dev_private;
9153         int i;
9154
9155         dev_priv->num_shared_dpll = 2;
9156
9157         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9158                 dev_priv->shared_dplls[i].id = i;
9159                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9160                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9161                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9162                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9163                 dev_priv->shared_dplls[i].get_hw_state =
9164                         ibx_pch_dpll_get_hw_state;
9165         }
9166 }
9167
9168 static void intel_shared_dpll_init(struct drm_device *dev)
9169 {
9170         struct drm_i915_private *dev_priv = dev->dev_private;
9171
9172         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9173                 ibx_pch_dpll_init(dev);
9174         else
9175                 dev_priv->num_shared_dpll = 0;
9176
9177         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9178         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9179                       dev_priv->num_shared_dpll);
9180 }
9181
9182 static void intel_crtc_init(struct drm_device *dev, int pipe)
9183 {
9184         drm_i915_private_t *dev_priv = dev->dev_private;
9185         struct intel_crtc *intel_crtc;
9186         int i;
9187
9188         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9189         if (intel_crtc == NULL)
9190                 return;
9191
9192         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9193
9194         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9195         for (i = 0; i < 256; i++) {
9196                 intel_crtc->lut_r[i] = i;
9197                 intel_crtc->lut_g[i] = i;
9198                 intel_crtc->lut_b[i] = i;
9199         }
9200
9201         /* Swap pipes & planes for FBC on pre-965 */
9202         intel_crtc->pipe = pipe;
9203         intel_crtc->plane = pipe;
9204         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9205                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9206                 intel_crtc->plane = !pipe;
9207         }
9208
9209         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9210                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9211         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9212         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9213
9214         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9215 }
9216
9217 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9218                                 struct drm_file *file)
9219 {
9220         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9221         struct drm_mode_object *drmmode_obj;
9222         struct intel_crtc *crtc;
9223
9224         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9225                 return -ENODEV;
9226
9227         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9228                         DRM_MODE_OBJECT_CRTC);
9229
9230         if (!drmmode_obj) {
9231                 DRM_ERROR("no such CRTC id\n");
9232                 return -EINVAL;
9233         }
9234
9235         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9236         pipe_from_crtc_id->pipe = crtc->pipe;
9237
9238         return 0;
9239 }
9240
9241 static int intel_encoder_clones(struct intel_encoder *encoder)
9242 {
9243         struct drm_device *dev = encoder->base.dev;
9244         struct intel_encoder *source_encoder;
9245         int index_mask = 0;
9246         int entry = 0;
9247
9248         list_for_each_entry(source_encoder,
9249                             &dev->mode_config.encoder_list, base.head) {
9250
9251                 if (encoder == source_encoder)
9252                         index_mask |= (1 << entry);
9253
9254                 /* Intel hw has only one MUX where enocoders could be cloned. */
9255                 if (encoder->cloneable && source_encoder->cloneable)
9256                         index_mask |= (1 << entry);
9257
9258                 entry++;
9259         }
9260
9261         return index_mask;
9262 }
9263
9264 static bool has_edp_a(struct drm_device *dev)
9265 {
9266         struct drm_i915_private *dev_priv = dev->dev_private;
9267
9268         if (!IS_MOBILE(dev))
9269                 return false;
9270
9271         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9272                 return false;
9273
9274         if (IS_GEN5(dev) &&
9275             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9276                 return false;
9277
9278         return true;
9279 }
9280
9281 static void intel_setup_outputs(struct drm_device *dev)
9282 {
9283         struct drm_i915_private *dev_priv = dev->dev_private;
9284         struct intel_encoder *encoder;
9285         bool dpd_is_edp = false;
9286
9287         intel_lvds_init(dev);
9288
9289         if (!IS_ULT(dev))
9290                 intel_crt_init(dev);
9291
9292         if (HAS_DDI(dev)) {
9293                 int found;
9294
9295                 /* Haswell uses DDI functions to detect digital outputs */
9296                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9297                 /* DDI A only supports eDP */
9298                 if (found)
9299                         intel_ddi_init(dev, PORT_A);
9300
9301                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9302                  * register */
9303                 found = I915_READ(SFUSE_STRAP);
9304
9305                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9306                         intel_ddi_init(dev, PORT_B);
9307                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9308                         intel_ddi_init(dev, PORT_C);
9309                 if (found & SFUSE_STRAP_DDID_DETECTED)
9310                         intel_ddi_init(dev, PORT_D);
9311         } else if (HAS_PCH_SPLIT(dev)) {
9312                 int found;
9313                 dpd_is_edp = intel_dpd_is_edp(dev);
9314
9315                 if (has_edp_a(dev))
9316                         intel_dp_init(dev, DP_A, PORT_A);
9317
9318                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9319                         /* PCH SDVOB multiplex with HDMIB */
9320                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9321                         if (!found)
9322                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9323                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9324                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9325                 }
9326
9327                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9328                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9329
9330                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9331                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9332
9333                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9334                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9335
9336                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9337                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9338         } else if (IS_VALLEYVIEW(dev)) {
9339                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9340                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9341                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9342
9343                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9344                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9345                                         PORT_B);
9346                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9347                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9348                 }
9349         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9350                 bool found = false;
9351
9352                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9353                         DRM_DEBUG_KMS("probing SDVOB\n");
9354                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9355                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9356                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9357                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9358                         }
9359
9360                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9361                                 intel_dp_init(dev, DP_B, PORT_B);
9362                 }
9363
9364                 /* Before G4X SDVOC doesn't have its own detect register */
9365
9366                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9367                         DRM_DEBUG_KMS("probing SDVOC\n");
9368                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9369                 }
9370
9371                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9372
9373                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9374                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9375                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9376                         }
9377                         if (SUPPORTS_INTEGRATED_DP(dev))
9378                                 intel_dp_init(dev, DP_C, PORT_C);
9379                 }
9380
9381                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9382                     (I915_READ(DP_D) & DP_DETECTED))
9383                         intel_dp_init(dev, DP_D, PORT_D);
9384         } else if (IS_GEN2(dev))
9385                 intel_dvo_init(dev);
9386
9387         if (SUPPORTS_TV(dev))
9388                 intel_tv_init(dev);
9389
9390         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9391                 encoder->base.possible_crtcs = encoder->crtc_mask;
9392                 encoder->base.possible_clones =
9393                         intel_encoder_clones(encoder);
9394         }
9395
9396         intel_init_pch_refclk(dev);
9397
9398         drm_helper_move_panel_connectors_to_head(dev);
9399 }
9400
9401 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9402 {
9403         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9404
9405         drm_framebuffer_cleanup(fb);
9406         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9407
9408         kfree(intel_fb);
9409 }
9410
9411 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9412                                                 struct drm_file *file,
9413                                                 unsigned int *handle)
9414 {
9415         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9416         struct drm_i915_gem_object *obj = intel_fb->obj;
9417
9418         return drm_gem_handle_create(file, &obj->base, handle);
9419 }
9420
9421 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9422         .destroy = intel_user_framebuffer_destroy,
9423         .create_handle = intel_user_framebuffer_create_handle,
9424 };
9425
9426 int intel_framebuffer_init(struct drm_device *dev,
9427                            struct intel_framebuffer *intel_fb,
9428                            struct drm_mode_fb_cmd2 *mode_cmd,
9429                            struct drm_i915_gem_object *obj)
9430 {
9431         int pitch_limit;
9432         int ret;
9433
9434         if (obj->tiling_mode == I915_TILING_Y) {
9435                 DRM_DEBUG("hardware does not support tiling Y\n");
9436                 return -EINVAL;
9437         }
9438
9439         if (mode_cmd->pitches[0] & 63) {
9440                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9441                           mode_cmd->pitches[0]);
9442                 return -EINVAL;
9443         }
9444
9445         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9446                 pitch_limit = 32*1024;
9447         } else if (INTEL_INFO(dev)->gen >= 4) {
9448                 if (obj->tiling_mode)
9449                         pitch_limit = 16*1024;
9450                 else
9451                         pitch_limit = 32*1024;
9452         } else if (INTEL_INFO(dev)->gen >= 3) {
9453                 if (obj->tiling_mode)
9454                         pitch_limit = 8*1024;
9455                 else
9456                         pitch_limit = 16*1024;
9457         } else
9458                 /* XXX DSPC is limited to 4k tiled */
9459                 pitch_limit = 8*1024;
9460
9461         if (mode_cmd->pitches[0] > pitch_limit) {
9462                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9463                           obj->tiling_mode ? "tiled" : "linear",
9464                           mode_cmd->pitches[0], pitch_limit);
9465                 return -EINVAL;
9466         }
9467
9468         if (obj->tiling_mode != I915_TILING_NONE &&
9469             mode_cmd->pitches[0] != obj->stride) {
9470                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9471                           mode_cmd->pitches[0], obj->stride);
9472                 return -EINVAL;
9473         }
9474
9475         /* Reject formats not supported by any plane early. */
9476         switch (mode_cmd->pixel_format) {
9477         case DRM_FORMAT_C8:
9478         case DRM_FORMAT_RGB565:
9479         case DRM_FORMAT_XRGB8888:
9480         case DRM_FORMAT_ARGB8888:
9481                 break;
9482         case DRM_FORMAT_XRGB1555:
9483         case DRM_FORMAT_ARGB1555:
9484                 if (INTEL_INFO(dev)->gen > 3) {
9485                         DRM_DEBUG("unsupported pixel format: %s\n",
9486                                   drm_get_format_name(mode_cmd->pixel_format));
9487                         return -EINVAL;
9488                 }
9489                 break;
9490         case DRM_FORMAT_XBGR8888:
9491         case DRM_FORMAT_ABGR8888:
9492         case DRM_FORMAT_XRGB2101010:
9493         case DRM_FORMAT_ARGB2101010:
9494         case DRM_FORMAT_XBGR2101010:
9495         case DRM_FORMAT_ABGR2101010:
9496                 if (INTEL_INFO(dev)->gen < 4) {
9497                         DRM_DEBUG("unsupported pixel format: %s\n",
9498                                   drm_get_format_name(mode_cmd->pixel_format));
9499                         return -EINVAL;
9500                 }
9501                 break;
9502         case DRM_FORMAT_YUYV:
9503         case DRM_FORMAT_UYVY:
9504         case DRM_FORMAT_YVYU:
9505         case DRM_FORMAT_VYUY:
9506                 if (INTEL_INFO(dev)->gen < 5) {
9507                         DRM_DEBUG("unsupported pixel format: %s\n",
9508                                   drm_get_format_name(mode_cmd->pixel_format));
9509                         return -EINVAL;
9510                 }
9511                 break;
9512         default:
9513                 DRM_DEBUG("unsupported pixel format: %s\n",
9514                           drm_get_format_name(mode_cmd->pixel_format));
9515                 return -EINVAL;
9516         }
9517
9518         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9519         if (mode_cmd->offsets[0] != 0)
9520                 return -EINVAL;
9521
9522         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9523         intel_fb->obj = obj;
9524
9525         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9526         if (ret) {
9527                 DRM_ERROR("framebuffer init failed %d\n", ret);
9528                 return ret;
9529         }
9530
9531         return 0;
9532 }
9533
9534 static struct drm_framebuffer *
9535 intel_user_framebuffer_create(struct drm_device *dev,
9536                               struct drm_file *filp,
9537                               struct drm_mode_fb_cmd2 *mode_cmd)
9538 {
9539         struct drm_i915_gem_object *obj;
9540
9541         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9542                                                 mode_cmd->handles[0]));
9543         if (&obj->base == NULL)
9544                 return ERR_PTR(-ENOENT);
9545
9546         return intel_framebuffer_create(dev, mode_cmd, obj);
9547 }
9548
9549 static const struct drm_mode_config_funcs intel_mode_funcs = {
9550         .fb_create = intel_user_framebuffer_create,
9551         .output_poll_changed = intel_fb_output_poll_changed,
9552 };
9553
9554 /* Set up chip specific display functions */
9555 static void intel_init_display(struct drm_device *dev)
9556 {
9557         struct drm_i915_private *dev_priv = dev->dev_private;
9558
9559         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9560                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9561         else if (IS_VALLEYVIEW(dev))
9562                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9563         else if (IS_PINEVIEW(dev))
9564                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9565         else
9566                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9567
9568         if (HAS_DDI(dev)) {
9569                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9570                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9571                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9572                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9573                 dev_priv->display.off = haswell_crtc_off;
9574                 dev_priv->display.update_plane = ironlake_update_plane;
9575         } else if (HAS_PCH_SPLIT(dev)) {
9576                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9577                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9578                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9579                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9580                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9581                 dev_priv->display.off = ironlake_crtc_off;
9582                 dev_priv->display.update_plane = ironlake_update_plane;
9583         } else if (IS_VALLEYVIEW(dev)) {
9584                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9585                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9586                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9587                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9588                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9589                 dev_priv->display.off = i9xx_crtc_off;
9590                 dev_priv->display.update_plane = i9xx_update_plane;
9591         } else {
9592                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9593                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9594                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9595                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9596                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9597                 dev_priv->display.off = i9xx_crtc_off;
9598                 dev_priv->display.update_plane = i9xx_update_plane;
9599         }
9600
9601         /* Returns the core display clock speed */
9602         if (IS_VALLEYVIEW(dev))
9603                 dev_priv->display.get_display_clock_speed =
9604                         valleyview_get_display_clock_speed;
9605         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9606                 dev_priv->display.get_display_clock_speed =
9607                         i945_get_display_clock_speed;
9608         else if (IS_I915G(dev))
9609                 dev_priv->display.get_display_clock_speed =
9610                         i915_get_display_clock_speed;
9611         else if (IS_I945GM(dev) || IS_845G(dev))
9612                 dev_priv->display.get_display_clock_speed =
9613                         i9xx_misc_get_display_clock_speed;
9614         else if (IS_PINEVIEW(dev))
9615                 dev_priv->display.get_display_clock_speed =
9616                         pnv_get_display_clock_speed;
9617         else if (IS_I915GM(dev))
9618                 dev_priv->display.get_display_clock_speed =
9619                         i915gm_get_display_clock_speed;
9620         else if (IS_I865G(dev))
9621                 dev_priv->display.get_display_clock_speed =
9622                         i865_get_display_clock_speed;
9623         else if (IS_I85X(dev))
9624                 dev_priv->display.get_display_clock_speed =
9625                         i855_get_display_clock_speed;
9626         else /* 852, 830 */
9627                 dev_priv->display.get_display_clock_speed =
9628                         i830_get_display_clock_speed;
9629
9630         if (HAS_PCH_SPLIT(dev)) {
9631                 if (IS_GEN5(dev)) {
9632                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9633                         dev_priv->display.write_eld = ironlake_write_eld;
9634                 } else if (IS_GEN6(dev)) {
9635                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9636                         dev_priv->display.write_eld = ironlake_write_eld;
9637                 } else if (IS_IVYBRIDGE(dev)) {
9638                         /* FIXME: detect B0+ stepping and use auto training */
9639                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9640                         dev_priv->display.write_eld = ironlake_write_eld;
9641                         dev_priv->display.modeset_global_resources =
9642                                 ivb_modeset_global_resources;
9643                 } else if (IS_HASWELL(dev)) {
9644                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9645                         dev_priv->display.write_eld = haswell_write_eld;
9646                         dev_priv->display.modeset_global_resources =
9647                                 haswell_modeset_global_resources;
9648                 }
9649         } else if (IS_G4X(dev)) {
9650                 dev_priv->display.write_eld = g4x_write_eld;
9651         }
9652
9653         /* Default just returns -ENODEV to indicate unsupported */
9654         dev_priv->display.queue_flip = intel_default_queue_flip;
9655
9656         switch (INTEL_INFO(dev)->gen) {
9657         case 2:
9658                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9659                 break;
9660
9661         case 3:
9662                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9663                 break;
9664
9665         case 4:
9666         case 5:
9667                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9668                 break;
9669
9670         case 6:
9671                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9672                 break;
9673         case 7:
9674                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9675                 break;
9676         }
9677 }
9678
9679 /*
9680  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9681  * resume, or other times.  This quirk makes sure that's the case for
9682  * affected systems.
9683  */
9684 static void quirk_pipea_force(struct drm_device *dev)
9685 {
9686         struct drm_i915_private *dev_priv = dev->dev_private;
9687
9688         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9689         DRM_INFO("applying pipe a force quirk\n");
9690 }
9691
9692 /*
9693  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9694  */
9695 static void quirk_ssc_force_disable(struct drm_device *dev)
9696 {
9697         struct drm_i915_private *dev_priv = dev->dev_private;
9698         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9699         DRM_INFO("applying lvds SSC disable quirk\n");
9700 }
9701
9702 /*
9703  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9704  * brightness value
9705  */
9706 static void quirk_invert_brightness(struct drm_device *dev)
9707 {
9708         struct drm_i915_private *dev_priv = dev->dev_private;
9709         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9710         DRM_INFO("applying inverted panel brightness quirk\n");
9711 }
9712
9713 /*
9714  * Some machines (Dell XPS13) suffer broken backlight controls if
9715  * BLM_PCH_PWM_ENABLE is set.
9716  */
9717 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9718 {
9719         struct drm_i915_private *dev_priv = dev->dev_private;
9720         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9721         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9722 }
9723
9724 struct intel_quirk {
9725         int device;
9726         int subsystem_vendor;
9727         int subsystem_device;
9728         void (*hook)(struct drm_device *dev);
9729 };
9730
9731 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9732 struct intel_dmi_quirk {
9733         void (*hook)(struct drm_device *dev);
9734         const struct dmi_system_id (*dmi_id_list)[];
9735 };
9736
9737 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9738 {
9739         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9740         return 1;
9741 }
9742
9743 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9744         {
9745                 .dmi_id_list = &(const struct dmi_system_id[]) {
9746                         {
9747                                 .callback = intel_dmi_reverse_brightness,
9748                                 .ident = "NCR Corporation",
9749                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9750                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9751                                 },
9752                         },
9753                         { }  /* terminating entry */
9754                 },
9755                 .hook = quirk_invert_brightness,
9756         },
9757 };
9758
9759 static struct intel_quirk intel_quirks[] = {
9760         /* HP Mini needs pipe A force quirk (LP: #322104) */
9761         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9762
9763         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9764         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9765
9766         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9767         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9768
9769         /* 830/845 need to leave pipe A & dpll A up */
9770         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9771         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9772
9773         /* Lenovo U160 cannot use SSC on LVDS */
9774         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9775
9776         /* Sony Vaio Y cannot use SSC on LVDS */
9777         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9778
9779         /* Acer Aspire 5734Z must invert backlight brightness */
9780         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9781
9782         /* Acer/eMachines G725 */
9783         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9784
9785         /* Acer/eMachines e725 */
9786         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9787
9788         /* Acer/Packard Bell NCL20 */
9789         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9790
9791         /* Acer Aspire 4736Z */
9792         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9793
9794         /* Dell XPS13 HD Sandy Bridge */
9795         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9796         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9797         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9798 };
9799
9800 static void intel_init_quirks(struct drm_device *dev)
9801 {
9802         struct pci_dev *d = dev->pdev;
9803         int i;
9804
9805         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9806                 struct intel_quirk *q = &intel_quirks[i];
9807
9808                 if (d->device == q->device &&
9809                     (d->subsystem_vendor == q->subsystem_vendor ||
9810                      q->subsystem_vendor == PCI_ANY_ID) &&
9811                     (d->subsystem_device == q->subsystem_device ||
9812                      q->subsystem_device == PCI_ANY_ID))
9813                         q->hook(dev);
9814         }
9815         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9816                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9817                         intel_dmi_quirks[i].hook(dev);
9818         }
9819 }
9820
9821 /* Disable the VGA plane that we never use */
9822 static void i915_disable_vga(struct drm_device *dev)
9823 {
9824         struct drm_i915_private *dev_priv = dev->dev_private;
9825         u8 sr1;
9826         u32 vga_reg = i915_vgacntrl_reg(dev);
9827
9828         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9829         outb(SR01, VGA_SR_INDEX);
9830         sr1 = inb(VGA_SR_DATA);
9831         outb(sr1 | 1<<5, VGA_SR_DATA);
9832         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9833         udelay(300);
9834
9835         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9836         POSTING_READ(vga_reg);
9837 }
9838
9839 void intel_modeset_init_hw(struct drm_device *dev)
9840 {
9841         intel_init_power_well(dev);
9842
9843         intel_prepare_ddi(dev);
9844
9845         intel_init_clock_gating(dev);
9846
9847         mutex_lock(&dev->struct_mutex);
9848         intel_enable_gt_powersave(dev);
9849         mutex_unlock(&dev->struct_mutex);
9850 }
9851
9852 void intel_modeset_suspend_hw(struct drm_device *dev)
9853 {
9854         intel_suspend_hw(dev);
9855 }
9856
9857 void intel_modeset_init(struct drm_device *dev)
9858 {
9859         struct drm_i915_private *dev_priv = dev->dev_private;
9860         int i, j, ret;
9861
9862         drm_mode_config_init(dev);
9863
9864         dev->mode_config.min_width = 0;
9865         dev->mode_config.min_height = 0;
9866
9867         dev->mode_config.preferred_depth = 24;
9868         dev->mode_config.prefer_shadow = 1;
9869
9870         dev->mode_config.funcs = &intel_mode_funcs;
9871
9872         intel_init_quirks(dev);
9873
9874         intel_init_pm(dev);
9875
9876         if (INTEL_INFO(dev)->num_pipes == 0)
9877                 return;
9878
9879         intel_init_display(dev);
9880
9881         if (IS_GEN2(dev)) {
9882                 dev->mode_config.max_width = 2048;
9883                 dev->mode_config.max_height = 2048;
9884         } else if (IS_GEN3(dev)) {
9885                 dev->mode_config.max_width = 4096;
9886                 dev->mode_config.max_height = 4096;
9887         } else {
9888                 dev->mode_config.max_width = 8192;
9889                 dev->mode_config.max_height = 8192;
9890         }
9891         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9892
9893         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9894                       INTEL_INFO(dev)->num_pipes,
9895                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9896
9897         for_each_pipe(i) {
9898                 intel_crtc_init(dev, i);
9899                 for (j = 0; j < dev_priv->num_plane; j++) {
9900                         ret = intel_plane_init(dev, i, j);
9901                         if (ret)
9902                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9903                                               pipe_name(i), sprite_name(i, j), ret);
9904                 }
9905         }
9906
9907         intel_cpu_pll_init(dev);
9908         intel_shared_dpll_init(dev);
9909
9910         /* Just disable it once at startup */
9911         i915_disable_vga(dev);
9912         intel_setup_outputs(dev);
9913
9914         /* Just in case the BIOS is doing something questionable. */
9915         intel_disable_fbc(dev);
9916 }
9917
9918 static void
9919 intel_connector_break_all_links(struct intel_connector *connector)
9920 {
9921         connector->base.dpms = DRM_MODE_DPMS_OFF;
9922         connector->base.encoder = NULL;
9923         connector->encoder->connectors_active = false;
9924         connector->encoder->base.crtc = NULL;
9925 }
9926
9927 static void intel_enable_pipe_a(struct drm_device *dev)
9928 {
9929         struct intel_connector *connector;
9930         struct drm_connector *crt = NULL;
9931         struct intel_load_detect_pipe load_detect_temp;
9932
9933         /* We can't just switch on the pipe A, we need to set things up with a
9934          * proper mode and output configuration. As a gross hack, enable pipe A
9935          * by enabling the load detect pipe once. */
9936         list_for_each_entry(connector,
9937                             &dev->mode_config.connector_list,
9938                             base.head) {
9939                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9940                         crt = &connector->base;
9941                         break;
9942                 }
9943         }
9944
9945         if (!crt)
9946                 return;
9947
9948         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9949                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9950
9951
9952 }
9953
9954 static bool
9955 intel_check_plane_mapping(struct intel_crtc *crtc)
9956 {
9957         struct drm_device *dev = crtc->base.dev;
9958         struct drm_i915_private *dev_priv = dev->dev_private;
9959         u32 reg, val;
9960
9961         if (INTEL_INFO(dev)->num_pipes == 1)
9962                 return true;
9963
9964         reg = DSPCNTR(!crtc->plane);
9965         val = I915_READ(reg);
9966
9967         if ((val & DISPLAY_PLANE_ENABLE) &&
9968             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9969                 return false;
9970
9971         return true;
9972 }
9973
9974 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9975 {
9976         struct drm_device *dev = crtc->base.dev;
9977         struct drm_i915_private *dev_priv = dev->dev_private;
9978         u32 reg;
9979
9980         /* Clear any frame start delays used for debugging left by the BIOS */
9981         reg = PIPECONF(crtc->config.cpu_transcoder);
9982         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9983
9984         /* We need to sanitize the plane -> pipe mapping first because this will
9985          * disable the crtc (and hence change the state) if it is wrong. Note
9986          * that gen4+ has a fixed plane -> pipe mapping.  */
9987         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9988                 struct intel_connector *connector;
9989                 bool plane;
9990
9991                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9992                               crtc->base.base.id);
9993
9994                 /* Pipe has the wrong plane attached and the plane is active.
9995                  * Temporarily change the plane mapping and disable everything
9996                  * ...  */
9997                 plane = crtc->plane;
9998                 crtc->plane = !plane;
9999                 dev_priv->display.crtc_disable(&crtc->base);
10000                 crtc->plane = plane;
10001
10002                 /* ... and break all links. */
10003                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10004                                     base.head) {
10005                         if (connector->encoder->base.crtc != &crtc->base)
10006                                 continue;
10007
10008                         intel_connector_break_all_links(connector);
10009                 }
10010
10011                 WARN_ON(crtc->active);
10012                 crtc->base.enabled = false;
10013         }
10014
10015         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10016             crtc->pipe == PIPE_A && !crtc->active) {
10017                 /* BIOS forgot to enable pipe A, this mostly happens after
10018                  * resume. Force-enable the pipe to fix this, the update_dpms
10019                  * call below we restore the pipe to the right state, but leave
10020                  * the required bits on. */
10021                 intel_enable_pipe_a(dev);
10022         }
10023
10024         /* Adjust the state of the output pipe according to whether we
10025          * have active connectors/encoders. */
10026         intel_crtc_update_dpms(&crtc->base);
10027
10028         if (crtc->active != crtc->base.enabled) {
10029                 struct intel_encoder *encoder;
10030
10031                 /* This can happen either due to bugs in the get_hw_state
10032                  * functions or because the pipe is force-enabled due to the
10033                  * pipe A quirk. */
10034                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10035                               crtc->base.base.id,
10036                               crtc->base.enabled ? "enabled" : "disabled",
10037                               crtc->active ? "enabled" : "disabled");
10038
10039                 crtc->base.enabled = crtc->active;
10040
10041                 /* Because we only establish the connector -> encoder ->
10042                  * crtc links if something is active, this means the
10043                  * crtc is now deactivated. Break the links. connector
10044                  * -> encoder links are only establish when things are
10045                  *  actually up, hence no need to break them. */
10046                 WARN_ON(crtc->active);
10047
10048                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10049                         WARN_ON(encoder->connectors_active);
10050                         encoder->base.crtc = NULL;
10051                 }
10052         }
10053 }
10054
10055 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10056 {
10057         struct intel_connector *connector;
10058         struct drm_device *dev = encoder->base.dev;
10059
10060         /* We need to check both for a crtc link (meaning that the
10061          * encoder is active and trying to read from a pipe) and the
10062          * pipe itself being active. */
10063         bool has_active_crtc = encoder->base.crtc &&
10064                 to_intel_crtc(encoder->base.crtc)->active;
10065
10066         if (encoder->connectors_active && !has_active_crtc) {
10067                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10068                               encoder->base.base.id,
10069                               drm_get_encoder_name(&encoder->base));
10070
10071                 /* Connector is active, but has no active pipe. This is
10072                  * fallout from our resume register restoring. Disable
10073                  * the encoder manually again. */
10074                 if (encoder->base.crtc) {
10075                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10076                                       encoder->base.base.id,
10077                                       drm_get_encoder_name(&encoder->base));
10078                         encoder->disable(encoder);
10079                 }
10080
10081                 /* Inconsistent output/port/pipe state happens presumably due to
10082                  * a bug in one of the get_hw_state functions. Or someplace else
10083                  * in our code, like the register restore mess on resume. Clamp
10084                  * things to off as a safer default. */
10085                 list_for_each_entry(connector,
10086                                     &dev->mode_config.connector_list,
10087                                     base.head) {
10088                         if (connector->encoder != encoder)
10089                                 continue;
10090
10091                         intel_connector_break_all_links(connector);
10092                 }
10093         }
10094         /* Enabled encoders without active connectors will be fixed in
10095          * the crtc fixup. */
10096 }
10097
10098 void i915_redisable_vga(struct drm_device *dev)
10099 {
10100         struct drm_i915_private *dev_priv = dev->dev_private;
10101         u32 vga_reg = i915_vgacntrl_reg(dev);
10102
10103         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10104                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10105                 i915_disable_vga(dev);
10106         }
10107 }
10108
10109 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10110 {
10111         struct drm_i915_private *dev_priv = dev->dev_private;
10112         enum pipe pipe;
10113         struct intel_crtc *crtc;
10114         struct intel_encoder *encoder;
10115         struct intel_connector *connector;
10116         int i;
10117
10118         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10119                             base.head) {
10120                 memset(&crtc->config, 0, sizeof(crtc->config));
10121
10122                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10123                                                                  &crtc->config);
10124
10125                 crtc->base.enabled = crtc->active;
10126
10127                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10128                               crtc->base.base.id,
10129                               crtc->active ? "enabled" : "disabled");
10130         }
10131
10132         /* FIXME: Smash this into the new shared dpll infrastructure. */
10133         if (HAS_DDI(dev))
10134                 intel_ddi_setup_hw_pll_state(dev);
10135
10136         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10137                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10138
10139                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10140                 pll->active = 0;
10141                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10142                                     base.head) {
10143                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10144                                 pll->active++;
10145                 }
10146                 pll->refcount = pll->active;
10147
10148                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10149                               pll->name, pll->refcount, pll->on);
10150         }
10151
10152         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10153                             base.head) {
10154                 pipe = 0;
10155
10156                 if (encoder->get_hw_state(encoder, &pipe)) {
10157                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10158                         encoder->base.crtc = &crtc->base;
10159                         if (encoder->get_config)
10160                                 encoder->get_config(encoder, &crtc->config);
10161                 } else {
10162                         encoder->base.crtc = NULL;
10163                 }
10164
10165                 encoder->connectors_active = false;
10166                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10167                               encoder->base.base.id,
10168                               drm_get_encoder_name(&encoder->base),
10169                               encoder->base.crtc ? "enabled" : "disabled",
10170                               pipe);
10171         }
10172
10173         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10174                             base.head) {
10175                 if (!crtc->active)
10176                         continue;
10177                 if (dev_priv->display.get_clock)
10178                         dev_priv->display.get_clock(crtc,
10179                                                     &crtc->config);
10180         }
10181
10182         list_for_each_entry(connector, &dev->mode_config.connector_list,
10183                             base.head) {
10184                 if (connector->get_hw_state(connector)) {
10185                         connector->base.dpms = DRM_MODE_DPMS_ON;
10186                         connector->encoder->connectors_active = true;
10187                         connector->base.encoder = &connector->encoder->base;
10188                 } else {
10189                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10190                         connector->base.encoder = NULL;
10191                 }
10192                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10193                               connector->base.base.id,
10194                               drm_get_connector_name(&connector->base),
10195                               connector->base.encoder ? "enabled" : "disabled");
10196         }
10197 }
10198
10199 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10200  * and i915 state tracking structures. */
10201 void intel_modeset_setup_hw_state(struct drm_device *dev,
10202                                   bool force_restore)
10203 {
10204         struct drm_i915_private *dev_priv = dev->dev_private;
10205         enum pipe pipe;
10206         struct drm_plane *plane;
10207         struct intel_crtc *crtc;
10208         struct intel_encoder *encoder;
10209         int i;
10210
10211         intel_modeset_readout_hw_state(dev);
10212
10213         /*
10214          * Now that we have the config, copy it to each CRTC struct
10215          * Note that this could go away if we move to using crtc_config
10216          * checking everywhere.
10217          */
10218         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10219                             base.head) {
10220                 if (crtc->active && i915_fastboot) {
10221                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10222
10223                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10224                                       crtc->base.base.id);
10225                         drm_mode_debug_printmodeline(&crtc->base.mode);
10226                 }
10227         }
10228
10229         /* HW state is read out, now we need to sanitize this mess. */
10230         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10231                             base.head) {
10232                 intel_sanitize_encoder(encoder);
10233         }
10234
10235         for_each_pipe(pipe) {
10236                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10237                 intel_sanitize_crtc(crtc);
10238                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10239         }
10240
10241         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10242                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10243
10244                 if (!pll->on || pll->active)
10245                         continue;
10246
10247                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10248
10249                 pll->disable(dev_priv, pll);
10250                 pll->on = false;
10251         }
10252
10253         if (force_restore) {
10254                 /*
10255                  * We need to use raw interfaces for restoring state to avoid
10256                  * checking (bogus) intermediate states.
10257                  */
10258                 for_each_pipe(pipe) {
10259                         struct drm_crtc *crtc =
10260                                 dev_priv->pipe_to_crtc_mapping[pipe];
10261
10262                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10263                                          crtc->fb);
10264                 }
10265                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10266                         intel_plane_restore(plane);
10267
10268                 i915_redisable_vga(dev);
10269         } else {
10270                 intel_modeset_update_staged_output_state(dev);
10271         }
10272
10273         intel_modeset_check_state(dev);
10274
10275         drm_mode_config_reset(dev);
10276 }
10277
10278 void intel_modeset_gem_init(struct drm_device *dev)
10279 {
10280         intel_modeset_init_hw(dev);
10281
10282         intel_setup_overlay(dev);
10283
10284         intel_modeset_setup_hw_state(dev, false);
10285 }
10286
10287 void intel_modeset_cleanup(struct drm_device *dev)
10288 {
10289         struct drm_i915_private *dev_priv = dev->dev_private;
10290         struct drm_crtc *crtc;
10291         struct intel_crtc *intel_crtc;
10292
10293         /*
10294          * Interrupts and polling as the first thing to avoid creating havoc.
10295          * Too much stuff here (turning of rps, connectors, ...) would
10296          * experience fancy races otherwise.
10297          */
10298         drm_irq_uninstall(dev);
10299         cancel_work_sync(&dev_priv->hotplug_work);
10300         /*
10301          * Due to the hpd irq storm handling the hotplug work can re-arm the
10302          * poll handlers. Hence disable polling after hpd handling is shut down.
10303          */
10304         drm_kms_helper_poll_fini(dev);
10305
10306         mutex_lock(&dev->struct_mutex);
10307
10308         intel_unregister_dsm_handler();
10309
10310         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10311                 /* Skip inactive CRTCs */
10312                 if (!crtc->fb)
10313                         continue;
10314
10315                 intel_crtc = to_intel_crtc(crtc);
10316                 intel_increase_pllclock(crtc);
10317         }
10318
10319         intel_disable_fbc(dev);
10320
10321         intel_disable_gt_powersave(dev);
10322
10323         ironlake_teardown_rc6(dev);
10324
10325         mutex_unlock(&dev->struct_mutex);
10326
10327         /* flush any delayed tasks or pending work */
10328         flush_scheduled_work();
10329
10330         /* destroy backlight, if any, before the connectors */
10331         intel_panel_destroy_backlight(dev);
10332
10333         drm_mode_config_cleanup(dev);
10334
10335         intel_cleanup_overlay(dev);
10336 }
10337
10338 /*
10339  * Return which encoder is currently attached for connector.
10340  */
10341 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10342 {
10343         return &intel_attached_encoder(connector)->base;
10344 }
10345
10346 void intel_connector_attach_encoder(struct intel_connector *connector,
10347                                     struct intel_encoder *encoder)
10348 {
10349         connector->encoder = encoder;
10350         drm_mode_connector_attach_encoder(&connector->base,
10351                                           &encoder->base);
10352 }
10353
10354 /*
10355  * set vga decode state - true == enable VGA decode
10356  */
10357 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10358 {
10359         struct drm_i915_private *dev_priv = dev->dev_private;
10360         u16 gmch_ctrl;
10361
10362         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10363         if (state)
10364                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10365         else
10366                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10367         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10368         return 0;
10369 }
10370
10371 struct intel_display_error_state {
10372
10373         u32 power_well_driver;
10374
10375         struct intel_cursor_error_state {
10376                 u32 control;
10377                 u32 position;
10378                 u32 base;
10379                 u32 size;
10380         } cursor[I915_MAX_PIPES];
10381
10382         struct intel_pipe_error_state {
10383                 enum transcoder cpu_transcoder;
10384                 u32 conf;
10385                 u32 source;
10386
10387                 u32 htotal;
10388                 u32 hblank;
10389                 u32 hsync;
10390                 u32 vtotal;
10391                 u32 vblank;
10392                 u32 vsync;
10393         } pipe[I915_MAX_PIPES];
10394
10395         struct intel_plane_error_state {
10396                 u32 control;
10397                 u32 stride;
10398                 u32 size;
10399                 u32 pos;
10400                 u32 addr;
10401                 u32 surface;
10402                 u32 tile_offset;
10403         } plane[I915_MAX_PIPES];
10404 };
10405
10406 struct intel_display_error_state *
10407 intel_display_capture_error_state(struct drm_device *dev)
10408 {
10409         drm_i915_private_t *dev_priv = dev->dev_private;
10410         struct intel_display_error_state *error;
10411         enum transcoder cpu_transcoder;
10412         int i;
10413
10414         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10415         if (error == NULL)
10416                 return NULL;
10417
10418         if (HAS_POWER_WELL(dev))
10419                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10420
10421         for_each_pipe(i) {
10422                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10423                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10424
10425                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10426                         error->cursor[i].control = I915_READ(CURCNTR(i));
10427                         error->cursor[i].position = I915_READ(CURPOS(i));
10428                         error->cursor[i].base = I915_READ(CURBASE(i));
10429                 } else {
10430                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10431                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10432                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10433                 }
10434
10435                 error->plane[i].control = I915_READ(DSPCNTR(i));
10436                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10437                 if (INTEL_INFO(dev)->gen <= 3) {
10438                         error->plane[i].size = I915_READ(DSPSIZE(i));
10439                         error->plane[i].pos = I915_READ(DSPPOS(i));
10440                 }
10441                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10442                         error->plane[i].addr = I915_READ(DSPADDR(i));
10443                 if (INTEL_INFO(dev)->gen >= 4) {
10444                         error->plane[i].surface = I915_READ(DSPSURF(i));
10445                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10446                 }
10447
10448                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10449                 error->pipe[i].source = I915_READ(PIPESRC(i));
10450                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10451                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10452                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10453                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10454                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10455                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10456         }
10457
10458         /* In the code above we read the registers without checking if the power
10459          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10460          * prevent the next I915_WRITE from detecting it and printing an error
10461          * message. */
10462         intel_uncore_clear_errors(dev);
10463
10464         return error;
10465 }
10466
10467 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10468
10469 void
10470 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10471                                 struct drm_device *dev,
10472                                 struct intel_display_error_state *error)
10473 {
10474         int i;
10475
10476         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10477         if (HAS_POWER_WELL(dev))
10478                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10479                            error->power_well_driver);
10480         for_each_pipe(i) {
10481                 err_printf(m, "Pipe [%d]:\n", i);
10482                 err_printf(m, "  CPU transcoder: %c\n",
10483                            transcoder_name(error->pipe[i].cpu_transcoder));
10484                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10485                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10486                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10487                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10488                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10489                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10490                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10491                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10492
10493                 err_printf(m, "Plane [%d]:\n", i);
10494                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10495                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10496                 if (INTEL_INFO(dev)->gen <= 3) {
10497                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10498                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10499                 }
10500                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10501                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10502                 if (INTEL_INFO(dev)->gen >= 4) {
10503                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10504                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10505                 }
10506
10507                 err_printf(m, "Cursor [%d]:\n", i);
10508                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10509                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10510                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10511         }
10512 }