drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79 };
  80
  81 /* Cursor formats */
  82 static const uint32_t intel_cursor_formats[] = {
  83         DRM_FORMAT_ARGB8888,
  84 };
  85
  86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87
  88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89                                 struct intel_crtc_state *pipe_config);
  90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91                                    struct intel_crtc_state *pipe_config);
  92
  93 static int intel_framebuffer_init(struct drm_device *dev,
  94                                   struct intel_framebuffer *ifb,
  95                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96                                   struct drm_i915_gem_object *obj);
  97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 100                                          struct intel_link_m_n *m_n,
 101                                          struct intel_link_m_n *m2_n2);
 102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 105 static void vlv_prepare_pll(struct intel_crtc *crtc,
 106                             const struct intel_crtc_state *pipe_config);
 107 static void chv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 114                            int num_connectors);
 115 static void skylake_pfit_enable(struct intel_crtc *crtc);
 116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 119
 120 typedef struct {
 121         int     min, max;
 122 } intel_range_t;
 123
 124 typedef struct {
 125         int     dot_limit;
 126         int     p2_slow, p2_fast;
 127 } intel_p2_t;
 128
 129 typedef struct intel_limit intel_limit_t;
 130 struct intel_limit {
 131         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 132         intel_p2_t          p2;
 133 };
 134
 135 /* returns HPLL frequency in kHz */
 136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 137 {
 138         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 139
 140         /* Obtain SKU information */
 141         mutex_lock(&dev_priv->sb_lock);
 142         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 143                 CCK_FUSE_HPLL_FREQ_MASK;
 144         mutex_unlock(&dev_priv->sb_lock);
 145
 146         return vco_freq[hpll_freq] * 1000;
 147 }
 148
 149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 150                                   const char *name, u32 reg)
 151 {
 152         u32 val;
 153         int divider;
 154
 155         if (dev_priv->hpll_freq == 0)
 156                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 157
 158         mutex_lock(&dev_priv->sb_lock);
 159         val = vlv_cck_read(dev_priv, reg);
 160         mutex_unlock(&dev_priv->sb_lock);
 161
 162         divider = val & CCK_FREQUENCY_VALUES;
 163
 164         WARN((val & CCK_FREQUENCY_STATUS) !=
 165              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 166              "%s change in progress\n", name);
 167
 168         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
 169 }
 170
 171 int
 172 intel_pch_rawclk(struct drm_device *dev)
 173 {
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175
 176         WARN_ON(!HAS_PCH_SPLIT(dev));
 177
 178         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 179 }
 180
 181 /* hrawclock is 1/4 the FSB frequency */
 182 int intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 215 {
 216         if (!IS_VALLEYVIEW(dev_priv))
 217                 return;
 218
 219         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 220                                                       CCK_CZ_CLOCK_CONTROL);
 221
 222         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 223 }
 224
 225 static inline u32 /* units of 100MHz */
 226 intel_fdi_link_freq(struct drm_device *dev)
 227 {
 228         if (IS_GEN5(dev)) {
 229                 struct drm_i915_private *dev_priv = dev->dev_private;
 230                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 231         } else
 232                 return 27;
 233 }
 234
 235 static const intel_limit_t intel_limits_i8xx_dac = {
 236         .dot = { .min = 25000, .max = 350000 },
 237         .vco = { .min = 908000, .max = 1512000 },
 238         .n = { .min = 2, .max = 16 },
 239         .m = { .min = 96, .max = 140 },
 240         .m1 = { .min = 18, .max = 26 },
 241         .m2 = { .min = 6, .max = 16 },
 242         .p = { .min = 4, .max = 128 },
 243         .p1 = { .min = 2, .max = 33 },
 244         .p2 = { .dot_limit = 165000,
 245                 .p2_slow = 4, .p2_fast = 2 },
 246 };
 247
 248 static const intel_limit_t intel_limits_i8xx_dvo = {
 249         .dot = { .min = 25000, .max = 350000 },
 250         .vco = { .min = 908000, .max = 1512000 },
 251         .n = { .min = 2, .max = 16 },
 252         .m = { .min = 96, .max = 140 },
 253         .m1 = { .min = 18, .max = 26 },
 254         .m2 = { .min = 6, .max = 16 },
 255         .p = { .min = 4, .max = 128 },
 256         .p1 = { .min = 2, .max = 33 },
 257         .p2 = { .dot_limit = 165000,
 258                 .p2_slow = 4, .p2_fast = 4 },
 259 };
 260
 261 static const intel_limit_t intel_limits_i8xx_lvds = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 908000, .max = 1512000 },
 264         .n = { .min = 2, .max = 16 },
 265         .m = { .min = 96, .max = 140 },
 266         .m1 = { .min = 18, .max = 26 },
 267         .m2 = { .min = 6, .max = 16 },
 268         .p = { .min = 4, .max = 128 },
 269         .p1 = { .min = 1, .max = 6 },
 270         .p2 = { .dot_limit = 165000,
 271                 .p2_slow = 14, .p2_fast = 7 },
 272 };
 273
 274 static const intel_limit_t intel_limits_i9xx_sdvo = {
 275         .dot = { .min = 20000, .max = 400000 },
 276         .vco = { .min = 1400000, .max = 2800000 },
 277         .n = { .min = 1, .max = 6 },
 278         .m = { .min = 70, .max = 120 },
 279         .m1 = { .min = 8, .max = 18 },
 280         .m2 = { .min = 3, .max = 7 },
 281         .p = { .min = 5, .max = 80 },
 282         .p1 = { .min = 1, .max = 8 },
 283         .p2 = { .dot_limit = 200000,
 284                 .p2_slow = 10, .p2_fast = 5 },
 285 };
 286
 287 static const intel_limit_t intel_limits_i9xx_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1400000, .max = 2800000 },
 290         .n = { .min = 1, .max = 6 },
 291         .m = { .min = 70, .max = 120 },
 292         .m1 = { .min = 8, .max = 18 },
 293         .m2 = { .min = 3, .max = 7 },
 294         .p = { .min = 7, .max = 98 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 7 },
 298 };
 299
 300
 301 static const intel_limit_t intel_limits_g4x_sdvo = {
 302         .dot = { .min = 25000, .max = 270000 },
 303         .vco = { .min = 1750000, .max = 3500000},
 304         .n = { .min = 1, .max = 4 },
 305         .m = { .min = 104, .max = 138 },
 306         .m1 = { .min = 17, .max = 23 },
 307         .m2 = { .min = 5, .max = 11 },
 308         .p = { .min = 10, .max = 30 },
 309         .p1 = { .min = 1, .max = 3},
 310         .p2 = { .dot_limit = 270000,
 311                 .p2_slow = 10,
 312                 .p2_fast = 10
 313         },
 314 };
 315
 316 static const intel_limit_t intel_limits_g4x_hdmi = {
 317         .dot = { .min = 22000, .max = 400000 },
 318         .vco = { .min = 1750000, .max = 3500000},
 319         .n = { .min = 1, .max = 4 },
 320         .m = { .min = 104, .max = 138 },
 321         .m1 = { .min = 16, .max = 23 },
 322         .m2 = { .min = 5, .max = 11 },
 323         .p = { .min = 5, .max = 80 },
 324         .p1 = { .min = 1, .max = 8},
 325         .p2 = { .dot_limit = 165000,
 326                 .p2_slow = 10, .p2_fast = 5 },
 327 };
 328
 329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 330         .dot = { .min = 20000, .max = 115000 },
 331         .vco = { .min = 1750000, .max = 3500000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 104, .max = 138 },
 334         .m1 = { .min = 17, .max = 23 },
 335         .m2 = { .min = 5, .max = 11 },
 336         .p = { .min = 28, .max = 112 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 0,
 339                 .p2_slow = 14, .p2_fast = 14
 340         },
 341 };
 342
 343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 344         .dot = { .min = 80000, .max = 224000 },
 345         .vco = { .min = 1750000, .max = 3500000 },
 346         .n = { .min = 1, .max = 3 },
 347         .m = { .min = 104, .max = 138 },
 348         .m1 = { .min = 17, .max = 23 },
 349         .m2 = { .min = 5, .max = 11 },
 350         .p = { .min = 14, .max = 42 },
 351         .p1 = { .min = 2, .max = 6 },
 352         .p2 = { .dot_limit = 0,
 353                 .p2_slow = 7, .p2_fast = 7
 354         },
 355 };
 356
 357 static const intel_limit_t intel_limits_pineview_sdvo = {
 358         .dot = { .min = 20000, .max = 400000},
 359         .vco = { .min = 1700000, .max = 3500000 },
 360         /* Pineview's Ncounter is a ring counter */
 361         .n = { .min = 3, .max = 6 },
 362         .m = { .min = 2, .max = 256 },
 363         /* Pineview only has one combined m divider, which we treat as m2. */
 364         .m1 = { .min = 0, .max = 0 },
 365         .m2 = { .min = 0, .max = 254 },
 366         .p = { .min = 5, .max = 80 },
 367         .p1 = { .min = 1, .max = 8 },
 368         .p2 = { .dot_limit = 200000,
 369                 .p2_slow = 10, .p2_fast = 5 },
 370 };
 371
 372 static const intel_limit_t intel_limits_pineview_lvds = {
 373         .dot = { .min = 20000, .max = 400000 },
 374         .vco = { .min = 1700000, .max = 3500000 },
 375         .n = { .min = 3, .max = 6 },
 376         .m = { .min = 2, .max = 256 },
 377         .m1 = { .min = 0, .max = 0 },
 378         .m2 = { .min = 0, .max = 254 },
 379         .p = { .min = 7, .max = 112 },
 380         .p1 = { .min = 1, .max = 8 },
 381         .p2 = { .dot_limit = 112000,
 382                 .p2_slow = 14, .p2_fast = 14 },
 383 };
 384
 385 /* Ironlake / Sandybridge
 386  *
 387  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 388  * the range value for them is (actual_value - 2).
 389  */
 390 static const intel_limit_t intel_limits_ironlake_dac = {
 391         .dot = { .min = 25000, .max = 350000 },
 392         .vco = { .min = 1760000, .max = 3510000 },
 393         .n = { .min = 1, .max = 5 },
 394         .m = { .min = 79, .max = 127 },
 395         .m1 = { .min = 12, .max = 22 },
 396         .m2 = { .min = 5, .max = 9 },
 397         .p = { .min = 5, .max = 80 },
 398         .p1 = { .min = 1, .max = 8 },
 399         .p2 = { .dot_limit = 225000,
 400                 .p2_slow = 10, .p2_fast = 5 },
 401 };
 402
 403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 404         .dot = { .min = 25000, .max = 350000 },
 405         .vco = { .min = 1760000, .max = 3510000 },
 406         .n = { .min = 1, .max = 3 },
 407         .m = { .min = 79, .max = 118 },
 408         .m1 = { .min = 12, .max = 22 },
 409         .m2 = { .min = 5, .max = 9 },
 410         .p = { .min = 28, .max = 112 },
 411         .p1 = { .min = 2, .max = 8 },
 412         .p2 = { .dot_limit = 225000,
 413                 .p2_slow = 14, .p2_fast = 14 },
 414 };
 415
 416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 417         .dot = { .min = 25000, .max = 350000 },
 418         .vco = { .min = 1760000, .max = 3510000 },
 419         .n = { .min = 1, .max = 3 },
 420         .m = { .min = 79, .max = 127 },
 421         .m1 = { .min = 12, .max = 22 },
 422         .m2 = { .min = 5, .max = 9 },
 423         .p = { .min = 14, .max = 56 },
 424         .p1 = { .min = 2, .max = 8 },
 425         .p2 = { .dot_limit = 225000,
 426                 .p2_slow = 7, .p2_fast = 7 },
 427 };
 428
 429 /* LVDS 100mhz refclk limits. */
 430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 431         .dot = { .min = 25000, .max = 350000 },
 432         .vco = { .min = 1760000, .max = 3510000 },
 433         .n = { .min = 1, .max = 2 },
 434         .m = { .min = 79, .max = 126 },
 435         .m1 = { .min = 12, .max = 22 },
 436         .m2 = { .min = 5, .max = 9 },
 437         .p = { .min = 28, .max = 112 },
 438         .p1 = { .min = 2, .max = 8 },
 439         .p2 = { .dot_limit = 225000,
 440                 .p2_slow = 14, .p2_fast = 14 },
 441 };
 442
 443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 444         .dot = { .min = 25000, .max = 350000 },
 445         .vco = { .min = 1760000, .max = 3510000 },
 446         .n = { .min = 1, .max = 3 },
 447         .m = { .min = 79, .max = 126 },
 448         .m1 = { .min = 12, .max = 22 },
 449         .m2 = { .min = 5, .max = 9 },
 450         .p = { .min = 14, .max = 42 },
 451         .p1 = { .min = 2, .max = 6 },
 452         .p2 = { .dot_limit = 225000,
 453                 .p2_slow = 7, .p2_fast = 7 },
 454 };
 455
 456 static const intel_limit_t intel_limits_vlv = {
 457          /*
 458           * These are the data rate limits (measured in fast clocks)
 459           * since those are the strictest limits we have. The fast
 460           * clock and actual rate limits are more relaxed, so checking
 461           * them would make no difference.
 462           */
 463         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 464         .vco = { .min = 4000000, .max = 6000000 },
 465         .n = { .min = 1, .max = 7 },
 466         .m1 = { .min = 2, .max = 3 },
 467         .m2 = { .min = 11, .max = 156 },
 468         .p1 = { .min = 2, .max = 3 },
 469         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 470 };
 471
 472 static const intel_limit_t intel_limits_chv = {
 473         /*
 474          * These are the data rate limits (measured in fast clocks)
 475          * since those are the strictest limits we have.  The fast
 476          * clock and actual rate limits are more relaxed, so checking
 477          * them would make no difference.
 478          */
 479         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 480         .vco = { .min = 4800000, .max = 6480000 },
 481         .n = { .min = 1, .max = 1 },
 482         .m1 = { .min = 2, .max = 2 },
 483         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 484         .p1 = { .min = 2, .max = 4 },
 485         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 486 };
 487
 488 static const intel_limit_t intel_limits_bxt = {
 489         /* FIXME: find real dot limits */
 490         .dot = { .min = 0, .max = INT_MAX },
 491         .vco = { .min = 4800000, .max = 6700000 },
 492         .n = { .min = 1, .max = 1 },
 493         .m1 = { .min = 2, .max = 2 },
 494         /* FIXME: find real m2 limits */
 495         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 496         .p1 = { .min = 2, .max = 4 },
 497         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 498 };
 499
 500 static bool
 501 needs_modeset(struct drm_crtc_state *state)
 502 {
 503         return drm_atomic_crtc_needs_modeset(state);
 504 }
 505
 506 /**
 507  * Returns whether any output on the specified pipe is of the specified type
 508  */
 509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 510 {
 511         struct drm_device *dev = crtc->base.dev;
 512         struct intel_encoder *encoder;
 513
 514         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 515                 if (encoder->type == type)
 516                         return true;
 517
 518         return false;
 519 }
 520
 521 /**
 522  * Returns whether any output on the specified pipe will have the specified
 523  * type after a staged modeset is complete, i.e., the same as
 524  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 525  * encoder->crtc.
 526  */
 527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 528                                       int type)
 529 {
 530         struct drm_atomic_state *state = crtc_state->base.state;
 531         struct drm_connector *connector;
 532         struct drm_connector_state *connector_state;
 533         struct intel_encoder *encoder;
 534         int i, num_connectors = 0;
 535
 536         for_each_connector_in_state(state, connector, connector_state, i) {
 537                 if (connector_state->crtc != crtc_state->base.crtc)
 538                         continue;
 539
 540                 num_connectors++;
 541
 542                 encoder = to_intel_encoder(connector_state->best_encoder);
 543                 if (encoder->type == type)
 544                         return true;
 545         }
 546
 547         WARN_ON(num_connectors == 0);
 548
 549         return false;
 550 }
 551
 552 static const intel_limit_t *
 553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 554 {
 555         struct drm_device *dev = crtc_state->base.crtc->dev;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 559                 if (intel_is_dual_link_lvds(dev)) {
 560                         if (refclk == 100000)
 561                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 562                         else
 563                                 limit = &intel_limits_ironlake_dual_lvds;
 564                 } else {
 565                         if (refclk == 100000)
 566                                 limit = &intel_limits_ironlake_single_lvds_100m;
 567                         else
 568                                 limit = &intel_limits_ironlake_single_lvds;
 569                 }
 570         } else
 571                 limit = &intel_limits_ironlake_dac;
 572
 573         return limit;
 574 }
 575
 576 static const intel_limit_t *
 577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 578 {
 579         struct drm_device *dev = crtc_state->base.crtc->dev;
 580         const intel_limit_t *limit;
 581
 582         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 583                 if (intel_is_dual_link_lvds(dev))
 584                         limit = &intel_limits_g4x_dual_channel_lvds;
 585                 else
 586                         limit = &intel_limits_g4x_single_channel_lvds;
 587         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 588                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 589                 limit = &intel_limits_g4x_hdmi;
 590         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 591                 limit = &intel_limits_g4x_sdvo;
 592         } else /* The option is for other outputs */
 593                 limit = &intel_limits_i9xx_sdvo;
 594
 595         return limit;
 596 }
 597
 598 static const intel_limit_t *
 599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 600 {
 601         struct drm_device *dev = crtc_state->base.crtc->dev;
 602         const intel_limit_t *limit;
 603
 604         if (IS_BROXTON(dev))
 605                 limit = &intel_limits_bxt;
 606         else if (HAS_PCH_SPLIT(dev))
 607                 limit = intel_ironlake_limit(crtc_state, refclk);
 608         else if (IS_G4X(dev)) {
 609                 limit = intel_g4x_limit(crtc_state);
 610         } else if (IS_PINEVIEW(dev)) {
 611                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 612                         limit = &intel_limits_pineview_lvds;
 613                 else
 614                         limit = &intel_limits_pineview_sdvo;
 615         } else if (IS_CHERRYVIEW(dev)) {
 616                 limit = &intel_limits_chv;
 617         } else if (IS_VALLEYVIEW(dev)) {
 618                 limit = &intel_limits_vlv;
 619         } else if (!IS_GEN2(dev)) {
 620                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 621                         limit = &intel_limits_i9xx_lvds;
 622                 else
 623                         limit = &intel_limits_i9xx_sdvo;
 624         } else {
 625                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 626                         limit = &intel_limits_i8xx_lvds;
 627                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 628                         limit = &intel_limits_i8xx_dvo;
 629                 else
 630                         limit = &intel_limits_i8xx_dac;
 631         }
 632         return limit;
 633 }
 634
 635 /*
 636  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 637  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 638  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 639  * The helpers' return value is the rate of the clock that is fed to the
 640  * display engine's pipe which can be the above fast dot clock rate or a
 641  * divided-down version of it.
 642  */
 643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 645 {
 646         clock->m = clock->m2 + 2;
 647         clock->p = clock->p1 * clock->p2;
 648         if (WARN_ON(clock->n == 0 || clock->p == 0))
 649                 return 0;
 650         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 651         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 652
 653         return clock->dot;
 654 }
 655
 656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 657 {
 658         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 659 }
 660
 661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 662 {
 663         clock->m = i9xx_dpll_compute_m(clock);
 664         clock->p = clock->p1 * clock->p2;
 665         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 666                 return 0;
 667         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 668         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 669
 670         return clock->dot;
 671 }
 672
 673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 674 {
 675         clock->m = clock->m1 * clock->m2;
 676         clock->p = clock->p1 * clock->p2;
 677         if (WARN_ON(clock->n == 0 || clock->p == 0))
 678                 return 0;
 679         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 680         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 681
 682         return clock->dot / 5;
 683 }
 684
 685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 686 {
 687         clock->m = clock->m1 * clock->m2;
 688         clock->p = clock->p1 * clock->p2;
 689         if (WARN_ON(clock->n == 0 || clock->p == 0))
 690                 return 0;
 691         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 692                         clock->n << 22);
 693         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 694
 695         return clock->dot / 5;
 696 }
 697
 698 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 699 /**
 700  * Returns whether the given set of divisors are valid for a given refclk with
 701  * the given connectors.
 702  */
 703
 704 static bool intel_PLL_is_valid(struct drm_device *dev,
 705                                const intel_limit_t *limit,
 706                                const intel_clock_t *clock)
 707 {
 708         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 709                 INTELPllInvalid("n out of range\n");
 710         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 711                 INTELPllInvalid("p1 out of range\n");
 712         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 713                 INTELPllInvalid("m2 out of range\n");
 714         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 715                 INTELPllInvalid("m1 out of range\n");
 716
 717         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 718                 if (clock->m1 <= clock->m2)
 719                         INTELPllInvalid("m1 <= m2\n");
 720
 721         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 722                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 723                         INTELPllInvalid("p out of range\n");
 724                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 725                         INTELPllInvalid("m out of range\n");
 726         }
 727
 728         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 729                 INTELPllInvalid("vco out of range\n");
 730         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 731          * connector, etc., rather than just a single range.
 732          */
 733         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 734                 INTELPllInvalid("dot out of range\n");
 735
 736         return true;
 737 }
 738
 739 static int
 740 i9xx_select_p2_div(const intel_limit_t *limit,
 741                    const struct intel_crtc_state *crtc_state,
 742                    int target)
 743 {
 744         struct drm_device *dev = crtc_state->base.crtc->dev;
 745
 746         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 747                 /*
 748                  * For LVDS just rely on its current settings for dual-channel.
 749                  * We haven't figured out how to reliably set up different
 750                  * single/dual channel state, if we even can.
 751                  */
 752                 if (intel_is_dual_link_lvds(dev))
 753                         return limit->p2.p2_fast;
 754                 else
 755                         return limit->p2.p2_slow;
 756         } else {
 757                 if (target < limit->p2.dot_limit)
 758                         return limit->p2.p2_slow;
 759                 else
 760                         return limit->p2.p2_fast;
 761         }
 762 }
 763
 764 static bool
 765 i9xx_find_best_dpll(const intel_limit_t *limit,
 766                     struct intel_crtc_state *crtc_state,
 767                     int target, int refclk, intel_clock_t *match_clock,
 768                     intel_clock_t *best_clock)
 769 {
 770         struct drm_device *dev = crtc_state->base.crtc->dev;
 771         intel_clock_t clock;
 772         int err = target;
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775
 776         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 777
 778         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 779              clock.m1++) {
 780                 for (clock.m2 = limit->m2.min;
 781                      clock.m2 <= limit->m2.max; clock.m2++) {
 782                         if (clock.m2 >= clock.m1)
 783                                 break;
 784                         for (clock.n = limit->n.min;
 785                              clock.n <= limit->n.max; clock.n++) {
 786                                 for (clock.p1 = limit->p1.min;
 787                                         clock.p1 <= limit->p1.max; clock.p1++) {
 788                                         int this_err;
 789
 790                                         i9xx_calc_dpll_params(refclk, &clock);
 791                                         if (!intel_PLL_is_valid(dev, limit,
 792                                                                 &clock))
 793                                                 continue;
 794                                         if (match_clock &&
 795                                             clock.p != match_clock->p)
 796                                                 continue;
 797
 798                                         this_err = abs(clock.dot - target);
 799                                         if (this_err < err) {
 800                                                 *best_clock = clock;
 801                                                 err = this_err;
 802                                         }
 803                                 }
 804                         }
 805                 }
 806         }
 807
 808         return (err != target);
 809 }
 810
 811 static bool
 812 pnv_find_best_dpll(const intel_limit_t *limit,
 813                    struct intel_crtc_state *crtc_state,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc_state->base.crtc->dev;
 818         intel_clock_t clock;
 819         int err = target;
 820
 821         memset(best_clock, 0, sizeof(*best_clock));
 822
 823         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 824
 825         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 826              clock.m1++) {
 827                 for (clock.m2 = limit->m2.min;
 828                      clock.m2 <= limit->m2.max; clock.m2++) {
 829                         for (clock.n = limit->n.min;
 830                              clock.n <= limit->n.max; clock.n++) {
 831                                 for (clock.p1 = limit->p1.min;
 832                                         clock.p1 <= limit->p1.max; clock.p1++) {
 833                                         int this_err;
 834
 835                                         pnv_calc_dpll_params(refclk, &clock);
 836                                         if (!intel_PLL_is_valid(dev, limit,
 837                                                                 &clock))
 838                                                 continue;
 839                                         if (match_clock &&
 840                                             clock.p != match_clock->p)
 841                                                 continue;
 842
 843                                         this_err = abs(clock.dot - target);
 844                                         if (this_err < err) {
 845                                                 *best_clock = clock;
 846                                                 err = this_err;
 847                                         }
 848                                 }
 849                         }
 850                 }
 851         }
 852
 853         return (err != target);
 854 }
 855
 856 static bool
 857 g4x_find_best_dpll(const intel_limit_t *limit,
 858                    struct intel_crtc_state *crtc_state,
 859                    int target, int refclk, intel_clock_t *match_clock,
 860                    intel_clock_t *best_clock)
 861 {
 862         struct drm_device *dev = crtc_state->base.crtc->dev;
 863         intel_clock_t clock;
 864         int max_n;
 865         bool found = false;
 866         /* approximately equals target * 0.00585 */
 867         int err_most = (target >> 8) + (target >> 9);
 868
 869         memset(best_clock, 0, sizeof(*best_clock));
 870
 871         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 872
 873         max_n = limit->n.max;
 874         /* based on hardware requirement, prefer smaller n to precision */
 875         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 876                 /* based on hardware requirement, prefere larger m1,m2 */
 877                 for (clock.m1 = limit->m1.max;
 878                      clock.m1 >= limit->m1.min; clock.m1--) {
 879                         for (clock.m2 = limit->m2.max;
 880                              clock.m2 >= limit->m2.min; clock.m2--) {
 881                                 for (clock.p1 = limit->p1.max;
 882                                      clock.p1 >= limit->p1.min; clock.p1--) {
 883                                         int this_err;
 884
 885                                         i9xx_calc_dpll_params(refclk, &clock);
 886                                         if (!intel_PLL_is_valid(dev, limit,
 887                                                                 &clock))
 888                                                 continue;
 889
 890                                         this_err = abs(clock.dot - target);
 891                                         if (this_err < err_most) {
 892                                                 *best_clock = clock;
 893                                                 err_most = this_err;
 894                                                 max_n = clock.n;
 895                                                 found = true;
 896                                         }
 897                                 }
 898                         }
 899                 }
 900         }
 901         return found;
 902 }
 903
 904 /*
 905  * Check if the calculated PLL configuration is more optimal compared to the
 906  * best configuration and error found so far. Return the calculated error.
 907  */
 908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 909                                const intel_clock_t *calculated_clock,
 910                                const intel_clock_t *best_clock,
 911                                unsigned int best_error_ppm,
 912                                unsigned int *error_ppm)
 913 {
 914         /*
 915          * For CHV ignore the error and consider only the P value.
 916          * Prefer a bigger P value based on HW requirements.
 917          */
 918         if (IS_CHERRYVIEW(dev)) {
 919                 *error_ppm = 0;
 920
 921                 return calculated_clock->p > best_clock->p;
 922         }
 923
 924         if (WARN_ON_ONCE(!target_freq))
 925                 return false;
 926
 927         *error_ppm = div_u64(1000000ULL *
 928                                 abs(target_freq - calculated_clock->dot),
 929                              target_freq);
 930         /*
 931          * Prefer a better P value over a better (smaller) error if the error
 932          * is small. Ensure this preference for future configurations too by
 933          * setting the error to 0.
 934          */
 935         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 936                 *error_ppm = 0;
 937
 938                 return true;
 939         }
 940
 941         return *error_ppm + 10 < best_error_ppm;
 942 }
 943
 944 static bool
 945 vlv_find_best_dpll(const intel_limit_t *limit,
 946                    struct intel_crtc_state *crtc_state,
 947                    int target, int refclk, intel_clock_t *match_clock,
 948                    intel_clock_t *best_clock)
 949 {
 950         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 951         struct drm_device *dev = crtc->base.dev;
 952         intel_clock_t clock;
 953         unsigned int bestppm = 1000000;
 954         /* min update 19.2 MHz */
 955         int max_n = min(limit->n.max, refclk / 19200);
 956         bool found = false;
 957
 958         target *= 5; /* fast clock */
 959
 960         memset(best_clock, 0, sizeof(*best_clock));
 961
 962         /* based on hardware requirement, prefer smaller n to precision */
 963         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 964                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 965                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 966                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 967                                 clock.p = clock.p1 * clock.p2;
 968                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 969                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 970                                         unsigned int ppm;
 971
 972                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 973                                                                      refclk * clock.m1);
 974
 975                                         vlv_calc_dpll_params(refclk, &clock);
 976
 977                                         if (!intel_PLL_is_valid(dev, limit,
 978                                                                 &clock))
 979                                                 continue;
 980
 981                                         if (!vlv_PLL_is_optimal(dev, target,
 982                                                                 &clock,
 983                                                                 best_clock,
 984                                                                 bestppm, &ppm))
 985                                                 continue;
 986
 987                                         *best_clock = clock;
 988                                         bestppm = ppm;
 989                                         found = true;
 990                                 }
 991                         }
 992                 }
 993         }
 994
 995         return found;
 996 }
 997
 998 static bool
 999 chv_find_best_dpll(const intel_limit_t *limit,
1000                    struct intel_crtc_state *crtc_state,
1001                    int target, int refclk, intel_clock_t *match_clock,
1002                    intel_clock_t *best_clock)
1003 {
1004         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005         struct drm_device *dev = crtc->base.dev;
1006         unsigned int best_error_ppm;
1007         intel_clock_t clock;
1008         uint64_t m2;
1009         int found = false;
1010
1011         memset(best_clock, 0, sizeof(*best_clock));
1012         best_error_ppm = 1000000;
1013
1014         /*
1015          * Based on hardware doc, the n always set to 1, and m1 always
1016          * set to 2.  If requires to support 200Mhz refclk, we need to
1017          * revisit this because n may not 1 anymore.
1018          */
1019         clock.n = 1, clock.m1 = 2;
1020         target *= 5;    /* fast clock */
1021
1022         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023                 for (clock.p2 = limit->p2.p2_fast;
1024                                 clock.p2 >= limit->p2.p2_slow;
1025                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026                         unsigned int error_ppm;
1027
1028                         clock.p = clock.p1 * clock.p2;
1029
1030                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031                                         clock.n) << 22, refclk * clock.m1);
1032
1033                         if (m2 > INT_MAX/clock.m1)
1034                                 continue;
1035
1036                         clock.m2 = m2;
1037
1038                         chv_calc_dpll_params(refclk, &clock);
1039
1040                         if (!intel_PLL_is_valid(dev, limit, &clock))
1041                                 continue;
1042
1043                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044                                                 best_error_ppm, &error_ppm))
1045                                 continue;
1046
1047                         *best_clock = clock;
1048                         best_error_ppm = error_ppm;
1049                         found = true;
1050                 }
1051         }
1052
1053         return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057                         intel_clock_t *best_clock)
1058 {
1059         int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062                                   target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069         /* Be paranoid as we can arrive here with only partial
1070          * state retrieved from the hardware during setup.
1071          *
1072          * We can ditch the adjusted_mode.crtc_clock check as soon
1073          * as Haswell has gained clock readout/fastboot support.
1074          *
1075          * We can ditch the crtc->primary->fb check as soon as we can
1076          * properly reconstruct framebuffers.
1077          *
1078          * FIXME: The intel_crtc->active here should be switched to
1079          * crtc->state->active once we have proper CRTC states wired up
1080          * for atomic.
1081          */
1082         return intel_crtc->active && crtc->primary->state->fb &&
1083                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087                                              enum pipe pipe)
1088 {
1089         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092         return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097         struct drm_i915_private *dev_priv = dev->dev_private;
1098         u32 reg = PIPEDSL(pipe);
1099         u32 line1, line2;
1100         u32 line_mask;
1101
1102         if (IS_GEN2(dev))
1103                 line_mask = DSL_LINEMASK_GEN2;
1104         else
1105                 line_mask = DSL_LINEMASK_GEN3;
1106
1107         line1 = I915_READ(reg) & line_mask;
1108         msleep(5);
1109         line2 = I915_READ(reg) & line_mask;
1110
1111         return line1 == line2;
1112 }
1113
1114 /*
1115  * intel_wait_for_pipe_off - wait for pipe to turn off
1116  * @crtc: crtc whose pipe to wait for
1117  *
1118  * After disabling a pipe, we can't wait for vblank in the usual way,
1119  * spinning on the vblank interrupt status bit, since we won't actually
1120  * see an interrupt when the pipe is disabled.
1121  *
1122  * On Gen4 and above:
1123  *   wait for the pipe register state bit to turn off
1124  *
1125  * Otherwise:
1126  *   wait for the display line value to settle (it usually
1127  *   ends up stopping at the start of the next frame).
1128  *
1129  */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132         struct drm_device *dev = crtc->base.dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135         enum pipe pipe = crtc->pipe;
1136
1137         if (INTEL_INFO(dev)->gen >= 4) {
1138                 int reg = PIPECONF(cpu_transcoder);
1139
1140                 /* Wait for the Pipe State to go off */
1141                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142                              100))
1143                         WARN(1, "pipe_off wait timed out\n");
1144         } else {
1145                 /* Wait for the display line to settle */
1146                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147                         WARN(1, "pipe_off wait timed out\n");
1148         }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153         return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158                 enum pipe pipe, bool state)
1159 {
1160         int reg;
1161         u32 val;
1162         bool cur_state;
1163
1164         reg = DPLL(pipe);
1165         val = I915_READ(reg);
1166         cur_state = !!(val & DPLL_VCO_ENABLE);
1167         I915_STATE_WARN(cur_state != state,
1168              "PLL state assertion failure (expected %s, current %s)\n",
1169              state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175         u32 val;
1176         bool cur_state;
1177
1178         mutex_lock(&dev_priv->sb_lock);
1179         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180         mutex_unlock(&dev_priv->sb_lock);
1181
1182         cur_state = val & DSI_PLL_VCO_EN;
1183         I915_STATE_WARN(cur_state != state,
1184              "DSI PLL state assertion failure (expected %s, current %s)\n",
1185              state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195         if (crtc->config->shared_dpll < 0)
1196                 return NULL;
1197
1198         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203                         struct intel_shared_dpll *pll,
1204                         bool state)
1205 {
1206         bool cur_state;
1207         struct intel_dpll_hw_state hw_state;
1208
1209         if (WARN (!pll,
1210                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1211                 return;
1212
1213         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214         I915_STATE_WARN(cur_state != state,
1215              "%s assertion failure (expected %s, current %s)\n",
1216              pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220                           enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226                                                                       pipe);
1227
1228         if (HAS_DDI(dev_priv->dev)) {
1229                 /* DDI does not have a specific FDI_TX register */
1230                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1231                 val = I915_READ(reg);
1232                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1233         } else {
1234                 reg = FDI_TX_CTL(pipe);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & FDI_TX_ENABLE);
1237         }
1238         I915_STATE_WARN(cur_state != state,
1239              "FDI TX state assertion failure (expected %s, current %s)\n",
1240              state_string(state), state_string(cur_state));
1241 }
1242 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1244
1245 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246                           enum pipe pipe, bool state)
1247 {
1248         int reg;
1249         u32 val;
1250         bool cur_state;
1251
1252         reg = FDI_RX_CTL(pipe);
1253         val = I915_READ(reg);
1254         cur_state = !!(val & FDI_RX_ENABLE);
1255         I915_STATE_WARN(cur_state != state,
1256              "FDI RX state assertion failure (expected %s, current %s)\n",
1257              state_string(state), state_string(cur_state));
1258 }
1259 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1261
1262 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263                                       enum pipe pipe)
1264 {
1265         int reg;
1266         u32 val;
1267
1268         /* ILK FDI PLL is always enabled */
1269         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1270                 return;
1271
1272         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1273         if (HAS_DDI(dev_priv->dev))
1274                 return;
1275
1276         reg = FDI_TX_CTL(pipe);
1277         val = I915_READ(reg);
1278         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1279 }
1280
1281 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282                        enum pipe pipe, bool state)
1283 {
1284         int reg;
1285         u32 val;
1286         bool cur_state;
1287
1288         reg = FDI_RX_CTL(pipe);
1289         val = I915_READ(reg);
1290         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1291         I915_STATE_WARN(cur_state != state,
1292              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293              state_string(state), state_string(cur_state));
1294 }
1295
1296 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1297                            enum pipe pipe)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         int pp_reg;
1301         u32 val;
1302         enum pipe panel_pipe = PIPE_A;
1303         bool locked = true;
1304
1305         if (WARN_ON(HAS_DDI(dev)))
1306                 return;
1307
1308         if (HAS_PCH_SPLIT(dev)) {
1309                 u32 port_sel;
1310
1311                 pp_reg = PCH_PP_CONTROL;
1312                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1313
1314                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316                         panel_pipe = PIPE_B;
1317                 /* XXX: else fix for eDP */
1318         } else if (IS_VALLEYVIEW(dev)) {
1319                 /* presumably write lock depends on pipe, not port select */
1320                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1321                 panel_pipe = pipe;
1322         } else {
1323                 pp_reg = PP_CONTROL;
1324                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325                         panel_pipe = PIPE_B;
1326         }
1327
1328         val = I915_READ(pp_reg);
1329         if (!(val & PANEL_POWER_ON) ||
1330             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1331                 locked = false;
1332
1333         I915_STATE_WARN(panel_pipe == pipe && locked,
1334              "panel assertion failure, pipe %c regs locked\n",
1335              pipe_name(pipe));
1336 }
1337
1338 static void assert_cursor(struct drm_i915_private *dev_priv,
1339                           enum pipe pipe, bool state)
1340 {
1341         struct drm_device *dev = dev_priv->dev;
1342         bool cur_state;
1343
1344         if (IS_845G(dev) || IS_I865G(dev))
1345                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1346         else
1347                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1348
1349         I915_STATE_WARN(cur_state != state,
1350              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351              pipe_name(pipe), state_string(state), state_string(cur_state));
1352 }
1353 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1355
1356 void assert_pipe(struct drm_i915_private *dev_priv,
1357                  enum pipe pipe, bool state)
1358 {
1359         int reg;
1360         u32 val;
1361         bool cur_state;
1362         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1363                                                                       pipe);
1364
1365         /* if we need the pipe quirk it must be always on */
1366         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1368                 state = true;
1369
1370         if (!intel_display_power_is_enabled(dev_priv,
1371                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1372                 cur_state = false;
1373         } else {
1374                 reg = PIPECONF(cpu_transcoder);
1375                 val = I915_READ(reg);
1376                 cur_state = !!(val & PIPECONF_ENABLE);
1377         }
1378
1379         I915_STATE_WARN(cur_state != state,
1380              "pipe %c assertion failure (expected %s, current %s)\n",
1381              pipe_name(pipe), state_string(state), state_string(cur_state));
1382 }
1383
1384 static void assert_plane(struct drm_i915_private *dev_priv,
1385                          enum plane plane, bool state)
1386 {
1387         int reg;
1388         u32 val;
1389         bool cur_state;
1390
1391         reg = DSPCNTR(plane);
1392         val = I915_READ(reg);
1393         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1394         I915_STATE_WARN(cur_state != state,
1395              "plane %c assertion failure (expected %s, current %s)\n",
1396              plane_name(plane), state_string(state), state_string(cur_state));
1397 }
1398
1399 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1401
1402 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1403                                    enum pipe pipe)
1404 {
1405         struct drm_device *dev = dev_priv->dev;
1406         int reg, i;
1407         u32 val;
1408         int cur_pipe;
1409
1410         /* Primary planes are fixed to pipes on gen4+ */
1411         if (INTEL_INFO(dev)->gen >= 4) {
1412                 reg = DSPCNTR(pipe);
1413                 val = I915_READ(reg);
1414                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1415                      "plane %c assertion failure, should be disabled but not\n",
1416                      plane_name(pipe));
1417                 return;
1418         }
1419
1420         /* Need to check both planes against the pipe */
1421         for_each_pipe(dev_priv, i) {
1422                 reg = DSPCNTR(i);
1423                 val = I915_READ(reg);
1424                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425                         DISPPLANE_SEL_PIPE_SHIFT;
1426                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1427                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428                      plane_name(i), pipe_name(pipe));
1429         }
1430 }
1431
1432 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1433                                     enum pipe pipe)
1434 {
1435         struct drm_device *dev = dev_priv->dev;
1436         int reg, sprite;
1437         u32 val;
1438
1439         if (INTEL_INFO(dev)->gen >= 9) {
1440                 for_each_sprite(dev_priv, pipe, sprite) {
1441                         val = I915_READ(PLANE_CTL(pipe, sprite));
1442                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1443                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444                              sprite, pipe_name(pipe));
1445                 }
1446         } else if (IS_VALLEYVIEW(dev)) {
1447                 for_each_sprite(dev_priv, pipe, sprite) {
1448                         reg = SPCNTR(pipe, sprite);
1449                         val = I915_READ(reg);
1450                         I915_STATE_WARN(val & SP_ENABLE,
1451                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1452                              sprite_name(pipe, sprite), pipe_name(pipe));
1453                 }
1454         } else if (INTEL_INFO(dev)->gen >= 7) {
1455                 reg = SPRCTL(pipe);
1456                 val = I915_READ(reg);
1457                 I915_STATE_WARN(val & SPRITE_ENABLE,
1458                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1459                      plane_name(pipe), pipe_name(pipe));
1460         } else if (INTEL_INFO(dev)->gen >= 5) {
1461                 reg = DVSCNTR(pipe);
1462                 val = I915_READ(reg);
1463                 I915_STATE_WARN(val & DVS_ENABLE,
1464                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1465                      plane_name(pipe), pipe_name(pipe));
1466         }
1467 }
1468
1469 static void assert_vblank_disabled(struct drm_crtc *crtc)
1470 {
1471         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1472                 drm_crtc_vblank_put(crtc);
1473 }
1474
1475 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1476 {
1477         u32 val;
1478         bool enabled;
1479
1480         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1481
1482         val = I915_READ(PCH_DREF_CONTROL);
1483         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484                             DREF_SUPERSPREAD_SOURCE_MASK));
1485         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1486 }
1487
1488 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1489                                            enum pipe pipe)
1490 {
1491         int reg;
1492         u32 val;
1493         bool enabled;
1494
1495         reg = PCH_TRANSCONF(pipe);
1496         val = I915_READ(reg);
1497         enabled = !!(val & TRANS_ENABLE);
1498         I915_STATE_WARN(enabled,
1499              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1500              pipe_name(pipe));
1501 }
1502
1503 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504                             enum pipe pipe, u32 port_sel, u32 val)
1505 {
1506         if ((val & DP_PORT_EN) == 0)
1507                 return false;
1508
1509         if (HAS_PCH_CPT(dev_priv->dev)) {
1510                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1513                         return false;
1514         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1516                         return false;
1517         } else {
1518                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1519                         return false;
1520         }
1521         return true;
1522 }
1523
1524 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525                               enum pipe pipe, u32 val)
1526 {
1527         if ((val & SDVO_ENABLE) == 0)
1528                 return false;
1529
1530         if (HAS_PCH_CPT(dev_priv->dev)) {
1531                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1532                         return false;
1533         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1535                         return false;
1536         } else {
1537                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1538                         return false;
1539         }
1540         return true;
1541 }
1542
1543 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544                               enum pipe pipe, u32 val)
1545 {
1546         if ((val & LVDS_PORT_EN) == 0)
1547                 return false;
1548
1549         if (HAS_PCH_CPT(dev_priv->dev)) {
1550                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1551                         return false;
1552         } else {
1553                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1554                         return false;
1555         }
1556         return true;
1557 }
1558
1559 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560                               enum pipe pipe, u32 val)
1561 {
1562         if ((val & ADPA_DAC_ENABLE) == 0)
1563                 return false;
1564         if (HAS_PCH_CPT(dev_priv->dev)) {
1565                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1566                         return false;
1567         } else {
1568                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1569                         return false;
1570         }
1571         return true;
1572 }
1573
1574 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1575                                    enum pipe pipe, int reg, u32 port_sel)
1576 {
1577         u32 val = I915_READ(reg);
1578         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1579              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1580              reg, pipe_name(pipe));
1581
1582         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1583              && (val & DP_PIPEB_SELECT),
1584              "IBX PCH dp port still using transcoder B\n");
1585 }
1586
1587 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588                                      enum pipe pipe, int reg)
1589 {
1590         u32 val = I915_READ(reg);
1591         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1592              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1593              reg, pipe_name(pipe));
1594
1595         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1596              && (val & SDVO_PIPE_B_SELECT),
1597              "IBX PCH hdmi port still using transcoder B\n");
1598 }
1599
1600 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1601                                       enum pipe pipe)
1602 {
1603         int reg;
1604         u32 val;
1605
1606         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1609
1610         reg = PCH_ADPA;
1611         val = I915_READ(reg);
1612         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1613              "PCH VGA enabled on transcoder %c, should be disabled\n",
1614              pipe_name(pipe));
1615
1616         reg = PCH_LVDS;
1617         val = I915_READ(reg);
1618         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1619              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1620              pipe_name(pipe));
1621
1622         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1625 }
1626
1627 static void vlv_enable_pll(struct intel_crtc *crtc,
1628                            const struct intel_crtc_state *pipe_config)
1629 {
1630         struct drm_device *dev = crtc->base.dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         int reg = DPLL(crtc->pipe);
1633         u32 dpll = pipe_config->dpll_hw_state.dpll;
1634
1635         assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637         /* No really, not for ILK+ */
1638         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1639
1640         /* PLL is protected by panel, make sure we can write it */
1641         if (IS_MOBILE(dev_priv->dev))
1642                 assert_panel_unlocked(dev_priv, crtc->pipe);
1643
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150);
1647
1648         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1650
1651         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1652         POSTING_READ(DPLL_MD(crtc->pipe));
1653
1654         /* We do this three times for luck */
1655         I915_WRITE(reg, dpll);
1656         POSTING_READ(reg);
1657         udelay(150); /* wait for warmup */
1658         I915_WRITE(reg, dpll);
1659         POSTING_READ(reg);
1660         udelay(150); /* wait for warmup */
1661         I915_WRITE(reg, dpll);
1662         POSTING_READ(reg);
1663         udelay(150); /* wait for warmup */
1664 }
1665
1666 static void chv_enable_pll(struct intel_crtc *crtc,
1667                            const struct intel_crtc_state *pipe_config)
1668 {
1669         struct drm_device *dev = crtc->base.dev;
1670         struct drm_i915_private *dev_priv = dev->dev_private;
1671         int pipe = crtc->pipe;
1672         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1673         u32 tmp;
1674
1675         assert_pipe_disabled(dev_priv, crtc->pipe);
1676
1677         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1678
1679         mutex_lock(&dev_priv->sb_lock);
1680
1681         /* Enable back the 10bit clock to display controller */
1682         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683         tmp |= DPIO_DCLKP_EN;
1684         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1685
1686         mutex_unlock(&dev_priv->sb_lock);
1687
1688         /*
1689          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1690          */
1691         udelay(1);
1692
1693         /* Enable PLL */
1694         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1695
1696         /* Check PLL is locked */
1697         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1698                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1699
1700         /* not sure when this should be written */
1701         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1702         POSTING_READ(DPLL_MD(pipe));
1703 }
1704
1705 static int intel_num_dvo_pipes(struct drm_device *dev)
1706 {
1707         struct intel_crtc *crtc;
1708         int count = 0;
1709
1710         for_each_intel_crtc(dev, crtc)
1711                 count += crtc->base.state->active &&
1712                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1713
1714         return count;
1715 }
1716
1717 static void i9xx_enable_pll(struct intel_crtc *crtc)
1718 {
1719         struct drm_device *dev = crtc->base.dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721         int reg = DPLL(crtc->pipe);
1722         u32 dpll = crtc->config->dpll_hw_state.dpll;
1723
1724         assert_pipe_disabled(dev_priv, crtc->pipe);
1725
1726         /* No really, not for ILK+ */
1727         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1728
1729         /* PLL is protected by panel, make sure we can write it */
1730         if (IS_MOBILE(dev) && !IS_I830(dev))
1731                 assert_panel_unlocked(dev_priv, crtc->pipe);
1732
1733         /* Enable DVO 2x clock on both PLLs if necessary */
1734         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1735                 /*
1736                  * It appears to be important that we don't enable this
1737                  * for the current pipe before otherwise configuring the
1738                  * PLL. No idea how this should be handled if multiple
1739                  * DVO outputs are enabled simultaneosly.
1740                  */
1741                 dpll |= DPLL_DVO_2X_MODE;
1742                 I915_WRITE(DPLL(!crtc->pipe),
1743                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1744         }
1745
1746         /* Wait for the clocks to stabilize. */
1747         POSTING_READ(reg);
1748         udelay(150);
1749
1750         if (INTEL_INFO(dev)->gen >= 4) {
1751                 I915_WRITE(DPLL_MD(crtc->pipe),
1752                            crtc->config->dpll_hw_state.dpll_md);
1753         } else {
1754                 /* The pixel multiplier can only be updated once the
1755                  * DPLL is enabled and the clocks are stable.
1756                  *
1757                  * So write it again.
1758                  */
1759                 I915_WRITE(reg, dpll);
1760         }
1761
1762         /* We do this three times for luck */
1763         I915_WRITE(reg, dpll);
1764         POSTING_READ(reg);
1765         udelay(150); /* wait for warmup */
1766         I915_WRITE(reg, dpll);
1767         POSTING_READ(reg);
1768         udelay(150); /* wait for warmup */
1769         I915_WRITE(reg, dpll);
1770         POSTING_READ(reg);
1771         udelay(150); /* wait for warmup */
1772 }
1773
1774 /**
1775  * i9xx_disable_pll - disable a PLL
1776  * @dev_priv: i915 private structure
1777  * @pipe: pipe PLL to disable
1778  *
1779  * Disable the PLL for @pipe, making sure the pipe is off first.
1780  *
1781  * Note!  This is for pre-ILK only.
1782  */
1783 static void i9xx_disable_pll(struct intel_crtc *crtc)
1784 {
1785         struct drm_device *dev = crtc->base.dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         enum pipe pipe = crtc->pipe;
1788
1789         /* Disable DVO 2x clock on both PLLs if necessary */
1790         if (IS_I830(dev) &&
1791             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1792             !intel_num_dvo_pipes(dev)) {
1793                 I915_WRITE(DPLL(PIPE_B),
1794                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795                 I915_WRITE(DPLL(PIPE_A),
1796                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1797         }
1798
1799         /* Don't disable pipe or pipe PLLs if needed */
1800         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1802                 return;
1803
1804         /* Make sure the pipe isn't still relying on us */
1805         assert_pipe_disabled(dev_priv, pipe);
1806
1807         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1808         POSTING_READ(DPLL(pipe));
1809 }
1810
1811 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812 {
1813         u32 val;
1814
1815         /* Make sure the pipe isn't still relying on us */
1816         assert_pipe_disabled(dev_priv, pipe);
1817
1818         /*
1819          * Leave integrated clock source and reference clock enabled for pipe B.
1820          * The latter is needed for VGA hotplug / manual detection.
1821          */
1822         val = DPLL_VGA_MODE_DIS;
1823         if (pipe == PIPE_B)
1824                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1825         I915_WRITE(DPLL(pipe), val);
1826         POSTING_READ(DPLL(pipe));
1827
1828 }
1829
1830 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1831 {
1832         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1833         u32 val;
1834
1835         /* Make sure the pipe isn't still relying on us */
1836         assert_pipe_disabled(dev_priv, pipe);
1837
1838         /* Set PLL en = 0 */
1839         val = DPLL_SSC_REF_CLK_CHV |
1840                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1841         if (pipe != PIPE_A)
1842                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843         I915_WRITE(DPLL(pipe), val);
1844         POSTING_READ(DPLL(pipe));
1845
1846         mutex_lock(&dev_priv->sb_lock);
1847
1848         /* Disable 10bit clock to display controller */
1849         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850         val &= ~DPIO_DCLKP_EN;
1851         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1852
1853         mutex_unlock(&dev_priv->sb_lock);
1854 }
1855
1856 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1857                          struct intel_digital_port *dport,
1858                          unsigned int expected_mask)
1859 {
1860         u32 port_mask;
1861         int dpll_reg;
1862
1863         switch (dport->port) {
1864         case PORT_B:
1865                 port_mask = DPLL_PORTB_READY_MASK;
1866                 dpll_reg = DPLL(0);
1867                 break;
1868         case PORT_C:
1869                 port_mask = DPLL_PORTC_READY_MASK;
1870                 dpll_reg = DPLL(0);
1871                 expected_mask <<= 4;
1872                 break;
1873         case PORT_D:
1874                 port_mask = DPLL_PORTD_READY_MASK;
1875                 dpll_reg = DPIO_PHY_STATUS;
1876                 break;
1877         default:
1878                 BUG();
1879         }
1880
1881         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1884 }
1885
1886 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887 {
1888         struct drm_device *dev = crtc->base.dev;
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
1892         if (WARN_ON(pll == NULL))
1893                 return;
1894
1895         WARN_ON(!pll->config.crtc_mask);
1896         if (pll->active == 0) {
1897                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898                 WARN_ON(pll->on);
1899                 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901                 pll->mode_set(dev_priv, pll);
1902         }
1903 }
1904
1905 /**
1906  * intel_enable_shared_dpll - enable PCH PLL
1907  * @dev_priv: i915 private structure
1908  * @pipe: pipe PLL to enable
1909  *
1910  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911  * drives the transcoder clock.
1912  */
1913 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915         struct drm_device *dev = crtc->base.dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919         if (WARN_ON(pll == NULL))
1920                 return;
1921
1922         if (WARN_ON(pll->config.crtc_mask == 0))
1923                 return;
1924
1925         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1926                       pll->name, pll->active, pll->on,
1927                       crtc->base.base.id);
1928
1929         if (pll->active++) {
1930                 WARN_ON(!pll->on);
1931                 assert_shared_dpll_enabled(dev_priv, pll);
1932                 return;
1933         }
1934         WARN_ON(pll->on);
1935
1936         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
1938         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1939         pll->enable(dev_priv, pll);
1940         pll->on = true;
1941 }
1942
1943 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1944 {
1945         struct drm_device *dev = crtc->base.dev;
1946         struct drm_i915_private *dev_priv = dev->dev_private;
1947         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1948
1949         /* PCH only available on ILK+ */
1950         if (INTEL_INFO(dev)->gen < 5)
1951                 return;
1952
1953         if (pll == NULL)
1954                 return;
1955
1956         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1957                 return;
1958
1959         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960                       pll->name, pll->active, pll->on,
1961                       crtc->base.base.id);
1962
1963         if (WARN_ON(pll->active == 0)) {
1964                 assert_shared_dpll_disabled(dev_priv, pll);
1965                 return;
1966         }
1967
1968         assert_shared_dpll_enabled(dev_priv, pll);
1969         WARN_ON(!pll->on);
1970         if (--pll->active)
1971                 return;
1972
1973         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1974         pll->disable(dev_priv, pll);
1975         pll->on = false;
1976
1977         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1978 }
1979
1980 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1981                                            enum pipe pipe)
1982 {
1983         struct drm_device *dev = dev_priv->dev;
1984         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1986         uint32_t reg, val, pipeconf_val;
1987
1988         /* PCH only available on ILK+ */
1989         BUG_ON(!HAS_PCH_SPLIT(dev));
1990
1991         /* Make sure PCH DPLL is enabled */
1992         assert_shared_dpll_enabled(dev_priv,
1993                                    intel_crtc_to_shared_dpll(intel_crtc));
1994
1995         /* FDI must be feeding us bits for PCH ports */
1996         assert_fdi_tx_enabled(dev_priv, pipe);
1997         assert_fdi_rx_enabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_CPT(dev)) {
2000                 /* Workaround: Set the timing override bit before enabling the
2001                  * pch transcoder. */
2002                 reg = TRANS_CHICKEN2(pipe);
2003                 val = I915_READ(reg);
2004                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005                 I915_WRITE(reg, val);
2006         }
2007
2008         reg = PCH_TRANSCONF(pipe);
2009         val = I915_READ(reg);
2010         pipeconf_val = I915_READ(PIPECONF(pipe));
2011
2012         if (HAS_PCH_IBX(dev_priv->dev)) {
2013                 /*
2014                  * Make the BPC in transcoder be consistent with
2015                  * that in pipeconf reg. For HDMI we must use 8bpc
2016                  * here for both 8bpc and 12bpc.
2017                  */
2018                 val &= ~PIPECONF_BPC_MASK;
2019                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020                         val |= PIPECONF_8BPC;
2021                 else
2022                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2023         }
2024
2025         val &= ~TRANS_INTERLACE_MASK;
2026         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2027                 if (HAS_PCH_IBX(dev_priv->dev) &&
2028                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2029                         val |= TRANS_LEGACY_INTERLACED_ILK;
2030                 else
2031                         val |= TRANS_INTERLACED;
2032         else
2033                 val |= TRANS_PROGRESSIVE;
2034
2035         I915_WRITE(reg, val | TRANS_ENABLE);
2036         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2037                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2038 }
2039
2040 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2041                                       enum transcoder cpu_transcoder)
2042 {
2043         u32 val, pipeconf_val;
2044
2045         /* PCH only available on ILK+ */
2046         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2047
2048         /* FDI must be feeding us bits for PCH ports */
2049         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2050         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2051
2052         /* Workaround: set timing override bit. */
2053         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2054         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2055         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2056
2057         val = TRANS_ENABLE;
2058         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2059
2060         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061             PIPECONF_INTERLACED_ILK)
2062                 val |= TRANS_INTERLACED;
2063         else
2064                 val |= TRANS_PROGRESSIVE;
2065
2066         I915_WRITE(LPT_TRANSCONF, val);
2067         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2068                 DRM_ERROR("Failed to enable PCH transcoder\n");
2069 }
2070
2071 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2072                                             enum pipe pipe)
2073 {
2074         struct drm_device *dev = dev_priv->dev;
2075         uint32_t reg, val;
2076
2077         /* FDI relies on the transcoder */
2078         assert_fdi_tx_disabled(dev_priv, pipe);
2079         assert_fdi_rx_disabled(dev_priv, pipe);
2080
2081         /* Ports must be off as well */
2082         assert_pch_ports_disabled(dev_priv, pipe);
2083
2084         reg = PCH_TRANSCONF(pipe);
2085         val = I915_READ(reg);
2086         val &= ~TRANS_ENABLE;
2087         I915_WRITE(reg, val);
2088         /* wait for PCH transcoder off, transcoder state */
2089         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2090                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2091
2092         if (!HAS_PCH_IBX(dev)) {
2093                 /* Workaround: Clear the timing override chicken bit again. */
2094                 reg = TRANS_CHICKEN2(pipe);
2095                 val = I915_READ(reg);
2096                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097                 I915_WRITE(reg, val);
2098         }
2099 }
2100
2101 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2102 {
2103         u32 val;
2104
2105         val = I915_READ(LPT_TRANSCONF);
2106         val &= ~TRANS_ENABLE;
2107         I915_WRITE(LPT_TRANSCONF, val);
2108         /* wait for PCH transcoder off, transcoder state */
2109         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2110                 DRM_ERROR("Failed to disable PCH transcoder\n");
2111
2112         /* Workaround: clear timing override bit. */
2113         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2114         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2115         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2116 }
2117
2118 /**
2119  * intel_enable_pipe - enable a pipe, asserting requirements
2120  * @crtc: crtc responsible for the pipe
2121  *
2122  * Enable @crtc's pipe, making sure that various hardware specific requirements
2123  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2124  */
2125 static void intel_enable_pipe(struct intel_crtc *crtc)
2126 {
2127         struct drm_device *dev = crtc->base.dev;
2128         struct drm_i915_private *dev_priv = dev->dev_private;
2129         enum pipe pipe = crtc->pipe;
2130         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2131                                                                       pipe);
2132         enum pipe pch_transcoder;
2133         int reg;
2134         u32 val;
2135
2136         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2137
2138         assert_planes_disabled(dev_priv, pipe);
2139         assert_cursor_disabled(dev_priv, pipe);
2140         assert_sprites_disabled(dev_priv, pipe);
2141
2142         if (HAS_PCH_LPT(dev_priv->dev))
2143                 pch_transcoder = TRANSCODER_A;
2144         else
2145                 pch_transcoder = pipe;
2146
2147         /*
2148          * A pipe without a PLL won't actually be able to drive bits from
2149          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2150          * need the check.
2151          */
2152         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2153                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2154                         assert_dsi_pll_enabled(dev_priv);
2155                 else
2156                         assert_pll_enabled(dev_priv, pipe);
2157         else {
2158                 if (crtc->config->has_pch_encoder) {
2159                         /* if driving the PCH, we need FDI enabled */
2160                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2161                         assert_fdi_tx_pll_enabled(dev_priv,
2162                                                   (enum pipe) cpu_transcoder);
2163                 }
2164                 /* FIXME: assert CPU port conditions for SNB+ */
2165         }
2166
2167         reg = PIPECONF(cpu_transcoder);
2168         val = I915_READ(reg);
2169         if (val & PIPECONF_ENABLE) {
2170                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2172                 return;
2173         }
2174
2175         I915_WRITE(reg, val | PIPECONF_ENABLE);
2176         POSTING_READ(reg);
2177 }
2178
2179 /**
2180  * intel_disable_pipe - disable a pipe, asserting requirements
2181  * @crtc: crtc whose pipes is to be disabled
2182  *
2183  * Disable the pipe of @crtc, making sure that various hardware
2184  * specific requirements are met, if applicable, e.g. plane
2185  * disabled, panel fitter off, etc.
2186  *
2187  * Will wait until the pipe has shut down before returning.
2188  */
2189 static void intel_disable_pipe(struct intel_crtc *crtc)
2190 {
2191         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2192         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2193         enum pipe pipe = crtc->pipe;
2194         int reg;
2195         u32 val;
2196
2197         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2198
2199         /*
2200          * Make sure planes won't keep trying to pump pixels to us,
2201          * or we might hang the display.
2202          */
2203         assert_planes_disabled(dev_priv, pipe);
2204         assert_cursor_disabled(dev_priv, pipe);
2205         assert_sprites_disabled(dev_priv, pipe);
2206
2207         reg = PIPECONF(cpu_transcoder);
2208         val = I915_READ(reg);
2209         if ((val & PIPECONF_ENABLE) == 0)
2210                 return;
2211
2212         /*
2213          * Double wide has implications for planes
2214          * so best keep it disabled when not needed.
2215          */
2216         if (crtc->config->double_wide)
2217                 val &= ~PIPECONF_DOUBLE_WIDE;
2218
2219         /* Don't disable pipe or pipe PLLs if needed */
2220         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2222                 val &= ~PIPECONF_ENABLE;
2223
2224         I915_WRITE(reg, val);
2225         if ((val & PIPECONF_ENABLE) == 0)
2226                 intel_wait_for_pipe_off(crtc);
2227 }
2228
2229 static bool need_vtd_wa(struct drm_device *dev)
2230 {
2231 #ifdef CONFIG_INTEL_IOMMU
2232         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2233                 return true;
2234 #endif
2235         return false;
2236 }
2237
2238 unsigned int
2239 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2240                   uint64_t fb_format_modifier, unsigned int plane)
2241 {
2242         unsigned int tile_height;
2243         uint32_t pixel_bytes;
2244
2245         switch (fb_format_modifier) {
2246         case DRM_FORMAT_MOD_NONE:
2247                 tile_height = 1;
2248                 break;
2249         case I915_FORMAT_MOD_X_TILED:
2250                 tile_height = IS_GEN2(dev) ? 16 : 8;
2251                 break;
2252         case I915_FORMAT_MOD_Y_TILED:
2253                 tile_height = 32;
2254                 break;
2255         case I915_FORMAT_MOD_Yf_TILED:
2256                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2257                 switch (pixel_bytes) {
2258                 default:
2259                 case 1:
2260                         tile_height = 64;
2261                         break;
2262                 case 2:
2263                 case 4:
2264                         tile_height = 32;
2265                         break;
2266                 case 8:
2267                         tile_height = 16;
2268                         break;
2269                 case 16:
2270                         WARN_ONCE(1,
2271                                   "128-bit pixels are not supported for display!");
2272                         tile_height = 16;
2273                         break;
2274                 }
2275                 break;
2276         default:
2277                 MISSING_CASE(fb_format_modifier);
2278                 tile_height = 1;
2279                 break;
2280         }
2281
2282         return tile_height;
2283 }
2284
2285 unsigned int
2286 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287                       uint32_t pixel_format, uint64_t fb_format_modifier)
2288 {
2289         return ALIGN(height, intel_tile_height(dev, pixel_format,
2290                                                fb_format_modifier, 0));
2291 }
2292
2293 static int
2294 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295                         const struct drm_plane_state *plane_state)
2296 {
2297         struct intel_rotation_info *info = &view->rotation_info;
2298         unsigned int tile_height, tile_pitch;
2299
2300         *view = i915_ggtt_view_normal;
2301
2302         if (!plane_state)
2303                 return 0;
2304
2305         if (!intel_rotation_90_or_270(plane_state->rotation))
2306                 return 0;
2307
2308         *view = i915_ggtt_view_rotated;
2309
2310         info->height = fb->height;
2311         info->pixel_format = fb->pixel_format;
2312         info->pitch = fb->pitches[0];
2313         info->uv_offset = fb->offsets[1];
2314         info->fb_modifier = fb->modifier[0];
2315
2316         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2317                                         fb->modifier[0], 0);
2318         tile_pitch = PAGE_SIZE / tile_height;
2319         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
2323         if (info->pixel_format == DRM_FORMAT_NV12) {
2324                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325                                                 fb->modifier[0], 1);
2326                 tile_pitch = PAGE_SIZE / tile_height;
2327                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2329                                                      tile_height);
2330                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2331                                 PAGE_SIZE;
2332         }
2333
2334         return 0;
2335 }
2336
2337 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2338 {
2339         if (INTEL_INFO(dev_priv)->gen >= 9)
2340                 return 256 * 1024;
2341         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342                  IS_VALLEYVIEW(dev_priv))
2343                 return 128 * 1024;
2344         else if (INTEL_INFO(dev_priv)->gen >= 4)
2345                 return 4 * 1024;
2346         else
2347                 return 0;
2348 }
2349
2350 int
2351 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352                            struct drm_framebuffer *fb,
2353                            const struct drm_plane_state *plane_state,
2354                            struct intel_engine_cs *pipelined,
2355                            struct drm_i915_gem_request **pipelined_request)
2356 {
2357         struct drm_device *dev = fb->dev;
2358         struct drm_i915_private *dev_priv = dev->dev_private;
2359         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360         struct i915_ggtt_view view;
2361         u32 alignment;
2362         int ret;
2363
2364         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
2366         switch (fb->modifier[0]) {
2367         case DRM_FORMAT_MOD_NONE:
2368                 alignment = intel_linear_alignment(dev_priv);
2369                 break;
2370         case I915_FORMAT_MOD_X_TILED:
2371                 if (INTEL_INFO(dev)->gen >= 9)
2372                         alignment = 256 * 1024;
2373                 else {
2374                         /* pin() will align the object as required by fence */
2375                         alignment = 0;
2376                 }
2377                 break;
2378         case I915_FORMAT_MOD_Y_TILED:
2379         case I915_FORMAT_MOD_Yf_TILED:
2380                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381                           "Y tiling bo slipped through, driver bug!\n"))
2382                         return -EINVAL;
2383                 alignment = 1 * 1024 * 1024;
2384                 break;
2385         default:
2386                 MISSING_CASE(fb->modifier[0]);
2387                 return -EINVAL;
2388         }
2389
2390         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2391         if (ret)
2392                 return ret;
2393
2394         /* Note that the w/a also requires 64 PTE of padding following the
2395          * bo. We currently fill all unused PTE with the shadow page and so
2396          * we should always have valid PTE following the scanout preventing
2397          * the VT-d warning.
2398          */
2399         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400                 alignment = 256 * 1024;
2401
2402         /*
2403          * Global gtt pte registers are special registers which actually forward
2404          * writes to a chunk of system memory. Which means that there is no risk
2405          * that the register values disappear as soon as we call
2406          * intel_runtime_pm_put(), so it is correct to wrap only the
2407          * pin/unpin/fence and not more.
2408          */
2409         intel_runtime_pm_get(dev_priv);
2410
2411         dev_priv->mm.interruptible = false;
2412         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2413                                                    pipelined_request, &view);
2414         if (ret)
2415                 goto err_interruptible;
2416
2417         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418          * fence, whereas 965+ only requires a fence if using
2419          * framebuffer compression.  For simplicity, we always install
2420          * a fence as the cost is not that onerous.
2421          */
2422         ret = i915_gem_object_get_fence(obj);
2423         if (ret == -EDEADLK) {
2424                 /*
2425                  * -EDEADLK means there are no free fences
2426                  * no pending flips.
2427                  *
2428                  * This is propagated to atomic, but it uses
2429                  * -EDEADLK to force a locking recovery, so
2430                  * change the returned error to -EBUSY.
2431                  */
2432                 ret = -EBUSY;
2433                 goto err_unpin;
2434         } else if (ret)
2435                 goto err_unpin;
2436
2437         i915_gem_object_pin_fence(obj);
2438
2439         dev_priv->mm.interruptible = true;
2440         intel_runtime_pm_put(dev_priv);
2441         return 0;
2442
2443 err_unpin:
2444         i915_gem_object_unpin_from_display_plane(obj, &view);
2445 err_interruptible:
2446         dev_priv->mm.interruptible = true;
2447         intel_runtime_pm_put(dev_priv);
2448         return ret;
2449 }
2450
2451 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452                                const struct drm_plane_state *plane_state)
2453 {
2454         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2455         struct i915_ggtt_view view;
2456         int ret;
2457
2458         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2459
2460         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461         WARN_ONCE(ret, "Couldn't get view from plane state!");
2462
2463         i915_gem_object_unpin_fence(obj);
2464         i915_gem_object_unpin_from_display_plane(obj, &view);
2465 }
2466
2467 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468  * is assumed to be a power-of-two. */
2469 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2470                                              int *x, int *y,
2471                                              unsigned int tiling_mode,
2472                                              unsigned int cpp,
2473                                              unsigned int pitch)
2474 {
2475         if (tiling_mode != I915_TILING_NONE) {
2476                 unsigned int tile_rows, tiles;
2477
2478                 tile_rows = *y / 8;
2479                 *y %= 8;
2480
2481                 tiles = *x / (512/cpp);
2482                 *x %= 512/cpp;
2483
2484                 return tile_rows * pitch * 8 + tiles * 4096;
2485         } else {
2486                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2487                 unsigned int offset;
2488
2489                 offset = *y * pitch + *x * cpp;
2490                 *y = (offset & alignment) / pitch;
2491                 *x = ((offset & alignment) - *y * pitch) / cpp;
2492                 return offset & ~alignment;
2493         }
2494 }
2495
2496 static int i9xx_format_to_fourcc(int format)
2497 {
2498         switch (format) {
2499         case DISPPLANE_8BPP:
2500                 return DRM_FORMAT_C8;
2501         case DISPPLANE_BGRX555:
2502                 return DRM_FORMAT_XRGB1555;
2503         case DISPPLANE_BGRX565:
2504                 return DRM_FORMAT_RGB565;
2505         default:
2506         case DISPPLANE_BGRX888:
2507                 return DRM_FORMAT_XRGB8888;
2508         case DISPPLANE_RGBX888:
2509                 return DRM_FORMAT_XBGR8888;
2510         case DISPPLANE_BGRX101010:
2511                 return DRM_FORMAT_XRGB2101010;
2512         case DISPPLANE_RGBX101010:
2513                 return DRM_FORMAT_XBGR2101010;
2514         }
2515 }
2516
2517 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2518 {
2519         switch (format) {
2520         case PLANE_CTL_FORMAT_RGB_565:
2521                 return DRM_FORMAT_RGB565;
2522         default:
2523         case PLANE_CTL_FORMAT_XRGB_8888:
2524                 if (rgb_order) {
2525                         if (alpha)
2526                                 return DRM_FORMAT_ABGR8888;
2527                         else
2528                                 return DRM_FORMAT_XBGR8888;
2529                 } else {
2530                         if (alpha)
2531                                 return DRM_FORMAT_ARGB8888;
2532                         else
2533                                 return DRM_FORMAT_XRGB8888;
2534                 }
2535         case PLANE_CTL_FORMAT_XRGB_2101010:
2536                 if (rgb_order)
2537                         return DRM_FORMAT_XBGR2101010;
2538                 else
2539                         return DRM_FORMAT_XRGB2101010;
2540         }
2541 }
2542
2543 static bool
2544 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545                               struct intel_initial_plane_config *plane_config)
2546 {
2547         struct drm_device *dev = crtc->base.dev;
2548         struct drm_i915_gem_object *obj = NULL;
2549         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2550         struct drm_framebuffer *fb = &plane_config->fb->base;
2551         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2552         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2553                                     PAGE_SIZE);
2554
2555         size_aligned -= base_aligned;
2556
2557         if (plane_config->size == 0)
2558                 return false;
2559
2560         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2561                                                              base_aligned,
2562                                                              base_aligned,
2563                                                              size_aligned);
2564         if (!obj)
2565                 return false;
2566
2567         obj->tiling_mode = plane_config->tiling;
2568         if (obj->tiling_mode == I915_TILING_X)
2569                 obj->stride = fb->pitches[0];
2570
2571         mode_cmd.pixel_format = fb->pixel_format;
2572         mode_cmd.width = fb->width;
2573         mode_cmd.height = fb->height;
2574         mode_cmd.pitches[0] = fb->pitches[0];
2575         mode_cmd.modifier[0] = fb->modifier[0];
2576         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2577
2578         mutex_lock(&dev->struct_mutex);
2579         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2580                                    &mode_cmd, obj)) {
2581                 DRM_DEBUG_KMS("intel fb init failed\n");
2582                 goto out_unref_obj;
2583         }
2584         mutex_unlock(&dev->struct_mutex);
2585
2586         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2587         return true;
2588
2589 out_unref_obj:
2590         drm_gem_object_unreference(&obj->base);
2591         mutex_unlock(&dev->struct_mutex);
2592         return false;
2593 }
2594
2595 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2596 static void
2597 update_state_fb(struct drm_plane *plane)
2598 {
2599         if (plane->fb == plane->state->fb)
2600                 return;
2601
2602         if (plane->state->fb)
2603                 drm_framebuffer_unreference(plane->state->fb);
2604         plane->state->fb = plane->fb;
2605         if (plane->state->fb)
2606                 drm_framebuffer_reference(plane->state->fb);
2607 }
2608
2609 static void
2610 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2611                              struct intel_initial_plane_config *plane_config)
2612 {
2613         struct drm_device *dev = intel_crtc->base.dev;
2614         struct drm_i915_private *dev_priv = dev->dev_private;
2615         struct drm_crtc *c;
2616         struct intel_crtc *i;
2617         struct drm_i915_gem_object *obj;
2618         struct drm_plane *primary = intel_crtc->base.primary;
2619         struct drm_plane_state *plane_state = primary->state;
2620         struct drm_framebuffer *fb;
2621
2622         if (!plane_config->fb)
2623                 return;
2624
2625         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2626                 fb = &plane_config->fb->base;
2627                 goto valid_fb;
2628         }
2629
2630         kfree(plane_config->fb);
2631
2632         /*
2633          * Failed to alloc the obj, check to see if we should share
2634          * an fb with another CRTC instead
2635          */
2636         for_each_crtc(dev, c) {
2637                 i = to_intel_crtc(c);
2638
2639                 if (c == &intel_crtc->base)
2640                         continue;
2641
2642                 if (!i->active)
2643                         continue;
2644
2645                 fb = c->primary->fb;
2646                 if (!fb)
2647                         continue;
2648
2649                 obj = intel_fb_obj(fb);
2650                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2651                         drm_framebuffer_reference(fb);
2652                         goto valid_fb;
2653                 }
2654         }
2655
2656         return;
2657
2658 valid_fb:
2659         plane_state->src_x = plane_state->src_y = 0;
2660         plane_state->src_w = fb->width << 16;
2661         plane_state->src_h = fb->height << 16;
2662
2663         plane_state->crtc_x = plane_state->src_y = 0;
2664         plane_state->crtc_w = fb->width;
2665         plane_state->crtc_h = fb->height;
2666
2667         obj = intel_fb_obj(fb);
2668         if (obj->tiling_mode != I915_TILING_NONE)
2669                 dev_priv->preserve_bios_swizzle = true;
2670
2671         drm_framebuffer_reference(fb);
2672         primary->fb = primary->state->fb = fb;
2673         primary->crtc = primary->state->crtc = &intel_crtc->base;
2674         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2675         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2676 }
2677
2678 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2679                                       struct drm_framebuffer *fb,
2680                                       int x, int y)
2681 {
2682         struct drm_device *dev = crtc->dev;
2683         struct drm_i915_private *dev_priv = dev->dev_private;
2684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2685         struct drm_plane *primary = crtc->primary;
2686         bool visible = to_intel_plane_state(primary->state)->visible;
2687         struct drm_i915_gem_object *obj;
2688         int plane = intel_crtc->plane;
2689         unsigned long linear_offset;
2690         u32 dspcntr;
2691         u32 reg = DSPCNTR(plane);
2692         int pixel_size;
2693
2694         if (!visible || !fb) {
2695                 I915_WRITE(reg, 0);
2696                 if (INTEL_INFO(dev)->gen >= 4)
2697                         I915_WRITE(DSPSURF(plane), 0);
2698                 else
2699                         I915_WRITE(DSPADDR(plane), 0);
2700                 POSTING_READ(reg);
2701                 return;
2702         }
2703
2704         obj = intel_fb_obj(fb);
2705         if (WARN_ON(obj == NULL))
2706                 return;
2707
2708         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2709
2710         dspcntr = DISPPLANE_GAMMA_ENABLE;
2711
2712         dspcntr |= DISPLAY_PLANE_ENABLE;
2713
2714         if (INTEL_INFO(dev)->gen < 4) {
2715                 if (intel_crtc->pipe == PIPE_B)
2716                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2717
2718                 /* pipesrc and dspsize control the size that is scaled from,
2719                  * which should always be the user's requested size.
2720                  */
2721                 I915_WRITE(DSPSIZE(plane),
2722                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723                            (intel_crtc->config->pipe_src_w - 1));
2724                 I915_WRITE(DSPPOS(plane), 0);
2725         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2726                 I915_WRITE(PRIMSIZE(plane),
2727                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2728                            (intel_crtc->config->pipe_src_w - 1));
2729                 I915_WRITE(PRIMPOS(plane), 0);
2730                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2731         }
2732
2733         switch (fb->pixel_format) {
2734         case DRM_FORMAT_C8:
2735                 dspcntr |= DISPPLANE_8BPP;
2736                 break;
2737         case DRM_FORMAT_XRGB1555:
2738                 dspcntr |= DISPPLANE_BGRX555;
2739                 break;
2740         case DRM_FORMAT_RGB565:
2741                 dspcntr |= DISPPLANE_BGRX565;
2742                 break;
2743         case DRM_FORMAT_XRGB8888:
2744                 dspcntr |= DISPPLANE_BGRX888;
2745                 break;
2746         case DRM_FORMAT_XBGR8888:
2747                 dspcntr |= DISPPLANE_RGBX888;
2748                 break;
2749         case DRM_FORMAT_XRGB2101010:
2750                 dspcntr |= DISPPLANE_BGRX101010;
2751                 break;
2752         case DRM_FORMAT_XBGR2101010:
2753                 dspcntr |= DISPPLANE_RGBX101010;
2754                 break;
2755         default:
2756                 BUG();
2757         }
2758
2759         if (INTEL_INFO(dev)->gen >= 4 &&
2760             obj->tiling_mode != I915_TILING_NONE)
2761                 dspcntr |= DISPPLANE_TILED;
2762
2763         if (IS_G4X(dev))
2764                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2765
2766         linear_offset = y * fb->pitches[0] + x * pixel_size;
2767
2768         if (INTEL_INFO(dev)->gen >= 4) {
2769                 intel_crtc->dspaddr_offset =
2770                         intel_gen4_compute_page_offset(dev_priv,
2771                                                        &x, &y, obj->tiling_mode,
2772                                                        pixel_size,
2773                                                        fb->pitches[0]);
2774                 linear_offset -= intel_crtc->dspaddr_offset;
2775         } else {
2776                 intel_crtc->dspaddr_offset = linear_offset;
2777         }
2778
2779         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2780                 dspcntr |= DISPPLANE_ROTATE_180;
2781
2782                 x += (intel_crtc->config->pipe_src_w - 1);
2783                 y += (intel_crtc->config->pipe_src_h - 1);
2784
2785                 /* Finding the last pixel of the last line of the display
2786                 data and adding to linear_offset*/
2787                 linear_offset +=
2788                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2790         }
2791
2792         intel_crtc->adjusted_x = x;
2793         intel_crtc->adjusted_y = y;
2794
2795         I915_WRITE(reg, dspcntr);
2796
2797         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2798         if (INTEL_INFO(dev)->gen >= 4) {
2799                 I915_WRITE(DSPSURF(plane),
2800                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2801                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2802                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2803         } else
2804                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2805         POSTING_READ(reg);
2806 }
2807
2808 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2809                                           struct drm_framebuffer *fb,
2810                                           int x, int y)
2811 {
2812         struct drm_device *dev = crtc->dev;
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815         struct drm_plane *primary = crtc->primary;
2816         bool visible = to_intel_plane_state(primary->state)->visible;
2817         struct drm_i915_gem_object *obj;
2818         int plane = intel_crtc->plane;
2819         unsigned long linear_offset;
2820         u32 dspcntr;
2821         u32 reg = DSPCNTR(plane);
2822         int pixel_size;
2823
2824         if (!visible || !fb) {
2825                 I915_WRITE(reg, 0);
2826                 I915_WRITE(DSPSURF(plane), 0);
2827                 POSTING_READ(reg);
2828                 return;
2829         }
2830
2831         obj = intel_fb_obj(fb);
2832         if (WARN_ON(obj == NULL))
2833                 return;
2834
2835         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2836
2837         dspcntr = DISPPLANE_GAMMA_ENABLE;
2838
2839         dspcntr |= DISPLAY_PLANE_ENABLE;
2840
2841         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2843
2844         switch (fb->pixel_format) {
2845         case DRM_FORMAT_C8:
2846                 dspcntr |= DISPPLANE_8BPP;
2847                 break;
2848         case DRM_FORMAT_RGB565:
2849                 dspcntr |= DISPPLANE_BGRX565;
2850                 break;
2851         case DRM_FORMAT_XRGB8888:
2852                 dspcntr |= DISPPLANE_BGRX888;
2853                 break;
2854         case DRM_FORMAT_XBGR8888:
2855                 dspcntr |= DISPPLANE_RGBX888;
2856                 break;
2857         case DRM_FORMAT_XRGB2101010:
2858                 dspcntr |= DISPPLANE_BGRX101010;
2859                 break;
2860         case DRM_FORMAT_XBGR2101010:
2861                 dspcntr |= DISPPLANE_RGBX101010;
2862                 break;
2863         default:
2864                 BUG();
2865         }
2866
2867         if (obj->tiling_mode != I915_TILING_NONE)
2868                 dspcntr |= DISPPLANE_TILED;
2869
2870         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2871                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2872
2873         linear_offset = y * fb->pitches[0] + x * pixel_size;
2874         intel_crtc->dspaddr_offset =
2875                 intel_gen4_compute_page_offset(dev_priv,
2876                                                &x, &y, obj->tiling_mode,
2877                                                pixel_size,
2878                                                fb->pitches[0]);
2879         linear_offset -= intel_crtc->dspaddr_offset;
2880         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2881                 dspcntr |= DISPPLANE_ROTATE_180;
2882
2883                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2884                         x += (intel_crtc->config->pipe_src_w - 1);
2885                         y += (intel_crtc->config->pipe_src_h - 1);
2886
2887                         /* Finding the last pixel of the last line of the display
2888                         data and adding to linear_offset*/
2889                         linear_offset +=
2890                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2891                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2892                 }
2893         }
2894
2895         intel_crtc->adjusted_x = x;
2896         intel_crtc->adjusted_y = y;
2897
2898         I915_WRITE(reg, dspcntr);
2899
2900         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2901         I915_WRITE(DSPSURF(plane),
2902                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2903         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2904                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2905         } else {
2906                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2907                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2908         }
2909         POSTING_READ(reg);
2910 }
2911
2912 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2913                               uint32_t pixel_format)
2914 {
2915         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2916
2917         /*
2918          * The stride is either expressed as a multiple of 64 bytes
2919          * chunks for linear buffers or in number of tiles for tiled
2920          * buffers.
2921          */
2922         switch (fb_modifier) {
2923         case DRM_FORMAT_MOD_NONE:
2924                 return 64;
2925         case I915_FORMAT_MOD_X_TILED:
2926                 if (INTEL_INFO(dev)->gen == 2)
2927                         return 128;
2928                 return 512;
2929         case I915_FORMAT_MOD_Y_TILED:
2930                 /* No need to check for old gens and Y tiling since this is
2931                  * about the display engine and those will be blocked before
2932                  * we get here.
2933                  */
2934                 return 128;
2935         case I915_FORMAT_MOD_Yf_TILED:
2936                 if (bits_per_pixel == 8)
2937                         return 64;
2938                 else
2939                         return 128;
2940         default:
2941                 MISSING_CASE(fb_modifier);
2942                 return 64;
2943         }
2944 }
2945
2946 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2947                                      struct drm_i915_gem_object *obj,
2948                                      unsigned int plane)
2949 {
2950         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2951         struct i915_vma *vma;
2952         unsigned char *offset;
2953
2954         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2955                 view = &i915_ggtt_view_rotated;
2956
2957         vma = i915_gem_obj_to_ggtt_view(obj, view);
2958         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2959                 view->type))
2960                 return -1;
2961
2962         offset = (unsigned char *)vma->node.start;
2963
2964         if (plane == 1) {
2965                 offset += vma->ggtt_view.rotation_info.uv_start_page *
2966                           PAGE_SIZE;
2967         }
2968
2969         return (unsigned long)offset;
2970 }
2971
2972 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2973 {
2974         struct drm_device *dev = intel_crtc->base.dev;
2975         struct drm_i915_private *dev_priv = dev->dev_private;
2976
2977         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2980 }
2981
2982 /*
2983  * This function detaches (aka. unbinds) unused scalers in hardware
2984  */
2985 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2986 {
2987         struct intel_crtc_scaler_state *scaler_state;
2988         int i;
2989
2990         scaler_state = &intel_crtc->config->scaler_state;
2991
2992         /* loop through and disable scalers that aren't in use */
2993         for (i = 0; i < intel_crtc->num_scalers; i++) {
2994                 if (!scaler_state->scalers[i].in_use)
2995                         skl_detach_scaler(intel_crtc, i);
2996         }
2997 }
2998
2999 u32 skl_plane_ctl_format(uint32_t pixel_format)
3000 {
3001         switch (pixel_format) {
3002         case DRM_FORMAT_C8:
3003                 return PLANE_CTL_FORMAT_INDEXED;
3004         case DRM_FORMAT_RGB565:
3005                 return PLANE_CTL_FORMAT_RGB_565;
3006         case DRM_FORMAT_XBGR8888:
3007                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3008         case DRM_FORMAT_XRGB8888:
3009                 return PLANE_CTL_FORMAT_XRGB_8888;
3010         /*
3011          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012          * to be already pre-multiplied. We need to add a knob (or a different
3013          * DRM_FORMAT) for user-space to configure that.
3014          */
3015         case DRM_FORMAT_ABGR8888:
3016                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3017                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3018         case DRM_FORMAT_ARGB8888:
3019                 return PLANE_CTL_FORMAT_XRGB_8888 |
3020                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3021         case DRM_FORMAT_XRGB2101010:
3022                 return PLANE_CTL_FORMAT_XRGB_2101010;
3023         case DRM_FORMAT_XBGR2101010:
3024                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3025         case DRM_FORMAT_YUYV:
3026                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3027         case DRM_FORMAT_YVYU:
3028                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3029         case DRM_FORMAT_UYVY:
3030                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3031         case DRM_FORMAT_VYUY:
3032                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3033         default:
3034                 MISSING_CASE(pixel_format);
3035         }
3036
3037         return 0;
3038 }
3039
3040 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3041 {
3042         switch (fb_modifier) {
3043         case DRM_FORMAT_MOD_NONE:
3044                 break;
3045         case I915_FORMAT_MOD_X_TILED:
3046                 return PLANE_CTL_TILED_X;
3047         case I915_FORMAT_MOD_Y_TILED:
3048                 return PLANE_CTL_TILED_Y;
3049         case I915_FORMAT_MOD_Yf_TILED:
3050                 return PLANE_CTL_TILED_YF;
3051         default:
3052                 MISSING_CASE(fb_modifier);
3053         }
3054
3055         return 0;
3056 }
3057
3058 u32 skl_plane_ctl_rotation(unsigned int rotation)
3059 {
3060         switch (rotation) {
3061         case BIT(DRM_ROTATE_0):
3062                 break;
3063         /*
3064          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065          * while i915 HW rotation is clockwise, thats why this swapping.
3066          */
3067         case BIT(DRM_ROTATE_90):
3068                 return PLANE_CTL_ROTATE_270;
3069         case BIT(DRM_ROTATE_180):
3070                 return PLANE_CTL_ROTATE_180;
3071         case BIT(DRM_ROTATE_270):
3072                 return PLANE_CTL_ROTATE_90;
3073         default:
3074                 MISSING_CASE(rotation);
3075         }
3076
3077         return 0;
3078 }
3079
3080 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081                                          struct drm_framebuffer *fb,
3082                                          int x, int y)
3083 {
3084         struct drm_device *dev = crtc->dev;
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087         struct drm_plane *plane = crtc->primary;
3088         bool visible = to_intel_plane_state(plane->state)->visible;
3089         struct drm_i915_gem_object *obj;
3090         int pipe = intel_crtc->pipe;
3091         u32 plane_ctl, stride_div, stride;
3092         u32 tile_height, plane_offset, plane_size;
3093         unsigned int rotation;
3094         int x_offset, y_offset;
3095         unsigned long surf_addr;
3096         struct intel_crtc_state *crtc_state = intel_crtc->config;
3097         struct intel_plane_state *plane_state;
3098         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3100         int scaler_id = -1;
3101
3102         plane_state = to_intel_plane_state(plane->state);
3103
3104         if (!visible || !fb) {
3105                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107                 POSTING_READ(PLANE_CTL(pipe, 0));
3108                 return;
3109         }
3110
3111         plane_ctl = PLANE_CTL_ENABLE |
3112                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3113                     PLANE_CTL_PIPE_CSC_ENABLE;
3114
3115         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3118
3119         rotation = plane->state->rotation;
3120         plane_ctl |= skl_plane_ctl_rotation(rotation);
3121
3122         obj = intel_fb_obj(fb);
3123         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3124                                                fb->pixel_format);
3125         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3126
3127         /*
3128          * FIXME: intel_plane_state->src, dst aren't set when transitional
3129          * update_plane helpers are called from legacy paths.
3130          * Once full atomic crtc is available, below check can be avoided.
3131          */
3132         if (drm_rect_width(&plane_state->src)) {
3133                 scaler_id = plane_state->scaler_id;
3134                 src_x = plane_state->src.x1 >> 16;
3135                 src_y = plane_state->src.y1 >> 16;
3136                 src_w = drm_rect_width(&plane_state->src) >> 16;
3137                 src_h = drm_rect_height(&plane_state->src) >> 16;
3138                 dst_x = plane_state->dst.x1;
3139                 dst_y = plane_state->dst.y1;
3140                 dst_w = drm_rect_width(&plane_state->dst);
3141                 dst_h = drm_rect_height(&plane_state->dst);
3142
3143                 WARN_ON(x != src_x || y != src_y);
3144         } else {
3145                 src_w = intel_crtc->config->pipe_src_w;
3146                 src_h = intel_crtc->config->pipe_src_h;
3147         }
3148
3149         if (intel_rotation_90_or_270(rotation)) {
3150                 /* stride = Surface height in tiles */
3151                 tile_height = intel_tile_height(dev, fb->pixel_format,
3152                                                 fb->modifier[0], 0);
3153                 stride = DIV_ROUND_UP(fb->height, tile_height);
3154                 x_offset = stride * tile_height - y - src_h;
3155                 y_offset = x;
3156                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3157         } else {
3158                 stride = fb->pitches[0] / stride_div;
3159                 x_offset = x;
3160                 y_offset = y;
3161                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3162         }
3163         plane_offset = y_offset << 16 | x_offset;
3164
3165         intel_crtc->adjusted_x = x_offset;
3166         intel_crtc->adjusted_y = y_offset;
3167
3168         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3169         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3170         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3171         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3172
3173         if (scaler_id >= 0) {
3174                 uint32_t ps_ctrl = 0;
3175
3176                 WARN_ON(!dst_w || !dst_h);
3177                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3178                         crtc_state->scaler_state.scalers[scaler_id].mode;
3179                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3180                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3181                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3182                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3183                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3184         } else {
3185                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3186         }
3187
3188         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3189
3190         POSTING_READ(PLANE_SURF(pipe, 0));
3191 }
3192
3193 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3194 static int
3195 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3196                            int x, int y, enum mode_set_atomic state)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200
3201         if (dev_priv->fbc.disable_fbc)
3202                 dev_priv->fbc.disable_fbc(dev_priv);
3203
3204         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3205
3206         return 0;
3207 }
3208
3209 static void intel_complete_page_flips(struct drm_device *dev)
3210 {
3211         struct drm_crtc *crtc;
3212
3213         for_each_crtc(dev, crtc) {
3214                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215                 enum plane plane = intel_crtc->plane;
3216
3217                 intel_prepare_page_flip(dev, plane);
3218                 intel_finish_page_flip_plane(dev, plane);
3219         }
3220 }
3221
3222 static void intel_update_primary_planes(struct drm_device *dev)
3223 {
3224         struct drm_crtc *crtc;
3225
3226         for_each_crtc(dev, crtc) {
3227                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3228                 struct intel_plane_state *plane_state;
3229
3230                 drm_modeset_lock_crtc(crtc, &plane->base);
3231
3232                 plane_state = to_intel_plane_state(plane->base.state);
3233
3234                 if (plane_state->base.fb)
3235                         plane->commit_plane(&plane->base, plane_state);
3236
3237                 drm_modeset_unlock_crtc(crtc);
3238         }
3239 }
3240
3241 void intel_prepare_reset(struct drm_device *dev)
3242 {
3243         /* no reset support for gen2 */
3244         if (IS_GEN2(dev))
3245                 return;
3246
3247         /* reset doesn't touch the display */
3248         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3249                 return;
3250
3251         drm_modeset_lock_all(dev);
3252         /*
3253          * Disabling the crtcs gracefully seems nicer. Also the
3254          * g33 docs say we should at least disable all the planes.
3255          */
3256         intel_display_suspend(dev);
3257 }
3258
3259 void intel_finish_reset(struct drm_device *dev)
3260 {
3261         struct drm_i915_private *dev_priv = to_i915(dev);
3262
3263         /*
3264          * Flips in the rings will be nuked by the reset,
3265          * so complete all pending flips so that user space
3266          * will get its events and not get stuck.
3267          */
3268         intel_complete_page_flips(dev);
3269
3270         /* no reset support for gen2 */
3271         if (IS_GEN2(dev))
3272                 return;
3273
3274         /* reset doesn't touch the display */
3275         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3276                 /*
3277                  * Flips in the rings have been nuked by the reset,
3278                  * so update the base address of all primary
3279                  * planes to the the last fb to make sure we're
3280                  * showing the correct fb after a reset.
3281                  *
3282                  * FIXME: Atomic will make this obsolete since we won't schedule
3283                  * CS-based flips (which might get lost in gpu resets) any more.
3284                  */
3285                 intel_update_primary_planes(dev);
3286                 return;
3287         }
3288
3289         /*
3290          * The display has been reset as well,
3291          * so need a full re-initialization.
3292          */
3293         intel_runtime_pm_disable_interrupts(dev_priv);
3294         intel_runtime_pm_enable_interrupts(dev_priv);
3295
3296         intel_modeset_init_hw(dev);
3297
3298         spin_lock_irq(&dev_priv->irq_lock);
3299         if (dev_priv->display.hpd_irq_setup)
3300                 dev_priv->display.hpd_irq_setup(dev);
3301         spin_unlock_irq(&dev_priv->irq_lock);
3302
3303         intel_display_resume(dev);
3304
3305         intel_hpd_init(dev_priv);
3306
3307         drm_modeset_unlock_all(dev);
3308 }
3309
3310 static void
3311 intel_finish_fb(struct drm_framebuffer *old_fb)
3312 {
3313         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3314         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3315         bool was_interruptible = dev_priv->mm.interruptible;
3316         int ret;
3317
3318         /* Big Hammer, we also need to ensure that any pending
3319          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3320          * current scanout is retired before unpinning the old
3321          * framebuffer. Note that we rely on userspace rendering
3322          * into the buffer attached to the pipe they are waiting
3323          * on. If not, userspace generates a GPU hang with IPEHR
3324          * point to the MI_WAIT_FOR_EVENT.
3325          *
3326          * This should only fail upon a hung GPU, in which case we
3327          * can safely continue.
3328          */
3329         dev_priv->mm.interruptible = false;
3330         ret = i915_gem_object_wait_rendering(obj, true);
3331         dev_priv->mm.interruptible = was_interruptible;
3332
3333         WARN_ON(ret);
3334 }
3335
3336 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3337 {
3338         struct drm_device *dev = crtc->dev;
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341         bool pending;
3342
3343         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3344             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3345                 return false;
3346
3347         spin_lock_irq(&dev->event_lock);
3348         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3349         spin_unlock_irq(&dev->event_lock);
3350
3351         return pending;
3352 }
3353
3354 static void intel_update_pipe_config(struct intel_crtc *crtc,
3355                                      struct intel_crtc_state *old_crtc_state)
3356 {
3357         struct drm_device *dev = crtc->base.dev;
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         struct intel_crtc_state *pipe_config =
3360                 to_intel_crtc_state(crtc->base.state);
3361
3362         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3363         crtc->base.mode = crtc->base.state->mode;
3364
3365         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3366                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3367                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3368
3369         if (HAS_DDI(dev))
3370                 intel_set_pipe_csc(&crtc->base);
3371
3372         /*
3373          * Update pipe size and adjust fitter if needed: the reason for this is
3374          * that in compute_mode_changes we check the native mode (not the pfit
3375          * mode) to see if we can flip rather than do a full mode set. In the
3376          * fastboot case, we'll flip, but if we don't update the pipesrc and
3377          * pfit state, we'll end up with a big fb scanned out into the wrong
3378          * sized surface.
3379          */
3380
3381         I915_WRITE(PIPESRC(crtc->pipe),
3382                    ((pipe_config->pipe_src_w - 1) << 16) |
3383                    (pipe_config->pipe_src_h - 1));
3384
3385         /* on skylake this is done by detaching scalers */
3386         if (INTEL_INFO(dev)->gen >= 9) {
3387                 skl_detach_scalers(crtc);
3388
3389                 if (pipe_config->pch_pfit.enabled)
3390                         skylake_pfit_enable(crtc);
3391         } else if (HAS_PCH_SPLIT(dev)) {
3392                 if (pipe_config->pch_pfit.enabled)
3393                         ironlake_pfit_enable(crtc);
3394                 else if (old_crtc_state->pch_pfit.enabled)
3395                         ironlake_pfit_disable(crtc, true);
3396         }
3397 }
3398
3399 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3400 {
3401         struct drm_device *dev = crtc->dev;
3402         struct drm_i915_private *dev_priv = dev->dev_private;
3403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404         int pipe = intel_crtc->pipe;
3405         u32 reg, temp;
3406
3407         /* enable normal train */
3408         reg = FDI_TX_CTL(pipe);
3409         temp = I915_READ(reg);
3410         if (IS_IVYBRIDGE(dev)) {
3411                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3413         } else {
3414                 temp &= ~FDI_LINK_TRAIN_NONE;
3415                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3416         }
3417         I915_WRITE(reg, temp);
3418
3419         reg = FDI_RX_CTL(pipe);
3420         temp = I915_READ(reg);
3421         if (HAS_PCH_CPT(dev)) {
3422                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3423                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3424         } else {
3425                 temp &= ~FDI_LINK_TRAIN_NONE;
3426                 temp |= FDI_LINK_TRAIN_NONE;
3427         }
3428         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3429
3430         /* wait one idle pattern time */
3431         POSTING_READ(reg);
3432         udelay(1000);
3433
3434         /* IVB wants error correction enabled */
3435         if (IS_IVYBRIDGE(dev))
3436                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437                            FDI_FE_ERRC_ENABLE);
3438 }
3439
3440 /* The FDI link training functions for ILK/Ibexpeak. */
3441 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3442 {
3443         struct drm_device *dev = crtc->dev;
3444         struct drm_i915_private *dev_priv = dev->dev_private;
3445         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446         int pipe = intel_crtc->pipe;
3447         u32 reg, temp, tries;
3448
3449         /* FDI needs bits from pipe first */
3450         assert_pipe_enabled(dev_priv, pipe);
3451
3452         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453            for train result */
3454         reg = FDI_RX_IMR(pipe);
3455         temp = I915_READ(reg);
3456         temp &= ~FDI_RX_SYMBOL_LOCK;
3457         temp &= ~FDI_RX_BIT_LOCK;
3458         I915_WRITE(reg, temp);
3459         I915_READ(reg);
3460         udelay(150);
3461
3462         /* enable CPU FDI TX and PCH FDI RX */
3463         reg = FDI_TX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3466         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3467         temp &= ~FDI_LINK_TRAIN_NONE;
3468         temp |= FDI_LINK_TRAIN_PATTERN_1;
3469         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3470
3471         reg = FDI_RX_CTL(pipe);
3472         temp = I915_READ(reg);
3473         temp &= ~FDI_LINK_TRAIN_NONE;
3474         temp |= FDI_LINK_TRAIN_PATTERN_1;
3475         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3476
3477         POSTING_READ(reg);
3478         udelay(150);
3479
3480         /* Ironlake workaround, enable clock pointer after FDI enable*/
3481         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3482         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3483                    FDI_RX_PHASE_SYNC_POINTER_EN);
3484
3485         reg = FDI_RX_IIR(pipe);
3486         for (tries = 0; tries < 5; tries++) {
3487                 temp = I915_READ(reg);
3488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489
3490                 if ((temp & FDI_RX_BIT_LOCK)) {
3491                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3492                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3493                         break;
3494                 }
3495         }
3496         if (tries == 5)
3497                 DRM_ERROR("FDI train 1 fail!\n");
3498
3499         /* Train 2 */
3500         reg = FDI_TX_CTL(pipe);
3501         temp = I915_READ(reg);
3502         temp &= ~FDI_LINK_TRAIN_NONE;
3503         temp |= FDI_LINK_TRAIN_PATTERN_2;
3504         I915_WRITE(reg, temp);
3505
3506         reg = FDI_RX_CTL(pipe);
3507         temp = I915_READ(reg);
3508         temp &= ~FDI_LINK_TRAIN_NONE;
3509         temp |= FDI_LINK_TRAIN_PATTERN_2;
3510         I915_WRITE(reg, temp);
3511
3512         POSTING_READ(reg);
3513         udelay(150);
3514
3515         reg = FDI_RX_IIR(pipe);
3516         for (tries = 0; tries < 5; tries++) {
3517                 temp = I915_READ(reg);
3518                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519
3520                 if (temp & FDI_RX_SYMBOL_LOCK) {
3521                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3522                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3523                         break;
3524                 }
3525         }
3526         if (tries == 5)
3527                 DRM_ERROR("FDI train 2 fail!\n");
3528
3529         DRM_DEBUG_KMS("FDI train done\n");
3530
3531 }
3532
3533 static const int snb_b_fdi_train_param[] = {
3534         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3535         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3536         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3537         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3538 };
3539
3540 /* The FDI link training functions for SNB/Cougarpoint. */
3541 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3542 {
3543         struct drm_device *dev = crtc->dev;
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546         int pipe = intel_crtc->pipe;
3547         u32 reg, temp, i, retry;
3548
3549         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3550            for train result */
3551         reg = FDI_RX_IMR(pipe);
3552         temp = I915_READ(reg);
3553         temp &= ~FDI_RX_SYMBOL_LOCK;
3554         temp &= ~FDI_RX_BIT_LOCK;
3555         I915_WRITE(reg, temp);
3556
3557         POSTING_READ(reg);
3558         udelay(150);
3559
3560         /* enable CPU FDI TX and PCH FDI RX */
3561         reg = FDI_TX_CTL(pipe);
3562         temp = I915_READ(reg);
3563         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3564         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3565         temp &= ~FDI_LINK_TRAIN_NONE;
3566         temp |= FDI_LINK_TRAIN_PATTERN_1;
3567         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568         /* SNB-B */
3569         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3570         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3571
3572         I915_WRITE(FDI_RX_MISC(pipe),
3573                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3574
3575         reg = FDI_RX_CTL(pipe);
3576         temp = I915_READ(reg);
3577         if (HAS_PCH_CPT(dev)) {
3578                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3580         } else {
3581                 temp &= ~FDI_LINK_TRAIN_NONE;
3582                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3583         }
3584         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3585
3586         POSTING_READ(reg);
3587         udelay(150);
3588
3589         for (i = 0; i < 4; i++) {
3590                 reg = FDI_TX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593                 temp |= snb_b_fdi_train_param[i];
3594                 I915_WRITE(reg, temp);
3595
3596                 POSTING_READ(reg);
3597                 udelay(500);
3598
3599                 for (retry = 0; retry < 5; retry++) {
3600                         reg = FDI_RX_IIR(pipe);
3601                         temp = I915_READ(reg);
3602                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603                         if (temp & FDI_RX_BIT_LOCK) {
3604                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3606                                 break;
3607                         }
3608                         udelay(50);
3609                 }
3610                 if (retry < 5)
3611                         break;
3612         }
3613         if (i == 4)
3614                 DRM_ERROR("FDI train 1 fail!\n");
3615
3616         /* Train 2 */
3617         reg = FDI_TX_CTL(pipe);
3618         temp = I915_READ(reg);
3619         temp &= ~FDI_LINK_TRAIN_NONE;
3620         temp |= FDI_LINK_TRAIN_PATTERN_2;
3621         if (IS_GEN6(dev)) {
3622                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623                 /* SNB-B */
3624                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3625         }
3626         I915_WRITE(reg, temp);
3627
3628         reg = FDI_RX_CTL(pipe);
3629         temp = I915_READ(reg);
3630         if (HAS_PCH_CPT(dev)) {
3631                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3632                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3633         } else {
3634                 temp &= ~FDI_LINK_TRAIN_NONE;
3635                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3636         }
3637         I915_WRITE(reg, temp);
3638
3639         POSTING_READ(reg);
3640         udelay(150);
3641
3642         for (i = 0; i < 4; i++) {
3643                 reg = FDI_TX_CTL(pipe);
3644                 temp = I915_READ(reg);
3645                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3646                 temp |= snb_b_fdi_train_param[i];
3647                 I915_WRITE(reg, temp);
3648
3649                 POSTING_READ(reg);
3650                 udelay(500);
3651
3652                 for (retry = 0; retry < 5; retry++) {
3653                         reg = FDI_RX_IIR(pipe);
3654                         temp = I915_READ(reg);
3655                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3656                         if (temp & FDI_RX_SYMBOL_LOCK) {
3657                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3659                                 break;
3660                         }
3661                         udelay(50);
3662                 }
3663                 if (retry < 5)
3664                         break;
3665         }
3666         if (i == 4)
3667                 DRM_ERROR("FDI train 2 fail!\n");
3668
3669         DRM_DEBUG_KMS("FDI train done.\n");
3670 }
3671
3672 /* Manual link training for Ivy Bridge A0 parts */
3673 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3674 {
3675         struct drm_device *dev = crtc->dev;
3676         struct drm_i915_private *dev_priv = dev->dev_private;
3677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678         int pipe = intel_crtc->pipe;
3679         u32 reg, temp, i, j;
3680
3681         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3682            for train result */
3683         reg = FDI_RX_IMR(pipe);
3684         temp = I915_READ(reg);
3685         temp &= ~FDI_RX_SYMBOL_LOCK;
3686         temp &= ~FDI_RX_BIT_LOCK;
3687         I915_WRITE(reg, temp);
3688
3689         POSTING_READ(reg);
3690         udelay(150);
3691
3692         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3693                       I915_READ(FDI_RX_IIR(pipe)));
3694
3695         /* Try each vswing and preemphasis setting twice before moving on */
3696         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3697                 /* disable first in case we need to retry */
3698                 reg = FDI_TX_CTL(pipe);
3699                 temp = I915_READ(reg);
3700                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3701                 temp &= ~FDI_TX_ENABLE;
3702                 I915_WRITE(reg, temp);
3703
3704                 reg = FDI_RX_CTL(pipe);
3705                 temp = I915_READ(reg);
3706                 temp &= ~FDI_LINK_TRAIN_AUTO;
3707                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708                 temp &= ~FDI_RX_ENABLE;
3709                 I915_WRITE(reg, temp);
3710
3711                 /* enable CPU FDI TX and PCH FDI RX */
3712                 reg = FDI_TX_CTL(pipe);
3713                 temp = I915_READ(reg);
3714                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3715                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3716                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3717                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3718                 temp |= snb_b_fdi_train_param[j/2];
3719                 temp |= FDI_COMPOSITE_SYNC;
3720                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3721
3722                 I915_WRITE(FDI_RX_MISC(pipe),
3723                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3724
3725                 reg = FDI_RX_CTL(pipe);
3726                 temp = I915_READ(reg);
3727                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728                 temp |= FDI_COMPOSITE_SYNC;
3729                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3730
3731                 POSTING_READ(reg);
3732                 udelay(1); /* should be 0.5us */
3733
3734                 for (i = 0; i < 4; i++) {
3735                         reg = FDI_RX_IIR(pipe);
3736                         temp = I915_READ(reg);
3737                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739                         if (temp & FDI_RX_BIT_LOCK ||
3740                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3741                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3742                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3743                                               i);
3744                                 break;
3745                         }
3746                         udelay(1); /* should be 0.5us */
3747                 }
3748                 if (i == 4) {
3749                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3750                         continue;
3751                 }
3752
3753                 /* Train 2 */
3754                 reg = FDI_TX_CTL(pipe);
3755                 temp = I915_READ(reg);
3756                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3757                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3758                 I915_WRITE(reg, temp);
3759
3760                 reg = FDI_RX_CTL(pipe);
3761                 temp = I915_READ(reg);
3762                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3763                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3764                 I915_WRITE(reg, temp);
3765
3766                 POSTING_READ(reg);
3767                 udelay(2); /* should be 1.5us */
3768
3769                 for (i = 0; i < 4; i++) {
3770                         reg = FDI_RX_IIR(pipe);
3771                         temp = I915_READ(reg);
3772                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3773
3774                         if (temp & FDI_RX_SYMBOL_LOCK ||
3775                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3776                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3777                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3778                                               i);
3779                                 goto train_done;
3780                         }
3781                         udelay(2); /* should be 1.5us */
3782                 }
3783                 if (i == 4)
3784                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3785         }
3786
3787 train_done:
3788         DRM_DEBUG_KMS("FDI train done.\n");
3789 }
3790
3791 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3792 {
3793         struct drm_device *dev = intel_crtc->base.dev;
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         int pipe = intel_crtc->pipe;
3796         u32 reg, temp;
3797
3798
3799         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3800         reg = FDI_RX_CTL(pipe);
3801         temp = I915_READ(reg);
3802         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3803         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3804         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3805         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3806
3807         POSTING_READ(reg);
3808         udelay(200);
3809
3810         /* Switch from Rawclk to PCDclk */
3811         temp = I915_READ(reg);
3812         I915_WRITE(reg, temp | FDI_PCDCLK);
3813
3814         POSTING_READ(reg);
3815         udelay(200);
3816
3817         /* Enable CPU FDI TX PLL, always on for Ironlake */
3818         reg = FDI_TX_CTL(pipe);
3819         temp = I915_READ(reg);
3820         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3821                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3822
3823                 POSTING_READ(reg);
3824                 udelay(100);
3825         }
3826 }
3827
3828 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3829 {
3830         struct drm_device *dev = intel_crtc->base.dev;
3831         struct drm_i915_private *dev_priv = dev->dev_private;
3832         int pipe = intel_crtc->pipe;
3833         u32 reg, temp;
3834
3835         /* Switch from PCDclk to Rawclk */
3836         reg = FDI_RX_CTL(pipe);
3837         temp = I915_READ(reg);
3838         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3839
3840         /* Disable CPU FDI TX PLL */
3841         reg = FDI_TX_CTL(pipe);
3842         temp = I915_READ(reg);
3843         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3844
3845         POSTING_READ(reg);
3846         udelay(100);
3847
3848         reg = FDI_RX_CTL(pipe);
3849         temp = I915_READ(reg);
3850         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3851
3852         /* Wait for the clocks to turn off. */
3853         POSTING_READ(reg);
3854         udelay(100);
3855 }
3856
3857 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3858 {
3859         struct drm_device *dev = crtc->dev;
3860         struct drm_i915_private *dev_priv = dev->dev_private;
3861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862         int pipe = intel_crtc->pipe;
3863         u32 reg, temp;
3864
3865         /* disable CPU FDI tx and PCH FDI rx */
3866         reg = FDI_TX_CTL(pipe);
3867         temp = I915_READ(reg);
3868         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3869         POSTING_READ(reg);
3870
3871         reg = FDI_RX_CTL(pipe);
3872         temp = I915_READ(reg);
3873         temp &= ~(0x7 << 16);
3874         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3875         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3876
3877         POSTING_READ(reg);
3878         udelay(100);
3879
3880         /* Ironlake workaround, disable clock pointer after downing FDI */
3881         if (HAS_PCH_IBX(dev))
3882                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3883
3884         /* still set train pattern 1 */
3885         reg = FDI_TX_CTL(pipe);
3886         temp = I915_READ(reg);
3887         temp &= ~FDI_LINK_TRAIN_NONE;
3888         temp |= FDI_LINK_TRAIN_PATTERN_1;
3889         I915_WRITE(reg, temp);
3890
3891         reg = FDI_RX_CTL(pipe);
3892         temp = I915_READ(reg);
3893         if (HAS_PCH_CPT(dev)) {
3894                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3895                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3896         } else {
3897                 temp &= ~FDI_LINK_TRAIN_NONE;
3898                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3899         }
3900         /* BPC in FDI rx is consistent with that in PIPECONF */
3901         temp &= ~(0x07 << 16);
3902         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3903         I915_WRITE(reg, temp);
3904
3905         POSTING_READ(reg);
3906         udelay(100);
3907 }
3908
3909 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3910 {
3911         struct intel_crtc *crtc;
3912
3913         /* Note that we don't need to be called with mode_config.lock here
3914          * as our list of CRTC objects is static for the lifetime of the
3915          * device and so cannot disappear as we iterate. Similarly, we can
3916          * happily treat the predicates as racy, atomic checks as userspace
3917          * cannot claim and pin a new fb without at least acquring the
3918          * struct_mutex and so serialising with us.
3919          */
3920         for_each_intel_crtc(dev, crtc) {
3921                 if (atomic_read(&crtc->unpin_work_count) == 0)
3922                         continue;
3923
3924                 if (crtc->unpin_work)
3925                         intel_wait_for_vblank(dev, crtc->pipe);
3926
3927                 return true;
3928         }
3929
3930         return false;
3931 }
3932
3933 static void page_flip_completed(struct intel_crtc *intel_crtc)
3934 {
3935         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3936         struct intel_unpin_work *work = intel_crtc->unpin_work;
3937
3938         /* ensure that the unpin work is consistent wrt ->pending. */
3939         smp_rmb();
3940         intel_crtc->unpin_work = NULL;
3941
3942         if (work->event)
3943                 drm_send_vblank_event(intel_crtc->base.dev,
3944                                       intel_crtc->pipe,
3945                                       work->event);
3946
3947         drm_crtc_vblank_put(&intel_crtc->base);
3948
3949         wake_up_all(&dev_priv->pending_flip_queue);
3950         queue_work(dev_priv->wq, &work->work);
3951
3952         trace_i915_flip_complete(intel_crtc->plane,
3953                                  work->pending_flip_obj);
3954 }
3955
3956 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960
3961         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3962         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3963                                        !intel_crtc_has_pending_flip(crtc),
3964                                        60*HZ) == 0)) {
3965                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3966
3967                 spin_lock_irq(&dev->event_lock);
3968                 if (intel_crtc->unpin_work) {
3969                         WARN_ONCE(1, "Removing stuck page flip\n");
3970                         page_flip_completed(intel_crtc);
3971                 }
3972                 spin_unlock_irq(&dev->event_lock);
3973         }
3974
3975         if (crtc->primary->fb) {
3976                 mutex_lock(&dev->struct_mutex);
3977                 intel_finish_fb(crtc->primary->fb);
3978                 mutex_unlock(&dev->struct_mutex);
3979         }
3980 }
3981
3982 /* Program iCLKIP clock to the desired frequency */
3983 static void lpt_program_iclkip(struct drm_crtc *crtc)
3984 {
3985         struct drm_device *dev = crtc->dev;
3986         struct drm_i915_private *dev_priv = dev->dev_private;
3987         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3988         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3989         u32 temp;
3990
3991         mutex_lock(&dev_priv->sb_lock);
3992
3993         /* It is necessary to ungate the pixclk gate prior to programming
3994          * the divisors, and gate it back when it is done.
3995          */
3996         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3997
3998         /* Disable SSCCTL */
3999         intel_sbi_write(dev_priv, SBI_SSCCTL6,
4000                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4001                                 SBI_SSCCTL_DISABLE,
4002                         SBI_ICLK);
4003
4004         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
4005         if (clock == 20000) {
4006                 auxdiv = 1;
4007                 divsel = 0x41;
4008                 phaseinc = 0x20;
4009         } else {
4010                 /* The iCLK virtual clock root frequency is in MHz,
4011                  * but the adjusted_mode->crtc_clock in in KHz. To get the
4012                  * divisors, it is necessary to divide one by another, so we
4013                  * convert the virtual clock precision to KHz here for higher
4014                  * precision.
4015                  */
4016                 u32 iclk_virtual_root_freq = 172800 * 1000;
4017                 u32 iclk_pi_range = 64;
4018                 u32 desired_divisor, msb_divisor_value, pi_value;
4019
4020                 desired_divisor = (iclk_virtual_root_freq / clock);
4021                 msb_divisor_value = desired_divisor / iclk_pi_range;
4022                 pi_value = desired_divisor % iclk_pi_range;
4023
4024                 auxdiv = 0;
4025                 divsel = msb_divisor_value - 2;
4026                 phaseinc = pi_value;
4027         }
4028
4029         /* This should not happen with any sane values */
4030         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4034
4035         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4036                         clock,
4037                         auxdiv,
4038                         divsel,
4039                         phasedir,
4040                         phaseinc);
4041
4042         /* Program SSCDIVINTPHASE6 */
4043         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4044         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4050         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4051
4052         /* Program SSCAUXDIV */
4053         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4054         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4056         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4057
4058         /* Enable modulator and associated divider */
4059         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4060         temp &= ~SBI_SSCCTL_DISABLE;
4061         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4062
4063         /* Wait for initialization time */
4064         udelay(24);
4065
4066         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4067
4068         mutex_unlock(&dev_priv->sb_lock);
4069 }
4070
4071 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072                                                 enum pipe pch_transcoder)
4073 {
4074         struct drm_device *dev = crtc->base.dev;
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4077
4078         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079                    I915_READ(HTOTAL(cpu_transcoder)));
4080         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081                    I915_READ(HBLANK(cpu_transcoder)));
4082         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083                    I915_READ(HSYNC(cpu_transcoder)));
4084
4085         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086                    I915_READ(VTOTAL(cpu_transcoder)));
4087         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088                    I915_READ(VBLANK(cpu_transcoder)));
4089         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090                    I915_READ(VSYNC(cpu_transcoder)));
4091         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4093 }
4094
4095 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4096 {
4097         struct drm_i915_private *dev_priv = dev->dev_private;
4098         uint32_t temp;
4099
4100         temp = I915_READ(SOUTH_CHICKEN1);
4101         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4102                 return;
4103
4104         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4106
4107         temp &= ~FDI_BC_BIFURCATION_SELECT;
4108         if (enable)
4109                 temp |= FDI_BC_BIFURCATION_SELECT;
4110
4111         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4112         I915_WRITE(SOUTH_CHICKEN1, temp);
4113         POSTING_READ(SOUTH_CHICKEN1);
4114 }
4115
4116 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4117 {
4118         struct drm_device *dev = intel_crtc->base.dev;
4119
4120         switch (intel_crtc->pipe) {
4121         case PIPE_A:
4122                 break;
4123         case PIPE_B:
4124                 if (intel_crtc->config->fdi_lanes > 2)
4125                         cpt_set_fdi_bc_bifurcation(dev, false);
4126                 else
4127                         cpt_set_fdi_bc_bifurcation(dev, true);
4128
4129                 break;
4130         case PIPE_C:
4131                 cpt_set_fdi_bc_bifurcation(dev, true);
4132
4133                 break;
4134         default:
4135                 BUG();
4136         }
4137 }
4138
4139 /*
4140  * Enable PCH resources required for PCH ports:
4141  *   - PCH PLLs
4142  *   - FDI training & RX/TX
4143  *   - update transcoder timings
4144  *   - DP transcoding bits
4145  *   - transcoder
4146  */
4147 static void ironlake_pch_enable(struct drm_crtc *crtc)
4148 {
4149         struct drm_device *dev = crtc->dev;
4150         struct drm_i915_private *dev_priv = dev->dev_private;
4151         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152         int pipe = intel_crtc->pipe;
4153         u32 reg, temp;
4154
4155         assert_pch_transcoder_disabled(dev_priv, pipe);
4156
4157         if (IS_IVYBRIDGE(dev))
4158                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4159
4160         /* Write the TU size bits before fdi link training, so that error
4161          * detection works. */
4162         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4164
4165         /* For PCH output, training FDI link */
4166         dev_priv->display.fdi_link_train(crtc);
4167
4168         /* We need to program the right clock selection before writing the pixel
4169          * mutliplier into the DPLL. */
4170         if (HAS_PCH_CPT(dev)) {
4171                 u32 sel;
4172
4173                 temp = I915_READ(PCH_DPLL_SEL);
4174                 temp |= TRANS_DPLL_ENABLE(pipe);
4175                 sel = TRANS_DPLLB_SEL(pipe);
4176                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4177                         temp |= sel;
4178                 else
4179                         temp &= ~sel;
4180                 I915_WRITE(PCH_DPLL_SEL, temp);
4181         }
4182
4183         /* XXX: pch pll's can be enabled any time before we enable the PCH
4184          * transcoder, and we actually should do this to not upset any PCH
4185          * transcoder that already use the clock when we share it.
4186          *
4187          * Note that enable_shared_dpll tries to do the right thing, but
4188          * get_shared_dpll unconditionally resets the pll - we need that to have
4189          * the right LVDS enable sequence. */
4190         intel_enable_shared_dpll(intel_crtc);
4191
4192         /* set transcoder timing, panel must allow it */
4193         assert_panel_unlocked(dev_priv, pipe);
4194         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4195
4196         intel_fdi_normal_train(crtc);
4197
4198         /* For PCH DP, enable TRANS_DP_CTL */
4199         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4200                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4201                 reg = TRANS_DP_CTL(pipe);
4202                 temp = I915_READ(reg);
4203                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4204                           TRANS_DP_SYNC_MASK |
4205                           TRANS_DP_BPC_MASK);
4206                 temp |= TRANS_DP_OUTPUT_ENABLE;
4207                 temp |= bpc << 9; /* same format but at 11:9 */
4208
4209                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4210                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4211                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4212                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4213
4214                 switch (intel_trans_dp_port_sel(crtc)) {
4215                 case PCH_DP_B:
4216                         temp |= TRANS_DP_PORT_SEL_B;
4217                         break;
4218                 case PCH_DP_C:
4219                         temp |= TRANS_DP_PORT_SEL_C;
4220                         break;
4221                 case PCH_DP_D:
4222                         temp |= TRANS_DP_PORT_SEL_D;
4223                         break;
4224                 default:
4225                         BUG();
4226                 }
4227
4228                 I915_WRITE(reg, temp);
4229         }
4230
4231         ironlake_enable_pch_transcoder(dev_priv, pipe);
4232 }
4233
4234 static void lpt_pch_enable(struct drm_crtc *crtc)
4235 {
4236         struct drm_device *dev = crtc->dev;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4239         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4240
4241         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4242
4243         lpt_program_iclkip(crtc);
4244
4245         /* Set transcoder timing. */
4246         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4247
4248         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4249 }
4250
4251 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252                                                 struct intel_crtc_state *crtc_state)
4253 {
4254         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4255         struct intel_shared_dpll *pll;
4256         struct intel_shared_dpll_config *shared_dpll;
4257         enum intel_dpll_id i;
4258
4259         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4260
4261         if (HAS_PCH_IBX(dev_priv->dev)) {
4262                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4263                 i = (enum intel_dpll_id) crtc->pipe;
4264                 pll = &dev_priv->shared_dplls[i];
4265
4266                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267                               crtc->base.base.id, pll->name);
4268
4269                 WARN_ON(shared_dpll[i].crtc_mask);
4270
4271                 goto found;
4272         }
4273
4274         if (IS_BROXTON(dev_priv->dev)) {
4275                 /* PLL is attached to port in bxt */
4276                 struct intel_encoder *encoder;
4277                 struct intel_digital_port *intel_dig_port;
4278
4279                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280                 if (WARN_ON(!encoder))
4281                         return NULL;
4282
4283                 intel_dig_port = enc_to_dig_port(&encoder->base);
4284                 /* 1:1 mapping between ports and PLLs */
4285                 i = (enum intel_dpll_id)intel_dig_port->port;
4286                 pll = &dev_priv->shared_dplls[i];
4287                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288                         crtc->base.base.id, pll->name);
4289                 WARN_ON(shared_dpll[i].crtc_mask);
4290
4291                 goto found;
4292         }
4293
4294         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295                 pll = &dev_priv->shared_dplls[i];
4296
4297                 /* Only want to check enabled timings first */
4298                 if (shared_dpll[i].crtc_mask == 0)
4299                         continue;
4300
4301                 if (memcmp(&crtc_state->dpll_hw_state,
4302                            &shared_dpll[i].hw_state,
4303                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4304                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4305                                       crtc->base.base.id, pll->name,
4306                                       shared_dpll[i].crtc_mask,
4307                                       pll->active);
4308                         goto found;
4309                 }
4310         }
4311
4312         /* Ok no matching timings, maybe there's a free one? */
4313         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314                 pll = &dev_priv->shared_dplls[i];
4315                 if (shared_dpll[i].crtc_mask == 0) {
4316                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317                                       crtc->base.base.id, pll->name);
4318                         goto found;
4319                 }
4320         }
4321
4322         return NULL;
4323
4324 found:
4325         if (shared_dpll[i].crtc_mask == 0)
4326                 shared_dpll[i].hw_state =
4327                         crtc_state->dpll_hw_state;
4328
4329         crtc_state->shared_dpll = i;
4330         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331                          pipe_name(crtc->pipe));
4332
4333         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4334
4335         return pll;
4336 }
4337
4338 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4339 {
4340         struct drm_i915_private *dev_priv = to_i915(state->dev);
4341         struct intel_shared_dpll_config *shared_dpll;
4342         struct intel_shared_dpll *pll;
4343         enum intel_dpll_id i;
4344
4345         if (!to_intel_atomic_state(state)->dpll_set)
4346                 return;
4347
4348         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4349         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350                 pll = &dev_priv->shared_dplls[i];
4351                 pll->config = shared_dpll[i];
4352         }
4353 }
4354
4355 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4356 {
4357         struct drm_i915_private *dev_priv = dev->dev_private;
4358         int dslreg = PIPEDSL(pipe);
4359         u32 temp;
4360
4361         temp = I915_READ(dslreg);
4362         udelay(500);
4363         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4364                 if (wait_for(I915_READ(dslreg) != temp, 5))
4365                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4366         }
4367 }
4368
4369 static int
4370 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4371                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4372                   int src_w, int src_h, int dst_w, int dst_h)
4373 {
4374         struct intel_crtc_scaler_state *scaler_state =
4375                 &crtc_state->scaler_state;
4376         struct intel_crtc *intel_crtc =
4377                 to_intel_crtc(crtc_state->base.crtc);
4378         int need_scaling;
4379
4380         need_scaling = intel_rotation_90_or_270(rotation) ?
4381                 (src_h != dst_w || src_w != dst_h):
4382                 (src_w != dst_w || src_h != dst_h);
4383
4384         /*
4385          * if plane is being disabled or scaler is no more required or force detach
4386          *  - free scaler binded to this plane/crtc
4387          *  - in order to do this, update crtc->scaler_usage
4388          *
4389          * Here scaler state in crtc_state is set free so that
4390          * scaler can be assigned to other user. Actual register
4391          * update to free the scaler is done in plane/panel-fit programming.
4392          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4393          */
4394         if (force_detach || !need_scaling) {
4395                 if (*scaler_id >= 0) {
4396                         scaler_state->scaler_users &= ~(1 << scaler_user);
4397                         scaler_state->scalers[*scaler_id].in_use = 0;
4398
4399                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4400                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4401                                 intel_crtc->pipe, scaler_user, *scaler_id,
4402                                 scaler_state->scaler_users);
4403                         *scaler_id = -1;
4404                 }
4405                 return 0;
4406         }
4407
4408         /* range checks */
4409         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4410                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4411
4412                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4413                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4414                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4415                         "size is out of scaler range\n",
4416                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4417                 return -EINVAL;
4418         }
4419
4420         /* mark this plane as a scaler user in crtc_state */
4421         scaler_state->scaler_users |= (1 << scaler_user);
4422         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4424                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4425                 scaler_state->scaler_users);
4426
4427         return 0;
4428 }
4429
4430 /**
4431  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4432  *
4433  * @state: crtc's scaler state
4434  *
4435  * Return
4436  *     0 - scaler_usage updated successfully
4437  *    error - requested scaling cannot be supported or other error condition
4438  */
4439 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4440 {
4441         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4442         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4443
4444         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4445                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4446
4447         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4448                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4449                 state->pipe_src_w, state->pipe_src_h,
4450                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4451 }
4452
4453 /**
4454  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4455  *
4456  * @state: crtc's scaler state
4457  * @plane_state: atomic plane state to update
4458  *
4459  * Return
4460  *     0 - scaler_usage updated successfully
4461  *    error - requested scaling cannot be supported or other error condition
4462  */
4463 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4464                                    struct intel_plane_state *plane_state)
4465 {
4466
4467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4468         struct intel_plane *intel_plane =
4469                 to_intel_plane(plane_state->base.plane);
4470         struct drm_framebuffer *fb = plane_state->base.fb;
4471         int ret;
4472
4473         bool force_detach = !fb || !plane_state->visible;
4474
4475         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4476                       intel_plane->base.base.id, intel_crtc->pipe,
4477                       drm_plane_index(&intel_plane->base));
4478
4479         ret = skl_update_scaler(crtc_state, force_detach,
4480                                 drm_plane_index(&intel_plane->base),
4481                                 &plane_state->scaler_id,
4482                                 plane_state->base.rotation,
4483                                 drm_rect_width(&plane_state->src) >> 16,
4484                                 drm_rect_height(&plane_state->src) >> 16,
4485                                 drm_rect_width(&plane_state->dst),
4486                                 drm_rect_height(&plane_state->dst));
4487
4488         if (ret || plane_state->scaler_id < 0)
4489                 return ret;
4490
4491         /* check colorkey */
4492         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4493                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4494                               intel_plane->base.base.id);
4495                 return -EINVAL;
4496         }
4497
4498         /* Check src format */
4499         switch (fb->pixel_format) {
4500         case DRM_FORMAT_RGB565:
4501         case DRM_FORMAT_XBGR8888:
4502         case DRM_FORMAT_XRGB8888:
4503         case DRM_FORMAT_ABGR8888:
4504         case DRM_FORMAT_ARGB8888:
4505         case DRM_FORMAT_XRGB2101010:
4506         case DRM_FORMAT_XBGR2101010:
4507         case DRM_FORMAT_YUYV:
4508         case DRM_FORMAT_YVYU:
4509         case DRM_FORMAT_UYVY:
4510         case DRM_FORMAT_VYUY:
4511                 break;
4512         default:
4513                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4514                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4515                 return -EINVAL;
4516         }
4517
4518         return 0;
4519 }
4520
4521 static void skylake_scaler_disable(struct intel_crtc *crtc)
4522 {
4523         int i;
4524
4525         for (i = 0; i < crtc->num_scalers; i++)
4526                 skl_detach_scaler(crtc, i);
4527 }
4528
4529 static void skylake_pfit_enable(struct intel_crtc *crtc)
4530 {
4531         struct drm_device *dev = crtc->base.dev;
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533         int pipe = crtc->pipe;
4534         struct intel_crtc_scaler_state *scaler_state =
4535                 &crtc->config->scaler_state;
4536
4537         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4538
4539         if (crtc->config->pch_pfit.enabled) {
4540                 int id;
4541
4542                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4543                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4544                         return;
4545                 }
4546
4547                 id = scaler_state->scaler_id;
4548                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4549                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4550                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4551                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4552
4553                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4554         }
4555 }
4556
4557 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4558 {
4559         struct drm_device *dev = crtc->base.dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         int pipe = crtc->pipe;
4562
4563         if (crtc->config->pch_pfit.enabled) {
4564                 /* Force use of hard-coded filter coefficients
4565                  * as some pre-programmed values are broken,
4566                  * e.g. x201.
4567                  */
4568                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4569                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4570                                                  PF_PIPE_SEL_IVB(pipe));
4571                 else
4572                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4573                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4574                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4575         }
4576 }
4577
4578 void hsw_enable_ips(struct intel_crtc *crtc)
4579 {
4580         struct drm_device *dev = crtc->base.dev;
4581         struct drm_i915_private *dev_priv = dev->dev_private;
4582
4583         if (!crtc->config->ips_enabled)
4584                 return;
4585
4586         /* We can only enable IPS after we enable a plane and wait for a vblank */
4587         intel_wait_for_vblank(dev, crtc->pipe);
4588
4589         assert_plane_enabled(dev_priv, crtc->plane);
4590         if (IS_BROADWELL(dev)) {
4591                 mutex_lock(&dev_priv->rps.hw_lock);
4592                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4593                 mutex_unlock(&dev_priv->rps.hw_lock);
4594                 /* Quoting Art Runyan: "its not safe to expect any particular
4595                  * value in IPS_CTL bit 31 after enabling IPS through the
4596                  * mailbox." Moreover, the mailbox may return a bogus state,
4597                  * so we need to just enable it and continue on.
4598                  */
4599         } else {
4600                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4601                 /* The bit only becomes 1 in the next vblank, so this wait here
4602                  * is essentially intel_wait_for_vblank. If we don't have this
4603                  * and don't wait for vblanks until the end of crtc_enable, then
4604                  * the HW state readout code will complain that the expected
4605                  * IPS_CTL value is not the one we read. */
4606                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4607                         DRM_ERROR("Timed out waiting for IPS enable\n");
4608         }
4609 }
4610
4611 void hsw_disable_ips(struct intel_crtc *crtc)
4612 {
4613         struct drm_device *dev = crtc->base.dev;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615
4616         if (!crtc->config->ips_enabled)
4617                 return;
4618
4619         assert_plane_enabled(dev_priv, crtc->plane);
4620         if (IS_BROADWELL(dev)) {
4621                 mutex_lock(&dev_priv->rps.hw_lock);
4622                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4623                 mutex_unlock(&dev_priv->rps.hw_lock);
4624                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4625                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4626                         DRM_ERROR("Timed out waiting for IPS disable\n");
4627         } else {
4628                 I915_WRITE(IPS_CTL, 0);
4629                 POSTING_READ(IPS_CTL);
4630         }
4631
4632         /* We need to wait for a vblank before we can disable the plane. */
4633         intel_wait_for_vblank(dev, crtc->pipe);
4634 }
4635
4636 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4637 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4638 {
4639         struct drm_device *dev = crtc->dev;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642         enum pipe pipe = intel_crtc->pipe;
4643         int i;
4644         bool reenable_ips = false;
4645
4646         /* The clocks have to be on to load the palette. */
4647         if (!crtc->state->active)
4648                 return;
4649
4650         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4651                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4652                         assert_dsi_pll_enabled(dev_priv);
4653                 else
4654                         assert_pll_enabled(dev_priv, pipe);
4655         }
4656
4657         /* Workaround : Do not read or write the pipe palette/gamma data while
4658          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4659          */
4660         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4661             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4662              GAMMA_MODE_MODE_SPLIT)) {
4663                 hsw_disable_ips(intel_crtc);
4664                 reenable_ips = true;
4665         }
4666
4667         for (i = 0; i < 256; i++) {
4668                 u32 palreg;
4669
4670                 if (HAS_GMCH_DISPLAY(dev))
4671                         palreg = PALETTE(pipe, i);
4672                 else
4673                         palreg = LGC_PALETTE(pipe, i);
4674
4675                 I915_WRITE(palreg,
4676                            (intel_crtc->lut_r[i] << 16) |
4677                            (intel_crtc->lut_g[i] << 8) |
4678                            intel_crtc->lut_b[i]);
4679         }
4680
4681         if (reenable_ips)
4682                 hsw_enable_ips(intel_crtc);
4683 }
4684
4685 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4686 {
4687         if (intel_crtc->overlay) {
4688                 struct drm_device *dev = intel_crtc->base.dev;
4689                 struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691                 mutex_lock(&dev->struct_mutex);
4692                 dev_priv->mm.interruptible = false;
4693                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4694                 dev_priv->mm.interruptible = true;
4695                 mutex_unlock(&dev->struct_mutex);
4696         }
4697
4698         /* Let userspace switch the overlay on again. In most cases userspace
4699          * has to recompute where to put it anyway.
4700          */
4701 }
4702
4703 /**
4704  * intel_post_enable_primary - Perform operations after enabling primary plane
4705  * @crtc: the CRTC whose primary plane was just enabled
4706  *
4707  * Performs potentially sleeping operations that must be done after the primary
4708  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4709  * called due to an explicit primary plane update, or due to an implicit
4710  * re-enable that is caused when a sprite plane is updated to no longer
4711  * completely hide the primary plane.
4712  */
4713 static void
4714 intel_post_enable_primary(struct drm_crtc *crtc)
4715 {
4716         struct drm_device *dev = crtc->dev;
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719         int pipe = intel_crtc->pipe;
4720
4721         /*
4722          * BDW signals flip done immediately if the plane
4723          * is disabled, even if the plane enable is already
4724          * armed to occur at the next vblank :(
4725          */
4726         if (IS_BROADWELL(dev))
4727                 intel_wait_for_vblank(dev, pipe);
4728
4729         /*
4730          * FIXME IPS should be fine as long as one plane is
4731          * enabled, but in practice it seems to have problems
4732          * when going from primary only to sprite only and vice
4733          * versa.
4734          */
4735         hsw_enable_ips(intel_crtc);
4736
4737         /*
4738          * Gen2 reports pipe underruns whenever all planes are disabled.
4739          * So don't enable underrun reporting before at least some planes
4740          * are enabled.
4741          * FIXME: Need to fix the logic to work when we turn off all planes
4742          * but leave the pipe running.
4743          */
4744         if (IS_GEN2(dev))
4745                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4746
4747         /* Underruns don't raise interrupts, so check manually. */
4748         if (HAS_GMCH_DISPLAY(dev))
4749                 i9xx_check_fifo_underruns(dev_priv);
4750 }
4751
4752 /**
4753  * intel_pre_disable_primary - Perform operations before disabling primary plane
4754  * @crtc: the CRTC whose primary plane is to be disabled
4755  *
4756  * Performs potentially sleeping operations that must be done before the
4757  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4758  * be called due to an explicit primary plane update, or due to an implicit
4759  * disable that is caused when a sprite plane completely hides the primary
4760  * plane.
4761  */
4762 static void
4763 intel_pre_disable_primary(struct drm_crtc *crtc)
4764 {
4765         struct drm_device *dev = crtc->dev;
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768         int pipe = intel_crtc->pipe;
4769
4770         /*
4771          * Gen2 reports pipe underruns whenever all planes are disabled.
4772          * So diasble underrun reporting before all the planes get disabled.
4773          * FIXME: Need to fix the logic to work when we turn off all planes
4774          * but leave the pipe running.
4775          */
4776         if (IS_GEN2(dev))
4777                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4778
4779         /*
4780          * Vblank time updates from the shadow to live plane control register
4781          * are blocked if the memory self-refresh mode is active at that
4782          * moment. So to make sure the plane gets truly disabled, disable
4783          * first the self-refresh mode. The self-refresh enable bit in turn
4784          * will be checked/applied by the HW only at the next frame start
4785          * event which is after the vblank start event, so we need to have a
4786          * wait-for-vblank between disabling the plane and the pipe.
4787          */
4788         if (HAS_GMCH_DISPLAY(dev)) {
4789                 intel_set_memory_cxsr(dev_priv, false);
4790                 dev_priv->wm.vlv.cxsr = false;
4791                 intel_wait_for_vblank(dev, pipe);
4792         }
4793
4794         /*
4795          * FIXME IPS should be fine as long as one plane is
4796          * enabled, but in practice it seems to have problems
4797          * when going from primary only to sprite only and vice
4798          * versa.
4799          */
4800         hsw_disable_ips(intel_crtc);
4801 }
4802
4803 static void intel_post_plane_update(struct intel_crtc *crtc)
4804 {
4805         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4806         struct drm_device *dev = crtc->base.dev;
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct drm_plane *plane;
4809
4810         if (atomic->wait_vblank)
4811                 intel_wait_for_vblank(dev, crtc->pipe);
4812
4813         intel_frontbuffer_flip(dev, atomic->fb_bits);
4814
4815         if (atomic->disable_cxsr)
4816                 crtc->wm.cxsr_allowed = true;
4817
4818         if (crtc->atomic.update_wm_post)
4819                 intel_update_watermarks(&crtc->base);
4820
4821         if (atomic->update_fbc)
4822                 intel_fbc_update(dev_priv);
4823
4824         if (atomic->post_enable_primary)
4825                 intel_post_enable_primary(&crtc->base);
4826
4827         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4828                 intel_update_sprite_watermarks(plane, &crtc->base,
4829                                                0, 0, 0, false, false);
4830
4831         memset(atomic, 0, sizeof(*atomic));
4832 }
4833
4834 static void intel_pre_plane_update(struct intel_crtc *crtc)
4835 {
4836         struct drm_device *dev = crtc->base.dev;
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4839         struct drm_plane *p;
4840
4841         /* Track fb's for any planes being disabled */
4842         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4843                 struct intel_plane *plane = to_intel_plane(p);
4844
4845                 mutex_lock(&dev->struct_mutex);
4846                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4847                                   plane->frontbuffer_bit);
4848                 mutex_unlock(&dev->struct_mutex);
4849         }
4850
4851         if (atomic->wait_for_flips)
4852                 intel_crtc_wait_for_pending_flips(&crtc->base);
4853
4854         if (atomic->disable_fbc)
4855                 intel_fbc_disable_crtc(crtc);
4856
4857         if (crtc->atomic.disable_ips)
4858                 hsw_disable_ips(crtc);
4859
4860         if (atomic->pre_disable_primary)
4861                 intel_pre_disable_primary(&crtc->base);
4862
4863         if (atomic->disable_cxsr) {
4864                 crtc->wm.cxsr_allowed = false;
4865                 intel_set_memory_cxsr(dev_priv, false);
4866         }
4867 }
4868
4869 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4870 {
4871         struct drm_device *dev = crtc->dev;
4872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4873         struct drm_plane *p;
4874         int pipe = intel_crtc->pipe;
4875
4876         intel_crtc_dpms_overlay_disable(intel_crtc);
4877
4878         drm_for_each_plane_mask(p, dev, plane_mask)
4879                 to_intel_plane(p)->disable_plane(p, crtc);
4880
4881         /*
4882          * FIXME: Once we grow proper nuclear flip support out of this we need
4883          * to compute the mask of flip planes precisely. For the time being
4884          * consider this a flip to a NULL plane.
4885          */
4886         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4887 }
4888
4889 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4890 {
4891         struct drm_device *dev = crtc->dev;
4892         struct drm_i915_private *dev_priv = dev->dev_private;
4893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4894         struct intel_encoder *encoder;
4895         int pipe = intel_crtc->pipe;
4896
4897         if (WARN_ON(intel_crtc->active))
4898                 return;
4899
4900         if (intel_crtc->config->has_pch_encoder)
4901                 intel_prepare_shared_dpll(intel_crtc);
4902
4903         if (intel_crtc->config->has_dp_encoder)
4904                 intel_dp_set_m_n(intel_crtc, M1_N1);
4905
4906         intel_set_pipe_timings(intel_crtc);
4907
4908         if (intel_crtc->config->has_pch_encoder) {
4909                 intel_cpu_transcoder_set_m_n(intel_crtc,
4910                                      &intel_crtc->config->fdi_m_n, NULL);
4911         }
4912
4913         ironlake_set_pipeconf(crtc);
4914
4915         intel_crtc->active = true;
4916
4917         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4918         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4919
4920         for_each_encoder_on_crtc(dev, crtc, encoder)
4921                 if (encoder->pre_enable)
4922                         encoder->pre_enable(encoder);
4923
4924         if (intel_crtc->config->has_pch_encoder) {
4925                 /* Note: FDI PLL enabling _must_ be done before we enable the
4926                  * cpu pipes, hence this is separate from all the other fdi/pch
4927                  * enabling. */
4928                 ironlake_fdi_pll_enable(intel_crtc);
4929         } else {
4930                 assert_fdi_tx_disabled(dev_priv, pipe);
4931                 assert_fdi_rx_disabled(dev_priv, pipe);
4932         }
4933
4934         ironlake_pfit_enable(intel_crtc);
4935
4936         /*
4937          * On ILK+ LUT must be loaded before the pipe is running but with
4938          * clocks enabled
4939          */
4940         intel_crtc_load_lut(crtc);
4941
4942         intel_update_watermarks(crtc);
4943         intel_enable_pipe(intel_crtc);
4944
4945         if (intel_crtc->config->has_pch_encoder)
4946                 ironlake_pch_enable(crtc);
4947
4948         assert_vblank_disabled(crtc);
4949         drm_crtc_vblank_on(crtc);
4950
4951         for_each_encoder_on_crtc(dev, crtc, encoder)
4952                 encoder->enable(encoder);
4953
4954         if (HAS_PCH_CPT(dev))
4955                 cpt_verify_modeset(dev, intel_crtc->pipe);
4956 }
4957
4958 /* IPS only exists on ULT machines and is tied to pipe A. */
4959 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4960 {
4961         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4962 }
4963
4964 static void haswell_crtc_enable(struct drm_crtc *crtc)
4965 {
4966         struct drm_device *dev = crtc->dev;
4967         struct drm_i915_private *dev_priv = dev->dev_private;
4968         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969         struct intel_encoder *encoder;
4970         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4971         struct intel_crtc_state *pipe_config =
4972                 to_intel_crtc_state(crtc->state);
4973
4974         if (WARN_ON(intel_crtc->active))
4975                 return;
4976
4977         if (intel_crtc_to_shared_dpll(intel_crtc))
4978                 intel_enable_shared_dpll(intel_crtc);
4979
4980         if (intel_crtc->config->has_dp_encoder)
4981                 intel_dp_set_m_n(intel_crtc, M1_N1);
4982
4983         intel_set_pipe_timings(intel_crtc);
4984
4985         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4986                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4987                            intel_crtc->config->pixel_multiplier - 1);
4988         }
4989
4990         if (intel_crtc->config->has_pch_encoder) {
4991                 intel_cpu_transcoder_set_m_n(intel_crtc,
4992                                      &intel_crtc->config->fdi_m_n, NULL);
4993         }
4994
4995         haswell_set_pipeconf(crtc);
4996
4997         intel_set_pipe_csc(crtc);
4998
4999         intel_crtc->active = true;
5000
5001         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5002         for_each_encoder_on_crtc(dev, crtc, encoder)
5003                 if (encoder->pre_enable)
5004                         encoder->pre_enable(encoder);
5005
5006         if (intel_crtc->config->has_pch_encoder) {
5007                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5008                                                       true);
5009                 dev_priv->display.fdi_link_train(crtc);
5010         }
5011
5012         intel_ddi_enable_pipe_clock(intel_crtc);
5013
5014         if (INTEL_INFO(dev)->gen >= 9)
5015                 skylake_pfit_enable(intel_crtc);
5016         else
5017                 ironlake_pfit_enable(intel_crtc);
5018
5019         /*
5020          * On ILK+ LUT must be loaded before the pipe is running but with
5021          * clocks enabled
5022          */
5023         intel_crtc_load_lut(crtc);
5024
5025         intel_ddi_set_pipe_settings(crtc);
5026         intel_ddi_enable_transcoder_func(crtc);
5027
5028         intel_update_watermarks(crtc);
5029         intel_enable_pipe(intel_crtc);
5030
5031         if (intel_crtc->config->has_pch_encoder)
5032                 lpt_pch_enable(crtc);
5033
5034         if (intel_crtc->config->dp_encoder_is_mst)
5035                 intel_ddi_set_vc_payload_alloc(crtc, true);
5036
5037         assert_vblank_disabled(crtc);
5038         drm_crtc_vblank_on(crtc);
5039
5040         for_each_encoder_on_crtc(dev, crtc, encoder) {
5041                 encoder->enable(encoder);
5042                 intel_opregion_notify_encoder(encoder, true);
5043         }
5044
5045         /* If we change the relative order between pipe/planes enabling, we need
5046          * to change the workaround. */
5047         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5048         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5049                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5050                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5051         }
5052 }
5053
5054 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5055 {
5056         struct drm_device *dev = crtc->base.dev;
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         int pipe = crtc->pipe;
5059
5060         /* To avoid upsetting the power well on haswell only disable the pfit if
5061          * it's in use. The hw state code will make sure we get this right. */
5062         if (force || crtc->config->pch_pfit.enabled) {
5063                 I915_WRITE(PF_CTL(pipe), 0);
5064                 I915_WRITE(PF_WIN_POS(pipe), 0);
5065                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5066         }
5067 }
5068
5069 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5070 {
5071         struct drm_device *dev = crtc->dev;
5072         struct drm_i915_private *dev_priv = dev->dev_private;
5073         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074         struct intel_encoder *encoder;
5075         int pipe = intel_crtc->pipe;
5076         u32 reg, temp;
5077
5078         for_each_encoder_on_crtc(dev, crtc, encoder)
5079                 encoder->disable(encoder);
5080
5081         drm_crtc_vblank_off(crtc);
5082         assert_vblank_disabled(crtc);
5083
5084         if (intel_crtc->config->has_pch_encoder)
5085                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5086
5087         intel_disable_pipe(intel_crtc);
5088
5089         ironlake_pfit_disable(intel_crtc, false);
5090
5091         if (intel_crtc->config->has_pch_encoder)
5092                 ironlake_fdi_disable(crtc);
5093
5094         for_each_encoder_on_crtc(dev, crtc, encoder)
5095                 if (encoder->post_disable)
5096                         encoder->post_disable(encoder);
5097
5098         if (intel_crtc->config->has_pch_encoder) {
5099                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5100
5101                 if (HAS_PCH_CPT(dev)) {
5102                         /* disable TRANS_DP_CTL */
5103                         reg = TRANS_DP_CTL(pipe);
5104                         temp = I915_READ(reg);
5105                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5106                                   TRANS_DP_PORT_SEL_MASK);
5107                         temp |= TRANS_DP_PORT_SEL_NONE;
5108                         I915_WRITE(reg, temp);
5109
5110                         /* disable DPLL_SEL */
5111                         temp = I915_READ(PCH_DPLL_SEL);
5112                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5113                         I915_WRITE(PCH_DPLL_SEL, temp);
5114                 }
5115
5116                 ironlake_fdi_pll_disable(intel_crtc);
5117         }
5118 }
5119
5120 static void haswell_crtc_disable(struct drm_crtc *crtc)
5121 {
5122         struct drm_device *dev = crtc->dev;
5123         struct drm_i915_private *dev_priv = dev->dev_private;
5124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5125         struct intel_encoder *encoder;
5126         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5127
5128         for_each_encoder_on_crtc(dev, crtc, encoder) {
5129                 intel_opregion_notify_encoder(encoder, false);
5130                 encoder->disable(encoder);
5131         }
5132
5133         drm_crtc_vblank_off(crtc);
5134         assert_vblank_disabled(crtc);
5135
5136         if (intel_crtc->config->has_pch_encoder)
5137                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5138                                                       false);
5139         intel_disable_pipe(intel_crtc);
5140
5141         if (intel_crtc->config->dp_encoder_is_mst)
5142                 intel_ddi_set_vc_payload_alloc(crtc, false);
5143
5144         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5145
5146         if (INTEL_INFO(dev)->gen >= 9)
5147                 skylake_scaler_disable(intel_crtc);
5148         else
5149                 ironlake_pfit_disable(intel_crtc, false);
5150
5151         intel_ddi_disable_pipe_clock(intel_crtc);
5152
5153         if (intel_crtc->config->has_pch_encoder) {
5154                 lpt_disable_pch_transcoder(dev_priv);
5155                 intel_ddi_fdi_disable(crtc);
5156         }
5157
5158         for_each_encoder_on_crtc(dev, crtc, encoder)
5159                 if (encoder->post_disable)
5160                         encoder->post_disable(encoder);
5161 }
5162
5163 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5164 {
5165         struct drm_device *dev = crtc->base.dev;
5166         struct drm_i915_private *dev_priv = dev->dev_private;
5167         struct intel_crtc_state *pipe_config = crtc->config;
5168
5169         if (!pipe_config->gmch_pfit.control)
5170                 return;
5171
5172         /*
5173          * The panel fitter should only be adjusted whilst the pipe is disabled,
5174          * according to register description and PRM.
5175          */
5176         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5177         assert_pipe_disabled(dev_priv, crtc->pipe);
5178
5179         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5180         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5181
5182         /* Border color in case we don't scale up to the full screen. Black by
5183          * default, change to something else for debugging. */
5184         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5185 }
5186
5187 static enum intel_display_power_domain port_to_power_domain(enum port port)
5188 {
5189         switch (port) {
5190         case PORT_A:
5191                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5192         case PORT_B:
5193                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5194         case PORT_C:
5195                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5196         case PORT_D:
5197                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5198         case PORT_E:
5199                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5200         default:
5201                 WARN_ON_ONCE(1);
5202                 return POWER_DOMAIN_PORT_OTHER;
5203         }
5204 }
5205
5206 #define for_each_power_domain(domain, mask)                             \
5207         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5208                 if ((1 << (domain)) & (mask))
5209
5210 enum intel_display_power_domain
5211 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5212 {
5213         struct drm_device *dev = intel_encoder->base.dev;
5214         struct intel_digital_port *intel_dig_port;
5215
5216         switch (intel_encoder->type) {
5217         case INTEL_OUTPUT_UNKNOWN:
5218                 /* Only DDI platforms should ever use this output type */
5219                 WARN_ON_ONCE(!HAS_DDI(dev));
5220         case INTEL_OUTPUT_DISPLAYPORT:
5221         case INTEL_OUTPUT_HDMI:
5222         case INTEL_OUTPUT_EDP:
5223                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5224                 return port_to_power_domain(intel_dig_port->port);
5225         case INTEL_OUTPUT_DP_MST:
5226                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5227                 return port_to_power_domain(intel_dig_port->port);
5228         case INTEL_OUTPUT_ANALOG:
5229                 return POWER_DOMAIN_PORT_CRT;
5230         case INTEL_OUTPUT_DSI:
5231                 return POWER_DOMAIN_PORT_DSI;
5232         default:
5233                 return POWER_DOMAIN_PORT_OTHER;
5234         }
5235 }
5236
5237 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5238 {
5239         struct drm_device *dev = crtc->dev;
5240         struct intel_encoder *intel_encoder;
5241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5242         enum pipe pipe = intel_crtc->pipe;
5243         unsigned long mask;
5244         enum transcoder transcoder;
5245
5246         if (!crtc->state->active)
5247                 return 0;
5248
5249         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5250
5251         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5252         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5253         if (intel_crtc->config->pch_pfit.enabled ||
5254             intel_crtc->config->pch_pfit.force_thru)
5255                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5256
5257         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5258                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5259
5260         return mask;
5261 }
5262
5263 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5264 {
5265         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5266         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5267         enum intel_display_power_domain domain;
5268         unsigned long domains, new_domains, old_domains;
5269
5270         old_domains = intel_crtc->enabled_power_domains;
5271         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5272
5273         domains = new_domains & ~old_domains;
5274
5275         for_each_power_domain(domain, domains)
5276                 intel_display_power_get(dev_priv, domain);
5277
5278         return old_domains & ~new_domains;
5279 }
5280
5281 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5282                                       unsigned long domains)
5283 {
5284         enum intel_display_power_domain domain;
5285
5286         for_each_power_domain(domain, domains)
5287                 intel_display_power_put(dev_priv, domain);
5288 }
5289
5290 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5291 {
5292         struct drm_device *dev = state->dev;
5293         struct drm_i915_private *dev_priv = dev->dev_private;
5294         unsigned long put_domains[I915_MAX_PIPES] = {};
5295         struct drm_crtc_state *crtc_state;
5296         struct drm_crtc *crtc;
5297         int i;
5298
5299         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5300                 if (needs_modeset(crtc->state))
5301                         put_domains[to_intel_crtc(crtc)->pipe] =
5302                                 modeset_get_crtc_power_domains(crtc);
5303         }
5304
5305         if (dev_priv->display.modeset_commit_cdclk) {
5306                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5307
5308                 if (cdclk != dev_priv->cdclk_freq &&
5309                     !WARN_ON(!state->allow_modeset))
5310                         dev_priv->display.modeset_commit_cdclk(state);
5311         }
5312
5313         for (i = 0; i < I915_MAX_PIPES; i++)
5314                 if (put_domains[i])
5315                         modeset_put_power_domains(dev_priv, put_domains[i]);
5316 }
5317
5318 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5319 {
5320         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5321
5322         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5323             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5324                 return max_cdclk_freq;
5325         else if (IS_CHERRYVIEW(dev_priv))
5326                 return max_cdclk_freq*95/100;
5327         else if (INTEL_INFO(dev_priv)->gen < 4)
5328                 return 2*max_cdclk_freq*90/100;
5329         else
5330                 return max_cdclk_freq*90/100;
5331 }
5332
5333 static void intel_update_max_cdclk(struct drm_device *dev)
5334 {
5335         struct drm_i915_private *dev_priv = dev->dev_private;
5336
5337         if (IS_SKYLAKE(dev)) {
5338                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5339
5340                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5341                         dev_priv->max_cdclk_freq = 675000;
5342                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5343                         dev_priv->max_cdclk_freq = 540000;
5344                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5345                         dev_priv->max_cdclk_freq = 450000;
5346                 else
5347                         dev_priv->max_cdclk_freq = 337500;
5348         } else if (IS_BROADWELL(dev))  {
5349                 /*
5350                  * FIXME with extra cooling we can allow
5351                  * 540 MHz for ULX and 675 Mhz for ULT.
5352                  * How can we know if extra cooling is
5353                  * available? PCI ID, VTB, something else?
5354                  */
5355                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5356                         dev_priv->max_cdclk_freq = 450000;
5357                 else if (IS_BDW_ULX(dev))
5358                         dev_priv->max_cdclk_freq = 450000;
5359                 else if (IS_BDW_ULT(dev))
5360                         dev_priv->max_cdclk_freq = 540000;
5361                 else
5362                         dev_priv->max_cdclk_freq = 675000;
5363         } else if (IS_CHERRYVIEW(dev)) {
5364                 dev_priv->max_cdclk_freq = 320000;
5365         } else if (IS_VALLEYVIEW(dev)) {
5366                 dev_priv->max_cdclk_freq = 400000;
5367         } else {
5368                 /* otherwise assume cdclk is fixed */
5369                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5370         }
5371
5372         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5373
5374         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5375                          dev_priv->max_cdclk_freq);
5376
5377         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5378                          dev_priv->max_dotclk_freq);
5379 }
5380
5381 static void intel_update_cdclk(struct drm_device *dev)
5382 {
5383         struct drm_i915_private *dev_priv = dev->dev_private;
5384
5385         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5386         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5387                          dev_priv->cdclk_freq);
5388
5389         /*
5390          * Program the gmbus_freq based on the cdclk frequency.
5391          * BSpec erroneously claims we should aim for 4MHz, but
5392          * in fact 1MHz is the correct frequency.
5393          */
5394         if (IS_VALLEYVIEW(dev)) {
5395                 /*
5396                  * Program the gmbus_freq based on the cdclk frequency.
5397                  * BSpec erroneously claims we should aim for 4MHz, but
5398                  * in fact 1MHz is the correct frequency.
5399                  */
5400                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5401         }
5402
5403         if (dev_priv->max_cdclk_freq == 0)
5404                 intel_update_max_cdclk(dev);
5405 }
5406
5407 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5408 {
5409         struct drm_i915_private *dev_priv = dev->dev_private;
5410         uint32_t divider;
5411         uint32_t ratio;
5412         uint32_t current_freq;
5413         int ret;
5414
5415         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5416         switch (frequency) {
5417         case 144000:
5418                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5419                 ratio = BXT_DE_PLL_RATIO(60);
5420                 break;
5421         case 288000:
5422                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5423                 ratio = BXT_DE_PLL_RATIO(60);
5424                 break;
5425         case 384000:
5426                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5427                 ratio = BXT_DE_PLL_RATIO(60);
5428                 break;
5429         case 576000:
5430                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5431                 ratio = BXT_DE_PLL_RATIO(60);
5432                 break;
5433         case 624000:
5434                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5435                 ratio = BXT_DE_PLL_RATIO(65);
5436                 break;
5437         case 19200:
5438                 /*
5439                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5440                  * to suppress GCC warning.
5441                  */
5442                 ratio = 0;
5443                 divider = 0;
5444                 break;
5445         default:
5446                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5447
5448                 return;
5449         }
5450
5451         mutex_lock(&dev_priv->rps.hw_lock);
5452         /* Inform power controller of upcoming frequency change */
5453         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5454                                       0x80000000);
5455         mutex_unlock(&dev_priv->rps.hw_lock);
5456
5457         if (ret) {
5458                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5459                           ret, frequency);
5460                 return;
5461         }
5462
5463         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5464         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5465         current_freq = current_freq * 500 + 1000;
5466
5467         /*
5468          * DE PLL has to be disabled when
5469          * - setting to 19.2MHz (bypass, PLL isn't used)
5470          * - before setting to 624MHz (PLL needs toggling)
5471          * - before setting to any frequency from 624MHz (PLL needs toggling)
5472          */
5473         if (frequency == 19200 || frequency == 624000 ||
5474             current_freq == 624000) {
5475                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5476                 /* Timeout 200us */
5477                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5478                              1))
5479                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5480         }
5481
5482         if (frequency != 19200) {
5483                 uint32_t val;
5484
5485                 val = I915_READ(BXT_DE_PLL_CTL);
5486                 val &= ~BXT_DE_PLL_RATIO_MASK;
5487                 val |= ratio;
5488                 I915_WRITE(BXT_DE_PLL_CTL, val);
5489
5490                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5491                 /* Timeout 200us */
5492                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5493                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5494
5495                 val = I915_READ(CDCLK_CTL);
5496                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5497                 val |= divider;
5498                 /*
5499                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5500                  * enable otherwise.
5501                  */
5502                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5503                 if (frequency >= 500000)
5504                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5505
5506                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5507                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5508                 val |= (frequency - 1000) / 500;
5509                 I915_WRITE(CDCLK_CTL, val);
5510         }
5511
5512         mutex_lock(&dev_priv->rps.hw_lock);
5513         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5514                                       DIV_ROUND_UP(frequency, 25000));
5515         mutex_unlock(&dev_priv->rps.hw_lock);
5516
5517         if (ret) {
5518                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5519                           ret, frequency);
5520                 return;
5521         }
5522
5523         intel_update_cdclk(dev);
5524 }
5525
5526 void broxton_init_cdclk(struct drm_device *dev)
5527 {
5528         struct drm_i915_private *dev_priv = dev->dev_private;
5529         uint32_t val;
5530
5531         /*
5532          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5533          * or else the reset will hang because there is no PCH to respond.
5534          * Move the handshake programming to initialization sequence.
5535          * Previously was left up to BIOS.
5536          */
5537         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5538         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5539         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5540
5541         /* Enable PG1 for cdclk */
5542         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5543
5544         /* check if cd clock is enabled */
5545         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5546                 DRM_DEBUG_KMS("Display already initialized\n");
5547                 return;
5548         }
5549
5550         /*
5551          * FIXME:
5552          * - The initial CDCLK needs to be read from VBT.
5553          *   Need to make this change after VBT has changes for BXT.
5554          * - check if setting the max (or any) cdclk freq is really necessary
5555          *   here, it belongs to modeset time
5556          */
5557         broxton_set_cdclk(dev, 624000);
5558
5559         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5560         POSTING_READ(DBUF_CTL);
5561
5562         udelay(10);
5563
5564         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5565                 DRM_ERROR("DBuf power enable timeout!\n");
5566 }
5567
5568 void broxton_uninit_cdclk(struct drm_device *dev)
5569 {
5570         struct drm_i915_private *dev_priv = dev->dev_private;
5571
5572         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5573         POSTING_READ(DBUF_CTL);
5574
5575         udelay(10);
5576
5577         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5578                 DRM_ERROR("DBuf power disable timeout!\n");
5579
5580         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5581         broxton_set_cdclk(dev, 19200);
5582
5583         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5584 }
5585
5586 static const struct skl_cdclk_entry {
5587         unsigned int freq;
5588         unsigned int vco;
5589 } skl_cdclk_frequencies[] = {
5590         { .freq = 308570, .vco = 8640 },
5591         { .freq = 337500, .vco = 8100 },
5592         { .freq = 432000, .vco = 8640 },
5593         { .freq = 450000, .vco = 8100 },
5594         { .freq = 540000, .vco = 8100 },
5595         { .freq = 617140, .vco = 8640 },
5596         { .freq = 675000, .vco = 8100 },
5597 };
5598
5599 static unsigned int skl_cdclk_decimal(unsigned int freq)
5600 {
5601         return (freq - 1000) / 500;
5602 }
5603
5604 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5605 {
5606         unsigned int i;
5607
5608         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5609                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5610
5611                 if (e->freq == freq)
5612                         return e->vco;
5613         }
5614
5615         return 8100;
5616 }
5617
5618 static void
5619 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5620 {
5621         unsigned int min_freq;
5622         u32 val;
5623
5624         /* select the minimum CDCLK before enabling DPLL 0 */
5625         val = I915_READ(CDCLK_CTL);
5626         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5627         val |= CDCLK_FREQ_337_308;
5628
5629         if (required_vco == 8640)
5630                 min_freq = 308570;
5631         else
5632                 min_freq = 337500;
5633
5634         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5635
5636         I915_WRITE(CDCLK_CTL, val);
5637         POSTING_READ(CDCLK_CTL);
5638
5639         /*
5640          * We always enable DPLL0 with the lowest link rate possible, but still
5641          * taking into account the VCO required to operate the eDP panel at the
5642          * desired frequency. The usual DP link rates operate with a VCO of
5643          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5644          * The modeset code is responsible for the selection of the exact link
5645          * rate later on, with the constraint of choosing a frequency that
5646          * works with required_vco.
5647          */
5648         val = I915_READ(DPLL_CTRL1);
5649
5650         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5651                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5652         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5653         if (required_vco == 8640)
5654                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5655                                             SKL_DPLL0);
5656         else
5657                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5658                                             SKL_DPLL0);
5659
5660         I915_WRITE(DPLL_CTRL1, val);
5661         POSTING_READ(DPLL_CTRL1);
5662
5663         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5664
5665         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5666                 DRM_ERROR("DPLL0 not locked\n");
5667 }
5668
5669 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5670 {
5671         int ret;
5672         u32 val;
5673
5674         /* inform PCU we want to change CDCLK */
5675         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5676         mutex_lock(&dev_priv->rps.hw_lock);
5677         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5678         mutex_unlock(&dev_priv->rps.hw_lock);
5679
5680         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5681 }
5682
5683 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5684 {
5685         unsigned int i;
5686
5687         for (i = 0; i < 15; i++) {
5688                 if (skl_cdclk_pcu_ready(dev_priv))
5689                         return true;
5690                 udelay(10);
5691         }
5692
5693         return false;
5694 }
5695
5696 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5697 {
5698         struct drm_device *dev = dev_priv->dev;
5699         u32 freq_select, pcu_ack;
5700
5701         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5702
5703         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5704                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5705                 return;
5706         }
5707
5708         /* set CDCLK_CTL */
5709         switch(freq) {
5710         case 450000:
5711         case 432000:
5712                 freq_select = CDCLK_FREQ_450_432;
5713                 pcu_ack = 1;
5714                 break;
5715         case 540000:
5716                 freq_select = CDCLK_FREQ_540;
5717                 pcu_ack = 2;
5718                 break;
5719         case 308570:
5720         case 337500:
5721         default:
5722                 freq_select = CDCLK_FREQ_337_308;
5723                 pcu_ack = 0;
5724                 break;
5725         case 617140:
5726         case 675000:
5727                 freq_select = CDCLK_FREQ_675_617;
5728                 pcu_ack = 3;
5729                 break;
5730         }
5731
5732         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5733         POSTING_READ(CDCLK_CTL);
5734
5735         /* inform PCU of the change */
5736         mutex_lock(&dev_priv->rps.hw_lock);
5737         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5738         mutex_unlock(&dev_priv->rps.hw_lock);
5739
5740         intel_update_cdclk(dev);
5741 }
5742
5743 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5744 {
5745         /* disable DBUF power */
5746         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5747         POSTING_READ(DBUF_CTL);
5748
5749         udelay(10);
5750
5751         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5752                 DRM_ERROR("DBuf power disable timeout\n");
5753
5754         /*
5755          * DMC assumes ownership of LCPLL and will get confused if we touch it.
5756          */
5757         if (dev_priv->csr.dmc_payload) {
5758                 /* disable DPLL0 */
5759                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5760                                         ~LCPLL_PLL_ENABLE);
5761                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5762                         DRM_ERROR("Couldn't disable DPLL0\n");
5763         }
5764
5765         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5766 }
5767
5768 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5769 {
5770         u32 val;
5771         unsigned int required_vco;
5772
5773         /* enable PCH reset handshake */
5774         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5775         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5776
5777         /* enable PG1 and Misc I/O */
5778         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5779
5780         /* DPLL0 not enabled (happens on early BIOS versions) */
5781         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5782                 /* enable DPLL0 */
5783                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5784                 skl_dpll0_enable(dev_priv, required_vco);
5785         }
5786
5787         /* set CDCLK to the frequency the BIOS chose */
5788         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5789
5790         /* enable DBUF power */
5791         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5792         POSTING_READ(DBUF_CTL);
5793
5794         udelay(10);
5795
5796         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5797                 DRM_ERROR("DBuf power enable timeout\n");
5798 }
5799
5800 /* Adjust CDclk dividers to allow high res or save power if possible */
5801 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5802 {
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         u32 val, cmd;
5805
5806         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807                                         != dev_priv->cdclk_freq);
5808
5809         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5810                 cmd = 2;
5811         else if (cdclk == 266667)
5812                 cmd = 1;
5813         else
5814                 cmd = 0;
5815
5816         mutex_lock(&dev_priv->rps.hw_lock);
5817         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5818         val &= ~DSPFREQGUAR_MASK;
5819         val |= (cmd << DSPFREQGUAR_SHIFT);
5820         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5821         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5822                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5823                      50)) {
5824                 DRM_ERROR("timed out waiting for CDclk change\n");
5825         }
5826         mutex_unlock(&dev_priv->rps.hw_lock);
5827
5828         mutex_lock(&dev_priv->sb_lock);
5829
5830         if (cdclk == 400000) {
5831                 u32 divider;
5832
5833                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5834
5835                 /* adjust cdclk divider */
5836                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5837                 val &= ~CCK_FREQUENCY_VALUES;
5838                 val |= divider;
5839                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5840
5841                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5842                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5843                              50))
5844                         DRM_ERROR("timed out waiting for CDclk change\n");
5845         }
5846
5847         /* adjust self-refresh exit latency value */
5848         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5849         val &= ~0x7f;
5850
5851         /*
5852          * For high bandwidth configs, we set a higher latency in the bunit
5853          * so that the core display fetch happens in time to avoid underruns.
5854          */
5855         if (cdclk == 400000)
5856                 val |= 4500 / 250; /* 4.5 usec */
5857         else
5858                 val |= 3000 / 250; /* 3.0 usec */
5859         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5860
5861         mutex_unlock(&dev_priv->sb_lock);
5862
5863         intel_update_cdclk(dev);
5864 }
5865
5866 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5867 {
5868         struct drm_i915_private *dev_priv = dev->dev_private;
5869         u32 val, cmd;
5870
5871         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5872                                                 != dev_priv->cdclk_freq);
5873
5874         switch (cdclk) {
5875         case 333333:
5876         case 320000:
5877         case 266667:
5878         case 200000:
5879                 break;
5880         default:
5881                 MISSING_CASE(cdclk);
5882                 return;
5883         }
5884
5885         /*
5886          * Specs are full of misinformation, but testing on actual
5887          * hardware has shown that we just need to write the desired
5888          * CCK divider into the Punit register.
5889          */
5890         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5891
5892         mutex_lock(&dev_priv->rps.hw_lock);
5893         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5894         val &= ~DSPFREQGUAR_MASK_CHV;
5895         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5896         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5897         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5898                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5899                      50)) {
5900                 DRM_ERROR("timed out waiting for CDclk change\n");
5901         }
5902         mutex_unlock(&dev_priv->rps.hw_lock);
5903
5904         intel_update_cdclk(dev);
5905 }
5906
5907 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5908                                  int max_pixclk)
5909 {
5910         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5911         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5912
5913         /*
5914          * Really only a few cases to deal with, as only 4 CDclks are supported:
5915          *   200MHz
5916          *   267MHz
5917          *   320/333MHz (depends on HPLL freq)
5918          *   400MHz (VLV only)
5919          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5920          * of the lower bin and adjust if needed.
5921          *
5922          * We seem to get an unstable or solid color picture at 200MHz.
5923          * Not sure what's wrong. For now use 200MHz only when all pipes
5924          * are off.
5925          */
5926         if (!IS_CHERRYVIEW(dev_priv) &&
5927             max_pixclk > freq_320*limit/100)
5928                 return 400000;
5929         else if (max_pixclk > 266667*limit/100)
5930                 return freq_320;
5931         else if (max_pixclk > 0)
5932                 return 266667;
5933         else
5934                 return 200000;
5935 }
5936
5937 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5938                               int max_pixclk)
5939 {
5940         /*
5941          * FIXME:
5942          * - remove the guardband, it's not needed on BXT
5943          * - set 19.2MHz bypass frequency if there are no active pipes
5944          */
5945         if (max_pixclk > 576000*9/10)
5946                 return 624000;
5947         else if (max_pixclk > 384000*9/10)
5948                 return 576000;
5949         else if (max_pixclk > 288000*9/10)
5950                 return 384000;
5951         else if (max_pixclk > 144000*9/10)
5952                 return 288000;
5953         else
5954                 return 144000;
5955 }
5956
5957 /* Compute the max pixel clock for new configuration. Uses atomic state if
5958  * that's non-NULL, look at current state otherwise. */
5959 static int intel_mode_max_pixclk(struct drm_device *dev,
5960                                  struct drm_atomic_state *state)
5961 {
5962         struct intel_crtc *intel_crtc;
5963         struct intel_crtc_state *crtc_state;
5964         int max_pixclk = 0;
5965
5966         for_each_intel_crtc(dev, intel_crtc) {
5967                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5968                 if (IS_ERR(crtc_state))
5969                         return PTR_ERR(crtc_state);
5970
5971                 if (!crtc_state->base.enable)
5972                         continue;
5973
5974                 max_pixclk = max(max_pixclk,
5975                                  crtc_state->base.adjusted_mode.crtc_clock);
5976         }
5977
5978         return max_pixclk;
5979 }
5980
5981 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5982 {
5983         struct drm_device *dev = state->dev;
5984         struct drm_i915_private *dev_priv = dev->dev_private;
5985         int max_pixclk = intel_mode_max_pixclk(dev, state);
5986
5987         if (max_pixclk < 0)
5988                 return max_pixclk;
5989
5990         to_intel_atomic_state(state)->cdclk =
5991                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5992
5993         return 0;
5994 }
5995
5996 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5997 {
5998         struct drm_device *dev = state->dev;
5999         struct drm_i915_private *dev_priv = dev->dev_private;
6000         int max_pixclk = intel_mode_max_pixclk(dev, state);
6001
6002         if (max_pixclk < 0)
6003                 return max_pixclk;
6004
6005         to_intel_atomic_state(state)->cdclk =
6006                 broxton_calc_cdclk(dev_priv, max_pixclk);
6007
6008         return 0;
6009 }
6010
6011 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6012 {
6013         unsigned int credits, default_credits;
6014
6015         if (IS_CHERRYVIEW(dev_priv))
6016                 default_credits = PFI_CREDIT(12);
6017         else
6018                 default_credits = PFI_CREDIT(8);
6019
6020         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6021                 /* CHV suggested value is 31 or 63 */
6022                 if (IS_CHERRYVIEW(dev_priv))
6023                         credits = PFI_CREDIT_63;
6024                 else
6025                         credits = PFI_CREDIT(15);
6026         } else {
6027                 credits = default_credits;
6028         }
6029
6030         /*
6031          * WA - write default credits before re-programming
6032          * FIXME: should we also set the resend bit here?
6033          */
6034         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6035                    default_credits);
6036
6037         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6038                    credits | PFI_CREDIT_RESEND);
6039
6040         /*
6041          * FIXME is this guaranteed to clear
6042          * immediately or should we poll for it?
6043          */
6044         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6045 }
6046
6047 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6048 {
6049         struct drm_device *dev = old_state->dev;
6050         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6051         struct drm_i915_private *dev_priv = dev->dev_private;
6052
6053         /*
6054          * FIXME: We can end up here with all power domains off, yet
6055          * with a CDCLK frequency other than the minimum. To account
6056          * for this take the PIPE-A power domain, which covers the HW
6057          * blocks needed for the following programming. This can be
6058          * removed once it's guaranteed that we get here either with
6059          * the minimum CDCLK set, or the required power domains
6060          * enabled.
6061          */
6062         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6063
6064         if (IS_CHERRYVIEW(dev))
6065                 cherryview_set_cdclk(dev, req_cdclk);
6066         else
6067                 valleyview_set_cdclk(dev, req_cdclk);
6068
6069         vlv_program_pfi_credits(dev_priv);
6070
6071         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6072 }
6073
6074 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6075 {
6076         struct drm_device *dev = crtc->dev;
6077         struct drm_i915_private *dev_priv = to_i915(dev);
6078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079         struct intel_encoder *encoder;
6080         int pipe = intel_crtc->pipe;
6081         bool is_dsi;
6082
6083         if (WARN_ON(intel_crtc->active))
6084                 return;
6085
6086         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6087
6088         if (intel_crtc->config->has_dp_encoder)
6089                 intel_dp_set_m_n(intel_crtc, M1_N1);
6090
6091         intel_set_pipe_timings(intel_crtc);
6092
6093         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6094                 struct drm_i915_private *dev_priv = dev->dev_private;
6095
6096                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6097                 I915_WRITE(CHV_CANVAS(pipe), 0);
6098         }
6099
6100         i9xx_set_pipeconf(intel_crtc);
6101
6102         intel_crtc->active = true;
6103
6104         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6105
6106         for_each_encoder_on_crtc(dev, crtc, encoder)
6107                 if (encoder->pre_pll_enable)
6108                         encoder->pre_pll_enable(encoder);
6109
6110         if (!is_dsi) {
6111                 if (IS_CHERRYVIEW(dev)) {
6112                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6113                         chv_enable_pll(intel_crtc, intel_crtc->config);
6114                 } else {
6115                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6116                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6117                 }
6118         }
6119
6120         for_each_encoder_on_crtc(dev, crtc, encoder)
6121                 if (encoder->pre_enable)
6122                         encoder->pre_enable(encoder);
6123
6124         i9xx_pfit_enable(intel_crtc);
6125
6126         intel_crtc_load_lut(crtc);
6127
6128         intel_enable_pipe(intel_crtc);
6129
6130         assert_vblank_disabled(crtc);
6131         drm_crtc_vblank_on(crtc);
6132
6133         for_each_encoder_on_crtc(dev, crtc, encoder)
6134                 encoder->enable(encoder);
6135 }
6136
6137 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6138 {
6139         struct drm_device *dev = crtc->base.dev;
6140         struct drm_i915_private *dev_priv = dev->dev_private;
6141
6142         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6143         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6144 }
6145
6146 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6147 {
6148         struct drm_device *dev = crtc->dev;
6149         struct drm_i915_private *dev_priv = to_i915(dev);
6150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151         struct intel_encoder *encoder;
6152         int pipe = intel_crtc->pipe;
6153
6154         if (WARN_ON(intel_crtc->active))
6155                 return;
6156
6157         i9xx_set_pll_dividers(intel_crtc);
6158
6159         if (intel_crtc->config->has_dp_encoder)
6160                 intel_dp_set_m_n(intel_crtc, M1_N1);
6161
6162         intel_set_pipe_timings(intel_crtc);
6163
6164         i9xx_set_pipeconf(intel_crtc);
6165
6166         intel_crtc->active = true;
6167
6168         if (!IS_GEN2(dev))
6169                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6170
6171         for_each_encoder_on_crtc(dev, crtc, encoder)
6172                 if (encoder->pre_enable)
6173                         encoder->pre_enable(encoder);
6174
6175         i9xx_enable_pll(intel_crtc);
6176
6177         i9xx_pfit_enable(intel_crtc);
6178
6179         intel_crtc_load_lut(crtc);
6180
6181         intel_update_watermarks(crtc);
6182         intel_enable_pipe(intel_crtc);
6183
6184         assert_vblank_disabled(crtc);
6185         drm_crtc_vblank_on(crtc);
6186
6187         for_each_encoder_on_crtc(dev, crtc, encoder)
6188                 encoder->enable(encoder);
6189 }
6190
6191 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6192 {
6193         struct drm_device *dev = crtc->base.dev;
6194         struct drm_i915_private *dev_priv = dev->dev_private;
6195
6196         if (!crtc->config->gmch_pfit.control)
6197                 return;
6198
6199         assert_pipe_disabled(dev_priv, crtc->pipe);
6200
6201         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6202                          I915_READ(PFIT_CONTROL));
6203         I915_WRITE(PFIT_CONTROL, 0);
6204 }
6205
6206 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6207 {
6208         struct drm_device *dev = crtc->dev;
6209         struct drm_i915_private *dev_priv = dev->dev_private;
6210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6211         struct intel_encoder *encoder;
6212         int pipe = intel_crtc->pipe;
6213
6214         /*
6215          * On gen2 planes are double buffered but the pipe isn't, so we must
6216          * wait for planes to fully turn off before disabling the pipe.
6217          * We also need to wait on all gmch platforms because of the
6218          * self-refresh mode constraint explained above.
6219          */
6220         intel_wait_for_vblank(dev, pipe);
6221
6222         for_each_encoder_on_crtc(dev, crtc, encoder)
6223                 encoder->disable(encoder);
6224
6225         drm_crtc_vblank_off(crtc);
6226         assert_vblank_disabled(crtc);
6227
6228         intel_disable_pipe(intel_crtc);
6229
6230         i9xx_pfit_disable(intel_crtc);
6231
6232         for_each_encoder_on_crtc(dev, crtc, encoder)
6233                 if (encoder->post_disable)
6234                         encoder->post_disable(encoder);
6235
6236         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6237                 if (IS_CHERRYVIEW(dev))
6238                         chv_disable_pll(dev_priv, pipe);
6239                 else if (IS_VALLEYVIEW(dev))
6240                         vlv_disable_pll(dev_priv, pipe);
6241                 else
6242                         i9xx_disable_pll(intel_crtc);
6243         }
6244
6245         for_each_encoder_on_crtc(dev, crtc, encoder)
6246                 if (encoder->post_pll_disable)
6247                         encoder->post_pll_disable(encoder);
6248
6249         if (!IS_GEN2(dev))
6250                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6251 }
6252
6253 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6254 {
6255         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6257         enum intel_display_power_domain domain;
6258         unsigned long domains;
6259
6260         if (!intel_crtc->active)
6261                 return;
6262
6263         if (to_intel_plane_state(crtc->primary->state)->visible) {
6264                 intel_crtc_wait_for_pending_flips(crtc);
6265                 intel_pre_disable_primary(crtc);
6266         }
6267
6268         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6269         dev_priv->display.crtc_disable(crtc);
6270         intel_crtc->active = false;
6271         intel_update_watermarks(crtc);
6272         intel_disable_shared_dpll(intel_crtc);
6273
6274         domains = intel_crtc->enabled_power_domains;
6275         for_each_power_domain(domain, domains)
6276                 intel_display_power_put(dev_priv, domain);
6277         intel_crtc->enabled_power_domains = 0;
6278 }
6279
6280 /*
6281  * turn all crtc's off, but do not adjust state
6282  * This has to be paired with a call to intel_modeset_setup_hw_state.
6283  */
6284 int intel_display_suspend(struct drm_device *dev)
6285 {
6286         struct drm_mode_config *config = &dev->mode_config;
6287         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6288         struct drm_atomic_state *state;
6289         struct drm_crtc *crtc;
6290         unsigned crtc_mask = 0;
6291         int ret = 0;
6292
6293         if (WARN_ON(!ctx))
6294                 return 0;
6295
6296         lockdep_assert_held(&ctx->ww_ctx);
6297         state = drm_atomic_state_alloc(dev);
6298         if (WARN_ON(!state))
6299                 return -ENOMEM;
6300
6301         state->acquire_ctx = ctx;
6302         state->allow_modeset = true;
6303
6304         for_each_crtc(dev, crtc) {
6305                 struct drm_crtc_state *crtc_state =
6306                         drm_atomic_get_crtc_state(state, crtc);
6307
6308                 ret = PTR_ERR_OR_ZERO(crtc_state);
6309                 if (ret)
6310                         goto free;
6311
6312                 if (!crtc_state->active)
6313                         continue;
6314
6315                 crtc_state->active = false;
6316                 crtc_mask |= 1 << drm_crtc_index(crtc);
6317         }
6318
6319         if (crtc_mask) {
6320                 ret = drm_atomic_commit(state);
6321
6322                 if (!ret) {
6323                         for_each_crtc(dev, crtc)
6324                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6325                                         crtc->state->active = true;
6326
6327                         return ret;
6328                 }
6329         }
6330
6331 free:
6332         if (ret)
6333                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6334         drm_atomic_state_free(state);
6335         return ret;
6336 }
6337
6338 void intel_encoder_destroy(struct drm_encoder *encoder)
6339 {
6340         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6341
6342         drm_encoder_cleanup(encoder);
6343         kfree(intel_encoder);
6344 }
6345
6346 /* Cross check the actual hw state with our own modeset state tracking (and it's
6347  * internal consistency). */
6348 static void intel_connector_check_state(struct intel_connector *connector)
6349 {
6350         struct drm_crtc *crtc = connector->base.state->crtc;
6351
6352         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6353                       connector->base.base.id,
6354                       connector->base.name);
6355
6356         if (connector->get_hw_state(connector)) {
6357                 struct intel_encoder *encoder = connector->encoder;
6358                 struct drm_connector_state *conn_state = connector->base.state;
6359
6360                 I915_STATE_WARN(!crtc,
6361                          "connector enabled without attached crtc\n");
6362
6363                 if (!crtc)
6364                         return;
6365
6366                 I915_STATE_WARN(!crtc->state->active,
6367                       "connector is active, but attached crtc isn't\n");
6368
6369                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6370                         return;
6371
6372                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6373                         "atomic encoder doesn't match attached encoder\n");
6374
6375                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6376                         "attached encoder crtc differs from connector crtc\n");
6377         } else {
6378                 I915_STATE_WARN(crtc && crtc->state->active,
6379                         "attached crtc is active, but connector isn't\n");
6380                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6381                         "best encoder set without crtc!\n");
6382         }
6383 }
6384
6385 int intel_connector_init(struct intel_connector *connector)
6386 {
6387         struct drm_connector_state *connector_state;
6388
6389         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6390         if (!connector_state)
6391                 return -ENOMEM;
6392
6393         connector->base.state = connector_state;
6394         return 0;
6395 }
6396
6397 struct intel_connector *intel_connector_alloc(void)
6398 {
6399         struct intel_connector *connector;
6400
6401         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6402         if (!connector)
6403                 return NULL;
6404
6405         if (intel_connector_init(connector) < 0) {
6406                 kfree(connector);
6407                 return NULL;
6408         }
6409
6410         return connector;
6411 }
6412
6413 /* Simple connector->get_hw_state implementation for encoders that support only
6414  * one connector and no cloning and hence the encoder state determines the state
6415  * of the connector. */
6416 bool intel_connector_get_hw_state(struct intel_connector *connector)
6417 {
6418         enum pipe pipe = 0;
6419         struct intel_encoder *encoder = connector->encoder;
6420
6421         return encoder->get_hw_state(encoder, &pipe);
6422 }
6423
6424 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6425 {
6426         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6427                 return crtc_state->fdi_lanes;
6428
6429         return 0;
6430 }
6431
6432 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6433                                      struct intel_crtc_state *pipe_config)
6434 {
6435         struct drm_atomic_state *state = pipe_config->base.state;
6436         struct intel_crtc *other_crtc;
6437         struct intel_crtc_state *other_crtc_state;
6438
6439         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6440                       pipe_name(pipe), pipe_config->fdi_lanes);
6441         if (pipe_config->fdi_lanes > 4) {
6442                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6443                               pipe_name(pipe), pipe_config->fdi_lanes);
6444                 return -EINVAL;
6445         }
6446
6447         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6448                 if (pipe_config->fdi_lanes > 2) {
6449                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6450                                       pipe_config->fdi_lanes);
6451                         return -EINVAL;
6452                 } else {
6453                         return 0;
6454                 }
6455         }
6456
6457         if (INTEL_INFO(dev)->num_pipes == 2)
6458                 return 0;
6459
6460         /* Ivybridge 3 pipe is really complicated */
6461         switch (pipe) {
6462         case PIPE_A:
6463                 return 0;
6464         case PIPE_B:
6465                 if (pipe_config->fdi_lanes <= 2)
6466                         return 0;
6467
6468                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6469                 other_crtc_state =
6470                         intel_atomic_get_crtc_state(state, other_crtc);
6471                 if (IS_ERR(other_crtc_state))
6472                         return PTR_ERR(other_crtc_state);
6473
6474                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6475                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6476                                       pipe_name(pipe), pipe_config->fdi_lanes);
6477                         return -EINVAL;
6478                 }
6479                 return 0;
6480         case PIPE_C:
6481                 if (pipe_config->fdi_lanes > 2) {
6482                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6483                                       pipe_name(pipe), pipe_config->fdi_lanes);
6484                         return -EINVAL;
6485                 }
6486
6487                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6488                 other_crtc_state =
6489                         intel_atomic_get_crtc_state(state, other_crtc);
6490                 if (IS_ERR(other_crtc_state))
6491                         return PTR_ERR(other_crtc_state);
6492
6493                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6494                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6495                         return -EINVAL;
6496                 }
6497                 return 0;
6498         default:
6499                 BUG();
6500         }
6501 }
6502
6503 #define RETRY 1
6504 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6505                                        struct intel_crtc_state *pipe_config)
6506 {
6507         struct drm_device *dev = intel_crtc->base.dev;
6508         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6509         int lane, link_bw, fdi_dotclock, ret;
6510         bool needs_recompute = false;
6511
6512 retry:
6513         /* FDI is a binary signal running at ~2.7GHz, encoding
6514          * each output octet as 10 bits. The actual frequency
6515          * is stored as a divider into a 100MHz clock, and the
6516          * mode pixel clock is stored in units of 1KHz.
6517          * Hence the bw of each lane in terms of the mode signal
6518          * is:
6519          */
6520         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6521
6522         fdi_dotclock = adjusted_mode->crtc_clock;
6523
6524         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6525                                            pipe_config->pipe_bpp);
6526
6527         pipe_config->fdi_lanes = lane;
6528
6529         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6530                                link_bw, &pipe_config->fdi_m_n);
6531
6532         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6533                                        intel_crtc->pipe, pipe_config);
6534         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6535                 pipe_config->pipe_bpp -= 2*3;
6536                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6537                               pipe_config->pipe_bpp);
6538                 needs_recompute = true;
6539                 pipe_config->bw_constrained = true;
6540
6541                 goto retry;
6542         }
6543
6544         if (needs_recompute)
6545                 return RETRY;
6546
6547         return ret;
6548 }
6549
6550 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6551                                      struct intel_crtc_state *pipe_config)
6552 {
6553         if (pipe_config->pipe_bpp > 24)
6554                 return false;
6555
6556         /* HSW can handle pixel rate up to cdclk? */
6557         if (IS_HASWELL(dev_priv->dev))
6558                 return true;
6559
6560         /*
6561          * We compare against max which means we must take
6562          * the increased cdclk requirement into account when
6563          * calculating the new cdclk.
6564          *
6565          * Should measure whether using a lower cdclk w/o IPS
6566          */
6567         return ilk_pipe_pixel_rate(pipe_config) <=
6568                 dev_priv->max_cdclk_freq * 95 / 100;
6569 }
6570
6571 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6572                                    struct intel_crtc_state *pipe_config)
6573 {
6574         struct drm_device *dev = crtc->base.dev;
6575         struct drm_i915_private *dev_priv = dev->dev_private;
6576
6577         pipe_config->ips_enabled = i915.enable_ips &&
6578                 hsw_crtc_supports_ips(crtc) &&
6579                 pipe_config_supports_ips(dev_priv, pipe_config);
6580 }
6581
6582 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6583                                      struct intel_crtc_state *pipe_config)
6584 {
6585         struct drm_device *dev = crtc->base.dev;
6586         struct drm_i915_private *dev_priv = dev->dev_private;
6587         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6588
6589         /* FIXME should check pixel clock limits on all platforms */
6590         if (INTEL_INFO(dev)->gen < 4) {
6591                 int clock_limit = dev_priv->max_cdclk_freq;
6592
6593                 /*
6594                  * Enable pixel doubling when the dot clock
6595                  * is > 90% of the (display) core speed.
6596                  *
6597                  * GDG double wide on either pipe,
6598                  * otherwise pipe A only.
6599                  */
6600                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6601                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6602                         clock_limit *= 2;
6603                         pipe_config->double_wide = true;
6604                 }
6605
6606                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6607                         return -EINVAL;
6608         }
6609
6610         /*
6611          * Pipe horizontal size must be even in:
6612          * - DVO ganged mode
6613          * - LVDS dual channel mode
6614          * - Double wide pipe
6615          */
6616         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6617              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6618                 pipe_config->pipe_src_w &= ~1;
6619
6620         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6621          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6622          */
6623         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6624                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6625                 return -EINVAL;
6626
6627         if (HAS_IPS(dev))
6628                 hsw_compute_ips_config(crtc, pipe_config);
6629
6630         if (pipe_config->has_pch_encoder)
6631                 return ironlake_fdi_compute_config(crtc, pipe_config);
6632
6633         return 0;
6634 }
6635
6636 static int skylake_get_display_clock_speed(struct drm_device *dev)
6637 {
6638         struct drm_i915_private *dev_priv = to_i915(dev);
6639         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6640         uint32_t cdctl = I915_READ(CDCLK_CTL);
6641         uint32_t linkrate;
6642
6643         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6644                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6645
6646         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6647                 return 540000;
6648
6649         linkrate = (I915_READ(DPLL_CTRL1) &
6650                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6651
6652         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6653             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6654                 /* vco 8640 */
6655                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6656                 case CDCLK_FREQ_450_432:
6657                         return 432000;
6658                 case CDCLK_FREQ_337_308:
6659                         return 308570;
6660                 case CDCLK_FREQ_675_617:
6661                         return 617140;
6662                 default:
6663                         WARN(1, "Unknown cd freq selection\n");
6664                 }
6665         } else {
6666                 /* vco 8100 */
6667                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6668                 case CDCLK_FREQ_450_432:
6669                         return 450000;
6670                 case CDCLK_FREQ_337_308:
6671                         return 337500;
6672                 case CDCLK_FREQ_675_617:
6673                         return 675000;
6674                 default:
6675                         WARN(1, "Unknown cd freq selection\n");
6676                 }
6677         }
6678
6679         /* error case, do as if DPLL0 isn't enabled */
6680         return 24000;
6681 }
6682
6683 static int broxton_get_display_clock_speed(struct drm_device *dev)
6684 {
6685         struct drm_i915_private *dev_priv = to_i915(dev);
6686         uint32_t cdctl = I915_READ(CDCLK_CTL);
6687         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6688         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6689         int cdclk;
6690
6691         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6692                 return 19200;
6693
6694         cdclk = 19200 * pll_ratio / 2;
6695
6696         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6697         case BXT_CDCLK_CD2X_DIV_SEL_1:
6698                 return cdclk;  /* 576MHz or 624MHz */
6699         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6700                 return cdclk * 2 / 3; /* 384MHz */
6701         case BXT_CDCLK_CD2X_DIV_SEL_2:
6702                 return cdclk / 2; /* 288MHz */
6703         case BXT_CDCLK_CD2X_DIV_SEL_4:
6704                 return cdclk / 4; /* 144MHz */
6705         }
6706
6707         /* error case, do as if DE PLL isn't enabled */
6708         return 19200;
6709 }
6710
6711 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6712 {
6713         struct drm_i915_private *dev_priv = dev->dev_private;
6714         uint32_t lcpll = I915_READ(LCPLL_CTL);
6715         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6716
6717         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6718                 return 800000;
6719         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6720                 return 450000;
6721         else if (freq == LCPLL_CLK_FREQ_450)
6722                 return 450000;
6723         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6724                 return 540000;
6725         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6726                 return 337500;
6727         else
6728                 return 675000;
6729 }
6730
6731 static int haswell_get_display_clock_speed(struct drm_device *dev)
6732 {
6733         struct drm_i915_private *dev_priv = dev->dev_private;
6734         uint32_t lcpll = I915_READ(LCPLL_CTL);
6735         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6736
6737         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6738                 return 800000;
6739         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6740                 return 450000;
6741         else if (freq == LCPLL_CLK_FREQ_450)
6742                 return 450000;
6743         else if (IS_HSW_ULT(dev))
6744                 return 337500;
6745         else
6746                 return 540000;
6747 }
6748
6749 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6750 {
6751         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6752                                       CCK_DISPLAY_CLOCK_CONTROL);
6753 }
6754
6755 static int ilk_get_display_clock_speed(struct drm_device *dev)
6756 {
6757         return 450000;
6758 }
6759
6760 static int i945_get_display_clock_speed(struct drm_device *dev)
6761 {
6762         return 400000;
6763 }
6764
6765 static int i915_get_display_clock_speed(struct drm_device *dev)
6766 {
6767         return 333333;
6768 }
6769
6770 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6771 {
6772         return 200000;
6773 }
6774
6775 static int pnv_get_display_clock_speed(struct drm_device *dev)
6776 {
6777         u16 gcfgc = 0;
6778
6779         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780
6781         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6782         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6783                 return 266667;
6784         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6785                 return 333333;
6786         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6787                 return 444444;
6788         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6789                 return 200000;
6790         default:
6791                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6792         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6793                 return 133333;
6794         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6795                 return 166667;
6796         }
6797 }
6798
6799 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6800 {
6801         u16 gcfgc = 0;
6802
6803         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6804
6805         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6806                 return 133333;
6807         else {
6808                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6809                 case GC_DISPLAY_CLOCK_333_MHZ:
6810                         return 333333;
6811                 default:
6812                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6813                         return 190000;
6814                 }
6815         }
6816 }
6817
6818 static int i865_get_display_clock_speed(struct drm_device *dev)
6819 {
6820         return 266667;
6821 }
6822
6823 static int i85x_get_display_clock_speed(struct drm_device *dev)
6824 {
6825         u16 hpllcc = 0;
6826
6827         /*
6828          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6829          * encoding is different :(
6830          * FIXME is this the right way to detect 852GM/852GMV?
6831          */
6832         if (dev->pdev->revision == 0x1)
6833                 return 133333;
6834
6835         pci_bus_read_config_word(dev->pdev->bus,
6836                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6837
6838         /* Assume that the hardware is in the high speed state.  This
6839          * should be the default.
6840          */
6841         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6842         case GC_CLOCK_133_200:
6843         case GC_CLOCK_133_200_2:
6844         case GC_CLOCK_100_200:
6845                 return 200000;
6846         case GC_CLOCK_166_250:
6847                 return 250000;
6848         case GC_CLOCK_100_133:
6849                 return 133333;
6850         case GC_CLOCK_133_266:
6851         case GC_CLOCK_133_266_2:
6852         case GC_CLOCK_166_266:
6853                 return 266667;
6854         }
6855
6856         /* Shouldn't happen */
6857         return 0;
6858 }
6859
6860 static int i830_get_display_clock_speed(struct drm_device *dev)
6861 {
6862         return 133333;
6863 }
6864
6865 static unsigned int intel_hpll_vco(struct drm_device *dev)
6866 {
6867         struct drm_i915_private *dev_priv = dev->dev_private;
6868         static const unsigned int blb_vco[8] = {
6869                 [0] = 3200000,
6870                 [1] = 4000000,
6871                 [2] = 5333333,
6872                 [3] = 4800000,
6873                 [4] = 6400000,
6874         };
6875         static const unsigned int pnv_vco[8] = {
6876                 [0] = 3200000,
6877                 [1] = 4000000,
6878                 [2] = 5333333,
6879                 [3] = 4800000,
6880                 [4] = 2666667,
6881         };
6882         static const unsigned int cl_vco[8] = {
6883                 [0] = 3200000,
6884                 [1] = 4000000,
6885                 [2] = 5333333,
6886                 [3] = 6400000,
6887                 [4] = 3333333,
6888                 [5] = 3566667,
6889                 [6] = 4266667,
6890         };
6891         static const unsigned int elk_vco[8] = {
6892                 [0] = 3200000,
6893                 [1] = 4000000,
6894                 [2] = 5333333,
6895                 [3] = 4800000,
6896         };
6897         static const unsigned int ctg_vco[8] = {
6898                 [0] = 3200000,
6899                 [1] = 4000000,
6900                 [2] = 5333333,
6901                 [3] = 6400000,
6902                 [4] = 2666667,
6903                 [5] = 4266667,
6904         };
6905         const unsigned int *vco_table;
6906         unsigned int vco;
6907         uint8_t tmp = 0;
6908
6909         /* FIXME other chipsets? */
6910         if (IS_GM45(dev))
6911                 vco_table = ctg_vco;
6912         else if (IS_G4X(dev))
6913                 vco_table = elk_vco;
6914         else if (IS_CRESTLINE(dev))
6915                 vco_table = cl_vco;
6916         else if (IS_PINEVIEW(dev))
6917                 vco_table = pnv_vco;
6918         else if (IS_G33(dev))
6919                 vco_table = blb_vco;
6920         else
6921                 return 0;
6922
6923         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6924
6925         vco = vco_table[tmp & 0x7];
6926         if (vco == 0)
6927                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6928         else
6929                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6930
6931         return vco;
6932 }
6933
6934 static int gm45_get_display_clock_speed(struct drm_device *dev)
6935 {
6936         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6937         uint16_t tmp = 0;
6938
6939         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6940
6941         cdclk_sel = (tmp >> 12) & 0x1;
6942
6943         switch (vco) {
6944         case 2666667:
6945         case 4000000:
6946         case 5333333:
6947                 return cdclk_sel ? 333333 : 222222;
6948         case 3200000:
6949                 return cdclk_sel ? 320000 : 228571;
6950         default:
6951                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6952                 return 222222;
6953         }
6954 }
6955
6956 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6957 {
6958         static const uint8_t div_3200[] = { 16, 10,  8 };
6959         static const uint8_t div_4000[] = { 20, 12, 10 };
6960         static const uint8_t div_5333[] = { 24, 16, 14 };
6961         const uint8_t *div_table;
6962         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6963         uint16_t tmp = 0;
6964
6965         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6966
6967         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6968
6969         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6970                 goto fail;
6971
6972         switch (vco) {
6973         case 3200000:
6974                 div_table = div_3200;
6975                 break;
6976         case 4000000:
6977                 div_table = div_4000;
6978                 break;
6979         case 5333333:
6980                 div_table = div_5333;
6981                 break;
6982         default:
6983                 goto fail;
6984         }
6985
6986         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6987
6988 fail:
6989         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6990         return 200000;
6991 }
6992
6993 static int g33_get_display_clock_speed(struct drm_device *dev)
6994 {
6995         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6996         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6997         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6998         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6999         const uint8_t *div_table;
7000         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7001         uint16_t tmp = 0;
7002
7003         pci_read_config_word(dev->pdev, GCFGC, &tmp);
7004
7005         cdclk_sel = (tmp >> 4) & 0x7;
7006
7007         if (cdclk_sel >= ARRAY_SIZE(div_3200))
7008                 goto fail;
7009
7010         switch (vco) {
7011         case 3200000:
7012                 div_table = div_3200;
7013                 break;
7014         case 4000000:
7015                 div_table = div_4000;
7016                 break;
7017         case 4800000:
7018                 div_table = div_4800;
7019                 break;
7020         case 5333333:
7021                 div_table = div_5333;
7022                 break;
7023         default:
7024                 goto fail;
7025         }
7026
7027         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7028
7029 fail:
7030         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7031         return 190476;
7032 }
7033
7034 static void
7035 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7036 {
7037         while (*num > DATA_LINK_M_N_MASK ||
7038                *den > DATA_LINK_M_N_MASK) {
7039                 *num >>= 1;
7040                 *den >>= 1;
7041         }
7042 }
7043
7044 static void compute_m_n(unsigned int m, unsigned int n,
7045                         uint32_t *ret_m, uint32_t *ret_n)
7046 {
7047         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7048         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7049         intel_reduce_m_n_ratio(ret_m, ret_n);
7050 }
7051
7052 void
7053 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7054                        int pixel_clock, int link_clock,
7055                        struct intel_link_m_n *m_n)
7056 {
7057         m_n->tu = 64;
7058
7059         compute_m_n(bits_per_pixel * pixel_clock,
7060                     link_clock * nlanes * 8,
7061                     &m_n->gmch_m, &m_n->gmch_n);
7062
7063         compute_m_n(pixel_clock, link_clock,
7064                     &m_n->link_m, &m_n->link_n);
7065 }
7066
7067 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7068 {
7069         if (i915.panel_use_ssc >= 0)
7070                 return i915.panel_use_ssc != 0;
7071         return dev_priv->vbt.lvds_use_ssc
7072                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7073 }
7074
7075 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7076                            int num_connectors)
7077 {
7078         struct drm_device *dev = crtc_state->base.crtc->dev;
7079         struct drm_i915_private *dev_priv = dev->dev_private;
7080         int refclk;
7081
7082         WARN_ON(!crtc_state->base.state);
7083
7084         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7085                 refclk = 100000;
7086         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7087             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7088                 refclk = dev_priv->vbt.lvds_ssc_freq;
7089                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7090         } else if (!IS_GEN2(dev)) {
7091                 refclk = 96000;
7092         } else {
7093                 refclk = 48000;
7094         }
7095
7096         return refclk;
7097 }
7098
7099 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7100 {
7101         return (1 << dpll->n) << 16 | dpll->m2;
7102 }
7103
7104 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7105 {
7106         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7107 }
7108
7109 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7110                                      struct intel_crtc_state *crtc_state,
7111                                      intel_clock_t *reduced_clock)
7112 {
7113         struct drm_device *dev = crtc->base.dev;
7114         u32 fp, fp2 = 0;
7115
7116         if (IS_PINEVIEW(dev)) {
7117                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7118                 if (reduced_clock)
7119                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7120         } else {
7121                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7122                 if (reduced_clock)
7123                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7124         }
7125
7126         crtc_state->dpll_hw_state.fp0 = fp;
7127
7128         crtc->lowfreq_avail = false;
7129         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7130             reduced_clock) {
7131                 crtc_state->dpll_hw_state.fp1 = fp2;
7132                 crtc->lowfreq_avail = true;
7133         } else {
7134                 crtc_state->dpll_hw_state.fp1 = fp;
7135         }
7136 }
7137
7138 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7139                 pipe)
7140 {
7141         u32 reg_val;
7142
7143         /*
7144          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7145          * and set it to a reasonable value instead.
7146          */
7147         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7148         reg_val &= 0xffffff00;
7149         reg_val |= 0x00000030;
7150         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7151
7152         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7153         reg_val &= 0x8cffffff;
7154         reg_val = 0x8c000000;
7155         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7156
7157         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7158         reg_val &= 0xffffff00;
7159         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7160
7161         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7162         reg_val &= 0x00ffffff;
7163         reg_val |= 0xb0000000;
7164         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7165 }
7166
7167 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7168                                          struct intel_link_m_n *m_n)
7169 {
7170         struct drm_device *dev = crtc->base.dev;
7171         struct drm_i915_private *dev_priv = dev->dev_private;
7172         int pipe = crtc->pipe;
7173
7174         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7176         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7177         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7178 }
7179
7180 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7181                                          struct intel_link_m_n *m_n,
7182                                          struct intel_link_m_n *m2_n2)
7183 {
7184         struct drm_device *dev = crtc->base.dev;
7185         struct drm_i915_private *dev_priv = dev->dev_private;
7186         int pipe = crtc->pipe;
7187         enum transcoder transcoder = crtc->config->cpu_transcoder;
7188
7189         if (INTEL_INFO(dev)->gen >= 5) {
7190                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7192                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7193                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7194                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7195                  * for gen < 8) and if DRRS is supported (to make sure the
7196                  * registers are not unnecessarily accessed).
7197                  */
7198                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7199                         crtc->config->has_drrs) {
7200                         I915_WRITE(PIPE_DATA_M2(transcoder),
7201                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7202                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7203                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7204                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7205                 }
7206         } else {
7207                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7208                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7209                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7210                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7211         }
7212 }
7213
7214 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7215 {
7216         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7217
7218         if (m_n == M1_N1) {
7219                 dp_m_n = &crtc->config->dp_m_n;
7220                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7221         } else if (m_n == M2_N2) {
7222
7223                 /*
7224                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7225                  * needs to be programmed into M1_N1.
7226                  */
7227                 dp_m_n = &crtc->config->dp_m2_n2;
7228         } else {
7229                 DRM_ERROR("Unsupported divider value\n");
7230                 return;
7231         }
7232
7233         if (crtc->config->has_pch_encoder)
7234                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7235         else
7236                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7237 }
7238
7239 static void vlv_compute_dpll(struct intel_crtc *crtc,
7240                              struct intel_crtc_state *pipe_config)
7241 {
7242         u32 dpll, dpll_md;
7243
7244         /*
7245          * Enable DPIO clock input. We should never disable the reference
7246          * clock for pipe B, since VGA hotplug / manual detection depends
7247          * on it.
7248          */
7249         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7250                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7251         /* We should never disable this, set it here for state tracking */
7252         if (crtc->pipe == PIPE_B)
7253                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7254         dpll |= DPLL_VCO_ENABLE;
7255         pipe_config->dpll_hw_state.dpll = dpll;
7256
7257         dpll_md = (pipe_config->pixel_multiplier - 1)
7258                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7259         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7260 }
7261
7262 static void vlv_prepare_pll(struct intel_crtc *crtc,
7263                             const struct intel_crtc_state *pipe_config)
7264 {
7265         struct drm_device *dev = crtc->base.dev;
7266         struct drm_i915_private *dev_priv = dev->dev_private;
7267         int pipe = crtc->pipe;
7268         u32 mdiv;
7269         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7270         u32 coreclk, reg_val;
7271
7272         mutex_lock(&dev_priv->sb_lock);
7273
7274         bestn = pipe_config->dpll.n;
7275         bestm1 = pipe_config->dpll.m1;
7276         bestm2 = pipe_config->dpll.m2;
7277         bestp1 = pipe_config->dpll.p1;
7278         bestp2 = pipe_config->dpll.p2;
7279
7280         /* See eDP HDMI DPIO driver vbios notes doc */
7281
7282         /* PLL B needs special handling */
7283         if (pipe == PIPE_B)
7284                 vlv_pllb_recal_opamp(dev_priv, pipe);
7285
7286         /* Set up Tx target for periodic Rcomp update */
7287         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7288
7289         /* Disable target IRef on PLL */
7290         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7291         reg_val &= 0x00ffffff;
7292         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7293
7294         /* Disable fast lock */
7295         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7296
7297         /* Set idtafcrecal before PLL is enabled */
7298         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7299         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7300         mdiv |= ((bestn << DPIO_N_SHIFT));
7301         mdiv |= (1 << DPIO_K_SHIFT);
7302
7303         /*
7304          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7305          * but we don't support that).
7306          * Note: don't use the DAC post divider as it seems unstable.
7307          */
7308         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7309         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7310
7311         mdiv |= DPIO_ENABLE_CALIBRATION;
7312         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7313
7314         /* Set HBR and RBR LPF coefficients */
7315         if (pipe_config->port_clock == 162000 ||
7316             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7317             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7318                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7319                                  0x009f0003);
7320         else
7321                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7322                                  0x00d0000f);
7323
7324         if (pipe_config->has_dp_encoder) {
7325                 /* Use SSC source */
7326                 if (pipe == PIPE_A)
7327                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7328                                          0x0df40000);
7329                 else
7330                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7331                                          0x0df70000);
7332         } else { /* HDMI or VGA */
7333                 /* Use bend source */
7334                 if (pipe == PIPE_A)
7335                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7336                                          0x0df70000);
7337                 else
7338                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7339                                          0x0df40000);
7340         }
7341
7342         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7343         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7344         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7345             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7346                 coreclk |= 0x01000000;
7347         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7348
7349         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7350         mutex_unlock(&dev_priv->sb_lock);
7351 }
7352
7353 static void chv_compute_dpll(struct intel_crtc *crtc,
7354                              struct intel_crtc_state *pipe_config)
7355 {
7356         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7357                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7358                 DPLL_VCO_ENABLE;
7359         if (crtc->pipe != PIPE_A)
7360                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7361
7362         pipe_config->dpll_hw_state.dpll_md =
7363                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7364 }
7365
7366 static void chv_prepare_pll(struct intel_crtc *crtc,
7367                             const struct intel_crtc_state *pipe_config)
7368 {
7369         struct drm_device *dev = crtc->base.dev;
7370         struct drm_i915_private *dev_priv = dev->dev_private;
7371         int pipe = crtc->pipe;
7372         int dpll_reg = DPLL(crtc->pipe);
7373         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7374         u32 loopfilter, tribuf_calcntr;
7375         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7376         u32 dpio_val;
7377         int vco;
7378
7379         bestn = pipe_config->dpll.n;
7380         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7381         bestm1 = pipe_config->dpll.m1;
7382         bestm2 = pipe_config->dpll.m2 >> 22;
7383         bestp1 = pipe_config->dpll.p1;
7384         bestp2 = pipe_config->dpll.p2;
7385         vco = pipe_config->dpll.vco;
7386         dpio_val = 0;
7387         loopfilter = 0;
7388
7389         /*
7390          * Enable Refclk and SSC
7391          */
7392         I915_WRITE(dpll_reg,
7393                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7394
7395         mutex_lock(&dev_priv->sb_lock);
7396
7397         /* p1 and p2 divider */
7398         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7399                         5 << DPIO_CHV_S1_DIV_SHIFT |
7400                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7401                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7402                         1 << DPIO_CHV_K_DIV_SHIFT);
7403
7404         /* Feedback post-divider - m2 */
7405         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7406
7407         /* Feedback refclk divider - n and m1 */
7408         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7409                         DPIO_CHV_M1_DIV_BY_2 |
7410                         1 << DPIO_CHV_N_DIV_SHIFT);
7411
7412         /* M2 fraction division */
7413         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7414
7415         /* M2 fraction division enable */
7416         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7417         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7418         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7419         if (bestm2_frac)
7420                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7421         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7422
7423         /* Program digital lock detect threshold */
7424         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7425         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7426                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7427         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7428         if (!bestm2_frac)
7429                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7430         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7431
7432         /* Loop filter */
7433         if (vco == 5400000) {
7434                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7435                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7436                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437                 tribuf_calcntr = 0x9;
7438         } else if (vco <= 6200000) {
7439                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7440                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7441                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7442                 tribuf_calcntr = 0x9;
7443         } else if (vco <= 6480000) {
7444                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7445                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7446                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7447                 tribuf_calcntr = 0x8;
7448         } else {
7449                 /* Not supported. Apply the same limits as in the max case */
7450                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7451                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7452                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7453                 tribuf_calcntr = 0;
7454         }
7455         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7456
7457         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7458         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7459         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7460         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7461
7462         /* AFC Recal */
7463         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7464                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7465                         DPIO_AFC_RECAL);
7466
7467         mutex_unlock(&dev_priv->sb_lock);
7468 }
7469
7470 /**
7471  * vlv_force_pll_on - forcibly enable just the PLL
7472  * @dev_priv: i915 private structure
7473  * @pipe: pipe PLL to enable
7474  * @dpll: PLL configuration
7475  *
7476  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7477  * in cases where we need the PLL enabled even when @pipe is not going to
7478  * be enabled.
7479  */
7480 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7481                       const struct dpll *dpll)
7482 {
7483         struct intel_crtc *crtc =
7484                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7485         struct intel_crtc_state pipe_config = {
7486                 .base.crtc = &crtc->base,
7487                 .pixel_multiplier = 1,
7488                 .dpll = *dpll,
7489         };
7490
7491         if (IS_CHERRYVIEW(dev)) {
7492                 chv_compute_dpll(crtc, &pipe_config);
7493                 chv_prepare_pll(crtc, &pipe_config);
7494                 chv_enable_pll(crtc, &pipe_config);
7495         } else {
7496                 vlv_compute_dpll(crtc, &pipe_config);
7497                 vlv_prepare_pll(crtc, &pipe_config);
7498                 vlv_enable_pll(crtc, &pipe_config);
7499         }
7500 }
7501
7502 /**
7503  * vlv_force_pll_off - forcibly disable just the PLL
7504  * @dev_priv: i915 private structure
7505  * @pipe: pipe PLL to disable
7506  *
7507  * Disable the PLL for @pipe. To be used in cases where we need
7508  * the PLL enabled even when @pipe is not going to be enabled.
7509  */
7510 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7511 {
7512         if (IS_CHERRYVIEW(dev))
7513                 chv_disable_pll(to_i915(dev), pipe);
7514         else
7515                 vlv_disable_pll(to_i915(dev), pipe);
7516 }
7517
7518 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7519                               struct intel_crtc_state *crtc_state,
7520                               intel_clock_t *reduced_clock,
7521                               int num_connectors)
7522 {
7523         struct drm_device *dev = crtc->base.dev;
7524         struct drm_i915_private *dev_priv = dev->dev_private;
7525         u32 dpll;
7526         bool is_sdvo;
7527         struct dpll *clock = &crtc_state->dpll;
7528
7529         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7530
7531         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7532                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7533
7534         dpll = DPLL_VGA_MODE_DIS;
7535
7536         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7537                 dpll |= DPLLB_MODE_LVDS;
7538         else
7539                 dpll |= DPLLB_MODE_DAC_SERIAL;
7540
7541         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7542                 dpll |= (crtc_state->pixel_multiplier - 1)
7543                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7544         }
7545
7546         if (is_sdvo)
7547                 dpll |= DPLL_SDVO_HIGH_SPEED;
7548
7549         if (crtc_state->has_dp_encoder)
7550                 dpll |= DPLL_SDVO_HIGH_SPEED;
7551
7552         /* compute bitmask from p1 value */
7553         if (IS_PINEVIEW(dev))
7554                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7555         else {
7556                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7557                 if (IS_G4X(dev) && reduced_clock)
7558                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7559         }
7560         switch (clock->p2) {
7561         case 5:
7562                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7563                 break;
7564         case 7:
7565                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7566                 break;
7567         case 10:
7568                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7569                 break;
7570         case 14:
7571                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7572                 break;
7573         }
7574         if (INTEL_INFO(dev)->gen >= 4)
7575                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7576
7577         if (crtc_state->sdvo_tv_clock)
7578                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7579         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7580                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7581                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7582         else
7583                 dpll |= PLL_REF_INPUT_DREFCLK;
7584
7585         dpll |= DPLL_VCO_ENABLE;
7586         crtc_state->dpll_hw_state.dpll = dpll;
7587
7588         if (INTEL_INFO(dev)->gen >= 4) {
7589                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7590                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7591                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7592         }
7593 }
7594
7595 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7596                               struct intel_crtc_state *crtc_state,
7597                               intel_clock_t *reduced_clock,
7598                               int num_connectors)
7599 {
7600         struct drm_device *dev = crtc->base.dev;
7601         struct drm_i915_private *dev_priv = dev->dev_private;
7602         u32 dpll;
7603         struct dpll *clock = &crtc_state->dpll;
7604
7605         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7606
7607         dpll = DPLL_VGA_MODE_DIS;
7608
7609         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7610                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611         } else {
7612                 if (clock->p1 == 2)
7613                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7614                 else
7615                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7616                 if (clock->p2 == 4)
7617                         dpll |= PLL_P2_DIVIDE_BY_4;
7618         }
7619
7620         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7621                 dpll |= DPLL_DVO_2X_MODE;
7622
7623         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7624                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7625                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7626         else
7627                 dpll |= PLL_REF_INPUT_DREFCLK;
7628
7629         dpll |= DPLL_VCO_ENABLE;
7630         crtc_state->dpll_hw_state.dpll = dpll;
7631 }
7632
7633 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7634 {
7635         struct drm_device *dev = intel_crtc->base.dev;
7636         struct drm_i915_private *dev_priv = dev->dev_private;
7637         enum pipe pipe = intel_crtc->pipe;
7638         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7639         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7640         uint32_t crtc_vtotal, crtc_vblank_end;
7641         int vsyncshift = 0;
7642
7643         /* We need to be careful not to changed the adjusted mode, for otherwise
7644          * the hw state checker will get angry at the mismatch. */
7645         crtc_vtotal = adjusted_mode->crtc_vtotal;
7646         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7647
7648         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7649                 /* the chip adds 2 halflines automatically */
7650                 crtc_vtotal -= 1;
7651                 crtc_vblank_end -= 1;
7652
7653                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7654                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7655                 else
7656                         vsyncshift = adjusted_mode->crtc_hsync_start -
7657                                 adjusted_mode->crtc_htotal / 2;
7658                 if (vsyncshift < 0)
7659                         vsyncshift += adjusted_mode->crtc_htotal;
7660         }
7661
7662         if (INTEL_INFO(dev)->gen > 3)
7663                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7664
7665         I915_WRITE(HTOTAL(cpu_transcoder),
7666                    (adjusted_mode->crtc_hdisplay - 1) |
7667                    ((adjusted_mode->crtc_htotal - 1) << 16));
7668         I915_WRITE(HBLANK(cpu_transcoder),
7669                    (adjusted_mode->crtc_hblank_start - 1) |
7670                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7671         I915_WRITE(HSYNC(cpu_transcoder),
7672                    (adjusted_mode->crtc_hsync_start - 1) |
7673                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7674
7675         I915_WRITE(VTOTAL(cpu_transcoder),
7676                    (adjusted_mode->crtc_vdisplay - 1) |
7677                    ((crtc_vtotal - 1) << 16));
7678         I915_WRITE(VBLANK(cpu_transcoder),
7679                    (adjusted_mode->crtc_vblank_start - 1) |
7680                    ((crtc_vblank_end - 1) << 16));
7681         I915_WRITE(VSYNC(cpu_transcoder),
7682                    (adjusted_mode->crtc_vsync_start - 1) |
7683                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7684
7685         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7686          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7687          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7688          * bits. */
7689         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7690             (pipe == PIPE_B || pipe == PIPE_C))
7691                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7692
7693         /* pipesrc controls the size that is scaled from, which should
7694          * always be the user's requested size.
7695          */
7696         I915_WRITE(PIPESRC(pipe),
7697                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7698                    (intel_crtc->config->pipe_src_h - 1));
7699 }
7700
7701 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7702                                    struct intel_crtc_state *pipe_config)
7703 {
7704         struct drm_device *dev = crtc->base.dev;
7705         struct drm_i915_private *dev_priv = dev->dev_private;
7706         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7707         uint32_t tmp;
7708
7709         tmp = I915_READ(HTOTAL(cpu_transcoder));
7710         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7711         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7712         tmp = I915_READ(HBLANK(cpu_transcoder));
7713         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7714         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7715         tmp = I915_READ(HSYNC(cpu_transcoder));
7716         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7717         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7718
7719         tmp = I915_READ(VTOTAL(cpu_transcoder));
7720         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7721         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7722         tmp = I915_READ(VBLANK(cpu_transcoder));
7723         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7724         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7725         tmp = I915_READ(VSYNC(cpu_transcoder));
7726         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7727         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7728
7729         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7730                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7731                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7732                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7733         }
7734
7735         tmp = I915_READ(PIPESRC(crtc->pipe));
7736         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7737         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7738
7739         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7740         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7741 }
7742
7743 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7744                                  struct intel_crtc_state *pipe_config)
7745 {
7746         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7747         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7748         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7749         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7750
7751         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7752         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7753         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7754         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7755
7756         mode->flags = pipe_config->base.adjusted_mode.flags;
7757         mode->type = DRM_MODE_TYPE_DRIVER;
7758
7759         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7760         mode->flags |= pipe_config->base.adjusted_mode.flags;
7761
7762         mode->hsync = drm_mode_hsync(mode);
7763         mode->vrefresh = drm_mode_vrefresh(mode);
7764         drm_mode_set_name(mode);
7765 }
7766
7767 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7768 {
7769         struct drm_device *dev = intel_crtc->base.dev;
7770         struct drm_i915_private *dev_priv = dev->dev_private;
7771         uint32_t pipeconf;
7772
7773         pipeconf = 0;
7774
7775         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7776             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7777                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7778
7779         if (intel_crtc->config->double_wide)
7780                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7781
7782         /* only g4x and later have fancy bpc/dither controls */
7783         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7784                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7785                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7786                         pipeconf |= PIPECONF_DITHER_EN |
7787                                     PIPECONF_DITHER_TYPE_SP;
7788
7789                 switch (intel_crtc->config->pipe_bpp) {
7790                 case 18:
7791                         pipeconf |= PIPECONF_6BPC;
7792                         break;
7793                 case 24:
7794                         pipeconf |= PIPECONF_8BPC;
7795                         break;
7796                 case 30:
7797                         pipeconf |= PIPECONF_10BPC;
7798                         break;
7799                 default:
7800                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7801                         BUG();
7802                 }
7803         }
7804
7805         if (HAS_PIPE_CXSR(dev)) {
7806                 if (intel_crtc->lowfreq_avail) {
7807                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7808                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7809                 } else {
7810                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7811                 }
7812         }
7813
7814         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7815                 if (INTEL_INFO(dev)->gen < 4 ||
7816                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7817                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7818                 else
7819                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7820         } else
7821                 pipeconf |= PIPECONF_PROGRESSIVE;
7822
7823         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7824                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7825
7826         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7827         POSTING_READ(PIPECONF(intel_crtc->pipe));
7828 }
7829
7830 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7831                                    struct intel_crtc_state *crtc_state)
7832 {
7833         struct drm_device *dev = crtc->base.dev;
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835         int refclk, num_connectors = 0;
7836         intel_clock_t clock;
7837         bool ok;
7838         bool is_dsi = false;
7839         struct intel_encoder *encoder;
7840         const intel_limit_t *limit;
7841         struct drm_atomic_state *state = crtc_state->base.state;
7842         struct drm_connector *connector;
7843         struct drm_connector_state *connector_state;
7844         int i;
7845
7846         memset(&crtc_state->dpll_hw_state, 0,
7847                sizeof(crtc_state->dpll_hw_state));
7848
7849         for_each_connector_in_state(state, connector, connector_state, i) {
7850                 if (connector_state->crtc != &crtc->base)
7851                         continue;
7852
7853                 encoder = to_intel_encoder(connector_state->best_encoder);
7854
7855                 switch (encoder->type) {
7856                 case INTEL_OUTPUT_DSI:
7857                         is_dsi = true;
7858                         break;
7859                 default:
7860                         break;
7861                 }
7862
7863                 num_connectors++;
7864         }
7865
7866         if (is_dsi)
7867                 return 0;
7868
7869         if (!crtc_state->clock_set) {
7870                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7871
7872                 /*
7873                  * Returns a set of divisors for the desired target clock with
7874                  * the given refclk, or FALSE.  The returned values represent
7875                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7876                  * 2) / p1 / p2.
7877                  */
7878                 limit = intel_limit(crtc_state, refclk);
7879                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7880                                                  crtc_state->port_clock,
7881                                                  refclk, NULL, &clock);
7882                 if (!ok) {
7883                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7884                         return -EINVAL;
7885                 }
7886
7887                 /* Compat-code for transition, will disappear. */
7888                 crtc_state->dpll.n = clock.n;
7889                 crtc_state->dpll.m1 = clock.m1;
7890                 crtc_state->dpll.m2 = clock.m2;
7891                 crtc_state->dpll.p1 = clock.p1;
7892                 crtc_state->dpll.p2 = clock.p2;
7893         }
7894
7895         if (IS_GEN2(dev)) {
7896                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7897                                   num_connectors);
7898         } else if (IS_CHERRYVIEW(dev)) {
7899                 chv_compute_dpll(crtc, crtc_state);
7900         } else if (IS_VALLEYVIEW(dev)) {
7901                 vlv_compute_dpll(crtc, crtc_state);
7902         } else {
7903                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7904                                   num_connectors);
7905         }
7906
7907         return 0;
7908 }
7909
7910 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7911                                  struct intel_crtc_state *pipe_config)
7912 {
7913         struct drm_device *dev = crtc->base.dev;
7914         struct drm_i915_private *dev_priv = dev->dev_private;
7915         uint32_t tmp;
7916
7917         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7918                 return;
7919
7920         tmp = I915_READ(PFIT_CONTROL);
7921         if (!(tmp & PFIT_ENABLE))
7922                 return;
7923
7924         /* Check whether the pfit is attached to our pipe. */
7925         if (INTEL_INFO(dev)->gen < 4) {
7926                 if (crtc->pipe != PIPE_B)
7927                         return;
7928         } else {
7929                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7930                         return;
7931         }
7932
7933         pipe_config->gmch_pfit.control = tmp;
7934         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7935         if (INTEL_INFO(dev)->gen < 5)
7936                 pipe_config->gmch_pfit.lvds_border_bits =
7937                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7938 }
7939
7940 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7941                                struct intel_crtc_state *pipe_config)
7942 {
7943         struct drm_device *dev = crtc->base.dev;
7944         struct drm_i915_private *dev_priv = dev->dev_private;
7945         int pipe = pipe_config->cpu_transcoder;
7946         intel_clock_t clock;
7947         u32 mdiv;
7948         int refclk = 100000;
7949
7950         /* In case of MIPI DPLL will not even be used */
7951         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7952                 return;
7953
7954         mutex_lock(&dev_priv->sb_lock);
7955         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7956         mutex_unlock(&dev_priv->sb_lock);
7957
7958         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7959         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7960         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7961         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7962         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7963
7964         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7965 }
7966
7967 static void
7968 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7969                               struct intel_initial_plane_config *plane_config)
7970 {
7971         struct drm_device *dev = crtc->base.dev;
7972         struct drm_i915_private *dev_priv = dev->dev_private;
7973         u32 val, base, offset;
7974         int pipe = crtc->pipe, plane = crtc->plane;
7975         int fourcc, pixel_format;
7976         unsigned int aligned_height;
7977         struct drm_framebuffer *fb;
7978         struct intel_framebuffer *intel_fb;
7979
7980         val = I915_READ(DSPCNTR(plane));
7981         if (!(val & DISPLAY_PLANE_ENABLE))
7982                 return;
7983
7984         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7985         if (!intel_fb) {
7986                 DRM_DEBUG_KMS("failed to alloc fb\n");
7987                 return;
7988         }
7989
7990         fb = &intel_fb->base;
7991
7992         if (INTEL_INFO(dev)->gen >= 4) {
7993                 if (val & DISPPLANE_TILED) {
7994                         plane_config->tiling = I915_TILING_X;
7995                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7996                 }
7997         }
7998
7999         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8000         fourcc = i9xx_format_to_fourcc(pixel_format);
8001         fb->pixel_format = fourcc;
8002         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8003
8004         if (INTEL_INFO(dev)->gen >= 4) {
8005                 if (plane_config->tiling)
8006                         offset = I915_READ(DSPTILEOFF(plane));
8007                 else
8008                         offset = I915_READ(DSPLINOFF(plane));
8009                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8010         } else {
8011                 base = I915_READ(DSPADDR(plane));
8012         }
8013         plane_config->base = base;
8014
8015         val = I915_READ(PIPESRC(pipe));
8016         fb->width = ((val >> 16) & 0xfff) + 1;
8017         fb->height = ((val >> 0) & 0xfff) + 1;
8018
8019         val = I915_READ(DSPSTRIDE(pipe));
8020         fb->pitches[0] = val & 0xffffffc0;
8021
8022         aligned_height = intel_fb_align_height(dev, fb->height,
8023                                                fb->pixel_format,
8024                                                fb->modifier[0]);
8025
8026         plane_config->size = fb->pitches[0] * aligned_height;
8027
8028         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8029                       pipe_name(pipe), plane, fb->width, fb->height,
8030                       fb->bits_per_pixel, base, fb->pitches[0],
8031                       plane_config->size);
8032
8033         plane_config->fb = intel_fb;
8034 }
8035
8036 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8037                                struct intel_crtc_state *pipe_config)
8038 {
8039         struct drm_device *dev = crtc->base.dev;
8040         struct drm_i915_private *dev_priv = dev->dev_private;
8041         int pipe = pipe_config->cpu_transcoder;
8042         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8043         intel_clock_t clock;
8044         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8045         int refclk = 100000;
8046
8047         mutex_lock(&dev_priv->sb_lock);
8048         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8049         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8050         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8051         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8052         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8053         mutex_unlock(&dev_priv->sb_lock);
8054
8055         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8056         clock.m2 = (pll_dw0 & 0xff) << 22;
8057         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8058                 clock.m2 |= pll_dw2 & 0x3fffff;
8059         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8060         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8061         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8062
8063         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8064 }
8065
8066 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8067                                  struct intel_crtc_state *pipe_config)
8068 {
8069         struct drm_device *dev = crtc->base.dev;
8070         struct drm_i915_private *dev_priv = dev->dev_private;
8071         uint32_t tmp;
8072
8073         if (!intel_display_power_is_enabled(dev_priv,
8074                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8075                 return false;
8076
8077         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8078         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8079
8080         tmp = I915_READ(PIPECONF(crtc->pipe));
8081         if (!(tmp & PIPECONF_ENABLE))
8082                 return false;
8083
8084         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8085                 switch (tmp & PIPECONF_BPC_MASK) {
8086                 case PIPECONF_6BPC:
8087                         pipe_config->pipe_bpp = 18;
8088                         break;
8089                 case PIPECONF_8BPC:
8090                         pipe_config->pipe_bpp = 24;
8091                         break;
8092                 case PIPECONF_10BPC:
8093                         pipe_config->pipe_bpp = 30;
8094                         break;
8095                 default:
8096                         break;
8097                 }
8098         }
8099
8100         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8101                 pipe_config->limited_color_range = true;
8102
8103         if (INTEL_INFO(dev)->gen < 4)
8104                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8105
8106         intel_get_pipe_timings(crtc, pipe_config);
8107
8108         i9xx_get_pfit_config(crtc, pipe_config);
8109
8110         if (INTEL_INFO(dev)->gen >= 4) {
8111                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8112                 pipe_config->pixel_multiplier =
8113                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8114                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8115                 pipe_config->dpll_hw_state.dpll_md = tmp;
8116         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8117                 tmp = I915_READ(DPLL(crtc->pipe));
8118                 pipe_config->pixel_multiplier =
8119                         ((tmp & SDVO_MULTIPLIER_MASK)
8120                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8121         } else {
8122                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8123                  * port and will be fixed up in the encoder->get_config
8124                  * function. */
8125                 pipe_config->pixel_multiplier = 1;
8126         }
8127         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8128         if (!IS_VALLEYVIEW(dev)) {
8129                 /*
8130                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8131                  * on 830. Filter it out here so that we don't
8132                  * report errors due to that.
8133                  */
8134                 if (IS_I830(dev))
8135                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8136
8137                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8138                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8139         } else {
8140                 /* Mask out read-only status bits. */
8141                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8142                                                      DPLL_PORTC_READY_MASK |
8143                                                      DPLL_PORTB_READY_MASK);
8144         }
8145
8146         if (IS_CHERRYVIEW(dev))
8147                 chv_crtc_clock_get(crtc, pipe_config);
8148         else if (IS_VALLEYVIEW(dev))
8149                 vlv_crtc_clock_get(crtc, pipe_config);
8150         else
8151                 i9xx_crtc_clock_get(crtc, pipe_config);
8152
8153         /*
8154          * Normally the dotclock is filled in by the encoder .get_config()
8155          * but in case the pipe is enabled w/o any ports we need a sane
8156          * default.
8157          */
8158         pipe_config->base.adjusted_mode.crtc_clock =
8159                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8160
8161         return true;
8162 }
8163
8164 static void ironlake_init_pch_refclk(struct drm_device *dev)
8165 {
8166         struct drm_i915_private *dev_priv = dev->dev_private;
8167         struct intel_encoder *encoder;
8168         u32 val, final;
8169         bool has_lvds = false;
8170         bool has_cpu_edp = false;
8171         bool has_panel = false;
8172         bool has_ck505 = false;
8173         bool can_ssc = false;
8174
8175         /* We need to take the global config into account */
8176         for_each_intel_encoder(dev, encoder) {
8177                 switch (encoder->type) {
8178                 case INTEL_OUTPUT_LVDS:
8179                         has_panel = true;
8180                         has_lvds = true;
8181                         break;
8182                 case INTEL_OUTPUT_EDP:
8183                         has_panel = true;
8184                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8185                                 has_cpu_edp = true;
8186                         break;
8187                 default:
8188                         break;
8189                 }
8190         }
8191
8192         if (HAS_PCH_IBX(dev)) {
8193                 has_ck505 = dev_priv->vbt.display_clock_mode;
8194                 can_ssc = has_ck505;
8195         } else {
8196                 has_ck505 = false;
8197                 can_ssc = true;
8198         }
8199
8200         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8201                       has_panel, has_lvds, has_ck505);
8202
8203         /* Ironlake: try to setup display ref clock before DPLL
8204          * enabling. This is only under driver's control after
8205          * PCH B stepping, previous chipset stepping should be
8206          * ignoring this setting.
8207          */
8208         val = I915_READ(PCH_DREF_CONTROL);
8209
8210         /* As we must carefully and slowly disable/enable each source in turn,
8211          * compute the final state we want first and check if we need to
8212          * make any changes at all.
8213          */
8214         final = val;
8215         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8216         if (has_ck505)
8217                 final |= DREF_NONSPREAD_CK505_ENABLE;
8218         else
8219                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8220
8221         final &= ~DREF_SSC_SOURCE_MASK;
8222         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8223         final &= ~DREF_SSC1_ENABLE;
8224
8225         if (has_panel) {
8226                 final |= DREF_SSC_SOURCE_ENABLE;
8227
8228                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8229                         final |= DREF_SSC1_ENABLE;
8230
8231                 if (has_cpu_edp) {
8232                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8233                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8234                         else
8235                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8236                 } else
8237                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8238         } else {
8239                 final |= DREF_SSC_SOURCE_DISABLE;
8240                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8241         }
8242
8243         if (final == val)
8244                 return;
8245
8246         /* Always enable nonspread source */
8247         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8248
8249         if (has_ck505)
8250                 val |= DREF_NONSPREAD_CK505_ENABLE;
8251         else
8252                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8253
8254         if (has_panel) {
8255                 val &= ~DREF_SSC_SOURCE_MASK;
8256                 val |= DREF_SSC_SOURCE_ENABLE;
8257
8258                 /* SSC must be turned on before enabling the CPU output  */
8259                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8260                         DRM_DEBUG_KMS("Using SSC on panel\n");
8261                         val |= DREF_SSC1_ENABLE;
8262                 } else
8263                         val &= ~DREF_SSC1_ENABLE;
8264
8265                 /* Get SSC going before enabling the outputs */
8266                 I915_WRITE(PCH_DREF_CONTROL, val);
8267                 POSTING_READ(PCH_DREF_CONTROL);
8268                 udelay(200);
8269
8270                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8271
8272                 /* Enable CPU source on CPU attached eDP */
8273                 if (has_cpu_edp) {
8274                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8275                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8276                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8277                         } else
8278                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8279                 } else
8280                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8281
8282                 I915_WRITE(PCH_DREF_CONTROL, val);
8283                 POSTING_READ(PCH_DREF_CONTROL);
8284                 udelay(200);
8285         } else {
8286                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8287
8288                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8289
8290                 /* Turn off CPU output */
8291                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8292
8293                 I915_WRITE(PCH_DREF_CONTROL, val);
8294                 POSTING_READ(PCH_DREF_CONTROL);
8295                 udelay(200);
8296
8297                 /* Turn off the SSC source */
8298                 val &= ~DREF_SSC_SOURCE_MASK;
8299                 val |= DREF_SSC_SOURCE_DISABLE;
8300
8301                 /* Turn off SSC1 */
8302                 val &= ~DREF_SSC1_ENABLE;
8303
8304                 I915_WRITE(PCH_DREF_CONTROL, val);
8305                 POSTING_READ(PCH_DREF_CONTROL);
8306                 udelay(200);
8307         }
8308
8309         BUG_ON(val != final);
8310 }
8311
8312 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8313 {
8314         uint32_t tmp;
8315
8316         tmp = I915_READ(SOUTH_CHICKEN2);
8317         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8318         I915_WRITE(SOUTH_CHICKEN2, tmp);
8319
8320         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8321                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8322                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8323
8324         tmp = I915_READ(SOUTH_CHICKEN2);
8325         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8326         I915_WRITE(SOUTH_CHICKEN2, tmp);
8327
8328         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8329                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8330                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8331 }
8332
8333 /* WaMPhyProgramming:hsw */
8334 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8335 {
8336         uint32_t tmp;
8337
8338         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8339         tmp &= ~(0xFF << 24);
8340         tmp |= (0x12 << 24);
8341         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8342
8343         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8344         tmp |= (1 << 11);
8345         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8346
8347         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8348         tmp |= (1 << 11);
8349         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8350
8351         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8352         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8353         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8354
8355         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8356         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8357         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8358
8359         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8360         tmp &= ~(7 << 13);
8361         tmp |= (5 << 13);
8362         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8363
8364         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8365         tmp &= ~(7 << 13);
8366         tmp |= (5 << 13);
8367         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8368
8369         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8370         tmp &= ~0xFF;
8371         tmp |= 0x1C;
8372         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8373
8374         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8375         tmp &= ~0xFF;
8376         tmp |= 0x1C;
8377         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8378
8379         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8380         tmp &= ~(0xFF << 16);
8381         tmp |= (0x1C << 16);
8382         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8383
8384         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8385         tmp &= ~(0xFF << 16);
8386         tmp |= (0x1C << 16);
8387         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8388
8389         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8390         tmp |= (1 << 27);
8391         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8392
8393         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8394         tmp |= (1 << 27);
8395         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8396
8397         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8398         tmp &= ~(0xF << 28);
8399         tmp |= (4 << 28);
8400         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8401
8402         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8403         tmp &= ~(0xF << 28);
8404         tmp |= (4 << 28);
8405         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8406 }
8407
8408 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8409  * Programming" based on the parameters passed:
8410  * - Sequence to enable CLKOUT_DP
8411  * - Sequence to enable CLKOUT_DP without spread
8412  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8413  */
8414 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8415                                  bool with_fdi)
8416 {
8417         struct drm_i915_private *dev_priv = dev->dev_private;
8418         uint32_t reg, tmp;
8419
8420         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8421                 with_spread = true;
8422         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8423                 with_fdi = false;
8424
8425         mutex_lock(&dev_priv->sb_lock);
8426
8427         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8428         tmp &= ~SBI_SSCCTL_DISABLE;
8429         tmp |= SBI_SSCCTL_PATHALT;
8430         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8431
8432         udelay(24);
8433
8434         if (with_spread) {
8435                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8436                 tmp &= ~SBI_SSCCTL_PATHALT;
8437                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438
8439                 if (with_fdi) {
8440                         lpt_reset_fdi_mphy(dev_priv);
8441                         lpt_program_fdi_mphy(dev_priv);
8442                 }
8443         }
8444
8445         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8446         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8447         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8448         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8449
8450         mutex_unlock(&dev_priv->sb_lock);
8451 }
8452
8453 /* Sequence to disable CLKOUT_DP */
8454 static void lpt_disable_clkout_dp(struct drm_device *dev)
8455 {
8456         struct drm_i915_private *dev_priv = dev->dev_private;
8457         uint32_t reg, tmp;
8458
8459         mutex_lock(&dev_priv->sb_lock);
8460
8461         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8462         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8463         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8464         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8465
8466         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8467         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8468                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8469                         tmp |= SBI_SSCCTL_PATHALT;
8470                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8471                         udelay(32);
8472                 }
8473                 tmp |= SBI_SSCCTL_DISABLE;
8474                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8475         }
8476
8477         mutex_unlock(&dev_priv->sb_lock);
8478 }
8479
8480 static void lpt_init_pch_refclk(struct drm_device *dev)
8481 {
8482         struct intel_encoder *encoder;
8483         bool has_vga = false;
8484
8485         for_each_intel_encoder(dev, encoder) {
8486                 switch (encoder->type) {
8487                 case INTEL_OUTPUT_ANALOG:
8488                         has_vga = true;
8489                         break;
8490                 default:
8491                         break;
8492                 }
8493         }
8494
8495         if (has_vga)
8496                 lpt_enable_clkout_dp(dev, true, true);
8497         else
8498                 lpt_disable_clkout_dp(dev);
8499 }
8500
8501 /*
8502  * Initialize reference clocks when the driver loads
8503  */
8504 void intel_init_pch_refclk(struct drm_device *dev)
8505 {
8506         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8507                 ironlake_init_pch_refclk(dev);
8508         else if (HAS_PCH_LPT(dev))
8509                 lpt_init_pch_refclk(dev);
8510 }
8511
8512 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8513 {
8514         struct drm_device *dev = crtc_state->base.crtc->dev;
8515         struct drm_i915_private *dev_priv = dev->dev_private;
8516         struct drm_atomic_state *state = crtc_state->base.state;
8517         struct drm_connector *connector;
8518         struct drm_connector_state *connector_state;
8519         struct intel_encoder *encoder;
8520         int num_connectors = 0, i;
8521         bool is_lvds = false;
8522
8523         for_each_connector_in_state(state, connector, connector_state, i) {
8524                 if (connector_state->crtc != crtc_state->base.crtc)
8525                         continue;
8526
8527                 encoder = to_intel_encoder(connector_state->best_encoder);
8528
8529                 switch (encoder->type) {
8530                 case INTEL_OUTPUT_LVDS:
8531                         is_lvds = true;
8532                         break;
8533                 default:
8534                         break;
8535                 }
8536                 num_connectors++;
8537         }
8538
8539         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8540                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8541                               dev_priv->vbt.lvds_ssc_freq);
8542                 return dev_priv->vbt.lvds_ssc_freq;
8543         }
8544
8545         return 120000;
8546 }
8547
8548 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8549 {
8550         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8551         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8552         int pipe = intel_crtc->pipe;
8553         uint32_t val;
8554
8555         val = 0;
8556
8557         switch (intel_crtc->config->pipe_bpp) {
8558         case 18:
8559                 val |= PIPECONF_6BPC;
8560                 break;
8561         case 24:
8562                 val |= PIPECONF_8BPC;
8563                 break;
8564         case 30:
8565                 val |= PIPECONF_10BPC;
8566                 break;
8567         case 36:
8568                 val |= PIPECONF_12BPC;
8569                 break;
8570         default:
8571                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8572                 BUG();
8573         }
8574
8575         if (intel_crtc->config->dither)
8576                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8577
8578         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8579                 val |= PIPECONF_INTERLACED_ILK;
8580         else
8581                 val |= PIPECONF_PROGRESSIVE;
8582
8583         if (intel_crtc->config->limited_color_range)
8584                 val |= PIPECONF_COLOR_RANGE_SELECT;
8585
8586         I915_WRITE(PIPECONF(pipe), val);
8587         POSTING_READ(PIPECONF(pipe));
8588 }
8589
8590 /*
8591  * Set up the pipe CSC unit.
8592  *
8593  * Currently only full range RGB to limited range RGB conversion
8594  * is supported, but eventually this should handle various
8595  * RGB<->YCbCr scenarios as well.
8596  */
8597 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8598 {
8599         struct drm_device *dev = crtc->dev;
8600         struct drm_i915_private *dev_priv = dev->dev_private;
8601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8602         int pipe = intel_crtc->pipe;
8603         uint16_t coeff = 0x7800; /* 1.0 */
8604
8605         /*
8606          * TODO: Check what kind of values actually come out of the pipe
8607          * with these coeff/postoff values and adjust to get the best
8608          * accuracy. Perhaps we even need to take the bpc value into
8609          * consideration.
8610          */
8611
8612         if (intel_crtc->config->limited_color_range)
8613                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8614
8615         /*
8616          * GY/GU and RY/RU should be the other way around according
8617          * to BSpec, but reality doesn't agree. Just set them up in
8618          * a way that results in the correct picture.
8619          */
8620         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8621         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8622
8623         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8624         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8625
8626         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8627         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8628
8629         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8630         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8631         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8632
8633         if (INTEL_INFO(dev)->gen > 6) {
8634                 uint16_t postoff = 0;
8635
8636                 if (intel_crtc->config->limited_color_range)
8637                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8638
8639                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8640                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8641                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8642
8643                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8644         } else {
8645                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8646
8647                 if (intel_crtc->config->limited_color_range)
8648                         mode |= CSC_BLACK_SCREEN_OFFSET;
8649
8650                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8651         }
8652 }
8653
8654 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8655 {
8656         struct drm_device *dev = crtc->dev;
8657         struct drm_i915_private *dev_priv = dev->dev_private;
8658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8659         enum pipe pipe = intel_crtc->pipe;
8660         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8661         uint32_t val;
8662
8663         val = 0;
8664
8665         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8666                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8667
8668         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8669                 val |= PIPECONF_INTERLACED_ILK;
8670         else
8671                 val |= PIPECONF_PROGRESSIVE;
8672
8673         I915_WRITE(PIPECONF(cpu_transcoder), val);
8674         POSTING_READ(PIPECONF(cpu_transcoder));
8675
8676         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8677         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8678
8679         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8680                 val = 0;
8681
8682                 switch (intel_crtc->config->pipe_bpp) {
8683                 case 18:
8684                         val |= PIPEMISC_DITHER_6_BPC;
8685                         break;
8686                 case 24:
8687                         val |= PIPEMISC_DITHER_8_BPC;
8688                         break;
8689                 case 30:
8690                         val |= PIPEMISC_DITHER_10_BPC;
8691                         break;
8692                 case 36:
8693                         val |= PIPEMISC_DITHER_12_BPC;
8694                         break;
8695                 default:
8696                         /* Case prevented by pipe_config_set_bpp. */
8697                         BUG();
8698                 }
8699
8700                 if (intel_crtc->config->dither)
8701                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8702
8703                 I915_WRITE(PIPEMISC(pipe), val);
8704         }
8705 }
8706
8707 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8708                                     struct intel_crtc_state *crtc_state,
8709                                     intel_clock_t *clock,
8710                                     bool *has_reduced_clock,
8711                                     intel_clock_t *reduced_clock)
8712 {
8713         struct drm_device *dev = crtc->dev;
8714         struct drm_i915_private *dev_priv = dev->dev_private;
8715         int refclk;
8716         const intel_limit_t *limit;
8717         bool ret;
8718
8719         refclk = ironlake_get_refclk(crtc_state);
8720
8721         /*
8722          * Returns a set of divisors for the desired target clock with the given
8723          * refclk, or FALSE.  The returned values represent the clock equation:
8724          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8725          */
8726         limit = intel_limit(crtc_state, refclk);
8727         ret = dev_priv->display.find_dpll(limit, crtc_state,
8728                                           crtc_state->port_clock,
8729                                           refclk, NULL, clock);
8730         if (!ret)
8731                 return false;
8732
8733         return true;
8734 }
8735
8736 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8737 {
8738         /*
8739          * Account for spread spectrum to avoid
8740          * oversubscribing the link. Max center spread
8741          * is 2.5%; use 5% for safety's sake.
8742          */
8743         u32 bps = target_clock * bpp * 21 / 20;
8744         return DIV_ROUND_UP(bps, link_bw * 8);
8745 }
8746
8747 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8748 {
8749         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8750 }
8751
8752 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8753                                       struct intel_crtc_state *crtc_state,
8754                                       u32 *fp,
8755                                       intel_clock_t *reduced_clock, u32 *fp2)
8756 {
8757         struct drm_crtc *crtc = &intel_crtc->base;
8758         struct drm_device *dev = crtc->dev;
8759         struct drm_i915_private *dev_priv = dev->dev_private;
8760         struct drm_atomic_state *state = crtc_state->base.state;
8761         struct drm_connector *connector;
8762         struct drm_connector_state *connector_state;
8763         struct intel_encoder *encoder;
8764         uint32_t dpll;
8765         int factor, num_connectors = 0, i;
8766         bool is_lvds = false, is_sdvo = false;
8767
8768         for_each_connector_in_state(state, connector, connector_state, i) {
8769                 if (connector_state->crtc != crtc_state->base.crtc)
8770                         continue;
8771
8772                 encoder = to_intel_encoder(connector_state->best_encoder);
8773
8774                 switch (encoder->type) {
8775                 case INTEL_OUTPUT_LVDS:
8776                         is_lvds = true;
8777                         break;
8778                 case INTEL_OUTPUT_SDVO:
8779                 case INTEL_OUTPUT_HDMI:
8780                         is_sdvo = true;
8781                         break;
8782                 default:
8783                         break;
8784                 }
8785
8786                 num_connectors++;
8787         }
8788
8789         /* Enable autotuning of the PLL clock (if permissible) */
8790         factor = 21;
8791         if (is_lvds) {
8792                 if ((intel_panel_use_ssc(dev_priv) &&
8793                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8794                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8795                         factor = 25;
8796         } else if (crtc_state->sdvo_tv_clock)
8797                 factor = 20;
8798
8799         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8800                 *fp |= FP_CB_TUNE;
8801
8802         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8803                 *fp2 |= FP_CB_TUNE;
8804
8805         dpll = 0;
8806
8807         if (is_lvds)
8808                 dpll |= DPLLB_MODE_LVDS;
8809         else
8810                 dpll |= DPLLB_MODE_DAC_SERIAL;
8811
8812         dpll |= (crtc_state->pixel_multiplier - 1)
8813                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8814
8815         if (is_sdvo)
8816                 dpll |= DPLL_SDVO_HIGH_SPEED;
8817         if (crtc_state->has_dp_encoder)
8818                 dpll |= DPLL_SDVO_HIGH_SPEED;
8819
8820         /* compute bitmask from p1 value */
8821         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8822         /* also FPA1 */
8823         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8824
8825         switch (crtc_state->dpll.p2) {
8826         case 5:
8827                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8828                 break;
8829         case 7:
8830                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8831                 break;
8832         case 10:
8833                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8834                 break;
8835         case 14:
8836                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8837                 break;
8838         }
8839
8840         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8841                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8842         else
8843                 dpll |= PLL_REF_INPUT_DREFCLK;
8844
8845         return dpll | DPLL_VCO_ENABLE;
8846 }
8847
8848 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8849                                        struct intel_crtc_state *crtc_state)
8850 {
8851         struct drm_device *dev = crtc->base.dev;
8852         intel_clock_t clock, reduced_clock;
8853         u32 dpll = 0, fp = 0, fp2 = 0;
8854         bool ok, has_reduced_clock = false;
8855         bool is_lvds = false;
8856         struct intel_shared_dpll *pll;
8857
8858         memset(&crtc_state->dpll_hw_state, 0,
8859                sizeof(crtc_state->dpll_hw_state));
8860
8861         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8862
8863         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8864              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8865
8866         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8867                                      &has_reduced_clock, &reduced_clock);
8868         if (!ok && !crtc_state->clock_set) {
8869                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8870                 return -EINVAL;
8871         }
8872         /* Compat-code for transition, will disappear. */
8873         if (!crtc_state->clock_set) {
8874                 crtc_state->dpll.n = clock.n;
8875                 crtc_state->dpll.m1 = clock.m1;
8876                 crtc_state->dpll.m2 = clock.m2;
8877                 crtc_state->dpll.p1 = clock.p1;
8878                 crtc_state->dpll.p2 = clock.p2;
8879         }
8880
8881         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8882         if (crtc_state->has_pch_encoder) {
8883                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8884                 if (has_reduced_clock)
8885                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8886
8887                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8888                                              &fp, &reduced_clock,
8889                                              has_reduced_clock ? &fp2 : NULL);
8890
8891                 crtc_state->dpll_hw_state.dpll = dpll;
8892                 crtc_state->dpll_hw_state.fp0 = fp;
8893                 if (has_reduced_clock)
8894                         crtc_state->dpll_hw_state.fp1 = fp2;
8895                 else
8896                         crtc_state->dpll_hw_state.fp1 = fp;
8897
8898                 pll = intel_get_shared_dpll(crtc, crtc_state);
8899                 if (pll == NULL) {
8900                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8901                                          pipe_name(crtc->pipe));
8902                         return -EINVAL;
8903                 }
8904         }
8905
8906         if (is_lvds && has_reduced_clock)
8907                 crtc->lowfreq_avail = true;
8908         else
8909                 crtc->lowfreq_avail = false;
8910
8911         return 0;
8912 }
8913
8914 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8915                                          struct intel_link_m_n *m_n)
8916 {
8917         struct drm_device *dev = crtc->base.dev;
8918         struct drm_i915_private *dev_priv = dev->dev_private;
8919         enum pipe pipe = crtc->pipe;
8920
8921         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8922         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8923         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8924                 & ~TU_SIZE_MASK;
8925         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8926         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8927                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8928 }
8929
8930 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8931                                          enum transcoder transcoder,
8932                                          struct intel_link_m_n *m_n,
8933                                          struct intel_link_m_n *m2_n2)
8934 {
8935         struct drm_device *dev = crtc->base.dev;
8936         struct drm_i915_private *dev_priv = dev->dev_private;
8937         enum pipe pipe = crtc->pipe;
8938
8939         if (INTEL_INFO(dev)->gen >= 5) {
8940                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8941                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8942                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8943                         & ~TU_SIZE_MASK;
8944                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8945                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8946                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8947                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8948                  * gen < 8) and if DRRS is supported (to make sure the
8949                  * registers are not unnecessarily read).
8950                  */
8951                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8952                         crtc->config->has_drrs) {
8953                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8954                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8955                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8956                                         & ~TU_SIZE_MASK;
8957                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8958                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8959                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8960                 }
8961         } else {
8962                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8963                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8964                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8965                         & ~TU_SIZE_MASK;
8966                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8967                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8968                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8969         }
8970 }
8971
8972 void intel_dp_get_m_n(struct intel_crtc *crtc,
8973                       struct intel_crtc_state *pipe_config)
8974 {
8975         if (pipe_config->has_pch_encoder)
8976                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8977         else
8978                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8979                                              &pipe_config->dp_m_n,
8980                                              &pipe_config->dp_m2_n2);
8981 }
8982
8983 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8984                                         struct intel_crtc_state *pipe_config)
8985 {
8986         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8987                                      &pipe_config->fdi_m_n, NULL);
8988 }
8989
8990 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8991                                     struct intel_crtc_state *pipe_config)
8992 {
8993         struct drm_device *dev = crtc->base.dev;
8994         struct drm_i915_private *dev_priv = dev->dev_private;
8995         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8996         uint32_t ps_ctrl = 0;
8997         int id = -1;
8998         int i;
8999
9000         /* find scaler attached to this pipe */
9001         for (i = 0; i < crtc->num_scalers; i++) {
9002                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9003                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9004                         id = i;
9005                         pipe_config->pch_pfit.enabled = true;
9006                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9007                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9008                         break;
9009                 }
9010         }
9011
9012         scaler_state->scaler_id = id;
9013         if (id >= 0) {
9014                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9015         } else {
9016                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9017         }
9018 }
9019
9020 static void
9021 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9022                                  struct intel_initial_plane_config *plane_config)
9023 {
9024         struct drm_device *dev = crtc->base.dev;
9025         struct drm_i915_private *dev_priv = dev->dev_private;
9026         u32 val, base, offset, stride_mult, tiling;
9027         int pipe = crtc->pipe;
9028         int fourcc, pixel_format;
9029         unsigned int aligned_height;
9030         struct drm_framebuffer *fb;
9031         struct intel_framebuffer *intel_fb;
9032
9033         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9034         if (!intel_fb) {
9035                 DRM_DEBUG_KMS("failed to alloc fb\n");
9036                 return;
9037         }
9038
9039         fb = &intel_fb->base;
9040
9041         val = I915_READ(PLANE_CTL(pipe, 0));
9042         if (!(val & PLANE_CTL_ENABLE))
9043                 goto error;
9044
9045         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9046         fourcc = skl_format_to_fourcc(pixel_format,
9047                                       val & PLANE_CTL_ORDER_RGBX,
9048                                       val & PLANE_CTL_ALPHA_MASK);
9049         fb->pixel_format = fourcc;
9050         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9051
9052         tiling = val & PLANE_CTL_TILED_MASK;
9053         switch (tiling) {
9054         case PLANE_CTL_TILED_LINEAR:
9055                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9056                 break;
9057         case PLANE_CTL_TILED_X:
9058                 plane_config->tiling = I915_TILING_X;
9059                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9060                 break;
9061         case PLANE_CTL_TILED_Y:
9062                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9063                 break;
9064         case PLANE_CTL_TILED_YF:
9065                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9066                 break;
9067         default:
9068                 MISSING_CASE(tiling);
9069                 goto error;
9070         }
9071
9072         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9073         plane_config->base = base;
9074
9075         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9076
9077         val = I915_READ(PLANE_SIZE(pipe, 0));
9078         fb->height = ((val >> 16) & 0xfff) + 1;
9079         fb->width = ((val >> 0) & 0x1fff) + 1;
9080
9081         val = I915_READ(PLANE_STRIDE(pipe, 0));
9082         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9083                                                 fb->pixel_format);
9084         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9085
9086         aligned_height = intel_fb_align_height(dev, fb->height,
9087                                                fb->pixel_format,
9088                                                fb->modifier[0]);
9089
9090         plane_config->size = fb->pitches[0] * aligned_height;
9091
9092         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9093                       pipe_name(pipe), fb->width, fb->height,
9094                       fb->bits_per_pixel, base, fb->pitches[0],
9095                       plane_config->size);
9096
9097         plane_config->fb = intel_fb;
9098         return;
9099
9100 error:
9101         kfree(fb);
9102 }
9103
9104 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9105                                      struct intel_crtc_state *pipe_config)
9106 {
9107         struct drm_device *dev = crtc->base.dev;
9108         struct drm_i915_private *dev_priv = dev->dev_private;
9109         uint32_t tmp;
9110
9111         tmp = I915_READ(PF_CTL(crtc->pipe));
9112
9113         if (tmp & PF_ENABLE) {
9114                 pipe_config->pch_pfit.enabled = true;
9115                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9116                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9117
9118                 /* We currently do not free assignements of panel fitters on
9119                  * ivb/hsw (since we don't use the higher upscaling modes which
9120                  * differentiates them) so just WARN about this case for now. */
9121                 if (IS_GEN7(dev)) {
9122                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9123                                 PF_PIPE_SEL_IVB(crtc->pipe));
9124                 }
9125         }
9126 }
9127
9128 static void
9129 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9130                                   struct intel_initial_plane_config *plane_config)
9131 {
9132         struct drm_device *dev = crtc->base.dev;
9133         struct drm_i915_private *dev_priv = dev->dev_private;
9134         u32 val, base, offset;
9135         int pipe = crtc->pipe;
9136         int fourcc, pixel_format;
9137         unsigned int aligned_height;
9138         struct drm_framebuffer *fb;
9139         struct intel_framebuffer *intel_fb;
9140
9141         val = I915_READ(DSPCNTR(pipe));
9142         if (!(val & DISPLAY_PLANE_ENABLE))
9143                 return;
9144
9145         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9146         if (!intel_fb) {
9147                 DRM_DEBUG_KMS("failed to alloc fb\n");
9148                 return;
9149         }
9150
9151         fb = &intel_fb->base;
9152
9153         if (INTEL_INFO(dev)->gen >= 4) {
9154                 if (val & DISPPLANE_TILED) {
9155                         plane_config->tiling = I915_TILING_X;
9156                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9157                 }
9158         }
9159
9160         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9161         fourcc = i9xx_format_to_fourcc(pixel_format);
9162         fb->pixel_format = fourcc;
9163         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9164
9165         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9166         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9167                 offset = I915_READ(DSPOFFSET(pipe));
9168         } else {
9169                 if (plane_config->tiling)
9170                         offset = I915_READ(DSPTILEOFF(pipe));
9171                 else
9172                         offset = I915_READ(DSPLINOFF(pipe));
9173         }
9174         plane_config->base = base;
9175
9176         val = I915_READ(PIPESRC(pipe));
9177         fb->width = ((val >> 16) & 0xfff) + 1;
9178         fb->height = ((val >> 0) & 0xfff) + 1;
9179
9180         val = I915_READ(DSPSTRIDE(pipe));
9181         fb->pitches[0] = val & 0xffffffc0;
9182
9183         aligned_height = intel_fb_align_height(dev, fb->height,
9184                                                fb->pixel_format,
9185                                                fb->modifier[0]);
9186
9187         plane_config->size = fb->pitches[0] * aligned_height;
9188
9189         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9190                       pipe_name(pipe), fb->width, fb->height,
9191                       fb->bits_per_pixel, base, fb->pitches[0],
9192                       plane_config->size);
9193
9194         plane_config->fb = intel_fb;
9195 }
9196
9197 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9198                                      struct intel_crtc_state *pipe_config)
9199 {
9200         struct drm_device *dev = crtc->base.dev;
9201         struct drm_i915_private *dev_priv = dev->dev_private;
9202         uint32_t tmp;
9203
9204         if (!intel_display_power_is_enabled(dev_priv,
9205                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9206                 return false;
9207
9208         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9209         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9210
9211         tmp = I915_READ(PIPECONF(crtc->pipe));
9212         if (!(tmp & PIPECONF_ENABLE))
9213                 return false;
9214
9215         switch (tmp & PIPECONF_BPC_MASK) {
9216         case PIPECONF_6BPC:
9217                 pipe_config->pipe_bpp = 18;
9218                 break;
9219         case PIPECONF_8BPC:
9220                 pipe_config->pipe_bpp = 24;
9221                 break;
9222         case PIPECONF_10BPC:
9223                 pipe_config->pipe_bpp = 30;
9224                 break;
9225         case PIPECONF_12BPC:
9226                 pipe_config->pipe_bpp = 36;
9227                 break;
9228         default:
9229                 break;
9230         }
9231
9232         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9233                 pipe_config->limited_color_range = true;
9234
9235         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9236                 struct intel_shared_dpll *pll;
9237
9238                 pipe_config->has_pch_encoder = true;
9239
9240                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9241                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9242                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9243
9244                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9245
9246                 if (HAS_PCH_IBX(dev_priv->dev)) {
9247                         pipe_config->shared_dpll =
9248                                 (enum intel_dpll_id) crtc->pipe;
9249                 } else {
9250                         tmp = I915_READ(PCH_DPLL_SEL);
9251                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9252                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9253                         else
9254                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9255                 }
9256
9257                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9258
9259                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9260                                            &pipe_config->dpll_hw_state));
9261
9262                 tmp = pipe_config->dpll_hw_state.dpll;
9263                 pipe_config->pixel_multiplier =
9264                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9265                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9266
9267                 ironlake_pch_clock_get(crtc, pipe_config);
9268         } else {
9269                 pipe_config->pixel_multiplier = 1;
9270         }
9271
9272         intel_get_pipe_timings(crtc, pipe_config);
9273
9274         ironlake_get_pfit_config(crtc, pipe_config);
9275
9276         return true;
9277 }
9278
9279 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9280 {
9281         struct drm_device *dev = dev_priv->dev;
9282         struct intel_crtc *crtc;
9283
9284         for_each_intel_crtc(dev, crtc)
9285                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9286                      pipe_name(crtc->pipe));
9287
9288         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9289         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9290         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9291         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9292         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9293         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9294              "CPU PWM1 enabled\n");
9295         if (IS_HASWELL(dev))
9296                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9297                      "CPU PWM2 enabled\n");
9298         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9299              "PCH PWM1 enabled\n");
9300         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9301              "Utility pin enabled\n");
9302         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9303
9304         /*
9305          * In theory we can still leave IRQs enabled, as long as only the HPD
9306          * interrupts remain enabled. We used to check for that, but since it's
9307          * gen-specific and since we only disable LCPLL after we fully disable
9308          * the interrupts, the check below should be enough.
9309          */
9310         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9311 }
9312
9313 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9314 {
9315         struct drm_device *dev = dev_priv->dev;
9316
9317         if (IS_HASWELL(dev))
9318                 return I915_READ(D_COMP_HSW);
9319         else
9320                 return I915_READ(D_COMP_BDW);
9321 }
9322
9323 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9324 {
9325         struct drm_device *dev = dev_priv->dev;
9326
9327         if (IS_HASWELL(dev)) {
9328                 mutex_lock(&dev_priv->rps.hw_lock);
9329                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9330                                             val))
9331                         DRM_ERROR("Failed to write to D_COMP\n");
9332                 mutex_unlock(&dev_priv->rps.hw_lock);
9333         } else {
9334                 I915_WRITE(D_COMP_BDW, val);
9335                 POSTING_READ(D_COMP_BDW);
9336         }
9337 }
9338
9339 /*
9340  * This function implements pieces of two sequences from BSpec:
9341  * - Sequence for display software to disable LCPLL
9342  * - Sequence for display software to allow package C8+
9343  * The steps implemented here are just the steps that actually touch the LCPLL
9344  * register. Callers should take care of disabling all the display engine
9345  * functions, doing the mode unset, fixing interrupts, etc.
9346  */
9347 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9348                               bool switch_to_fclk, bool allow_power_down)
9349 {
9350         uint32_t val;
9351
9352         assert_can_disable_lcpll(dev_priv);
9353
9354         val = I915_READ(LCPLL_CTL);
9355
9356         if (switch_to_fclk) {
9357                 val |= LCPLL_CD_SOURCE_FCLK;
9358                 I915_WRITE(LCPLL_CTL, val);
9359
9360                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9361                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9362                         DRM_ERROR("Switching to FCLK failed\n");
9363
9364                 val = I915_READ(LCPLL_CTL);
9365         }
9366
9367         val |= LCPLL_PLL_DISABLE;
9368         I915_WRITE(LCPLL_CTL, val);
9369         POSTING_READ(LCPLL_CTL);
9370
9371         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9372                 DRM_ERROR("LCPLL still locked\n");
9373
9374         val = hsw_read_dcomp(dev_priv);
9375         val |= D_COMP_COMP_DISABLE;
9376         hsw_write_dcomp(dev_priv, val);
9377         ndelay(100);
9378
9379         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9380                      1))
9381                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9382
9383         if (allow_power_down) {
9384                 val = I915_READ(LCPLL_CTL);
9385                 val |= LCPLL_POWER_DOWN_ALLOW;
9386                 I915_WRITE(LCPLL_CTL, val);
9387                 POSTING_READ(LCPLL_CTL);
9388         }
9389 }
9390
9391 /*
9392  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9393  * source.
9394  */
9395 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9396 {
9397         uint32_t val;
9398
9399         val = I915_READ(LCPLL_CTL);
9400
9401         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9402                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9403                 return;
9404
9405         /*
9406          * Make sure we're not on PC8 state before disabling PC8, otherwise
9407          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9408          */
9409         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9410
9411         if (val & LCPLL_POWER_DOWN_ALLOW) {
9412                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9413                 I915_WRITE(LCPLL_CTL, val);
9414                 POSTING_READ(LCPLL_CTL);
9415         }
9416
9417         val = hsw_read_dcomp(dev_priv);
9418         val |= D_COMP_COMP_FORCE;
9419         val &= ~D_COMP_COMP_DISABLE;
9420         hsw_write_dcomp(dev_priv, val);
9421
9422         val = I915_READ(LCPLL_CTL);
9423         val &= ~LCPLL_PLL_DISABLE;
9424         I915_WRITE(LCPLL_CTL, val);
9425
9426         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9427                 DRM_ERROR("LCPLL not locked yet\n");
9428
9429         if (val & LCPLL_CD_SOURCE_FCLK) {
9430                 val = I915_READ(LCPLL_CTL);
9431                 val &= ~LCPLL_CD_SOURCE_FCLK;
9432                 I915_WRITE(LCPLL_CTL, val);
9433
9434                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9435                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9436                         DRM_ERROR("Switching back to LCPLL failed\n");
9437         }
9438
9439         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9440         intel_update_cdclk(dev_priv->dev);
9441 }
9442
9443 /*
9444  * Package states C8 and deeper are really deep PC states that can only be
9445  * reached when all the devices on the system allow it, so even if the graphics
9446  * device allows PC8+, it doesn't mean the system will actually get to these
9447  * states. Our driver only allows PC8+ when going into runtime PM.
9448  *
9449  * The requirements for PC8+ are that all the outputs are disabled, the power
9450  * well is disabled and most interrupts are disabled, and these are also
9451  * requirements for runtime PM. When these conditions are met, we manually do
9452  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9453  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9454  * hang the machine.
9455  *
9456  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9457  * the state of some registers, so when we come back from PC8+ we need to
9458  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9459  * need to take care of the registers kept by RC6. Notice that this happens even
9460  * if we don't put the device in PCI D3 state (which is what currently happens
9461  * because of the runtime PM support).
9462  *
9463  * For more, read "Display Sequences for Package C8" on the hardware
9464  * documentation.
9465  */
9466 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9467 {
9468         struct drm_device *dev = dev_priv->dev;
9469         uint32_t val;
9470
9471         DRM_DEBUG_KMS("Enabling package C8+\n");
9472
9473         if (HAS_PCH_LPT_LP(dev)) {
9474                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9475                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9476                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9477         }
9478
9479         lpt_disable_clkout_dp(dev);
9480         hsw_disable_lcpll(dev_priv, true, true);
9481 }
9482
9483 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9484 {
9485         struct drm_device *dev = dev_priv->dev;
9486         uint32_t val;
9487
9488         DRM_DEBUG_KMS("Disabling package C8+\n");
9489
9490         hsw_restore_lcpll(dev_priv);
9491         lpt_init_pch_refclk(dev);
9492
9493         if (HAS_PCH_LPT_LP(dev)) {
9494                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9495                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9496                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9497         }
9498
9499         intel_prepare_ddi(dev);
9500 }
9501
9502 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9503 {
9504         struct drm_device *dev = old_state->dev;
9505         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9506
9507         broxton_set_cdclk(dev, req_cdclk);
9508 }
9509
9510 /* compute the max rate for new configuration */
9511 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9512 {
9513         struct intel_crtc *intel_crtc;
9514         struct intel_crtc_state *crtc_state;
9515         int max_pixel_rate = 0;
9516
9517         for_each_intel_crtc(state->dev, intel_crtc) {
9518                 int pixel_rate;
9519
9520                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9521                 if (IS_ERR(crtc_state))
9522                         return PTR_ERR(crtc_state);
9523
9524                 if (!crtc_state->base.enable)
9525                         continue;
9526
9527                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9528
9529                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9530                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9531                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9532
9533                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9534         }
9535
9536         return max_pixel_rate;
9537 }
9538
9539 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9540 {
9541         struct drm_i915_private *dev_priv = dev->dev_private;
9542         uint32_t val, data;
9543         int ret;
9544
9545         if (WARN((I915_READ(LCPLL_CTL) &
9546                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9547                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9548                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9549                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9550                  "trying to change cdclk frequency with cdclk not enabled\n"))
9551                 return;
9552
9553         mutex_lock(&dev_priv->rps.hw_lock);
9554         ret = sandybridge_pcode_write(dev_priv,
9555                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9556         mutex_unlock(&dev_priv->rps.hw_lock);
9557         if (ret) {
9558                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9559                 return;
9560         }
9561
9562         val = I915_READ(LCPLL_CTL);
9563         val |= LCPLL_CD_SOURCE_FCLK;
9564         I915_WRITE(LCPLL_CTL, val);
9565
9566         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9567                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9568                 DRM_ERROR("Switching to FCLK failed\n");
9569
9570         val = I915_READ(LCPLL_CTL);
9571         val &= ~LCPLL_CLK_FREQ_MASK;
9572
9573         switch (cdclk) {
9574         case 450000:
9575                 val |= LCPLL_CLK_FREQ_450;
9576                 data = 0;
9577                 break;
9578         case 540000:
9579                 val |= LCPLL_CLK_FREQ_54O_BDW;
9580                 data = 1;
9581                 break;
9582         case 337500:
9583                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9584                 data = 2;
9585                 break;
9586         case 675000:
9587                 val |= LCPLL_CLK_FREQ_675_BDW;
9588                 data = 3;
9589                 break;
9590         default:
9591                 WARN(1, "invalid cdclk frequency\n");
9592                 return;
9593         }
9594
9595         I915_WRITE(LCPLL_CTL, val);
9596
9597         val = I915_READ(LCPLL_CTL);
9598         val &= ~LCPLL_CD_SOURCE_FCLK;
9599         I915_WRITE(LCPLL_CTL, val);
9600
9601         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9602                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9603                 DRM_ERROR("Switching back to LCPLL failed\n");
9604
9605         mutex_lock(&dev_priv->rps.hw_lock);
9606         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9607         mutex_unlock(&dev_priv->rps.hw_lock);
9608
9609         intel_update_cdclk(dev);
9610
9611         WARN(cdclk != dev_priv->cdclk_freq,
9612              "cdclk requested %d kHz but got %d kHz\n",
9613              cdclk, dev_priv->cdclk_freq);
9614 }
9615
9616 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9617 {
9618         struct drm_i915_private *dev_priv = to_i915(state->dev);
9619         int max_pixclk = ilk_max_pixel_rate(state);
9620         int cdclk;
9621
9622         /*
9623          * FIXME should also account for plane ratio
9624          * once 64bpp pixel formats are supported.
9625          */
9626         if (max_pixclk > 540000)
9627                 cdclk = 675000;
9628         else if (max_pixclk > 450000)
9629                 cdclk = 540000;
9630         else if (max_pixclk > 337500)
9631                 cdclk = 450000;
9632         else
9633                 cdclk = 337500;
9634
9635         /*
9636          * FIXME move the cdclk caclulation to
9637          * compute_config() so we can fail gracegully.
9638          */
9639         if (cdclk > dev_priv->max_cdclk_freq) {
9640                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9641                           cdclk, dev_priv->max_cdclk_freq);
9642                 cdclk = dev_priv->max_cdclk_freq;
9643         }
9644
9645         to_intel_atomic_state(state)->cdclk = cdclk;
9646
9647         return 0;
9648 }
9649
9650 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9651 {
9652         struct drm_device *dev = old_state->dev;
9653         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9654
9655         broadwell_set_cdclk(dev, req_cdclk);
9656 }
9657
9658 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9659                                       struct intel_crtc_state *crtc_state)
9660 {
9661         if (!intel_ddi_pll_select(crtc, crtc_state))
9662                 return -EINVAL;
9663
9664         crtc->lowfreq_avail = false;
9665
9666         return 0;
9667 }
9668
9669 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9670                                 enum port port,
9671                                 struct intel_crtc_state *pipe_config)
9672 {
9673         switch (port) {
9674         case PORT_A:
9675                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9676                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9677                 break;
9678         case PORT_B:
9679                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9680                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9681                 break;
9682         case PORT_C:
9683                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9684                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9685                 break;
9686         default:
9687                 DRM_ERROR("Incorrect port type\n");
9688         }
9689 }
9690
9691 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9692                                 enum port port,
9693                                 struct intel_crtc_state *pipe_config)
9694 {
9695         u32 temp, dpll_ctl1;
9696
9697         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9698         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9699
9700         switch (pipe_config->ddi_pll_sel) {
9701         case SKL_DPLL0:
9702                 /*
9703                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9704                  * of the shared DPLL framework and thus needs to be read out
9705                  * separately
9706                  */
9707                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9708                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9709                 break;
9710         case SKL_DPLL1:
9711                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9712                 break;
9713         case SKL_DPLL2:
9714                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9715                 break;
9716         case SKL_DPLL3:
9717                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9718                 break;
9719         }
9720 }
9721
9722 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9723                                 enum port port,
9724                                 struct intel_crtc_state *pipe_config)
9725 {
9726         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9727
9728         switch (pipe_config->ddi_pll_sel) {
9729         case PORT_CLK_SEL_WRPLL1:
9730                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9731                 break;
9732         case PORT_CLK_SEL_WRPLL2:
9733                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9734                 break;
9735         }
9736 }
9737
9738 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9739                                        struct intel_crtc_state *pipe_config)
9740 {
9741         struct drm_device *dev = crtc->base.dev;
9742         struct drm_i915_private *dev_priv = dev->dev_private;
9743         struct intel_shared_dpll *pll;
9744         enum port port;
9745         uint32_t tmp;
9746
9747         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9748
9749         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9750
9751         if (IS_SKYLAKE(dev))
9752                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9753         else if (IS_BROXTON(dev))
9754                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9755         else
9756                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9757
9758         if (pipe_config->shared_dpll >= 0) {
9759                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9760
9761                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9762                                            &pipe_config->dpll_hw_state));
9763         }
9764
9765         /*
9766          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9767          * DDI E. So just check whether this pipe is wired to DDI E and whether
9768          * the PCH transcoder is on.
9769          */
9770         if (INTEL_INFO(dev)->gen < 9 &&
9771             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9772                 pipe_config->has_pch_encoder = true;
9773
9774                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9775                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9776                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9777
9778                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9779         }
9780 }
9781
9782 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9783                                     struct intel_crtc_state *pipe_config)
9784 {
9785         struct drm_device *dev = crtc->base.dev;
9786         struct drm_i915_private *dev_priv = dev->dev_private;
9787         enum intel_display_power_domain pfit_domain;
9788         uint32_t tmp;
9789
9790         if (!intel_display_power_is_enabled(dev_priv,
9791                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9792                 return false;
9793
9794         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9795         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9796
9797         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9798         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9799                 enum pipe trans_edp_pipe;
9800                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9801                 default:
9802                         WARN(1, "unknown pipe linked to edp transcoder\n");
9803                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9804                 case TRANS_DDI_EDP_INPUT_A_ON:
9805                         trans_edp_pipe = PIPE_A;
9806                         break;
9807                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9808                         trans_edp_pipe = PIPE_B;
9809                         break;
9810                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9811                         trans_edp_pipe = PIPE_C;
9812                         break;
9813                 }
9814
9815                 if (trans_edp_pipe == crtc->pipe)
9816                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9817         }
9818
9819         if (!intel_display_power_is_enabled(dev_priv,
9820                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9821                 return false;
9822
9823         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9824         if (!(tmp & PIPECONF_ENABLE))
9825                 return false;
9826
9827         haswell_get_ddi_port_state(crtc, pipe_config);
9828
9829         intel_get_pipe_timings(crtc, pipe_config);
9830
9831         if (INTEL_INFO(dev)->gen >= 9) {
9832                 skl_init_scalers(dev, crtc, pipe_config);
9833         }
9834
9835         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9836
9837         if (INTEL_INFO(dev)->gen >= 9) {
9838                 pipe_config->scaler_state.scaler_id = -1;
9839                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9840         }
9841
9842         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9843                 if (INTEL_INFO(dev)->gen >= 9)
9844                         skylake_get_pfit_config(crtc, pipe_config);
9845                 else
9846                         ironlake_get_pfit_config(crtc, pipe_config);
9847         }
9848
9849         if (IS_HASWELL(dev))
9850                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9851                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9852
9853         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9854                 pipe_config->pixel_multiplier =
9855                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9856         } else {
9857                 pipe_config->pixel_multiplier = 1;
9858         }
9859
9860         return true;
9861 }
9862
9863 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9864 {
9865         struct drm_device *dev = crtc->dev;
9866         struct drm_i915_private *dev_priv = dev->dev_private;
9867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9868         uint32_t cntl = 0, size = 0;
9869
9870         if (base) {
9871                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9872                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9873                 unsigned int stride = roundup_pow_of_two(width) * 4;
9874
9875                 switch (stride) {
9876                 default:
9877                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9878                                   width, stride);
9879                         stride = 256;
9880                         /* fallthrough */
9881                 case 256:
9882                 case 512:
9883                 case 1024:
9884                 case 2048:
9885                         break;
9886                 }
9887
9888                 cntl |= CURSOR_ENABLE |
9889                         CURSOR_GAMMA_ENABLE |
9890                         CURSOR_FORMAT_ARGB |
9891                         CURSOR_STRIDE(stride);
9892
9893                 size = (height << 12) | width;
9894         }
9895
9896         if (intel_crtc->cursor_cntl != 0 &&
9897             (intel_crtc->cursor_base != base ||
9898              intel_crtc->cursor_size != size ||
9899              intel_crtc->cursor_cntl != cntl)) {
9900                 /* On these chipsets we can only modify the base/size/stride
9901                  * whilst the cursor is disabled.
9902                  */
9903                 I915_WRITE(CURCNTR(PIPE_A), 0);
9904                 POSTING_READ(CURCNTR(PIPE_A));
9905                 intel_crtc->cursor_cntl = 0;
9906         }
9907
9908         if (intel_crtc->cursor_base != base) {
9909                 I915_WRITE(CURBASE(PIPE_A), base);
9910                 intel_crtc->cursor_base = base;
9911         }
9912
9913         if (intel_crtc->cursor_size != size) {
9914                 I915_WRITE(CURSIZE, size);
9915                 intel_crtc->cursor_size = size;
9916         }
9917
9918         if (intel_crtc->cursor_cntl != cntl) {
9919                 I915_WRITE(CURCNTR(PIPE_A), cntl);
9920                 POSTING_READ(CURCNTR(PIPE_A));
9921                 intel_crtc->cursor_cntl = cntl;
9922         }
9923 }
9924
9925 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9926 {
9927         struct drm_device *dev = crtc->dev;
9928         struct drm_i915_private *dev_priv = dev->dev_private;
9929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9930         int pipe = intel_crtc->pipe;
9931         uint32_t cntl;
9932
9933         cntl = 0;
9934         if (base) {
9935                 cntl = MCURSOR_GAMMA_ENABLE;
9936                 switch (intel_crtc->base.cursor->state->crtc_w) {
9937                         case 64:
9938                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9939                                 break;
9940                         case 128:
9941                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9942                                 break;
9943                         case 256:
9944                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9945                                 break;
9946                         default:
9947                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9948                                 return;
9949                 }
9950                 cntl |= pipe << 28; /* Connect to correct pipe */
9951
9952                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9953                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9954         }
9955
9956         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9957                 cntl |= CURSOR_ROTATE_180;
9958
9959         if (intel_crtc->cursor_cntl != cntl) {
9960                 I915_WRITE(CURCNTR(pipe), cntl);
9961                 POSTING_READ(CURCNTR(pipe));
9962                 intel_crtc->cursor_cntl = cntl;
9963         }
9964
9965         /* and commit changes on next vblank */
9966         I915_WRITE(CURBASE(pipe), base);
9967         POSTING_READ(CURBASE(pipe));
9968
9969         intel_crtc->cursor_base = base;
9970 }
9971
9972 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9973 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9974                                      bool on)
9975 {
9976         struct drm_device *dev = crtc->dev;
9977         struct drm_i915_private *dev_priv = dev->dev_private;
9978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9979         int pipe = intel_crtc->pipe;
9980         struct drm_plane_state *cursor_state = crtc->cursor->state;
9981         int x = cursor_state->crtc_x;
9982         int y = cursor_state->crtc_y;
9983         u32 base = 0, pos = 0;
9984
9985         if (on)
9986                 base = intel_crtc->cursor_addr;
9987
9988         if (x >= intel_crtc->config->pipe_src_w)
9989                 base = 0;
9990
9991         if (y >= intel_crtc->config->pipe_src_h)
9992                 base = 0;
9993
9994         if (x < 0) {
9995                 if (x + cursor_state->crtc_w <= 0)
9996                         base = 0;
9997
9998                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9999                 x = -x;
10000         }
10001         pos |= x << CURSOR_X_SHIFT;
10002
10003         if (y < 0) {
10004                 if (y + cursor_state->crtc_h <= 0)
10005                         base = 0;
10006
10007                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10008                 y = -y;
10009         }
10010         pos |= y << CURSOR_Y_SHIFT;
10011
10012         if (base == 0 && intel_crtc->cursor_base == 0)
10013                 return;
10014
10015         I915_WRITE(CURPOS(pipe), pos);
10016
10017         /* ILK+ do this automagically */
10018         if (HAS_GMCH_DISPLAY(dev) &&
10019             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10020                 base += (cursor_state->crtc_h *
10021                          cursor_state->crtc_w - 1) * 4;
10022         }
10023
10024         if (IS_845G(dev) || IS_I865G(dev))
10025                 i845_update_cursor(crtc, base);
10026         else
10027                 i9xx_update_cursor(crtc, base);
10028 }
10029
10030 static bool cursor_size_ok(struct drm_device *dev,
10031                            uint32_t width, uint32_t height)
10032 {
10033         if (width == 0 || height == 0)
10034                 return false;
10035
10036         /*
10037          * 845g/865g are special in that they are only limited by
10038          * the width of their cursors, the height is arbitrary up to
10039          * the precision of the register. Everything else requires
10040          * square cursors, limited to a few power-of-two sizes.
10041          */
10042         if (IS_845G(dev) || IS_I865G(dev)) {
10043                 if ((width & 63) != 0)
10044                         return false;
10045
10046                 if (width > (IS_845G(dev) ? 64 : 512))
10047                         return false;
10048
10049                 if (height > 1023)
10050                         return false;
10051         } else {
10052                 switch (width | height) {
10053                 case 256:
10054                 case 128:
10055                         if (IS_GEN2(dev))
10056                                 return false;
10057                 case 64:
10058                         break;
10059                 default:
10060                         return false;
10061                 }
10062         }
10063
10064         return true;
10065 }
10066
10067 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10068                                  u16 *blue, uint32_t start, uint32_t size)
10069 {
10070         int end = (start + size > 256) ? 256 : start + size, i;
10071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10072
10073         for (i = start; i < end; i++) {
10074                 intel_crtc->lut_r[i] = red[i] >> 8;
10075                 intel_crtc->lut_g[i] = green[i] >> 8;
10076                 intel_crtc->lut_b[i] = blue[i] >> 8;
10077         }
10078
10079         intel_crtc_load_lut(crtc);
10080 }
10081
10082 /* VESA 640x480x72Hz mode to set on the pipe */
10083 static struct drm_display_mode load_detect_mode = {
10084         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10085                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10086 };
10087
10088 struct drm_framebuffer *
10089 __intel_framebuffer_create(struct drm_device *dev,
10090                            struct drm_mode_fb_cmd2 *mode_cmd,
10091                            struct drm_i915_gem_object *obj)
10092 {
10093         struct intel_framebuffer *intel_fb;
10094         int ret;
10095
10096         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10097         if (!intel_fb) {
10098                 drm_gem_object_unreference(&obj->base);
10099                 return ERR_PTR(-ENOMEM);
10100         }
10101
10102         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10103         if (ret)
10104                 goto err;
10105
10106         return &intel_fb->base;
10107 err:
10108         drm_gem_object_unreference(&obj->base);
10109         kfree(intel_fb);
10110
10111         return ERR_PTR(ret);
10112 }
10113
10114 static struct drm_framebuffer *
10115 intel_framebuffer_create(struct drm_device *dev,
10116                          struct drm_mode_fb_cmd2 *mode_cmd,
10117                          struct drm_i915_gem_object *obj)
10118 {
10119         struct drm_framebuffer *fb;
10120         int ret;
10121
10122         ret = i915_mutex_lock_interruptible(dev);
10123         if (ret)
10124                 return ERR_PTR(ret);
10125         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10126         mutex_unlock(&dev->struct_mutex);
10127
10128         return fb;
10129 }
10130
10131 static u32
10132 intel_framebuffer_pitch_for_width(int width, int bpp)
10133 {
10134         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10135         return ALIGN(pitch, 64);
10136 }
10137
10138 static u32
10139 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10140 {
10141         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10142         return PAGE_ALIGN(pitch * mode->vdisplay);
10143 }
10144
10145 static struct drm_framebuffer *
10146 intel_framebuffer_create_for_mode(struct drm_device *dev,
10147                                   struct drm_display_mode *mode,
10148                                   int depth, int bpp)
10149 {
10150         struct drm_i915_gem_object *obj;
10151         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10152
10153         obj = i915_gem_alloc_object(dev,
10154                                     intel_framebuffer_size_for_mode(mode, bpp));
10155         if (obj == NULL)
10156                 return ERR_PTR(-ENOMEM);
10157
10158         mode_cmd.width = mode->hdisplay;
10159         mode_cmd.height = mode->vdisplay;
10160         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10161                                                                 bpp);
10162         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10163
10164         return intel_framebuffer_create(dev, &mode_cmd, obj);
10165 }
10166
10167 static struct drm_framebuffer *
10168 mode_fits_in_fbdev(struct drm_device *dev,
10169                    struct drm_display_mode *mode)
10170 {
10171 #ifdef CONFIG_DRM_FBDEV_EMULATION
10172         struct drm_i915_private *dev_priv = dev->dev_private;
10173         struct drm_i915_gem_object *obj;
10174         struct drm_framebuffer *fb;
10175
10176         if (!dev_priv->fbdev)
10177                 return NULL;
10178
10179         if (!dev_priv->fbdev->fb)
10180                 return NULL;
10181
10182         obj = dev_priv->fbdev->fb->obj;
10183         BUG_ON(!obj);
10184
10185         fb = &dev_priv->fbdev->fb->base;
10186         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10187                                                                fb->bits_per_pixel))
10188                 return NULL;
10189
10190         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10191                 return NULL;
10192
10193         return fb;
10194 #else
10195         return NULL;
10196 #endif
10197 }
10198
10199 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10200                                            struct drm_crtc *crtc,
10201                                            struct drm_display_mode *mode,
10202                                            struct drm_framebuffer *fb,
10203                                            int x, int y)
10204 {
10205         struct drm_plane_state *plane_state;
10206         int hdisplay, vdisplay;
10207         int ret;
10208
10209         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10210         if (IS_ERR(plane_state))
10211                 return PTR_ERR(plane_state);
10212
10213         if (mode)
10214                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10215         else
10216                 hdisplay = vdisplay = 0;
10217
10218         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10219         if (ret)
10220                 return ret;
10221         drm_atomic_set_fb_for_plane(plane_state, fb);
10222         plane_state->crtc_x = 0;
10223         plane_state->crtc_y = 0;
10224         plane_state->crtc_w = hdisplay;
10225         plane_state->crtc_h = vdisplay;
10226         plane_state->src_x = x << 16;
10227         plane_state->src_y = y << 16;
10228         plane_state->src_w = hdisplay << 16;
10229         plane_state->src_h = vdisplay << 16;
10230
10231         return 0;
10232 }
10233
10234 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10235                                 struct drm_display_mode *mode,
10236                                 struct intel_load_detect_pipe *old,
10237                                 struct drm_modeset_acquire_ctx *ctx)
10238 {
10239         struct intel_crtc *intel_crtc;
10240         struct intel_encoder *intel_encoder =
10241                 intel_attached_encoder(connector);
10242         struct drm_crtc *possible_crtc;
10243         struct drm_encoder *encoder = &intel_encoder->base;
10244         struct drm_crtc *crtc = NULL;
10245         struct drm_device *dev = encoder->dev;
10246         struct drm_framebuffer *fb;
10247         struct drm_mode_config *config = &dev->mode_config;
10248         struct drm_atomic_state *state = NULL;
10249         struct drm_connector_state *connector_state;
10250         struct intel_crtc_state *crtc_state;
10251         int ret, i = -1;
10252
10253         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10254                       connector->base.id, connector->name,
10255                       encoder->base.id, encoder->name);
10256
10257 retry:
10258         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10259         if (ret)
10260                 goto fail;
10261
10262         /*
10263          * Algorithm gets a little messy:
10264          *
10265          *   - if the connector already has an assigned crtc, use it (but make
10266          *     sure it's on first)
10267          *
10268          *   - try to find the first unused crtc that can drive this connector,
10269          *     and use that if we find one
10270          */
10271
10272         /* See if we already have a CRTC for this connector */
10273         if (encoder->crtc) {
10274                 crtc = encoder->crtc;
10275
10276                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10277                 if (ret)
10278                         goto fail;
10279                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10280                 if (ret)
10281                         goto fail;
10282
10283                 old->dpms_mode = connector->dpms;
10284                 old->load_detect_temp = false;
10285
10286                 /* Make sure the crtc and connector are running */
10287                 if (connector->dpms != DRM_MODE_DPMS_ON)
10288                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10289
10290                 return true;
10291         }
10292
10293         /* Find an unused one (if possible) */
10294         for_each_crtc(dev, possible_crtc) {
10295                 i++;
10296                 if (!(encoder->possible_crtcs & (1 << i)))
10297                         continue;
10298                 if (possible_crtc->state->enable)
10299                         continue;
10300
10301                 crtc = possible_crtc;
10302                 break;
10303         }
10304
10305         /*
10306          * If we didn't find an unused CRTC, don't use any.
10307          */
10308         if (!crtc) {
10309                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10310                 goto fail;
10311         }
10312
10313         ret = drm_modeset_lock(&crtc->mutex, ctx);
10314         if (ret)
10315                 goto fail;
10316         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10317         if (ret)
10318                 goto fail;
10319
10320         intel_crtc = to_intel_crtc(crtc);
10321         old->dpms_mode = connector->dpms;
10322         old->load_detect_temp = true;
10323         old->release_fb = NULL;
10324
10325         state = drm_atomic_state_alloc(dev);
10326         if (!state)
10327                 return false;
10328
10329         state->acquire_ctx = ctx;
10330
10331         connector_state = drm_atomic_get_connector_state(state, connector);
10332         if (IS_ERR(connector_state)) {
10333                 ret = PTR_ERR(connector_state);
10334                 goto fail;
10335         }
10336
10337         connector_state->crtc = crtc;
10338         connector_state->best_encoder = &intel_encoder->base;
10339
10340         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10341         if (IS_ERR(crtc_state)) {
10342                 ret = PTR_ERR(crtc_state);
10343                 goto fail;
10344         }
10345
10346         crtc_state->base.active = crtc_state->base.enable = true;
10347
10348         if (!mode)
10349                 mode = &load_detect_mode;
10350
10351         /* We need a framebuffer large enough to accommodate all accesses
10352          * that the plane may generate whilst we perform load detection.
10353          * We can not rely on the fbcon either being present (we get called
10354          * during its initialisation to detect all boot displays, or it may
10355          * not even exist) or that it is large enough to satisfy the
10356          * requested mode.
10357          */
10358         fb = mode_fits_in_fbdev(dev, mode);
10359         if (fb == NULL) {
10360                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10361                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10362                 old->release_fb = fb;
10363         } else
10364                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10365         if (IS_ERR(fb)) {
10366                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10367                 goto fail;
10368         }
10369
10370         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10371         if (ret)
10372                 goto fail;
10373
10374         drm_mode_copy(&crtc_state->base.mode, mode);
10375
10376         if (drm_atomic_commit(state)) {
10377                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10378                 if (old->release_fb)
10379                         old->release_fb->funcs->destroy(old->release_fb);
10380                 goto fail;
10381         }
10382         crtc->primary->crtc = crtc;
10383
10384         /* let the connector get through one full cycle before testing */
10385         intel_wait_for_vblank(dev, intel_crtc->pipe);
10386         return true;
10387
10388 fail:
10389         drm_atomic_state_free(state);
10390         state = NULL;
10391
10392         if (ret == -EDEADLK) {
10393                 drm_modeset_backoff(ctx);
10394                 goto retry;
10395         }
10396
10397         return false;
10398 }
10399
10400 void intel_release_load_detect_pipe(struct drm_connector *connector,
10401                                     struct intel_load_detect_pipe *old,
10402                                     struct drm_modeset_acquire_ctx *ctx)
10403 {
10404         struct drm_device *dev = connector->dev;
10405         struct intel_encoder *intel_encoder =
10406                 intel_attached_encoder(connector);
10407         struct drm_encoder *encoder = &intel_encoder->base;
10408         struct drm_crtc *crtc = encoder->crtc;
10409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10410         struct drm_atomic_state *state;
10411         struct drm_connector_state *connector_state;
10412         struct intel_crtc_state *crtc_state;
10413         int ret;
10414
10415         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10416                       connector->base.id, connector->name,
10417                       encoder->base.id, encoder->name);
10418
10419         if (old->load_detect_temp) {
10420                 state = drm_atomic_state_alloc(dev);
10421                 if (!state)
10422                         goto fail;
10423
10424                 state->acquire_ctx = ctx;
10425
10426                 connector_state = drm_atomic_get_connector_state(state, connector);
10427                 if (IS_ERR(connector_state))
10428                         goto fail;
10429
10430                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10431                 if (IS_ERR(crtc_state))
10432                         goto fail;
10433
10434                 connector_state->best_encoder = NULL;
10435                 connector_state->crtc = NULL;
10436
10437                 crtc_state->base.enable = crtc_state->base.active = false;
10438
10439                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10440                                                       0, 0);
10441                 if (ret)
10442                         goto fail;
10443
10444                 ret = drm_atomic_commit(state);
10445                 if (ret)
10446                         goto fail;
10447
10448                 if (old->release_fb) {
10449                         drm_framebuffer_unregister_private(old->release_fb);
10450                         drm_framebuffer_unreference(old->release_fb);
10451                 }
10452
10453                 return;
10454         }
10455
10456         /* Switch crtc and encoder back off if necessary */
10457         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10458                 connector->funcs->dpms(connector, old->dpms_mode);
10459
10460         return;
10461 fail:
10462         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10463         drm_atomic_state_free(state);
10464 }
10465
10466 static int i9xx_pll_refclk(struct drm_device *dev,
10467                            const struct intel_crtc_state *pipe_config)
10468 {
10469         struct drm_i915_private *dev_priv = dev->dev_private;
10470         u32 dpll = pipe_config->dpll_hw_state.dpll;
10471
10472         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10473                 return dev_priv->vbt.lvds_ssc_freq;
10474         else if (HAS_PCH_SPLIT(dev))
10475                 return 120000;
10476         else if (!IS_GEN2(dev))
10477                 return 96000;
10478         else
10479                 return 48000;
10480 }
10481
10482 /* Returns the clock of the currently programmed mode of the given pipe. */
10483 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10484                                 struct intel_crtc_state *pipe_config)
10485 {
10486         struct drm_device *dev = crtc->base.dev;
10487         struct drm_i915_private *dev_priv = dev->dev_private;
10488         int pipe = pipe_config->cpu_transcoder;
10489         u32 dpll = pipe_config->dpll_hw_state.dpll;
10490         u32 fp;
10491         intel_clock_t clock;
10492         int port_clock;
10493         int refclk = i9xx_pll_refclk(dev, pipe_config);
10494
10495         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10496                 fp = pipe_config->dpll_hw_state.fp0;
10497         else
10498                 fp = pipe_config->dpll_hw_state.fp1;
10499
10500         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10501         if (IS_PINEVIEW(dev)) {
10502                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10503                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10504         } else {
10505                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10506                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10507         }
10508
10509         if (!IS_GEN2(dev)) {
10510                 if (IS_PINEVIEW(dev))
10511                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10512                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10513                 else
10514                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10515                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10516
10517                 switch (dpll & DPLL_MODE_MASK) {
10518                 case DPLLB_MODE_DAC_SERIAL:
10519                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10520                                 5 : 10;
10521                         break;
10522                 case DPLLB_MODE_LVDS:
10523                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10524                                 7 : 14;
10525                         break;
10526                 default:
10527                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10528                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10529                         return;
10530                 }
10531
10532                 if (IS_PINEVIEW(dev))
10533                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10534                 else
10535                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10536         } else {
10537                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10538                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10539
10540                 if (is_lvds) {
10541                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10542                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10543
10544                         if (lvds & LVDS_CLKB_POWER_UP)
10545                                 clock.p2 = 7;
10546                         else
10547                                 clock.p2 = 14;
10548                 } else {
10549                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10550                                 clock.p1 = 2;
10551                         else {
10552                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10553                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10554                         }
10555                         if (dpll & PLL_P2_DIVIDE_BY_4)
10556                                 clock.p2 = 4;
10557                         else
10558                                 clock.p2 = 2;
10559                 }
10560
10561                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10562         }
10563
10564         /*
10565          * This value includes pixel_multiplier. We will use
10566          * port_clock to compute adjusted_mode.crtc_clock in the
10567          * encoder's get_config() function.
10568          */
10569         pipe_config->port_clock = port_clock;
10570 }
10571
10572 int intel_dotclock_calculate(int link_freq,
10573                              const struct intel_link_m_n *m_n)
10574 {
10575         /*
10576          * The calculation for the data clock is:
10577          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10578          * But we want to avoid losing precison if possible, so:
10579          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10580          *
10581          * and the link clock is simpler:
10582          * link_clock = (m * link_clock) / n
10583          */
10584
10585         if (!m_n->link_n)
10586                 return 0;
10587
10588         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10589 }
10590
10591 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10592                                    struct intel_crtc_state *pipe_config)
10593 {
10594         struct drm_device *dev = crtc->base.dev;
10595
10596         /* read out port_clock from the DPLL */
10597         i9xx_crtc_clock_get(crtc, pipe_config);
10598
10599         /*
10600          * This value does not include pixel_multiplier.
10601          * We will check that port_clock and adjusted_mode.crtc_clock
10602          * agree once we know their relationship in the encoder's
10603          * get_config() function.
10604          */
10605         pipe_config->base.adjusted_mode.crtc_clock =
10606                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10607                                          &pipe_config->fdi_m_n);
10608 }
10609
10610 /** Returns the currently programmed mode of the given pipe. */
10611 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10612                                              struct drm_crtc *crtc)
10613 {
10614         struct drm_i915_private *dev_priv = dev->dev_private;
10615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10616         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10617         struct drm_display_mode *mode;
10618         struct intel_crtc_state pipe_config;
10619         int htot = I915_READ(HTOTAL(cpu_transcoder));
10620         int hsync = I915_READ(HSYNC(cpu_transcoder));
10621         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10622         int vsync = I915_READ(VSYNC(cpu_transcoder));
10623         enum pipe pipe = intel_crtc->pipe;
10624
10625         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10626         if (!mode)
10627                 return NULL;
10628
10629         /*
10630          * Construct a pipe_config sufficient for getting the clock info
10631          * back out of crtc_clock_get.
10632          *
10633          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10634          * to use a real value here instead.
10635          */
10636         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10637         pipe_config.pixel_multiplier = 1;
10638         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10639         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10640         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10641         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10642
10643         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10644         mode->hdisplay = (htot & 0xffff) + 1;
10645         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10646         mode->hsync_start = (hsync & 0xffff) + 1;
10647         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10648         mode->vdisplay = (vtot & 0xffff) + 1;
10649         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10650         mode->vsync_start = (vsync & 0xffff) + 1;
10651         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10652
10653         drm_mode_set_name(mode);
10654
10655         return mode;
10656 }
10657
10658 void intel_mark_busy(struct drm_device *dev)
10659 {
10660         struct drm_i915_private *dev_priv = dev->dev_private;
10661
10662         if (dev_priv->mm.busy)
10663                 return;
10664
10665         intel_runtime_pm_get(dev_priv);
10666         i915_update_gfx_val(dev_priv);
10667         if (INTEL_INFO(dev)->gen >= 6)
10668                 gen6_rps_busy(dev_priv);
10669         dev_priv->mm.busy = true;
10670 }
10671
10672 void intel_mark_idle(struct drm_device *dev)
10673 {
10674         struct drm_i915_private *dev_priv = dev->dev_private;
10675
10676         if (!dev_priv->mm.busy)
10677                 return;
10678
10679         dev_priv->mm.busy = false;
10680
10681         if (INTEL_INFO(dev)->gen >= 6)
10682                 gen6_rps_idle(dev->dev_private);
10683
10684         intel_runtime_pm_put(dev_priv);
10685 }
10686
10687 static void intel_crtc_destroy(struct drm_crtc *crtc)
10688 {
10689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10690         struct drm_device *dev = crtc->dev;
10691         struct intel_unpin_work *work;
10692
10693         spin_lock_irq(&dev->event_lock);
10694         work = intel_crtc->unpin_work;
10695         intel_crtc->unpin_work = NULL;
10696         spin_unlock_irq(&dev->event_lock);
10697
10698         if (work) {
10699                 cancel_work_sync(&work->work);
10700                 kfree(work);
10701         }
10702
10703         drm_crtc_cleanup(crtc);
10704
10705         kfree(intel_crtc);
10706 }
10707
10708 static void intel_unpin_work_fn(struct work_struct *__work)
10709 {
10710         struct intel_unpin_work *work =
10711                 container_of(__work, struct intel_unpin_work, work);
10712         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10713         struct drm_device *dev = crtc->base.dev;
10714         struct drm_plane *primary = crtc->base.primary;
10715
10716         mutex_lock(&dev->struct_mutex);
10717         intel_unpin_fb_obj(work->old_fb, primary->state);
10718         drm_gem_object_unreference(&work->pending_flip_obj->base);
10719
10720         if (work->flip_queued_req)
10721                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10722         mutex_unlock(&dev->struct_mutex);
10723
10724         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10725         drm_framebuffer_unreference(work->old_fb);
10726
10727         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10728         atomic_dec(&crtc->unpin_work_count);
10729
10730         kfree(work);
10731 }
10732
10733 static void do_intel_finish_page_flip(struct drm_device *dev,
10734                                       struct drm_crtc *crtc)
10735 {
10736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10737         struct intel_unpin_work *work;
10738         unsigned long flags;
10739
10740         /* Ignore early vblank irqs */
10741         if (intel_crtc == NULL)
10742                 return;
10743
10744         /*
10745          * This is called both by irq handlers and the reset code (to complete
10746          * lost pageflips) so needs the full irqsave spinlocks.
10747          */
10748         spin_lock_irqsave(&dev->event_lock, flags);
10749         work = intel_crtc->unpin_work;
10750
10751         /* Ensure we don't miss a work->pending update ... */
10752         smp_rmb();
10753
10754         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10755                 spin_unlock_irqrestore(&dev->event_lock, flags);
10756                 return;
10757         }
10758
10759         page_flip_completed(intel_crtc);
10760
10761         spin_unlock_irqrestore(&dev->event_lock, flags);
10762 }
10763
10764 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10765 {
10766         struct drm_i915_private *dev_priv = dev->dev_private;
10767         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10768
10769         do_intel_finish_page_flip(dev, crtc);
10770 }
10771
10772 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10773 {
10774         struct drm_i915_private *dev_priv = dev->dev_private;
10775         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10776
10777         do_intel_finish_page_flip(dev, crtc);
10778 }
10779
10780 /* Is 'a' after or equal to 'b'? */
10781 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10782 {
10783         return !((a - b) & 0x80000000);
10784 }
10785
10786 static bool page_flip_finished(struct intel_crtc *crtc)
10787 {
10788         struct drm_device *dev = crtc->base.dev;
10789         struct drm_i915_private *dev_priv = dev->dev_private;
10790
10791         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10792             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10793                 return true;
10794
10795         /*
10796          * The relevant registers doen't exist on pre-ctg.
10797          * As the flip done interrupt doesn't trigger for mmio
10798          * flips on gmch platforms, a flip count check isn't
10799          * really needed there. But since ctg has the registers,
10800          * include it in the check anyway.
10801          */
10802         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10803                 return true;
10804
10805         /*
10806          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10807          * used the same base address. In that case the mmio flip might
10808          * have completed, but the CS hasn't even executed the flip yet.
10809          *
10810          * A flip count check isn't enough as the CS might have updated
10811          * the base address just after start of vblank, but before we
10812          * managed to process the interrupt. This means we'd complete the
10813          * CS flip too soon.
10814          *
10815          * Combining both checks should get us a good enough result. It may
10816          * still happen that the CS flip has been executed, but has not
10817          * yet actually completed. But in case the base address is the same
10818          * anyway, we don't really care.
10819          */
10820         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10821                 crtc->unpin_work->gtt_offset &&
10822                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10823                                     crtc->unpin_work->flip_count);
10824 }
10825
10826 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10827 {
10828         struct drm_i915_private *dev_priv = dev->dev_private;
10829         struct intel_crtc *intel_crtc =
10830                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10831         unsigned long flags;
10832
10833
10834         /*
10835          * This is called both by irq handlers and the reset code (to complete
10836          * lost pageflips) so needs the full irqsave spinlocks.
10837          *
10838          * NB: An MMIO update of the plane base pointer will also
10839          * generate a page-flip completion irq, i.e. every modeset
10840          * is also accompanied by a spurious intel_prepare_page_flip().
10841          */
10842         spin_lock_irqsave(&dev->event_lock, flags);
10843         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10844                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10845         spin_unlock_irqrestore(&dev->event_lock, flags);
10846 }
10847
10848 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10849 {
10850         /* Ensure that the work item is consistent when activating it ... */
10851         smp_wmb();
10852         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10853         /* and that it is marked active as soon as the irq could fire. */
10854         smp_wmb();
10855 }
10856
10857 static int intel_gen2_queue_flip(struct drm_device *dev,
10858                                  struct drm_crtc *crtc,
10859                                  struct drm_framebuffer *fb,
10860                                  struct drm_i915_gem_object *obj,
10861                                  struct drm_i915_gem_request *req,
10862                                  uint32_t flags)
10863 {
10864         struct intel_engine_cs *ring = req->ring;
10865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10866         u32 flip_mask;
10867         int ret;
10868
10869         ret = intel_ring_begin(req, 6);
10870         if (ret)
10871                 return ret;
10872
10873         /* Can't queue multiple flips, so wait for the previous
10874          * one to finish before executing the next.
10875          */
10876         if (intel_crtc->plane)
10877                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10878         else
10879                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10880         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10881         intel_ring_emit(ring, MI_NOOP);
10882         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10883                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10884         intel_ring_emit(ring, fb->pitches[0]);
10885         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10886         intel_ring_emit(ring, 0); /* aux display base address, unused */
10887
10888         intel_mark_page_flip_active(intel_crtc);
10889         return 0;
10890 }
10891
10892 static int intel_gen3_queue_flip(struct drm_device *dev,
10893                                  struct drm_crtc *crtc,
10894                                  struct drm_framebuffer *fb,
10895                                  struct drm_i915_gem_object *obj,
10896                                  struct drm_i915_gem_request *req,
10897                                  uint32_t flags)
10898 {
10899         struct intel_engine_cs *ring = req->ring;
10900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10901         u32 flip_mask;
10902         int ret;
10903
10904         ret = intel_ring_begin(req, 6);
10905         if (ret)
10906                 return ret;
10907
10908         if (intel_crtc->plane)
10909                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10910         else
10911                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10912         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10913         intel_ring_emit(ring, MI_NOOP);
10914         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10915                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10916         intel_ring_emit(ring, fb->pitches[0]);
10917         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10918         intel_ring_emit(ring, MI_NOOP);
10919
10920         intel_mark_page_flip_active(intel_crtc);
10921         return 0;
10922 }
10923
10924 static int intel_gen4_queue_flip(struct drm_device *dev,
10925                                  struct drm_crtc *crtc,
10926                                  struct drm_framebuffer *fb,
10927                                  struct drm_i915_gem_object *obj,
10928                                  struct drm_i915_gem_request *req,
10929                                  uint32_t flags)
10930 {
10931         struct intel_engine_cs *ring = req->ring;
10932         struct drm_i915_private *dev_priv = dev->dev_private;
10933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10934         uint32_t pf, pipesrc;
10935         int ret;
10936
10937         ret = intel_ring_begin(req, 4);
10938         if (ret)
10939                 return ret;
10940
10941         /* i965+ uses the linear or tiled offsets from the
10942          * Display Registers (which do not change across a page-flip)
10943          * so we need only reprogram the base address.
10944          */
10945         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10946                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10947         intel_ring_emit(ring, fb->pitches[0]);
10948         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10949                         obj->tiling_mode);
10950
10951         /* XXX Enabling the panel-fitter across page-flip is so far
10952          * untested on non-native modes, so ignore it for now.
10953          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10954          */
10955         pf = 0;
10956         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10957         intel_ring_emit(ring, pf | pipesrc);
10958
10959         intel_mark_page_flip_active(intel_crtc);
10960         return 0;
10961 }
10962
10963 static int intel_gen6_queue_flip(struct drm_device *dev,
10964                                  struct drm_crtc *crtc,
10965                                  struct drm_framebuffer *fb,
10966                                  struct drm_i915_gem_object *obj,
10967                                  struct drm_i915_gem_request *req,
10968                                  uint32_t flags)
10969 {
10970         struct intel_engine_cs *ring = req->ring;
10971         struct drm_i915_private *dev_priv = dev->dev_private;
10972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10973         uint32_t pf, pipesrc;
10974         int ret;
10975
10976         ret = intel_ring_begin(req, 4);
10977         if (ret)
10978                 return ret;
10979
10980         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10981                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10982         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10983         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10984
10985         /* Contrary to the suggestions in the documentation,
10986          * "Enable Panel Fitter" does not seem to be required when page
10987          * flipping with a non-native mode, and worse causes a normal
10988          * modeset to fail.
10989          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10990          */
10991         pf = 0;
10992         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10993         intel_ring_emit(ring, pf | pipesrc);
10994
10995         intel_mark_page_flip_active(intel_crtc);
10996         return 0;
10997 }
10998
10999 static int intel_gen7_queue_flip(struct drm_device *dev,
11000                                  struct drm_crtc *crtc,
11001                                  struct drm_framebuffer *fb,
11002                                  struct drm_i915_gem_object *obj,
11003                                  struct drm_i915_gem_request *req,
11004                                  uint32_t flags)
11005 {
11006         struct intel_engine_cs *ring = req->ring;
11007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11008         uint32_t plane_bit = 0;
11009         int len, ret;
11010
11011         switch (intel_crtc->plane) {
11012         case PLANE_A:
11013                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11014                 break;
11015         case PLANE_B:
11016                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11017                 break;
11018         case PLANE_C:
11019                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11020                 break;
11021         default:
11022                 WARN_ONCE(1, "unknown plane in flip command\n");
11023                 return -ENODEV;
11024         }
11025
11026         len = 4;
11027         if (ring->id == RCS) {
11028                 len += 6;
11029                 /*
11030                  * On Gen 8, SRM is now taking an extra dword to accommodate
11031                  * 48bits addresses, and we need a NOOP for the batch size to
11032                  * stay even.
11033                  */
11034                 if (IS_GEN8(dev))
11035                         len += 2;
11036         }
11037
11038         /*
11039          * BSpec MI_DISPLAY_FLIP for IVB:
11040          * "The full packet must be contained within the same cache line."
11041          *
11042          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11043          * cacheline, if we ever start emitting more commands before
11044          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11045          * then do the cacheline alignment, and finally emit the
11046          * MI_DISPLAY_FLIP.
11047          */
11048         ret = intel_ring_cacheline_align(req);
11049         if (ret)
11050                 return ret;
11051
11052         ret = intel_ring_begin(req, len);
11053         if (ret)
11054                 return ret;
11055
11056         /* Unmask the flip-done completion message. Note that the bspec says that
11057          * we should do this for both the BCS and RCS, and that we must not unmask
11058          * more than one flip event at any time (or ensure that one flip message
11059          * can be sent by waiting for flip-done prior to queueing new flips).
11060          * Experimentation says that BCS works despite DERRMR masking all
11061          * flip-done completion events and that unmasking all planes at once
11062          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11063          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11064          */
11065         if (ring->id == RCS) {
11066                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11067                 intel_ring_emit(ring, DERRMR);
11068                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11069                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11070                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11071                 if (IS_GEN8(dev))
11072                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11073                                               MI_SRM_LRM_GLOBAL_GTT);
11074                 else
11075                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11076                                               MI_SRM_LRM_GLOBAL_GTT);
11077                 intel_ring_emit(ring, DERRMR);
11078                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11079                 if (IS_GEN8(dev)) {
11080                         intel_ring_emit(ring, 0);
11081                         intel_ring_emit(ring, MI_NOOP);
11082                 }
11083         }
11084
11085         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11086         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11087         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11088         intel_ring_emit(ring, (MI_NOOP));
11089
11090         intel_mark_page_flip_active(intel_crtc);
11091         return 0;
11092 }
11093
11094 static bool use_mmio_flip(struct intel_engine_cs *ring,
11095                           struct drm_i915_gem_object *obj)
11096 {
11097         /*
11098          * This is not being used for older platforms, because
11099          * non-availability of flip done interrupt forces us to use
11100          * CS flips. Older platforms derive flip done using some clever
11101          * tricks involving the flip_pending status bits and vblank irqs.
11102          * So using MMIO flips there would disrupt this mechanism.
11103          */
11104
11105         if (ring == NULL)
11106                 return true;
11107
11108         if (INTEL_INFO(ring->dev)->gen < 5)
11109                 return false;
11110
11111         if (i915.use_mmio_flip < 0)
11112                 return false;
11113         else if (i915.use_mmio_flip > 0)
11114                 return true;
11115         else if (i915.enable_execlists)
11116                 return true;
11117         else
11118                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11119 }
11120
11121 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11122 {
11123         struct drm_device *dev = intel_crtc->base.dev;
11124         struct drm_i915_private *dev_priv = dev->dev_private;
11125         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11126         const enum pipe pipe = intel_crtc->pipe;
11127         u32 ctl, stride;
11128
11129         ctl = I915_READ(PLANE_CTL(pipe, 0));
11130         ctl &= ~PLANE_CTL_TILED_MASK;
11131         switch (fb->modifier[0]) {
11132         case DRM_FORMAT_MOD_NONE:
11133                 break;
11134         case I915_FORMAT_MOD_X_TILED:
11135                 ctl |= PLANE_CTL_TILED_X;
11136                 break;
11137         case I915_FORMAT_MOD_Y_TILED:
11138                 ctl |= PLANE_CTL_TILED_Y;
11139                 break;
11140         case I915_FORMAT_MOD_Yf_TILED:
11141                 ctl |= PLANE_CTL_TILED_YF;
11142                 break;
11143         default:
11144                 MISSING_CASE(fb->modifier[0]);
11145         }
11146
11147         /*
11148          * The stride is either expressed as a multiple of 64 bytes chunks for
11149          * linear buffers or in number of tiles for tiled buffers.
11150          */
11151         stride = fb->pitches[0] /
11152                  intel_fb_stride_alignment(dev, fb->modifier[0],
11153                                            fb->pixel_format);
11154
11155         /*
11156          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11157          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11158          */
11159         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11160         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11161
11162         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11163         POSTING_READ(PLANE_SURF(pipe, 0));
11164 }
11165
11166 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11167 {
11168         struct drm_device *dev = intel_crtc->base.dev;
11169         struct drm_i915_private *dev_priv = dev->dev_private;
11170         struct intel_framebuffer *intel_fb =
11171                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11172         struct drm_i915_gem_object *obj = intel_fb->obj;
11173         u32 dspcntr;
11174         u32 reg;
11175
11176         reg = DSPCNTR(intel_crtc->plane);
11177         dspcntr = I915_READ(reg);
11178
11179         if (obj->tiling_mode != I915_TILING_NONE)
11180                 dspcntr |= DISPPLANE_TILED;
11181         else
11182                 dspcntr &= ~DISPPLANE_TILED;
11183
11184         I915_WRITE(reg, dspcntr);
11185
11186         I915_WRITE(DSPSURF(intel_crtc->plane),
11187                    intel_crtc->unpin_work->gtt_offset);
11188         POSTING_READ(DSPSURF(intel_crtc->plane));
11189
11190 }
11191
11192 /*
11193  * XXX: This is the temporary way to update the plane registers until we get
11194  * around to using the usual plane update functions for MMIO flips
11195  */
11196 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11197 {
11198         struct drm_device *dev = intel_crtc->base.dev;
11199
11200         intel_mark_page_flip_active(intel_crtc);
11201
11202         intel_pipe_update_start(intel_crtc);
11203
11204         if (INTEL_INFO(dev)->gen >= 9)
11205                 skl_do_mmio_flip(intel_crtc);
11206         else
11207                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11208                 ilk_do_mmio_flip(intel_crtc);
11209
11210         intel_pipe_update_end(intel_crtc);
11211 }
11212
11213 static void intel_mmio_flip_work_func(struct work_struct *work)
11214 {
11215         struct intel_mmio_flip *mmio_flip =
11216                 container_of(work, struct intel_mmio_flip, work);
11217
11218         if (mmio_flip->req)
11219                 WARN_ON(__i915_wait_request(mmio_flip->req,
11220                                             mmio_flip->crtc->reset_counter,
11221                                             false, NULL,
11222                                             &mmio_flip->i915->rps.mmioflips));
11223
11224         intel_do_mmio_flip(mmio_flip->crtc);
11225
11226         i915_gem_request_unreference__unlocked(mmio_flip->req);
11227         kfree(mmio_flip);
11228 }
11229
11230 static int intel_queue_mmio_flip(struct drm_device *dev,
11231                                  struct drm_crtc *crtc,
11232                                  struct drm_framebuffer *fb,
11233                                  struct drm_i915_gem_object *obj,
11234                                  struct intel_engine_cs *ring,
11235                                  uint32_t flags)
11236 {
11237         struct intel_mmio_flip *mmio_flip;
11238
11239         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11240         if (mmio_flip == NULL)
11241                 return -ENOMEM;
11242
11243         mmio_flip->i915 = to_i915(dev);
11244         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11245         mmio_flip->crtc = to_intel_crtc(crtc);
11246
11247         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11248         schedule_work(&mmio_flip->work);
11249
11250         return 0;
11251 }
11252
11253 static int intel_default_queue_flip(struct drm_device *dev,
11254                                     struct drm_crtc *crtc,
11255                                     struct drm_framebuffer *fb,
11256                                     struct drm_i915_gem_object *obj,
11257                                     struct drm_i915_gem_request *req,
11258                                     uint32_t flags)
11259 {
11260         return -ENODEV;
11261 }
11262
11263 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11264                                          struct drm_crtc *crtc)
11265 {
11266         struct drm_i915_private *dev_priv = dev->dev_private;
11267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11268         struct intel_unpin_work *work = intel_crtc->unpin_work;
11269         u32 addr;
11270
11271         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11272                 return true;
11273
11274         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11275                 return false;
11276
11277         if (!work->enable_stall_check)
11278                 return false;
11279
11280         if (work->flip_ready_vblank == 0) {
11281                 if (work->flip_queued_req &&
11282                     !i915_gem_request_completed(work->flip_queued_req, true))
11283                         return false;
11284
11285                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11286         }
11287
11288         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11289                 return false;
11290
11291         /* Potential stall - if we see that the flip has happened,
11292          * assume a missed interrupt. */
11293         if (INTEL_INFO(dev)->gen >= 4)
11294                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11295         else
11296                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11297
11298         /* There is a potential issue here with a false positive after a flip
11299          * to the same address. We could address this by checking for a
11300          * non-incrementing frame counter.
11301          */
11302         return addr == work->gtt_offset;
11303 }
11304
11305 void intel_check_page_flip(struct drm_device *dev, int pipe)
11306 {
11307         struct drm_i915_private *dev_priv = dev->dev_private;
11308         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11310         struct intel_unpin_work *work;
11311
11312         WARN_ON(!in_interrupt());
11313
11314         if (crtc == NULL)
11315                 return;
11316
11317         spin_lock(&dev->event_lock);
11318         work = intel_crtc->unpin_work;
11319         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11320                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11321                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11322                 page_flip_completed(intel_crtc);
11323                 work = NULL;
11324         }
11325         if (work != NULL &&
11326             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11327                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11328         spin_unlock(&dev->event_lock);
11329 }
11330
11331 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11332                                 struct drm_framebuffer *fb,
11333                                 struct drm_pending_vblank_event *event,
11334                                 uint32_t page_flip_flags)
11335 {
11336         struct drm_device *dev = crtc->dev;
11337         struct drm_i915_private *dev_priv = dev->dev_private;
11338         struct drm_framebuffer *old_fb = crtc->primary->fb;
11339         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11341         struct drm_plane *primary = crtc->primary;
11342         enum pipe pipe = intel_crtc->pipe;
11343         struct intel_unpin_work *work;
11344         struct intel_engine_cs *ring;
11345         bool mmio_flip;
11346         struct drm_i915_gem_request *request = NULL;
11347         int ret;
11348
11349         /*
11350          * drm_mode_page_flip_ioctl() should already catch this, but double
11351          * check to be safe.  In the future we may enable pageflipping from
11352          * a disabled primary plane.
11353          */
11354         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11355                 return -EBUSY;
11356
11357         /* Can't change pixel format via MI display flips. */
11358         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11359                 return -EINVAL;
11360
11361         /*
11362          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11363          * Note that pitch changes could also affect these register.
11364          */
11365         if (INTEL_INFO(dev)->gen > 3 &&
11366             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11367              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11368                 return -EINVAL;
11369
11370         if (i915_terminally_wedged(&dev_priv->gpu_error))
11371                 goto out_hang;
11372
11373         work = kzalloc(sizeof(*work), GFP_KERNEL);
11374         if (work == NULL)
11375                 return -ENOMEM;
11376
11377         work->event = event;
11378         work->crtc = crtc;
11379         work->old_fb = old_fb;
11380         INIT_WORK(&work->work, intel_unpin_work_fn);
11381
11382         ret = drm_crtc_vblank_get(crtc);
11383         if (ret)
11384                 goto free_work;
11385
11386         /* We borrow the event spin lock for protecting unpin_work */
11387         spin_lock_irq(&dev->event_lock);
11388         if (intel_crtc->unpin_work) {
11389                 /* Before declaring the flip queue wedged, check if
11390                  * the hardware completed the operation behind our backs.
11391                  */
11392                 if (__intel_pageflip_stall_check(dev, crtc)) {
11393                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11394                         page_flip_completed(intel_crtc);
11395                 } else {
11396                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11397                         spin_unlock_irq(&dev->event_lock);
11398
11399                         drm_crtc_vblank_put(crtc);
11400                         kfree(work);
11401                         return -EBUSY;
11402                 }
11403         }
11404         intel_crtc->unpin_work = work;
11405         spin_unlock_irq(&dev->event_lock);
11406
11407         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11408                 flush_workqueue(dev_priv->wq);
11409
11410         /* Reference the objects for the scheduled work. */
11411         drm_framebuffer_reference(work->old_fb);
11412         drm_gem_object_reference(&obj->base);
11413
11414         crtc->primary->fb = fb;
11415         update_state_fb(crtc->primary);
11416
11417         work->pending_flip_obj = obj;
11418
11419         ret = i915_mutex_lock_interruptible(dev);
11420         if (ret)
11421                 goto cleanup;
11422
11423         atomic_inc(&intel_crtc->unpin_work_count);
11424         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11425
11426         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11427                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11428
11429         if (IS_VALLEYVIEW(dev)) {
11430                 ring = &dev_priv->ring[BCS];
11431                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11432                         /* vlv: DISPLAY_FLIP fails to change tiling */
11433                         ring = NULL;
11434         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11435                 ring = &dev_priv->ring[BCS];
11436         } else if (INTEL_INFO(dev)->gen >= 7) {
11437                 ring = i915_gem_request_get_ring(obj->last_write_req);
11438                 if (ring == NULL || ring->id != RCS)
11439                         ring = &dev_priv->ring[BCS];
11440         } else {
11441                 ring = &dev_priv->ring[RCS];
11442         }
11443
11444         mmio_flip = use_mmio_flip(ring, obj);
11445
11446         /* When using CS flips, we want to emit semaphores between rings.
11447          * However, when using mmio flips we will create a task to do the
11448          * synchronisation, so all we want here is to pin the framebuffer
11449          * into the display plane and skip any waits.
11450          */
11451         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11452                                          crtc->primary->state,
11453                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11454         if (ret)
11455                 goto cleanup_pending;
11456
11457         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11458                                                   obj, 0);
11459         work->gtt_offset += intel_crtc->dspaddr_offset;
11460
11461         if (mmio_flip) {
11462                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11463                                             page_flip_flags);
11464                 if (ret)
11465                         goto cleanup_unpin;
11466
11467                 i915_gem_request_assign(&work->flip_queued_req,
11468                                         obj->last_write_req);
11469         } else {
11470                 if (!request) {
11471                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11472                         if (ret)
11473                                 goto cleanup_unpin;
11474                 }
11475
11476                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11477                                                    page_flip_flags);
11478                 if (ret)
11479                         goto cleanup_unpin;
11480
11481                 i915_gem_request_assign(&work->flip_queued_req, request);
11482         }
11483
11484         if (request)
11485                 i915_add_request_no_flush(request);
11486
11487         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11488         work->enable_stall_check = true;
11489
11490         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11491                           to_intel_plane(primary)->frontbuffer_bit);
11492         mutex_unlock(&dev->struct_mutex);
11493
11494         intel_fbc_disable_crtc(intel_crtc);
11495         intel_frontbuffer_flip_prepare(dev,
11496                                        to_intel_plane(primary)->frontbuffer_bit);
11497
11498         trace_i915_flip_request(intel_crtc->plane, obj);
11499
11500         return 0;
11501
11502 cleanup_unpin:
11503         intel_unpin_fb_obj(fb, crtc->primary->state);
11504 cleanup_pending:
11505         if (request)
11506                 i915_gem_request_cancel(request);
11507         atomic_dec(&intel_crtc->unpin_work_count);
11508         mutex_unlock(&dev->struct_mutex);
11509 cleanup:
11510         crtc->primary->fb = old_fb;
11511         update_state_fb(crtc->primary);
11512
11513         drm_gem_object_unreference_unlocked(&obj->base);
11514         drm_framebuffer_unreference(work->old_fb);
11515
11516         spin_lock_irq(&dev->event_lock);
11517         intel_crtc->unpin_work = NULL;
11518         spin_unlock_irq(&dev->event_lock);
11519
11520         drm_crtc_vblank_put(crtc);
11521 free_work:
11522         kfree(work);
11523
11524         if (ret == -EIO) {
11525                 struct drm_atomic_state *state;
11526                 struct drm_plane_state *plane_state;
11527
11528 out_hang:
11529                 state = drm_atomic_state_alloc(dev);
11530                 if (!state)
11531                         return -ENOMEM;
11532                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11533
11534 retry:
11535                 plane_state = drm_atomic_get_plane_state(state, primary);
11536                 ret = PTR_ERR_OR_ZERO(plane_state);
11537                 if (!ret) {
11538                         drm_atomic_set_fb_for_plane(plane_state, fb);
11539
11540                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11541                         if (!ret)
11542                                 ret = drm_atomic_commit(state);
11543                 }
11544
11545                 if (ret == -EDEADLK) {
11546                         drm_modeset_backoff(state->acquire_ctx);
11547                         drm_atomic_state_clear(state);
11548                         goto retry;
11549                 }
11550
11551                 if (ret)
11552                         drm_atomic_state_free(state);
11553
11554                 if (ret == 0 && event) {
11555                         spin_lock_irq(&dev->event_lock);
11556                         drm_send_vblank_event(dev, pipe, event);
11557                         spin_unlock_irq(&dev->event_lock);
11558                 }
11559         }
11560         return ret;
11561 }
11562
11563
11564 /**
11565  * intel_wm_need_update - Check whether watermarks need updating
11566  * @plane: drm plane
11567  * @state: new plane state
11568  *
11569  * Check current plane state versus the new one to determine whether
11570  * watermarks need to be recalculated.
11571  *
11572  * Returns true or false.
11573  */
11574 static bool intel_wm_need_update(struct drm_plane *plane,
11575                                  struct drm_plane_state *state)
11576 {
11577         /* Update watermarks on tiling changes. */
11578         if (!plane->state->fb || !state->fb ||
11579             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11580             plane->state->rotation != state->rotation)
11581                 return true;
11582
11583         if (plane->state->crtc_w != state->crtc_w)
11584                 return true;
11585
11586         return false;
11587 }
11588
11589 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11590                                     struct drm_plane_state *plane_state)
11591 {
11592         struct drm_crtc *crtc = crtc_state->crtc;
11593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11594         struct drm_plane *plane = plane_state->plane;
11595         struct drm_device *dev = crtc->dev;
11596         struct drm_i915_private *dev_priv = dev->dev_private;
11597         struct intel_plane_state *old_plane_state =
11598                 to_intel_plane_state(plane->state);
11599         int idx = intel_crtc->base.base.id, ret;
11600         int i = drm_plane_index(plane);
11601         bool mode_changed = needs_modeset(crtc_state);
11602         bool was_crtc_enabled = crtc->state->active;
11603         bool is_crtc_enabled = crtc_state->active;
11604
11605         bool turn_off, turn_on, visible, was_visible;
11606         struct drm_framebuffer *fb = plane_state->fb;
11607
11608         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11609             plane->type != DRM_PLANE_TYPE_CURSOR) {
11610                 ret = skl_update_scaler_plane(
11611                         to_intel_crtc_state(crtc_state),
11612                         to_intel_plane_state(plane_state));
11613                 if (ret)
11614                         return ret;
11615         }
11616
11617         /*
11618          * Disabling a plane is always okay; we just need to update
11619          * fb tracking in a special way since cleanup_fb() won't
11620          * get called by the plane helpers.
11621          */
11622         if (old_plane_state->base.fb && !fb)
11623                 intel_crtc->atomic.disabled_planes |= 1 << i;
11624
11625         was_visible = old_plane_state->visible;
11626         visible = to_intel_plane_state(plane_state)->visible;
11627
11628         if (!was_crtc_enabled && WARN_ON(was_visible))
11629                 was_visible = false;
11630
11631         if (!is_crtc_enabled && WARN_ON(visible))
11632                 visible = false;
11633
11634         if (!was_visible && !visible)
11635                 return 0;
11636
11637         turn_off = was_visible && (!visible || mode_changed);
11638         turn_on = visible && (!was_visible || mode_changed);
11639
11640         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11641                          plane->base.id, fb ? fb->base.id : -1);
11642
11643         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11644                          plane->base.id, was_visible, visible,
11645                          turn_off, turn_on, mode_changed);
11646
11647         if (turn_on) {
11648                 intel_crtc->atomic.update_wm_pre = true;
11649                 /* must disable cxsr around plane enable/disable */
11650                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11651                         intel_crtc->atomic.disable_cxsr = true;
11652                         /* to potentially re-enable cxsr */
11653                         intel_crtc->atomic.wait_vblank = true;
11654                         intel_crtc->atomic.update_wm_post = true;
11655                 }
11656         } else if (turn_off) {
11657                 intel_crtc->atomic.update_wm_post = true;
11658                 /* must disable cxsr around plane enable/disable */
11659                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11660                         if (is_crtc_enabled)
11661                                 intel_crtc->atomic.wait_vblank = true;
11662                         intel_crtc->atomic.disable_cxsr = true;
11663                 }
11664         } else if (intel_wm_need_update(plane, plane_state)) {
11665                 intel_crtc->atomic.update_wm_pre = true;
11666         }
11667
11668         if (visible || was_visible)
11669                 intel_crtc->atomic.fb_bits |=
11670                         to_intel_plane(plane)->frontbuffer_bit;
11671
11672         switch (plane->type) {
11673         case DRM_PLANE_TYPE_PRIMARY:
11674                 intel_crtc->atomic.wait_for_flips = true;
11675                 intel_crtc->atomic.pre_disable_primary = turn_off;
11676                 intel_crtc->atomic.post_enable_primary = turn_on;
11677
11678                 if (turn_off) {
11679                         /*
11680                          * FIXME: Actually if we will still have any other
11681                          * plane enabled on the pipe we could let IPS enabled
11682                          * still, but for now lets consider that when we make
11683                          * primary invisible by setting DSPCNTR to 0 on
11684                          * update_primary_plane function IPS needs to be
11685                          * disable.
11686                          */
11687                         intel_crtc->atomic.disable_ips = true;
11688
11689                         intel_crtc->atomic.disable_fbc = true;
11690                 }
11691
11692                 /*
11693                  * FBC does not work on some platforms for rotated
11694                  * planes, so disable it when rotation is not 0 and
11695                  * update it when rotation is set back to 0.
11696                  *
11697                  * FIXME: This is redundant with the fbc update done in
11698                  * the primary plane enable function except that that
11699                  * one is done too late. We eventually need to unify
11700                  * this.
11701                  */
11702
11703                 if (visible &&
11704                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11705                     dev_priv->fbc.crtc == intel_crtc &&
11706                     plane_state->rotation != BIT(DRM_ROTATE_0))
11707                         intel_crtc->atomic.disable_fbc = true;
11708
11709                 /*
11710                  * BDW signals flip done immediately if the plane
11711                  * is disabled, even if the plane enable is already
11712                  * armed to occur at the next vblank :(
11713                  */
11714                 if (turn_on && IS_BROADWELL(dev))
11715                         intel_crtc->atomic.wait_vblank = true;
11716
11717                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11718                 break;
11719         case DRM_PLANE_TYPE_CURSOR:
11720                 break;
11721         case DRM_PLANE_TYPE_OVERLAY:
11722                 if (turn_off && !mode_changed) {
11723                         intel_crtc->atomic.wait_vblank = true;
11724                         intel_crtc->atomic.update_sprite_watermarks |=
11725                                 1 << i;
11726                 }
11727         }
11728         return 0;
11729 }
11730
11731 static bool encoders_cloneable(const struct intel_encoder *a,
11732                                const struct intel_encoder *b)
11733 {
11734         /* masks could be asymmetric, so check both ways */
11735         return a == b || (a->cloneable & (1 << b->type) &&
11736                           b->cloneable & (1 << a->type));
11737 }
11738
11739 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11740                                          struct intel_crtc *crtc,
11741                                          struct intel_encoder *encoder)
11742 {
11743         struct intel_encoder *source_encoder;
11744         struct drm_connector *connector;
11745         struct drm_connector_state *connector_state;
11746         int i;
11747
11748         for_each_connector_in_state(state, connector, connector_state, i) {
11749                 if (connector_state->crtc != &crtc->base)
11750                         continue;
11751
11752                 source_encoder =
11753                         to_intel_encoder(connector_state->best_encoder);
11754                 if (!encoders_cloneable(encoder, source_encoder))
11755                         return false;
11756         }
11757
11758         return true;
11759 }
11760
11761 static bool check_encoder_cloning(struct drm_atomic_state *state,
11762                                   struct intel_crtc *crtc)
11763 {
11764         struct intel_encoder *encoder;
11765         struct drm_connector *connector;
11766         struct drm_connector_state *connector_state;
11767         int i;
11768
11769         for_each_connector_in_state(state, connector, connector_state, i) {
11770                 if (connector_state->crtc != &crtc->base)
11771                         continue;
11772
11773                 encoder = to_intel_encoder(connector_state->best_encoder);
11774                 if (!check_single_encoder_cloning(state, crtc, encoder))
11775                         return false;
11776         }
11777
11778         return true;
11779 }
11780
11781 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11782                                    struct drm_crtc_state *crtc_state)
11783 {
11784         struct drm_device *dev = crtc->dev;
11785         struct drm_i915_private *dev_priv = dev->dev_private;
11786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11787         struct intel_crtc_state *pipe_config =
11788                 to_intel_crtc_state(crtc_state);
11789         struct drm_atomic_state *state = crtc_state->state;
11790         int ret;
11791         bool mode_changed = needs_modeset(crtc_state);
11792
11793         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11794                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11795                 return -EINVAL;
11796         }
11797
11798         if (mode_changed && !crtc_state->active)
11799                 intel_crtc->atomic.update_wm_post = true;
11800
11801         if (mode_changed && crtc_state->enable &&
11802             dev_priv->display.crtc_compute_clock &&
11803             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11804                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11805                                                            pipe_config);
11806                 if (ret)
11807                         return ret;
11808         }
11809
11810         ret = 0;
11811         if (INTEL_INFO(dev)->gen >= 9) {
11812                 if (mode_changed)
11813                         ret = skl_update_scaler_crtc(pipe_config);
11814
11815                 if (!ret)
11816                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11817                                                          pipe_config);
11818         }
11819
11820         return ret;
11821 }
11822
11823 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11824         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11825         .load_lut = intel_crtc_load_lut,
11826         .atomic_begin = intel_begin_crtc_commit,
11827         .atomic_flush = intel_finish_crtc_commit,
11828         .atomic_check = intel_crtc_atomic_check,
11829 };
11830
11831 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11832 {
11833         struct intel_connector *connector;
11834
11835         for_each_intel_connector(dev, connector) {
11836                 if (connector->base.encoder) {
11837                         connector->base.state->best_encoder =
11838                                 connector->base.encoder;
11839                         connector->base.state->crtc =
11840                                 connector->base.encoder->crtc;
11841                 } else {
11842                         connector->base.state->best_encoder = NULL;
11843                         connector->base.state->crtc = NULL;
11844                 }
11845         }
11846 }
11847
11848 static void
11849 connected_sink_compute_bpp(struct intel_connector *connector,
11850                            struct intel_crtc_state *pipe_config)
11851 {
11852         int bpp = pipe_config->pipe_bpp;
11853
11854         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11855                 connector->base.base.id,
11856                 connector->base.name);
11857
11858         /* Don't use an invalid EDID bpc value */
11859         if (connector->base.display_info.bpc &&
11860             connector->base.display_info.bpc * 3 < bpp) {
11861                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11862                               bpp, connector->base.display_info.bpc*3);
11863                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11864         }
11865
11866         /* Clamp bpp to 8 on screens without EDID 1.4 */
11867         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11868                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11869                               bpp);
11870                 pipe_config->pipe_bpp = 24;
11871         }
11872 }
11873
11874 static int
11875 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11876                           struct intel_crtc_state *pipe_config)
11877 {
11878         struct drm_device *dev = crtc->base.dev;
11879         struct drm_atomic_state *state;
11880         struct drm_connector *connector;
11881         struct drm_connector_state *connector_state;
11882         int bpp, i;
11883
11884         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11885                 bpp = 10*3;
11886         else if (INTEL_INFO(dev)->gen >= 5)
11887                 bpp = 12*3;
11888         else
11889                 bpp = 8*3;
11890
11891
11892         pipe_config->pipe_bpp = bpp;
11893
11894         state = pipe_config->base.state;
11895
11896         /* Clamp display bpp to EDID value */
11897         for_each_connector_in_state(state, connector, connector_state, i) {
11898                 if (connector_state->crtc != &crtc->base)
11899                         continue;
11900
11901                 connected_sink_compute_bpp(to_intel_connector(connector),
11902                                            pipe_config);
11903         }
11904
11905         return bpp;
11906 }
11907
11908 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11909 {
11910         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11911                         "type: 0x%x flags: 0x%x\n",
11912                 mode->crtc_clock,
11913                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11914                 mode->crtc_hsync_end, mode->crtc_htotal,
11915                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11916                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11917 }
11918
11919 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11920                                    struct intel_crtc_state *pipe_config,
11921                                    const char *context)
11922 {
11923         struct drm_device *dev = crtc->base.dev;
11924         struct drm_plane *plane;
11925         struct intel_plane *intel_plane;
11926         struct intel_plane_state *state;
11927         struct drm_framebuffer *fb;
11928
11929         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11930                       context, pipe_config, pipe_name(crtc->pipe));
11931
11932         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11933         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11934                       pipe_config->pipe_bpp, pipe_config->dither);
11935         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11936                       pipe_config->has_pch_encoder,
11937                       pipe_config->fdi_lanes,
11938                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11939                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11940                       pipe_config->fdi_m_n.tu);
11941         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11942                       pipe_config->has_dp_encoder,
11943                       pipe_config->lane_count,
11944                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11945                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11946                       pipe_config->dp_m_n.tu);
11947
11948         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11949                       pipe_config->has_dp_encoder,
11950                       pipe_config->lane_count,
11951                       pipe_config->dp_m2_n2.gmch_m,
11952                       pipe_config->dp_m2_n2.gmch_n,
11953                       pipe_config->dp_m2_n2.link_m,
11954                       pipe_config->dp_m2_n2.link_n,
11955                       pipe_config->dp_m2_n2.tu);
11956
11957         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11958                       pipe_config->has_audio,
11959                       pipe_config->has_infoframe);
11960
11961         DRM_DEBUG_KMS("requested mode:\n");
11962         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11963         DRM_DEBUG_KMS("adjusted mode:\n");
11964         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11965         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11966         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11967         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11968                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11969         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11970                       crtc->num_scalers,
11971                       pipe_config->scaler_state.scaler_users,
11972                       pipe_config->scaler_state.scaler_id);
11973         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11974                       pipe_config->gmch_pfit.control,
11975                       pipe_config->gmch_pfit.pgm_ratios,
11976                       pipe_config->gmch_pfit.lvds_border_bits);
11977         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11978                       pipe_config->pch_pfit.pos,
11979                       pipe_config->pch_pfit.size,
11980                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11981         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11982         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11983
11984         if (IS_BROXTON(dev)) {
11985                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11986                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11987                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11988                               pipe_config->ddi_pll_sel,
11989                               pipe_config->dpll_hw_state.ebb0,
11990                               pipe_config->dpll_hw_state.ebb4,
11991                               pipe_config->dpll_hw_state.pll0,
11992                               pipe_config->dpll_hw_state.pll1,
11993                               pipe_config->dpll_hw_state.pll2,
11994                               pipe_config->dpll_hw_state.pll3,
11995                               pipe_config->dpll_hw_state.pll6,
11996                               pipe_config->dpll_hw_state.pll8,
11997                               pipe_config->dpll_hw_state.pll9,
11998                               pipe_config->dpll_hw_state.pll10,
11999                               pipe_config->dpll_hw_state.pcsdw12);
12000         } else if (IS_SKYLAKE(dev)) {
12001                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12002                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12003                               pipe_config->ddi_pll_sel,
12004                               pipe_config->dpll_hw_state.ctrl1,
12005                               pipe_config->dpll_hw_state.cfgcr1,
12006                               pipe_config->dpll_hw_state.cfgcr2);
12007         } else if (HAS_DDI(dev)) {
12008                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12009                               pipe_config->ddi_pll_sel,
12010                               pipe_config->dpll_hw_state.wrpll);
12011         } else {
12012                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12013                               "fp0: 0x%x, fp1: 0x%x\n",
12014                               pipe_config->dpll_hw_state.dpll,
12015                               pipe_config->dpll_hw_state.dpll_md,
12016                               pipe_config->dpll_hw_state.fp0,
12017                               pipe_config->dpll_hw_state.fp1);
12018         }
12019
12020         DRM_DEBUG_KMS("planes on this crtc\n");
12021         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12022                 intel_plane = to_intel_plane(plane);
12023                 if (intel_plane->pipe != crtc->pipe)
12024                         continue;
12025
12026                 state = to_intel_plane_state(plane->state);
12027                 fb = state->base.fb;
12028                 if (!fb) {
12029                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12030                                 "disabled, scaler_id = %d\n",
12031                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12032                                 plane->base.id, intel_plane->pipe,
12033                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12034                                 drm_plane_index(plane), state->scaler_id);
12035                         continue;
12036                 }
12037
12038                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12039                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12040                         plane->base.id, intel_plane->pipe,
12041                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12042                         drm_plane_index(plane));
12043                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12044                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12045                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12046                         state->scaler_id,
12047                         state->src.x1 >> 16, state->src.y1 >> 16,
12048                         drm_rect_width(&state->src) >> 16,
12049                         drm_rect_height(&state->src) >> 16,
12050                         state->dst.x1, state->dst.y1,
12051                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12052         }
12053 }
12054
12055 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12056 {
12057         struct drm_device *dev = state->dev;
12058         struct intel_encoder *encoder;
12059         struct drm_connector *connector;
12060         struct drm_connector_state *connector_state;
12061         unsigned int used_ports = 0;
12062         int i;
12063
12064         /*
12065          * Walk the connector list instead of the encoder
12066          * list to detect the problem on ddi platforms
12067          * where there's just one encoder per digital port.
12068          */
12069         for_each_connector_in_state(state, connector, connector_state, i) {
12070                 if (!connector_state->best_encoder)
12071                         continue;
12072
12073                 encoder = to_intel_encoder(connector_state->best_encoder);
12074
12075                 WARN_ON(!connector_state->crtc);
12076
12077                 switch (encoder->type) {
12078                         unsigned int port_mask;
12079                 case INTEL_OUTPUT_UNKNOWN:
12080                         if (WARN_ON(!HAS_DDI(dev)))
12081                                 break;
12082                 case INTEL_OUTPUT_DISPLAYPORT:
12083                 case INTEL_OUTPUT_HDMI:
12084                 case INTEL_OUTPUT_EDP:
12085                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12086
12087                         /* the same port mustn't appear more than once */
12088                         if (used_ports & port_mask)
12089                                 return false;
12090
12091                         used_ports |= port_mask;
12092                 default:
12093                         break;
12094                 }
12095         }
12096
12097         return true;
12098 }
12099
12100 static void
12101 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12102 {
12103         struct drm_crtc_state tmp_state;
12104         struct intel_crtc_scaler_state scaler_state;
12105         struct intel_dpll_hw_state dpll_hw_state;
12106         enum intel_dpll_id shared_dpll;
12107         uint32_t ddi_pll_sel;
12108         bool force_thru;
12109
12110         /* FIXME: before the switch to atomic started, a new pipe_config was
12111          * kzalloc'd. Code that depends on any field being zero should be
12112          * fixed, so that the crtc_state can be safely duplicated. For now,
12113          * only fields that are know to not cause problems are preserved. */
12114
12115         tmp_state = crtc_state->base;
12116         scaler_state = crtc_state->scaler_state;
12117         shared_dpll = crtc_state->shared_dpll;
12118         dpll_hw_state = crtc_state->dpll_hw_state;
12119         ddi_pll_sel = crtc_state->ddi_pll_sel;
12120         force_thru = crtc_state->pch_pfit.force_thru;
12121
12122         memset(crtc_state, 0, sizeof *crtc_state);
12123
12124         crtc_state->base = tmp_state;
12125         crtc_state->scaler_state = scaler_state;
12126         crtc_state->shared_dpll = shared_dpll;
12127         crtc_state->dpll_hw_state = dpll_hw_state;
12128         crtc_state->ddi_pll_sel = ddi_pll_sel;
12129         crtc_state->pch_pfit.force_thru = force_thru;
12130 }
12131
12132 static int
12133 intel_modeset_pipe_config(struct drm_crtc *crtc,
12134                           struct intel_crtc_state *pipe_config)
12135 {
12136         struct drm_atomic_state *state = pipe_config->base.state;
12137         struct intel_encoder *encoder;
12138         struct drm_connector *connector;
12139         struct drm_connector_state *connector_state;
12140         int base_bpp, ret = -EINVAL;
12141         int i;
12142         bool retry = true;
12143
12144         clear_intel_crtc_state(pipe_config);
12145
12146         pipe_config->cpu_transcoder =
12147                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12148
12149         /*
12150          * Sanitize sync polarity flags based on requested ones. If neither
12151          * positive or negative polarity is requested, treat this as meaning
12152          * negative polarity.
12153          */
12154         if (!(pipe_config->base.adjusted_mode.flags &
12155               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12156                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12157
12158         if (!(pipe_config->base.adjusted_mode.flags &
12159               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12160                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12161
12162         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12163                                              pipe_config);
12164         if (base_bpp < 0)
12165                 goto fail;
12166
12167         /*
12168          * Determine the real pipe dimensions. Note that stereo modes can
12169          * increase the actual pipe size due to the frame doubling and
12170          * insertion of additional space for blanks between the frame. This
12171          * is stored in the crtc timings. We use the requested mode to do this
12172          * computation to clearly distinguish it from the adjusted mode, which
12173          * can be changed by the connectors in the below retry loop.
12174          */
12175         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12176                                &pipe_config->pipe_src_w,
12177                                &pipe_config->pipe_src_h);
12178
12179 encoder_retry:
12180         /* Ensure the port clock defaults are reset when retrying. */
12181         pipe_config->port_clock = 0;
12182         pipe_config->pixel_multiplier = 1;
12183
12184         /* Fill in default crtc timings, allow encoders to overwrite them. */
12185         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12186                               CRTC_STEREO_DOUBLE);
12187
12188         /* Pass our mode to the connectors and the CRTC to give them a chance to
12189          * adjust it according to limitations or connector properties, and also
12190          * a chance to reject the mode entirely.
12191          */
12192         for_each_connector_in_state(state, connector, connector_state, i) {
12193                 if (connector_state->crtc != crtc)
12194                         continue;
12195
12196                 encoder = to_intel_encoder(connector_state->best_encoder);
12197
12198                 if (!(encoder->compute_config(encoder, pipe_config))) {
12199                         DRM_DEBUG_KMS("Encoder config failure\n");
12200                         goto fail;
12201                 }
12202         }
12203
12204         /* Set default port clock if not overwritten by the encoder. Needs to be
12205          * done afterwards in case the encoder adjusts the mode. */
12206         if (!pipe_config->port_clock)
12207                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12208                         * pipe_config->pixel_multiplier;
12209
12210         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12211         if (ret < 0) {
12212                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12213                 goto fail;
12214         }
12215
12216         if (ret == RETRY) {
12217                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12218                         ret = -EINVAL;
12219                         goto fail;
12220                 }
12221
12222                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12223                 retry = false;
12224                 goto encoder_retry;
12225         }
12226
12227         /* Dithering seems to not pass-through bits correctly when it should, so
12228          * only enable it on 6bpc panels. */
12229         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12230         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12231                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12232
12233 fail:
12234         return ret;
12235 }
12236
12237 static void
12238 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12239 {
12240         struct drm_crtc *crtc;
12241         struct drm_crtc_state *crtc_state;
12242         int i;
12243
12244         /* Double check state. */
12245         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12246                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12247
12248                 /* Update hwmode for vblank functions */
12249                 if (crtc->state->active)
12250                         crtc->hwmode = crtc->state->adjusted_mode;
12251                 else
12252                         crtc->hwmode.crtc_clock = 0;
12253         }
12254 }
12255
12256 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12257 {
12258         int diff;
12259
12260         if (clock1 == clock2)
12261                 return true;
12262
12263         if (!clock1 || !clock2)
12264                 return false;
12265
12266         diff = abs(clock1 - clock2);
12267
12268         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12269                 return true;
12270
12271         return false;
12272 }
12273
12274 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12275         list_for_each_entry((intel_crtc), \
12276                             &(dev)->mode_config.crtc_list, \
12277                             base.head) \
12278                 if (mask & (1 <<(intel_crtc)->pipe))
12279
12280 static bool
12281 intel_compare_m_n(unsigned int m, unsigned int n,
12282                   unsigned int m2, unsigned int n2,
12283                   bool exact)
12284 {
12285         if (m == m2 && n == n2)
12286                 return true;
12287
12288         if (exact || !m || !n || !m2 || !n2)
12289                 return false;
12290
12291         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12292
12293         if (m > m2) {
12294                 while (m > m2) {
12295                         m2 <<= 1;
12296                         n2 <<= 1;
12297                 }
12298         } else if (m < m2) {
12299                 while (m < m2) {
12300                         m <<= 1;
12301                         n <<= 1;
12302                 }
12303         }
12304
12305         return m == m2 && n == n2;
12306 }
12307
12308 static bool
12309 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12310                        struct intel_link_m_n *m2_n2,
12311                        bool adjust)
12312 {
12313         if (m_n->tu == m2_n2->tu &&
12314             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12315                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12316             intel_compare_m_n(m_n->link_m, m_n->link_n,
12317                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12318                 if (adjust)
12319                         *m2_n2 = *m_n;
12320
12321                 return true;
12322         }
12323
12324         return false;
12325 }
12326
12327 static bool
12328 intel_pipe_config_compare(struct drm_device *dev,
12329                           struct intel_crtc_state *current_config,
12330                           struct intel_crtc_state *pipe_config,
12331                           bool adjust)
12332 {
12333         bool ret = true;
12334
12335 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12336         do { \
12337                 if (!adjust) \
12338                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12339                 else \
12340                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12341         } while (0)
12342
12343 #define PIPE_CONF_CHECK_X(name) \
12344         if (current_config->name != pipe_config->name) { \
12345                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12346                           "(expected 0x%08x, found 0x%08x)\n", \
12347                           current_config->name, \
12348                           pipe_config->name); \
12349                 ret = false; \
12350         }
12351
12352 #define PIPE_CONF_CHECK_I(name) \
12353         if (current_config->name != pipe_config->name) { \
12354                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12355                           "(expected %i, found %i)\n", \
12356                           current_config->name, \
12357                           pipe_config->name); \
12358                 ret = false; \
12359         }
12360
12361 #define PIPE_CONF_CHECK_M_N(name) \
12362         if (!intel_compare_link_m_n(&current_config->name, \
12363                                     &pipe_config->name,\
12364                                     adjust)) { \
12365                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12366                           "(expected tu %i gmch %i/%i link %i/%i, " \
12367                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12368                           current_config->name.tu, \
12369                           current_config->name.gmch_m, \
12370                           current_config->name.gmch_n, \
12371                           current_config->name.link_m, \
12372                           current_config->name.link_n, \
12373                           pipe_config->name.tu, \
12374                           pipe_config->name.gmch_m, \
12375                           pipe_config->name.gmch_n, \
12376                           pipe_config->name.link_m, \
12377                           pipe_config->name.link_n); \
12378                 ret = false; \
12379         }
12380
12381 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12382         if (!intel_compare_link_m_n(&current_config->name, \
12383                                     &pipe_config->name, adjust) && \
12384             !intel_compare_link_m_n(&current_config->alt_name, \
12385                                     &pipe_config->name, adjust)) { \
12386                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12387                           "(expected tu %i gmch %i/%i link %i/%i, " \
12388                           "or tu %i gmch %i/%i link %i/%i, " \
12389                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12390                           current_config->name.tu, \
12391                           current_config->name.gmch_m, \
12392                           current_config->name.gmch_n, \
12393                           current_config->name.link_m, \
12394                           current_config->name.link_n, \
12395                           current_config->alt_name.tu, \
12396                           current_config->alt_name.gmch_m, \
12397                           current_config->alt_name.gmch_n, \
12398                           current_config->alt_name.link_m, \
12399                           current_config->alt_name.link_n, \
12400                           pipe_config->name.tu, \
12401                           pipe_config->name.gmch_m, \
12402                           pipe_config->name.gmch_n, \
12403                           pipe_config->name.link_m, \
12404                           pipe_config->name.link_n); \
12405                 ret = false; \
12406         }
12407
12408 /* This is required for BDW+ where there is only one set of registers for
12409  * switching between high and low RR.
12410  * This macro can be used whenever a comparison has to be made between one
12411  * hw state and multiple sw state variables.
12412  */
12413 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12414         if ((current_config->name != pipe_config->name) && \
12415                 (current_config->alt_name != pipe_config->name)) { \
12416                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12417                                   "(expected %i or %i, found %i)\n", \
12418                                   current_config->name, \
12419                                   current_config->alt_name, \
12420                                   pipe_config->name); \
12421                         ret = false; \
12422         }
12423
12424 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12425         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12426                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12427                           "(expected %i, found %i)\n", \
12428                           current_config->name & (mask), \
12429                           pipe_config->name & (mask)); \
12430                 ret = false; \
12431         }
12432
12433 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12434         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12435                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12436                           "(expected %i, found %i)\n", \
12437                           current_config->name, \
12438                           pipe_config->name); \
12439                 ret = false; \
12440         }
12441
12442 #define PIPE_CONF_QUIRK(quirk)  \
12443         ((current_config->quirks | pipe_config->quirks) & (quirk))
12444
12445         PIPE_CONF_CHECK_I(cpu_transcoder);
12446
12447         PIPE_CONF_CHECK_I(has_pch_encoder);
12448         PIPE_CONF_CHECK_I(fdi_lanes);
12449         PIPE_CONF_CHECK_M_N(fdi_m_n);
12450
12451         PIPE_CONF_CHECK_I(has_dp_encoder);
12452         PIPE_CONF_CHECK_I(lane_count);
12453
12454         if (INTEL_INFO(dev)->gen < 8) {
12455                 PIPE_CONF_CHECK_M_N(dp_m_n);
12456
12457                 PIPE_CONF_CHECK_I(has_drrs);
12458                 if (current_config->has_drrs)
12459                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12460         } else
12461                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12462
12463         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12464         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12465         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12466         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12467         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12468         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12469
12470         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12471         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12472         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12473         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12474         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12475         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12476
12477         PIPE_CONF_CHECK_I(pixel_multiplier);
12478         PIPE_CONF_CHECK_I(has_hdmi_sink);
12479         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12480             IS_VALLEYVIEW(dev))
12481                 PIPE_CONF_CHECK_I(limited_color_range);
12482         PIPE_CONF_CHECK_I(has_infoframe);
12483
12484         PIPE_CONF_CHECK_I(has_audio);
12485
12486         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12487                               DRM_MODE_FLAG_INTERLACE);
12488
12489         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12490                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12491                                       DRM_MODE_FLAG_PHSYNC);
12492                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12493                                       DRM_MODE_FLAG_NHSYNC);
12494                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12495                                       DRM_MODE_FLAG_PVSYNC);
12496                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12497                                       DRM_MODE_FLAG_NVSYNC);
12498         }
12499
12500         PIPE_CONF_CHECK_X(gmch_pfit.control);
12501         /* pfit ratios are autocomputed by the hw on gen4+ */
12502         if (INTEL_INFO(dev)->gen < 4)
12503                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12504         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12505
12506         if (!adjust) {
12507                 PIPE_CONF_CHECK_I(pipe_src_w);
12508                 PIPE_CONF_CHECK_I(pipe_src_h);
12509
12510                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12511                 if (current_config->pch_pfit.enabled) {
12512                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12513                         PIPE_CONF_CHECK_X(pch_pfit.size);
12514                 }
12515
12516                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12517         }
12518
12519         /* BDW+ don't expose a synchronous way to read the state */
12520         if (IS_HASWELL(dev))
12521                 PIPE_CONF_CHECK_I(ips_enabled);
12522
12523         PIPE_CONF_CHECK_I(double_wide);
12524
12525         PIPE_CONF_CHECK_X(ddi_pll_sel);
12526
12527         PIPE_CONF_CHECK_I(shared_dpll);
12528         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12529         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12530         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12531         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12532         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12533         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12534         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12535         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12536
12537         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12538                 PIPE_CONF_CHECK_I(pipe_bpp);
12539
12540         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12541         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12542
12543 #undef PIPE_CONF_CHECK_X
12544 #undef PIPE_CONF_CHECK_I
12545 #undef PIPE_CONF_CHECK_I_ALT
12546 #undef PIPE_CONF_CHECK_FLAGS
12547 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12548 #undef PIPE_CONF_QUIRK
12549 #undef INTEL_ERR_OR_DBG_KMS
12550
12551         return ret;
12552 }
12553
12554 static void check_wm_state(struct drm_device *dev)
12555 {
12556         struct drm_i915_private *dev_priv = dev->dev_private;
12557         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12558         struct intel_crtc *intel_crtc;
12559         int plane;
12560
12561         if (INTEL_INFO(dev)->gen < 9)
12562                 return;
12563
12564         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12565         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12566
12567         for_each_intel_crtc(dev, intel_crtc) {
12568                 struct skl_ddb_entry *hw_entry, *sw_entry;
12569                 const enum pipe pipe = intel_crtc->pipe;
12570
12571                 if (!intel_crtc->active)
12572                         continue;
12573
12574                 /* planes */
12575                 for_each_plane(dev_priv, pipe, plane) {
12576                         hw_entry = &hw_ddb.plane[pipe][plane];
12577                         sw_entry = &sw_ddb->plane[pipe][plane];
12578
12579                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12580                                 continue;
12581
12582                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12583                                   "(expected (%u,%u), found (%u,%u))\n",
12584                                   pipe_name(pipe), plane + 1,
12585                                   sw_entry->start, sw_entry->end,
12586                                   hw_entry->start, hw_entry->end);
12587                 }
12588
12589                 /* cursor */
12590                 hw_entry = &hw_ddb.cursor[pipe];
12591                 sw_entry = &sw_ddb->cursor[pipe];
12592
12593                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12594                         continue;
12595
12596                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12597                           "(expected (%u,%u), found (%u,%u))\n",
12598                           pipe_name(pipe),
12599                           sw_entry->start, sw_entry->end,
12600                           hw_entry->start, hw_entry->end);
12601         }
12602 }
12603
12604 static void
12605 check_connector_state(struct drm_device *dev,
12606                       struct drm_atomic_state *old_state)
12607 {
12608         struct drm_connector_state *old_conn_state;
12609         struct drm_connector *connector;
12610         int i;
12611
12612         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12613                 struct drm_encoder *encoder = connector->encoder;
12614                 struct drm_connector_state *state = connector->state;
12615
12616                 /* This also checks the encoder/connector hw state with the
12617                  * ->get_hw_state callbacks. */
12618                 intel_connector_check_state(to_intel_connector(connector));
12619
12620                 I915_STATE_WARN(state->best_encoder != encoder,
12621                      "connector's atomic encoder doesn't match legacy encoder\n");
12622         }
12623 }
12624
12625 static void
12626 check_encoder_state(struct drm_device *dev)
12627 {
12628         struct intel_encoder *encoder;
12629         struct intel_connector *connector;
12630
12631         for_each_intel_encoder(dev, encoder) {
12632                 bool enabled = false;
12633                 enum pipe pipe;
12634
12635                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12636                               encoder->base.base.id,
12637                               encoder->base.name);
12638
12639                 for_each_intel_connector(dev, connector) {
12640                         if (connector->base.state->best_encoder != &encoder->base)
12641                                 continue;
12642                         enabled = true;
12643
12644                         I915_STATE_WARN(connector->base.state->crtc !=
12645                                         encoder->base.crtc,
12646                              "connector's crtc doesn't match encoder crtc\n");
12647                 }
12648
12649                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12650                      "encoder's enabled state mismatch "
12651                      "(expected %i, found %i)\n",
12652                      !!encoder->base.crtc, enabled);
12653
12654                 if (!encoder->base.crtc) {
12655                         bool active;
12656
12657                         active = encoder->get_hw_state(encoder, &pipe);
12658                         I915_STATE_WARN(active,
12659                              "encoder detached but still enabled on pipe %c.\n",
12660                              pipe_name(pipe));
12661                 }
12662         }
12663 }
12664
12665 static void
12666 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12667 {
12668         struct drm_i915_private *dev_priv = dev->dev_private;
12669         struct intel_encoder *encoder;
12670         struct drm_crtc_state *old_crtc_state;
12671         struct drm_crtc *crtc;
12672         int i;
12673
12674         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12675                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12676                 struct intel_crtc_state *pipe_config, *sw_config;
12677                 bool active;
12678
12679                 if (!needs_modeset(crtc->state) &&
12680                     !to_intel_crtc_state(crtc->state)->update_pipe)
12681                         continue;
12682
12683                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12684                 pipe_config = to_intel_crtc_state(old_crtc_state);
12685                 memset(pipe_config, 0, sizeof(*pipe_config));
12686                 pipe_config->base.crtc = crtc;
12687                 pipe_config->base.state = old_state;
12688
12689                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12690                               crtc->base.id);
12691
12692                 active = dev_priv->display.get_pipe_config(intel_crtc,
12693                                                            pipe_config);
12694
12695                 /* hw state is inconsistent with the pipe quirk */
12696                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12697                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12698                         active = crtc->state->active;
12699
12700                 I915_STATE_WARN(crtc->state->active != active,
12701                      "crtc active state doesn't match with hw state "
12702                      "(expected %i, found %i)\n", crtc->state->active, active);
12703
12704                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12705                      "transitional active state does not match atomic hw state "
12706                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12707
12708                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12709                         enum pipe pipe;
12710
12711                         active = encoder->get_hw_state(encoder, &pipe);
12712                         I915_STATE_WARN(active != crtc->state->active,
12713                                 "[ENCODER:%i] active %i with crtc active %i\n",
12714                                 encoder->base.base.id, active, crtc->state->active);
12715
12716                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12717                                         "Encoder connected to wrong pipe %c\n",
12718                                         pipe_name(pipe));
12719
12720                         if (active)
12721                                 encoder->get_config(encoder, pipe_config);
12722                 }
12723
12724                 if (!crtc->state->active)
12725                         continue;
12726
12727                 sw_config = to_intel_crtc_state(crtc->state);
12728                 if (!intel_pipe_config_compare(dev, sw_config,
12729                                                pipe_config, false)) {
12730                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12731                         intel_dump_pipe_config(intel_crtc, pipe_config,
12732                                                "[hw state]");
12733                         intel_dump_pipe_config(intel_crtc, sw_config,
12734                                                "[sw state]");
12735                 }
12736         }
12737 }
12738
12739 static void
12740 check_shared_dpll_state(struct drm_device *dev)
12741 {
12742         struct drm_i915_private *dev_priv = dev->dev_private;
12743         struct intel_crtc *crtc;
12744         struct intel_dpll_hw_state dpll_hw_state;
12745         int i;
12746
12747         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12748                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12749                 int enabled_crtcs = 0, active_crtcs = 0;
12750                 bool active;
12751
12752                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12753
12754                 DRM_DEBUG_KMS("%s\n", pll->name);
12755
12756                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12757
12758                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12759                      "more active pll users than references: %i vs %i\n",
12760                      pll->active, hweight32(pll->config.crtc_mask));
12761                 I915_STATE_WARN(pll->active && !pll->on,
12762                      "pll in active use but not on in sw tracking\n");
12763                 I915_STATE_WARN(pll->on && !pll->active,
12764                      "pll in on but not on in use in sw tracking\n");
12765                 I915_STATE_WARN(pll->on != active,
12766                      "pll on state mismatch (expected %i, found %i)\n",
12767                      pll->on, active);
12768
12769                 for_each_intel_crtc(dev, crtc) {
12770                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12771                                 enabled_crtcs++;
12772                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12773                                 active_crtcs++;
12774                 }
12775                 I915_STATE_WARN(pll->active != active_crtcs,
12776                      "pll active crtcs mismatch (expected %i, found %i)\n",
12777                      pll->active, active_crtcs);
12778                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12779                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12780                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12781
12782                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12783                                        sizeof(dpll_hw_state)),
12784                      "pll hw state mismatch\n");
12785         }
12786 }
12787
12788 static void
12789 intel_modeset_check_state(struct drm_device *dev,
12790                           struct drm_atomic_state *old_state)
12791 {
12792         check_wm_state(dev);
12793         check_connector_state(dev, old_state);
12794         check_encoder_state(dev);
12795         check_crtc_state(dev, old_state);
12796         check_shared_dpll_state(dev);
12797 }
12798
12799 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12800                                      int dotclock)
12801 {
12802         /*
12803          * FDI already provided one idea for the dotclock.
12804          * Yell if the encoder disagrees.
12805          */
12806         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12807              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12808              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12809 }
12810
12811 static void update_scanline_offset(struct intel_crtc *crtc)
12812 {
12813         struct drm_device *dev = crtc->base.dev;
12814
12815         /*
12816          * The scanline counter increments at the leading edge of hsync.
12817          *
12818          * On most platforms it starts counting from vtotal-1 on the
12819          * first active line. That means the scanline counter value is
12820          * always one less than what we would expect. Ie. just after
12821          * start of vblank, which also occurs at start of hsync (on the
12822          * last active line), the scanline counter will read vblank_start-1.
12823          *
12824          * On gen2 the scanline counter starts counting from 1 instead
12825          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12826          * to keep the value positive), instead of adding one.
12827          *
12828          * On HSW+ the behaviour of the scanline counter depends on the output
12829          * type. For DP ports it behaves like most other platforms, but on HDMI
12830          * there's an extra 1 line difference. So we need to add two instead of
12831          * one to the value.
12832          */
12833         if (IS_GEN2(dev)) {
12834                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12835                 int vtotal;
12836
12837                 vtotal = adjusted_mode->crtc_vtotal;
12838                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12839                         vtotal /= 2;
12840
12841                 crtc->scanline_offset = vtotal - 1;
12842         } else if (HAS_DDI(dev) &&
12843                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12844                 crtc->scanline_offset = 2;
12845         } else
12846                 crtc->scanline_offset = 1;
12847 }
12848
12849 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12850 {
12851         struct drm_device *dev = state->dev;
12852         struct drm_i915_private *dev_priv = to_i915(dev);
12853         struct intel_shared_dpll_config *shared_dpll = NULL;
12854         struct intel_crtc *intel_crtc;
12855         struct intel_crtc_state *intel_crtc_state;
12856         struct drm_crtc *crtc;
12857         struct drm_crtc_state *crtc_state;
12858         int i;
12859
12860         if (!dev_priv->display.crtc_compute_clock)
12861                 return;
12862
12863         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12864                 int dpll;
12865
12866                 intel_crtc = to_intel_crtc(crtc);
12867                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12868                 dpll = intel_crtc_state->shared_dpll;
12869
12870                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12871                         continue;
12872
12873                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12874
12875                 if (!shared_dpll)
12876                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12877
12878                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12879         }
12880 }
12881
12882 /*
12883  * This implements the workaround described in the "notes" section of the mode
12884  * set sequence documentation. When going from no pipes or single pipe to
12885  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12886  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12887  */
12888 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12889 {
12890         struct drm_crtc_state *crtc_state;
12891         struct intel_crtc *intel_crtc;
12892         struct drm_crtc *crtc;
12893         struct intel_crtc_state *first_crtc_state = NULL;
12894         struct intel_crtc_state *other_crtc_state = NULL;
12895         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12896         int i;
12897
12898         /* look at all crtc's that are going to be enabled in during modeset */
12899         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12900                 intel_crtc = to_intel_crtc(crtc);
12901
12902                 if (!crtc_state->active || !needs_modeset(crtc_state))
12903                         continue;
12904
12905                 if (first_crtc_state) {
12906                         other_crtc_state = to_intel_crtc_state(crtc_state);
12907                         break;
12908                 } else {
12909                         first_crtc_state = to_intel_crtc_state(crtc_state);
12910                         first_pipe = intel_crtc->pipe;
12911                 }
12912         }
12913
12914         /* No workaround needed? */
12915         if (!first_crtc_state)
12916                 return 0;
12917
12918         /* w/a possibly needed, check how many crtc's are already enabled. */
12919         for_each_intel_crtc(state->dev, intel_crtc) {
12920                 struct intel_crtc_state *pipe_config;
12921
12922                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12923                 if (IS_ERR(pipe_config))
12924                         return PTR_ERR(pipe_config);
12925
12926                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12927
12928                 if (!pipe_config->base.active ||
12929                     needs_modeset(&pipe_config->base))
12930                         continue;
12931
12932                 /* 2 or more enabled crtcs means no need for w/a */
12933                 if (enabled_pipe != INVALID_PIPE)
12934                         return 0;
12935
12936                 enabled_pipe = intel_crtc->pipe;
12937         }
12938
12939         if (enabled_pipe != INVALID_PIPE)
12940                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12941         else if (other_crtc_state)
12942                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12943
12944         return 0;
12945 }
12946
12947 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12948 {
12949         struct drm_crtc *crtc;
12950         struct drm_crtc_state *crtc_state;
12951         int ret = 0;
12952
12953         /* add all active pipes to the state */
12954         for_each_crtc(state->dev, crtc) {
12955                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12956                 if (IS_ERR(crtc_state))
12957                         return PTR_ERR(crtc_state);
12958
12959                 if (!crtc_state->active || needs_modeset(crtc_state))
12960                         continue;
12961
12962                 crtc_state->mode_changed = true;
12963
12964                 ret = drm_atomic_add_affected_connectors(state, crtc);
12965                 if (ret)
12966                         break;
12967
12968                 ret = drm_atomic_add_affected_planes(state, crtc);
12969                 if (ret)
12970                         break;
12971         }
12972
12973         return ret;
12974 }
12975
12976 static int intel_modeset_checks(struct drm_atomic_state *state)
12977 {
12978         struct drm_device *dev = state->dev;
12979         struct drm_i915_private *dev_priv = dev->dev_private;
12980         int ret;
12981
12982         if (!check_digital_port_conflicts(state)) {
12983                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12984                 return -EINVAL;
12985         }
12986
12987         /*
12988          * See if the config requires any additional preparation, e.g.
12989          * to adjust global state with pipes off.  We need to do this
12990          * here so we can get the modeset_pipe updated config for the new
12991          * mode set on this crtc.  For other crtcs we need to use the
12992          * adjusted_mode bits in the crtc directly.
12993          */
12994         if (dev_priv->display.modeset_calc_cdclk) {
12995                 unsigned int cdclk;
12996
12997                 ret = dev_priv->display.modeset_calc_cdclk(state);
12998
12999                 cdclk = to_intel_atomic_state(state)->cdclk;
13000                 if (!ret && cdclk != dev_priv->cdclk_freq)
13001                         ret = intel_modeset_all_pipes(state);
13002
13003                 if (ret < 0)
13004                         return ret;
13005         } else
13006                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13007
13008         intel_modeset_clear_plls(state);
13009
13010         if (IS_HASWELL(dev))
13011                 return haswell_mode_set_planes_workaround(state);
13012
13013         return 0;
13014 }
13015
13016 /**
13017  * intel_atomic_check - validate state object
13018  * @dev: drm device
13019  * @state: state to validate
13020  */
13021 static int intel_atomic_check(struct drm_device *dev,
13022                               struct drm_atomic_state *state)
13023 {
13024         struct drm_crtc *crtc;
13025         struct drm_crtc_state *crtc_state;
13026         int ret, i;
13027         bool any_ms = false;
13028
13029         ret = drm_atomic_helper_check_modeset(dev, state);
13030         if (ret)
13031                 return ret;
13032
13033         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13034                 struct intel_crtc_state *pipe_config =
13035                         to_intel_crtc_state(crtc_state);
13036
13037                 /* Catch I915_MODE_FLAG_INHERITED */
13038                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13039                         crtc_state->mode_changed = true;
13040
13041                 if (!crtc_state->enable) {
13042                         if (needs_modeset(crtc_state))
13043                                 any_ms = true;
13044                         continue;
13045                 }
13046
13047                 if (!needs_modeset(crtc_state))
13048                         continue;
13049
13050                 /* FIXME: For only active_changed we shouldn't need to do any
13051                  * state recomputation at all. */
13052
13053                 ret = drm_atomic_add_affected_connectors(state, crtc);
13054                 if (ret)
13055                         return ret;
13056
13057                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13058                 if (ret)
13059                         return ret;
13060
13061                 if (intel_pipe_config_compare(state->dev,
13062                                         to_intel_crtc_state(crtc->state),
13063                                         pipe_config, true)) {
13064                         crtc_state->mode_changed = false;
13065                         to_intel_crtc_state(crtc_state)->update_pipe = true;
13066                 }
13067
13068                 if (needs_modeset(crtc_state)) {
13069                         any_ms = true;
13070
13071                         ret = drm_atomic_add_affected_planes(state, crtc);
13072                         if (ret)
13073                                 return ret;
13074                 }
13075
13076                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13077                                        needs_modeset(crtc_state) ?
13078                                        "[modeset]" : "[fastset]");
13079         }
13080
13081         if (any_ms) {
13082                 ret = intel_modeset_checks(state);
13083
13084                 if (ret)
13085                         return ret;
13086         } else
13087                 to_intel_atomic_state(state)->cdclk =
13088                         to_i915(state->dev)->cdclk_freq;
13089
13090         return drm_atomic_helper_check_planes(state->dev, state);
13091 }
13092
13093 /**
13094  * intel_atomic_commit - commit validated state object
13095  * @dev: DRM device
13096  * @state: the top-level driver state object
13097  * @async: asynchronous commit
13098  *
13099  * This function commits a top-level state object that has been validated
13100  * with drm_atomic_helper_check().
13101  *
13102  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13103  * we can only handle plane-related operations and do not yet support
13104  * asynchronous commit.
13105  *
13106  * RETURNS
13107  * Zero for success or -errno.
13108  */
13109 static int intel_atomic_commit(struct drm_device *dev,
13110                                struct drm_atomic_state *state,
13111                                bool async)
13112 {
13113         struct drm_i915_private *dev_priv = dev->dev_private;
13114         struct drm_crtc *crtc;
13115         struct drm_crtc_state *crtc_state;
13116         int ret = 0;
13117         int i;
13118         bool any_ms = false;
13119
13120         if (async) {
13121                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13122                 return -EINVAL;
13123         }
13124
13125         ret = drm_atomic_helper_prepare_planes(dev, state);
13126         if (ret)
13127                 return ret;
13128
13129         drm_atomic_helper_swap_state(dev, state);
13130
13131         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13132                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13133
13134                 if (!needs_modeset(crtc->state))
13135                         continue;
13136
13137                 any_ms = true;
13138                 intel_pre_plane_update(intel_crtc);
13139
13140                 if (crtc_state->active) {
13141                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13142                         dev_priv->display.crtc_disable(crtc);
13143                         intel_crtc->active = false;
13144                         intel_disable_shared_dpll(intel_crtc);
13145                 }
13146         }
13147
13148         /* Only after disabling all output pipelines that will be changed can we
13149          * update the the output configuration. */
13150         intel_modeset_update_crtc_state(state);
13151
13152         if (any_ms) {
13153                 intel_shared_dpll_commit(state);
13154
13155                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13156                 modeset_update_crtc_power_domains(state);
13157         }
13158
13159         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13160         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13161                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13162                 bool modeset = needs_modeset(crtc->state);
13163                 bool update_pipe = !modeset &&
13164                         to_intel_crtc_state(crtc->state)->update_pipe;
13165                 unsigned long put_domains = 0;
13166
13167                 if (modeset && crtc->state->active) {
13168                         update_scanline_offset(to_intel_crtc(crtc));
13169                         dev_priv->display.crtc_enable(crtc);
13170                 }
13171
13172                 if (update_pipe) {
13173                         put_domains = modeset_get_crtc_power_domains(crtc);
13174
13175                         /* make sure intel_modeset_check_state runs */
13176                         any_ms = true;
13177                 }
13178
13179                 if (!modeset)
13180                         intel_pre_plane_update(intel_crtc);
13181
13182                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13183
13184                 if (put_domains)
13185                         modeset_put_power_domains(dev_priv, put_domains);
13186
13187                 intel_post_plane_update(intel_crtc);
13188         }
13189
13190         /* FIXME: add subpixel order */
13191
13192         drm_atomic_helper_wait_for_vblanks(dev, state);
13193         drm_atomic_helper_cleanup_planes(dev, state);
13194
13195         if (any_ms)
13196                 intel_modeset_check_state(dev, state);
13197
13198         drm_atomic_state_free(state);
13199
13200         return 0;
13201 }
13202
13203 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13204 {
13205         struct drm_device *dev = crtc->dev;
13206         struct drm_atomic_state *state;
13207         struct drm_crtc_state *crtc_state;
13208         int ret;
13209
13210         state = drm_atomic_state_alloc(dev);
13211         if (!state) {
13212                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13213                               crtc->base.id);
13214                 return;
13215         }
13216
13217         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13218
13219 retry:
13220         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13221         ret = PTR_ERR_OR_ZERO(crtc_state);
13222         if (!ret) {
13223                 if (!crtc_state->active)
13224                         goto out;
13225
13226                 crtc_state->mode_changed = true;
13227                 ret = drm_atomic_commit(state);
13228         }
13229
13230         if (ret == -EDEADLK) {
13231                 drm_atomic_state_clear(state);
13232                 drm_modeset_backoff(state->acquire_ctx);
13233                 goto retry;
13234         }
13235
13236         if (ret)
13237 out:
13238                 drm_atomic_state_free(state);
13239 }
13240
13241 #undef for_each_intel_crtc_masked
13242
13243 static const struct drm_crtc_funcs intel_crtc_funcs = {
13244         .gamma_set = intel_crtc_gamma_set,
13245         .set_config = drm_atomic_helper_set_config,
13246         .destroy = intel_crtc_destroy,
13247         .page_flip = intel_crtc_page_flip,
13248         .atomic_duplicate_state = intel_crtc_duplicate_state,
13249         .atomic_destroy_state = intel_crtc_destroy_state,
13250 };
13251
13252 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13253                                       struct intel_shared_dpll *pll,
13254                                       struct intel_dpll_hw_state *hw_state)
13255 {
13256         uint32_t val;
13257
13258         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13259                 return false;
13260
13261         val = I915_READ(PCH_DPLL(pll->id));
13262         hw_state->dpll = val;
13263         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13264         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13265
13266         return val & DPLL_VCO_ENABLE;
13267 }
13268
13269 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13270                                   struct intel_shared_dpll *pll)
13271 {
13272         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13273         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13274 }
13275
13276 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13277                                 struct intel_shared_dpll *pll)
13278 {
13279         /* PCH refclock must be enabled first */
13280         ibx_assert_pch_refclk_enabled(dev_priv);
13281
13282         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13283
13284         /* Wait for the clocks to stabilize. */
13285         POSTING_READ(PCH_DPLL(pll->id));
13286         udelay(150);
13287
13288         /* The pixel multiplier can only be updated once the
13289          * DPLL is enabled and the clocks are stable.
13290          *
13291          * So write it again.
13292          */
13293         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13294         POSTING_READ(PCH_DPLL(pll->id));
13295         udelay(200);
13296 }
13297
13298 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13299                                  struct intel_shared_dpll *pll)
13300 {
13301         struct drm_device *dev = dev_priv->dev;
13302         struct intel_crtc *crtc;
13303
13304         /* Make sure no transcoder isn't still depending on us. */
13305         for_each_intel_crtc(dev, crtc) {
13306                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13307                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13308         }
13309
13310         I915_WRITE(PCH_DPLL(pll->id), 0);
13311         POSTING_READ(PCH_DPLL(pll->id));
13312         udelay(200);
13313 }
13314
13315 static char *ibx_pch_dpll_names[] = {
13316         "PCH DPLL A",
13317         "PCH DPLL B",
13318 };
13319
13320 static void ibx_pch_dpll_init(struct drm_device *dev)
13321 {
13322         struct drm_i915_private *dev_priv = dev->dev_private;
13323         int i;
13324
13325         dev_priv->num_shared_dpll = 2;
13326
13327         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13328                 dev_priv->shared_dplls[i].id = i;
13329                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13330                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13331                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13332                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13333                 dev_priv->shared_dplls[i].get_hw_state =
13334                         ibx_pch_dpll_get_hw_state;
13335         }
13336 }
13337
13338 static void intel_shared_dpll_init(struct drm_device *dev)
13339 {
13340         struct drm_i915_private *dev_priv = dev->dev_private;
13341
13342         if (HAS_DDI(dev))
13343                 intel_ddi_pll_init(dev);
13344         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13345                 ibx_pch_dpll_init(dev);
13346         else
13347                 dev_priv->num_shared_dpll = 0;
13348
13349         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13350 }
13351
13352 /**
13353  * intel_prepare_plane_fb - Prepare fb for usage on plane
13354  * @plane: drm plane to prepare for
13355  * @fb: framebuffer to prepare for presentation
13356  *
13357  * Prepares a framebuffer for usage on a display plane.  Generally this
13358  * involves pinning the underlying object and updating the frontbuffer tracking
13359  * bits.  Some older platforms need special physical address handling for
13360  * cursor planes.
13361  *
13362  * Returns 0 on success, negative error code on failure.
13363  */
13364 int
13365 intel_prepare_plane_fb(struct drm_plane *plane,
13366                        const struct drm_plane_state *new_state)
13367 {
13368         struct drm_device *dev = plane->dev;
13369         struct drm_framebuffer *fb = new_state->fb;
13370         struct intel_plane *intel_plane = to_intel_plane(plane);
13371         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13372         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13373         int ret = 0;
13374
13375         if (!obj)
13376                 return 0;
13377
13378         mutex_lock(&dev->struct_mutex);
13379
13380         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13381             INTEL_INFO(dev)->cursor_needs_physical) {
13382                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13383                 ret = i915_gem_object_attach_phys(obj, align);
13384                 if (ret)
13385                         DRM_DEBUG_KMS("failed to attach phys object\n");
13386         } else {
13387                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13388         }
13389
13390         if (ret == 0)
13391                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13392
13393         mutex_unlock(&dev->struct_mutex);
13394
13395         return ret;
13396 }
13397
13398 /**
13399  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13400  * @plane: drm plane to clean up for
13401  * @fb: old framebuffer that was on plane
13402  *
13403  * Cleans up a framebuffer that has just been removed from a plane.
13404  */
13405 void
13406 intel_cleanup_plane_fb(struct drm_plane *plane,
13407                        const struct drm_plane_state *old_state)
13408 {
13409         struct drm_device *dev = plane->dev;
13410         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13411
13412         if (!obj)
13413                 return;
13414
13415         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13416             !INTEL_INFO(dev)->cursor_needs_physical) {
13417                 mutex_lock(&dev->struct_mutex);
13418                 intel_unpin_fb_obj(old_state->fb, old_state);
13419                 mutex_unlock(&dev->struct_mutex);
13420         }
13421 }
13422
13423 int
13424 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13425 {
13426         int max_scale;
13427         struct drm_device *dev;
13428         struct drm_i915_private *dev_priv;
13429         int crtc_clock, cdclk;
13430
13431         if (!intel_crtc || !crtc_state)
13432                 return DRM_PLANE_HELPER_NO_SCALING;
13433
13434         dev = intel_crtc->base.dev;
13435         dev_priv = dev->dev_private;
13436         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13437         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13438
13439         if (!crtc_clock || !cdclk)
13440                 return DRM_PLANE_HELPER_NO_SCALING;
13441
13442         /*
13443          * skl max scale is lower of:
13444          *    close to 3 but not 3, -1 is for that purpose
13445          *            or
13446          *    cdclk/crtc_clock
13447          */
13448         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13449
13450         return max_scale;
13451 }
13452
13453 static int
13454 intel_check_primary_plane(struct drm_plane *plane,
13455                           struct intel_crtc_state *crtc_state,
13456                           struct intel_plane_state *state)
13457 {
13458         struct drm_crtc *crtc = state->base.crtc;
13459         struct drm_framebuffer *fb = state->base.fb;
13460         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13461         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13462         bool can_position = false;
13463
13464         /* use scaler when colorkey is not required */
13465         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13466             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13467                 min_scale = 1;
13468                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13469                 can_position = true;
13470         }
13471
13472         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13473                                              &state->dst, &state->clip,
13474                                              min_scale, max_scale,
13475                                              can_position, true,
13476                                              &state->visible);
13477 }
13478
13479 static void
13480 intel_commit_primary_plane(struct drm_plane *plane,
13481                            struct intel_plane_state *state)
13482 {
13483         struct drm_crtc *crtc = state->base.crtc;
13484         struct drm_framebuffer *fb = state->base.fb;
13485         struct drm_device *dev = plane->dev;
13486         struct drm_i915_private *dev_priv = dev->dev_private;
13487         struct intel_crtc *intel_crtc;
13488         struct drm_rect *src = &state->src;
13489
13490         crtc = crtc ? crtc : plane->crtc;
13491         intel_crtc = to_intel_crtc(crtc);
13492
13493         plane->fb = fb;
13494         crtc->x = src->x1 >> 16;
13495         crtc->y = src->y1 >> 16;
13496
13497         if (!crtc->state->active)
13498                 return;
13499
13500         dev_priv->display.update_primary_plane(crtc, fb,
13501                                                state->src.x1 >> 16,
13502                                                state->src.y1 >> 16);
13503 }
13504
13505 static void
13506 intel_disable_primary_plane(struct drm_plane *plane,
13507                             struct drm_crtc *crtc)
13508 {
13509         struct drm_device *dev = plane->dev;
13510         struct drm_i915_private *dev_priv = dev->dev_private;
13511
13512         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13513 }
13514
13515 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13516                                     struct drm_crtc_state *old_crtc_state)
13517 {
13518         struct drm_device *dev = crtc->dev;
13519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13520         struct intel_crtc_state *old_intel_state =
13521                 to_intel_crtc_state(old_crtc_state);
13522         bool modeset = needs_modeset(crtc->state);
13523
13524         if (intel_crtc->atomic.update_wm_pre)
13525                 intel_update_watermarks(crtc);
13526
13527         /* Perform vblank evasion around commit operation */
13528         if (crtc->state->active)
13529                 intel_pipe_update_start(intel_crtc);
13530
13531         if (modeset)
13532                 return;
13533
13534         if (to_intel_crtc_state(crtc->state)->update_pipe)
13535                 intel_update_pipe_config(intel_crtc, old_intel_state);
13536         else if (INTEL_INFO(dev)->gen >= 9)
13537                 skl_detach_scalers(intel_crtc);
13538 }
13539
13540 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13541                                      struct drm_crtc_state *old_crtc_state)
13542 {
13543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13544
13545         if (crtc->state->active)
13546                 intel_pipe_update_end(intel_crtc);
13547 }
13548
13549 /**
13550  * intel_plane_destroy - destroy a plane
13551  * @plane: plane to destroy
13552  *
13553  * Common destruction function for all types of planes (primary, cursor,
13554  * sprite).
13555  */
13556 void intel_plane_destroy(struct drm_plane *plane)
13557 {
13558         struct intel_plane *intel_plane = to_intel_plane(plane);
13559         drm_plane_cleanup(plane);
13560         kfree(intel_plane);
13561 }
13562
13563 const struct drm_plane_funcs intel_plane_funcs = {
13564         .update_plane = drm_atomic_helper_update_plane,
13565         .disable_plane = drm_atomic_helper_disable_plane,
13566         .destroy = intel_plane_destroy,
13567         .set_property = drm_atomic_helper_plane_set_property,
13568         .atomic_get_property = intel_plane_atomic_get_property,
13569         .atomic_set_property = intel_plane_atomic_set_property,
13570         .atomic_duplicate_state = intel_plane_duplicate_state,
13571         .atomic_destroy_state = intel_plane_destroy_state,
13572
13573 };
13574
13575 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13576                                                     int pipe)
13577 {
13578         struct intel_plane *primary;
13579         struct intel_plane_state *state;
13580         const uint32_t *intel_primary_formats;
13581         unsigned int num_formats;
13582
13583         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13584         if (primary == NULL)
13585                 return NULL;
13586
13587         state = intel_create_plane_state(&primary->base);
13588         if (!state) {
13589                 kfree(primary);
13590                 return NULL;
13591         }
13592         primary->base.state = &state->base;
13593
13594         primary->can_scale = false;
13595         primary->max_downscale = 1;
13596         if (INTEL_INFO(dev)->gen >= 9) {
13597                 primary->can_scale = true;
13598                 state->scaler_id = -1;
13599         }
13600         primary->pipe = pipe;
13601         primary->plane = pipe;
13602         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13603         primary->check_plane = intel_check_primary_plane;
13604         primary->commit_plane = intel_commit_primary_plane;
13605         primary->disable_plane = intel_disable_primary_plane;
13606         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13607                 primary->plane = !pipe;
13608
13609         if (INTEL_INFO(dev)->gen >= 9) {
13610                 intel_primary_formats = skl_primary_formats;
13611                 num_formats = ARRAY_SIZE(skl_primary_formats);
13612         } else if (INTEL_INFO(dev)->gen >= 4) {
13613                 intel_primary_formats = i965_primary_formats;
13614                 num_formats = ARRAY_SIZE(i965_primary_formats);
13615         } else {
13616                 intel_primary_formats = i8xx_primary_formats;
13617                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13618         }
13619
13620         drm_universal_plane_init(dev, &primary->base, 0,
13621                                  &intel_plane_funcs,
13622                                  intel_primary_formats, num_formats,
13623                                  DRM_PLANE_TYPE_PRIMARY);
13624
13625         if (INTEL_INFO(dev)->gen >= 4)
13626                 intel_create_rotation_property(dev, primary);
13627
13628         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13629
13630         return &primary->base;
13631 }
13632
13633 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13634 {
13635         if (!dev->mode_config.rotation_property) {
13636                 unsigned long flags = BIT(DRM_ROTATE_0) |
13637                         BIT(DRM_ROTATE_180);
13638
13639                 if (INTEL_INFO(dev)->gen >= 9)
13640                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13641
13642                 dev->mode_config.rotation_property =
13643                         drm_mode_create_rotation_property(dev, flags);
13644         }
13645         if (dev->mode_config.rotation_property)
13646                 drm_object_attach_property(&plane->base.base,
13647                                 dev->mode_config.rotation_property,
13648                                 plane->base.state->rotation);
13649 }
13650
13651 static int
13652 intel_check_cursor_plane(struct drm_plane *plane,
13653                          struct intel_crtc_state *crtc_state,
13654                          struct intel_plane_state *state)
13655 {
13656         struct drm_crtc *crtc = crtc_state->base.crtc;
13657         struct drm_framebuffer *fb = state->base.fb;
13658         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13659         unsigned stride;
13660         int ret;
13661
13662         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13663                                             &state->dst, &state->clip,
13664                                             DRM_PLANE_HELPER_NO_SCALING,
13665                                             DRM_PLANE_HELPER_NO_SCALING,
13666                                             true, true, &state->visible);
13667         if (ret)
13668                 return ret;
13669
13670         /* if we want to turn off the cursor ignore width and height */
13671         if (!obj)
13672                 return 0;
13673
13674         /* Check for which cursor types we support */
13675         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13676                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13677                           state->base.crtc_w, state->base.crtc_h);
13678                 return -EINVAL;
13679         }
13680
13681         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13682         if (obj->base.size < stride * state->base.crtc_h) {
13683                 DRM_DEBUG_KMS("buffer is too small\n");
13684                 return -ENOMEM;
13685         }
13686
13687         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13688                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13689                 return -EINVAL;
13690         }
13691
13692         return 0;
13693 }
13694
13695 static void
13696 intel_disable_cursor_plane(struct drm_plane *plane,
13697                            struct drm_crtc *crtc)
13698 {
13699         intel_crtc_update_cursor(crtc, false);
13700 }
13701
13702 static void
13703 intel_commit_cursor_plane(struct drm_plane *plane,
13704                           struct intel_plane_state *state)
13705 {
13706         struct drm_crtc *crtc = state->base.crtc;
13707         struct drm_device *dev = plane->dev;
13708         struct intel_crtc *intel_crtc;
13709         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13710         uint32_t addr;
13711
13712         crtc = crtc ? crtc : plane->crtc;
13713         intel_crtc = to_intel_crtc(crtc);
13714
13715         if (intel_crtc->cursor_bo == obj)
13716                 goto update;
13717
13718         if (!obj)
13719                 addr = 0;
13720         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13721                 addr = i915_gem_obj_ggtt_offset(obj);
13722         else
13723                 addr = obj->phys_handle->busaddr;
13724
13725         intel_crtc->cursor_addr = addr;
13726         intel_crtc->cursor_bo = obj;
13727
13728 update:
13729         if (crtc->state->active)
13730                 intel_crtc_update_cursor(crtc, state->visible);
13731 }
13732
13733 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13734                                                    int pipe)
13735 {
13736         struct intel_plane *cursor;
13737         struct intel_plane_state *state;
13738
13739         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13740         if (cursor == NULL)
13741                 return NULL;
13742
13743         state = intel_create_plane_state(&cursor->base);
13744         if (!state) {
13745                 kfree(cursor);
13746                 return NULL;
13747         }
13748         cursor->base.state = &state->base;
13749
13750         cursor->can_scale = false;
13751         cursor->max_downscale = 1;
13752         cursor->pipe = pipe;
13753         cursor->plane = pipe;
13754         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13755         cursor->check_plane = intel_check_cursor_plane;
13756         cursor->commit_plane = intel_commit_cursor_plane;
13757         cursor->disable_plane = intel_disable_cursor_plane;
13758
13759         drm_universal_plane_init(dev, &cursor->base, 0,
13760                                  &intel_plane_funcs,
13761                                  intel_cursor_formats,
13762                                  ARRAY_SIZE(intel_cursor_formats),
13763                                  DRM_PLANE_TYPE_CURSOR);
13764
13765         if (INTEL_INFO(dev)->gen >= 4) {
13766                 if (!dev->mode_config.rotation_property)
13767                         dev->mode_config.rotation_property =
13768                                 drm_mode_create_rotation_property(dev,
13769                                                         BIT(DRM_ROTATE_0) |
13770                                                         BIT(DRM_ROTATE_180));
13771                 if (dev->mode_config.rotation_property)
13772                         drm_object_attach_property(&cursor->base.base,
13773                                 dev->mode_config.rotation_property,
13774                                 state->base.rotation);
13775         }
13776
13777         if (INTEL_INFO(dev)->gen >=9)
13778                 state->scaler_id = -1;
13779
13780         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13781
13782         return &cursor->base;
13783 }
13784
13785 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13786         struct intel_crtc_state *crtc_state)
13787 {
13788         int i;
13789         struct intel_scaler *intel_scaler;
13790         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13791
13792         for (i = 0; i < intel_crtc->num_scalers; i++) {
13793                 intel_scaler = &scaler_state->scalers[i];
13794                 intel_scaler->in_use = 0;
13795                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13796         }
13797
13798         scaler_state->scaler_id = -1;
13799 }
13800
13801 static void intel_crtc_init(struct drm_device *dev, int pipe)
13802 {
13803         struct drm_i915_private *dev_priv = dev->dev_private;
13804         struct intel_crtc *intel_crtc;
13805         struct intel_crtc_state *crtc_state = NULL;
13806         struct drm_plane *primary = NULL;
13807         struct drm_plane *cursor = NULL;
13808         int i, ret;
13809
13810         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13811         if (intel_crtc == NULL)
13812                 return;
13813
13814         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13815         if (!crtc_state)
13816                 goto fail;
13817         intel_crtc->config = crtc_state;
13818         intel_crtc->base.state = &crtc_state->base;
13819         crtc_state->base.crtc = &intel_crtc->base;
13820
13821         /* initialize shared scalers */
13822         if (INTEL_INFO(dev)->gen >= 9) {
13823                 if (pipe == PIPE_C)
13824                         intel_crtc->num_scalers = 1;
13825                 else
13826                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13827
13828                 skl_init_scalers(dev, intel_crtc, crtc_state);
13829         }
13830
13831         primary = intel_primary_plane_create(dev, pipe);
13832         if (!primary)
13833                 goto fail;
13834
13835         cursor = intel_cursor_plane_create(dev, pipe);
13836         if (!cursor)
13837                 goto fail;
13838
13839         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13840                                         cursor, &intel_crtc_funcs);
13841         if (ret)
13842                 goto fail;
13843
13844         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13845         for (i = 0; i < 256; i++) {
13846                 intel_crtc->lut_r[i] = i;
13847                 intel_crtc->lut_g[i] = i;
13848                 intel_crtc->lut_b[i] = i;
13849         }
13850
13851         /*
13852          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13853          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13854          */
13855         intel_crtc->pipe = pipe;
13856         intel_crtc->plane = pipe;
13857         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13858                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13859                 intel_crtc->plane = !pipe;
13860         }
13861
13862         intel_crtc->cursor_base = ~0;
13863         intel_crtc->cursor_cntl = ~0;
13864         intel_crtc->cursor_size = ~0;
13865
13866         intel_crtc->wm.cxsr_allowed = true;
13867
13868         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13869                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13870         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13871         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13872
13873         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13874
13875         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13876         return;
13877
13878 fail:
13879         if (primary)
13880                 drm_plane_cleanup(primary);
13881         if (cursor)
13882                 drm_plane_cleanup(cursor);
13883         kfree(crtc_state);
13884         kfree(intel_crtc);
13885 }
13886
13887 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13888 {
13889         struct drm_encoder *encoder = connector->base.encoder;
13890         struct drm_device *dev = connector->base.dev;
13891
13892         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13893
13894         if (!encoder || WARN_ON(!encoder->crtc))
13895                 return INVALID_PIPE;
13896
13897         return to_intel_crtc(encoder->crtc)->pipe;
13898 }
13899
13900 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13901                                 struct drm_file *file)
13902 {
13903         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13904         struct drm_crtc *drmmode_crtc;
13905         struct intel_crtc *crtc;
13906
13907         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13908
13909         if (!drmmode_crtc) {
13910                 DRM_ERROR("no such CRTC id\n");
13911                 return -ENOENT;
13912         }
13913
13914         crtc = to_intel_crtc(drmmode_crtc);
13915         pipe_from_crtc_id->pipe = crtc->pipe;
13916
13917         return 0;
13918 }
13919
13920 static int intel_encoder_clones(struct intel_encoder *encoder)
13921 {
13922         struct drm_device *dev = encoder->base.dev;
13923         struct intel_encoder *source_encoder;
13924         int index_mask = 0;
13925         int entry = 0;
13926
13927         for_each_intel_encoder(dev, source_encoder) {
13928                 if (encoders_cloneable(encoder, source_encoder))
13929                         index_mask |= (1 << entry);
13930
13931                 entry++;
13932         }
13933
13934         return index_mask;
13935 }
13936
13937 static bool has_edp_a(struct drm_device *dev)
13938 {
13939         struct drm_i915_private *dev_priv = dev->dev_private;
13940
13941         if (!IS_MOBILE(dev))
13942                 return false;
13943
13944         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13945                 return false;
13946
13947         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13948                 return false;
13949
13950         return true;
13951 }
13952
13953 static bool intel_crt_present(struct drm_device *dev)
13954 {
13955         struct drm_i915_private *dev_priv = dev->dev_private;
13956
13957         if (INTEL_INFO(dev)->gen >= 9)
13958                 return false;
13959
13960         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13961                 return false;
13962
13963         if (IS_CHERRYVIEW(dev))
13964                 return false;
13965
13966         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13967                 return false;
13968
13969         return true;
13970 }
13971
13972 static void intel_setup_outputs(struct drm_device *dev)
13973 {
13974         struct drm_i915_private *dev_priv = dev->dev_private;
13975         struct intel_encoder *encoder;
13976         bool dpd_is_edp = false;
13977
13978         intel_lvds_init(dev);
13979
13980         if (intel_crt_present(dev))
13981                 intel_crt_init(dev);
13982
13983         if (IS_BROXTON(dev)) {
13984                 /*
13985                  * FIXME: Broxton doesn't support port detection via the
13986                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13987                  * detect the ports.
13988                  */
13989                 intel_ddi_init(dev, PORT_A);
13990                 intel_ddi_init(dev, PORT_B);
13991                 intel_ddi_init(dev, PORT_C);
13992         } else if (HAS_DDI(dev)) {
13993                 int found;
13994
13995                 /*
13996                  * Haswell uses DDI functions to detect digital outputs.
13997                  * On SKL pre-D0 the strap isn't connected, so we assume
13998                  * it's there.
13999                  */
14000                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14001                 /* WaIgnoreDDIAStrap: skl */
14002                 if (found || IS_SKYLAKE(dev))
14003                         intel_ddi_init(dev, PORT_A);
14004
14005                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14006                  * register */
14007                 found = I915_READ(SFUSE_STRAP);
14008
14009                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14010                         intel_ddi_init(dev, PORT_B);
14011                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14012                         intel_ddi_init(dev, PORT_C);
14013                 if (found & SFUSE_STRAP_DDID_DETECTED)
14014                         intel_ddi_init(dev, PORT_D);
14015                 /*
14016                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14017                  */
14018                 if (IS_SKYLAKE(dev) &&
14019                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14020                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14021                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14022                         intel_ddi_init(dev, PORT_E);
14023
14024         } else if (HAS_PCH_SPLIT(dev)) {
14025                 int found;
14026                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14027
14028                 if (has_edp_a(dev))
14029                         intel_dp_init(dev, DP_A, PORT_A);
14030
14031                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14032                         /* PCH SDVOB multiplex with HDMIB */
14033                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
14034                         if (!found)
14035                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14036                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14037                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14038                 }
14039
14040                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14041                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14042
14043                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14044                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14045
14046                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14047                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14048
14049                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14050                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14051         } else if (IS_VALLEYVIEW(dev)) {
14052                 /*
14053                  * The DP_DETECTED bit is the latched state of the DDC
14054                  * SDA pin at boot. However since eDP doesn't require DDC
14055                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14056                  * eDP ports may have been muxed to an alternate function.
14057                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14058                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14059                  * detect eDP ports.
14060                  */
14061                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14062                     !intel_dp_is_edp(dev, PORT_B))
14063                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14064                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14065                     intel_dp_is_edp(dev, PORT_B))
14066                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14067
14068                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14069                     !intel_dp_is_edp(dev, PORT_C))
14070                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14071                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14072                     intel_dp_is_edp(dev, PORT_C))
14073                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14074
14075                 if (IS_CHERRYVIEW(dev)) {
14076                         /* eDP not supported on port D, so don't check VBT */
14077                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14078                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14079                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14080                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14081                 }
14082
14083                 intel_dsi_init(dev);
14084         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14085                 bool found = false;
14086
14087                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14088                         DRM_DEBUG_KMS("probing SDVOB\n");
14089                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14090                         if (!found && IS_G4X(dev)) {
14091                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14092                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14093                         }
14094
14095                         if (!found && IS_G4X(dev))
14096                                 intel_dp_init(dev, DP_B, PORT_B);
14097                 }
14098
14099                 /* Before G4X SDVOC doesn't have its own detect register */
14100
14101                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14102                         DRM_DEBUG_KMS("probing SDVOC\n");
14103                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14104                 }
14105
14106                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14107
14108                         if (IS_G4X(dev)) {
14109                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14110                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14111                         }
14112                         if (IS_G4X(dev))
14113                                 intel_dp_init(dev, DP_C, PORT_C);
14114                 }
14115
14116                 if (IS_G4X(dev) &&
14117                     (I915_READ(DP_D) & DP_DETECTED))
14118                         intel_dp_init(dev, DP_D, PORT_D);
14119         } else if (IS_GEN2(dev))
14120                 intel_dvo_init(dev);
14121
14122         if (SUPPORTS_TV(dev))
14123                 intel_tv_init(dev);
14124
14125         intel_psr_init(dev);
14126
14127         for_each_intel_encoder(dev, encoder) {
14128                 encoder->base.possible_crtcs = encoder->crtc_mask;
14129                 encoder->base.possible_clones =
14130                         intel_encoder_clones(encoder);
14131         }
14132
14133         intel_init_pch_refclk(dev);
14134
14135         drm_helper_move_panel_connectors_to_head(dev);
14136 }
14137
14138 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14139 {
14140         struct drm_device *dev = fb->dev;
14141         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14142
14143         drm_framebuffer_cleanup(fb);
14144         mutex_lock(&dev->struct_mutex);
14145         WARN_ON(!intel_fb->obj->framebuffer_references--);
14146         drm_gem_object_unreference(&intel_fb->obj->base);
14147         mutex_unlock(&dev->struct_mutex);
14148         kfree(intel_fb);
14149 }
14150
14151 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14152                                                 struct drm_file *file,
14153                                                 unsigned int *handle)
14154 {
14155         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14156         struct drm_i915_gem_object *obj = intel_fb->obj;
14157
14158         return drm_gem_handle_create(file, &obj->base, handle);
14159 }
14160
14161 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14162                                         struct drm_file *file,
14163                                         unsigned flags, unsigned color,
14164                                         struct drm_clip_rect *clips,
14165                                         unsigned num_clips)
14166 {
14167         struct drm_device *dev = fb->dev;
14168         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14169         struct drm_i915_gem_object *obj = intel_fb->obj;
14170
14171         mutex_lock(&dev->struct_mutex);
14172         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14173         mutex_unlock(&dev->struct_mutex);
14174
14175         return 0;
14176 }
14177
14178 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14179         .destroy = intel_user_framebuffer_destroy,
14180         .create_handle = intel_user_framebuffer_create_handle,
14181         .dirty = intel_user_framebuffer_dirty,
14182 };
14183
14184 static
14185 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14186                          uint32_t pixel_format)
14187 {
14188         u32 gen = INTEL_INFO(dev)->gen;
14189
14190         if (gen >= 9) {
14191                 /* "The stride in bytes must not exceed the of the size of 8K
14192                  *  pixels and 32K bytes."
14193                  */
14194                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14195         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14196                 return 32*1024;
14197         } else if (gen >= 4) {
14198                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14199                         return 16*1024;
14200                 else
14201                         return 32*1024;
14202         } else if (gen >= 3) {
14203                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14204                         return 8*1024;
14205                 else
14206                         return 16*1024;
14207         } else {
14208                 /* XXX DSPC is limited to 4k tiled */
14209                 return 8*1024;
14210         }
14211 }
14212
14213 static int intel_framebuffer_init(struct drm_device *dev,
14214                                   struct intel_framebuffer *intel_fb,
14215                                   struct drm_mode_fb_cmd2 *mode_cmd,
14216                                   struct drm_i915_gem_object *obj)
14217 {
14218         unsigned int aligned_height;
14219         int ret;
14220         u32 pitch_limit, stride_alignment;
14221
14222         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14223
14224         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14225                 /* Enforce that fb modifier and tiling mode match, but only for
14226                  * X-tiled. This is needed for FBC. */
14227                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14228                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14229                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14230                         return -EINVAL;
14231                 }
14232         } else {
14233                 if (obj->tiling_mode == I915_TILING_X)
14234                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14235                 else if (obj->tiling_mode == I915_TILING_Y) {
14236                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14237                         return -EINVAL;
14238                 }
14239         }
14240
14241         /* Passed in modifier sanity checking. */
14242         switch (mode_cmd->modifier[0]) {
14243         case I915_FORMAT_MOD_Y_TILED:
14244         case I915_FORMAT_MOD_Yf_TILED:
14245                 if (INTEL_INFO(dev)->gen < 9) {
14246                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14247                                   mode_cmd->modifier[0]);
14248                         return -EINVAL;
14249                 }
14250         case DRM_FORMAT_MOD_NONE:
14251         case I915_FORMAT_MOD_X_TILED:
14252                 break;
14253         default:
14254                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14255                           mode_cmd->modifier[0]);
14256                 return -EINVAL;
14257         }
14258
14259         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14260                                                      mode_cmd->pixel_format);
14261         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14262                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14263                           mode_cmd->pitches[0], stride_alignment);
14264                 return -EINVAL;
14265         }
14266
14267         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14268                                            mode_cmd->pixel_format);
14269         if (mode_cmd->pitches[0] > pitch_limit) {
14270                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14271                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14272                           "tiled" : "linear",
14273                           mode_cmd->pitches[0], pitch_limit);
14274                 return -EINVAL;
14275         }
14276
14277         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14278             mode_cmd->pitches[0] != obj->stride) {
14279                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14280                           mode_cmd->pitches[0], obj->stride);
14281                 return -EINVAL;
14282         }
14283
14284         /* Reject formats not supported by any plane early. */
14285         switch (mode_cmd->pixel_format) {
14286         case DRM_FORMAT_C8:
14287         case DRM_FORMAT_RGB565:
14288         case DRM_FORMAT_XRGB8888:
14289         case DRM_FORMAT_ARGB8888:
14290                 break;
14291         case DRM_FORMAT_XRGB1555:
14292                 if (INTEL_INFO(dev)->gen > 3) {
14293                         DRM_DEBUG("unsupported pixel format: %s\n",
14294                                   drm_get_format_name(mode_cmd->pixel_format));
14295                         return -EINVAL;
14296                 }
14297                 break;
14298         case DRM_FORMAT_ABGR8888:
14299                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14300                         DRM_DEBUG("unsupported pixel format: %s\n",
14301                                   drm_get_format_name(mode_cmd->pixel_format));
14302                         return -EINVAL;
14303                 }
14304                 break;
14305         case DRM_FORMAT_XBGR8888:
14306         case DRM_FORMAT_XRGB2101010:
14307         case DRM_FORMAT_XBGR2101010:
14308                 if (INTEL_INFO(dev)->gen < 4) {
14309                         DRM_DEBUG("unsupported pixel format: %s\n",
14310                                   drm_get_format_name(mode_cmd->pixel_format));
14311                         return -EINVAL;
14312                 }
14313                 break;
14314         case DRM_FORMAT_ABGR2101010:
14315                 if (!IS_VALLEYVIEW(dev)) {
14316                         DRM_DEBUG("unsupported pixel format: %s\n",
14317                                   drm_get_format_name(mode_cmd->pixel_format));
14318                         return -EINVAL;
14319                 }
14320                 break;
14321         case DRM_FORMAT_YUYV:
14322         case DRM_FORMAT_UYVY:
14323         case DRM_FORMAT_YVYU:
14324         case DRM_FORMAT_VYUY:
14325                 if (INTEL_INFO(dev)->gen < 5) {
14326                         DRM_DEBUG("unsupported pixel format: %s\n",
14327                                   drm_get_format_name(mode_cmd->pixel_format));
14328                         return -EINVAL;
14329                 }
14330                 break;
14331         default:
14332                 DRM_DEBUG("unsupported pixel format: %s\n",
14333                           drm_get_format_name(mode_cmd->pixel_format));
14334                 return -EINVAL;
14335         }
14336
14337         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14338         if (mode_cmd->offsets[0] != 0)
14339                 return -EINVAL;
14340
14341         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14342                                                mode_cmd->pixel_format,
14343                                                mode_cmd->modifier[0]);
14344         /* FIXME drm helper for size checks (especially planar formats)? */
14345         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14346                 return -EINVAL;
14347
14348         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14349         intel_fb->obj = obj;
14350         intel_fb->obj->framebuffer_references++;
14351
14352         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14353         if (ret) {
14354                 DRM_ERROR("framebuffer init failed %d\n", ret);
14355                 return ret;
14356         }
14357
14358         return 0;
14359 }
14360
14361 static struct drm_framebuffer *
14362 intel_user_framebuffer_create(struct drm_device *dev,
14363                               struct drm_file *filp,
14364                               struct drm_mode_fb_cmd2 *mode_cmd)
14365 {
14366         struct drm_i915_gem_object *obj;
14367
14368         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14369                                                 mode_cmd->handles[0]));
14370         if (&obj->base == NULL)
14371                 return ERR_PTR(-ENOENT);
14372
14373         return intel_framebuffer_create(dev, mode_cmd, obj);
14374 }
14375
14376 #ifndef CONFIG_DRM_FBDEV_EMULATION
14377 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14378 {
14379 }
14380 #endif
14381
14382 static const struct drm_mode_config_funcs intel_mode_funcs = {
14383         .fb_create = intel_user_framebuffer_create,
14384         .output_poll_changed = intel_fbdev_output_poll_changed,
14385         .atomic_check = intel_atomic_check,
14386         .atomic_commit = intel_atomic_commit,
14387         .atomic_state_alloc = intel_atomic_state_alloc,
14388         .atomic_state_clear = intel_atomic_state_clear,
14389 };
14390
14391 /* Set up chip specific display functions */
14392 static void intel_init_display(struct drm_device *dev)
14393 {
14394         struct drm_i915_private *dev_priv = dev->dev_private;
14395
14396         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14397                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14398         else if (IS_CHERRYVIEW(dev))
14399                 dev_priv->display.find_dpll = chv_find_best_dpll;
14400         else if (IS_VALLEYVIEW(dev))
14401                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14402         else if (IS_PINEVIEW(dev))
14403                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14404         else
14405                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14406
14407         if (INTEL_INFO(dev)->gen >= 9) {
14408                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14409                 dev_priv->display.get_initial_plane_config =
14410                         skylake_get_initial_plane_config;
14411                 dev_priv->display.crtc_compute_clock =
14412                         haswell_crtc_compute_clock;
14413                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14414                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14415                 dev_priv->display.update_primary_plane =
14416                         skylake_update_primary_plane;
14417         } else if (HAS_DDI(dev)) {
14418                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14419                 dev_priv->display.get_initial_plane_config =
14420                         ironlake_get_initial_plane_config;
14421                 dev_priv->display.crtc_compute_clock =
14422                         haswell_crtc_compute_clock;
14423                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14424                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14425                 dev_priv->display.update_primary_plane =
14426                         ironlake_update_primary_plane;
14427         } else if (HAS_PCH_SPLIT(dev)) {
14428                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14429                 dev_priv->display.get_initial_plane_config =
14430                         ironlake_get_initial_plane_config;
14431                 dev_priv->display.crtc_compute_clock =
14432                         ironlake_crtc_compute_clock;
14433                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14434                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14435                 dev_priv->display.update_primary_plane =
14436                         ironlake_update_primary_plane;
14437         } else if (IS_VALLEYVIEW(dev)) {
14438                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14439                 dev_priv->display.get_initial_plane_config =
14440                         i9xx_get_initial_plane_config;
14441                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14442                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14443                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14444                 dev_priv->display.update_primary_plane =
14445                         i9xx_update_primary_plane;
14446         } else {
14447                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14448                 dev_priv->display.get_initial_plane_config =
14449                         i9xx_get_initial_plane_config;
14450                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14451                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14452                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14453                 dev_priv->display.update_primary_plane =
14454                         i9xx_update_primary_plane;
14455         }
14456
14457         /* Returns the core display clock speed */
14458         if (IS_SKYLAKE(dev))
14459                 dev_priv->display.get_display_clock_speed =
14460                         skylake_get_display_clock_speed;
14461         else if (IS_BROXTON(dev))
14462                 dev_priv->display.get_display_clock_speed =
14463                         broxton_get_display_clock_speed;
14464         else if (IS_BROADWELL(dev))
14465                 dev_priv->display.get_display_clock_speed =
14466                         broadwell_get_display_clock_speed;
14467         else if (IS_HASWELL(dev))
14468                 dev_priv->display.get_display_clock_speed =
14469                         haswell_get_display_clock_speed;
14470         else if (IS_VALLEYVIEW(dev))
14471                 dev_priv->display.get_display_clock_speed =
14472                         valleyview_get_display_clock_speed;
14473         else if (IS_GEN5(dev))
14474                 dev_priv->display.get_display_clock_speed =
14475                         ilk_get_display_clock_speed;
14476         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14477                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14478                 dev_priv->display.get_display_clock_speed =
14479                         i945_get_display_clock_speed;
14480         else if (IS_GM45(dev))
14481                 dev_priv->display.get_display_clock_speed =
14482                         gm45_get_display_clock_speed;
14483         else if (IS_CRESTLINE(dev))
14484                 dev_priv->display.get_display_clock_speed =
14485                         i965gm_get_display_clock_speed;
14486         else if (IS_PINEVIEW(dev))
14487                 dev_priv->display.get_display_clock_speed =
14488                         pnv_get_display_clock_speed;
14489         else if (IS_G33(dev) || IS_G4X(dev))
14490                 dev_priv->display.get_display_clock_speed =
14491                         g33_get_display_clock_speed;
14492         else if (IS_I915G(dev))
14493                 dev_priv->display.get_display_clock_speed =
14494                         i915_get_display_clock_speed;
14495         else if (IS_I945GM(dev) || IS_845G(dev))
14496                 dev_priv->display.get_display_clock_speed =
14497                         i9xx_misc_get_display_clock_speed;
14498         else if (IS_PINEVIEW(dev))
14499                 dev_priv->display.get_display_clock_speed =
14500                         pnv_get_display_clock_speed;
14501         else if (IS_I915GM(dev))
14502                 dev_priv->display.get_display_clock_speed =
14503                         i915gm_get_display_clock_speed;
14504         else if (IS_I865G(dev))
14505                 dev_priv->display.get_display_clock_speed =
14506                         i865_get_display_clock_speed;
14507         else if (IS_I85X(dev))
14508                 dev_priv->display.get_display_clock_speed =
14509                         i85x_get_display_clock_speed;
14510         else { /* 830 */
14511                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14512                 dev_priv->display.get_display_clock_speed =
14513                         i830_get_display_clock_speed;
14514         }
14515
14516         if (IS_GEN5(dev)) {
14517                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14518         } else if (IS_GEN6(dev)) {
14519                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14520         } else if (IS_IVYBRIDGE(dev)) {
14521                 /* FIXME: detect B0+ stepping and use auto training */
14522                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14523         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14524                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14525                 if (IS_BROADWELL(dev)) {
14526                         dev_priv->display.modeset_commit_cdclk =
14527                                 broadwell_modeset_commit_cdclk;
14528                         dev_priv->display.modeset_calc_cdclk =
14529                                 broadwell_modeset_calc_cdclk;
14530                 }
14531         } else if (IS_VALLEYVIEW(dev)) {
14532                 dev_priv->display.modeset_commit_cdclk =
14533                         valleyview_modeset_commit_cdclk;
14534                 dev_priv->display.modeset_calc_cdclk =
14535                         valleyview_modeset_calc_cdclk;
14536         } else if (IS_BROXTON(dev)) {
14537                 dev_priv->display.modeset_commit_cdclk =
14538                         broxton_modeset_commit_cdclk;
14539                 dev_priv->display.modeset_calc_cdclk =
14540                         broxton_modeset_calc_cdclk;
14541         }
14542
14543         switch (INTEL_INFO(dev)->gen) {
14544         case 2:
14545                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14546                 break;
14547
14548         case 3:
14549                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14550                 break;
14551
14552         case 4:
14553         case 5:
14554                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14555                 break;
14556
14557         case 6:
14558                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14559                 break;
14560         case 7:
14561         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14562                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14563                 break;
14564         case 9:
14565                 /* Drop through - unsupported since execlist only. */
14566         default:
14567                 /* Default just returns -ENODEV to indicate unsupported */
14568                 dev_priv->display.queue_flip = intel_default_queue_flip;
14569         }
14570
14571         mutex_init(&dev_priv->pps_mutex);
14572 }
14573
14574 /*
14575  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14576  * resume, or other times.  This quirk makes sure that's the case for
14577  * affected systems.
14578  */
14579 static void quirk_pipea_force(struct drm_device *dev)
14580 {
14581         struct drm_i915_private *dev_priv = dev->dev_private;
14582
14583         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14584         DRM_INFO("applying pipe a force quirk\n");
14585 }
14586
14587 static void quirk_pipeb_force(struct drm_device *dev)
14588 {
14589         struct drm_i915_private *dev_priv = dev->dev_private;
14590
14591         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14592         DRM_INFO("applying pipe b force quirk\n");
14593 }
14594
14595 /*
14596  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14597  */
14598 static void quirk_ssc_force_disable(struct drm_device *dev)
14599 {
14600         struct drm_i915_private *dev_priv = dev->dev_private;
14601         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14602         DRM_INFO("applying lvds SSC disable quirk\n");
14603 }
14604
14605 /*
14606  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14607  * brightness value
14608  */
14609 static void quirk_invert_brightness(struct drm_device *dev)
14610 {
14611         struct drm_i915_private *dev_priv = dev->dev_private;
14612         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14613         DRM_INFO("applying inverted panel brightness quirk\n");
14614 }
14615
14616 /* Some VBT's incorrectly indicate no backlight is present */
14617 static void quirk_backlight_present(struct drm_device *dev)
14618 {
14619         struct drm_i915_private *dev_priv = dev->dev_private;
14620         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14621         DRM_INFO("applying backlight present quirk\n");
14622 }
14623
14624 struct intel_quirk {
14625         int device;
14626         int subsystem_vendor;
14627         int subsystem_device;
14628         void (*hook)(struct drm_device *dev);
14629 };
14630
14631 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14632 struct intel_dmi_quirk {
14633         void (*hook)(struct drm_device *dev);
14634         const struct dmi_system_id (*dmi_id_list)[];
14635 };
14636
14637 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14638 {
14639         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14640         return 1;
14641 }
14642
14643 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14644         {
14645                 .dmi_id_list = &(const struct dmi_system_id[]) {
14646                         {
14647                                 .callback = intel_dmi_reverse_brightness,
14648                                 .ident = "NCR Corporation",
14649                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14650                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14651                                 },
14652                         },
14653                         { }  /* terminating entry */
14654                 },
14655                 .hook = quirk_invert_brightness,
14656         },
14657 };
14658
14659 static struct intel_quirk intel_quirks[] = {
14660         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14661         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14662
14663         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14664         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14665
14666         /* 830 needs to leave pipe A & dpll A up */
14667         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14668
14669         /* 830 needs to leave pipe B & dpll B up */
14670         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14671
14672         /* Lenovo U160 cannot use SSC on LVDS */
14673         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14674
14675         /* Sony Vaio Y cannot use SSC on LVDS */
14676         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14677
14678         /* Acer Aspire 5734Z must invert backlight brightness */
14679         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14680
14681         /* Acer/eMachines G725 */
14682         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14683
14684         /* Acer/eMachines e725 */
14685         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14686
14687         /* Acer/Packard Bell NCL20 */
14688         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14689
14690         /* Acer Aspire 4736Z */
14691         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14692
14693         /* Acer Aspire 5336 */
14694         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14695
14696         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14697         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14698
14699         /* Acer C720 Chromebook (Core i3 4005U) */
14700         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14701
14702         /* Apple Macbook 2,1 (Core 2 T7400) */
14703         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14704
14705         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14706         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14707
14708         /* HP Chromebook 14 (Celeron 2955U) */
14709         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14710
14711         /* Dell Chromebook 11 */
14712         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14713 };
14714
14715 static void intel_init_quirks(struct drm_device *dev)
14716 {
14717         struct pci_dev *d = dev->pdev;
14718         int i;
14719
14720         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14721                 struct intel_quirk *q = &intel_quirks[i];
14722
14723                 if (d->device == q->device &&
14724                     (d->subsystem_vendor == q->subsystem_vendor ||
14725                      q->subsystem_vendor == PCI_ANY_ID) &&
14726                     (d->subsystem_device == q->subsystem_device ||
14727                      q->subsystem_device == PCI_ANY_ID))
14728                         q->hook(dev);
14729         }
14730         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14731                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14732                         intel_dmi_quirks[i].hook(dev);
14733         }
14734 }
14735
14736 /* Disable the VGA plane that we never use */
14737 static void i915_disable_vga(struct drm_device *dev)
14738 {
14739         struct drm_i915_private *dev_priv = dev->dev_private;
14740         u8 sr1;
14741         u32 vga_reg = i915_vgacntrl_reg(dev);
14742
14743         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14744         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14745         outb(SR01, VGA_SR_INDEX);
14746         sr1 = inb(VGA_SR_DATA);
14747         outb(sr1 | 1<<5, VGA_SR_DATA);
14748         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14749         udelay(300);
14750
14751         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14752         POSTING_READ(vga_reg);
14753 }
14754
14755 void intel_modeset_init_hw(struct drm_device *dev)
14756 {
14757         intel_update_cdclk(dev);
14758         intel_prepare_ddi(dev);
14759         intel_init_clock_gating(dev);
14760         intel_enable_gt_powersave(dev);
14761 }
14762
14763 void intel_modeset_init(struct drm_device *dev)
14764 {
14765         struct drm_i915_private *dev_priv = dev->dev_private;
14766         int sprite, ret;
14767         enum pipe pipe;
14768         struct intel_crtc *crtc;
14769
14770         drm_mode_config_init(dev);
14771
14772         dev->mode_config.min_width = 0;
14773         dev->mode_config.min_height = 0;
14774
14775         dev->mode_config.preferred_depth = 24;
14776         dev->mode_config.prefer_shadow = 1;
14777
14778         dev->mode_config.allow_fb_modifiers = true;
14779
14780         dev->mode_config.funcs = &intel_mode_funcs;
14781
14782         intel_init_quirks(dev);
14783
14784         intel_init_pm(dev);
14785
14786         if (INTEL_INFO(dev)->num_pipes == 0)
14787                 return;
14788
14789         /*
14790          * There may be no VBT; and if the BIOS enabled SSC we can
14791          * just keep using it to avoid unnecessary flicker.  Whereas if the
14792          * BIOS isn't using it, don't assume it will work even if the VBT
14793          * indicates as much.
14794          */
14795         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14796                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14797                                             DREF_SSC1_ENABLE);
14798
14799                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14800                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14801                                      bios_lvds_use_ssc ? "en" : "dis",
14802                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14803                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14804                 }
14805         }
14806
14807         intel_init_display(dev);
14808         intel_init_audio(dev);
14809
14810         if (IS_GEN2(dev)) {
14811                 dev->mode_config.max_width = 2048;
14812                 dev->mode_config.max_height = 2048;
14813         } else if (IS_GEN3(dev)) {
14814                 dev->mode_config.max_width = 4096;
14815                 dev->mode_config.max_height = 4096;
14816         } else {
14817                 dev->mode_config.max_width = 8192;
14818                 dev->mode_config.max_height = 8192;
14819         }
14820
14821         if (IS_845G(dev) || IS_I865G(dev)) {
14822                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14823                 dev->mode_config.cursor_height = 1023;
14824         } else if (IS_GEN2(dev)) {
14825                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14826                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14827         } else {
14828                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14829                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14830         }
14831
14832         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14833
14834         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14835                       INTEL_INFO(dev)->num_pipes,
14836                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14837
14838         for_each_pipe(dev_priv, pipe) {
14839                 intel_crtc_init(dev, pipe);
14840                 for_each_sprite(dev_priv, pipe, sprite) {
14841                         ret = intel_plane_init(dev, pipe, sprite);
14842                         if (ret)
14843                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14844                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14845                 }
14846         }
14847
14848         intel_update_czclk(dev_priv);
14849         intel_update_cdclk(dev);
14850
14851         intel_shared_dpll_init(dev);
14852
14853         /* Just disable it once at startup */
14854         i915_disable_vga(dev);
14855         intel_setup_outputs(dev);
14856
14857         /* Just in case the BIOS is doing something questionable. */
14858         intel_fbc_disable(dev_priv);
14859
14860         drm_modeset_lock_all(dev);
14861         intel_modeset_setup_hw_state(dev);
14862         drm_modeset_unlock_all(dev);
14863
14864         for_each_intel_crtc(dev, crtc) {
14865                 struct intel_initial_plane_config plane_config = {};
14866
14867                 if (!crtc->active)
14868                         continue;
14869
14870                 /*
14871                  * Note that reserving the BIOS fb up front prevents us
14872                  * from stuffing other stolen allocations like the ring
14873                  * on top.  This prevents some ugliness at boot time, and
14874                  * can even allow for smooth boot transitions if the BIOS
14875                  * fb is large enough for the active pipe configuration.
14876                  */
14877                 dev_priv->display.get_initial_plane_config(crtc,
14878                                                            &plane_config);
14879
14880                 /*
14881                  * If the fb is shared between multiple heads, we'll
14882                  * just get the first one.
14883                  */
14884                 intel_find_initial_plane_obj(crtc, &plane_config);
14885         }
14886 }
14887
14888 static void intel_enable_pipe_a(struct drm_device *dev)
14889 {
14890         struct intel_connector *connector;
14891         struct drm_connector *crt = NULL;
14892         struct intel_load_detect_pipe load_detect_temp;
14893         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14894
14895         /* We can't just switch on the pipe A, we need to set things up with a
14896          * proper mode and output configuration. As a gross hack, enable pipe A
14897          * by enabling the load detect pipe once. */
14898         for_each_intel_connector(dev, connector) {
14899                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14900                         crt = &connector->base;
14901                         break;
14902                 }
14903         }
14904
14905         if (!crt)
14906                 return;
14907
14908         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14909                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14910 }
14911
14912 static bool
14913 intel_check_plane_mapping(struct intel_crtc *crtc)
14914 {
14915         struct drm_device *dev = crtc->base.dev;
14916         struct drm_i915_private *dev_priv = dev->dev_private;
14917         u32 reg, val;
14918
14919         if (INTEL_INFO(dev)->num_pipes == 1)
14920                 return true;
14921
14922         reg = DSPCNTR(!crtc->plane);
14923         val = I915_READ(reg);
14924
14925         if ((val & DISPLAY_PLANE_ENABLE) &&
14926             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14927                 return false;
14928
14929         return true;
14930 }
14931
14932 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14933 {
14934         struct drm_device *dev = crtc->base.dev;
14935         struct intel_encoder *encoder;
14936
14937         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14938                 return true;
14939
14940         return false;
14941 }
14942
14943 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14944 {
14945         struct drm_device *dev = crtc->base.dev;
14946         struct drm_i915_private *dev_priv = dev->dev_private;
14947         u32 reg;
14948
14949         /* Clear any frame start delays used for debugging left by the BIOS */
14950         reg = PIPECONF(crtc->config->cpu_transcoder);
14951         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14952
14953         /* restore vblank interrupts to correct state */
14954         drm_crtc_vblank_reset(&crtc->base);
14955         if (crtc->active) {
14956                 struct intel_plane *plane;
14957
14958                 drm_crtc_vblank_on(&crtc->base);
14959
14960                 /* Disable everything but the primary plane */
14961                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14962                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14963                                 continue;
14964
14965                         plane->disable_plane(&plane->base, &crtc->base);
14966                 }
14967         }
14968
14969         /* We need to sanitize the plane -> pipe mapping first because this will
14970          * disable the crtc (and hence change the state) if it is wrong. Note
14971          * that gen4+ has a fixed plane -> pipe mapping.  */
14972         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14973                 bool plane;
14974
14975                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14976                               crtc->base.base.id);
14977
14978                 /* Pipe has the wrong plane attached and the plane is active.
14979                  * Temporarily change the plane mapping and disable everything
14980                  * ...  */
14981                 plane = crtc->plane;
14982                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14983                 crtc->plane = !plane;
14984                 intel_crtc_disable_noatomic(&crtc->base);
14985                 crtc->plane = plane;
14986         }
14987
14988         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14989             crtc->pipe == PIPE_A && !crtc->active) {
14990                 /* BIOS forgot to enable pipe A, this mostly happens after
14991                  * resume. Force-enable the pipe to fix this, the update_dpms
14992                  * call below we restore the pipe to the right state, but leave
14993                  * the required bits on. */
14994                 intel_enable_pipe_a(dev);
14995         }
14996
14997         /* Adjust the state of the output pipe according to whether we
14998          * have active connectors/encoders. */
14999         if (!intel_crtc_has_encoders(crtc))
15000                 intel_crtc_disable_noatomic(&crtc->base);
15001
15002         if (crtc->active != crtc->base.state->active) {
15003                 struct intel_encoder *encoder;
15004
15005                 /* This can happen either due to bugs in the get_hw_state
15006                  * functions or because of calls to intel_crtc_disable_noatomic,
15007                  * or because the pipe is force-enabled due to the
15008                  * pipe A quirk. */
15009                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15010                               crtc->base.base.id,
15011                               crtc->base.state->enable ? "enabled" : "disabled",
15012                               crtc->active ? "enabled" : "disabled");
15013
15014                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15015                 crtc->base.state->active = crtc->active;
15016                 crtc->base.enabled = crtc->active;
15017
15018                 /* Because we only establish the connector -> encoder ->
15019                  * crtc links if something is active, this means the
15020                  * crtc is now deactivated. Break the links. connector
15021                  * -> encoder links are only establish when things are
15022                  *  actually up, hence no need to break them. */
15023                 WARN_ON(crtc->active);
15024
15025                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15026                         encoder->base.crtc = NULL;
15027         }
15028
15029         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15030                 /*
15031                  * We start out with underrun reporting disabled to avoid races.
15032                  * For correct bookkeeping mark this on active crtcs.
15033                  *
15034                  * Also on gmch platforms we dont have any hardware bits to
15035                  * disable the underrun reporting. Which means we need to start
15036                  * out with underrun reporting disabled also on inactive pipes,
15037                  * since otherwise we'll complain about the garbage we read when
15038                  * e.g. coming up after runtime pm.
15039                  *
15040                  * No protection against concurrent access is required - at
15041                  * worst a fifo underrun happens which also sets this to false.
15042                  */
15043                 crtc->cpu_fifo_underrun_disabled = true;
15044                 crtc->pch_fifo_underrun_disabled = true;
15045         }
15046 }
15047
15048 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15049 {
15050         struct intel_connector *connector;
15051         struct drm_device *dev = encoder->base.dev;
15052         bool active = false;
15053
15054         /* We need to check both for a crtc link (meaning that the
15055          * encoder is active and trying to read from a pipe) and the
15056          * pipe itself being active. */
15057         bool has_active_crtc = encoder->base.crtc &&
15058                 to_intel_crtc(encoder->base.crtc)->active;
15059
15060         for_each_intel_connector(dev, connector) {
15061                 if (connector->base.encoder != &encoder->base)
15062                         continue;
15063
15064                 active = true;
15065                 break;
15066         }
15067
15068         if (active && !has_active_crtc) {
15069                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15070                               encoder->base.base.id,
15071                               encoder->base.name);
15072
15073                 /* Connector is active, but has no active pipe. This is
15074                  * fallout from our resume register restoring. Disable
15075                  * the encoder manually again. */
15076                 if (encoder->base.crtc) {
15077                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15078                                       encoder->base.base.id,
15079                                       encoder->base.name);
15080                         encoder->disable(encoder);
15081                         if (encoder->post_disable)
15082                                 encoder->post_disable(encoder);
15083                 }
15084                 encoder->base.crtc = NULL;
15085
15086                 /* Inconsistent output/port/pipe state happens presumably due to
15087                  * a bug in one of the get_hw_state functions. Or someplace else
15088                  * in our code, like the register restore mess on resume. Clamp
15089                  * things to off as a safer default. */
15090                 for_each_intel_connector(dev, connector) {
15091                         if (connector->encoder != encoder)
15092                                 continue;
15093                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15094                         connector->base.encoder = NULL;
15095                 }
15096         }
15097         /* Enabled encoders without active connectors will be fixed in
15098          * the crtc fixup. */
15099 }
15100
15101 void i915_redisable_vga_power_on(struct drm_device *dev)
15102 {
15103         struct drm_i915_private *dev_priv = dev->dev_private;
15104         u32 vga_reg = i915_vgacntrl_reg(dev);
15105
15106         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15107                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15108                 i915_disable_vga(dev);
15109         }
15110 }
15111
15112 void i915_redisable_vga(struct drm_device *dev)
15113 {
15114         struct drm_i915_private *dev_priv = dev->dev_private;
15115
15116         /* This function can be called both from intel_modeset_setup_hw_state or
15117          * at a very early point in our resume sequence, where the power well
15118          * structures are not yet restored. Since this function is at a very
15119          * paranoid "someone might have enabled VGA while we were not looking"
15120          * level, just check if the power well is enabled instead of trying to
15121          * follow the "don't touch the power well if we don't need it" policy
15122          * the rest of the driver uses. */
15123         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15124                 return;
15125
15126         i915_redisable_vga_power_on(dev);
15127 }
15128
15129 static bool primary_get_hw_state(struct intel_plane *plane)
15130 {
15131         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15132
15133         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15134 }
15135
15136 /* FIXME read out full plane state for all planes */
15137 static void readout_plane_state(struct intel_crtc *crtc)
15138 {
15139         struct drm_plane *primary = crtc->base.primary;
15140         struct intel_plane_state *plane_state =
15141                 to_intel_plane_state(primary->state);
15142
15143         plane_state->visible =
15144                 primary_get_hw_state(to_intel_plane(primary));
15145
15146         if (plane_state->visible)
15147                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15148 }
15149
15150 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15151 {
15152         struct drm_i915_private *dev_priv = dev->dev_private;
15153         enum pipe pipe;
15154         struct intel_crtc *crtc;
15155         struct intel_encoder *encoder;
15156         struct intel_connector *connector;
15157         int i;
15158
15159         for_each_intel_crtc(dev, crtc) {
15160                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15161                 memset(crtc->config, 0, sizeof(*crtc->config));
15162                 crtc->config->base.crtc = &crtc->base;
15163
15164                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15165                                                                  crtc->config);
15166
15167                 crtc->base.state->active = crtc->active;
15168                 crtc->base.enabled = crtc->active;
15169
15170                 readout_plane_state(crtc);
15171
15172                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15173                               crtc->base.base.id,
15174                               crtc->active ? "enabled" : "disabled");
15175         }
15176
15177         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15178                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15179
15180                 pll->on = pll->get_hw_state(dev_priv, pll,
15181                                             &pll->config.hw_state);
15182                 pll->active = 0;
15183                 pll->config.crtc_mask = 0;
15184                 for_each_intel_crtc(dev, crtc) {
15185                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15186                                 pll->active++;
15187                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15188                         }
15189                 }
15190
15191                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15192                               pll->name, pll->config.crtc_mask, pll->on);
15193
15194                 if (pll->config.crtc_mask)
15195                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15196         }
15197
15198         for_each_intel_encoder(dev, encoder) {
15199                 pipe = 0;
15200
15201                 if (encoder->get_hw_state(encoder, &pipe)) {
15202                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15203                         encoder->base.crtc = &crtc->base;
15204                         encoder->get_config(encoder, crtc->config);
15205                 } else {
15206                         encoder->base.crtc = NULL;
15207                 }
15208
15209                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15210                               encoder->base.base.id,
15211                               encoder->base.name,
15212                               encoder->base.crtc ? "enabled" : "disabled",
15213                               pipe_name(pipe));
15214         }
15215
15216         for_each_intel_connector(dev, connector) {
15217                 if (connector->get_hw_state(connector)) {
15218                         connector->base.dpms = DRM_MODE_DPMS_ON;
15219                         connector->base.encoder = &connector->encoder->base;
15220                 } else {
15221                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15222                         connector->base.encoder = NULL;
15223                 }
15224                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15225                               connector->base.base.id,
15226                               connector->base.name,
15227                               connector->base.encoder ? "enabled" : "disabled");
15228         }
15229
15230         for_each_intel_crtc(dev, crtc) {
15231                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15232
15233                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15234                 if (crtc->base.state->active) {
15235                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15236                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15237                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15238
15239                         /*
15240                          * The initial mode needs to be set in order to keep
15241                          * the atomic core happy. It wants a valid mode if the
15242                          * crtc's enabled, so we do the above call.
15243                          *
15244                          * At this point some state updated by the connectors
15245                          * in their ->detect() callback has not run yet, so
15246                          * no recalculation can be done yet.
15247                          *
15248                          * Even if we could do a recalculation and modeset
15249                          * right now it would cause a double modeset if
15250                          * fbdev or userspace chooses a different initial mode.
15251                          *
15252                          * If that happens, someone indicated they wanted a
15253                          * mode change, which means it's safe to do a full
15254                          * recalculation.
15255                          */
15256                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15257
15258                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15259                         update_scanline_offset(crtc);
15260                 }
15261         }
15262 }
15263
15264 /* Scan out the current hw modeset state,
15265  * and sanitizes it to the current state
15266  */
15267 static void
15268 intel_modeset_setup_hw_state(struct drm_device *dev)
15269 {
15270         struct drm_i915_private *dev_priv = dev->dev_private;
15271         enum pipe pipe;
15272         struct intel_crtc *crtc;
15273         struct intel_encoder *encoder;
15274         int i;
15275
15276         intel_modeset_readout_hw_state(dev);
15277
15278         /* HW state is read out, now we need to sanitize this mess. */
15279         for_each_intel_encoder(dev, encoder) {
15280                 intel_sanitize_encoder(encoder);
15281         }
15282
15283         for_each_pipe(dev_priv, pipe) {
15284                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15285                 intel_sanitize_crtc(crtc);
15286                 intel_dump_pipe_config(crtc, crtc->config,
15287                                        "[setup_hw_state]");
15288         }
15289
15290         intel_modeset_update_connector_atomic_state(dev);
15291
15292         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15293                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15294
15295                 if (!pll->on || pll->active)
15296                         continue;
15297
15298                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15299
15300                 pll->disable(dev_priv, pll);
15301                 pll->on = false;
15302         }
15303
15304         if (IS_VALLEYVIEW(dev))
15305                 vlv_wm_get_hw_state(dev);
15306         else if (IS_GEN9(dev))
15307                 skl_wm_get_hw_state(dev);
15308         else if (HAS_PCH_SPLIT(dev))
15309                 ilk_wm_get_hw_state(dev);
15310
15311         for_each_intel_crtc(dev, crtc) {
15312                 unsigned long put_domains;
15313
15314                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15315                 if (WARN_ON(put_domains))
15316                         modeset_put_power_domains(dev_priv, put_domains);
15317         }
15318         intel_display_set_init_power(dev_priv, false);
15319 }
15320
15321 void intel_display_resume(struct drm_device *dev)
15322 {
15323         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15324         struct intel_connector *conn;
15325         struct intel_plane *plane;
15326         struct drm_crtc *crtc;
15327         int ret;
15328
15329         if (!state)
15330                 return;
15331
15332         state->acquire_ctx = dev->mode_config.acquire_ctx;
15333
15334         /* preserve complete old state, including dpll */
15335         intel_atomic_get_shared_dpll_state(state);
15336
15337         for_each_crtc(dev, crtc) {
15338                 struct drm_crtc_state *crtc_state =
15339                         drm_atomic_get_crtc_state(state, crtc);
15340
15341                 ret = PTR_ERR_OR_ZERO(crtc_state);
15342                 if (ret)
15343                         goto err;
15344
15345                 /* force a restore */
15346                 crtc_state->mode_changed = true;
15347         }
15348
15349         for_each_intel_plane(dev, plane) {
15350                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15351                 if (ret)
15352                         goto err;
15353         }
15354
15355         for_each_intel_connector(dev, conn) {
15356                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15357                 if (ret)
15358                         goto err;
15359         }
15360
15361         intel_modeset_setup_hw_state(dev);
15362
15363         i915_redisable_vga(dev);
15364         ret = drm_atomic_commit(state);
15365         if (!ret)
15366                 return;
15367
15368 err:
15369         DRM_ERROR("Restoring old state failed with %i\n", ret);
15370         drm_atomic_state_free(state);
15371 }
15372
15373 void intel_modeset_gem_init(struct drm_device *dev)
15374 {
15375         struct drm_crtc *c;
15376         struct drm_i915_gem_object *obj;
15377         int ret;
15378
15379         mutex_lock(&dev->struct_mutex);
15380         intel_init_gt_powersave(dev);
15381         mutex_unlock(&dev->struct_mutex);
15382
15383         intel_modeset_init_hw(dev);
15384
15385         intel_setup_overlay(dev);
15386
15387         /*
15388          * Make sure any fbs we allocated at startup are properly
15389          * pinned & fenced.  When we do the allocation it's too early
15390          * for this.
15391          */
15392         for_each_crtc(dev, c) {
15393                 obj = intel_fb_obj(c->primary->fb);
15394                 if (obj == NULL)
15395                         continue;
15396
15397                 mutex_lock(&dev->struct_mutex);
15398                 ret = intel_pin_and_fence_fb_obj(c->primary,
15399                                                  c->primary->fb,
15400                                                  c->primary->state,
15401                                                  NULL, NULL);
15402                 mutex_unlock(&dev->struct_mutex);
15403                 if (ret) {
15404                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15405                                   to_intel_crtc(c)->pipe);
15406                         drm_framebuffer_unreference(c->primary->fb);
15407                         c->primary->fb = NULL;
15408                         c->primary->crtc = c->primary->state->crtc = NULL;
15409                         update_state_fb(c->primary);
15410                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15411                 }
15412         }
15413
15414         intel_backlight_register(dev);
15415 }
15416
15417 void intel_connector_unregister(struct intel_connector *intel_connector)
15418 {
15419         struct drm_connector *connector = &intel_connector->base;
15420
15421         intel_panel_destroy_backlight(connector);
15422         drm_connector_unregister(connector);
15423 }
15424
15425 void intel_modeset_cleanup(struct drm_device *dev)
15426 {
15427         struct drm_i915_private *dev_priv = dev->dev_private;
15428         struct drm_connector *connector;
15429
15430         intel_disable_gt_powersave(dev);
15431
15432         intel_backlight_unregister(dev);
15433
15434         /*
15435          * Interrupts and polling as the first thing to avoid creating havoc.
15436          * Too much stuff here (turning of connectors, ...) would
15437          * experience fancy races otherwise.
15438          */
15439         intel_irq_uninstall(dev_priv);
15440
15441         /*
15442          * Due to the hpd irq storm handling the hotplug work can re-arm the
15443          * poll handlers. Hence disable polling after hpd handling is shut down.
15444          */
15445         drm_kms_helper_poll_fini(dev);
15446
15447         intel_unregister_dsm_handler();
15448
15449         intel_fbc_disable(dev_priv);
15450
15451         /* flush any delayed tasks or pending work */
15452         flush_scheduled_work();
15453
15454         /* destroy the backlight and sysfs files before encoders/connectors */
15455         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15456                 struct intel_connector *intel_connector;
15457
15458                 intel_connector = to_intel_connector(connector);
15459                 intel_connector->unregister(intel_connector);
15460         }
15461
15462         drm_mode_config_cleanup(dev);
15463
15464         intel_cleanup_overlay(dev);
15465
15466         mutex_lock(&dev->struct_mutex);
15467         intel_cleanup_gt_powersave(dev);
15468         mutex_unlock(&dev->struct_mutex);
15469 }
15470
15471 /*
15472  * Return which encoder is currently attached for connector.
15473  */
15474 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15475 {
15476         return &intel_attached_encoder(connector)->base;
15477 }
15478
15479 void intel_connector_attach_encoder(struct intel_connector *connector,
15480                                     struct intel_encoder *encoder)
15481 {
15482         connector->encoder = encoder;
15483         drm_mode_connector_attach_encoder(&connector->base,
15484                                           &encoder->base);
15485 }
15486
15487 /*
15488  * set vga decode state - true == enable VGA decode
15489  */
15490 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15491 {
15492         struct drm_i915_private *dev_priv = dev->dev_private;
15493         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15494         u16 gmch_ctrl;
15495
15496         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15497                 DRM_ERROR("failed to read control word\n");
15498                 return -EIO;
15499         }
15500
15501         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15502                 return 0;
15503
15504         if (state)
15505                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15506         else
15507                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15508
15509         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15510                 DRM_ERROR("failed to write control word\n");
15511                 return -EIO;
15512         }
15513
15514         return 0;
15515 }
15516
15517 struct intel_display_error_state {
15518
15519         u32 power_well_driver;
15520
15521         int num_transcoders;
15522
15523         struct intel_cursor_error_state {
15524                 u32 control;
15525                 u32 position;
15526                 u32 base;
15527                 u32 size;
15528         } cursor[I915_MAX_PIPES];
15529
15530         struct intel_pipe_error_state {
15531                 bool power_domain_on;
15532                 u32 source;
15533                 u32 stat;
15534         } pipe[I915_MAX_PIPES];
15535
15536         struct intel_plane_error_state {
15537                 u32 control;
15538                 u32 stride;
15539                 u32 size;
15540                 u32 pos;
15541                 u32 addr;
15542                 u32 surface;
15543                 u32 tile_offset;
15544         } plane[I915_MAX_PIPES];
15545
15546         struct intel_transcoder_error_state {
15547                 bool power_domain_on;
15548                 enum transcoder cpu_transcoder;
15549
15550                 u32 conf;
15551
15552                 u32 htotal;
15553                 u32 hblank;
15554                 u32 hsync;
15555                 u32 vtotal;
15556                 u32 vblank;
15557                 u32 vsync;
15558         } transcoder[4];
15559 };
15560
15561 struct intel_display_error_state *
15562 intel_display_capture_error_state(struct drm_device *dev)
15563 {
15564         struct drm_i915_private *dev_priv = dev->dev_private;
15565         struct intel_display_error_state *error;
15566         int transcoders[] = {
15567                 TRANSCODER_A,
15568                 TRANSCODER_B,
15569                 TRANSCODER_C,
15570                 TRANSCODER_EDP,
15571         };
15572         int i;
15573
15574         if (INTEL_INFO(dev)->num_pipes == 0)
15575                 return NULL;
15576
15577         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15578         if (error == NULL)
15579                 return NULL;
15580
15581         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15582                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15583
15584         for_each_pipe(dev_priv, i) {
15585                 error->pipe[i].power_domain_on =
15586                         __intel_display_power_is_enabled(dev_priv,
15587                                                          POWER_DOMAIN_PIPE(i));
15588                 if (!error->pipe[i].power_domain_on)
15589                         continue;
15590
15591                 error->cursor[i].control = I915_READ(CURCNTR(i));
15592                 error->cursor[i].position = I915_READ(CURPOS(i));
15593                 error->cursor[i].base = I915_READ(CURBASE(i));
15594
15595                 error->plane[i].control = I915_READ(DSPCNTR(i));
15596                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15597                 if (INTEL_INFO(dev)->gen <= 3) {
15598                         error->plane[i].size = I915_READ(DSPSIZE(i));
15599                         error->plane[i].pos = I915_READ(DSPPOS(i));
15600                 }
15601                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15602                         error->plane[i].addr = I915_READ(DSPADDR(i));
15603                 if (INTEL_INFO(dev)->gen >= 4) {
15604                         error->plane[i].surface = I915_READ(DSPSURF(i));
15605                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15606                 }
15607
15608                 error->pipe[i].source = I915_READ(PIPESRC(i));
15609
15610                 if (HAS_GMCH_DISPLAY(dev))
15611                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15612         }
15613
15614         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15615         if (HAS_DDI(dev_priv->dev))
15616                 error->num_transcoders++; /* Account for eDP. */
15617
15618         for (i = 0; i < error->num_transcoders; i++) {
15619                 enum transcoder cpu_transcoder = transcoders[i];
15620
15621                 error->transcoder[i].power_domain_on =
15622                         __intel_display_power_is_enabled(dev_priv,
15623                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15624                 if (!error->transcoder[i].power_domain_on)
15625                         continue;
15626
15627                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15628
15629                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15630                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15631                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15632                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15633                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15634                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15635                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15636         }
15637
15638         return error;
15639 }
15640
15641 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15642
15643 void
15644 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15645                                 struct drm_device *dev,
15646                                 struct intel_display_error_state *error)
15647 {
15648         struct drm_i915_private *dev_priv = dev->dev_private;
15649         int i;
15650
15651         if (!error)
15652                 return;
15653
15654         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15655         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15656                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15657                            error->power_well_driver);
15658         for_each_pipe(dev_priv, i) {
15659                 err_printf(m, "Pipe [%d]:\n", i);
15660                 err_printf(m, "  Power: %s\n",
15661                            error->pipe[i].power_domain_on ? "on" : "off");
15662                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15663                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15664
15665                 err_printf(m, "Plane [%d]:\n", i);
15666                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15667                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15668                 if (INTEL_INFO(dev)->gen <= 3) {
15669                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15670                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15671                 }
15672                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15673                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15674                 if (INTEL_INFO(dev)->gen >= 4) {
15675                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15676                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15677                 }
15678
15679                 err_printf(m, "Cursor [%d]:\n", i);
15680                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15681                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15682                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15683         }
15684
15685         for (i = 0; i < error->num_transcoders; i++) {
15686                 err_printf(m, "CPU transcoder: %c\n",
15687                            transcoder_name(error->transcoder[i].cpu_transcoder));
15688                 err_printf(m, "  Power: %s\n",
15689                            error->transcoder[i].power_domain_on ? "on" : "off");
15690                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15691                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15692                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15693                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15694                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15695                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15696                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15697         }
15698 }
15699
15700 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15701 {
15702         struct intel_crtc *crtc;
15703
15704         for_each_intel_crtc(dev, crtc) {
15705                 struct intel_unpin_work *work;
15706
15707                 spin_lock_irq(&dev->event_lock);
15708
15709                 work = crtc->unpin_work;
15710
15711                 if (work && work->event &&
15712                     work->event->base.file_priv == file) {
15713                         kfree(work->event);
15714                         work->event = NULL;
15715                 }
15716
15717                 spin_unlock_irq(&dev->event_lock);
15718         }
15719 }