drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198                            struct drm_i915_gem_object *obj,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         u32 alignment;
2203         int ret;
2204
2205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207         switch (obj->tiling_mode) {
2208         case I915_TILING_NONE:
2209                 if (INTEL_INFO(dev)->gen >= 9)
2210                         alignment = 256 * 1024;
2211                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212                         alignment = 128 * 1024;
2213                 else if (INTEL_INFO(dev)->gen >= 4)
2214                         alignment = 4 * 1024;
2215                 else
2216                         alignment = 64 * 1024;
2217                 break;
2218         case I915_TILING_X:
2219                 if (INTEL_INFO(dev)->gen >= 9)
2220                         alignment = 256 * 1024;
2221                 else {
2222                         /* pin() will align the object as required by fence */
2223                         alignment = 0;
2224                 }
2225                 break;
2226         case I915_TILING_Y:
2227                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228                 return -EINVAL;
2229         default:
2230                 BUG();
2231         }
2232
2233         /* Note that the w/a also requires 64 PTE of padding following the
2234          * bo. We currently fill all unused PTE with the shadow page and so
2235          * we should always have valid PTE following the scanout preventing
2236          * the VT-d warning.
2237          */
2238         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239                 alignment = 256 * 1024;
2240
2241         /*
2242          * Global gtt pte registers are special registers which actually forward
2243          * writes to a chunk of system memory. Which means that there is no risk
2244          * that the register values disappear as soon as we call
2245          * intel_runtime_pm_put(), so it is correct to wrap only the
2246          * pin/unpin/fence and not more.
2247          */
2248         intel_runtime_pm_get(dev_priv);
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         intel_runtime_pm_put(dev_priv);
2268         return 0;
2269
2270 err_unpin:
2271         i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282         i915_gem_object_unpin_fence(obj);
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287  * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289                                              unsigned int tiling_mode,
2290                                              unsigned int cpp,
2291                                              unsigned int pitch)
2292 {
2293         if (tiling_mode != I915_TILING_NONE) {
2294                 unsigned int tile_rows, tiles;
2295
2296                 tile_rows = *y / 8;
2297                 *y %= 8;
2298
2299                 tiles = *x / (512/cpp);
2300                 *x %= 512/cpp;
2301
2302                 return tile_rows * pitch * 8 + tiles * 4096;
2303         } else {
2304                 unsigned int offset;
2305
2306                 offset = *y * pitch + *x * cpp;
2307                 *y = 0;
2308                 *x = (offset & 4095) / cpp;
2309                 return offset & -4096;
2310         }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315         switch (format) {
2316         case DISPPLANE_8BPP:
2317                 return DRM_FORMAT_C8;
2318         case DISPPLANE_BGRX555:
2319                 return DRM_FORMAT_XRGB1555;
2320         case DISPPLANE_BGRX565:
2321                 return DRM_FORMAT_RGB565;
2322         default:
2323         case DISPPLANE_BGRX888:
2324                 return DRM_FORMAT_XRGB8888;
2325         case DISPPLANE_RGBX888:
2326                 return DRM_FORMAT_XBGR8888;
2327         case DISPPLANE_BGRX101010:
2328                 return DRM_FORMAT_XRGB2101010;
2329         case DISPPLANE_RGBX101010:
2330                 return DRM_FORMAT_XBGR2101010;
2331         }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335                                   struct intel_plane_config *plane_config)
2336 {
2337         struct drm_device *dev = crtc->base.dev;
2338         struct drm_i915_gem_object *obj = NULL;
2339         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340         u32 base = plane_config->base;
2341
2342         if (plane_config->size == 0)
2343                 return false;
2344
2345         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346                                                              plane_config->size);
2347         if (!obj)
2348                 return false;
2349
2350         if (plane_config->tiled) {
2351                 obj->tiling_mode = I915_TILING_X;
2352                 obj->stride = crtc->base.primary->fb->pitches[0];
2353         }
2354
2355         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356         mode_cmd.width = crtc->base.primary->fb->width;
2357         mode_cmd.height = crtc->base.primary->fb->height;
2358         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360         mutex_lock(&dev->struct_mutex);
2361
2362         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363                                    &mode_cmd, obj)) {
2364                 DRM_DEBUG_KMS("intel fb init failed\n");
2365                 goto out_unref_obj;
2366         }
2367
2368         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369         mutex_unlock(&dev->struct_mutex);
2370
2371         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372         return true;
2373
2374 out_unref_obj:
2375         drm_gem_object_unreference(&obj->base);
2376         mutex_unlock(&dev->struct_mutex);
2377         return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381                                  struct intel_plane_config *plane_config)
2382 {
2383         struct drm_device *dev = intel_crtc->base.dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_crtc *c;
2386         struct intel_crtc *i;
2387         struct drm_i915_gem_object *obj;
2388
2389         if (!intel_crtc->base.primary->fb)
2390                 return;
2391
2392         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393                 return;
2394
2395         kfree(intel_crtc->base.primary->fb);
2396         intel_crtc->base.primary->fb = NULL;
2397
2398         /*
2399          * Failed to alloc the obj, check to see if we should share
2400          * an fb with another CRTC instead
2401          */
2402         for_each_crtc(dev, c) {
2403                 i = to_intel_crtc(c);
2404
2405                 if (c == &intel_crtc->base)
2406                         continue;
2407
2408                 if (!i->active)
2409                         continue;
2410
2411                 obj = intel_fb_obj(c->primary->fb);
2412                 if (obj == NULL)
2413                         continue;
2414
2415                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416                         if (obj->tiling_mode != I915_TILING_NONE)
2417                                 dev_priv->preserve_bios_swizzle = true;
2418
2419                         drm_framebuffer_reference(c->primary->fb);
2420                         intel_crtc->base.primary->fb = c->primary->fb;
2421                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2422                         break;
2423                 }
2424         }
2425 }
2426
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428                                       struct drm_framebuffer *fb,
2429                                       int x, int y)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg = DSPCNTR(plane);
2439         int pixel_size;
2440
2441         if (!intel_crtc->primary_enabled) {
2442                 I915_WRITE(reg, 0);
2443                 if (INTEL_INFO(dev)->gen >= 4)
2444                         I915_WRITE(DSPSURF(plane), 0);
2445                 else
2446                         I915_WRITE(DSPADDR(plane), 0);
2447                 POSTING_READ(reg);
2448                 return;
2449         }
2450
2451         obj = intel_fb_obj(fb);
2452         if (WARN_ON(obj == NULL))
2453                 return;
2454
2455         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
2457         dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
2459         dspcntr |= DISPLAY_PLANE_ENABLE;
2460
2461         if (INTEL_INFO(dev)->gen < 4) {
2462                 if (intel_crtc->pipe == PIPE_B)
2463                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465                 /* pipesrc and dspsize control the size that is scaled from,
2466                  * which should always be the user's requested size.
2467                  */
2468                 I915_WRITE(DSPSIZE(plane),
2469                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470                            (intel_crtc->config.pipe_src_w - 1));
2471                 I915_WRITE(DSPPOS(plane), 0);
2472         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473                 I915_WRITE(PRIMSIZE(plane),
2474                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475                            (intel_crtc->config.pipe_src_w - 1));
2476                 I915_WRITE(PRIMPOS(plane), 0);
2477                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2478         }
2479
2480         switch (fb->pixel_format) {
2481         case DRM_FORMAT_C8:
2482                 dspcntr |= DISPPLANE_8BPP;
2483                 break;
2484         case DRM_FORMAT_XRGB1555:
2485         case DRM_FORMAT_ARGB1555:
2486                 dspcntr |= DISPPLANE_BGRX555;
2487                 break;
2488         case DRM_FORMAT_RGB565:
2489                 dspcntr |= DISPPLANE_BGRX565;
2490                 break;
2491         case DRM_FORMAT_XRGB8888:
2492         case DRM_FORMAT_ARGB8888:
2493                 dspcntr |= DISPPLANE_BGRX888;
2494                 break;
2495         case DRM_FORMAT_XBGR8888:
2496         case DRM_FORMAT_ABGR8888:
2497                 dspcntr |= DISPPLANE_RGBX888;
2498                 break;
2499         case DRM_FORMAT_XRGB2101010:
2500         case DRM_FORMAT_ARGB2101010:
2501                 dspcntr |= DISPPLANE_BGRX101010;
2502                 break;
2503         case DRM_FORMAT_XBGR2101010:
2504         case DRM_FORMAT_ABGR2101010:
2505                 dspcntr |= DISPPLANE_RGBX101010;
2506                 break;
2507         default:
2508                 BUG();
2509         }
2510
2511         if (INTEL_INFO(dev)->gen >= 4 &&
2512             obj->tiling_mode != I915_TILING_NONE)
2513                 dspcntr |= DISPPLANE_TILED;
2514
2515         if (IS_G4X(dev))
2516                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
2518         linear_offset = y * fb->pitches[0] + x * pixel_size;
2519
2520         if (INTEL_INFO(dev)->gen >= 4) {
2521                 intel_crtc->dspaddr_offset =
2522                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2523                                                        pixel_size,
2524                                                        fb->pitches[0]);
2525                 linear_offset -= intel_crtc->dspaddr_offset;
2526         } else {
2527                 intel_crtc->dspaddr_offset = linear_offset;
2528         }
2529
2530         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531                 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533                 x += (intel_crtc->config.pipe_src_w - 1);
2534                 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536                 /* Finding the last pixel of the last line of the display
2537                 data and adding to linear_offset*/
2538                 linear_offset +=
2539                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541         }
2542
2543         I915_WRITE(reg, dspcntr);
2544
2545         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547                       fb->pitches[0]);
2548         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549         if (INTEL_INFO(dev)->gen >= 4) {
2550                 I915_WRITE(DSPSURF(plane),
2551                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2554         } else
2555                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2556         POSTING_READ(reg);
2557 }
2558
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560                                           struct drm_framebuffer *fb,
2561                                           int x, int y)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         struct drm_i915_gem_object *obj;
2567         int plane = intel_crtc->plane;
2568         unsigned long linear_offset;
2569         u32 dspcntr;
2570         u32 reg = DSPCNTR(plane);
2571         int pixel_size;
2572
2573         if (!intel_crtc->primary_enabled) {
2574                 I915_WRITE(reg, 0);
2575                 I915_WRITE(DSPSURF(plane), 0);
2576                 POSTING_READ(reg);
2577                 return;
2578         }
2579
2580         obj = intel_fb_obj(fb);
2581         if (WARN_ON(obj == NULL))
2582                 return;
2583
2584         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
2586         dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
2588         dspcntr |= DISPLAY_PLANE_ENABLE;
2589
2590         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
2593         switch (fb->pixel_format) {
2594         case DRM_FORMAT_C8:
2595                 dspcntr |= DISPPLANE_8BPP;
2596                 break;
2597         case DRM_FORMAT_RGB565:
2598                 dspcntr |= DISPPLANE_BGRX565;
2599                 break;
2600         case DRM_FORMAT_XRGB8888:
2601         case DRM_FORMAT_ARGB8888:
2602                 dspcntr |= DISPPLANE_BGRX888;
2603                 break;
2604         case DRM_FORMAT_XBGR8888:
2605         case DRM_FORMAT_ABGR8888:
2606                 dspcntr |= DISPPLANE_RGBX888;
2607                 break;
2608         case DRM_FORMAT_XRGB2101010:
2609         case DRM_FORMAT_ARGB2101010:
2610                 dspcntr |= DISPPLANE_BGRX101010;
2611                 break;
2612         case DRM_FORMAT_XBGR2101010:
2613         case DRM_FORMAT_ABGR2101010:
2614                 dspcntr |= DISPPLANE_RGBX101010;
2615                 break;
2616         default:
2617                 BUG();
2618         }
2619
2620         if (obj->tiling_mode != I915_TILING_NONE)
2621                 dspcntr |= DISPPLANE_TILED;
2622
2623         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2625
2626         linear_offset = y * fb->pitches[0] + x * pixel_size;
2627         intel_crtc->dspaddr_offset =
2628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629                                                pixel_size,
2630                                                fb->pitches[0]);
2631         linear_offset -= intel_crtc->dspaddr_offset;
2632         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633                 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636                         x += (intel_crtc->config.pipe_src_w - 1);
2637                         y += (intel_crtc->config.pipe_src_h - 1);
2638
2639                         /* Finding the last pixel of the last line of the display
2640                         data and adding to linear_offset*/
2641                         linear_offset +=
2642                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644                 }
2645         }
2646
2647         I915_WRITE(reg, dspcntr);
2648
2649         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651                       fb->pitches[0]);
2652         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653         I915_WRITE(DSPSURF(plane),
2654                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657         } else {
2658                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660         }
2661         POSTING_READ(reg);
2662 }
2663
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665                                          struct drm_framebuffer *fb,
2666                                          int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct intel_framebuffer *intel_fb;
2672         struct drm_i915_gem_object *obj;
2673         int pipe = intel_crtc->pipe;
2674         u32 plane_ctl, stride;
2675
2676         if (!intel_crtc->primary_enabled) {
2677                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679                 POSTING_READ(PLANE_CTL(pipe, 0));
2680                 return;
2681         }
2682
2683         plane_ctl = PLANE_CTL_ENABLE |
2684                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2685                     PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687         switch (fb->pixel_format) {
2688         case DRM_FORMAT_RGB565:
2689                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690                 break;
2691         case DRM_FORMAT_XRGB8888:
2692                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693                 break;
2694         case DRM_FORMAT_XBGR8888:
2695                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697                 break;
2698         case DRM_FORMAT_XRGB2101010:
2699                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700                 break;
2701         case DRM_FORMAT_XBGR2101010:
2702                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704                 break;
2705         default:
2706                 BUG();
2707         }
2708
2709         intel_fb = to_intel_framebuffer(fb);
2710         obj = intel_fb->obj;
2711
2712         /*
2713          * The stride is either expressed as a multiple of 64 bytes chunks for
2714          * linear buffers or in number of tiles for tiled buffers.
2715          */
2716         switch (obj->tiling_mode) {
2717         case I915_TILING_NONE:
2718                 stride = fb->pitches[0] >> 6;
2719                 break;
2720         case I915_TILING_X:
2721                 plane_ctl |= PLANE_CTL_TILED_X;
2722                 stride = fb->pitches[0] >> 9;
2723                 break;
2724         default:
2725                 BUG();
2726         }
2727
2728         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730                 plane_ctl |= PLANE_CTL_ROTATE_180;
2731
2732         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735                       i915_gem_obj_ggtt_offset(obj),
2736                       x, y, fb->width, fb->height,
2737                       fb->pitches[0]);
2738
2739         I915_WRITE(PLANE_POS(pipe, 0), 0);
2740         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741         I915_WRITE(PLANE_SIZE(pipe, 0),
2742                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2743                    (intel_crtc->config.pipe_src_w - 1));
2744         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747         POSTING_READ(PLANE_SURF(pipe, 0));
2748 }
2749
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2751 static int
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753                            int x, int y, enum mode_set_atomic state)
2754 {
2755         struct drm_device *dev = crtc->dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757
2758         if (dev_priv->display.disable_fbc)
2759                 dev_priv->display.disable_fbc(dev);
2760
2761         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763         return 0;
2764 }
2765
2766 void intel_display_handle_reset(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct drm_crtc *crtc;
2770
2771         /*
2772          * Flips in the rings have been nuked by the reset,
2773          * so complete all pending flips so that user space
2774          * will get its events and not get stuck.
2775          *
2776          * Also update the base address of all primary
2777          * planes to the the last fb to make sure we're
2778          * showing the correct fb after a reset.
2779          *
2780          * Need to make two loops over the crtcs so that we
2781          * don't try to grab a crtc mutex before the
2782          * pending_flip_queue really got woken up.
2783          */
2784
2785         for_each_crtc(dev, crtc) {
2786                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787                 enum plane plane = intel_crtc->plane;
2788
2789                 intel_prepare_page_flip(dev, plane);
2790                 intel_finish_page_flip_plane(dev, plane);
2791         }
2792
2793         for_each_crtc(dev, crtc) {
2794                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
2796                 drm_modeset_lock(&crtc->mutex, NULL);
2797                 /*
2798                  * FIXME: Once we have proper support for primary planes (and
2799                  * disabling them without disabling the entire crtc) allow again
2800                  * a NULL crtc->primary->fb.
2801                  */
2802                 if (intel_crtc->active && crtc->primary->fb)
2803                         dev_priv->display.update_primary_plane(crtc,
2804                                                                crtc->primary->fb,
2805                                                                crtc->x,
2806                                                                crtc->y);
2807                 drm_modeset_unlock(&crtc->mutex);
2808         }
2809 }
2810
2811 static int
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2813 {
2814         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816         bool was_interruptible = dev_priv->mm.interruptible;
2817         int ret;
2818
2819         /* Big Hammer, we also need to ensure that any pending
2820          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821          * current scanout is retired before unpinning the old
2822          * framebuffer.
2823          *
2824          * This should only fail upon a hung GPU, in which case we
2825          * can safely continue.
2826          */
2827         dev_priv->mm.interruptible = false;
2828         ret = i915_gem_object_finish_gpu(obj);
2829         dev_priv->mm.interruptible = was_interruptible;
2830
2831         return ret;
2832 }
2833
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irq(&dev->event_lock);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irq(&dev->event_lock);
2848
2849         return pending;
2850 }
2851
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->base.dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         const struct drm_display_mode *adjusted_mode;
2857
2858         if (!i915.fastboot)
2859                 return;
2860
2861         /*
2862          * Update pipe size and adjust fitter if needed: the reason for this is
2863          * that in compute_mode_changes we check the native mode (not the pfit
2864          * mode) to see if we can flip rather than do a full mode set. In the
2865          * fastboot case, we'll flip, but if we don't update the pipesrc and
2866          * pfit state, we'll end up with a big fb scanned out into the wrong
2867          * sized surface.
2868          *
2869          * To fix this properly, we need to hoist the checks up into
2870          * compute_mode_changes (or above), check the actual pfit state and
2871          * whether the platform allows pfit disable with pipe active, and only
2872          * then update the pipesrc and pfit state, even on the flip path.
2873          */
2874
2875         adjusted_mode = &crtc->config.adjusted_mode;
2876
2877         I915_WRITE(PIPESRC(crtc->pipe),
2878                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879                    (adjusted_mode->crtc_vdisplay - 1));
2880         if (!crtc->config.pch_pfit.enabled &&
2881             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886         }
2887         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889 }
2890
2891 static int
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893                     struct drm_framebuffer *fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         enum pipe pipe = intel_crtc->pipe;
2899         struct drm_framebuffer *old_fb = crtc->primary->fb;
2900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2902         int ret;
2903
2904         if (intel_crtc_has_pending_flip(crtc)) {
2905                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906                 return -EBUSY;
2907         }
2908
2909         /* no fb bound */
2910         if (!fb) {
2911                 DRM_ERROR("No FB bound\n");
2912                 return 0;
2913         }
2914
2915         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917                           plane_name(intel_crtc->plane),
2918                           INTEL_INFO(dev)->num_pipes);
2919                 return -EINVAL;
2920         }
2921
2922         mutex_lock(&dev->struct_mutex);
2923         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924         if (ret == 0)
2925                 i915_gem_track_fb(old_obj, obj,
2926                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2927         mutex_unlock(&dev->struct_mutex);
2928         if (ret != 0) {
2929                 DRM_ERROR("pin & fence failed\n");
2930                 return ret;
2931         }
2932
2933         intel_update_pipe_size(intel_crtc);
2934
2935         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2936
2937         if (intel_crtc->active)
2938                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
2940         crtc->primary->fb = fb;
2941         crtc->x = x;
2942         crtc->y = y;
2943
2944         if (old_fb) {
2945                 if (intel_crtc->active && old_fb != fb)
2946                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2947                 mutex_lock(&dev->struct_mutex);
2948                 intel_unpin_fb_obj(old_obj);
2949                 mutex_unlock(&dev->struct_mutex);
2950         }
2951
2952         mutex_lock(&dev->struct_mutex);
2953         intel_update_fbc(dev);
2954         mutex_unlock(&dev->struct_mutex);
2955
2956         return 0;
2957 }
2958
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         int pipe = intel_crtc->pipe;
2965         u32 reg, temp;
2966
2967         /* enable normal train */
2968         reg = FDI_TX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (IS_IVYBRIDGE(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2976         }
2977         I915_WRITE(reg, temp);
2978
2979         reg = FDI_RX_CTL(pipe);
2980         temp = I915_READ(reg);
2981         if (HAS_PCH_CPT(dev)) {
2982                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984         } else {
2985                 temp &= ~FDI_LINK_TRAIN_NONE;
2986                 temp |= FDI_LINK_TRAIN_NONE;
2987         }
2988         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990         /* wait one idle pattern time */
2991         POSTING_READ(reg);
2992         udelay(1000);
2993
2994         /* IVB wants error correction enabled */
2995         if (IS_IVYBRIDGE(dev))
2996                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997                            FDI_FE_ERRC_ENABLE);
2998 }
2999
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3001 {
3002         return crtc->base.enabled && crtc->active &&
3003                 crtc->config.has_pch_encoder;
3004 }
3005
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *pipe_B_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011         struct intel_crtc *pipe_C_crtc =
3012                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013         uint32_t temp;
3014
3015         /*
3016          * When everything is off disable fdi C so that we could enable fdi B
3017          * with all lanes. Note that we don't care about enabled pipes without
3018          * an enabled pch encoder.
3019          */
3020         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021             !pipe_has_enabled_pch(pipe_C_crtc)) {
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025                 temp = I915_READ(SOUTH_CHICKEN1);
3026                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028                 I915_WRITE(SOUTH_CHICKEN1, temp);
3029         }
3030 }
3031
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp, tries;
3040
3041         /* FDI needs bits from pipe first */
3042         assert_pipe_enabled(dev_priv, pipe);
3043
3044         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045            for train result */
3046         reg = FDI_RX_IMR(pipe);
3047         temp = I915_READ(reg);
3048         temp &= ~FDI_RX_SYMBOL_LOCK;
3049         temp &= ~FDI_RX_BIT_LOCK;
3050         I915_WRITE(reg, temp);
3051         I915_READ(reg);
3052         udelay(150);
3053
3054         /* enable CPU FDI TX and PCH FDI RX */
3055         reg = FDI_TX_CTL(pipe);
3056         temp = I915_READ(reg);
3057         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059         temp &= ~FDI_LINK_TRAIN_NONE;
3060         temp |= FDI_LINK_TRAIN_PATTERN_1;
3061         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3062
3063         reg = FDI_RX_CTL(pipe);
3064         temp = I915_READ(reg);
3065         temp &= ~FDI_LINK_TRAIN_NONE;
3066         temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069         POSTING_READ(reg);
3070         udelay(150);
3071
3072         /* Ironlake workaround, enable clock pointer after FDI enable*/
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075                    FDI_RX_PHASE_SYNC_POINTER_EN);
3076
3077         reg = FDI_RX_IIR(pipe);
3078         for (tries = 0; tries < 5; tries++) {
3079                 temp = I915_READ(reg);
3080                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                 if ((temp & FDI_RX_BIT_LOCK)) {
3083                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3084                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                         break;
3086                 }
3087         }
3088         if (tries == 5)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         I915_WRITE(reg, temp);
3097
3098         reg = FDI_RX_CTL(pipe);
3099         temp = I915_READ(reg);
3100         temp &= ~FDI_LINK_TRAIN_NONE;
3101         temp |= FDI_LINK_TRAIN_PATTERN_2;
3102         I915_WRITE(reg, temp);
3103
3104         POSTING_READ(reg);
3105         udelay(150);
3106
3107         reg = FDI_RX_IIR(pipe);
3108         for (tries = 0; tries < 5; tries++) {
3109                 temp = I915_READ(reg);
3110                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112                 if (temp & FDI_RX_SYMBOL_LOCK) {
3113                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3115                         break;
3116                 }
3117         }
3118         if (tries == 5)
3119                 DRM_ERROR("FDI train 2 fail!\n");
3120
3121         DRM_DEBUG_KMS("FDI train done\n");
3122
3123 }
3124
3125 static const int snb_b_fdi_train_param[] = {
3126         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130 };
3131
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134 {
3135         struct drm_device *dev = crtc->dev;
3136         struct drm_i915_private *dev_priv = dev->dev_private;
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp, i, retry;
3140
3141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142            for train result */
3143         reg = FDI_RX_IMR(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_RX_SYMBOL_LOCK;
3146         temp &= ~FDI_RX_BIT_LOCK;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         /* enable CPU FDI TX and PCH FDI RX */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_1;
3159         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160         /* SNB-B */
3161         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3163
3164         I915_WRITE(FDI_RX_MISC(pipe),
3165                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
3167         reg = FDI_RX_CTL(pipe);
3168         temp = I915_READ(reg);
3169         if (HAS_PCH_CPT(dev)) {
3170                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172         } else {
3173                 temp &= ~FDI_LINK_TRAIN_NONE;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175         }
3176         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178         POSTING_READ(reg);
3179         udelay(150);
3180
3181         for (i = 0; i < 4; i++) {
3182                 reg = FDI_TX_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185                 temp |= snb_b_fdi_train_param[i];
3186                 I915_WRITE(reg, temp);
3187
3188                 POSTING_READ(reg);
3189                 udelay(500);
3190
3191                 for (retry = 0; retry < 5; retry++) {
3192                         reg = FDI_RX_IIR(pipe);
3193                         temp = I915_READ(reg);
3194                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195                         if (temp & FDI_RX_BIT_LOCK) {
3196                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198                                 break;
3199                         }
3200                         udelay(50);
3201                 }
3202                 if (retry < 5)
3203                         break;
3204         }
3205         if (i == 4)
3206                 DRM_ERROR("FDI train 1 fail!\n");
3207
3208         /* Train 2 */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_LINK_TRAIN_NONE;
3212         temp |= FDI_LINK_TRAIN_PATTERN_2;
3213         if (IS_GEN6(dev)) {
3214                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215                 /* SNB-B */
3216                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217         }
3218         I915_WRITE(reg, temp);
3219
3220         reg = FDI_RX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (HAS_PCH_CPT(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         POSTING_READ(reg);
3232         udelay(150);
3233
3234         for (i = 0; i < 4; i++) {
3235                 reg = FDI_TX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238                 temp |= snb_b_fdi_train_param[i];
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(500);
3243
3244                 for (retry = 0; retry < 5; retry++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248                         if (temp & FDI_RX_SYMBOL_LOCK) {
3249                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251                                 break;
3252                         }
3253                         udelay(50);
3254                 }
3255                 if (retry < 5)
3256                         break;
3257         }
3258         if (i == 4)
3259                 DRM_ERROR("FDI train 2 fail!\n");
3260
3261         DRM_DEBUG_KMS("FDI train done.\n");
3262 }
3263
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp, i, j;
3272
3273         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274            for train result */
3275         reg = FDI_RX_IMR(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_RX_SYMBOL_LOCK;
3278         temp &= ~FDI_RX_BIT_LOCK;
3279         I915_WRITE(reg, temp);
3280
3281         POSTING_READ(reg);
3282         udelay(150);
3283
3284         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285                       I915_READ(FDI_RX_IIR(pipe)));
3286
3287         /* Try each vswing and preemphasis setting twice before moving on */
3288         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289                 /* disable first in case we need to retry */
3290                 reg = FDI_TX_CTL(pipe);
3291                 temp = I915_READ(reg);
3292                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293                 temp &= ~FDI_TX_ENABLE;
3294                 I915_WRITE(reg, temp);
3295
3296                 reg = FDI_RX_CTL(pipe);
3297                 temp = I915_READ(reg);
3298                 temp &= ~FDI_LINK_TRAIN_AUTO;
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp &= ~FDI_RX_ENABLE;
3301                 I915_WRITE(reg, temp);
3302
3303                 /* enable CPU FDI TX and PCH FDI RX */
3304                 reg = FDI_TX_CTL(pipe);
3305                 temp = I915_READ(reg);
3306                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310                 temp |= snb_b_fdi_train_param[j/2];
3311                 temp |= FDI_COMPOSITE_SYNC;
3312                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314                 I915_WRITE(FDI_RX_MISC(pipe),
3315                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317                 reg = FDI_RX_CTL(pipe);
3318                 temp = I915_READ(reg);
3319                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320                 temp |= FDI_COMPOSITE_SYNC;
3321                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323                 POSTING_READ(reg);
3324                 udelay(1); /* should be 0.5us */
3325
3326                 for (i = 0; i < 4; i++) {
3327                         reg = FDI_RX_IIR(pipe);
3328                         temp = I915_READ(reg);
3329                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331                         if (temp & FDI_RX_BIT_LOCK ||
3332                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335                                               i);
3336                                 break;
3337                         }
3338                         udelay(1); /* should be 0.5us */
3339                 }
3340                 if (i == 4) {
3341                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342                         continue;
3343                 }
3344
3345                 /* Train 2 */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356                 I915_WRITE(reg, temp);
3357
3358                 POSTING_READ(reg);
3359                 udelay(2); /* should be 1.5us */
3360
3361                 for (i = 0; i < 4; i++) {
3362                         reg = FDI_RX_IIR(pipe);
3363                         temp = I915_READ(reg);
3364                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3365
3366                         if (temp & FDI_RX_SYMBOL_LOCK ||
3367                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370                                               i);
3371                                 goto train_done;
3372                         }
3373                         udelay(2); /* should be 1.5us */
3374                 }
3375                 if (i == 4)
3376                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3377         }
3378
3379 train_done:
3380         DRM_DEBUG_KMS("FDI train done.\n");
3381 }
3382
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3384 {
3385         struct drm_device *dev = intel_crtc->base.dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         int pipe = intel_crtc->pipe;
3388         u32 reg, temp;
3389
3390
3391         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392         reg = FDI_RX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399         POSTING_READ(reg);
3400         udelay(200);
3401
3402         /* Switch from Rawclk to PCDclk */
3403         temp = I915_READ(reg);
3404         I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406         POSTING_READ(reg);
3407         udelay(200);
3408
3409         /* Enable CPU FDI TX PLL, always on for Ironlake */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3414
3415                 POSTING_READ(reg);
3416                 udelay(100);
3417         }
3418 }
3419
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp;
3426
3427         /* Switch from PCDclk to Rawclk */
3428         reg = FDI_RX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432         /* Disable CPU FDI TX PLL */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444         /* Wait for the clocks to turn off. */
3445         POSTING_READ(reg);
3446         udelay(100);
3447 }
3448
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         /* disable CPU FDI tx and PCH FDI rx */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461         POSTING_READ(reg);
3462
3463         reg = FDI_RX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~(0x7 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471
3472         /* Ironlake workaround, disable clock pointer after downing FDI */
3473         if (HAS_PCH_IBX(dev))
3474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3475
3476         /* still set train pattern 1 */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_LINK_TRAIN_NONE;
3480         temp |= FDI_LINK_TRAIN_PATTERN_1;
3481         I915_WRITE(reg, temp);
3482
3483         reg = FDI_RX_CTL(pipe);
3484         temp = I915_READ(reg);
3485         if (HAS_PCH_CPT(dev)) {
3486                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488         } else {
3489                 temp &= ~FDI_LINK_TRAIN_NONE;
3490                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491         }
3492         /* BPC in FDI rx is consistent with that in PIPECONF */
3493         temp &= ~(0x07 << 16);
3494         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495         I915_WRITE(reg, temp);
3496
3497         POSTING_READ(reg);
3498         udelay(100);
3499 }
3500
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502 {
3503         struct intel_crtc *crtc;
3504
3505         /* Note that we don't need to be called with mode_config.lock here
3506          * as our list of CRTC objects is static for the lifetime of the
3507          * device and so cannot disappear as we iterate. Similarly, we can
3508          * happily treat the predicates as racy, atomic checks as userspace
3509          * cannot claim and pin a new fb without at least acquring the
3510          * struct_mutex and so serialising with us.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (atomic_read(&crtc->unpin_work_count) == 0)
3514                         continue;
3515
3516                 if (crtc->unpin_work)
3517                         intel_wait_for_vblank(dev, crtc->pipe);
3518
3519                 return true;
3520         }
3521
3522         return false;
3523 }
3524
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3526 {
3527         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528         struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530         /* ensure that the unpin work is consistent wrt ->pending. */
3531         smp_rmb();
3532         intel_crtc->unpin_work = NULL;
3533
3534         if (work->event)
3535                 drm_send_vblank_event(intel_crtc->base.dev,
3536                                       intel_crtc->pipe,
3537                                       work->event);
3538
3539         drm_crtc_vblank_put(&intel_crtc->base);
3540
3541         wake_up_all(&dev_priv->pending_flip_queue);
3542         queue_work(dev_priv->wq, &work->work);
3543
3544         trace_i915_flip_complete(intel_crtc->plane,
3545                                  work->pending_flip_obj);
3546 }
3547
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555                                        !intel_crtc_has_pending_flip(crtc),
3556                                        60*HZ) == 0)) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558
3559                 spin_lock_irq(&dev->event_lock);
3560                 if (intel_crtc->unpin_work) {
3561                         WARN_ONCE(1, "Removing stuck page flip\n");
3562                         page_flip_completed(intel_crtc);
3563                 }
3564                 spin_unlock_irq(&dev->event_lock);
3565         }
3566
3567         if (crtc->primary->fb) {
3568                 mutex_lock(&dev->struct_mutex);
3569                 intel_finish_fb(crtc->primary->fb);
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572 }
3573
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581         u32 temp;
3582
3583         mutex_lock(&dev_priv->dpio_lock);
3584
3585         /* It is necessary to ungate the pixclk gate prior to programming
3586          * the divisors, and gate it back when it is done.
3587          */
3588         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590         /* Disable SSCCTL */
3591         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593                                 SBI_SSCCTL_DISABLE,
3594                         SBI_ICLK);
3595
3596         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597         if (clock == 20000) {
3598                 auxdiv = 1;
3599                 divsel = 0x41;
3600                 phaseinc = 0x20;
3601         } else {
3602                 /* The iCLK virtual clock root frequency is in MHz,
3603                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3604                  * divisors, it is necessary to divide one by another, so we
3605                  * convert the virtual clock precision to KHz here for higher
3606                  * precision.
3607                  */
3608                 u32 iclk_virtual_root_freq = 172800 * 1000;
3609                 u32 iclk_pi_range = 64;
3610                 u32 desired_divisor, msb_divisor_value, pi_value;
3611
3612                 desired_divisor = (iclk_virtual_root_freq / clock);
3613                 msb_divisor_value = desired_divisor / iclk_pi_range;
3614                 pi_value = desired_divisor % iclk_pi_range;
3615
3616                 auxdiv = 0;
3617                 divsel = msb_divisor_value - 2;
3618                 phaseinc = pi_value;
3619         }
3620
3621         /* This should not happen with any sane values */
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3628                         clock,
3629                         auxdiv,
3630                         divsel,
3631                         phasedir,
3632                         phaseinc);
3633
3634         /* Program SSCDIVINTPHASE6 */
3635         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3643
3644         /* Program SSCAUXDIV */
3645         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3649
3650         /* Enable modulator and associated divider */
3651         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652         temp &= ~SBI_SSCCTL_DISABLE;
3653         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3654
3655         /* Wait for initialization time */
3656         udelay(24);
3657
3658         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3659
3660         mutex_unlock(&dev_priv->dpio_lock);
3661 }
3662
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664                                                 enum pipe pch_transcoder)
3665 {
3666         struct drm_device *dev = crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671                    I915_READ(HTOTAL(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673                    I915_READ(HBLANK(cpu_transcoder)));
3674         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675                    I915_READ(HSYNC(cpu_transcoder)));
3676
3677         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678                    I915_READ(VTOTAL(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680                    I915_READ(VBLANK(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682                    I915_READ(VSYNC(cpu_transcoder)));
3683         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685 }
3686
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         uint32_t temp;
3691
3692         temp = I915_READ(SOUTH_CHICKEN1);
3693         if (temp & FDI_BC_BIFURCATION_SELECT)
3694                 return;
3695
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699         temp |= FDI_BC_BIFURCATION_SELECT;
3700         DRM_DEBUG_KMS("enabling fdi C rx\n");
3701         I915_WRITE(SOUTH_CHICKEN1, temp);
3702         POSTING_READ(SOUTH_CHICKEN1);
3703 }
3704
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706 {
3707         struct drm_device *dev = intel_crtc->base.dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         switch (intel_crtc->pipe) {
3711         case PIPE_A:
3712                 break;
3713         case PIPE_B:
3714                 if (intel_crtc->config.fdi_lanes > 2)
3715                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716                 else
3717                         cpt_enable_fdi_bc_bifurcation(dev);
3718
3719                 break;
3720         case PIPE_C:
3721                 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723                 break;
3724         default:
3725                 BUG();
3726         }
3727 }
3728
3729 /*
3730  * Enable PCH resources required for PCH ports:
3731  *   - PCH PLLs
3732  *   - FDI training & RX/TX
3733  *   - update transcoder timings
3734  *   - DP transcoding bits
3735  *   - transcoder
3736  */
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745         assert_pch_transcoder_disabled(dev_priv, pipe);
3746
3747         if (IS_IVYBRIDGE(dev))
3748                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
3750         /* Write the TU size bits before fdi link training, so that error
3751          * detection works. */
3752         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
3755         /* For PCH output, training FDI link */
3756         dev_priv->display.fdi_link_train(crtc);
3757
3758         /* We need to program the right clock selection before writing the pixel
3759          * mutliplier into the DPLL. */
3760         if (HAS_PCH_CPT(dev)) {
3761                 u32 sel;
3762
3763                 temp = I915_READ(PCH_DPLL_SEL);
3764                 temp |= TRANS_DPLL_ENABLE(pipe);
3765                 sel = TRANS_DPLLB_SEL(pipe);
3766                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3767                         temp |= sel;
3768                 else
3769                         temp &= ~sel;
3770                 I915_WRITE(PCH_DPLL_SEL, temp);
3771         }
3772
3773         /* XXX: pch pll's can be enabled any time before we enable the PCH
3774          * transcoder, and we actually should do this to not upset any PCH
3775          * transcoder that already use the clock when we share it.
3776          *
3777          * Note that enable_shared_dpll tries to do the right thing, but
3778          * get_shared_dpll unconditionally resets the pll - we need that to have
3779          * the right LVDS enable sequence. */
3780         intel_enable_shared_dpll(intel_crtc);
3781
3782         /* set transcoder timing, panel must allow it */
3783         assert_panel_unlocked(dev_priv, pipe);
3784         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3785
3786         intel_fdi_normal_train(crtc);
3787
3788         /* For PCH DP, enable TRANS_DP_CTL */
3789         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791                 reg = TRANS_DP_CTL(pipe);
3792                 temp = I915_READ(reg);
3793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794                           TRANS_DP_SYNC_MASK |
3795                           TRANS_DP_BPC_MASK);
3796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797                          TRANS_DP_ENH_FRAMING);
3798                 temp |= bpc << 9; /* same format but at 11:9 */
3799
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3804
3805                 switch (intel_trans_dp_port_sel(crtc)) {
3806                 case PCH_DP_B:
3807                         temp |= TRANS_DP_PORT_SEL_B;
3808                         break;
3809                 case PCH_DP_C:
3810                         temp |= TRANS_DP_PORT_SEL_C;
3811                         break;
3812                 case PCH_DP_D:
3813                         temp |= TRANS_DP_PORT_SEL_D;
3814                         break;
3815                 default:
3816                         BUG();
3817                 }
3818
3819                 I915_WRITE(reg, temp);
3820         }
3821
3822         ironlake_enable_pch_transcoder(dev_priv, pipe);
3823 }
3824
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3833
3834         lpt_program_iclkip(crtc);
3835
3836         /* Set transcoder timing. */
3837         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3838
3839         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3840 }
3841
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3843 {
3844         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3845
3846         if (pll == NULL)
3847                 return;
3848
3849         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3850                 WARN(1, "bad %s crtc mask\n", pll->name);
3851                 return;
3852         }
3853
3854         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3855         if (pll->config.crtc_mask == 0) {
3856                 WARN_ON(pll->on);
3857                 WARN_ON(pll->active);
3858         }
3859
3860         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3861 }
3862
3863 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3864 {
3865         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3866         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3867         enum intel_dpll_id i;
3868
3869         if (pll) {
3870                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3871                               crtc->base.base.id, pll->name);
3872                 intel_put_shared_dpll(crtc);
3873         }
3874
3875         if (HAS_PCH_IBX(dev_priv->dev)) {
3876                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3877                 i = (enum intel_dpll_id) crtc->pipe;
3878                 pll = &dev_priv->shared_dplls[i];
3879
3880                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3881                               crtc->base.base.id, pll->name);
3882
3883                 WARN_ON(pll->config.crtc_mask);
3884
3885                 goto found;
3886         }
3887
3888         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3889                 pll = &dev_priv->shared_dplls[i];
3890
3891                 /* Only want to check enabled timings first */
3892                 if (pll->config.crtc_mask == 0)
3893                         continue;
3894
3895                 if (memcmp(&crtc->config.dpll_hw_state,
3896                            &pll->config.hw_state,
3897                            sizeof(pll->config.hw_state)) == 0) {
3898                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s "
3899                                       "(crtc_mask 0x%08x, active %d)\n",
3900                                       crtc->base.base.id, pll->name,
3901                                       pll->config.crtc_mask, pll->active);
3902
3903                         goto found;
3904                 }
3905         }
3906
3907         /* Ok no matching timings, maybe there's a free one? */
3908         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3909                 pll = &dev_priv->shared_dplls[i];
3910                 if (pll->config.crtc_mask == 0) {
3911                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3912                                       crtc->base.base.id, pll->name);
3913                         goto found;
3914                 }
3915         }
3916
3917         return NULL;
3918
3919 found:
3920         if (pll->config.crtc_mask == 0)
3921                 pll->config.hw_state = crtc->config.dpll_hw_state;
3922
3923         crtc->config.shared_dpll = i;
3924         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3925                          pipe_name(crtc->pipe));
3926
3927         pll->config.crtc_mask |= 1 << crtc->pipe;
3928
3929         return pll;
3930 }
3931
3932 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3933 {
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935         int dslreg = PIPEDSL(pipe);
3936         u32 temp;
3937
3938         temp = I915_READ(dslreg);
3939         udelay(500);
3940         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3941                 if (wait_for(I915_READ(dslreg) != temp, 5))
3942                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3943         }
3944 }
3945
3946 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3947 {
3948         struct drm_device *dev = crtc->base.dev;
3949         struct drm_i915_private *dev_priv = dev->dev_private;
3950         int pipe = crtc->pipe;
3951
3952         if (crtc->config.pch_pfit.enabled) {
3953                 /* Force use of hard-coded filter coefficients
3954                  * as some pre-programmed values are broken,
3955                  * e.g. x201.
3956                  */
3957                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3958                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3959                                                  PF_PIPE_SEL_IVB(pipe));
3960                 else
3961                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3962                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3963                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3964         }
3965 }
3966
3967 static void intel_enable_planes(struct drm_crtc *crtc)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3971         struct drm_plane *plane;
3972         struct intel_plane *intel_plane;
3973
3974         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3975                 intel_plane = to_intel_plane(plane);
3976                 if (intel_plane->pipe == pipe)
3977                         intel_plane_restore(&intel_plane->base);
3978         }
3979 }
3980
3981 static void intel_disable_planes(struct drm_crtc *crtc)
3982 {
3983         struct drm_device *dev = crtc->dev;
3984         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3985         struct drm_plane *plane;
3986         struct intel_plane *intel_plane;
3987
3988         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3989                 intel_plane = to_intel_plane(plane);
3990                 if (intel_plane->pipe == pipe)
3991                         intel_plane_disable(&intel_plane->base);
3992         }
3993 }
3994
3995 void hsw_enable_ips(struct intel_crtc *crtc)
3996 {
3997         struct drm_device *dev = crtc->base.dev;
3998         struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000         if (!crtc->config.ips_enabled)
4001                 return;
4002
4003         /* We can only enable IPS after we enable a plane and wait for a vblank */
4004         intel_wait_for_vblank(dev, crtc->pipe);
4005
4006         assert_plane_enabled(dev_priv, crtc->plane);
4007         if (IS_BROADWELL(dev)) {
4008                 mutex_lock(&dev_priv->rps.hw_lock);
4009                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4010                 mutex_unlock(&dev_priv->rps.hw_lock);
4011                 /* Quoting Art Runyan: "its not safe to expect any particular
4012                  * value in IPS_CTL bit 31 after enabling IPS through the
4013                  * mailbox." Moreover, the mailbox may return a bogus state,
4014                  * so we need to just enable it and continue on.
4015                  */
4016         } else {
4017                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4018                 /* The bit only becomes 1 in the next vblank, so this wait here
4019                  * is essentially intel_wait_for_vblank. If we don't have this
4020                  * and don't wait for vblanks until the end of crtc_enable, then
4021                  * the HW state readout code will complain that the expected
4022                  * IPS_CTL value is not the one we read. */
4023                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4024                         DRM_ERROR("Timed out waiting for IPS enable\n");
4025         }
4026 }
4027
4028 void hsw_disable_ips(struct intel_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->base.dev;
4031         struct drm_i915_private *dev_priv = dev->dev_private;
4032
4033         if (!crtc->config.ips_enabled)
4034                 return;
4035
4036         assert_plane_enabled(dev_priv, crtc->plane);
4037         if (IS_BROADWELL(dev)) {
4038                 mutex_lock(&dev_priv->rps.hw_lock);
4039                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4040                 mutex_unlock(&dev_priv->rps.hw_lock);
4041                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4042                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4043                         DRM_ERROR("Timed out waiting for IPS disable\n");
4044         } else {
4045                 I915_WRITE(IPS_CTL, 0);
4046                 POSTING_READ(IPS_CTL);
4047         }
4048
4049         /* We need to wait for a vblank before we can disable the plane. */
4050         intel_wait_for_vblank(dev, crtc->pipe);
4051 }
4052
4053 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4054 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4055 {
4056         struct drm_device *dev = crtc->dev;
4057         struct drm_i915_private *dev_priv = dev->dev_private;
4058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4059         enum pipe pipe = intel_crtc->pipe;
4060         int palreg = PALETTE(pipe);
4061         int i;
4062         bool reenable_ips = false;
4063
4064         /* The clocks have to be on to load the palette. */
4065         if (!crtc->enabled || !intel_crtc->active)
4066                 return;
4067
4068         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4069                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4070                         assert_dsi_pll_enabled(dev_priv);
4071                 else
4072                         assert_pll_enabled(dev_priv, pipe);
4073         }
4074
4075         /* use legacy palette for Ironlake */
4076         if (!HAS_GMCH_DISPLAY(dev))
4077                 palreg = LGC_PALETTE(pipe);
4078
4079         /* Workaround : Do not read or write the pipe palette/gamma data while
4080          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4081          */
4082         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4083             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4084              GAMMA_MODE_MODE_SPLIT)) {
4085                 hsw_disable_ips(intel_crtc);
4086                 reenable_ips = true;
4087         }
4088
4089         for (i = 0; i < 256; i++) {
4090                 I915_WRITE(palreg + 4 * i,
4091                            (intel_crtc->lut_r[i] << 16) |
4092                            (intel_crtc->lut_g[i] << 8) |
4093                            intel_crtc->lut_b[i]);
4094         }
4095
4096         if (reenable_ips)
4097                 hsw_enable_ips(intel_crtc);
4098 }
4099
4100 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4101 {
4102         if (!enable && intel_crtc->overlay) {
4103                 struct drm_device *dev = intel_crtc->base.dev;
4104                 struct drm_i915_private *dev_priv = dev->dev_private;
4105
4106                 mutex_lock(&dev->struct_mutex);
4107                 dev_priv->mm.interruptible = false;
4108                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4109                 dev_priv->mm.interruptible = true;
4110                 mutex_unlock(&dev->struct_mutex);
4111         }
4112
4113         /* Let userspace switch the overlay on again. In most cases userspace
4114          * has to recompute where to put it anyway.
4115          */
4116 }
4117
4118 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4119 {
4120         struct drm_device *dev = crtc->dev;
4121         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4122         int pipe = intel_crtc->pipe;
4123
4124         intel_enable_primary_hw_plane(crtc->primary, crtc);
4125         intel_enable_planes(crtc);
4126         intel_crtc_update_cursor(crtc, true);
4127         intel_crtc_dpms_overlay(intel_crtc, true);
4128
4129         hsw_enable_ips(intel_crtc);
4130
4131         mutex_lock(&dev->struct_mutex);
4132         intel_update_fbc(dev);
4133         mutex_unlock(&dev->struct_mutex);
4134
4135         /*
4136          * FIXME: Once we grow proper nuclear flip support out of this we need
4137          * to compute the mask of flip planes precisely. For the time being
4138          * consider this a flip from a NULL plane.
4139          */
4140         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4141 }
4142
4143 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         int pipe = intel_crtc->pipe;
4149         int plane = intel_crtc->plane;
4150
4151         intel_crtc_wait_for_pending_flips(crtc);
4152
4153         if (dev_priv->fbc.plane == plane)
4154                 intel_disable_fbc(dev);
4155
4156         hsw_disable_ips(intel_crtc);
4157
4158         intel_crtc_dpms_overlay(intel_crtc, false);
4159         intel_crtc_update_cursor(crtc, false);
4160         intel_disable_planes(crtc);
4161         intel_disable_primary_hw_plane(crtc->primary, crtc);
4162
4163         /*
4164          * FIXME: Once we grow proper nuclear flip support out of this we need
4165          * to compute the mask of flip planes precisely. For the time being
4166          * consider this a flip to a NULL plane.
4167          */
4168         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4169 }
4170
4171 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4172 {
4173         struct drm_device *dev = crtc->dev;
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176         struct intel_encoder *encoder;
4177         int pipe = intel_crtc->pipe;
4178
4179         WARN_ON(!crtc->enabled);
4180
4181         if (intel_crtc->active)
4182                 return;
4183
4184         if (intel_crtc->config.has_pch_encoder)
4185                 intel_prepare_shared_dpll(intel_crtc);
4186
4187         if (intel_crtc->config.has_dp_encoder)
4188                 intel_dp_set_m_n(intel_crtc);
4189
4190         intel_set_pipe_timings(intel_crtc);
4191
4192         if (intel_crtc->config.has_pch_encoder) {
4193                 intel_cpu_transcoder_set_m_n(intel_crtc,
4194                                      &intel_crtc->config.fdi_m_n, NULL);
4195         }
4196
4197         ironlake_set_pipeconf(crtc);
4198
4199         intel_crtc->active = true;
4200
4201         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4202         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4203
4204         for_each_encoder_on_crtc(dev, crtc, encoder)
4205                 if (encoder->pre_enable)
4206                         encoder->pre_enable(encoder);
4207
4208         if (intel_crtc->config.has_pch_encoder) {
4209                 /* Note: FDI PLL enabling _must_ be done before we enable the
4210                  * cpu pipes, hence this is separate from all the other fdi/pch
4211                  * enabling. */
4212                 ironlake_fdi_pll_enable(intel_crtc);
4213         } else {
4214                 assert_fdi_tx_disabled(dev_priv, pipe);
4215                 assert_fdi_rx_disabled(dev_priv, pipe);
4216         }
4217
4218         ironlake_pfit_enable(intel_crtc);
4219
4220         /*
4221          * On ILK+ LUT must be loaded before the pipe is running but with
4222          * clocks enabled
4223          */
4224         intel_crtc_load_lut(crtc);
4225
4226         intel_update_watermarks(crtc);
4227         intel_enable_pipe(intel_crtc);
4228
4229         if (intel_crtc->config.has_pch_encoder)
4230                 ironlake_pch_enable(crtc);
4231
4232         for_each_encoder_on_crtc(dev, crtc, encoder)
4233                 encoder->enable(encoder);
4234
4235         if (HAS_PCH_CPT(dev))
4236                 cpt_verify_modeset(dev, intel_crtc->pipe);
4237
4238         assert_vblank_disabled(crtc);
4239         drm_crtc_vblank_on(crtc);
4240
4241         intel_crtc_enable_planes(crtc);
4242 }
4243
4244 /* IPS only exists on ULT machines and is tied to pipe A. */
4245 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4246 {
4247         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4248 }
4249
4250 /*
4251  * This implements the workaround described in the "notes" section of the mode
4252  * set sequence documentation. When going from no pipes or single pipe to
4253  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4254  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4255  */
4256 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4257 {
4258         struct drm_device *dev = crtc->base.dev;
4259         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4260
4261         /* We want to get the other_active_crtc only if there's only 1 other
4262          * active crtc. */
4263         for_each_intel_crtc(dev, crtc_it) {
4264                 if (!crtc_it->active || crtc_it == crtc)
4265                         continue;
4266
4267                 if (other_active_crtc)
4268                         return;
4269
4270                 other_active_crtc = crtc_it;
4271         }
4272         if (!other_active_crtc)
4273                 return;
4274
4275         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4276         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4277 }
4278
4279 static void haswell_crtc_enable(struct drm_crtc *crtc)
4280 {
4281         struct drm_device *dev = crtc->dev;
4282         struct drm_i915_private *dev_priv = dev->dev_private;
4283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284         struct intel_encoder *encoder;
4285         int pipe = intel_crtc->pipe;
4286
4287         WARN_ON(!crtc->enabled);
4288
4289         if (intel_crtc->active)
4290                 return;
4291
4292         if (intel_crtc_to_shared_dpll(intel_crtc))
4293                 intel_enable_shared_dpll(intel_crtc);
4294
4295         if (intel_crtc->config.has_dp_encoder)
4296                 intel_dp_set_m_n(intel_crtc);
4297
4298         intel_set_pipe_timings(intel_crtc);
4299
4300         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4301                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4302                            intel_crtc->config.pixel_multiplier - 1);
4303         }
4304
4305         if (intel_crtc->config.has_pch_encoder) {
4306                 intel_cpu_transcoder_set_m_n(intel_crtc,
4307                                      &intel_crtc->config.fdi_m_n, NULL);
4308         }
4309
4310         haswell_set_pipeconf(crtc);
4311
4312         intel_set_pipe_csc(crtc);
4313
4314         intel_crtc->active = true;
4315
4316         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4317         for_each_encoder_on_crtc(dev, crtc, encoder)
4318                 if (encoder->pre_enable)
4319                         encoder->pre_enable(encoder);
4320
4321         if (intel_crtc->config.has_pch_encoder) {
4322                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4323                                                       true);
4324                 dev_priv->display.fdi_link_train(crtc);
4325         }
4326
4327         intel_ddi_enable_pipe_clock(intel_crtc);
4328
4329         ironlake_pfit_enable(intel_crtc);
4330
4331         /*
4332          * On ILK+ LUT must be loaded before the pipe is running but with
4333          * clocks enabled
4334          */
4335         intel_crtc_load_lut(crtc);
4336
4337         intel_ddi_set_pipe_settings(crtc);
4338         intel_ddi_enable_transcoder_func(crtc);
4339
4340         intel_update_watermarks(crtc);
4341         intel_enable_pipe(intel_crtc);
4342
4343         if (intel_crtc->config.has_pch_encoder)
4344                 lpt_pch_enable(crtc);
4345
4346         if (intel_crtc->config.dp_encoder_is_mst)
4347                 intel_ddi_set_vc_payload_alloc(crtc, true);
4348
4349         for_each_encoder_on_crtc(dev, crtc, encoder) {
4350                 encoder->enable(encoder);
4351                 intel_opregion_notify_encoder(encoder, true);
4352         }
4353
4354         assert_vblank_disabled(crtc);
4355         drm_crtc_vblank_on(crtc);
4356
4357         /* If we change the relative order between pipe/planes enabling, we need
4358          * to change the workaround. */
4359         haswell_mode_set_planes_workaround(intel_crtc);
4360         intel_crtc_enable_planes(crtc);
4361 }
4362
4363 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4364 {
4365         struct drm_device *dev = crtc->base.dev;
4366         struct drm_i915_private *dev_priv = dev->dev_private;
4367         int pipe = crtc->pipe;
4368
4369         /* To avoid upsetting the power well on haswell only disable the pfit if
4370          * it's in use. The hw state code will make sure we get this right. */
4371         if (crtc->config.pch_pfit.enabled) {
4372                 I915_WRITE(PF_CTL(pipe), 0);
4373                 I915_WRITE(PF_WIN_POS(pipe), 0);
4374                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4375         }
4376 }
4377
4378 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4379 {
4380         struct drm_device *dev = crtc->dev;
4381         struct drm_i915_private *dev_priv = dev->dev_private;
4382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4383         struct intel_encoder *encoder;
4384         int pipe = intel_crtc->pipe;
4385         u32 reg, temp;
4386
4387         if (!intel_crtc->active)
4388                 return;
4389
4390         intel_crtc_disable_planes(crtc);
4391
4392         drm_crtc_vblank_off(crtc);
4393         assert_vblank_disabled(crtc);
4394
4395         for_each_encoder_on_crtc(dev, crtc, encoder)
4396                 encoder->disable(encoder);
4397
4398         if (intel_crtc->config.has_pch_encoder)
4399                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4400
4401         intel_disable_pipe(intel_crtc);
4402
4403         ironlake_pfit_disable(intel_crtc);
4404
4405         for_each_encoder_on_crtc(dev, crtc, encoder)
4406                 if (encoder->post_disable)
4407                         encoder->post_disable(encoder);
4408
4409         if (intel_crtc->config.has_pch_encoder) {
4410                 ironlake_fdi_disable(crtc);
4411
4412                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4413                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4414
4415                 if (HAS_PCH_CPT(dev)) {
4416                         /* disable TRANS_DP_CTL */
4417                         reg = TRANS_DP_CTL(pipe);
4418                         temp = I915_READ(reg);
4419                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4420                                   TRANS_DP_PORT_SEL_MASK);
4421                         temp |= TRANS_DP_PORT_SEL_NONE;
4422                         I915_WRITE(reg, temp);
4423
4424                         /* disable DPLL_SEL */
4425                         temp = I915_READ(PCH_DPLL_SEL);
4426                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4427                         I915_WRITE(PCH_DPLL_SEL, temp);
4428                 }
4429
4430                 /* disable PCH DPLL */
4431                 intel_disable_shared_dpll(intel_crtc);
4432
4433                 ironlake_fdi_pll_disable(intel_crtc);
4434         }
4435
4436         intel_crtc->active = false;
4437         intel_update_watermarks(crtc);
4438
4439         mutex_lock(&dev->struct_mutex);
4440         intel_update_fbc(dev);
4441         mutex_unlock(&dev->struct_mutex);
4442 }
4443
4444 static void haswell_crtc_disable(struct drm_crtc *crtc)
4445 {
4446         struct drm_device *dev = crtc->dev;
4447         struct drm_i915_private *dev_priv = dev->dev_private;
4448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4449         struct intel_encoder *encoder;
4450         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4451
4452         if (!intel_crtc->active)
4453                 return;
4454
4455         intel_crtc_disable_planes(crtc);
4456
4457         drm_crtc_vblank_off(crtc);
4458         assert_vblank_disabled(crtc);
4459
4460         for_each_encoder_on_crtc(dev, crtc, encoder) {
4461                 intel_opregion_notify_encoder(encoder, false);
4462                 encoder->disable(encoder);
4463         }
4464
4465         if (intel_crtc->config.has_pch_encoder)
4466                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4467                                                       false);
4468         intel_disable_pipe(intel_crtc);
4469
4470         if (intel_crtc->config.dp_encoder_is_mst)
4471                 intel_ddi_set_vc_payload_alloc(crtc, false);
4472
4473         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4474
4475         ironlake_pfit_disable(intel_crtc);
4476
4477         intel_ddi_disable_pipe_clock(intel_crtc);
4478
4479         if (intel_crtc->config.has_pch_encoder) {
4480                 lpt_disable_pch_transcoder(dev_priv);
4481                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4482                                                       true);
4483                 intel_ddi_fdi_disable(crtc);
4484         }
4485
4486         for_each_encoder_on_crtc(dev, crtc, encoder)
4487                 if (encoder->post_disable)
4488                         encoder->post_disable(encoder);
4489
4490         intel_crtc->active = false;
4491         intel_update_watermarks(crtc);
4492
4493         mutex_lock(&dev->struct_mutex);
4494         intel_update_fbc(dev);
4495         mutex_unlock(&dev->struct_mutex);
4496
4497         if (intel_crtc_to_shared_dpll(intel_crtc))
4498                 intel_disable_shared_dpll(intel_crtc);
4499 }
4500
4501 static void ironlake_crtc_off(struct drm_crtc *crtc)
4502 {
4503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4504         intel_put_shared_dpll(intel_crtc);
4505 }
4506
4507
4508 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->base.dev;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         struct intel_crtc_config *pipe_config = &crtc->config;
4513
4514         if (!crtc->config.gmch_pfit.control)
4515                 return;
4516
4517         /*
4518          * The panel fitter should only be adjusted whilst the pipe is disabled,
4519          * according to register description and PRM.
4520          */
4521         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4522         assert_pipe_disabled(dev_priv, crtc->pipe);
4523
4524         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4525         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4526
4527         /* Border color in case we don't scale up to the full screen. Black by
4528          * default, change to something else for debugging. */
4529         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4530 }
4531
4532 static enum intel_display_power_domain port_to_power_domain(enum port port)
4533 {
4534         switch (port) {
4535         case PORT_A:
4536                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4537         case PORT_B:
4538                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4539         case PORT_C:
4540                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4541         case PORT_D:
4542                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4543         default:
4544                 WARN_ON_ONCE(1);
4545                 return POWER_DOMAIN_PORT_OTHER;
4546         }
4547 }
4548
4549 #define for_each_power_domain(domain, mask)                             \
4550         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4551                 if ((1 << (domain)) & (mask))
4552
4553 enum intel_display_power_domain
4554 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4555 {
4556         struct drm_device *dev = intel_encoder->base.dev;
4557         struct intel_digital_port *intel_dig_port;
4558
4559         switch (intel_encoder->type) {
4560         case INTEL_OUTPUT_UNKNOWN:
4561                 /* Only DDI platforms should ever use this output type */
4562                 WARN_ON_ONCE(!HAS_DDI(dev));
4563         case INTEL_OUTPUT_DISPLAYPORT:
4564         case INTEL_OUTPUT_HDMI:
4565         case INTEL_OUTPUT_EDP:
4566                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4567                 return port_to_power_domain(intel_dig_port->port);
4568         case INTEL_OUTPUT_DP_MST:
4569                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4570                 return port_to_power_domain(intel_dig_port->port);
4571         case INTEL_OUTPUT_ANALOG:
4572                 return POWER_DOMAIN_PORT_CRT;
4573         case INTEL_OUTPUT_DSI:
4574                 return POWER_DOMAIN_PORT_DSI;
4575         default:
4576                 return POWER_DOMAIN_PORT_OTHER;
4577         }
4578 }
4579
4580 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4581 {
4582         struct drm_device *dev = crtc->dev;
4583         struct intel_encoder *intel_encoder;
4584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4585         enum pipe pipe = intel_crtc->pipe;
4586         unsigned long mask;
4587         enum transcoder transcoder;
4588
4589         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4590
4591         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4592         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4593         if (intel_crtc->config.pch_pfit.enabled ||
4594             intel_crtc->config.pch_pfit.force_thru)
4595                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4596
4597         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4598                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4599
4600         return mask;
4601 }
4602
4603 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4604 {
4605         struct drm_i915_private *dev_priv = dev->dev_private;
4606         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4607         struct intel_crtc *crtc;
4608
4609         /*
4610          * First get all needed power domains, then put all unneeded, to avoid
4611          * any unnecessary toggling of the power wells.
4612          */
4613         for_each_intel_crtc(dev, crtc) {
4614                 enum intel_display_power_domain domain;
4615
4616                 if (!crtc->base.enabled)
4617                         continue;
4618
4619                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4620
4621                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4622                         intel_display_power_get(dev_priv, domain);
4623         }
4624
4625         for_each_intel_crtc(dev, crtc) {
4626                 enum intel_display_power_domain domain;
4627
4628                 for_each_power_domain(domain, crtc->enabled_power_domains)
4629                         intel_display_power_put(dev_priv, domain);
4630
4631                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4632         }
4633
4634         intel_display_set_init_power(dev_priv, false);
4635 }
4636
4637 /* returns HPLL frequency in kHz */
4638 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4639 {
4640         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4641
4642         /* Obtain SKU information */
4643         mutex_lock(&dev_priv->dpio_lock);
4644         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4645                 CCK_FUSE_HPLL_FREQ_MASK;
4646         mutex_unlock(&dev_priv->dpio_lock);
4647
4648         return vco_freq[hpll_freq] * 1000;
4649 }
4650
4651 static void vlv_update_cdclk(struct drm_device *dev)
4652 {
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654
4655         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4656         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4657                          dev_priv->vlv_cdclk_freq);
4658
4659         /*
4660          * Program the gmbus_freq based on the cdclk frequency.
4661          * BSpec erroneously claims we should aim for 4MHz, but
4662          * in fact 1MHz is the correct frequency.
4663          */
4664         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4665 }
4666
4667 /* Adjust CDclk dividers to allow high res or save power if possible */
4668 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4669 {
4670         struct drm_i915_private *dev_priv = dev->dev_private;
4671         u32 val, cmd;
4672
4673         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4674
4675         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4676                 cmd = 2;
4677         else if (cdclk == 266667)
4678                 cmd = 1;
4679         else
4680                 cmd = 0;
4681
4682         mutex_lock(&dev_priv->rps.hw_lock);
4683         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4684         val &= ~DSPFREQGUAR_MASK;
4685         val |= (cmd << DSPFREQGUAR_SHIFT);
4686         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4687         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4688                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4689                      50)) {
4690                 DRM_ERROR("timed out waiting for CDclk change\n");
4691         }
4692         mutex_unlock(&dev_priv->rps.hw_lock);
4693
4694         if (cdclk == 400000) {
4695                 u32 divider, vco;
4696
4697                 vco = valleyview_get_vco(dev_priv);
4698                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4699
4700                 mutex_lock(&dev_priv->dpio_lock);
4701                 /* adjust cdclk divider */
4702                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4703                 val &= ~DISPLAY_FREQUENCY_VALUES;
4704                 val |= divider;
4705                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4706
4707                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4708                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4709                              50))
4710                         DRM_ERROR("timed out waiting for CDclk change\n");
4711                 mutex_unlock(&dev_priv->dpio_lock);
4712         }
4713
4714         mutex_lock(&dev_priv->dpio_lock);
4715         /* adjust self-refresh exit latency value */
4716         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4717         val &= ~0x7f;
4718
4719         /*
4720          * For high bandwidth configs, we set a higher latency in the bunit
4721          * so that the core display fetch happens in time to avoid underruns.
4722          */
4723         if (cdclk == 400000)
4724                 val |= 4500 / 250; /* 4.5 usec */
4725         else
4726                 val |= 3000 / 250; /* 3.0 usec */
4727         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4728         mutex_unlock(&dev_priv->dpio_lock);
4729
4730         vlv_update_cdclk(dev);
4731 }
4732
4733 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4734 {
4735         struct drm_i915_private *dev_priv = dev->dev_private;
4736         u32 val, cmd;
4737
4738         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4739
4740         switch (cdclk) {
4741         case 400000:
4742                 cmd = 3;
4743                 break;
4744         case 333333:
4745         case 320000:
4746                 cmd = 2;
4747                 break;
4748         case 266667:
4749                 cmd = 1;
4750                 break;
4751         case 200000:
4752                 cmd = 0;
4753                 break;
4754         default:
4755                 WARN_ON(1);
4756                 return;
4757         }
4758
4759         mutex_lock(&dev_priv->rps.hw_lock);
4760         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4761         val &= ~DSPFREQGUAR_MASK_CHV;
4762         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4763         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4764         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4765                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4766                      50)) {
4767                 DRM_ERROR("timed out waiting for CDclk change\n");
4768         }
4769         mutex_unlock(&dev_priv->rps.hw_lock);
4770
4771         vlv_update_cdclk(dev);
4772 }
4773
4774 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4775                                  int max_pixclk)
4776 {
4777         int vco = valleyview_get_vco(dev_priv);
4778         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4779
4780         /* FIXME: Punit isn't quite ready yet */
4781         if (IS_CHERRYVIEW(dev_priv->dev))
4782                 return 400000;
4783
4784         /*
4785          * Really only a few cases to deal with, as only 4 CDclks are supported:
4786          *   200MHz
4787          *   267MHz
4788          *   320/333MHz (depends on HPLL freq)
4789          *   400MHz
4790          * So we check to see whether we're above 90% of the lower bin and
4791          * adjust if needed.
4792          *
4793          * We seem to get an unstable or solid color picture at 200MHz.
4794          * Not sure what's wrong. For now use 200MHz only when all pipes
4795          * are off.
4796          */
4797         if (max_pixclk > freq_320*9/10)
4798                 return 400000;
4799         else if (max_pixclk > 266667*9/10)
4800                 return freq_320;
4801         else if (max_pixclk > 0)
4802                 return 266667;
4803         else
4804                 return 200000;
4805 }
4806
4807 /* compute the max pixel clock for new configuration */
4808 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4809 {
4810         struct drm_device *dev = dev_priv->dev;
4811         struct intel_crtc *intel_crtc;
4812         int max_pixclk = 0;
4813
4814         for_each_intel_crtc(dev, intel_crtc) {
4815                 if (intel_crtc->new_enabled)
4816                         max_pixclk = max(max_pixclk,
4817                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4818         }
4819
4820         return max_pixclk;
4821 }
4822
4823 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4824                                             unsigned *prepare_pipes)
4825 {
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827         struct intel_crtc *intel_crtc;
4828         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4829
4830         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4831             dev_priv->vlv_cdclk_freq)
4832                 return;
4833
4834         /* disable/enable all currently active pipes while we change cdclk */
4835         for_each_intel_crtc(dev, intel_crtc)
4836                 if (intel_crtc->base.enabled)
4837                         *prepare_pipes |= (1 << intel_crtc->pipe);
4838 }
4839
4840 static void valleyview_modeset_global_resources(struct drm_device *dev)
4841 {
4842         struct drm_i915_private *dev_priv = dev->dev_private;
4843         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4844         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4845
4846         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4847                 if (IS_CHERRYVIEW(dev))
4848                         cherryview_set_cdclk(dev, req_cdclk);
4849                 else
4850                         valleyview_set_cdclk(dev, req_cdclk);
4851         }
4852
4853         modeset_update_crtc_power_domains(dev);
4854 }
4855
4856 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4857 {
4858         struct drm_device *dev = crtc->dev;
4859         struct drm_i915_private *dev_priv = to_i915(dev);
4860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4861         struct intel_encoder *encoder;
4862         int pipe = intel_crtc->pipe;
4863         bool is_dsi;
4864
4865         WARN_ON(!crtc->enabled);
4866
4867         if (intel_crtc->active)
4868                 return;
4869
4870         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4871
4872         if (!is_dsi) {
4873                 if (IS_CHERRYVIEW(dev))
4874                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4875                 else
4876                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4877         }
4878
4879         if (intel_crtc->config.has_dp_encoder)
4880                 intel_dp_set_m_n(intel_crtc);
4881
4882         intel_set_pipe_timings(intel_crtc);
4883
4884         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4885                 struct drm_i915_private *dev_priv = dev->dev_private;
4886
4887                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4888                 I915_WRITE(CHV_CANVAS(pipe), 0);
4889         }
4890
4891         i9xx_set_pipeconf(intel_crtc);
4892
4893         intel_crtc->active = true;
4894
4895         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4896
4897         for_each_encoder_on_crtc(dev, crtc, encoder)
4898                 if (encoder->pre_pll_enable)
4899                         encoder->pre_pll_enable(encoder);
4900
4901         if (!is_dsi) {
4902                 if (IS_CHERRYVIEW(dev))
4903                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4904                 else
4905                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4906         }
4907
4908         for_each_encoder_on_crtc(dev, crtc, encoder)
4909                 if (encoder->pre_enable)
4910                         encoder->pre_enable(encoder);
4911
4912         i9xx_pfit_enable(intel_crtc);
4913
4914         intel_crtc_load_lut(crtc);
4915
4916         intel_update_watermarks(crtc);
4917         intel_enable_pipe(intel_crtc);
4918
4919         for_each_encoder_on_crtc(dev, crtc, encoder)
4920                 encoder->enable(encoder);
4921
4922         assert_vblank_disabled(crtc);
4923         drm_crtc_vblank_on(crtc);
4924
4925         intel_crtc_enable_planes(crtc);
4926
4927         /* Underruns don't raise interrupts, so check manually. */
4928         i9xx_check_fifo_underruns(dev_priv);
4929 }
4930
4931 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4932 {
4933         struct drm_device *dev = crtc->base.dev;
4934         struct drm_i915_private *dev_priv = dev->dev_private;
4935
4936         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4937         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4938 }
4939
4940 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4941 {
4942         struct drm_device *dev = crtc->dev;
4943         struct drm_i915_private *dev_priv = to_i915(dev);
4944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945         struct intel_encoder *encoder;
4946         int pipe = intel_crtc->pipe;
4947
4948         WARN_ON(!crtc->enabled);
4949
4950         if (intel_crtc->active)
4951                 return;
4952
4953         i9xx_set_pll_dividers(intel_crtc);
4954
4955         if (intel_crtc->config.has_dp_encoder)
4956                 intel_dp_set_m_n(intel_crtc);
4957
4958         intel_set_pipe_timings(intel_crtc);
4959
4960         i9xx_set_pipeconf(intel_crtc);
4961
4962         intel_crtc->active = true;
4963
4964         if (!IS_GEN2(dev))
4965                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4966
4967         for_each_encoder_on_crtc(dev, crtc, encoder)
4968                 if (encoder->pre_enable)
4969                         encoder->pre_enable(encoder);
4970
4971         i9xx_enable_pll(intel_crtc);
4972
4973         i9xx_pfit_enable(intel_crtc);
4974
4975         intel_crtc_load_lut(crtc);
4976
4977         intel_update_watermarks(crtc);
4978         intel_enable_pipe(intel_crtc);
4979
4980         for_each_encoder_on_crtc(dev, crtc, encoder)
4981                 encoder->enable(encoder);
4982
4983         assert_vblank_disabled(crtc);
4984         drm_crtc_vblank_on(crtc);
4985
4986         intel_crtc_enable_planes(crtc);
4987
4988         /*
4989          * Gen2 reports pipe underruns whenever all planes are disabled.
4990          * So don't enable underrun reporting before at least some planes
4991          * are enabled.
4992          * FIXME: Need to fix the logic to work when we turn off all planes
4993          * but leave the pipe running.
4994          */
4995         if (IS_GEN2(dev))
4996                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4997
4998         /* Underruns don't raise interrupts, so check manually. */
4999         i9xx_check_fifo_underruns(dev_priv);
5000 }
5001
5002 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5003 {
5004         struct drm_device *dev = crtc->base.dev;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006
5007         if (!crtc->config.gmch_pfit.control)
5008                 return;
5009
5010         assert_pipe_disabled(dev_priv, crtc->pipe);
5011
5012         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5013                          I915_READ(PFIT_CONTROL));
5014         I915_WRITE(PFIT_CONTROL, 0);
5015 }
5016
5017 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5018 {
5019         struct drm_device *dev = crtc->dev;
5020         struct drm_i915_private *dev_priv = dev->dev_private;
5021         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5022         struct intel_encoder *encoder;
5023         int pipe = intel_crtc->pipe;
5024
5025         if (!intel_crtc->active)
5026                 return;
5027
5028         /*
5029          * Gen2 reports pipe underruns whenever all planes are disabled.
5030          * So diasble underrun reporting before all the planes get disabled.
5031          * FIXME: Need to fix the logic to work when we turn off all planes
5032          * but leave the pipe running.
5033          */
5034         if (IS_GEN2(dev))
5035                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5036
5037         /*
5038          * Vblank time updates from the shadow to live plane control register
5039          * are blocked if the memory self-refresh mode is active at that
5040          * moment. So to make sure the plane gets truly disabled, disable
5041          * first the self-refresh mode. The self-refresh enable bit in turn
5042          * will be checked/applied by the HW only at the next frame start
5043          * event which is after the vblank start event, so we need to have a
5044          * wait-for-vblank between disabling the plane and the pipe.
5045          */
5046         intel_set_memory_cxsr(dev_priv, false);
5047         intel_crtc_disable_planes(crtc);
5048
5049         /*
5050          * On gen2 planes are double buffered but the pipe isn't, so we must
5051          * wait for planes to fully turn off before disabling the pipe.
5052          * We also need to wait on all gmch platforms because of the
5053          * self-refresh mode constraint explained above.
5054          */
5055         intel_wait_for_vblank(dev, pipe);
5056
5057         drm_crtc_vblank_off(crtc);
5058         assert_vblank_disabled(crtc);
5059
5060         for_each_encoder_on_crtc(dev, crtc, encoder)
5061                 encoder->disable(encoder);
5062
5063         intel_disable_pipe(intel_crtc);
5064
5065         i9xx_pfit_disable(intel_crtc);
5066
5067         for_each_encoder_on_crtc(dev, crtc, encoder)
5068                 if (encoder->post_disable)
5069                         encoder->post_disable(encoder);
5070
5071         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5072                 if (IS_CHERRYVIEW(dev))
5073                         chv_disable_pll(dev_priv, pipe);
5074                 else if (IS_VALLEYVIEW(dev))
5075                         vlv_disable_pll(dev_priv, pipe);
5076                 else
5077                         i9xx_disable_pll(intel_crtc);
5078         }
5079
5080         if (!IS_GEN2(dev))
5081                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5082
5083         intel_crtc->active = false;
5084         intel_update_watermarks(crtc);
5085
5086         mutex_lock(&dev->struct_mutex);
5087         intel_update_fbc(dev);
5088         mutex_unlock(&dev->struct_mutex);
5089 }
5090
5091 static void i9xx_crtc_off(struct drm_crtc *crtc)
5092 {
5093 }
5094
5095 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5096                                     bool enabled)
5097 {
5098         struct drm_device *dev = crtc->dev;
5099         struct drm_i915_master_private *master_priv;
5100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101         int pipe = intel_crtc->pipe;
5102
5103         if (!dev->primary->master)
5104                 return;
5105
5106         master_priv = dev->primary->master->driver_priv;
5107         if (!master_priv->sarea_priv)
5108                 return;
5109
5110         switch (pipe) {
5111         case 0:
5112                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5113                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5114                 break;
5115         case 1:
5116                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5117                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5118                 break;
5119         default:
5120                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5121                 break;
5122         }
5123 }
5124
5125 /* Master function to enable/disable CRTC and corresponding power wells */
5126 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5127 {
5128         struct drm_device *dev = crtc->dev;
5129         struct drm_i915_private *dev_priv = dev->dev_private;
5130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131         enum intel_display_power_domain domain;
5132         unsigned long domains;
5133
5134         if (enable) {
5135                 if (!intel_crtc->active) {
5136                         domains = get_crtc_power_domains(crtc);
5137                         for_each_power_domain(domain, domains)
5138                                 intel_display_power_get(dev_priv, domain);
5139                         intel_crtc->enabled_power_domains = domains;
5140
5141                         dev_priv->display.crtc_enable(crtc);
5142                 }
5143         } else {
5144                 if (intel_crtc->active) {
5145                         dev_priv->display.crtc_disable(crtc);
5146
5147                         domains = intel_crtc->enabled_power_domains;
5148                         for_each_power_domain(domain, domains)
5149                                 intel_display_power_put(dev_priv, domain);
5150                         intel_crtc->enabled_power_domains = 0;
5151                 }
5152         }
5153 }
5154
5155 /**
5156  * Sets the power management mode of the pipe and plane.
5157  */
5158 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5159 {
5160         struct drm_device *dev = crtc->dev;
5161         struct intel_encoder *intel_encoder;
5162         bool enable = false;
5163
5164         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5165                 enable |= intel_encoder->connectors_active;
5166
5167         intel_crtc_control(crtc, enable);
5168
5169         intel_crtc_update_sarea(crtc, enable);
5170 }
5171
5172 static void intel_crtc_disable(struct drm_crtc *crtc)
5173 {
5174         struct drm_device *dev = crtc->dev;
5175         struct drm_connector *connector;
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5178         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5179
5180         /* crtc should still be enabled when we disable it. */
5181         WARN_ON(!crtc->enabled);
5182
5183         dev_priv->display.crtc_disable(crtc);
5184         intel_crtc_update_sarea(crtc, false);
5185         dev_priv->display.off(crtc);
5186
5187         if (crtc->primary->fb) {
5188                 mutex_lock(&dev->struct_mutex);
5189                 intel_unpin_fb_obj(old_obj);
5190                 i915_gem_track_fb(old_obj, NULL,
5191                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5192                 mutex_unlock(&dev->struct_mutex);
5193                 crtc->primary->fb = NULL;
5194         }
5195
5196         /* Update computed state. */
5197         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5198                 if (!connector->encoder || !connector->encoder->crtc)
5199                         continue;
5200
5201                 if (connector->encoder->crtc != crtc)
5202                         continue;
5203
5204                 connector->dpms = DRM_MODE_DPMS_OFF;
5205                 to_intel_encoder(connector->encoder)->connectors_active = false;
5206         }
5207 }
5208
5209 void intel_encoder_destroy(struct drm_encoder *encoder)
5210 {
5211         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5212
5213         drm_encoder_cleanup(encoder);
5214         kfree(intel_encoder);
5215 }
5216
5217 /* Simple dpms helper for encoders with just one connector, no cloning and only
5218  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5219  * state of the entire output pipe. */
5220 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5221 {
5222         if (mode == DRM_MODE_DPMS_ON) {
5223                 encoder->connectors_active = true;
5224
5225                 intel_crtc_update_dpms(encoder->base.crtc);
5226         } else {
5227                 encoder->connectors_active = false;
5228
5229                 intel_crtc_update_dpms(encoder->base.crtc);
5230         }
5231 }
5232
5233 /* Cross check the actual hw state with our own modeset state tracking (and it's
5234  * internal consistency). */
5235 static void intel_connector_check_state(struct intel_connector *connector)
5236 {
5237         if (connector->get_hw_state(connector)) {
5238                 struct intel_encoder *encoder = connector->encoder;
5239                 struct drm_crtc *crtc;
5240                 bool encoder_enabled;
5241                 enum pipe pipe;
5242
5243                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5244                               connector->base.base.id,
5245                               connector->base.name);
5246
5247                 /* there is no real hw state for MST connectors */
5248                 if (connector->mst_port)
5249                         return;
5250
5251                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5252                      "wrong connector dpms state\n");
5253                 WARN(connector->base.encoder != &encoder->base,
5254                      "active connector not linked to encoder\n");
5255
5256                 if (encoder) {
5257                         WARN(!encoder->connectors_active,
5258                              "encoder->connectors_active not set\n");
5259
5260                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5261                         WARN(!encoder_enabled, "encoder not enabled\n");
5262                         if (WARN_ON(!encoder->base.crtc))
5263                                 return;
5264
5265                         crtc = encoder->base.crtc;
5266
5267                         WARN(!crtc->enabled, "crtc not enabled\n");
5268                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5269                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5270                              "encoder active on the wrong pipe\n");
5271                 }
5272         }
5273 }
5274
5275 /* Even simpler default implementation, if there's really no special case to
5276  * consider. */
5277 void intel_connector_dpms(struct drm_connector *connector, int mode)
5278 {
5279         /* All the simple cases only support two dpms states. */
5280         if (mode != DRM_MODE_DPMS_ON)
5281                 mode = DRM_MODE_DPMS_OFF;
5282
5283         if (mode == connector->dpms)
5284                 return;
5285
5286         connector->dpms = mode;
5287
5288         /* Only need to change hw state when actually enabled */
5289         if (connector->encoder)
5290                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5291
5292         intel_modeset_check_state(connector->dev);
5293 }
5294
5295 /* Simple connector->get_hw_state implementation for encoders that support only
5296  * one connector and no cloning and hence the encoder state determines the state
5297  * of the connector. */
5298 bool intel_connector_get_hw_state(struct intel_connector *connector)
5299 {
5300         enum pipe pipe = 0;
5301         struct intel_encoder *encoder = connector->encoder;
5302
5303         return encoder->get_hw_state(encoder, &pipe);
5304 }
5305
5306 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5307                                      struct intel_crtc_config *pipe_config)
5308 {
5309         struct drm_i915_private *dev_priv = dev->dev_private;
5310         struct intel_crtc *pipe_B_crtc =
5311                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5312
5313         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5314                       pipe_name(pipe), pipe_config->fdi_lanes);
5315         if (pipe_config->fdi_lanes > 4) {
5316                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5317                               pipe_name(pipe), pipe_config->fdi_lanes);
5318                 return false;
5319         }
5320
5321         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5322                 if (pipe_config->fdi_lanes > 2) {
5323                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5324                                       pipe_config->fdi_lanes);
5325                         return false;
5326                 } else {
5327                         return true;
5328                 }
5329         }
5330
5331         if (INTEL_INFO(dev)->num_pipes == 2)
5332                 return true;
5333
5334         /* Ivybridge 3 pipe is really complicated */
5335         switch (pipe) {
5336         case PIPE_A:
5337                 return true;
5338         case PIPE_B:
5339                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5340                     pipe_config->fdi_lanes > 2) {
5341                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5342                                       pipe_name(pipe), pipe_config->fdi_lanes);
5343                         return false;
5344                 }
5345                 return true;
5346         case PIPE_C:
5347                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5348                     pipe_B_crtc->config.fdi_lanes <= 2) {
5349                         if (pipe_config->fdi_lanes > 2) {
5350                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5351                                               pipe_name(pipe), pipe_config->fdi_lanes);
5352                                 return false;
5353                         }
5354                 } else {
5355                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5356                         return false;
5357                 }
5358                 return true;
5359         default:
5360                 BUG();
5361         }
5362 }
5363
5364 #define RETRY 1
5365 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5366                                        struct intel_crtc_config *pipe_config)
5367 {
5368         struct drm_device *dev = intel_crtc->base.dev;
5369         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5370         int lane, link_bw, fdi_dotclock;
5371         bool setup_ok, needs_recompute = false;
5372
5373 retry:
5374         /* FDI is a binary signal running at ~2.7GHz, encoding
5375          * each output octet as 10 bits. The actual frequency
5376          * is stored as a divider into a 100MHz clock, and the
5377          * mode pixel clock is stored in units of 1KHz.
5378          * Hence the bw of each lane in terms of the mode signal
5379          * is:
5380          */
5381         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5382
5383         fdi_dotclock = adjusted_mode->crtc_clock;
5384
5385         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5386                                            pipe_config->pipe_bpp);
5387
5388         pipe_config->fdi_lanes = lane;
5389
5390         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5391                                link_bw, &pipe_config->fdi_m_n);
5392
5393         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5394                                             intel_crtc->pipe, pipe_config);
5395         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5396                 pipe_config->pipe_bpp -= 2*3;
5397                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5398                               pipe_config->pipe_bpp);
5399                 needs_recompute = true;
5400                 pipe_config->bw_constrained = true;
5401
5402                 goto retry;
5403         }
5404
5405         if (needs_recompute)
5406                 return RETRY;
5407
5408         return setup_ok ? 0 : -EINVAL;
5409 }
5410
5411 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5412                                    struct intel_crtc_config *pipe_config)
5413 {
5414         pipe_config->ips_enabled = i915.enable_ips &&
5415                                    hsw_crtc_supports_ips(crtc) &&
5416                                    pipe_config->pipe_bpp <= 24;
5417 }
5418
5419 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5420                                      struct intel_crtc_config *pipe_config)
5421 {
5422         struct drm_device *dev = crtc->base.dev;
5423         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5424
5425         /* FIXME should check pixel clock limits on all platforms */
5426         if (INTEL_INFO(dev)->gen < 4) {
5427                 struct drm_i915_private *dev_priv = dev->dev_private;
5428                 int clock_limit =
5429                         dev_priv->display.get_display_clock_speed(dev);
5430
5431                 /*
5432                  * Enable pixel doubling when the dot clock
5433                  * is > 90% of the (display) core speed.
5434                  *
5435                  * GDG double wide on either pipe,
5436                  * otherwise pipe A only.
5437                  */
5438                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5439                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5440                         clock_limit *= 2;
5441                         pipe_config->double_wide = true;
5442                 }
5443
5444                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5445                         return -EINVAL;
5446         }
5447
5448         /*
5449          * Pipe horizontal size must be even in:
5450          * - DVO ganged mode
5451          * - LVDS dual channel mode
5452          * - Double wide pipe
5453          */
5454         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5455              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5456                 pipe_config->pipe_src_w &= ~1;
5457
5458         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5459          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5460          */
5461         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5462                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5463                 return -EINVAL;
5464
5465         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5466                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5467         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5468                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5469                  * for lvds. */
5470                 pipe_config->pipe_bpp = 8*3;
5471         }
5472
5473         if (HAS_IPS(dev))
5474                 hsw_compute_ips_config(crtc, pipe_config);
5475
5476         /*
5477          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5478          * old clock survives for now.
5479          */
5480         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5481                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5482
5483         if (pipe_config->has_pch_encoder)
5484                 return ironlake_fdi_compute_config(crtc, pipe_config);
5485
5486         return 0;
5487 }
5488
5489 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5490 {
5491         struct drm_i915_private *dev_priv = dev->dev_private;
5492         int vco = valleyview_get_vco(dev_priv);
5493         u32 val;
5494         int divider;
5495
5496         /* FIXME: Punit isn't quite ready yet */
5497         if (IS_CHERRYVIEW(dev))
5498                 return 400000;
5499
5500         mutex_lock(&dev_priv->dpio_lock);
5501         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5502         mutex_unlock(&dev_priv->dpio_lock);
5503
5504         divider = val & DISPLAY_FREQUENCY_VALUES;
5505
5506         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5507              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5508              "cdclk change in progress\n");
5509
5510         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5511 }
5512
5513 static int i945_get_display_clock_speed(struct drm_device *dev)
5514 {
5515         return 400000;
5516 }
5517
5518 static int i915_get_display_clock_speed(struct drm_device *dev)
5519 {
5520         return 333000;
5521 }
5522
5523 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5524 {
5525         return 200000;
5526 }
5527
5528 static int pnv_get_display_clock_speed(struct drm_device *dev)
5529 {
5530         u16 gcfgc = 0;
5531
5532         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5533
5534         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5535         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5536                 return 267000;
5537         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5538                 return 333000;
5539         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5540                 return 444000;
5541         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5542                 return 200000;
5543         default:
5544                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5545         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5546                 return 133000;
5547         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5548                 return 167000;
5549         }
5550 }
5551
5552 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5553 {
5554         u16 gcfgc = 0;
5555
5556         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5557
5558         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5559                 return 133000;
5560         else {
5561                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5562                 case GC_DISPLAY_CLOCK_333_MHZ:
5563                         return 333000;
5564                 default:
5565                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5566                         return 190000;
5567                 }
5568         }
5569 }
5570
5571 static int i865_get_display_clock_speed(struct drm_device *dev)
5572 {
5573         return 266000;
5574 }
5575
5576 static int i855_get_display_clock_speed(struct drm_device *dev)
5577 {
5578         u16 hpllcc = 0;
5579         /* Assume that the hardware is in the high speed state.  This
5580          * should be the default.
5581          */
5582         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5583         case GC_CLOCK_133_200:
5584         case GC_CLOCK_100_200:
5585                 return 200000;
5586         case GC_CLOCK_166_250:
5587                 return 250000;
5588         case GC_CLOCK_100_133:
5589                 return 133000;
5590         }
5591
5592         /* Shouldn't happen */
5593         return 0;
5594 }
5595
5596 static int i830_get_display_clock_speed(struct drm_device *dev)
5597 {
5598         return 133000;
5599 }
5600
5601 static void
5602 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5603 {
5604         while (*num > DATA_LINK_M_N_MASK ||
5605                *den > DATA_LINK_M_N_MASK) {
5606                 *num >>= 1;
5607                 *den >>= 1;
5608         }
5609 }
5610
5611 static void compute_m_n(unsigned int m, unsigned int n,
5612                         uint32_t *ret_m, uint32_t *ret_n)
5613 {
5614         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5615         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5616         intel_reduce_m_n_ratio(ret_m, ret_n);
5617 }
5618
5619 void
5620 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5621                        int pixel_clock, int link_clock,
5622                        struct intel_link_m_n *m_n)
5623 {
5624         m_n->tu = 64;
5625
5626         compute_m_n(bits_per_pixel * pixel_clock,
5627                     link_clock * nlanes * 8,
5628                     &m_n->gmch_m, &m_n->gmch_n);
5629
5630         compute_m_n(pixel_clock, link_clock,
5631                     &m_n->link_m, &m_n->link_n);
5632 }
5633
5634 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5635 {
5636         if (i915.panel_use_ssc >= 0)
5637                 return i915.panel_use_ssc != 0;
5638         return dev_priv->vbt.lvds_use_ssc
5639                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5640 }
5641
5642 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5643 {
5644         struct drm_device *dev = crtc->base.dev;
5645         struct drm_i915_private *dev_priv = dev->dev_private;
5646         int refclk;
5647
5648         if (IS_VALLEYVIEW(dev)) {
5649                 refclk = 100000;
5650         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5651             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5652                 refclk = dev_priv->vbt.lvds_ssc_freq;
5653                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5654         } else if (!IS_GEN2(dev)) {
5655                 refclk = 96000;
5656         } else {
5657                 refclk = 48000;
5658         }
5659
5660         return refclk;
5661 }
5662
5663 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5664 {
5665         return (1 << dpll->n) << 16 | dpll->m2;
5666 }
5667
5668 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5669 {
5670         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5671 }
5672
5673 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5674                                      intel_clock_t *reduced_clock)
5675 {
5676         struct drm_device *dev = crtc->base.dev;
5677         u32 fp, fp2 = 0;
5678
5679         if (IS_PINEVIEW(dev)) {
5680                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5681                 if (reduced_clock)
5682                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5683         } else {
5684                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5685                 if (reduced_clock)
5686                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5687         }
5688
5689         crtc->config.dpll_hw_state.fp0 = fp;
5690
5691         crtc->lowfreq_avail = false;
5692         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5693             reduced_clock && i915.powersave) {
5694                 crtc->config.dpll_hw_state.fp1 = fp2;
5695                 crtc->lowfreq_avail = true;
5696         } else {
5697                 crtc->config.dpll_hw_state.fp1 = fp;
5698         }
5699 }
5700
5701 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5702                 pipe)
5703 {
5704         u32 reg_val;
5705
5706         /*
5707          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5708          * and set it to a reasonable value instead.
5709          */
5710         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5711         reg_val &= 0xffffff00;
5712         reg_val |= 0x00000030;
5713         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5714
5715         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5716         reg_val &= 0x8cffffff;
5717         reg_val = 0x8c000000;
5718         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5719
5720         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5721         reg_val &= 0xffffff00;
5722         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5723
5724         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5725         reg_val &= 0x00ffffff;
5726         reg_val |= 0xb0000000;
5727         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5728 }
5729
5730 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5731                                          struct intel_link_m_n *m_n)
5732 {
5733         struct drm_device *dev = crtc->base.dev;
5734         struct drm_i915_private *dev_priv = dev->dev_private;
5735         int pipe = crtc->pipe;
5736
5737         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5738         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5739         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5740         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5741 }
5742
5743 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5744                                          struct intel_link_m_n *m_n,
5745                                          struct intel_link_m_n *m2_n2)
5746 {
5747         struct drm_device *dev = crtc->base.dev;
5748         struct drm_i915_private *dev_priv = dev->dev_private;
5749         int pipe = crtc->pipe;
5750         enum transcoder transcoder = crtc->config.cpu_transcoder;
5751
5752         if (INTEL_INFO(dev)->gen >= 5) {
5753                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5754                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5755                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5756                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5757                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5758                  * for gen < 8) and if DRRS is supported (to make sure the
5759                  * registers are not unnecessarily accessed).
5760                  */
5761                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5762                         crtc->config.has_drrs) {
5763                         I915_WRITE(PIPE_DATA_M2(transcoder),
5764                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5765                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5766                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5767                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5768                 }
5769         } else {
5770                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5771                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5772                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5773                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5774         }
5775 }
5776
5777 void intel_dp_set_m_n(struct intel_crtc *crtc)
5778 {
5779         if (crtc->config.has_pch_encoder)
5780                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5781         else
5782                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5783                                                    &crtc->config.dp_m2_n2);
5784 }
5785
5786 static void vlv_update_pll(struct intel_crtc *crtc,
5787                            struct intel_crtc_config *pipe_config)
5788 {
5789         u32 dpll, dpll_md;
5790
5791         /*
5792          * Enable DPIO clock input. We should never disable the reference
5793          * clock for pipe B, since VGA hotplug / manual detection depends
5794          * on it.
5795          */
5796         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5797                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5798         /* We should never disable this, set it here for state tracking */
5799         if (crtc->pipe == PIPE_B)
5800                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5801         dpll |= DPLL_VCO_ENABLE;
5802         pipe_config->dpll_hw_state.dpll = dpll;
5803
5804         dpll_md = (pipe_config->pixel_multiplier - 1)
5805                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5806         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5807 }
5808
5809 static void vlv_prepare_pll(struct intel_crtc *crtc,
5810                             const struct intel_crtc_config *pipe_config)
5811 {
5812         struct drm_device *dev = crtc->base.dev;
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         int pipe = crtc->pipe;
5815         u32 mdiv;
5816         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5817         u32 coreclk, reg_val;
5818
5819         mutex_lock(&dev_priv->dpio_lock);
5820
5821         bestn = pipe_config->dpll.n;
5822         bestm1 = pipe_config->dpll.m1;
5823         bestm2 = pipe_config->dpll.m2;
5824         bestp1 = pipe_config->dpll.p1;
5825         bestp2 = pipe_config->dpll.p2;
5826
5827         /* See eDP HDMI DPIO driver vbios notes doc */
5828
5829         /* PLL B needs special handling */
5830         if (pipe == PIPE_B)
5831                 vlv_pllb_recal_opamp(dev_priv, pipe);
5832
5833         /* Set up Tx target for periodic Rcomp update */
5834         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5835
5836         /* Disable target IRef on PLL */
5837         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5838         reg_val &= 0x00ffffff;
5839         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5840
5841         /* Disable fast lock */
5842         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5843
5844         /* Set idtafcrecal before PLL is enabled */
5845         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5846         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5847         mdiv |= ((bestn << DPIO_N_SHIFT));
5848         mdiv |= (1 << DPIO_K_SHIFT);
5849
5850         /*
5851          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5852          * but we don't support that).
5853          * Note: don't use the DAC post divider as it seems unstable.
5854          */
5855         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5856         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5857
5858         mdiv |= DPIO_ENABLE_CALIBRATION;
5859         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5860
5861         /* Set HBR and RBR LPF coefficients */
5862         if (pipe_config->port_clock == 162000 ||
5863             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5864             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5865                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5866                                  0x009f0003);
5867         else
5868                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5869                                  0x00d0000f);
5870
5871         if (crtc->config.has_dp_encoder) {
5872                 /* Use SSC source */
5873                 if (pipe == PIPE_A)
5874                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5875                                          0x0df40000);
5876                 else
5877                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5878                                          0x0df70000);
5879         } else { /* HDMI or VGA */
5880                 /* Use bend source */
5881                 if (pipe == PIPE_A)
5882                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5883                                          0x0df70000);
5884                 else
5885                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5886                                          0x0df40000);
5887         }
5888
5889         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5890         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5891         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5892             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5893                 coreclk |= 0x01000000;
5894         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5895
5896         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5897         mutex_unlock(&dev_priv->dpio_lock);
5898 }
5899
5900 static void chv_update_pll(struct intel_crtc *crtc,
5901                            struct intel_crtc_config *pipe_config)
5902 {
5903         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5904                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5905                 DPLL_VCO_ENABLE;
5906         if (crtc->pipe != PIPE_A)
5907                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5908
5909         pipe_config->dpll_hw_state.dpll_md =
5910                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5911 }
5912
5913 static void chv_prepare_pll(struct intel_crtc *crtc,
5914                             const struct intel_crtc_config *pipe_config)
5915 {
5916         struct drm_device *dev = crtc->base.dev;
5917         struct drm_i915_private *dev_priv = dev->dev_private;
5918         int pipe = crtc->pipe;
5919         int dpll_reg = DPLL(crtc->pipe);
5920         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5921         u32 loopfilter, intcoeff;
5922         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5923         int refclk;
5924
5925         bestn = pipe_config->dpll.n;
5926         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5927         bestm1 = pipe_config->dpll.m1;
5928         bestm2 = pipe_config->dpll.m2 >> 22;
5929         bestp1 = pipe_config->dpll.p1;
5930         bestp2 = pipe_config->dpll.p2;
5931
5932         /*
5933          * Enable Refclk and SSC
5934          */
5935         I915_WRITE(dpll_reg,
5936                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5937
5938         mutex_lock(&dev_priv->dpio_lock);
5939
5940         /* p1 and p2 divider */
5941         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5942                         5 << DPIO_CHV_S1_DIV_SHIFT |
5943                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5944                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5945                         1 << DPIO_CHV_K_DIV_SHIFT);
5946
5947         /* Feedback post-divider - m2 */
5948         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5949
5950         /* Feedback refclk divider - n and m1 */
5951         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5952                         DPIO_CHV_M1_DIV_BY_2 |
5953                         1 << DPIO_CHV_N_DIV_SHIFT);
5954
5955         /* M2 fraction division */
5956         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5957
5958         /* M2 fraction division enable */
5959         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5960                        DPIO_CHV_FRAC_DIV_EN |
5961                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5962
5963         /* Loop filter */
5964         refclk = i9xx_get_refclk(crtc, 0);
5965         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5966                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5967         if (refclk == 100000)
5968                 intcoeff = 11;
5969         else if (refclk == 38400)
5970                 intcoeff = 10;
5971         else
5972                 intcoeff = 9;
5973         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5974         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5975
5976         /* AFC Recal */
5977         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5978                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5979                         DPIO_AFC_RECAL);
5980
5981         mutex_unlock(&dev_priv->dpio_lock);
5982 }
5983
5984 /**
5985  * vlv_force_pll_on - forcibly enable just the PLL
5986  * @dev_priv: i915 private structure
5987  * @pipe: pipe PLL to enable
5988  * @dpll: PLL configuration
5989  *
5990  * Enable the PLL for @pipe using the supplied @dpll config. To be used
5991  * in cases where we need the PLL enabled even when @pipe is not going to
5992  * be enabled.
5993  */
5994 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
5995                       const struct dpll *dpll)
5996 {
5997         struct intel_crtc *crtc =
5998                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5999         struct intel_crtc_config pipe_config = {
6000                 .pixel_multiplier = 1,
6001                 .dpll = *dpll,
6002         };
6003
6004         if (IS_CHERRYVIEW(dev)) {
6005                 chv_update_pll(crtc, &pipe_config);
6006                 chv_prepare_pll(crtc, &pipe_config);
6007                 chv_enable_pll(crtc, &pipe_config);
6008         } else {
6009                 vlv_update_pll(crtc, &pipe_config);
6010                 vlv_prepare_pll(crtc, &pipe_config);
6011                 vlv_enable_pll(crtc, &pipe_config);
6012         }
6013 }
6014
6015 /**
6016  * vlv_force_pll_off - forcibly disable just the PLL
6017  * @dev_priv: i915 private structure
6018  * @pipe: pipe PLL to disable
6019  *
6020  * Disable the PLL for @pipe. To be used in cases where we need
6021  * the PLL enabled even when @pipe is not going to be enabled.
6022  */
6023 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6024 {
6025         if (IS_CHERRYVIEW(dev))
6026                 chv_disable_pll(to_i915(dev), pipe);
6027         else
6028                 vlv_disable_pll(to_i915(dev), pipe);
6029 }
6030
6031 static void i9xx_update_pll(struct intel_crtc *crtc,
6032                             intel_clock_t *reduced_clock,
6033                             int num_connectors)
6034 {
6035         struct drm_device *dev = crtc->base.dev;
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037         u32 dpll;
6038         bool is_sdvo;
6039         struct dpll *clock = &crtc->new_config->dpll;
6040
6041         i9xx_update_pll_dividers(crtc, reduced_clock);
6042
6043         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6044                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6045
6046         dpll = DPLL_VGA_MODE_DIS;
6047
6048         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6049                 dpll |= DPLLB_MODE_LVDS;
6050         else
6051                 dpll |= DPLLB_MODE_DAC_SERIAL;
6052
6053         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6054                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6055                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6056         }
6057
6058         if (is_sdvo)
6059                 dpll |= DPLL_SDVO_HIGH_SPEED;
6060
6061         if (crtc->new_config->has_dp_encoder)
6062                 dpll |= DPLL_SDVO_HIGH_SPEED;
6063
6064         /* compute bitmask from p1 value */
6065         if (IS_PINEVIEW(dev))
6066                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6067         else {
6068                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6069                 if (IS_G4X(dev) && reduced_clock)
6070                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6071         }
6072         switch (clock->p2) {
6073         case 5:
6074                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6075                 break;
6076         case 7:
6077                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6078                 break;
6079         case 10:
6080                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6081                 break;
6082         case 14:
6083                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6084                 break;
6085         }
6086         if (INTEL_INFO(dev)->gen >= 4)
6087                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6088
6089         if (crtc->new_config->sdvo_tv_clock)
6090                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6091         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6092                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6093                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6094         else
6095                 dpll |= PLL_REF_INPUT_DREFCLK;
6096
6097         dpll |= DPLL_VCO_ENABLE;
6098         crtc->new_config->dpll_hw_state.dpll = dpll;
6099
6100         if (INTEL_INFO(dev)->gen >= 4) {
6101                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6102                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6103                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6104         }
6105 }
6106
6107 static void i8xx_update_pll(struct intel_crtc *crtc,
6108                             intel_clock_t *reduced_clock,
6109                             int num_connectors)
6110 {
6111         struct drm_device *dev = crtc->base.dev;
6112         struct drm_i915_private *dev_priv = dev->dev_private;
6113         u32 dpll;
6114         struct dpll *clock = &crtc->new_config->dpll;
6115
6116         i9xx_update_pll_dividers(crtc, reduced_clock);
6117
6118         dpll = DPLL_VGA_MODE_DIS;
6119
6120         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6121                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6122         } else {
6123                 if (clock->p1 == 2)
6124                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6125                 else
6126                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6127                 if (clock->p2 == 4)
6128                         dpll |= PLL_P2_DIVIDE_BY_4;
6129         }
6130
6131         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6132                 dpll |= DPLL_DVO_2X_MODE;
6133
6134         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6135                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6136                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6137         else
6138                 dpll |= PLL_REF_INPUT_DREFCLK;
6139
6140         dpll |= DPLL_VCO_ENABLE;
6141         crtc->new_config->dpll_hw_state.dpll = dpll;
6142 }
6143
6144 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6145 {
6146         struct drm_device *dev = intel_crtc->base.dev;
6147         struct drm_i915_private *dev_priv = dev->dev_private;
6148         enum pipe pipe = intel_crtc->pipe;
6149         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6150         struct drm_display_mode *adjusted_mode =
6151                 &intel_crtc->config.adjusted_mode;
6152         uint32_t crtc_vtotal, crtc_vblank_end;
6153         int vsyncshift = 0;
6154
6155         /* We need to be careful not to changed the adjusted mode, for otherwise
6156          * the hw state checker will get angry at the mismatch. */
6157         crtc_vtotal = adjusted_mode->crtc_vtotal;
6158         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6159
6160         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6161                 /* the chip adds 2 halflines automatically */
6162                 crtc_vtotal -= 1;
6163                 crtc_vblank_end -= 1;
6164
6165                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6166                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6167                 else
6168                         vsyncshift = adjusted_mode->crtc_hsync_start -
6169                                 adjusted_mode->crtc_htotal / 2;
6170                 if (vsyncshift < 0)
6171                         vsyncshift += adjusted_mode->crtc_htotal;
6172         }
6173
6174         if (INTEL_INFO(dev)->gen > 3)
6175                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6176
6177         I915_WRITE(HTOTAL(cpu_transcoder),
6178                    (adjusted_mode->crtc_hdisplay - 1) |
6179                    ((adjusted_mode->crtc_htotal - 1) << 16));
6180         I915_WRITE(HBLANK(cpu_transcoder),
6181                    (adjusted_mode->crtc_hblank_start - 1) |
6182                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6183         I915_WRITE(HSYNC(cpu_transcoder),
6184                    (adjusted_mode->crtc_hsync_start - 1) |
6185                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6186
6187         I915_WRITE(VTOTAL(cpu_transcoder),
6188                    (adjusted_mode->crtc_vdisplay - 1) |
6189                    ((crtc_vtotal - 1) << 16));
6190         I915_WRITE(VBLANK(cpu_transcoder),
6191                    (adjusted_mode->crtc_vblank_start - 1) |
6192                    ((crtc_vblank_end - 1) << 16));
6193         I915_WRITE(VSYNC(cpu_transcoder),
6194                    (adjusted_mode->crtc_vsync_start - 1) |
6195                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6196
6197         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6198          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6199          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6200          * bits. */
6201         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6202             (pipe == PIPE_B || pipe == PIPE_C))
6203                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6204
6205         /* pipesrc controls the size that is scaled from, which should
6206          * always be the user's requested size.
6207          */
6208         I915_WRITE(PIPESRC(pipe),
6209                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6210                    (intel_crtc->config.pipe_src_h - 1));
6211 }
6212
6213 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6214                                    struct intel_crtc_config *pipe_config)
6215 {
6216         struct drm_device *dev = crtc->base.dev;
6217         struct drm_i915_private *dev_priv = dev->dev_private;
6218         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6219         uint32_t tmp;
6220
6221         tmp = I915_READ(HTOTAL(cpu_transcoder));
6222         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6223         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6224         tmp = I915_READ(HBLANK(cpu_transcoder));
6225         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6226         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6227         tmp = I915_READ(HSYNC(cpu_transcoder));
6228         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6229         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6230
6231         tmp = I915_READ(VTOTAL(cpu_transcoder));
6232         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6233         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6234         tmp = I915_READ(VBLANK(cpu_transcoder));
6235         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6236         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6237         tmp = I915_READ(VSYNC(cpu_transcoder));
6238         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6239         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6240
6241         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6242                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6243                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6244                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6245         }
6246
6247         tmp = I915_READ(PIPESRC(crtc->pipe));
6248         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6249         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6250
6251         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6252         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6253 }
6254
6255 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6256                                  struct intel_crtc_config *pipe_config)
6257 {
6258         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6259         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6260         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6261         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6262
6263         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6264         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6265         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6266         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6267
6268         mode->flags = pipe_config->adjusted_mode.flags;
6269
6270         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6271         mode->flags |= pipe_config->adjusted_mode.flags;
6272 }
6273
6274 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6275 {
6276         struct drm_device *dev = intel_crtc->base.dev;
6277         struct drm_i915_private *dev_priv = dev->dev_private;
6278         uint32_t pipeconf;
6279
6280         pipeconf = 0;
6281
6282         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6283             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6284                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6285
6286         if (intel_crtc->config.double_wide)
6287                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6288
6289         /* only g4x and later have fancy bpc/dither controls */
6290         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6291                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6292                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6293                         pipeconf |= PIPECONF_DITHER_EN |
6294                                     PIPECONF_DITHER_TYPE_SP;
6295
6296                 switch (intel_crtc->config.pipe_bpp) {
6297                 case 18:
6298                         pipeconf |= PIPECONF_6BPC;
6299                         break;
6300                 case 24:
6301                         pipeconf |= PIPECONF_8BPC;
6302                         break;
6303                 case 30:
6304                         pipeconf |= PIPECONF_10BPC;
6305                         break;
6306                 default:
6307                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6308                         BUG();
6309                 }
6310         }
6311
6312         if (HAS_PIPE_CXSR(dev)) {
6313                 if (intel_crtc->lowfreq_avail) {
6314                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6315                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6316                 } else {
6317                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6318                 }
6319         }
6320
6321         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6322                 if (INTEL_INFO(dev)->gen < 4 ||
6323                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6324                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6325                 else
6326                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6327         } else
6328                 pipeconf |= PIPECONF_PROGRESSIVE;
6329
6330         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6331                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6332
6333         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6334         POSTING_READ(PIPECONF(intel_crtc->pipe));
6335 }
6336
6337 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6338                               int x, int y,
6339                               struct drm_framebuffer *fb)
6340 {
6341         struct drm_device *dev = crtc->base.dev;
6342         struct drm_i915_private *dev_priv = dev->dev_private;
6343         int refclk, num_connectors = 0;
6344         intel_clock_t clock, reduced_clock;
6345         bool ok, has_reduced_clock = false;
6346         bool is_lvds = false, is_dsi = false;
6347         struct intel_encoder *encoder;
6348         const intel_limit_t *limit;
6349
6350         for_each_intel_encoder(dev, encoder) {
6351                 if (encoder->new_crtc != crtc)
6352                         continue;
6353
6354                 switch (encoder->type) {
6355                 case INTEL_OUTPUT_LVDS:
6356                         is_lvds = true;
6357                         break;
6358                 case INTEL_OUTPUT_DSI:
6359                         is_dsi = true;
6360                         break;
6361                 default:
6362                         break;
6363                 }
6364
6365                 num_connectors++;
6366         }
6367
6368         if (is_dsi)
6369                 return 0;
6370
6371         if (!crtc->new_config->clock_set) {
6372                 refclk = i9xx_get_refclk(crtc, num_connectors);
6373
6374                 /*
6375                  * Returns a set of divisors for the desired target clock with
6376                  * the given refclk, or FALSE.  The returned values represent
6377                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6378                  * 2) / p1 / p2.
6379                  */
6380                 limit = intel_limit(crtc, refclk);
6381                 ok = dev_priv->display.find_dpll(limit, crtc,
6382                                                  crtc->new_config->port_clock,
6383                                                  refclk, NULL, &clock);
6384                 if (!ok) {
6385                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6386                         return -EINVAL;
6387                 }
6388
6389                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6390                         /*
6391                          * Ensure we match the reduced clock's P to the target
6392                          * clock.  If the clocks don't match, we can't switch
6393                          * the display clock by using the FP0/FP1. In such case
6394                          * we will disable the LVDS downclock feature.
6395                          */
6396                         has_reduced_clock =
6397                                 dev_priv->display.find_dpll(limit, crtc,
6398                                                             dev_priv->lvds_downclock,
6399                                                             refclk, &clock,
6400                                                             &reduced_clock);
6401                 }
6402                 /* Compat-code for transition, will disappear. */
6403                 crtc->new_config->dpll.n = clock.n;
6404                 crtc->new_config->dpll.m1 = clock.m1;
6405                 crtc->new_config->dpll.m2 = clock.m2;
6406                 crtc->new_config->dpll.p1 = clock.p1;
6407                 crtc->new_config->dpll.p2 = clock.p2;
6408         }
6409
6410         if (IS_GEN2(dev)) {
6411                 i8xx_update_pll(crtc,
6412                                 has_reduced_clock ? &reduced_clock : NULL,
6413                                 num_connectors);
6414         } else if (IS_CHERRYVIEW(dev)) {
6415                 chv_update_pll(crtc, crtc->new_config);
6416         } else if (IS_VALLEYVIEW(dev)) {
6417                 vlv_update_pll(crtc, crtc->new_config);
6418         } else {
6419                 i9xx_update_pll(crtc,
6420                                 has_reduced_clock ? &reduced_clock : NULL,
6421                                 num_connectors);
6422         }
6423
6424         return 0;
6425 }
6426
6427 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6428                                  struct intel_crtc_config *pipe_config)
6429 {
6430         struct drm_device *dev = crtc->base.dev;
6431         struct drm_i915_private *dev_priv = dev->dev_private;
6432         uint32_t tmp;
6433
6434         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6435                 return;
6436
6437         tmp = I915_READ(PFIT_CONTROL);
6438         if (!(tmp & PFIT_ENABLE))
6439                 return;
6440
6441         /* Check whether the pfit is attached to our pipe. */
6442         if (INTEL_INFO(dev)->gen < 4) {
6443                 if (crtc->pipe != PIPE_B)
6444                         return;
6445         } else {
6446                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6447                         return;
6448         }
6449
6450         pipe_config->gmch_pfit.control = tmp;
6451         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6452         if (INTEL_INFO(dev)->gen < 5)
6453                 pipe_config->gmch_pfit.lvds_border_bits =
6454                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6455 }
6456
6457 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6458                                struct intel_crtc_config *pipe_config)
6459 {
6460         struct drm_device *dev = crtc->base.dev;
6461         struct drm_i915_private *dev_priv = dev->dev_private;
6462         int pipe = pipe_config->cpu_transcoder;
6463         intel_clock_t clock;
6464         u32 mdiv;
6465         int refclk = 100000;
6466
6467         /* In case of MIPI DPLL will not even be used */
6468         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6469                 return;
6470
6471         mutex_lock(&dev_priv->dpio_lock);
6472         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6473         mutex_unlock(&dev_priv->dpio_lock);
6474
6475         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6476         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6477         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6478         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6479         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6480
6481         vlv_clock(refclk, &clock);
6482
6483         /* clock.dot is the fast clock */
6484         pipe_config->port_clock = clock.dot / 5;
6485 }
6486
6487 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6488                                   struct intel_plane_config *plane_config)
6489 {
6490         struct drm_device *dev = crtc->base.dev;
6491         struct drm_i915_private *dev_priv = dev->dev_private;
6492         u32 val, base, offset;
6493         int pipe = crtc->pipe, plane = crtc->plane;
6494         int fourcc, pixel_format;
6495         int aligned_height;
6496
6497         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6498         if (!crtc->base.primary->fb) {
6499                 DRM_DEBUG_KMS("failed to alloc fb\n");
6500                 return;
6501         }
6502
6503         val = I915_READ(DSPCNTR(plane));
6504
6505         if (INTEL_INFO(dev)->gen >= 4)
6506                 if (val & DISPPLANE_TILED)
6507                         plane_config->tiled = true;
6508
6509         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6510         fourcc = intel_format_to_fourcc(pixel_format);
6511         crtc->base.primary->fb->pixel_format = fourcc;
6512         crtc->base.primary->fb->bits_per_pixel =
6513                 drm_format_plane_cpp(fourcc, 0) * 8;
6514
6515         if (INTEL_INFO(dev)->gen >= 4) {
6516                 if (plane_config->tiled)
6517                         offset = I915_READ(DSPTILEOFF(plane));
6518                 else
6519                         offset = I915_READ(DSPLINOFF(plane));
6520                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6521         } else {
6522                 base = I915_READ(DSPADDR(plane));
6523         }
6524         plane_config->base = base;
6525
6526         val = I915_READ(PIPESRC(pipe));
6527         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6528         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6529
6530         val = I915_READ(DSPSTRIDE(pipe));
6531         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6532
6533         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6534                                             plane_config->tiled);
6535
6536         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6537                                         aligned_height);
6538
6539         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6540                       pipe, plane, crtc->base.primary->fb->width,
6541                       crtc->base.primary->fb->height,
6542                       crtc->base.primary->fb->bits_per_pixel, base,
6543                       crtc->base.primary->fb->pitches[0],
6544                       plane_config->size);
6545
6546 }
6547
6548 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6549                                struct intel_crtc_config *pipe_config)
6550 {
6551         struct drm_device *dev = crtc->base.dev;
6552         struct drm_i915_private *dev_priv = dev->dev_private;
6553         int pipe = pipe_config->cpu_transcoder;
6554         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6555         intel_clock_t clock;
6556         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6557         int refclk = 100000;
6558
6559         mutex_lock(&dev_priv->dpio_lock);
6560         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6561         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6562         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6563         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6564         mutex_unlock(&dev_priv->dpio_lock);
6565
6566         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6567         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6568         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6569         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6570         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6571
6572         chv_clock(refclk, &clock);
6573
6574         /* clock.dot is the fast clock */
6575         pipe_config->port_clock = clock.dot / 5;
6576 }
6577
6578 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6579                                  struct intel_crtc_config *pipe_config)
6580 {
6581         struct drm_device *dev = crtc->base.dev;
6582         struct drm_i915_private *dev_priv = dev->dev_private;
6583         uint32_t tmp;
6584
6585         if (!intel_display_power_is_enabled(dev_priv,
6586                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6587                 return false;
6588
6589         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6590         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6591
6592         tmp = I915_READ(PIPECONF(crtc->pipe));
6593         if (!(tmp & PIPECONF_ENABLE))
6594                 return false;
6595
6596         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6597                 switch (tmp & PIPECONF_BPC_MASK) {
6598                 case PIPECONF_6BPC:
6599                         pipe_config->pipe_bpp = 18;
6600                         break;
6601                 case PIPECONF_8BPC:
6602                         pipe_config->pipe_bpp = 24;
6603                         break;
6604                 case PIPECONF_10BPC:
6605                         pipe_config->pipe_bpp = 30;
6606                         break;
6607                 default:
6608                         break;
6609                 }
6610         }
6611
6612         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6613                 pipe_config->limited_color_range = true;
6614
6615         if (INTEL_INFO(dev)->gen < 4)
6616                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6617
6618         intel_get_pipe_timings(crtc, pipe_config);
6619
6620         i9xx_get_pfit_config(crtc, pipe_config);
6621
6622         if (INTEL_INFO(dev)->gen >= 4) {
6623                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6624                 pipe_config->pixel_multiplier =
6625                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6626                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6627                 pipe_config->dpll_hw_state.dpll_md = tmp;
6628         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6629                 tmp = I915_READ(DPLL(crtc->pipe));
6630                 pipe_config->pixel_multiplier =
6631                         ((tmp & SDVO_MULTIPLIER_MASK)
6632                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6633         } else {
6634                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6635                  * port and will be fixed up in the encoder->get_config
6636                  * function. */
6637                 pipe_config->pixel_multiplier = 1;
6638         }
6639         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6640         if (!IS_VALLEYVIEW(dev)) {
6641                 /*
6642                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6643                  * on 830. Filter it out here so that we don't
6644                  * report errors due to that.
6645                  */
6646                 if (IS_I830(dev))
6647                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6648
6649                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6650                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6651         } else {
6652                 /* Mask out read-only status bits. */
6653                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6654                                                      DPLL_PORTC_READY_MASK |
6655                                                      DPLL_PORTB_READY_MASK);
6656         }
6657
6658         if (IS_CHERRYVIEW(dev))
6659                 chv_crtc_clock_get(crtc, pipe_config);
6660         else if (IS_VALLEYVIEW(dev))
6661                 vlv_crtc_clock_get(crtc, pipe_config);
6662         else
6663                 i9xx_crtc_clock_get(crtc, pipe_config);
6664
6665         return true;
6666 }
6667
6668 static void ironlake_init_pch_refclk(struct drm_device *dev)
6669 {
6670         struct drm_i915_private *dev_priv = dev->dev_private;
6671         struct intel_encoder *encoder;
6672         u32 val, final;
6673         bool has_lvds = false;
6674         bool has_cpu_edp = false;
6675         bool has_panel = false;
6676         bool has_ck505 = false;
6677         bool can_ssc = false;
6678
6679         /* We need to take the global config into account */
6680         for_each_intel_encoder(dev, encoder) {
6681                 switch (encoder->type) {
6682                 case INTEL_OUTPUT_LVDS:
6683                         has_panel = true;
6684                         has_lvds = true;
6685                         break;
6686                 case INTEL_OUTPUT_EDP:
6687                         has_panel = true;
6688                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6689                                 has_cpu_edp = true;
6690                         break;
6691                 default:
6692                         break;
6693                 }
6694         }
6695
6696         if (HAS_PCH_IBX(dev)) {
6697                 has_ck505 = dev_priv->vbt.display_clock_mode;
6698                 can_ssc = has_ck505;
6699         } else {
6700                 has_ck505 = false;
6701                 can_ssc = true;
6702         }
6703
6704         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6705                       has_panel, has_lvds, has_ck505);
6706
6707         /* Ironlake: try to setup display ref clock before DPLL
6708          * enabling. This is only under driver's control after
6709          * PCH B stepping, previous chipset stepping should be
6710          * ignoring this setting.
6711          */
6712         val = I915_READ(PCH_DREF_CONTROL);
6713
6714         /* As we must carefully and slowly disable/enable each source in turn,
6715          * compute the final state we want first and check if we need to
6716          * make any changes at all.
6717          */
6718         final = val;
6719         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6720         if (has_ck505)
6721                 final |= DREF_NONSPREAD_CK505_ENABLE;
6722         else
6723                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6724
6725         final &= ~DREF_SSC_SOURCE_MASK;
6726         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6727         final &= ~DREF_SSC1_ENABLE;
6728
6729         if (has_panel) {
6730                 final |= DREF_SSC_SOURCE_ENABLE;
6731
6732                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6733                         final |= DREF_SSC1_ENABLE;
6734
6735                 if (has_cpu_edp) {
6736                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6737                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6738                         else
6739                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6740                 } else
6741                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6742         } else {
6743                 final |= DREF_SSC_SOURCE_DISABLE;
6744                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6745         }
6746
6747         if (final == val)
6748                 return;
6749
6750         /* Always enable nonspread source */
6751         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6752
6753         if (has_ck505)
6754                 val |= DREF_NONSPREAD_CK505_ENABLE;
6755         else
6756                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6757
6758         if (has_panel) {
6759                 val &= ~DREF_SSC_SOURCE_MASK;
6760                 val |= DREF_SSC_SOURCE_ENABLE;
6761
6762                 /* SSC must be turned on before enabling the CPU output  */
6763                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6764                         DRM_DEBUG_KMS("Using SSC on panel\n");
6765                         val |= DREF_SSC1_ENABLE;
6766                 } else
6767                         val &= ~DREF_SSC1_ENABLE;
6768
6769                 /* Get SSC going before enabling the outputs */
6770                 I915_WRITE(PCH_DREF_CONTROL, val);
6771                 POSTING_READ(PCH_DREF_CONTROL);
6772                 udelay(200);
6773
6774                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6775
6776                 /* Enable CPU source on CPU attached eDP */
6777                 if (has_cpu_edp) {
6778                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6779                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6780                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6781                         } else
6782                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6783                 } else
6784                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6785
6786                 I915_WRITE(PCH_DREF_CONTROL, val);
6787                 POSTING_READ(PCH_DREF_CONTROL);
6788                 udelay(200);
6789         } else {
6790                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6791
6792                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6793
6794                 /* Turn off CPU output */
6795                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796
6797                 I915_WRITE(PCH_DREF_CONTROL, val);
6798                 POSTING_READ(PCH_DREF_CONTROL);
6799                 udelay(200);
6800
6801                 /* Turn off the SSC source */
6802                 val &= ~DREF_SSC_SOURCE_MASK;
6803                 val |= DREF_SSC_SOURCE_DISABLE;
6804
6805                 /* Turn off SSC1 */
6806                 val &= ~DREF_SSC1_ENABLE;
6807
6808                 I915_WRITE(PCH_DREF_CONTROL, val);
6809                 POSTING_READ(PCH_DREF_CONTROL);
6810                 udelay(200);
6811         }
6812
6813         BUG_ON(val != final);
6814 }
6815
6816 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6817 {
6818         uint32_t tmp;
6819
6820         tmp = I915_READ(SOUTH_CHICKEN2);
6821         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6822         I915_WRITE(SOUTH_CHICKEN2, tmp);
6823
6824         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6825                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6826                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6827
6828         tmp = I915_READ(SOUTH_CHICKEN2);
6829         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6830         I915_WRITE(SOUTH_CHICKEN2, tmp);
6831
6832         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6833                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6834                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6835 }
6836
6837 /* WaMPhyProgramming:hsw */
6838 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6839 {
6840         uint32_t tmp;
6841
6842         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6843         tmp &= ~(0xFF << 24);
6844         tmp |= (0x12 << 24);
6845         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6846
6847         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6848         tmp |= (1 << 11);
6849         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6850
6851         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6852         tmp |= (1 << 11);
6853         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6854
6855         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6856         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6857         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6858
6859         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6860         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6861         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6862
6863         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6864         tmp &= ~(7 << 13);
6865         tmp |= (5 << 13);
6866         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6867
6868         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6869         tmp &= ~(7 << 13);
6870         tmp |= (5 << 13);
6871         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6872
6873         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6874         tmp &= ~0xFF;
6875         tmp |= 0x1C;
6876         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6877
6878         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6879         tmp &= ~0xFF;
6880         tmp |= 0x1C;
6881         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6882
6883         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6884         tmp &= ~(0xFF << 16);
6885         tmp |= (0x1C << 16);
6886         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6887
6888         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6889         tmp &= ~(0xFF << 16);
6890         tmp |= (0x1C << 16);
6891         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6892
6893         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6894         tmp |= (1 << 27);
6895         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6896
6897         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6898         tmp |= (1 << 27);
6899         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6900
6901         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6902         tmp &= ~(0xF << 28);
6903         tmp |= (4 << 28);
6904         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6905
6906         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6907         tmp &= ~(0xF << 28);
6908         tmp |= (4 << 28);
6909         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6910 }
6911
6912 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6913  * Programming" based on the parameters passed:
6914  * - Sequence to enable CLKOUT_DP
6915  * - Sequence to enable CLKOUT_DP without spread
6916  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6917  */
6918 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6919                                  bool with_fdi)
6920 {
6921         struct drm_i915_private *dev_priv = dev->dev_private;
6922         uint32_t reg, tmp;
6923
6924         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6925                 with_spread = true;
6926         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6927                  with_fdi, "LP PCH doesn't have FDI\n"))
6928                 with_fdi = false;
6929
6930         mutex_lock(&dev_priv->dpio_lock);
6931
6932         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6933         tmp &= ~SBI_SSCCTL_DISABLE;
6934         tmp |= SBI_SSCCTL_PATHALT;
6935         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6936
6937         udelay(24);
6938
6939         if (with_spread) {
6940                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6941                 tmp &= ~SBI_SSCCTL_PATHALT;
6942                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6943
6944                 if (with_fdi) {
6945                         lpt_reset_fdi_mphy(dev_priv);
6946                         lpt_program_fdi_mphy(dev_priv);
6947                 }
6948         }
6949
6950         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6951                SBI_GEN0 : SBI_DBUFF0;
6952         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6953         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6954         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6955
6956         mutex_unlock(&dev_priv->dpio_lock);
6957 }
6958
6959 /* Sequence to disable CLKOUT_DP */
6960 static void lpt_disable_clkout_dp(struct drm_device *dev)
6961 {
6962         struct drm_i915_private *dev_priv = dev->dev_private;
6963         uint32_t reg, tmp;
6964
6965         mutex_lock(&dev_priv->dpio_lock);
6966
6967         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6968                SBI_GEN0 : SBI_DBUFF0;
6969         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6970         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6971         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6972
6973         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6974         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6975                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6976                         tmp |= SBI_SSCCTL_PATHALT;
6977                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6978                         udelay(32);
6979                 }
6980                 tmp |= SBI_SSCCTL_DISABLE;
6981                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6982         }
6983
6984         mutex_unlock(&dev_priv->dpio_lock);
6985 }
6986
6987 static void lpt_init_pch_refclk(struct drm_device *dev)
6988 {
6989         struct intel_encoder *encoder;
6990         bool has_vga = false;
6991
6992         for_each_intel_encoder(dev, encoder) {
6993                 switch (encoder->type) {
6994                 case INTEL_OUTPUT_ANALOG:
6995                         has_vga = true;
6996                         break;
6997                 default:
6998                         break;
6999                 }
7000         }
7001
7002         if (has_vga)
7003                 lpt_enable_clkout_dp(dev, true, true);
7004         else
7005                 lpt_disable_clkout_dp(dev);
7006 }
7007
7008 /*
7009  * Initialize reference clocks when the driver loads
7010  */
7011 void intel_init_pch_refclk(struct drm_device *dev)
7012 {
7013         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7014                 ironlake_init_pch_refclk(dev);
7015         else if (HAS_PCH_LPT(dev))
7016                 lpt_init_pch_refclk(dev);
7017 }
7018
7019 static int ironlake_get_refclk(struct drm_crtc *crtc)
7020 {
7021         struct drm_device *dev = crtc->dev;
7022         struct drm_i915_private *dev_priv = dev->dev_private;
7023         struct intel_encoder *encoder;
7024         int num_connectors = 0;
7025         bool is_lvds = false;
7026
7027         for_each_intel_encoder(dev, encoder) {
7028                 if (encoder->new_crtc != to_intel_crtc(crtc))
7029                         continue;
7030
7031                 switch (encoder->type) {
7032                 case INTEL_OUTPUT_LVDS:
7033                         is_lvds = true;
7034                         break;
7035                 default:
7036                         break;
7037                 }
7038                 num_connectors++;
7039         }
7040
7041         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7042                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7043                               dev_priv->vbt.lvds_ssc_freq);
7044                 return dev_priv->vbt.lvds_ssc_freq;
7045         }
7046
7047         return 120000;
7048 }
7049
7050 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7051 {
7052         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7053         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054         int pipe = intel_crtc->pipe;
7055         uint32_t val;
7056
7057         val = 0;
7058
7059         switch (intel_crtc->config.pipe_bpp) {
7060         case 18:
7061                 val |= PIPECONF_6BPC;
7062                 break;
7063         case 24:
7064                 val |= PIPECONF_8BPC;
7065                 break;
7066         case 30:
7067                 val |= PIPECONF_10BPC;
7068                 break;
7069         case 36:
7070                 val |= PIPECONF_12BPC;
7071                 break;
7072         default:
7073                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7074                 BUG();
7075         }
7076
7077         if (intel_crtc->config.dither)
7078                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7079
7080         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7081                 val |= PIPECONF_INTERLACED_ILK;
7082         else
7083                 val |= PIPECONF_PROGRESSIVE;
7084
7085         if (intel_crtc->config.limited_color_range)
7086                 val |= PIPECONF_COLOR_RANGE_SELECT;
7087
7088         I915_WRITE(PIPECONF(pipe), val);
7089         POSTING_READ(PIPECONF(pipe));
7090 }
7091
7092 /*
7093  * Set up the pipe CSC unit.
7094  *
7095  * Currently only full range RGB to limited range RGB conversion
7096  * is supported, but eventually this should handle various
7097  * RGB<->YCbCr scenarios as well.
7098  */
7099 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7100 {
7101         struct drm_device *dev = crtc->dev;
7102         struct drm_i915_private *dev_priv = dev->dev_private;
7103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104         int pipe = intel_crtc->pipe;
7105         uint16_t coeff = 0x7800; /* 1.0 */
7106
7107         /*
7108          * TODO: Check what kind of values actually come out of the pipe
7109          * with these coeff/postoff values and adjust to get the best
7110          * accuracy. Perhaps we even need to take the bpc value into
7111          * consideration.
7112          */
7113
7114         if (intel_crtc->config.limited_color_range)
7115                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7116
7117         /*
7118          * GY/GU and RY/RU should be the other way around according
7119          * to BSpec, but reality doesn't agree. Just set them up in
7120          * a way that results in the correct picture.
7121          */
7122         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7123         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7124
7125         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7126         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7127
7128         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7129         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7130
7131         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7132         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7133         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7134
7135         if (INTEL_INFO(dev)->gen > 6) {
7136                 uint16_t postoff = 0;
7137
7138                 if (intel_crtc->config.limited_color_range)
7139                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7140
7141                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7142                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7143                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7144
7145                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7146         } else {
7147                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7148
7149                 if (intel_crtc->config.limited_color_range)
7150                         mode |= CSC_BLACK_SCREEN_OFFSET;
7151
7152                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7153         }
7154 }
7155
7156 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7157 {
7158         struct drm_device *dev = crtc->dev;
7159         struct drm_i915_private *dev_priv = dev->dev_private;
7160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161         enum pipe pipe = intel_crtc->pipe;
7162         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7163         uint32_t val;
7164
7165         val = 0;
7166
7167         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7168                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7169
7170         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7171                 val |= PIPECONF_INTERLACED_ILK;
7172         else
7173                 val |= PIPECONF_PROGRESSIVE;
7174
7175         I915_WRITE(PIPECONF(cpu_transcoder), val);
7176         POSTING_READ(PIPECONF(cpu_transcoder));
7177
7178         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7179         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7180
7181         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7182                 val = 0;
7183
7184                 switch (intel_crtc->config.pipe_bpp) {
7185                 case 18:
7186                         val |= PIPEMISC_DITHER_6_BPC;
7187                         break;
7188                 case 24:
7189                         val |= PIPEMISC_DITHER_8_BPC;
7190                         break;
7191                 case 30:
7192                         val |= PIPEMISC_DITHER_10_BPC;
7193                         break;
7194                 case 36:
7195                         val |= PIPEMISC_DITHER_12_BPC;
7196                         break;
7197                 default:
7198                         /* Case prevented by pipe_config_set_bpp. */
7199                         BUG();
7200                 }
7201
7202                 if (intel_crtc->config.dither)
7203                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7204
7205                 I915_WRITE(PIPEMISC(pipe), val);
7206         }
7207 }
7208
7209 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7210                                     intel_clock_t *clock,
7211                                     bool *has_reduced_clock,
7212                                     intel_clock_t *reduced_clock)
7213 {
7214         struct drm_device *dev = crtc->dev;
7215         struct drm_i915_private *dev_priv = dev->dev_private;
7216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217         int refclk;
7218         const intel_limit_t *limit;
7219         bool ret, is_lvds = false;
7220
7221         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7222
7223         refclk = ironlake_get_refclk(crtc);
7224
7225         /*
7226          * Returns a set of divisors for the desired target clock with the given
7227          * refclk, or FALSE.  The returned values represent the clock equation:
7228          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7229          */
7230         limit = intel_limit(intel_crtc, refclk);
7231         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7232                                           intel_crtc->new_config->port_clock,
7233                                           refclk, NULL, clock);
7234         if (!ret)
7235                 return false;
7236
7237         if (is_lvds && dev_priv->lvds_downclock_avail) {
7238                 /*
7239                  * Ensure we match the reduced clock's P to the target clock.
7240                  * If the clocks don't match, we can't switch the display clock
7241                  * by using the FP0/FP1. In such case we will disable the LVDS
7242                  * downclock feature.
7243                 */
7244                 *has_reduced_clock =
7245                         dev_priv->display.find_dpll(limit, intel_crtc,
7246                                                     dev_priv->lvds_downclock,
7247                                                     refclk, clock,
7248                                                     reduced_clock);
7249         }
7250
7251         return true;
7252 }
7253
7254 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7255 {
7256         /*
7257          * Account for spread spectrum to avoid
7258          * oversubscribing the link. Max center spread
7259          * is 2.5%; use 5% for safety's sake.
7260          */
7261         u32 bps = target_clock * bpp * 21 / 20;
7262         return DIV_ROUND_UP(bps, link_bw * 8);
7263 }
7264
7265 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7266 {
7267         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7268 }
7269
7270 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7271                                       u32 *fp,
7272                                       intel_clock_t *reduced_clock, u32 *fp2)
7273 {
7274         struct drm_crtc *crtc = &intel_crtc->base;
7275         struct drm_device *dev = crtc->dev;
7276         struct drm_i915_private *dev_priv = dev->dev_private;
7277         struct intel_encoder *intel_encoder;
7278         uint32_t dpll;
7279         int factor, num_connectors = 0;
7280         bool is_lvds = false, is_sdvo = false;
7281
7282         for_each_intel_encoder(dev, intel_encoder) {
7283                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7284                         continue;
7285
7286                 switch (intel_encoder->type) {
7287                 case INTEL_OUTPUT_LVDS:
7288                         is_lvds = true;
7289                         break;
7290                 case INTEL_OUTPUT_SDVO:
7291                 case INTEL_OUTPUT_HDMI:
7292                         is_sdvo = true;
7293                         break;
7294                 default:
7295                         break;
7296                 }
7297
7298                 num_connectors++;
7299         }
7300
7301         /* Enable autotuning of the PLL clock (if permissible) */
7302         factor = 21;
7303         if (is_lvds) {
7304                 if ((intel_panel_use_ssc(dev_priv) &&
7305                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7306                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7307                         factor = 25;
7308         } else if (intel_crtc->new_config->sdvo_tv_clock)
7309                 factor = 20;
7310
7311         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7312                 *fp |= FP_CB_TUNE;
7313
7314         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7315                 *fp2 |= FP_CB_TUNE;
7316
7317         dpll = 0;
7318
7319         if (is_lvds)
7320                 dpll |= DPLLB_MODE_LVDS;
7321         else
7322                 dpll |= DPLLB_MODE_DAC_SERIAL;
7323
7324         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7325                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7326
7327         if (is_sdvo)
7328                 dpll |= DPLL_SDVO_HIGH_SPEED;
7329         if (intel_crtc->new_config->has_dp_encoder)
7330                 dpll |= DPLL_SDVO_HIGH_SPEED;
7331
7332         /* compute bitmask from p1 value */
7333         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7334         /* also FPA1 */
7335         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7336
7337         switch (intel_crtc->new_config->dpll.p2) {
7338         case 5:
7339                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7340                 break;
7341         case 7:
7342                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7343                 break;
7344         case 10:
7345                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7346                 break;
7347         case 14:
7348                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7349                 break;
7350         }
7351
7352         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7353                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7354         else
7355                 dpll |= PLL_REF_INPUT_DREFCLK;
7356
7357         return dpll | DPLL_VCO_ENABLE;
7358 }
7359
7360 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7361                                   int x, int y,
7362                                   struct drm_framebuffer *fb)
7363 {
7364         struct drm_device *dev = crtc->base.dev;
7365         intel_clock_t clock, reduced_clock;
7366         u32 dpll = 0, fp = 0, fp2 = 0;
7367         bool ok, has_reduced_clock = false;
7368         bool is_lvds = false;
7369         struct intel_shared_dpll *pll;
7370
7371         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7372
7373         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7374              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7375
7376         ok = ironlake_compute_clocks(&crtc->base, &clock,
7377                                      &has_reduced_clock, &reduced_clock);
7378         if (!ok && !crtc->new_config->clock_set) {
7379                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7380                 return -EINVAL;
7381         }
7382         /* Compat-code for transition, will disappear. */
7383         if (!crtc->new_config->clock_set) {
7384                 crtc->new_config->dpll.n = clock.n;
7385                 crtc->new_config->dpll.m1 = clock.m1;
7386                 crtc->new_config->dpll.m2 = clock.m2;
7387                 crtc->new_config->dpll.p1 = clock.p1;
7388                 crtc->new_config->dpll.p2 = clock.p2;
7389         }
7390
7391         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7392         if (crtc->new_config->has_pch_encoder) {
7393                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7394                 if (has_reduced_clock)
7395                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7396
7397                 dpll = ironlake_compute_dpll(crtc,
7398                                              &fp, &reduced_clock,
7399                                              has_reduced_clock ? &fp2 : NULL);
7400
7401                 crtc->new_config->dpll_hw_state.dpll = dpll;
7402                 crtc->new_config->dpll_hw_state.fp0 = fp;
7403                 if (has_reduced_clock)
7404                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7405                 else
7406                         crtc->new_config->dpll_hw_state.fp1 = fp;
7407
7408                 pll = intel_get_shared_dpll(crtc);
7409                 if (pll == NULL) {
7410                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7411                                          pipe_name(crtc->pipe));
7412                         return -EINVAL;
7413                 }
7414         } else
7415                 intel_put_shared_dpll(crtc);
7416
7417         if (is_lvds && has_reduced_clock && i915.powersave)
7418                 crtc->lowfreq_avail = true;
7419         else
7420                 crtc->lowfreq_avail = false;
7421
7422         return 0;
7423 }
7424
7425 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7426                                          struct intel_link_m_n *m_n)
7427 {
7428         struct drm_device *dev = crtc->base.dev;
7429         struct drm_i915_private *dev_priv = dev->dev_private;
7430         enum pipe pipe = crtc->pipe;
7431
7432         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7433         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7434         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7435                 & ~TU_SIZE_MASK;
7436         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7437         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7438                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7439 }
7440
7441 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7442                                          enum transcoder transcoder,
7443                                          struct intel_link_m_n *m_n,
7444                                          struct intel_link_m_n *m2_n2)
7445 {
7446         struct drm_device *dev = crtc->base.dev;
7447         struct drm_i915_private *dev_priv = dev->dev_private;
7448         enum pipe pipe = crtc->pipe;
7449
7450         if (INTEL_INFO(dev)->gen >= 5) {
7451                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7452                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7453                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7454                         & ~TU_SIZE_MASK;
7455                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7456                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7457                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7458                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7459                  * gen < 8) and if DRRS is supported (to make sure the
7460                  * registers are not unnecessarily read).
7461                  */
7462                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7463                         crtc->config.has_drrs) {
7464                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7465                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7466                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7467                                         & ~TU_SIZE_MASK;
7468                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7469                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7470                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7471                 }
7472         } else {
7473                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7474                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7475                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7476                         & ~TU_SIZE_MASK;
7477                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7478                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7479                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7480         }
7481 }
7482
7483 void intel_dp_get_m_n(struct intel_crtc *crtc,
7484                       struct intel_crtc_config *pipe_config)
7485 {
7486         if (crtc->config.has_pch_encoder)
7487                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7488         else
7489                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7490                                              &pipe_config->dp_m_n,
7491                                              &pipe_config->dp_m2_n2);
7492 }
7493
7494 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7495                                         struct intel_crtc_config *pipe_config)
7496 {
7497         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7498                                      &pipe_config->fdi_m_n, NULL);
7499 }
7500
7501 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7502                                      struct intel_crtc_config *pipe_config)
7503 {
7504         struct drm_device *dev = crtc->base.dev;
7505         struct drm_i915_private *dev_priv = dev->dev_private;
7506         uint32_t tmp;
7507
7508         tmp = I915_READ(PF_CTL(crtc->pipe));
7509
7510         if (tmp & PF_ENABLE) {
7511                 pipe_config->pch_pfit.enabled = true;
7512                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7513                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7514
7515                 /* We currently do not free assignements of panel fitters on
7516                  * ivb/hsw (since we don't use the higher upscaling modes which
7517                  * differentiates them) so just WARN about this case for now. */
7518                 if (IS_GEN7(dev)) {
7519                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7520                                 PF_PIPE_SEL_IVB(crtc->pipe));
7521                 }
7522         }
7523 }
7524
7525 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7526                                       struct intel_plane_config *plane_config)
7527 {
7528         struct drm_device *dev = crtc->base.dev;
7529         struct drm_i915_private *dev_priv = dev->dev_private;
7530         u32 val, base, offset;
7531         int pipe = crtc->pipe, plane = crtc->plane;
7532         int fourcc, pixel_format;
7533         int aligned_height;
7534
7535         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7536         if (!crtc->base.primary->fb) {
7537                 DRM_DEBUG_KMS("failed to alloc fb\n");
7538                 return;
7539         }
7540
7541         val = I915_READ(DSPCNTR(plane));
7542
7543         if (INTEL_INFO(dev)->gen >= 4)
7544                 if (val & DISPPLANE_TILED)
7545                         plane_config->tiled = true;
7546
7547         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7548         fourcc = intel_format_to_fourcc(pixel_format);
7549         crtc->base.primary->fb->pixel_format = fourcc;
7550         crtc->base.primary->fb->bits_per_pixel =
7551                 drm_format_plane_cpp(fourcc, 0) * 8;
7552
7553         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7554         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7555                 offset = I915_READ(DSPOFFSET(plane));
7556         } else {
7557                 if (plane_config->tiled)
7558                         offset = I915_READ(DSPTILEOFF(plane));
7559                 else
7560                         offset = I915_READ(DSPLINOFF(plane));
7561         }
7562         plane_config->base = base;
7563
7564         val = I915_READ(PIPESRC(pipe));
7565         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7566         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7567
7568         val = I915_READ(DSPSTRIDE(pipe));
7569         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7570
7571         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7572                                             plane_config->tiled);
7573
7574         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7575                                         aligned_height);
7576
7577         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7578                       pipe, plane, crtc->base.primary->fb->width,
7579                       crtc->base.primary->fb->height,
7580                       crtc->base.primary->fb->bits_per_pixel, base,
7581                       crtc->base.primary->fb->pitches[0],
7582                       plane_config->size);
7583 }
7584
7585 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7586                                      struct intel_crtc_config *pipe_config)
7587 {
7588         struct drm_device *dev = crtc->base.dev;
7589         struct drm_i915_private *dev_priv = dev->dev_private;
7590         uint32_t tmp;
7591
7592         if (!intel_display_power_is_enabled(dev_priv,
7593                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7594                 return false;
7595
7596         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7597         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7598
7599         tmp = I915_READ(PIPECONF(crtc->pipe));
7600         if (!(tmp & PIPECONF_ENABLE))
7601                 return false;
7602
7603         switch (tmp & PIPECONF_BPC_MASK) {
7604         case PIPECONF_6BPC:
7605                 pipe_config->pipe_bpp = 18;
7606                 break;
7607         case PIPECONF_8BPC:
7608                 pipe_config->pipe_bpp = 24;
7609                 break;
7610         case PIPECONF_10BPC:
7611                 pipe_config->pipe_bpp = 30;
7612                 break;
7613         case PIPECONF_12BPC:
7614                 pipe_config->pipe_bpp = 36;
7615                 break;
7616         default:
7617                 break;
7618         }
7619
7620         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7621                 pipe_config->limited_color_range = true;
7622
7623         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7624                 struct intel_shared_dpll *pll;
7625
7626                 pipe_config->has_pch_encoder = true;
7627
7628                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7629                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7630                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7631
7632                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7633
7634                 if (HAS_PCH_IBX(dev_priv->dev)) {
7635                         pipe_config->shared_dpll =
7636                                 (enum intel_dpll_id) crtc->pipe;
7637                 } else {
7638                         tmp = I915_READ(PCH_DPLL_SEL);
7639                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7640                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7641                         else
7642                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7643                 }
7644
7645                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7646
7647                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7648                                            &pipe_config->dpll_hw_state));
7649
7650                 tmp = pipe_config->dpll_hw_state.dpll;
7651                 pipe_config->pixel_multiplier =
7652                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7653                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7654
7655                 ironlake_pch_clock_get(crtc, pipe_config);
7656         } else {
7657                 pipe_config->pixel_multiplier = 1;
7658         }
7659
7660         intel_get_pipe_timings(crtc, pipe_config);
7661
7662         ironlake_get_pfit_config(crtc, pipe_config);
7663
7664         return true;
7665 }
7666
7667 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7668 {
7669         struct drm_device *dev = dev_priv->dev;
7670         struct intel_crtc *crtc;
7671
7672         for_each_intel_crtc(dev, crtc)
7673                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7674                      pipe_name(crtc->pipe));
7675
7676         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7677         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7678         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7679         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7680         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7681         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7682              "CPU PWM1 enabled\n");
7683         if (IS_HASWELL(dev))
7684                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7685                      "CPU PWM2 enabled\n");
7686         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7687              "PCH PWM1 enabled\n");
7688         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7689              "Utility pin enabled\n");
7690         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7691
7692         /*
7693          * In theory we can still leave IRQs enabled, as long as only the HPD
7694          * interrupts remain enabled. We used to check for that, but since it's
7695          * gen-specific and since we only disable LCPLL after we fully disable
7696          * the interrupts, the check below should be enough.
7697          */
7698         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7699 }
7700
7701 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7702 {
7703         struct drm_device *dev = dev_priv->dev;
7704
7705         if (IS_HASWELL(dev))
7706                 return I915_READ(D_COMP_HSW);
7707         else
7708                 return I915_READ(D_COMP_BDW);
7709 }
7710
7711 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7712 {
7713         struct drm_device *dev = dev_priv->dev;
7714
7715         if (IS_HASWELL(dev)) {
7716                 mutex_lock(&dev_priv->rps.hw_lock);
7717                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7718                                             val))
7719                         DRM_ERROR("Failed to write to D_COMP\n");
7720                 mutex_unlock(&dev_priv->rps.hw_lock);
7721         } else {
7722                 I915_WRITE(D_COMP_BDW, val);
7723                 POSTING_READ(D_COMP_BDW);
7724         }
7725 }
7726
7727 /*
7728  * This function implements pieces of two sequences from BSpec:
7729  * - Sequence for display software to disable LCPLL
7730  * - Sequence for display software to allow package C8+
7731  * The steps implemented here are just the steps that actually touch the LCPLL
7732  * register. Callers should take care of disabling all the display engine
7733  * functions, doing the mode unset, fixing interrupts, etc.
7734  */
7735 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7736                               bool switch_to_fclk, bool allow_power_down)
7737 {
7738         uint32_t val;
7739
7740         assert_can_disable_lcpll(dev_priv);
7741
7742         val = I915_READ(LCPLL_CTL);
7743
7744         if (switch_to_fclk) {
7745                 val |= LCPLL_CD_SOURCE_FCLK;
7746                 I915_WRITE(LCPLL_CTL, val);
7747
7748                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7749                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7750                         DRM_ERROR("Switching to FCLK failed\n");
7751
7752                 val = I915_READ(LCPLL_CTL);
7753         }
7754
7755         val |= LCPLL_PLL_DISABLE;
7756         I915_WRITE(LCPLL_CTL, val);
7757         POSTING_READ(LCPLL_CTL);
7758
7759         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7760                 DRM_ERROR("LCPLL still locked\n");
7761
7762         val = hsw_read_dcomp(dev_priv);
7763         val |= D_COMP_COMP_DISABLE;
7764         hsw_write_dcomp(dev_priv, val);
7765         ndelay(100);
7766
7767         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7768                      1))
7769                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7770
7771         if (allow_power_down) {
7772                 val = I915_READ(LCPLL_CTL);
7773                 val |= LCPLL_POWER_DOWN_ALLOW;
7774                 I915_WRITE(LCPLL_CTL, val);
7775                 POSTING_READ(LCPLL_CTL);
7776         }
7777 }
7778
7779 /*
7780  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7781  * source.
7782  */
7783 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7784 {
7785         uint32_t val;
7786
7787         val = I915_READ(LCPLL_CTL);
7788
7789         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7790                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7791                 return;
7792
7793         /*
7794          * Make sure we're not on PC8 state before disabling PC8, otherwise
7795          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7796          *
7797          * The other problem is that hsw_restore_lcpll() is called as part of
7798          * the runtime PM resume sequence, so we can't just call
7799          * gen6_gt_force_wake_get() because that function calls
7800          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7801          * while we are on the resume sequence. So to solve this problem we have
7802          * to call special forcewake code that doesn't touch runtime PM and
7803          * doesn't enable the forcewake delayed work.
7804          */
7805         spin_lock_irq(&dev_priv->uncore.lock);
7806         if (dev_priv->uncore.forcewake_count++ == 0)
7807                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7808         spin_unlock_irq(&dev_priv->uncore.lock);
7809
7810         if (val & LCPLL_POWER_DOWN_ALLOW) {
7811                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7812                 I915_WRITE(LCPLL_CTL, val);
7813                 POSTING_READ(LCPLL_CTL);
7814         }
7815
7816         val = hsw_read_dcomp(dev_priv);
7817         val |= D_COMP_COMP_FORCE;
7818         val &= ~D_COMP_COMP_DISABLE;
7819         hsw_write_dcomp(dev_priv, val);
7820
7821         val = I915_READ(LCPLL_CTL);
7822         val &= ~LCPLL_PLL_DISABLE;
7823         I915_WRITE(LCPLL_CTL, val);
7824
7825         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7826                 DRM_ERROR("LCPLL not locked yet\n");
7827
7828         if (val & LCPLL_CD_SOURCE_FCLK) {
7829                 val = I915_READ(LCPLL_CTL);
7830                 val &= ~LCPLL_CD_SOURCE_FCLK;
7831                 I915_WRITE(LCPLL_CTL, val);
7832
7833                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7834                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7835                         DRM_ERROR("Switching back to LCPLL failed\n");
7836         }
7837
7838         /* See the big comment above. */
7839         spin_lock_irq(&dev_priv->uncore.lock);
7840         if (--dev_priv->uncore.forcewake_count == 0)
7841                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7842         spin_unlock_irq(&dev_priv->uncore.lock);
7843 }
7844
7845 /*
7846  * Package states C8 and deeper are really deep PC states that can only be
7847  * reached when all the devices on the system allow it, so even if the graphics
7848  * device allows PC8+, it doesn't mean the system will actually get to these
7849  * states. Our driver only allows PC8+ when going into runtime PM.
7850  *
7851  * The requirements for PC8+ are that all the outputs are disabled, the power
7852  * well is disabled and most interrupts are disabled, and these are also
7853  * requirements for runtime PM. When these conditions are met, we manually do
7854  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7855  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7856  * hang the machine.
7857  *
7858  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7859  * the state of some registers, so when we come back from PC8+ we need to
7860  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7861  * need to take care of the registers kept by RC6. Notice that this happens even
7862  * if we don't put the device in PCI D3 state (which is what currently happens
7863  * because of the runtime PM support).
7864  *
7865  * For more, read "Display Sequences for Package C8" on the hardware
7866  * documentation.
7867  */
7868 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7869 {
7870         struct drm_device *dev = dev_priv->dev;
7871         uint32_t val;
7872
7873         DRM_DEBUG_KMS("Enabling package C8+\n");
7874
7875         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7876                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7877                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7878                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7879         }
7880
7881         lpt_disable_clkout_dp(dev);
7882         hsw_disable_lcpll(dev_priv, true, true);
7883 }
7884
7885 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7886 {
7887         struct drm_device *dev = dev_priv->dev;
7888         uint32_t val;
7889
7890         DRM_DEBUG_KMS("Disabling package C8+\n");
7891
7892         hsw_restore_lcpll(dev_priv);
7893         lpt_init_pch_refclk(dev);
7894
7895         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7896                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7897                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7898                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7899         }
7900
7901         intel_prepare_ddi(dev);
7902 }
7903
7904 static void snb_modeset_global_resources(struct drm_device *dev)
7905 {
7906         modeset_update_crtc_power_domains(dev);
7907 }
7908
7909 static void haswell_modeset_global_resources(struct drm_device *dev)
7910 {
7911         modeset_update_crtc_power_domains(dev);
7912 }
7913
7914 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7915                                  int x, int y,
7916                                  struct drm_framebuffer *fb)
7917 {
7918         if (!intel_ddi_pll_select(crtc))
7919                 return -EINVAL;
7920
7921         crtc->lowfreq_avail = false;
7922
7923         return 0;
7924 }
7925
7926 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7927                                 enum port port,
7928                                 struct intel_crtc_config *pipe_config)
7929 {
7930         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7931
7932         switch (pipe_config->ddi_pll_sel) {
7933         case PORT_CLK_SEL_WRPLL1:
7934                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7935                 break;
7936         case PORT_CLK_SEL_WRPLL2:
7937                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7938                 break;
7939         }
7940 }
7941
7942 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7943                                        struct intel_crtc_config *pipe_config)
7944 {
7945         struct drm_device *dev = crtc->base.dev;
7946         struct drm_i915_private *dev_priv = dev->dev_private;
7947         struct intel_shared_dpll *pll;
7948         enum port port;
7949         uint32_t tmp;
7950
7951         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7952
7953         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7954
7955         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7956
7957         if (pipe_config->shared_dpll >= 0) {
7958                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7959
7960                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7961                                            &pipe_config->dpll_hw_state));
7962         }
7963
7964         /*
7965          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7966          * DDI E. So just check whether this pipe is wired to DDI E and whether
7967          * the PCH transcoder is on.
7968          */
7969         if (INTEL_INFO(dev)->gen < 9 &&
7970             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7971                 pipe_config->has_pch_encoder = true;
7972
7973                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7974                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7975                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7976
7977                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7978         }
7979 }
7980
7981 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7982                                     struct intel_crtc_config *pipe_config)
7983 {
7984         struct drm_device *dev = crtc->base.dev;
7985         struct drm_i915_private *dev_priv = dev->dev_private;
7986         enum intel_display_power_domain pfit_domain;
7987         uint32_t tmp;
7988
7989         if (!intel_display_power_is_enabled(dev_priv,
7990                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7991                 return false;
7992
7993         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7994         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7995
7996         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7997         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7998                 enum pipe trans_edp_pipe;
7999                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8000                 default:
8001                         WARN(1, "unknown pipe linked to edp transcoder\n");
8002                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8003                 case TRANS_DDI_EDP_INPUT_A_ON:
8004                         trans_edp_pipe = PIPE_A;
8005                         break;
8006                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8007                         trans_edp_pipe = PIPE_B;
8008                         break;
8009                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8010                         trans_edp_pipe = PIPE_C;
8011                         break;
8012                 }
8013
8014                 if (trans_edp_pipe == crtc->pipe)
8015                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8016         }
8017
8018         if (!intel_display_power_is_enabled(dev_priv,
8019                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8020                 return false;
8021
8022         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8023         if (!(tmp & PIPECONF_ENABLE))
8024                 return false;
8025
8026         haswell_get_ddi_port_state(crtc, pipe_config);
8027
8028         intel_get_pipe_timings(crtc, pipe_config);
8029
8030         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8031         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8032                 ironlake_get_pfit_config(crtc, pipe_config);
8033
8034         if (IS_HASWELL(dev))
8035                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8036                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8037
8038         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8039                 pipe_config->pixel_multiplier =
8040                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8041         } else {
8042                 pipe_config->pixel_multiplier = 1;
8043         }
8044
8045         return true;
8046 }
8047
8048 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8049 {
8050         struct drm_device *dev = crtc->dev;
8051         struct drm_i915_private *dev_priv = dev->dev_private;
8052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8053         uint32_t cntl = 0, size = 0;
8054
8055         if (base) {
8056                 unsigned int width = intel_crtc->cursor_width;
8057                 unsigned int height = intel_crtc->cursor_height;
8058                 unsigned int stride = roundup_pow_of_two(width) * 4;
8059
8060                 switch (stride) {
8061                 default:
8062                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8063                                   width, stride);
8064                         stride = 256;
8065                         /* fallthrough */
8066                 case 256:
8067                 case 512:
8068                 case 1024:
8069                 case 2048:
8070                         break;
8071                 }
8072
8073                 cntl |= CURSOR_ENABLE |
8074                         CURSOR_GAMMA_ENABLE |
8075                         CURSOR_FORMAT_ARGB |
8076                         CURSOR_STRIDE(stride);
8077
8078                 size = (height << 12) | width;
8079         }
8080
8081         if (intel_crtc->cursor_cntl != 0 &&
8082             (intel_crtc->cursor_base != base ||
8083              intel_crtc->cursor_size != size ||
8084              intel_crtc->cursor_cntl != cntl)) {
8085                 /* On these chipsets we can only modify the base/size/stride
8086                  * whilst the cursor is disabled.
8087                  */
8088                 I915_WRITE(_CURACNTR, 0);
8089                 POSTING_READ(_CURACNTR);
8090                 intel_crtc->cursor_cntl = 0;
8091         }
8092
8093         if (intel_crtc->cursor_base != base) {
8094                 I915_WRITE(_CURABASE, base);
8095                 intel_crtc->cursor_base = base;
8096         }
8097
8098         if (intel_crtc->cursor_size != size) {
8099                 I915_WRITE(CURSIZE, size);
8100                 intel_crtc->cursor_size = size;
8101         }
8102
8103         if (intel_crtc->cursor_cntl != cntl) {
8104                 I915_WRITE(_CURACNTR, cntl);
8105                 POSTING_READ(_CURACNTR);
8106                 intel_crtc->cursor_cntl = cntl;
8107         }
8108 }
8109
8110 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8111 {
8112         struct drm_device *dev = crtc->dev;
8113         struct drm_i915_private *dev_priv = dev->dev_private;
8114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8115         int pipe = intel_crtc->pipe;
8116         uint32_t cntl;
8117
8118         cntl = 0;
8119         if (base) {
8120                 cntl = MCURSOR_GAMMA_ENABLE;
8121                 switch (intel_crtc->cursor_width) {
8122                         case 64:
8123                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8124                                 break;
8125                         case 128:
8126                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8127                                 break;
8128                         case 256:
8129                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8130                                 break;
8131                         default:
8132                                 WARN_ON(1);
8133                                 return;
8134                 }
8135                 cntl |= pipe << 28; /* Connect to correct pipe */
8136
8137                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8138                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8139         }
8140
8141         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8142                 cntl |= CURSOR_ROTATE_180;
8143
8144         if (intel_crtc->cursor_cntl != cntl) {
8145                 I915_WRITE(CURCNTR(pipe), cntl);
8146                 POSTING_READ(CURCNTR(pipe));
8147                 intel_crtc->cursor_cntl = cntl;
8148         }
8149
8150         /* and commit changes on next vblank */
8151         I915_WRITE(CURBASE(pipe), base);
8152         POSTING_READ(CURBASE(pipe));
8153
8154         intel_crtc->cursor_base = base;
8155 }
8156
8157 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8158 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8159                                      bool on)
8160 {
8161         struct drm_device *dev = crtc->dev;
8162         struct drm_i915_private *dev_priv = dev->dev_private;
8163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8164         int pipe = intel_crtc->pipe;
8165         int x = crtc->cursor_x;
8166         int y = crtc->cursor_y;
8167         u32 base = 0, pos = 0;
8168
8169         if (on)
8170                 base = intel_crtc->cursor_addr;
8171
8172         if (x >= intel_crtc->config.pipe_src_w)
8173                 base = 0;
8174
8175         if (y >= intel_crtc->config.pipe_src_h)
8176                 base = 0;
8177
8178         if (x < 0) {
8179                 if (x + intel_crtc->cursor_width <= 0)
8180                         base = 0;
8181
8182                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8183                 x = -x;
8184         }
8185         pos |= x << CURSOR_X_SHIFT;
8186
8187         if (y < 0) {
8188                 if (y + intel_crtc->cursor_height <= 0)
8189                         base = 0;
8190
8191                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8192                 y = -y;
8193         }
8194         pos |= y << CURSOR_Y_SHIFT;
8195
8196         if (base == 0 && intel_crtc->cursor_base == 0)
8197                 return;
8198
8199         I915_WRITE(CURPOS(pipe), pos);
8200
8201         /* ILK+ do this automagically */
8202         if (HAS_GMCH_DISPLAY(dev) &&
8203                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8204                 base += (intel_crtc->cursor_height *
8205                         intel_crtc->cursor_width - 1) * 4;
8206         }
8207
8208         if (IS_845G(dev) || IS_I865G(dev))
8209                 i845_update_cursor(crtc, base);
8210         else
8211                 i9xx_update_cursor(crtc, base);
8212 }
8213
8214 static bool cursor_size_ok(struct drm_device *dev,
8215                            uint32_t width, uint32_t height)
8216 {
8217         if (width == 0 || height == 0)
8218                 return false;
8219
8220         /*
8221          * 845g/865g are special in that they are only limited by
8222          * the width of their cursors, the height is arbitrary up to
8223          * the precision of the register. Everything else requires
8224          * square cursors, limited to a few power-of-two sizes.
8225          */
8226         if (IS_845G(dev) || IS_I865G(dev)) {
8227                 if ((width & 63) != 0)
8228                         return false;
8229
8230                 if (width > (IS_845G(dev) ? 64 : 512))
8231                         return false;
8232
8233                 if (height > 1023)
8234                         return false;
8235         } else {
8236                 switch (width | height) {
8237                 case 256:
8238                 case 128:
8239                         if (IS_GEN2(dev))
8240                                 return false;
8241                 case 64:
8242                         break;
8243                 default:
8244                         return false;
8245                 }
8246         }
8247
8248         return true;
8249 }
8250
8251 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8252                                      struct drm_i915_gem_object *obj,
8253                                      uint32_t width, uint32_t height)
8254 {
8255         struct drm_device *dev = crtc->dev;
8256         struct drm_i915_private *dev_priv = dev->dev_private;
8257         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8258         enum pipe pipe = intel_crtc->pipe;
8259         unsigned old_width;
8260         uint32_t addr;
8261         int ret;
8262
8263         /* if we want to turn off the cursor ignore width and height */
8264         if (!obj) {
8265                 DRM_DEBUG_KMS("cursor off\n");
8266                 addr = 0;
8267                 mutex_lock(&dev->struct_mutex);
8268                 goto finish;
8269         }
8270
8271         /* we only need to pin inside GTT if cursor is non-phy */
8272         mutex_lock(&dev->struct_mutex);
8273         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8274                 unsigned alignment;
8275
8276                 /*
8277                  * Global gtt pte registers are special registers which actually
8278                  * forward writes to a chunk of system memory. Which means that
8279                  * there is no risk that the register values disappear as soon
8280                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8281                  * only the pin/unpin/fence and not more.
8282                  */
8283                 intel_runtime_pm_get(dev_priv);
8284
8285                 /* Note that the w/a also requires 2 PTE of padding following
8286                  * the bo. We currently fill all unused PTE with the shadow
8287                  * page and so we should always have valid PTE following the
8288                  * cursor preventing the VT-d warning.
8289                  */
8290                 alignment = 0;
8291                 if (need_vtd_wa(dev))
8292                         alignment = 64*1024;
8293
8294                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8295                 if (ret) {
8296                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8297                         intel_runtime_pm_put(dev_priv);
8298                         goto fail_locked;
8299                 }
8300
8301                 ret = i915_gem_object_put_fence(obj);
8302                 if (ret) {
8303                         DRM_DEBUG_KMS("failed to release fence for cursor");
8304                         intel_runtime_pm_put(dev_priv);
8305                         goto fail_unpin;
8306                 }
8307
8308                 addr = i915_gem_obj_ggtt_offset(obj);
8309
8310                 intel_runtime_pm_put(dev_priv);
8311         } else {
8312                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8313                 ret = i915_gem_object_attach_phys(obj, align);
8314                 if (ret) {
8315                         DRM_DEBUG_KMS("failed to attach phys object\n");
8316                         goto fail_locked;
8317                 }
8318                 addr = obj->phys_handle->busaddr;
8319         }
8320
8321  finish:
8322         if (intel_crtc->cursor_bo) {
8323                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8324                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8325         }
8326
8327         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8328                           INTEL_FRONTBUFFER_CURSOR(pipe));
8329         mutex_unlock(&dev->struct_mutex);
8330
8331         old_width = intel_crtc->cursor_width;
8332
8333         intel_crtc->cursor_addr = addr;
8334         intel_crtc->cursor_bo = obj;
8335         intel_crtc->cursor_width = width;
8336         intel_crtc->cursor_height = height;
8337
8338         if (intel_crtc->active) {
8339                 if (old_width != width)
8340                         intel_update_watermarks(crtc);
8341                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8342
8343                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8344         }
8345
8346         return 0;
8347 fail_unpin:
8348         i915_gem_object_unpin_from_display_plane(obj);
8349 fail_locked:
8350         mutex_unlock(&dev->struct_mutex);
8351         return ret;
8352 }
8353
8354 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8355                                  u16 *blue, uint32_t start, uint32_t size)
8356 {
8357         int end = (start + size > 256) ? 256 : start + size, i;
8358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359
8360         for (i = start; i < end; i++) {
8361                 intel_crtc->lut_r[i] = red[i] >> 8;
8362                 intel_crtc->lut_g[i] = green[i] >> 8;
8363                 intel_crtc->lut_b[i] = blue[i] >> 8;
8364         }
8365
8366         intel_crtc_load_lut(crtc);
8367 }
8368
8369 /* VESA 640x480x72Hz mode to set on the pipe */
8370 static struct drm_display_mode load_detect_mode = {
8371         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8372                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8373 };
8374
8375 struct drm_framebuffer *
8376 __intel_framebuffer_create(struct drm_device *dev,
8377                            struct drm_mode_fb_cmd2 *mode_cmd,
8378                            struct drm_i915_gem_object *obj)
8379 {
8380         struct intel_framebuffer *intel_fb;
8381         int ret;
8382
8383         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8384         if (!intel_fb) {
8385                 drm_gem_object_unreference_unlocked(&obj->base);
8386                 return ERR_PTR(-ENOMEM);
8387         }
8388
8389         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8390         if (ret)
8391                 goto err;
8392
8393         return &intel_fb->base;
8394 err:
8395         drm_gem_object_unreference_unlocked(&obj->base);
8396         kfree(intel_fb);
8397
8398         return ERR_PTR(ret);
8399 }
8400
8401 static struct drm_framebuffer *
8402 intel_framebuffer_create(struct drm_device *dev,
8403                          struct drm_mode_fb_cmd2 *mode_cmd,
8404                          struct drm_i915_gem_object *obj)
8405 {
8406         struct drm_framebuffer *fb;
8407         int ret;
8408
8409         ret = i915_mutex_lock_interruptible(dev);
8410         if (ret)
8411                 return ERR_PTR(ret);
8412         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8413         mutex_unlock(&dev->struct_mutex);
8414
8415         return fb;
8416 }
8417
8418 static u32
8419 intel_framebuffer_pitch_for_width(int width, int bpp)
8420 {
8421         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8422         return ALIGN(pitch, 64);
8423 }
8424
8425 static u32
8426 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8427 {
8428         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8429         return PAGE_ALIGN(pitch * mode->vdisplay);
8430 }
8431
8432 static struct drm_framebuffer *
8433 intel_framebuffer_create_for_mode(struct drm_device *dev,
8434                                   struct drm_display_mode *mode,
8435                                   int depth, int bpp)
8436 {
8437         struct drm_i915_gem_object *obj;
8438         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8439
8440         obj = i915_gem_alloc_object(dev,
8441                                     intel_framebuffer_size_for_mode(mode, bpp));
8442         if (obj == NULL)
8443                 return ERR_PTR(-ENOMEM);
8444
8445         mode_cmd.width = mode->hdisplay;
8446         mode_cmd.height = mode->vdisplay;
8447         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8448                                                                 bpp);
8449         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8450
8451         return intel_framebuffer_create(dev, &mode_cmd, obj);
8452 }
8453
8454 static struct drm_framebuffer *
8455 mode_fits_in_fbdev(struct drm_device *dev,
8456                    struct drm_display_mode *mode)
8457 {
8458 #ifdef CONFIG_DRM_I915_FBDEV
8459         struct drm_i915_private *dev_priv = dev->dev_private;
8460         struct drm_i915_gem_object *obj;
8461         struct drm_framebuffer *fb;
8462
8463         if (!dev_priv->fbdev)
8464                 return NULL;
8465
8466         if (!dev_priv->fbdev->fb)
8467                 return NULL;
8468
8469         obj = dev_priv->fbdev->fb->obj;
8470         BUG_ON(!obj);
8471
8472         fb = &dev_priv->fbdev->fb->base;
8473         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8474                                                                fb->bits_per_pixel))
8475                 return NULL;
8476
8477         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8478                 return NULL;
8479
8480         return fb;
8481 #else
8482         return NULL;
8483 #endif
8484 }
8485
8486 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8487                                 struct drm_display_mode *mode,
8488                                 struct intel_load_detect_pipe *old,
8489                                 struct drm_modeset_acquire_ctx *ctx)
8490 {
8491         struct intel_crtc *intel_crtc;
8492         struct intel_encoder *intel_encoder =
8493                 intel_attached_encoder(connector);
8494         struct drm_crtc *possible_crtc;
8495         struct drm_encoder *encoder = &intel_encoder->base;
8496         struct drm_crtc *crtc = NULL;
8497         struct drm_device *dev = encoder->dev;
8498         struct drm_framebuffer *fb;
8499         struct drm_mode_config *config = &dev->mode_config;
8500         int ret, i = -1;
8501
8502         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8503                       connector->base.id, connector->name,
8504                       encoder->base.id, encoder->name);
8505
8506 retry:
8507         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8508         if (ret)
8509                 goto fail_unlock;
8510
8511         /*
8512          * Algorithm gets a little messy:
8513          *
8514          *   - if the connector already has an assigned crtc, use it (but make
8515          *     sure it's on first)
8516          *
8517          *   - try to find the first unused crtc that can drive this connector,
8518          *     and use that if we find one
8519          */
8520
8521         /* See if we already have a CRTC for this connector */
8522         if (encoder->crtc) {
8523                 crtc = encoder->crtc;
8524
8525                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8526                 if (ret)
8527                         goto fail_unlock;
8528
8529                 old->dpms_mode = connector->dpms;
8530                 old->load_detect_temp = false;
8531
8532                 /* Make sure the crtc and connector are running */
8533                 if (connector->dpms != DRM_MODE_DPMS_ON)
8534                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8535
8536                 return true;
8537         }
8538
8539         /* Find an unused one (if possible) */
8540         for_each_crtc(dev, possible_crtc) {
8541                 i++;
8542                 if (!(encoder->possible_crtcs & (1 << i)))
8543                         continue;
8544                 if (possible_crtc->enabled)
8545                         continue;
8546                 /* This can occur when applying the pipe A quirk on resume. */
8547                 if (to_intel_crtc(possible_crtc)->new_enabled)
8548                         continue;
8549
8550                 crtc = possible_crtc;
8551                 break;
8552         }
8553
8554         /*
8555          * If we didn't find an unused CRTC, don't use any.
8556          */
8557         if (!crtc) {
8558                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8559                 goto fail_unlock;
8560         }
8561
8562         ret = drm_modeset_lock(&crtc->mutex, ctx);
8563         if (ret)
8564                 goto fail_unlock;
8565         intel_encoder->new_crtc = to_intel_crtc(crtc);
8566         to_intel_connector(connector)->new_encoder = intel_encoder;
8567
8568         intel_crtc = to_intel_crtc(crtc);
8569         intel_crtc->new_enabled = true;
8570         intel_crtc->new_config = &intel_crtc->config;
8571         old->dpms_mode = connector->dpms;
8572         old->load_detect_temp = true;
8573         old->release_fb = NULL;
8574
8575         if (!mode)
8576                 mode = &load_detect_mode;
8577
8578         /* We need a framebuffer large enough to accommodate all accesses
8579          * that the plane may generate whilst we perform load detection.
8580          * We can not rely on the fbcon either being present (we get called
8581          * during its initialisation to detect all boot displays, or it may
8582          * not even exist) or that it is large enough to satisfy the
8583          * requested mode.
8584          */
8585         fb = mode_fits_in_fbdev(dev, mode);
8586         if (fb == NULL) {
8587                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8588                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8589                 old->release_fb = fb;
8590         } else
8591                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8592         if (IS_ERR(fb)) {
8593                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8594                 goto fail;
8595         }
8596
8597         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8598                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8599                 if (old->release_fb)
8600                         old->release_fb->funcs->destroy(old->release_fb);
8601                 goto fail;
8602         }
8603
8604         /* let the connector get through one full cycle before testing */
8605         intel_wait_for_vblank(dev, intel_crtc->pipe);
8606         return true;
8607
8608  fail:
8609         intel_crtc->new_enabled = crtc->enabled;
8610         if (intel_crtc->new_enabled)
8611                 intel_crtc->new_config = &intel_crtc->config;
8612         else
8613                 intel_crtc->new_config = NULL;
8614 fail_unlock:
8615         if (ret == -EDEADLK) {
8616                 drm_modeset_backoff(ctx);
8617                 goto retry;
8618         }
8619
8620         return false;
8621 }
8622
8623 void intel_release_load_detect_pipe(struct drm_connector *connector,
8624                                     struct intel_load_detect_pipe *old)
8625 {
8626         struct intel_encoder *intel_encoder =
8627                 intel_attached_encoder(connector);
8628         struct drm_encoder *encoder = &intel_encoder->base;
8629         struct drm_crtc *crtc = encoder->crtc;
8630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8631
8632         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8633                       connector->base.id, connector->name,
8634                       encoder->base.id, encoder->name);
8635
8636         if (old->load_detect_temp) {
8637                 to_intel_connector(connector)->new_encoder = NULL;
8638                 intel_encoder->new_crtc = NULL;
8639                 intel_crtc->new_enabled = false;
8640                 intel_crtc->new_config = NULL;
8641                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8642
8643                 if (old->release_fb) {
8644                         drm_framebuffer_unregister_private(old->release_fb);
8645                         drm_framebuffer_unreference(old->release_fb);
8646                 }
8647
8648                 return;
8649         }
8650
8651         /* Switch crtc and encoder back off if necessary */
8652         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8653                 connector->funcs->dpms(connector, old->dpms_mode);
8654 }
8655
8656 static int i9xx_pll_refclk(struct drm_device *dev,
8657                            const struct intel_crtc_config *pipe_config)
8658 {
8659         struct drm_i915_private *dev_priv = dev->dev_private;
8660         u32 dpll = pipe_config->dpll_hw_state.dpll;
8661
8662         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8663                 return dev_priv->vbt.lvds_ssc_freq;
8664         else if (HAS_PCH_SPLIT(dev))
8665                 return 120000;
8666         else if (!IS_GEN2(dev))
8667                 return 96000;
8668         else
8669                 return 48000;
8670 }
8671
8672 /* Returns the clock of the currently programmed mode of the given pipe. */
8673 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8674                                 struct intel_crtc_config *pipe_config)
8675 {
8676         struct drm_device *dev = crtc->base.dev;
8677         struct drm_i915_private *dev_priv = dev->dev_private;
8678         int pipe = pipe_config->cpu_transcoder;
8679         u32 dpll = pipe_config->dpll_hw_state.dpll;
8680         u32 fp;
8681         intel_clock_t clock;
8682         int refclk = i9xx_pll_refclk(dev, pipe_config);
8683
8684         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8685                 fp = pipe_config->dpll_hw_state.fp0;
8686         else
8687                 fp = pipe_config->dpll_hw_state.fp1;
8688
8689         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8690         if (IS_PINEVIEW(dev)) {
8691                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8692                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8693         } else {
8694                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8695                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8696         }
8697
8698         if (!IS_GEN2(dev)) {
8699                 if (IS_PINEVIEW(dev))
8700                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8701                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8702                 else
8703                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8704                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8705
8706                 switch (dpll & DPLL_MODE_MASK) {
8707                 case DPLLB_MODE_DAC_SERIAL:
8708                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8709                                 5 : 10;
8710                         break;
8711                 case DPLLB_MODE_LVDS:
8712                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8713                                 7 : 14;
8714                         break;
8715                 default:
8716                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8717                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8718                         return;
8719                 }
8720
8721                 if (IS_PINEVIEW(dev))
8722                         pineview_clock(refclk, &clock);
8723                 else
8724                         i9xx_clock(refclk, &clock);
8725         } else {
8726                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8727                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8728
8729                 if (is_lvds) {
8730                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8731                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8732
8733                         if (lvds & LVDS_CLKB_POWER_UP)
8734                                 clock.p2 = 7;
8735                         else
8736                                 clock.p2 = 14;
8737                 } else {
8738                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8739                                 clock.p1 = 2;
8740                         else {
8741                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8742                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8743                         }
8744                         if (dpll & PLL_P2_DIVIDE_BY_4)
8745                                 clock.p2 = 4;
8746                         else
8747                                 clock.p2 = 2;
8748                 }
8749
8750                 i9xx_clock(refclk, &clock);
8751         }
8752
8753         /*
8754          * This value includes pixel_multiplier. We will use
8755          * port_clock to compute adjusted_mode.crtc_clock in the
8756          * encoder's get_config() function.
8757          */
8758         pipe_config->port_clock = clock.dot;
8759 }
8760
8761 int intel_dotclock_calculate(int link_freq,
8762                              const struct intel_link_m_n *m_n)
8763 {
8764         /*
8765          * The calculation for the data clock is:
8766          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8767          * But we want to avoid losing precison if possible, so:
8768          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8769          *
8770          * and the link clock is simpler:
8771          * link_clock = (m * link_clock) / n
8772          */
8773
8774         if (!m_n->link_n)
8775                 return 0;
8776
8777         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8778 }
8779
8780 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8781                                    struct intel_crtc_config *pipe_config)
8782 {
8783         struct drm_device *dev = crtc->base.dev;
8784
8785         /* read out port_clock from the DPLL */
8786         i9xx_crtc_clock_get(crtc, pipe_config);
8787
8788         /*
8789          * This value does not include pixel_multiplier.
8790          * We will check that port_clock and adjusted_mode.crtc_clock
8791          * agree once we know their relationship in the encoder's
8792          * get_config() function.
8793          */
8794         pipe_config->adjusted_mode.crtc_clock =
8795                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8796                                          &pipe_config->fdi_m_n);
8797 }
8798
8799 /** Returns the currently programmed mode of the given pipe. */
8800 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8801                                              struct drm_crtc *crtc)
8802 {
8803         struct drm_i915_private *dev_priv = dev->dev_private;
8804         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8805         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8806         struct drm_display_mode *mode;
8807         struct intel_crtc_config pipe_config;
8808         int htot = I915_READ(HTOTAL(cpu_transcoder));
8809         int hsync = I915_READ(HSYNC(cpu_transcoder));
8810         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8811         int vsync = I915_READ(VSYNC(cpu_transcoder));
8812         enum pipe pipe = intel_crtc->pipe;
8813
8814         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8815         if (!mode)
8816                 return NULL;
8817
8818         /*
8819          * Construct a pipe_config sufficient for getting the clock info
8820          * back out of crtc_clock_get.
8821          *
8822          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8823          * to use a real value here instead.
8824          */
8825         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8826         pipe_config.pixel_multiplier = 1;
8827         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8828         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8829         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8830         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8831
8832         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8833         mode->hdisplay = (htot & 0xffff) + 1;
8834         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8835         mode->hsync_start = (hsync & 0xffff) + 1;
8836         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8837         mode->vdisplay = (vtot & 0xffff) + 1;
8838         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8839         mode->vsync_start = (vsync & 0xffff) + 1;
8840         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8841
8842         drm_mode_set_name(mode);
8843
8844         return mode;
8845 }
8846
8847 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8848 {
8849         struct drm_device *dev = crtc->dev;
8850         struct drm_i915_private *dev_priv = dev->dev_private;
8851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8852
8853         if (!HAS_GMCH_DISPLAY(dev))
8854                 return;
8855
8856         if (!dev_priv->lvds_downclock_avail)
8857                 return;
8858
8859         /*
8860          * Since this is called by a timer, we should never get here in
8861          * the manual case.
8862          */
8863         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8864                 int pipe = intel_crtc->pipe;
8865                 int dpll_reg = DPLL(pipe);
8866                 int dpll;
8867
8868                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8869
8870                 assert_panel_unlocked(dev_priv, pipe);
8871
8872                 dpll = I915_READ(dpll_reg);
8873                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8874                 I915_WRITE(dpll_reg, dpll);
8875                 intel_wait_for_vblank(dev, pipe);
8876                 dpll = I915_READ(dpll_reg);
8877                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8878                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8879         }
8880
8881 }
8882
8883 void intel_mark_busy(struct drm_device *dev)
8884 {
8885         struct drm_i915_private *dev_priv = dev->dev_private;
8886
8887         if (dev_priv->mm.busy)
8888                 return;
8889
8890         intel_runtime_pm_get(dev_priv);
8891         i915_update_gfx_val(dev_priv);
8892         dev_priv->mm.busy = true;
8893 }
8894
8895 void intel_mark_idle(struct drm_device *dev)
8896 {
8897         struct drm_i915_private *dev_priv = dev->dev_private;
8898         struct drm_crtc *crtc;
8899
8900         if (!dev_priv->mm.busy)
8901                 return;
8902
8903         dev_priv->mm.busy = false;
8904
8905         if (!i915.powersave)
8906                 goto out;
8907
8908         for_each_crtc(dev, crtc) {
8909                 if (!crtc->primary->fb)
8910                         continue;
8911
8912                 intel_decrease_pllclock(crtc);
8913         }
8914
8915         if (INTEL_INFO(dev)->gen >= 6)
8916                 gen6_rps_idle(dev->dev_private);
8917
8918 out:
8919         intel_runtime_pm_put(dev_priv);
8920 }
8921
8922 static void intel_crtc_destroy(struct drm_crtc *crtc)
8923 {
8924         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8925         struct drm_device *dev = crtc->dev;
8926         struct intel_unpin_work *work;
8927
8928         spin_lock_irq(&dev->event_lock);
8929         work = intel_crtc->unpin_work;
8930         intel_crtc->unpin_work = NULL;
8931         spin_unlock_irq(&dev->event_lock);
8932
8933         if (work) {
8934                 cancel_work_sync(&work->work);
8935                 kfree(work);
8936         }
8937
8938         drm_crtc_cleanup(crtc);
8939
8940         kfree(intel_crtc);
8941 }
8942
8943 static void intel_unpin_work_fn(struct work_struct *__work)
8944 {
8945         struct intel_unpin_work *work =
8946                 container_of(__work, struct intel_unpin_work, work);
8947         struct drm_device *dev = work->crtc->dev;
8948         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8949
8950         mutex_lock(&dev->struct_mutex);
8951         intel_unpin_fb_obj(work->old_fb_obj);
8952         drm_gem_object_unreference(&work->pending_flip_obj->base);
8953         drm_gem_object_unreference(&work->old_fb_obj->base);
8954
8955         intel_update_fbc(dev);
8956         mutex_unlock(&dev->struct_mutex);
8957
8958         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8959
8960         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8961         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8962
8963         kfree(work);
8964 }
8965
8966 static void do_intel_finish_page_flip(struct drm_device *dev,
8967                                       struct drm_crtc *crtc)
8968 {
8969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8970         struct intel_unpin_work *work;
8971         unsigned long flags;
8972
8973         /* Ignore early vblank irqs */
8974         if (intel_crtc == NULL)
8975                 return;
8976
8977         /*
8978          * This is called both by irq handlers and the reset code (to complete
8979          * lost pageflips) so needs the full irqsave spinlocks.
8980          */
8981         spin_lock_irqsave(&dev->event_lock, flags);
8982         work = intel_crtc->unpin_work;
8983
8984         /* Ensure we don't miss a work->pending update ... */
8985         smp_rmb();
8986
8987         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8988                 spin_unlock_irqrestore(&dev->event_lock, flags);
8989                 return;
8990         }
8991
8992         page_flip_completed(intel_crtc);
8993
8994         spin_unlock_irqrestore(&dev->event_lock, flags);
8995 }
8996
8997 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8998 {
8999         struct drm_i915_private *dev_priv = dev->dev_private;
9000         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9001
9002         do_intel_finish_page_flip(dev, crtc);
9003 }
9004
9005 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9006 {
9007         struct drm_i915_private *dev_priv = dev->dev_private;
9008         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9009
9010         do_intel_finish_page_flip(dev, crtc);
9011 }
9012
9013 /* Is 'a' after or equal to 'b'? */
9014 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9015 {
9016         return !((a - b) & 0x80000000);
9017 }
9018
9019 static bool page_flip_finished(struct intel_crtc *crtc)
9020 {
9021         struct drm_device *dev = crtc->base.dev;
9022         struct drm_i915_private *dev_priv = dev->dev_private;
9023
9024         /*
9025          * The relevant registers doen't exist on pre-ctg.
9026          * As the flip done interrupt doesn't trigger for mmio
9027          * flips on gmch platforms, a flip count check isn't
9028          * really needed there. But since ctg has the registers,
9029          * include it in the check anyway.
9030          */
9031         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9032                 return true;
9033
9034         /*
9035          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9036          * used the same base address. In that case the mmio flip might
9037          * have completed, but the CS hasn't even executed the flip yet.
9038          *
9039          * A flip count check isn't enough as the CS might have updated
9040          * the base address just after start of vblank, but before we
9041          * managed to process the interrupt. This means we'd complete the
9042          * CS flip too soon.
9043          *
9044          * Combining both checks should get us a good enough result. It may
9045          * still happen that the CS flip has been executed, but has not
9046          * yet actually completed. But in case the base address is the same
9047          * anyway, we don't really care.
9048          */
9049         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9050                 crtc->unpin_work->gtt_offset &&
9051                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9052                                     crtc->unpin_work->flip_count);
9053 }
9054
9055 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9056 {
9057         struct drm_i915_private *dev_priv = dev->dev_private;
9058         struct intel_crtc *intel_crtc =
9059                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9060         unsigned long flags;
9061
9062
9063         /*
9064          * This is called both by irq handlers and the reset code (to complete
9065          * lost pageflips) so needs the full irqsave spinlocks.
9066          *
9067          * NB: An MMIO update of the plane base pointer will also
9068          * generate a page-flip completion irq, i.e. every modeset
9069          * is also accompanied by a spurious intel_prepare_page_flip().
9070          */
9071         spin_lock_irqsave(&dev->event_lock, flags);
9072         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9073                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9074         spin_unlock_irqrestore(&dev->event_lock, flags);
9075 }
9076
9077 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9078 {
9079         /* Ensure that the work item is consistent when activating it ... */
9080         smp_wmb();
9081         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9082         /* and that it is marked active as soon as the irq could fire. */
9083         smp_wmb();
9084 }
9085
9086 static int intel_gen2_queue_flip(struct drm_device *dev,
9087                                  struct drm_crtc *crtc,
9088                                  struct drm_framebuffer *fb,
9089                                  struct drm_i915_gem_object *obj,
9090                                  struct intel_engine_cs *ring,
9091                                  uint32_t flags)
9092 {
9093         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9094         u32 flip_mask;
9095         int ret;
9096
9097         ret = intel_ring_begin(ring, 6);
9098         if (ret)
9099                 return ret;
9100
9101         /* Can't queue multiple flips, so wait for the previous
9102          * one to finish before executing the next.
9103          */
9104         if (intel_crtc->plane)
9105                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9106         else
9107                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9108         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9109         intel_ring_emit(ring, MI_NOOP);
9110         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9111                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9112         intel_ring_emit(ring, fb->pitches[0]);
9113         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9114         intel_ring_emit(ring, 0); /* aux display base address, unused */
9115
9116         intel_mark_page_flip_active(intel_crtc);
9117         __intel_ring_advance(ring);
9118         return 0;
9119 }
9120
9121 static int intel_gen3_queue_flip(struct drm_device *dev,
9122                                  struct drm_crtc *crtc,
9123                                  struct drm_framebuffer *fb,
9124                                  struct drm_i915_gem_object *obj,
9125                                  struct intel_engine_cs *ring,
9126                                  uint32_t flags)
9127 {
9128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9129         u32 flip_mask;
9130         int ret;
9131
9132         ret = intel_ring_begin(ring, 6);
9133         if (ret)
9134                 return ret;
9135
9136         if (intel_crtc->plane)
9137                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9138         else
9139                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9140         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9141         intel_ring_emit(ring, MI_NOOP);
9142         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9143                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9144         intel_ring_emit(ring, fb->pitches[0]);
9145         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9146         intel_ring_emit(ring, MI_NOOP);
9147
9148         intel_mark_page_flip_active(intel_crtc);
9149         __intel_ring_advance(ring);
9150         return 0;
9151 }
9152
9153 static int intel_gen4_queue_flip(struct drm_device *dev,
9154                                  struct drm_crtc *crtc,
9155                                  struct drm_framebuffer *fb,
9156                                  struct drm_i915_gem_object *obj,
9157                                  struct intel_engine_cs *ring,
9158                                  uint32_t flags)
9159 {
9160         struct drm_i915_private *dev_priv = dev->dev_private;
9161         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9162         uint32_t pf, pipesrc;
9163         int ret;
9164
9165         ret = intel_ring_begin(ring, 4);
9166         if (ret)
9167                 return ret;
9168
9169         /* i965+ uses the linear or tiled offsets from the
9170          * Display Registers (which do not change across a page-flip)
9171          * so we need only reprogram the base address.
9172          */
9173         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9174                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9175         intel_ring_emit(ring, fb->pitches[0]);
9176         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9177                         obj->tiling_mode);
9178
9179         /* XXX Enabling the panel-fitter across page-flip is so far
9180          * untested on non-native modes, so ignore it for now.
9181          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9182          */
9183         pf = 0;
9184         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9185         intel_ring_emit(ring, pf | pipesrc);
9186
9187         intel_mark_page_flip_active(intel_crtc);
9188         __intel_ring_advance(ring);
9189         return 0;
9190 }
9191
9192 static int intel_gen6_queue_flip(struct drm_device *dev,
9193                                  struct drm_crtc *crtc,
9194                                  struct drm_framebuffer *fb,
9195                                  struct drm_i915_gem_object *obj,
9196                                  struct intel_engine_cs *ring,
9197                                  uint32_t flags)
9198 {
9199         struct drm_i915_private *dev_priv = dev->dev_private;
9200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9201         uint32_t pf, pipesrc;
9202         int ret;
9203
9204         ret = intel_ring_begin(ring, 4);
9205         if (ret)
9206                 return ret;
9207
9208         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9209                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9210         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9211         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9212
9213         /* Contrary to the suggestions in the documentation,
9214          * "Enable Panel Fitter" does not seem to be required when page
9215          * flipping with a non-native mode, and worse causes a normal
9216          * modeset to fail.
9217          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9218          */
9219         pf = 0;
9220         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9221         intel_ring_emit(ring, pf | pipesrc);
9222
9223         intel_mark_page_flip_active(intel_crtc);
9224         __intel_ring_advance(ring);
9225         return 0;
9226 }
9227
9228 static int intel_gen7_queue_flip(struct drm_device *dev,
9229                                  struct drm_crtc *crtc,
9230                                  struct drm_framebuffer *fb,
9231                                  struct drm_i915_gem_object *obj,
9232                                  struct intel_engine_cs *ring,
9233                                  uint32_t flags)
9234 {
9235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9236         uint32_t plane_bit = 0;
9237         int len, ret;
9238
9239         switch (intel_crtc->plane) {
9240         case PLANE_A:
9241                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9242                 break;
9243         case PLANE_B:
9244                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9245                 break;
9246         case PLANE_C:
9247                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9248                 break;
9249         default:
9250                 WARN_ONCE(1, "unknown plane in flip command\n");
9251                 return -ENODEV;
9252         }
9253
9254         len = 4;
9255         if (ring->id == RCS) {
9256                 len += 6;
9257                 /*
9258                  * On Gen 8, SRM is now taking an extra dword to accommodate
9259                  * 48bits addresses, and we need a NOOP for the batch size to
9260                  * stay even.
9261                  */
9262                 if (IS_GEN8(dev))
9263                         len += 2;
9264         }
9265
9266         /*
9267          * BSpec MI_DISPLAY_FLIP for IVB:
9268          * "The full packet must be contained within the same cache line."
9269          *
9270          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9271          * cacheline, if we ever start emitting more commands before
9272          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9273          * then do the cacheline alignment, and finally emit the
9274          * MI_DISPLAY_FLIP.
9275          */
9276         ret = intel_ring_cacheline_align(ring);
9277         if (ret)
9278                 return ret;
9279
9280         ret = intel_ring_begin(ring, len);
9281         if (ret)
9282                 return ret;
9283
9284         /* Unmask the flip-done completion message. Note that the bspec says that
9285          * we should do this for both the BCS and RCS, and that we must not unmask
9286          * more than one flip event at any time (or ensure that one flip message
9287          * can be sent by waiting for flip-done prior to queueing new flips).
9288          * Experimentation says that BCS works despite DERRMR masking all
9289          * flip-done completion events and that unmasking all planes at once
9290          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9291          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9292          */
9293         if (ring->id == RCS) {
9294                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9295                 intel_ring_emit(ring, DERRMR);
9296                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9297                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9298                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9299                 if (IS_GEN8(dev))
9300                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9301                                               MI_SRM_LRM_GLOBAL_GTT);
9302                 else
9303                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9304                                               MI_SRM_LRM_GLOBAL_GTT);
9305                 intel_ring_emit(ring, DERRMR);
9306                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9307                 if (IS_GEN8(dev)) {
9308                         intel_ring_emit(ring, 0);
9309                         intel_ring_emit(ring, MI_NOOP);
9310                 }
9311         }
9312
9313         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9314         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9315         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9316         intel_ring_emit(ring, (MI_NOOP));
9317
9318         intel_mark_page_flip_active(intel_crtc);
9319         __intel_ring_advance(ring);
9320         return 0;
9321 }
9322
9323 static bool use_mmio_flip(struct intel_engine_cs *ring,
9324                           struct drm_i915_gem_object *obj)
9325 {
9326         /*
9327          * This is not being used for older platforms, because
9328          * non-availability of flip done interrupt forces us to use
9329          * CS flips. Older platforms derive flip done using some clever
9330          * tricks involving the flip_pending status bits and vblank irqs.
9331          * So using MMIO flips there would disrupt this mechanism.
9332          */
9333
9334         if (ring == NULL)
9335                 return true;
9336
9337         if (INTEL_INFO(ring->dev)->gen < 5)
9338                 return false;
9339
9340         if (i915.use_mmio_flip < 0)
9341                 return false;
9342         else if (i915.use_mmio_flip > 0)
9343                 return true;
9344         else if (i915.enable_execlists)
9345                 return true;
9346         else
9347                 return ring != obj->ring;
9348 }
9349
9350 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9351 {
9352         struct drm_device *dev = intel_crtc->base.dev;
9353         struct drm_i915_private *dev_priv = dev->dev_private;
9354         struct intel_framebuffer *intel_fb =
9355                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9356         struct drm_i915_gem_object *obj = intel_fb->obj;
9357         u32 dspcntr;
9358         u32 reg;
9359
9360         intel_mark_page_flip_active(intel_crtc);
9361
9362         reg = DSPCNTR(intel_crtc->plane);
9363         dspcntr = I915_READ(reg);
9364
9365         if (obj->tiling_mode != I915_TILING_NONE)
9366                 dspcntr |= DISPPLANE_TILED;
9367         else
9368                 dspcntr &= ~DISPPLANE_TILED;
9369
9370         I915_WRITE(reg, dspcntr);
9371
9372         I915_WRITE(DSPSURF(intel_crtc->plane),
9373                    intel_crtc->unpin_work->gtt_offset);
9374         POSTING_READ(DSPSURF(intel_crtc->plane));
9375 }
9376
9377 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9378 {
9379         struct intel_engine_cs *ring;
9380         int ret;
9381
9382         lockdep_assert_held(&obj->base.dev->struct_mutex);
9383
9384         if (!obj->last_write_seqno)
9385                 return 0;
9386
9387         ring = obj->ring;
9388
9389         if (i915_seqno_passed(ring->get_seqno(ring, true),
9390                               obj->last_write_seqno))
9391                 return 0;
9392
9393         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9394         if (ret)
9395                 return ret;
9396
9397         if (WARN_ON(!ring->irq_get(ring)))
9398                 return 0;
9399
9400         return 1;
9401 }
9402
9403 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9404 {
9405         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9406         struct intel_crtc *intel_crtc;
9407         unsigned long irq_flags;
9408         u32 seqno;
9409
9410         seqno = ring->get_seqno(ring, false);
9411
9412         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9413         for_each_intel_crtc(ring->dev, intel_crtc) {
9414                 struct intel_mmio_flip *mmio_flip;
9415
9416                 mmio_flip = &intel_crtc->mmio_flip;
9417                 if (mmio_flip->seqno == 0)
9418                         continue;
9419
9420                 if (ring->id != mmio_flip->ring_id)
9421                         continue;
9422
9423                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9424                         intel_do_mmio_flip(intel_crtc);
9425                         mmio_flip->seqno = 0;
9426                         ring->irq_put(ring);
9427                 }
9428         }
9429         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9430 }
9431
9432 static int intel_queue_mmio_flip(struct drm_device *dev,
9433                                  struct drm_crtc *crtc,
9434                                  struct drm_framebuffer *fb,
9435                                  struct drm_i915_gem_object *obj,
9436                                  struct intel_engine_cs *ring,
9437                                  uint32_t flags)
9438 {
9439         struct drm_i915_private *dev_priv = dev->dev_private;
9440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9441         int ret;
9442
9443         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9444                 return -EBUSY;
9445
9446         ret = intel_postpone_flip(obj);
9447         if (ret < 0)
9448                 return ret;
9449         if (ret == 0) {
9450                 intel_do_mmio_flip(intel_crtc);
9451                 return 0;
9452         }
9453
9454         spin_lock_irq(&dev_priv->mmio_flip_lock);
9455         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9456         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9457         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9458
9459         /*
9460          * Double check to catch cases where irq fired before
9461          * mmio flip data was ready
9462          */
9463         intel_notify_mmio_flip(obj->ring);
9464         return 0;
9465 }
9466
9467 static int intel_default_queue_flip(struct drm_device *dev,
9468                                     struct drm_crtc *crtc,
9469                                     struct drm_framebuffer *fb,
9470                                     struct drm_i915_gem_object *obj,
9471                                     struct intel_engine_cs *ring,
9472                                     uint32_t flags)
9473 {
9474         return -ENODEV;
9475 }
9476
9477 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9478                                          struct drm_crtc *crtc)
9479 {
9480         struct drm_i915_private *dev_priv = dev->dev_private;
9481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9482         struct intel_unpin_work *work = intel_crtc->unpin_work;
9483         u32 addr;
9484
9485         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9486                 return true;
9487
9488         if (!work->enable_stall_check)
9489                 return false;
9490
9491         if (work->flip_ready_vblank == 0) {
9492                 if (work->flip_queued_ring &&
9493                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9494                                        work->flip_queued_seqno))
9495                         return false;
9496
9497                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9498         }
9499
9500         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9501                 return false;
9502
9503         /* Potential stall - if we see that the flip has happened,
9504          * assume a missed interrupt. */
9505         if (INTEL_INFO(dev)->gen >= 4)
9506                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9507         else
9508                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9509
9510         /* There is a potential issue here with a false positive after a flip
9511          * to the same address. We could address this by checking for a
9512          * non-incrementing frame counter.
9513          */
9514         return addr == work->gtt_offset;
9515 }
9516
9517 void intel_check_page_flip(struct drm_device *dev, int pipe)
9518 {
9519         struct drm_i915_private *dev_priv = dev->dev_private;
9520         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9522
9523         WARN_ON(!in_irq());
9524
9525         if (crtc == NULL)
9526                 return;
9527
9528         spin_lock(&dev->event_lock);
9529         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9530                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9531                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9532                 page_flip_completed(intel_crtc);
9533         }
9534         spin_unlock(&dev->event_lock);
9535 }
9536
9537 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9538                                 struct drm_framebuffer *fb,
9539                                 struct drm_pending_vblank_event *event,
9540                                 uint32_t page_flip_flags)
9541 {
9542         struct drm_device *dev = crtc->dev;
9543         struct drm_i915_private *dev_priv = dev->dev_private;
9544         struct drm_framebuffer *old_fb = crtc->primary->fb;
9545         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9547         enum pipe pipe = intel_crtc->pipe;
9548         struct intel_unpin_work *work;
9549         struct intel_engine_cs *ring;
9550         int ret;
9551
9552         /*
9553          * drm_mode_page_flip_ioctl() should already catch this, but double
9554          * check to be safe.  In the future we may enable pageflipping from
9555          * a disabled primary plane.
9556          */
9557         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9558                 return -EBUSY;
9559
9560         /* Can't change pixel format via MI display flips. */
9561         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9562                 return -EINVAL;
9563
9564         /*
9565          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9566          * Note that pitch changes could also affect these register.
9567          */
9568         if (INTEL_INFO(dev)->gen > 3 &&
9569             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9570              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9571                 return -EINVAL;
9572
9573         if (i915_terminally_wedged(&dev_priv->gpu_error))
9574                 goto out_hang;
9575
9576         work = kzalloc(sizeof(*work), GFP_KERNEL);
9577         if (work == NULL)
9578                 return -ENOMEM;
9579
9580         work->event = event;
9581         work->crtc = crtc;
9582         work->old_fb_obj = intel_fb_obj(old_fb);
9583         INIT_WORK(&work->work, intel_unpin_work_fn);
9584
9585         ret = drm_crtc_vblank_get(crtc);
9586         if (ret)
9587                 goto free_work;
9588
9589         /* We borrow the event spin lock for protecting unpin_work */
9590         spin_lock_irq(&dev->event_lock);
9591         if (intel_crtc->unpin_work) {
9592                 /* Before declaring the flip queue wedged, check if
9593                  * the hardware completed the operation behind our backs.
9594                  */
9595                 if (__intel_pageflip_stall_check(dev, crtc)) {
9596                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9597                         page_flip_completed(intel_crtc);
9598                 } else {
9599                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9600                         spin_unlock_irq(&dev->event_lock);
9601
9602                         drm_crtc_vblank_put(crtc);
9603                         kfree(work);
9604                         return -EBUSY;
9605                 }
9606         }
9607         intel_crtc->unpin_work = work;
9608         spin_unlock_irq(&dev->event_lock);
9609
9610         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9611                 flush_workqueue(dev_priv->wq);
9612
9613         ret = i915_mutex_lock_interruptible(dev);
9614         if (ret)
9615                 goto cleanup;
9616
9617         /* Reference the objects for the scheduled work. */
9618         drm_gem_object_reference(&work->old_fb_obj->base);
9619         drm_gem_object_reference(&obj->base);
9620
9621         crtc->primary->fb = fb;
9622
9623         work->pending_flip_obj = obj;
9624
9625         atomic_inc(&intel_crtc->unpin_work_count);
9626         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9627
9628         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9629                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9630
9631         if (IS_VALLEYVIEW(dev)) {
9632                 ring = &dev_priv->ring[BCS];
9633                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9634                         /* vlv: DISPLAY_FLIP fails to change tiling */
9635                         ring = NULL;
9636         } else if (IS_IVYBRIDGE(dev)) {
9637                 ring = &dev_priv->ring[BCS];
9638         } else if (INTEL_INFO(dev)->gen >= 7) {
9639                 ring = obj->ring;
9640                 if (ring == NULL || ring->id != RCS)
9641                         ring = &dev_priv->ring[BCS];
9642         } else {
9643                 ring = &dev_priv->ring[RCS];
9644         }
9645
9646         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9647         if (ret)
9648                 goto cleanup_pending;
9649
9650         work->gtt_offset =
9651                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9652
9653         if (use_mmio_flip(ring, obj)) {
9654                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9655                                             page_flip_flags);
9656                 if (ret)
9657                         goto cleanup_unpin;
9658
9659                 work->flip_queued_seqno = obj->last_write_seqno;
9660                 work->flip_queued_ring = obj->ring;
9661         } else {
9662                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9663                                                    page_flip_flags);
9664                 if (ret)
9665                         goto cleanup_unpin;
9666
9667                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9668                 work->flip_queued_ring = ring;
9669         }
9670
9671         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9672         work->enable_stall_check = true;
9673
9674         i915_gem_track_fb(work->old_fb_obj, obj,
9675                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9676
9677         intel_disable_fbc(dev);
9678         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9679         mutex_unlock(&dev->struct_mutex);
9680
9681         trace_i915_flip_request(intel_crtc->plane, obj);
9682
9683         return 0;
9684
9685 cleanup_unpin:
9686         intel_unpin_fb_obj(obj);
9687 cleanup_pending:
9688         atomic_dec(&intel_crtc->unpin_work_count);
9689         crtc->primary->fb = old_fb;
9690         drm_gem_object_unreference(&work->old_fb_obj->base);
9691         drm_gem_object_unreference(&obj->base);
9692         mutex_unlock(&dev->struct_mutex);
9693
9694 cleanup:
9695         spin_lock_irq(&dev->event_lock);
9696         intel_crtc->unpin_work = NULL;
9697         spin_unlock_irq(&dev->event_lock);
9698
9699         drm_crtc_vblank_put(crtc);
9700 free_work:
9701         kfree(work);
9702
9703         if (ret == -EIO) {
9704 out_hang:
9705                 intel_crtc_wait_for_pending_flips(crtc);
9706                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9707                 if (ret == 0 && event) {
9708                         spin_lock_irq(&dev->event_lock);
9709                         drm_send_vblank_event(dev, pipe, event);
9710                         spin_unlock_irq(&dev->event_lock);
9711                 }
9712         }
9713         return ret;
9714 }
9715
9716 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9717         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9718         .load_lut = intel_crtc_load_lut,
9719 };
9720
9721 /**
9722  * intel_modeset_update_staged_output_state
9723  *
9724  * Updates the staged output configuration state, e.g. after we've read out the
9725  * current hw state.
9726  */
9727 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9728 {
9729         struct intel_crtc *crtc;
9730         struct intel_encoder *encoder;
9731         struct intel_connector *connector;
9732
9733         list_for_each_entry(connector, &dev->mode_config.connector_list,
9734                             base.head) {
9735                 connector->new_encoder =
9736                         to_intel_encoder(connector->base.encoder);
9737         }
9738
9739         for_each_intel_encoder(dev, encoder) {
9740                 encoder->new_crtc =
9741                         to_intel_crtc(encoder->base.crtc);
9742         }
9743
9744         for_each_intel_crtc(dev, crtc) {
9745                 crtc->new_enabled = crtc->base.enabled;
9746
9747                 if (crtc->new_enabled)
9748                         crtc->new_config = &crtc->config;
9749                 else
9750                         crtc->new_config = NULL;
9751         }
9752 }
9753
9754 /**
9755  * intel_modeset_commit_output_state
9756  *
9757  * This function copies the stage display pipe configuration to the real one.
9758  */
9759 static void intel_modeset_commit_output_state(struct drm_device *dev)
9760 {
9761         struct intel_crtc *crtc;
9762         struct intel_encoder *encoder;
9763         struct intel_connector *connector;
9764
9765         list_for_each_entry(connector, &dev->mode_config.connector_list,
9766                             base.head) {
9767                 connector->base.encoder = &connector->new_encoder->base;
9768         }
9769
9770         for_each_intel_encoder(dev, encoder) {
9771                 encoder->base.crtc = &encoder->new_crtc->base;
9772         }
9773
9774         for_each_intel_crtc(dev, crtc) {
9775                 crtc->base.enabled = crtc->new_enabled;
9776         }
9777 }
9778
9779 static void
9780 connected_sink_compute_bpp(struct intel_connector *connector,
9781                            struct intel_crtc_config *pipe_config)
9782 {
9783         int bpp = pipe_config->pipe_bpp;
9784
9785         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9786                 connector->base.base.id,
9787                 connector->base.name);
9788
9789         /* Don't use an invalid EDID bpc value */
9790         if (connector->base.display_info.bpc &&
9791             connector->base.display_info.bpc * 3 < bpp) {
9792                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9793                               bpp, connector->base.display_info.bpc*3);
9794                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9795         }
9796
9797         /* Clamp bpp to 8 on screens without EDID 1.4 */
9798         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9799                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9800                               bpp);
9801                 pipe_config->pipe_bpp = 24;
9802         }
9803 }
9804
9805 static int
9806 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9807                           struct drm_framebuffer *fb,
9808                           struct intel_crtc_config *pipe_config)
9809 {
9810         struct drm_device *dev = crtc->base.dev;
9811         struct intel_connector *connector;
9812         int bpp;
9813
9814         switch (fb->pixel_format) {
9815         case DRM_FORMAT_C8:
9816                 bpp = 8*3; /* since we go through a colormap */
9817                 break;
9818         case DRM_FORMAT_XRGB1555:
9819         case DRM_FORMAT_ARGB1555:
9820                 /* checked in intel_framebuffer_init already */
9821                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9822                         return -EINVAL;
9823         case DRM_FORMAT_RGB565:
9824                 bpp = 6*3; /* min is 18bpp */
9825                 break;
9826         case DRM_FORMAT_XBGR8888:
9827         case DRM_FORMAT_ABGR8888:
9828                 /* checked in intel_framebuffer_init already */
9829                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9830                         return -EINVAL;
9831         case DRM_FORMAT_XRGB8888:
9832         case DRM_FORMAT_ARGB8888:
9833                 bpp = 8*3;
9834                 break;
9835         case DRM_FORMAT_XRGB2101010:
9836         case DRM_FORMAT_ARGB2101010:
9837         case DRM_FORMAT_XBGR2101010:
9838         case DRM_FORMAT_ABGR2101010:
9839                 /* checked in intel_framebuffer_init already */
9840                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9841                         return -EINVAL;
9842                 bpp = 10*3;
9843                 break;
9844         /* TODO: gen4+ supports 16 bpc floating point, too. */
9845         default:
9846                 DRM_DEBUG_KMS("unsupported depth\n");
9847                 return -EINVAL;
9848         }
9849
9850         pipe_config->pipe_bpp = bpp;
9851
9852         /* Clamp display bpp to EDID value */
9853         list_for_each_entry(connector, &dev->mode_config.connector_list,
9854                             base.head) {
9855                 if (!connector->new_encoder ||
9856                     connector->new_encoder->new_crtc != crtc)
9857                         continue;
9858
9859                 connected_sink_compute_bpp(connector, pipe_config);
9860         }
9861
9862         return bpp;
9863 }
9864
9865 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9866 {
9867         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9868                         "type: 0x%x flags: 0x%x\n",
9869                 mode->crtc_clock,
9870                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9871                 mode->crtc_hsync_end, mode->crtc_htotal,
9872                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9873                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9874 }
9875
9876 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9877                                    struct intel_crtc_config *pipe_config,
9878                                    const char *context)
9879 {
9880         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9881                       context, pipe_name(crtc->pipe));
9882
9883         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9884         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9885                       pipe_config->pipe_bpp, pipe_config->dither);
9886         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9887                       pipe_config->has_pch_encoder,
9888                       pipe_config->fdi_lanes,
9889                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9890                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9891                       pipe_config->fdi_m_n.tu);
9892         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9893                       pipe_config->has_dp_encoder,
9894                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9895                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9896                       pipe_config->dp_m_n.tu);
9897
9898         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9899                       pipe_config->has_dp_encoder,
9900                       pipe_config->dp_m2_n2.gmch_m,
9901                       pipe_config->dp_m2_n2.gmch_n,
9902                       pipe_config->dp_m2_n2.link_m,
9903                       pipe_config->dp_m2_n2.link_n,
9904                       pipe_config->dp_m2_n2.tu);
9905
9906         DRM_DEBUG_KMS("requested mode:\n");
9907         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9908         DRM_DEBUG_KMS("adjusted mode:\n");
9909         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9910         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9911         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9912         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9913                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9914         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9915                       pipe_config->gmch_pfit.control,
9916                       pipe_config->gmch_pfit.pgm_ratios,
9917                       pipe_config->gmch_pfit.lvds_border_bits);
9918         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9919                       pipe_config->pch_pfit.pos,
9920                       pipe_config->pch_pfit.size,
9921                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9922         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9923         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9924 }
9925
9926 static bool encoders_cloneable(const struct intel_encoder *a,
9927                                const struct intel_encoder *b)
9928 {
9929         /* masks could be asymmetric, so check both ways */
9930         return a == b || (a->cloneable & (1 << b->type) &&
9931                           b->cloneable & (1 << a->type));
9932 }
9933
9934 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9935                                          struct intel_encoder *encoder)
9936 {
9937         struct drm_device *dev = crtc->base.dev;
9938         struct intel_encoder *source_encoder;
9939
9940         for_each_intel_encoder(dev, source_encoder) {
9941                 if (source_encoder->new_crtc != crtc)
9942                         continue;
9943
9944                 if (!encoders_cloneable(encoder, source_encoder))
9945                         return false;
9946         }
9947
9948         return true;
9949 }
9950
9951 static bool check_encoder_cloning(struct intel_crtc *crtc)
9952 {
9953         struct drm_device *dev = crtc->base.dev;
9954         struct intel_encoder *encoder;
9955
9956         for_each_intel_encoder(dev, encoder) {
9957                 if (encoder->new_crtc != crtc)
9958                         continue;
9959
9960                 if (!check_single_encoder_cloning(crtc, encoder))
9961                         return false;
9962         }
9963
9964         return true;
9965 }
9966
9967 static struct intel_crtc_config *
9968 intel_modeset_pipe_config(struct drm_crtc *crtc,
9969                           struct drm_framebuffer *fb,
9970                           struct drm_display_mode *mode)
9971 {
9972         struct drm_device *dev = crtc->dev;
9973         struct intel_encoder *encoder;
9974         struct intel_crtc_config *pipe_config;
9975         int plane_bpp, ret = -EINVAL;
9976         bool retry = true;
9977
9978         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9979                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9980                 return ERR_PTR(-EINVAL);
9981         }
9982
9983         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9984         if (!pipe_config)
9985                 return ERR_PTR(-ENOMEM);
9986
9987         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9988         drm_mode_copy(&pipe_config->requested_mode, mode);
9989
9990         pipe_config->cpu_transcoder =
9991                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9992         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9993
9994         /*
9995          * Sanitize sync polarity flags based on requested ones. If neither
9996          * positive or negative polarity is requested, treat this as meaning
9997          * negative polarity.
9998          */
9999         if (!(pipe_config->adjusted_mode.flags &
10000               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10001                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10002
10003         if (!(pipe_config->adjusted_mode.flags &
10004               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10005                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10006
10007         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10008          * plane pixel format and any sink constraints into account. Returns the
10009          * source plane bpp so that dithering can be selected on mismatches
10010          * after encoders and crtc also have had their say. */
10011         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10012                                               fb, pipe_config);
10013         if (plane_bpp < 0)
10014                 goto fail;
10015
10016         /*
10017          * Determine the real pipe dimensions. Note that stereo modes can
10018          * increase the actual pipe size due to the frame doubling and
10019          * insertion of additional space for blanks between the frame. This
10020          * is stored in the crtc timings. We use the requested mode to do this
10021          * computation to clearly distinguish it from the adjusted mode, which
10022          * can be changed by the connectors in the below retry loop.
10023          */
10024         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10025         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10026         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10027
10028 encoder_retry:
10029         /* Ensure the port clock defaults are reset when retrying. */
10030         pipe_config->port_clock = 0;
10031         pipe_config->pixel_multiplier = 1;
10032
10033         /* Fill in default crtc timings, allow encoders to overwrite them. */
10034         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10035
10036         /* Pass our mode to the connectors and the CRTC to give them a chance to
10037          * adjust it according to limitations or connector properties, and also
10038          * a chance to reject the mode entirely.
10039          */
10040         for_each_intel_encoder(dev, encoder) {
10041
10042                 if (&encoder->new_crtc->base != crtc)
10043                         continue;
10044
10045                 if (!(encoder->compute_config(encoder, pipe_config))) {
10046                         DRM_DEBUG_KMS("Encoder config failure\n");
10047                         goto fail;
10048                 }
10049         }
10050
10051         /* Set default port clock if not overwritten by the encoder. Needs to be
10052          * done afterwards in case the encoder adjusts the mode. */
10053         if (!pipe_config->port_clock)
10054                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10055                         * pipe_config->pixel_multiplier;
10056
10057         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10058         if (ret < 0) {
10059                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10060                 goto fail;
10061         }
10062
10063         if (ret == RETRY) {
10064                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10065                         ret = -EINVAL;
10066                         goto fail;
10067                 }
10068
10069                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10070                 retry = false;
10071                 goto encoder_retry;
10072         }
10073
10074         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10075         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10076                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10077
10078         return pipe_config;
10079 fail:
10080         kfree(pipe_config);
10081         return ERR_PTR(ret);
10082 }
10083
10084 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10085  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10086 static void
10087 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10088                              unsigned *prepare_pipes, unsigned *disable_pipes)
10089 {
10090         struct intel_crtc *intel_crtc;
10091         struct drm_device *dev = crtc->dev;
10092         struct intel_encoder *encoder;
10093         struct intel_connector *connector;
10094         struct drm_crtc *tmp_crtc;
10095
10096         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10097
10098         /* Check which crtcs have changed outputs connected to them, these need
10099          * to be part of the prepare_pipes mask. We don't (yet) support global
10100          * modeset across multiple crtcs, so modeset_pipes will only have one
10101          * bit set at most. */
10102         list_for_each_entry(connector, &dev->mode_config.connector_list,
10103                             base.head) {
10104                 if (connector->base.encoder == &connector->new_encoder->base)
10105                         continue;
10106
10107                 if (connector->base.encoder) {
10108                         tmp_crtc = connector->base.encoder->crtc;
10109
10110                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10111                 }
10112
10113                 if (connector->new_encoder)
10114                         *prepare_pipes |=
10115                                 1 << connector->new_encoder->new_crtc->pipe;
10116         }
10117
10118         for_each_intel_encoder(dev, encoder) {
10119                 if (encoder->base.crtc == &encoder->new_crtc->base)
10120                         continue;
10121
10122                 if (encoder->base.crtc) {
10123                         tmp_crtc = encoder->base.crtc;
10124
10125                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10126                 }
10127
10128                 if (encoder->new_crtc)
10129                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10130         }
10131
10132         /* Check for pipes that will be enabled/disabled ... */
10133         for_each_intel_crtc(dev, intel_crtc) {
10134                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10135                         continue;
10136
10137                 if (!intel_crtc->new_enabled)
10138                         *disable_pipes |= 1 << intel_crtc->pipe;
10139                 else
10140                         *prepare_pipes |= 1 << intel_crtc->pipe;
10141         }
10142
10143
10144         /* set_mode is also used to update properties on life display pipes. */
10145         intel_crtc = to_intel_crtc(crtc);
10146         if (intel_crtc->new_enabled)
10147                 *prepare_pipes |= 1 << intel_crtc->pipe;
10148
10149         /*
10150          * For simplicity do a full modeset on any pipe where the output routing
10151          * changed. We could be more clever, but that would require us to be
10152          * more careful with calling the relevant encoder->mode_set functions.
10153          */
10154         if (*prepare_pipes)
10155                 *modeset_pipes = *prepare_pipes;
10156
10157         /* ... and mask these out. */
10158         *modeset_pipes &= ~(*disable_pipes);
10159         *prepare_pipes &= ~(*disable_pipes);
10160
10161         /*
10162          * HACK: We don't (yet) fully support global modesets. intel_set_config
10163          * obies this rule, but the modeset restore mode of
10164          * intel_modeset_setup_hw_state does not.
10165          */
10166         *modeset_pipes &= 1 << intel_crtc->pipe;
10167         *prepare_pipes &= 1 << intel_crtc->pipe;
10168
10169         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10170                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10171 }
10172
10173 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10174 {
10175         struct drm_encoder *encoder;
10176         struct drm_device *dev = crtc->dev;
10177
10178         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10179                 if (encoder->crtc == crtc)
10180                         return true;
10181
10182         return false;
10183 }
10184
10185 static void
10186 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10187 {
10188         struct intel_encoder *intel_encoder;
10189         struct intel_crtc *intel_crtc;
10190         struct drm_connector *connector;
10191
10192         for_each_intel_encoder(dev, intel_encoder) {
10193                 if (!intel_encoder->base.crtc)
10194                         continue;
10195
10196                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10197
10198                 if (prepare_pipes & (1 << intel_crtc->pipe))
10199                         intel_encoder->connectors_active = false;
10200         }
10201
10202         intel_modeset_commit_output_state(dev);
10203
10204         /* Double check state. */
10205         for_each_intel_crtc(dev, intel_crtc) {
10206                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10207                 WARN_ON(intel_crtc->new_config &&
10208                         intel_crtc->new_config != &intel_crtc->config);
10209                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10210         }
10211
10212         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10213                 if (!connector->encoder || !connector->encoder->crtc)
10214                         continue;
10215
10216                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10217
10218                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10219                         struct drm_property *dpms_property =
10220                                 dev->mode_config.dpms_property;
10221
10222                         connector->dpms = DRM_MODE_DPMS_ON;
10223                         drm_object_property_set_value(&connector->base,
10224                                                          dpms_property,
10225                                                          DRM_MODE_DPMS_ON);
10226
10227                         intel_encoder = to_intel_encoder(connector->encoder);
10228                         intel_encoder->connectors_active = true;
10229                 }
10230         }
10231
10232 }
10233
10234 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10235 {
10236         int diff;
10237
10238         if (clock1 == clock2)
10239                 return true;
10240
10241         if (!clock1 || !clock2)
10242                 return false;
10243
10244         diff = abs(clock1 - clock2);
10245
10246         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10247                 return true;
10248
10249         return false;
10250 }
10251
10252 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10253         list_for_each_entry((intel_crtc), \
10254                             &(dev)->mode_config.crtc_list, \
10255                             base.head) \
10256                 if (mask & (1 <<(intel_crtc)->pipe))
10257
10258 static bool
10259 intel_pipe_config_compare(struct drm_device *dev,
10260                           struct intel_crtc_config *current_config,
10261                           struct intel_crtc_config *pipe_config)
10262 {
10263 #define PIPE_CONF_CHECK_X(name) \
10264         if (current_config->name != pipe_config->name) { \
10265                 DRM_ERROR("mismatch in " #name " " \
10266                           "(expected 0x%08x, found 0x%08x)\n", \
10267                           current_config->name, \
10268                           pipe_config->name); \
10269                 return false; \
10270         }
10271
10272 #define PIPE_CONF_CHECK_I(name) \
10273         if (current_config->name != pipe_config->name) { \
10274                 DRM_ERROR("mismatch in " #name " " \
10275                           "(expected %i, found %i)\n", \
10276                           current_config->name, \
10277                           pipe_config->name); \
10278                 return false; \
10279         }
10280
10281 /* This is required for BDW+ where there is only one set of registers for
10282  * switching between high and low RR.
10283  * This macro can be used whenever a comparison has to be made between one
10284  * hw state and multiple sw state variables.
10285  */
10286 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10287         if ((current_config->name != pipe_config->name) && \
10288                 (current_config->alt_name != pipe_config->name)) { \
10289                         DRM_ERROR("mismatch in " #name " " \
10290                                   "(expected %i or %i, found %i)\n", \
10291                                   current_config->name, \
10292                                   current_config->alt_name, \
10293                                   pipe_config->name); \
10294                         return false; \
10295         }
10296
10297 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10298         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10299                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10300                           "(expected %i, found %i)\n", \
10301                           current_config->name & (mask), \
10302                           pipe_config->name & (mask)); \
10303                 return false; \
10304         }
10305
10306 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10307         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10308                 DRM_ERROR("mismatch in " #name " " \
10309                           "(expected %i, found %i)\n", \
10310                           current_config->name, \
10311                           pipe_config->name); \
10312                 return false; \
10313         }
10314
10315 #define PIPE_CONF_QUIRK(quirk)  \
10316         ((current_config->quirks | pipe_config->quirks) & (quirk))
10317
10318         PIPE_CONF_CHECK_I(cpu_transcoder);
10319
10320         PIPE_CONF_CHECK_I(has_pch_encoder);
10321         PIPE_CONF_CHECK_I(fdi_lanes);
10322         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10323         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10324         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10325         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10326         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10327
10328         PIPE_CONF_CHECK_I(has_dp_encoder);
10329
10330         if (INTEL_INFO(dev)->gen < 8) {
10331                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10332                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10333                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10334                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10335                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10336
10337                 if (current_config->has_drrs) {
10338                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10339                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10340                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10341                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10342                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10343                 }
10344         } else {
10345                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10346                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10347                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10348                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10349                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10350         }
10351
10352         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10354         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10355         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10357         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10358
10359         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10360         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10361         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10362         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10363         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10364         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10365
10366         PIPE_CONF_CHECK_I(pixel_multiplier);
10367         PIPE_CONF_CHECK_I(has_hdmi_sink);
10368         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10369             IS_VALLEYVIEW(dev))
10370                 PIPE_CONF_CHECK_I(limited_color_range);
10371
10372         PIPE_CONF_CHECK_I(has_audio);
10373
10374         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10375                               DRM_MODE_FLAG_INTERLACE);
10376
10377         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10378                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10379                                       DRM_MODE_FLAG_PHSYNC);
10380                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10381                                       DRM_MODE_FLAG_NHSYNC);
10382                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10383                                       DRM_MODE_FLAG_PVSYNC);
10384                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10385                                       DRM_MODE_FLAG_NVSYNC);
10386         }
10387
10388         PIPE_CONF_CHECK_I(pipe_src_w);
10389         PIPE_CONF_CHECK_I(pipe_src_h);
10390
10391         /*
10392          * FIXME: BIOS likes to set up a cloned config with lvds+external
10393          * screen. Since we don't yet re-compute the pipe config when moving
10394          * just the lvds port away to another pipe the sw tracking won't match.
10395          *
10396          * Proper atomic modesets with recomputed global state will fix this.
10397          * Until then just don't check gmch state for inherited modes.
10398          */
10399         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10400                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10401                 /* pfit ratios are autocomputed by the hw on gen4+ */
10402                 if (INTEL_INFO(dev)->gen < 4)
10403                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10404                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10405         }
10406
10407         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10408         if (current_config->pch_pfit.enabled) {
10409                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10410                 PIPE_CONF_CHECK_I(pch_pfit.size);
10411         }
10412
10413         /* BDW+ don't expose a synchronous way to read the state */
10414         if (IS_HASWELL(dev))
10415                 PIPE_CONF_CHECK_I(ips_enabled);
10416
10417         PIPE_CONF_CHECK_I(double_wide);
10418
10419         PIPE_CONF_CHECK_X(ddi_pll_sel);
10420
10421         PIPE_CONF_CHECK_I(shared_dpll);
10422         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10423         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10424         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10425         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10426         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10427
10428         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10429                 PIPE_CONF_CHECK_I(pipe_bpp);
10430
10431         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10432         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10433
10434 #undef PIPE_CONF_CHECK_X
10435 #undef PIPE_CONF_CHECK_I
10436 #undef PIPE_CONF_CHECK_I_ALT
10437 #undef PIPE_CONF_CHECK_FLAGS
10438 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10439 #undef PIPE_CONF_QUIRK
10440
10441         return true;
10442 }
10443
10444 static void
10445 check_connector_state(struct drm_device *dev)
10446 {
10447         struct intel_connector *connector;
10448
10449         list_for_each_entry(connector, &dev->mode_config.connector_list,
10450                             base.head) {
10451                 /* This also checks the encoder/connector hw state with the
10452                  * ->get_hw_state callbacks. */
10453                 intel_connector_check_state(connector);
10454
10455                 WARN(&connector->new_encoder->base != connector->base.encoder,
10456                      "connector's staged encoder doesn't match current encoder\n");
10457         }
10458 }
10459
10460 static void
10461 check_encoder_state(struct drm_device *dev)
10462 {
10463         struct intel_encoder *encoder;
10464         struct intel_connector *connector;
10465
10466         for_each_intel_encoder(dev, encoder) {
10467                 bool enabled = false;
10468                 bool active = false;
10469                 enum pipe pipe, tracked_pipe;
10470
10471                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10472                               encoder->base.base.id,
10473                               encoder->base.name);
10474
10475                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10476                      "encoder's stage crtc doesn't match current crtc\n");
10477                 WARN(encoder->connectors_active && !encoder->base.crtc,
10478                      "encoder's active_connectors set, but no crtc\n");
10479
10480                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10481                                     base.head) {
10482                         if (connector->base.encoder != &encoder->base)
10483                                 continue;
10484                         enabled = true;
10485                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10486                                 active = true;
10487                 }
10488                 /*
10489                  * for MST connectors if we unplug the connector is gone
10490                  * away but the encoder is still connected to a crtc
10491                  * until a modeset happens in response to the hotplug.
10492                  */
10493                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10494                         continue;
10495
10496                 WARN(!!encoder->base.crtc != enabled,
10497                      "encoder's enabled state mismatch "
10498                      "(expected %i, found %i)\n",
10499                      !!encoder->base.crtc, enabled);
10500                 WARN(active && !encoder->base.crtc,
10501                      "active encoder with no crtc\n");
10502
10503                 WARN(encoder->connectors_active != active,
10504                      "encoder's computed active state doesn't match tracked active state "
10505                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10506
10507                 active = encoder->get_hw_state(encoder, &pipe);
10508                 WARN(active != encoder->connectors_active,
10509                      "encoder's hw state doesn't match sw tracking "
10510                      "(expected %i, found %i)\n",
10511                      encoder->connectors_active, active);
10512
10513                 if (!encoder->base.crtc)
10514                         continue;
10515
10516                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10517                 WARN(active && pipe != tracked_pipe,
10518                      "active encoder's pipe doesn't match"
10519                      "(expected %i, found %i)\n",
10520                      tracked_pipe, pipe);
10521
10522         }
10523 }
10524
10525 static void
10526 check_crtc_state(struct drm_device *dev)
10527 {
10528         struct drm_i915_private *dev_priv = dev->dev_private;
10529         struct intel_crtc *crtc;
10530         struct intel_encoder *encoder;
10531         struct intel_crtc_config pipe_config;
10532
10533         for_each_intel_crtc(dev, crtc) {
10534                 bool enabled = false;
10535                 bool active = false;
10536
10537                 memset(&pipe_config, 0, sizeof(pipe_config));
10538
10539                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10540                               crtc->base.base.id);
10541
10542                 WARN(crtc->active && !crtc->base.enabled,
10543                      "active crtc, but not enabled in sw tracking\n");
10544
10545                 for_each_intel_encoder(dev, encoder) {
10546                         if (encoder->base.crtc != &crtc->base)
10547                                 continue;
10548                         enabled = true;
10549                         if (encoder->connectors_active)
10550                                 active = true;
10551                 }
10552
10553                 WARN(active != crtc->active,
10554                      "crtc's computed active state doesn't match tracked active state "
10555                      "(expected %i, found %i)\n", active, crtc->active);
10556                 WARN(enabled != crtc->base.enabled,
10557                      "crtc's computed enabled state doesn't match tracked enabled state "
10558                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10559
10560                 active = dev_priv->display.get_pipe_config(crtc,
10561                                                            &pipe_config);
10562
10563                 /* hw state is inconsistent with the pipe quirk */
10564                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10565                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10566                         active = crtc->active;
10567
10568                 for_each_intel_encoder(dev, encoder) {
10569                         enum pipe pipe;
10570                         if (encoder->base.crtc != &crtc->base)
10571                                 continue;
10572                         if (encoder->get_hw_state(encoder, &pipe))
10573                                 encoder->get_config(encoder, &pipe_config);
10574                 }
10575
10576                 WARN(crtc->active != active,
10577                      "crtc active state doesn't match with hw state "
10578                      "(expected %i, found %i)\n", crtc->active, active);
10579
10580                 if (active &&
10581                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10582                         WARN(1, "pipe state doesn't match!\n");
10583                         intel_dump_pipe_config(crtc, &pipe_config,
10584                                                "[hw state]");
10585                         intel_dump_pipe_config(crtc, &crtc->config,
10586                                                "[sw state]");
10587                 }
10588         }
10589 }
10590
10591 static void
10592 check_shared_dpll_state(struct drm_device *dev)
10593 {
10594         struct drm_i915_private *dev_priv = dev->dev_private;
10595         struct intel_crtc *crtc;
10596         struct intel_dpll_hw_state dpll_hw_state;
10597         int i;
10598
10599         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10600                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10601                 int enabled_crtcs = 0, active_crtcs = 0;
10602                 bool active;
10603
10604                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10605
10606                 DRM_DEBUG_KMS("%s\n", pll->name);
10607
10608                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10609
10610                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10611                      "more active pll users than references: %i vs %i\n",
10612                      pll->active, hweight32(pll->config.crtc_mask));
10613                 WARN(pll->active && !pll->on,
10614                      "pll in active use but not on in sw tracking\n");
10615                 WARN(pll->on && !pll->active,
10616                      "pll in on but not on in use in sw tracking\n");
10617                 WARN(pll->on != active,
10618                      "pll on state mismatch (expected %i, found %i)\n",
10619                      pll->on, active);
10620
10621                 for_each_intel_crtc(dev, crtc) {
10622                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10623                                 enabled_crtcs++;
10624                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10625                                 active_crtcs++;
10626                 }
10627                 WARN(pll->active != active_crtcs,
10628                      "pll active crtcs mismatch (expected %i, found %i)\n",
10629                      pll->active, active_crtcs);
10630                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10631                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10632                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10633
10634                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10635                                        sizeof(dpll_hw_state)),
10636                      "pll hw state mismatch\n");
10637         }
10638 }
10639
10640 void
10641 intel_modeset_check_state(struct drm_device *dev)
10642 {
10643         check_connector_state(dev);
10644         check_encoder_state(dev);
10645         check_crtc_state(dev);
10646         check_shared_dpll_state(dev);
10647 }
10648
10649 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10650                                      int dotclock)
10651 {
10652         /*
10653          * FDI already provided one idea for the dotclock.
10654          * Yell if the encoder disagrees.
10655          */
10656         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10657              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10658              pipe_config->adjusted_mode.crtc_clock, dotclock);
10659 }
10660
10661 static void update_scanline_offset(struct intel_crtc *crtc)
10662 {
10663         struct drm_device *dev = crtc->base.dev;
10664
10665         /*
10666          * The scanline counter increments at the leading edge of hsync.
10667          *
10668          * On most platforms it starts counting from vtotal-1 on the
10669          * first active line. That means the scanline counter value is
10670          * always one less than what we would expect. Ie. just after
10671          * start of vblank, which also occurs at start of hsync (on the
10672          * last active line), the scanline counter will read vblank_start-1.
10673          *
10674          * On gen2 the scanline counter starts counting from 1 instead
10675          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10676          * to keep the value positive), instead of adding one.
10677          *
10678          * On HSW+ the behaviour of the scanline counter depends on the output
10679          * type. For DP ports it behaves like most other platforms, but on HDMI
10680          * there's an extra 1 line difference. So we need to add two instead of
10681          * one to the value.
10682          */
10683         if (IS_GEN2(dev)) {
10684                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10685                 int vtotal;
10686
10687                 vtotal = mode->crtc_vtotal;
10688                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10689                         vtotal /= 2;
10690
10691                 crtc->scanline_offset = vtotal - 1;
10692         } else if (HAS_DDI(dev) &&
10693                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10694                 crtc->scanline_offset = 2;
10695         } else
10696                 crtc->scanline_offset = 1;
10697 }
10698
10699 static int __intel_set_mode(struct drm_crtc *crtc,
10700                             struct drm_display_mode *mode,
10701                             int x, int y, struct drm_framebuffer *fb)
10702 {
10703         struct drm_device *dev = crtc->dev;
10704         struct drm_i915_private *dev_priv = dev->dev_private;
10705         struct drm_display_mode *saved_mode;
10706         struct intel_crtc_config *pipe_config = NULL;
10707         struct intel_crtc *intel_crtc;
10708         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10709         int ret = 0;
10710
10711         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10712         if (!saved_mode)
10713                 return -ENOMEM;
10714
10715         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10716                                      &prepare_pipes, &disable_pipes);
10717
10718         *saved_mode = crtc->mode;
10719
10720         /* Hack: Because we don't (yet) support global modeset on multiple
10721          * crtcs, we don't keep track of the new mode for more than one crtc.
10722          * Hence simply check whether any bit is set in modeset_pipes in all the
10723          * pieces of code that are not yet converted to deal with mutliple crtcs
10724          * changing their mode at the same time. */
10725         if (modeset_pipes) {
10726                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10727                 if (IS_ERR(pipe_config)) {
10728                         ret = PTR_ERR(pipe_config);
10729                         pipe_config = NULL;
10730
10731                         goto out;
10732                 }
10733                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10734                                        "[modeset]");
10735                 to_intel_crtc(crtc)->new_config = pipe_config;
10736         }
10737
10738         /*
10739          * See if the config requires any additional preparation, e.g.
10740          * to adjust global state with pipes off.  We need to do this
10741          * here so we can get the modeset_pipe updated config for the new
10742          * mode set on this crtc.  For other crtcs we need to use the
10743          * adjusted_mode bits in the crtc directly.
10744          */
10745         if (IS_VALLEYVIEW(dev)) {
10746                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10747
10748                 /* may have added more to prepare_pipes than we should */
10749                 prepare_pipes &= ~disable_pipes;
10750         }
10751
10752         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10753                 intel_crtc_disable(&intel_crtc->base);
10754
10755         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10756                 if (intel_crtc->base.enabled)
10757                         dev_priv->display.crtc_disable(&intel_crtc->base);
10758         }
10759
10760         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10761          * to set it here already despite that we pass it down the callchain.
10762          */
10763         if (modeset_pipes) {
10764                 crtc->mode = *mode;
10765                 /* mode_set/enable/disable functions rely on a correct pipe
10766                  * config. */
10767                 to_intel_crtc(crtc)->config = *pipe_config;
10768                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10769
10770                 /*
10771                  * Calculate and store various constants which
10772                  * are later needed by vblank and swap-completion
10773                  * timestamping. They are derived from true hwmode.
10774                  */
10775                 drm_calc_timestamping_constants(crtc,
10776                                                 &pipe_config->adjusted_mode);
10777         }
10778
10779         /* Only after disabling all output pipelines that will be changed can we
10780          * update the the output configuration. */
10781         intel_modeset_update_state(dev, prepare_pipes);
10782
10783         if (dev_priv->display.modeset_global_resources)
10784                 dev_priv->display.modeset_global_resources(dev);
10785
10786         /* Set up the DPLL and any encoders state that needs to adjust or depend
10787          * on the DPLL.
10788          */
10789         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10790                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10791                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10792                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10793
10794                 mutex_lock(&dev->struct_mutex);
10795                 ret = intel_pin_and_fence_fb_obj(dev,
10796                                                  obj,
10797                                                  NULL);
10798                 if (ret != 0) {
10799                         DRM_ERROR("pin & fence failed\n");
10800                         mutex_unlock(&dev->struct_mutex);
10801                         goto done;
10802                 }
10803                 if (old_fb)
10804                         intel_unpin_fb_obj(old_obj);
10805                 i915_gem_track_fb(old_obj, obj,
10806                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10807                 mutex_unlock(&dev->struct_mutex);
10808
10809                 crtc->primary->fb = fb;
10810                 crtc->x = x;
10811                 crtc->y = y;
10812
10813                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10814                 if (ret)
10815                         goto done;
10816         }
10817
10818         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10819         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10820                 update_scanline_offset(intel_crtc);
10821
10822                 dev_priv->display.crtc_enable(&intel_crtc->base);
10823         }
10824
10825         /* FIXME: add subpixel order */
10826 done:
10827         if (ret && crtc->enabled)
10828                 crtc->mode = *saved_mode;
10829
10830 out:
10831         kfree(pipe_config);
10832         kfree(saved_mode);
10833         return ret;
10834 }
10835
10836 static int intel_set_mode(struct drm_crtc *crtc,
10837                           struct drm_display_mode *mode,
10838                           int x, int y, struct drm_framebuffer *fb)
10839 {
10840         int ret;
10841
10842         ret = __intel_set_mode(crtc, mode, x, y, fb);
10843
10844         if (ret == 0)
10845                 intel_modeset_check_state(crtc->dev);
10846
10847         return ret;
10848 }
10849
10850 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10851 {
10852         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10853 }
10854
10855 #undef for_each_intel_crtc_masked
10856
10857 static void intel_set_config_free(struct intel_set_config *config)
10858 {
10859         if (!config)
10860                 return;
10861
10862         kfree(config->save_connector_encoders);
10863         kfree(config->save_encoder_crtcs);
10864         kfree(config->save_crtc_enabled);
10865         kfree(config);
10866 }
10867
10868 static int intel_set_config_save_state(struct drm_device *dev,
10869                                        struct intel_set_config *config)
10870 {
10871         struct drm_crtc *crtc;
10872         struct drm_encoder *encoder;
10873         struct drm_connector *connector;
10874         int count;
10875
10876         config->save_crtc_enabled =
10877                 kcalloc(dev->mode_config.num_crtc,
10878                         sizeof(bool), GFP_KERNEL);
10879         if (!config->save_crtc_enabled)
10880                 return -ENOMEM;
10881
10882         config->save_encoder_crtcs =
10883                 kcalloc(dev->mode_config.num_encoder,
10884                         sizeof(struct drm_crtc *), GFP_KERNEL);
10885         if (!config->save_encoder_crtcs)
10886                 return -ENOMEM;
10887
10888         config->save_connector_encoders =
10889                 kcalloc(dev->mode_config.num_connector,
10890                         sizeof(struct drm_encoder *), GFP_KERNEL);
10891         if (!config->save_connector_encoders)
10892                 return -ENOMEM;
10893
10894         /* Copy data. Note that driver private data is not affected.
10895          * Should anything bad happen only the expected state is
10896          * restored, not the drivers personal bookkeeping.
10897          */
10898         count = 0;
10899         for_each_crtc(dev, crtc) {
10900                 config->save_crtc_enabled[count++] = crtc->enabled;
10901         }
10902
10903         count = 0;
10904         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10905                 config->save_encoder_crtcs[count++] = encoder->crtc;
10906         }
10907
10908         count = 0;
10909         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10910                 config->save_connector_encoders[count++] = connector->encoder;
10911         }
10912
10913         return 0;
10914 }
10915
10916 static void intel_set_config_restore_state(struct drm_device *dev,
10917                                            struct intel_set_config *config)
10918 {
10919         struct intel_crtc *crtc;
10920         struct intel_encoder *encoder;
10921         struct intel_connector *connector;
10922         int count;
10923
10924         count = 0;
10925         for_each_intel_crtc(dev, crtc) {
10926                 crtc->new_enabled = config->save_crtc_enabled[count++];
10927
10928                 if (crtc->new_enabled)
10929                         crtc->new_config = &crtc->config;
10930                 else
10931                         crtc->new_config = NULL;
10932         }
10933
10934         count = 0;
10935         for_each_intel_encoder(dev, encoder) {
10936                 encoder->new_crtc =
10937                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10938         }
10939
10940         count = 0;
10941         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10942                 connector->new_encoder =
10943                         to_intel_encoder(config->save_connector_encoders[count++]);
10944         }
10945 }
10946
10947 static bool
10948 is_crtc_connector_off(struct drm_mode_set *set)
10949 {
10950         int i;
10951
10952         if (set->num_connectors == 0)
10953                 return false;
10954
10955         if (WARN_ON(set->connectors == NULL))
10956                 return false;
10957
10958         for (i = 0; i < set->num_connectors; i++)
10959                 if (set->connectors[i]->encoder &&
10960                     set->connectors[i]->encoder->crtc == set->crtc &&
10961                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10962                         return true;
10963
10964         return false;
10965 }
10966
10967 static void
10968 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10969                                       struct intel_set_config *config)
10970 {
10971
10972         /* We should be able to check here if the fb has the same properties
10973          * and then just flip_or_move it */
10974         if (is_crtc_connector_off(set)) {
10975                 config->mode_changed = true;
10976         } else if (set->crtc->primary->fb != set->fb) {
10977                 /*
10978                  * If we have no fb, we can only flip as long as the crtc is
10979                  * active, otherwise we need a full mode set.  The crtc may
10980                  * be active if we've only disabled the primary plane, or
10981                  * in fastboot situations.
10982                  */
10983                 if (set->crtc->primary->fb == NULL) {
10984                         struct intel_crtc *intel_crtc =
10985                                 to_intel_crtc(set->crtc);
10986
10987                         if (intel_crtc->active) {
10988                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10989                                 config->fb_changed = true;
10990                         } else {
10991                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10992                                 config->mode_changed = true;
10993                         }
10994                 } else if (set->fb == NULL) {
10995                         config->mode_changed = true;
10996                 } else if (set->fb->pixel_format !=
10997                            set->crtc->primary->fb->pixel_format) {
10998                         config->mode_changed = true;
10999                 } else {
11000                         config->fb_changed = true;
11001                 }
11002         }
11003
11004         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11005                 config->fb_changed = true;
11006
11007         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11008                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11009                 drm_mode_debug_printmodeline(&set->crtc->mode);
11010                 drm_mode_debug_printmodeline(set->mode);
11011                 config->mode_changed = true;
11012         }
11013
11014         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11015                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11016 }
11017
11018 static int
11019 intel_modeset_stage_output_state(struct drm_device *dev,
11020                                  struct drm_mode_set *set,
11021                                  struct intel_set_config *config)
11022 {
11023         struct intel_connector *connector;
11024         struct intel_encoder *encoder;
11025         struct intel_crtc *crtc;
11026         int ro;
11027
11028         /* The upper layers ensure that we either disable a crtc or have a list
11029          * of connectors. For paranoia, double-check this. */
11030         WARN_ON(!set->fb && (set->num_connectors != 0));
11031         WARN_ON(set->fb && (set->num_connectors == 0));
11032
11033         list_for_each_entry(connector, &dev->mode_config.connector_list,
11034                             base.head) {
11035                 /* Otherwise traverse passed in connector list and get encoders
11036                  * for them. */
11037                 for (ro = 0; ro < set->num_connectors; ro++) {
11038                         if (set->connectors[ro] == &connector->base) {
11039                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11040                                 break;
11041                         }
11042                 }
11043
11044                 /* If we disable the crtc, disable all its connectors. Also, if
11045                  * the connector is on the changing crtc but not on the new
11046                  * connector list, disable it. */
11047                 if ((!set->fb || ro == set->num_connectors) &&
11048                     connector->base.encoder &&
11049                     connector->base.encoder->crtc == set->crtc) {
11050                         connector->new_encoder = NULL;
11051
11052                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11053                                 connector->base.base.id,
11054                                 connector->base.name);
11055                 }
11056
11057
11058                 if (&connector->new_encoder->base != connector->base.encoder) {
11059                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11060                         config->mode_changed = true;
11061                 }
11062         }
11063         /* connector->new_encoder is now updated for all connectors. */
11064
11065         /* Update crtc of enabled connectors. */
11066         list_for_each_entry(connector, &dev->mode_config.connector_list,
11067                             base.head) {
11068                 struct drm_crtc *new_crtc;
11069
11070                 if (!connector->new_encoder)
11071                         continue;
11072
11073                 new_crtc = connector->new_encoder->base.crtc;
11074
11075                 for (ro = 0; ro < set->num_connectors; ro++) {
11076                         if (set->connectors[ro] == &connector->base)
11077                                 new_crtc = set->crtc;
11078                 }
11079
11080                 /* Make sure the new CRTC will work with the encoder */
11081                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11082                                          new_crtc)) {
11083                         return -EINVAL;
11084                 }
11085                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11086
11087                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11088                         connector->base.base.id,
11089                         connector->base.name,
11090                         new_crtc->base.id);
11091         }
11092
11093         /* Check for any encoders that needs to be disabled. */
11094         for_each_intel_encoder(dev, encoder) {
11095                 int num_connectors = 0;
11096                 list_for_each_entry(connector,
11097                                     &dev->mode_config.connector_list,
11098                                     base.head) {
11099                         if (connector->new_encoder == encoder) {
11100                                 WARN_ON(!connector->new_encoder->new_crtc);
11101                                 num_connectors++;
11102                         }
11103                 }
11104
11105                 if (num_connectors == 0)
11106                         encoder->new_crtc = NULL;
11107                 else if (num_connectors > 1)
11108                         return -EINVAL;
11109
11110                 /* Only now check for crtc changes so we don't miss encoders
11111                  * that will be disabled. */
11112                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11113                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11114                         config->mode_changed = true;
11115                 }
11116         }
11117         /* Now we've also updated encoder->new_crtc for all encoders. */
11118         list_for_each_entry(connector, &dev->mode_config.connector_list,
11119                             base.head) {
11120                 if (connector->new_encoder)
11121                         if (connector->new_encoder != connector->encoder)
11122                                 connector->encoder = connector->new_encoder;
11123         }
11124         for_each_intel_crtc(dev, crtc) {
11125                 crtc->new_enabled = false;
11126
11127                 for_each_intel_encoder(dev, encoder) {
11128                         if (encoder->new_crtc == crtc) {
11129                                 crtc->new_enabled = true;
11130                                 break;
11131                         }
11132                 }
11133
11134                 if (crtc->new_enabled != crtc->base.enabled) {
11135                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11136                                       crtc->new_enabled ? "en" : "dis");
11137                         config->mode_changed = true;
11138                 }
11139
11140                 if (crtc->new_enabled)
11141                         crtc->new_config = &crtc->config;
11142                 else
11143                         crtc->new_config = NULL;
11144         }
11145
11146         return 0;
11147 }
11148
11149 static void disable_crtc_nofb(struct intel_crtc *crtc)
11150 {
11151         struct drm_device *dev = crtc->base.dev;
11152         struct intel_encoder *encoder;
11153         struct intel_connector *connector;
11154
11155         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11156                       pipe_name(crtc->pipe));
11157
11158         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11159                 if (connector->new_encoder &&
11160                     connector->new_encoder->new_crtc == crtc)
11161                         connector->new_encoder = NULL;
11162         }
11163
11164         for_each_intel_encoder(dev, encoder) {
11165                 if (encoder->new_crtc == crtc)
11166                         encoder->new_crtc = NULL;
11167         }
11168
11169         crtc->new_enabled = false;
11170         crtc->new_config = NULL;
11171 }
11172
11173 static int intel_crtc_set_config(struct drm_mode_set *set)
11174 {
11175         struct drm_device *dev;
11176         struct drm_mode_set save_set;
11177         struct intel_set_config *config;
11178         int ret;
11179
11180         BUG_ON(!set);
11181         BUG_ON(!set->crtc);
11182         BUG_ON(!set->crtc->helper_private);
11183
11184         /* Enforce sane interface api - has been abused by the fb helper. */
11185         BUG_ON(!set->mode && set->fb);
11186         BUG_ON(set->fb && set->num_connectors == 0);
11187
11188         if (set->fb) {
11189                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11190                                 set->crtc->base.id, set->fb->base.id,
11191                                 (int)set->num_connectors, set->x, set->y);
11192         } else {
11193                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11194         }
11195
11196         dev = set->crtc->dev;
11197
11198         ret = -ENOMEM;
11199         config = kzalloc(sizeof(*config), GFP_KERNEL);
11200         if (!config)
11201                 goto out_config;
11202
11203         ret = intel_set_config_save_state(dev, config);
11204         if (ret)
11205                 goto out_config;
11206
11207         save_set.crtc = set->crtc;
11208         save_set.mode = &set->crtc->mode;
11209         save_set.x = set->crtc->x;
11210         save_set.y = set->crtc->y;
11211         save_set.fb = set->crtc->primary->fb;
11212
11213         /* Compute whether we need a full modeset, only an fb base update or no
11214          * change at all. In the future we might also check whether only the
11215          * mode changed, e.g. for LVDS where we only change the panel fitter in
11216          * such cases. */
11217         intel_set_config_compute_mode_changes(set, config);
11218
11219         ret = intel_modeset_stage_output_state(dev, set, config);
11220         if (ret)
11221                 goto fail;
11222
11223         if (config->mode_changed) {
11224                 ret = intel_set_mode(set->crtc, set->mode,
11225                                      set->x, set->y, set->fb);
11226         } else if (config->fb_changed) {
11227                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11228
11229                 intel_crtc_wait_for_pending_flips(set->crtc);
11230
11231                 ret = intel_pipe_set_base(set->crtc,
11232                                           set->x, set->y, set->fb);
11233
11234                 /*
11235                  * We need to make sure the primary plane is re-enabled if it
11236                  * has previously been turned off.
11237                  */
11238                 if (!intel_crtc->primary_enabled && ret == 0) {
11239                         WARN_ON(!intel_crtc->active);
11240                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11241                 }
11242
11243                 /*
11244                  * In the fastboot case this may be our only check of the
11245                  * state after boot.  It would be better to only do it on
11246                  * the first update, but we don't have a nice way of doing that
11247                  * (and really, set_config isn't used much for high freq page
11248                  * flipping, so increasing its cost here shouldn't be a big
11249                  * deal).
11250                  */
11251                 if (i915.fastboot && ret == 0)
11252                         intel_modeset_check_state(set->crtc->dev);
11253         }
11254
11255         if (ret) {
11256                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11257                               set->crtc->base.id, ret);
11258 fail:
11259                 intel_set_config_restore_state(dev, config);
11260
11261                 /*
11262                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11263                  * force the pipe off to avoid oopsing in the modeset code
11264                  * due to fb==NULL. This should only happen during boot since
11265                  * we don't yet reconstruct the FB from the hardware state.
11266                  */
11267                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11268                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11269
11270                 /* Try to restore the config */
11271                 if (config->mode_changed &&
11272                     intel_set_mode(save_set.crtc, save_set.mode,
11273                                    save_set.x, save_set.y, save_set.fb))
11274                         DRM_ERROR("failed to restore config after modeset failure\n");
11275         }
11276
11277 out_config:
11278         intel_set_config_free(config);
11279         return ret;
11280 }
11281
11282 static const struct drm_crtc_funcs intel_crtc_funcs = {
11283         .gamma_set = intel_crtc_gamma_set,
11284         .set_config = intel_crtc_set_config,
11285         .destroy = intel_crtc_destroy,
11286         .page_flip = intel_crtc_page_flip,
11287 };
11288
11289 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11290                                       struct intel_shared_dpll *pll,
11291                                       struct intel_dpll_hw_state *hw_state)
11292 {
11293         uint32_t val;
11294
11295         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11296                 return false;
11297
11298         val = I915_READ(PCH_DPLL(pll->id));
11299         hw_state->dpll = val;
11300         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11301         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11302
11303         return val & DPLL_VCO_ENABLE;
11304 }
11305
11306 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11307                                   struct intel_shared_dpll *pll)
11308 {
11309         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11310         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11311 }
11312
11313 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11314                                 struct intel_shared_dpll *pll)
11315 {
11316         /* PCH refclock must be enabled first */
11317         ibx_assert_pch_refclk_enabled(dev_priv);
11318
11319         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11320
11321         /* Wait for the clocks to stabilize. */
11322         POSTING_READ(PCH_DPLL(pll->id));
11323         udelay(150);
11324
11325         /* The pixel multiplier can only be updated once the
11326          * DPLL is enabled and the clocks are stable.
11327          *
11328          * So write it again.
11329          */
11330         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11331         POSTING_READ(PCH_DPLL(pll->id));
11332         udelay(200);
11333 }
11334
11335 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11336                                  struct intel_shared_dpll *pll)
11337 {
11338         struct drm_device *dev = dev_priv->dev;
11339         struct intel_crtc *crtc;
11340
11341         /* Make sure no transcoder isn't still depending on us. */
11342         for_each_intel_crtc(dev, crtc) {
11343                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11344                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11345         }
11346
11347         I915_WRITE(PCH_DPLL(pll->id), 0);
11348         POSTING_READ(PCH_DPLL(pll->id));
11349         udelay(200);
11350 }
11351
11352 static char *ibx_pch_dpll_names[] = {
11353         "PCH DPLL A",
11354         "PCH DPLL B",
11355 };
11356
11357 static void ibx_pch_dpll_init(struct drm_device *dev)
11358 {
11359         struct drm_i915_private *dev_priv = dev->dev_private;
11360         int i;
11361
11362         dev_priv->num_shared_dpll = 2;
11363
11364         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11365                 dev_priv->shared_dplls[i].id = i;
11366                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11367                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11368                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11369                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11370                 dev_priv->shared_dplls[i].get_hw_state =
11371                         ibx_pch_dpll_get_hw_state;
11372         }
11373 }
11374
11375 static void intel_shared_dpll_init(struct drm_device *dev)
11376 {
11377         struct drm_i915_private *dev_priv = dev->dev_private;
11378
11379         if (HAS_DDI(dev))
11380                 intel_ddi_pll_init(dev);
11381         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11382                 ibx_pch_dpll_init(dev);
11383         else
11384                 dev_priv->num_shared_dpll = 0;
11385
11386         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11387 }
11388
11389 static int
11390 intel_primary_plane_disable(struct drm_plane *plane)
11391 {
11392         struct drm_device *dev = plane->dev;
11393         struct intel_crtc *intel_crtc;
11394
11395         if (!plane->fb)
11396                 return 0;
11397
11398         BUG_ON(!plane->crtc);
11399
11400         intel_crtc = to_intel_crtc(plane->crtc);
11401
11402         /*
11403          * Even though we checked plane->fb above, it's still possible that
11404          * the primary plane has been implicitly disabled because the crtc
11405          * coordinates given weren't visible, or because we detected
11406          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11407          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11408          * In either case, we need to unpin the FB and let the fb pointer get
11409          * updated, but otherwise we don't need to touch the hardware.
11410          */
11411         if (!intel_crtc->primary_enabled)
11412                 goto disable_unpin;
11413
11414         intel_crtc_wait_for_pending_flips(plane->crtc);
11415         intel_disable_primary_hw_plane(plane, plane->crtc);
11416
11417 disable_unpin:
11418         mutex_lock(&dev->struct_mutex);
11419         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11420                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11421         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11422         mutex_unlock(&dev->struct_mutex);
11423         plane->fb = NULL;
11424
11425         return 0;
11426 }
11427
11428 static int
11429 intel_check_primary_plane(struct drm_plane *plane,
11430                           struct intel_plane_state *state)
11431 {
11432         struct drm_crtc *crtc = state->crtc;
11433         struct drm_framebuffer *fb = state->fb;
11434         struct drm_rect *dest = &state->dst;
11435         struct drm_rect *src = &state->src;
11436         const struct drm_rect *clip = &state->clip;
11437
11438         return drm_plane_helper_check_update(plane, crtc, fb,
11439                                              src, dest, clip,
11440                                              DRM_PLANE_HELPER_NO_SCALING,
11441                                              DRM_PLANE_HELPER_NO_SCALING,
11442                                              false, true, &state->visible);
11443 }
11444
11445 static int
11446 intel_prepare_primary_plane(struct drm_plane *plane,
11447                             struct intel_plane_state *state)
11448 {
11449         struct drm_crtc *crtc = state->crtc;
11450         struct drm_framebuffer *fb = state->fb;
11451         struct drm_device *dev = crtc->dev;
11452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11453         enum pipe pipe = intel_crtc->pipe;
11454         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11455         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11456         int ret;
11457
11458         intel_crtc_wait_for_pending_flips(crtc);
11459
11460         if (intel_crtc_has_pending_flip(crtc)) {
11461                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11462                 return -EBUSY;
11463         }
11464
11465         if (old_obj != obj) {
11466                 mutex_lock(&dev->struct_mutex);
11467                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11468                 if (ret == 0)
11469                         i915_gem_track_fb(old_obj, obj,
11470                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11471                 mutex_unlock(&dev->struct_mutex);
11472                 if (ret != 0) {
11473                         DRM_DEBUG_KMS("pin & fence failed\n");
11474                         return ret;
11475                 }
11476         }
11477
11478         return 0;
11479 }
11480
11481 static void
11482 intel_commit_primary_plane(struct drm_plane *plane,
11483                            struct intel_plane_state *state)
11484 {
11485         struct drm_crtc *crtc = state->crtc;
11486         struct drm_framebuffer *fb = state->fb;
11487         struct drm_device *dev = crtc->dev;
11488         struct drm_i915_private *dev_priv = dev->dev_private;
11489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11490         enum pipe pipe = intel_crtc->pipe;
11491         struct drm_framebuffer *old_fb = plane->fb;
11492         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11493         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11494         struct intel_plane *intel_plane = to_intel_plane(plane);
11495         struct drm_rect *src = &state->src;
11496
11497         crtc->primary->fb = fb;
11498         crtc->x = src->x1;
11499         crtc->y = src->y1;
11500
11501         intel_plane->crtc_x = state->orig_dst.x1;
11502         intel_plane->crtc_y = state->orig_dst.y1;
11503         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11504         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11505         intel_plane->src_x = state->orig_src.x1;
11506         intel_plane->src_y = state->orig_src.y1;
11507         intel_plane->src_w = drm_rect_width(&state->orig_src);
11508         intel_plane->src_h = drm_rect_height(&state->orig_src);
11509         intel_plane->obj = obj;
11510
11511         if (intel_crtc->active) {
11512                 /*
11513                  * FBC does not work on some platforms for rotated
11514                  * planes, so disable it when rotation is not 0 and
11515                  * update it when rotation is set back to 0.
11516                  *
11517                  * FIXME: This is redundant with the fbc update done in
11518                  * the primary plane enable function except that that
11519                  * one is done too late. We eventually need to unify
11520                  * this.
11521                  */
11522                 if (intel_crtc->primary_enabled &&
11523                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11524                     dev_priv->fbc.plane == intel_crtc->plane &&
11525                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11526                         intel_disable_fbc(dev);
11527                 }
11528
11529                 if (state->visible) {
11530                         bool was_enabled = intel_crtc->primary_enabled;
11531
11532                         /* FIXME: kill this fastboot hack */
11533                         intel_update_pipe_size(intel_crtc);
11534
11535                         intel_crtc->primary_enabled = true;
11536
11537                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11538                                         crtc->x, crtc->y);
11539
11540                         /*
11541                          * BDW signals flip done immediately if the plane
11542                          * is disabled, even if the plane enable is already
11543                          * armed to occur at the next vblank :(
11544                          */
11545                         if (IS_BROADWELL(dev) && !was_enabled)
11546                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11547                 } else {
11548                         /*
11549                          * If clipping results in a non-visible primary plane,
11550                          * we'll disable the primary plane.  Note that this is
11551                          * a bit different than what happens if userspace
11552                          * explicitly disables the plane by passing fb=0
11553                          * because plane->fb still gets set and pinned.
11554                          */
11555                         intel_disable_primary_hw_plane(plane, crtc);
11556                 }
11557
11558                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11559
11560                 mutex_lock(&dev->struct_mutex);
11561                 intel_update_fbc(dev);
11562                 mutex_unlock(&dev->struct_mutex);
11563         }
11564
11565         if (old_fb && old_fb != fb) {
11566                 if (intel_crtc->active)
11567                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11568
11569                 mutex_lock(&dev->struct_mutex);
11570                 intel_unpin_fb_obj(old_obj);
11571                 mutex_unlock(&dev->struct_mutex);
11572         }
11573 }
11574
11575 static int
11576 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11577                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11578                              unsigned int crtc_w, unsigned int crtc_h,
11579                              uint32_t src_x, uint32_t src_y,
11580                              uint32_t src_w, uint32_t src_h)
11581 {
11582         struct intel_plane_state state;
11583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11584         int ret;
11585
11586         state.crtc = crtc;
11587         state.fb = fb;
11588
11589         /* sample coordinates in 16.16 fixed point */
11590         state.src.x1 = src_x;
11591         state.src.x2 = src_x + src_w;
11592         state.src.y1 = src_y;
11593         state.src.y2 = src_y + src_h;
11594
11595         /* integer pixels */
11596         state.dst.x1 = crtc_x;
11597         state.dst.x2 = crtc_x + crtc_w;
11598         state.dst.y1 = crtc_y;
11599         state.dst.y2 = crtc_y + crtc_h;
11600
11601         state.clip.x1 = 0;
11602         state.clip.y1 = 0;
11603         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11604         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11605
11606         state.orig_src = state.src;
11607         state.orig_dst = state.dst;
11608
11609         ret = intel_check_primary_plane(plane, &state);
11610         if (ret)
11611                 return ret;
11612
11613         ret = intel_prepare_primary_plane(plane, &state);
11614         if (ret)
11615                 return ret;
11616
11617         intel_commit_primary_plane(plane, &state);
11618
11619         return 0;
11620 }
11621
11622 /* Common destruction function for both primary and cursor planes */
11623 static void intel_plane_destroy(struct drm_plane *plane)
11624 {
11625         struct intel_plane *intel_plane = to_intel_plane(plane);
11626         drm_plane_cleanup(plane);
11627         kfree(intel_plane);
11628 }
11629
11630 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11631         .update_plane = intel_primary_plane_setplane,
11632         .disable_plane = intel_primary_plane_disable,
11633         .destroy = intel_plane_destroy,
11634         .set_property = intel_plane_set_property
11635 };
11636
11637 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11638                                                     int pipe)
11639 {
11640         struct intel_plane *primary;
11641         const uint32_t *intel_primary_formats;
11642         int num_formats;
11643
11644         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11645         if (primary == NULL)
11646                 return NULL;
11647
11648         primary->can_scale = false;
11649         primary->max_downscale = 1;
11650         primary->pipe = pipe;
11651         primary->plane = pipe;
11652         primary->rotation = BIT(DRM_ROTATE_0);
11653         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11654                 primary->plane = !pipe;
11655
11656         if (INTEL_INFO(dev)->gen <= 3) {
11657                 intel_primary_formats = intel_primary_formats_gen2;
11658                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11659         } else {
11660                 intel_primary_formats = intel_primary_formats_gen4;
11661                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11662         }
11663
11664         drm_universal_plane_init(dev, &primary->base, 0,
11665                                  &intel_primary_plane_funcs,
11666                                  intel_primary_formats, num_formats,
11667                                  DRM_PLANE_TYPE_PRIMARY);
11668
11669         if (INTEL_INFO(dev)->gen >= 4) {
11670                 if (!dev->mode_config.rotation_property)
11671                         dev->mode_config.rotation_property =
11672                                 drm_mode_create_rotation_property(dev,
11673                                                         BIT(DRM_ROTATE_0) |
11674                                                         BIT(DRM_ROTATE_180));
11675                 if (dev->mode_config.rotation_property)
11676                         drm_object_attach_property(&primary->base.base,
11677                                 dev->mode_config.rotation_property,
11678                                 primary->rotation);
11679         }
11680
11681         return &primary->base;
11682 }
11683
11684 static int
11685 intel_cursor_plane_disable(struct drm_plane *plane)
11686 {
11687         if (!plane->fb)
11688                 return 0;
11689
11690         BUG_ON(!plane->crtc);
11691
11692         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11693 }
11694
11695 static int
11696 intel_check_cursor_plane(struct drm_plane *plane,
11697                          struct intel_plane_state *state)
11698 {
11699         struct drm_crtc *crtc = state->crtc;
11700         struct drm_device *dev = crtc->dev;
11701         struct drm_framebuffer *fb = state->fb;
11702         struct drm_rect *dest = &state->dst;
11703         struct drm_rect *src = &state->src;
11704         const struct drm_rect *clip = &state->clip;
11705         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11706         int crtc_w, crtc_h;
11707         unsigned stride;
11708         int ret;
11709
11710         ret = drm_plane_helper_check_update(plane, crtc, fb,
11711                                             src, dest, clip,
11712                                             DRM_PLANE_HELPER_NO_SCALING,
11713                                             DRM_PLANE_HELPER_NO_SCALING,
11714                                             true, true, &state->visible);
11715         if (ret)
11716                 return ret;
11717
11718
11719         /* if we want to turn off the cursor ignore width and height */
11720         if (!obj)
11721                 return 0;
11722
11723         /* Check for which cursor types we support */
11724         crtc_w = drm_rect_width(&state->orig_dst);
11725         crtc_h = drm_rect_height(&state->orig_dst);
11726         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11727                 DRM_DEBUG("Cursor dimension not supported\n");
11728                 return -EINVAL;
11729         }
11730
11731         stride = roundup_pow_of_two(crtc_w) * 4;
11732         if (obj->base.size < stride * crtc_h) {
11733                 DRM_DEBUG_KMS("buffer is too small\n");
11734                 return -ENOMEM;
11735         }
11736
11737         if (fb == crtc->cursor->fb)
11738                 return 0;
11739
11740         /* we only need to pin inside GTT if cursor is non-phy */
11741         mutex_lock(&dev->struct_mutex);
11742         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11743                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11744                 ret = -EINVAL;
11745         }
11746         mutex_unlock(&dev->struct_mutex);
11747
11748         return ret;
11749 }
11750
11751 static int
11752 intel_commit_cursor_plane(struct drm_plane *plane,
11753                           struct intel_plane_state *state)
11754 {
11755         struct drm_crtc *crtc = state->crtc;
11756         struct drm_framebuffer *fb = state->fb;
11757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11758         struct intel_plane *intel_plane = to_intel_plane(plane);
11759         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11760         struct drm_i915_gem_object *obj = intel_fb->obj;
11761         int crtc_w, crtc_h;
11762
11763         crtc->cursor_x = state->orig_dst.x1;
11764         crtc->cursor_y = state->orig_dst.y1;
11765
11766         intel_plane->crtc_x = state->orig_dst.x1;
11767         intel_plane->crtc_y = state->orig_dst.y1;
11768         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11769         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11770         intel_plane->src_x = state->orig_src.x1;
11771         intel_plane->src_y = state->orig_src.y1;
11772         intel_plane->src_w = drm_rect_width(&state->orig_src);
11773         intel_plane->src_h = drm_rect_height(&state->orig_src);
11774         intel_plane->obj = obj;
11775
11776         if (fb != crtc->cursor->fb) {
11777                 crtc_w = drm_rect_width(&state->orig_dst);
11778                 crtc_h = drm_rect_height(&state->orig_dst);
11779                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11780         } else {
11781                 intel_crtc_update_cursor(crtc, state->visible);
11782
11783                 intel_frontbuffer_flip(crtc->dev,
11784                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11785
11786                 return 0;
11787         }
11788 }
11789
11790 static int
11791 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11792                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11793                           unsigned int crtc_w, unsigned int crtc_h,
11794                           uint32_t src_x, uint32_t src_y,
11795                           uint32_t src_w, uint32_t src_h)
11796 {
11797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11798         struct intel_plane_state state;
11799         int ret;
11800
11801         state.crtc = crtc;
11802         state.fb = fb;
11803
11804         /* sample coordinates in 16.16 fixed point */
11805         state.src.x1 = src_x;
11806         state.src.x2 = src_x + src_w;
11807         state.src.y1 = src_y;
11808         state.src.y2 = src_y + src_h;
11809
11810         /* integer pixels */
11811         state.dst.x1 = crtc_x;
11812         state.dst.x2 = crtc_x + crtc_w;
11813         state.dst.y1 = crtc_y;
11814         state.dst.y2 = crtc_y + crtc_h;
11815
11816         state.clip.x1 = 0;
11817         state.clip.y1 = 0;
11818         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11819         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11820
11821         state.orig_src = state.src;
11822         state.orig_dst = state.dst;
11823
11824         ret = intel_check_cursor_plane(plane, &state);
11825         if (ret)
11826                 return ret;
11827
11828         return intel_commit_cursor_plane(plane, &state);
11829 }
11830
11831 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11832         .update_plane = intel_cursor_plane_update,
11833         .disable_plane = intel_cursor_plane_disable,
11834         .destroy = intel_plane_destroy,
11835         .set_property = intel_plane_set_property,
11836 };
11837
11838 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11839                                                    int pipe)
11840 {
11841         struct intel_plane *cursor;
11842
11843         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11844         if (cursor == NULL)
11845                 return NULL;
11846
11847         cursor->can_scale = false;
11848         cursor->max_downscale = 1;
11849         cursor->pipe = pipe;
11850         cursor->plane = pipe;
11851         cursor->rotation = BIT(DRM_ROTATE_0);
11852
11853         drm_universal_plane_init(dev, &cursor->base, 0,
11854                                  &intel_cursor_plane_funcs,
11855                                  intel_cursor_formats,
11856                                  ARRAY_SIZE(intel_cursor_formats),
11857                                  DRM_PLANE_TYPE_CURSOR);
11858
11859         if (INTEL_INFO(dev)->gen >= 4) {
11860                 if (!dev->mode_config.rotation_property)
11861                         dev->mode_config.rotation_property =
11862                                 drm_mode_create_rotation_property(dev,
11863                                                         BIT(DRM_ROTATE_0) |
11864                                                         BIT(DRM_ROTATE_180));
11865                 if (dev->mode_config.rotation_property)
11866                         drm_object_attach_property(&cursor->base.base,
11867                                 dev->mode_config.rotation_property,
11868                                 cursor->rotation);
11869         }
11870
11871         return &cursor->base;
11872 }
11873
11874 static void intel_crtc_init(struct drm_device *dev, int pipe)
11875 {
11876         struct drm_i915_private *dev_priv = dev->dev_private;
11877         struct intel_crtc *intel_crtc;
11878         struct drm_plane *primary = NULL;
11879         struct drm_plane *cursor = NULL;
11880         int i, ret;
11881
11882         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11883         if (intel_crtc == NULL)
11884                 return;
11885
11886         primary = intel_primary_plane_create(dev, pipe);
11887         if (!primary)
11888                 goto fail;
11889
11890         cursor = intel_cursor_plane_create(dev, pipe);
11891         if (!cursor)
11892                 goto fail;
11893
11894         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11895                                         cursor, &intel_crtc_funcs);
11896         if (ret)
11897                 goto fail;
11898
11899         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11900         for (i = 0; i < 256; i++) {
11901                 intel_crtc->lut_r[i] = i;
11902                 intel_crtc->lut_g[i] = i;
11903                 intel_crtc->lut_b[i] = i;
11904         }
11905
11906         /*
11907          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11908          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11909          */
11910         intel_crtc->pipe = pipe;
11911         intel_crtc->plane = pipe;
11912         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11913                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11914                 intel_crtc->plane = !pipe;
11915         }
11916
11917         intel_crtc->cursor_base = ~0;
11918         intel_crtc->cursor_cntl = ~0;
11919         intel_crtc->cursor_size = ~0;
11920
11921         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11922                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11923         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11924         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11925
11926         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11927
11928         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11929         return;
11930
11931 fail:
11932         if (primary)
11933                 drm_plane_cleanup(primary);
11934         if (cursor)
11935                 drm_plane_cleanup(cursor);
11936         kfree(intel_crtc);
11937 }
11938
11939 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11940 {
11941         struct drm_encoder *encoder = connector->base.encoder;
11942         struct drm_device *dev = connector->base.dev;
11943
11944         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11945
11946         if (!encoder)
11947                 return INVALID_PIPE;
11948
11949         return to_intel_crtc(encoder->crtc)->pipe;
11950 }
11951
11952 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11953                                 struct drm_file *file)
11954 {
11955         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11956         struct drm_crtc *drmmode_crtc;
11957         struct intel_crtc *crtc;
11958
11959         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11960                 return -ENODEV;
11961
11962         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11963
11964         if (!drmmode_crtc) {
11965                 DRM_ERROR("no such CRTC id\n");
11966                 return -ENOENT;
11967         }
11968
11969         crtc = to_intel_crtc(drmmode_crtc);
11970         pipe_from_crtc_id->pipe = crtc->pipe;
11971
11972         return 0;
11973 }
11974
11975 static int intel_encoder_clones(struct intel_encoder *encoder)
11976 {
11977         struct drm_device *dev = encoder->base.dev;
11978         struct intel_encoder *source_encoder;
11979         int index_mask = 0;
11980         int entry = 0;
11981
11982         for_each_intel_encoder(dev, source_encoder) {
11983                 if (encoders_cloneable(encoder, source_encoder))
11984                         index_mask |= (1 << entry);
11985
11986                 entry++;
11987         }
11988
11989         return index_mask;
11990 }
11991
11992 static bool has_edp_a(struct drm_device *dev)
11993 {
11994         struct drm_i915_private *dev_priv = dev->dev_private;
11995
11996         if (!IS_MOBILE(dev))
11997                 return false;
11998
11999         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12000                 return false;
12001
12002         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12003                 return false;
12004
12005         return true;
12006 }
12007
12008 const char *intel_output_name(int output)
12009 {
12010         static const char *names[] = {
12011                 [INTEL_OUTPUT_UNUSED] = "Unused",
12012                 [INTEL_OUTPUT_ANALOG] = "Analog",
12013                 [INTEL_OUTPUT_DVO] = "DVO",
12014                 [INTEL_OUTPUT_SDVO] = "SDVO",
12015                 [INTEL_OUTPUT_LVDS] = "LVDS",
12016                 [INTEL_OUTPUT_TVOUT] = "TV",
12017                 [INTEL_OUTPUT_HDMI] = "HDMI",
12018                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12019                 [INTEL_OUTPUT_EDP] = "eDP",
12020                 [INTEL_OUTPUT_DSI] = "DSI",
12021                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12022         };
12023
12024         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12025                 return "Invalid";
12026
12027         return names[output];
12028 }
12029
12030 static bool intel_crt_present(struct drm_device *dev)
12031 {
12032         struct drm_i915_private *dev_priv = dev->dev_private;
12033
12034         if (INTEL_INFO(dev)->gen >= 9)
12035                 return false;
12036
12037         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12038                 return false;
12039
12040         if (IS_CHERRYVIEW(dev))
12041                 return false;
12042
12043         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12044                 return false;
12045
12046         return true;
12047 }
12048
12049 static void intel_setup_outputs(struct drm_device *dev)
12050 {
12051         struct drm_i915_private *dev_priv = dev->dev_private;
12052         struct intel_encoder *encoder;
12053         bool dpd_is_edp = false;
12054
12055         intel_lvds_init(dev);
12056
12057         if (intel_crt_present(dev))
12058                 intel_crt_init(dev);
12059
12060         if (HAS_DDI(dev)) {
12061                 int found;
12062
12063                 /* Haswell uses DDI functions to detect digital outputs */
12064                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12065                 /* DDI A only supports eDP */
12066                 if (found)
12067                         intel_ddi_init(dev, PORT_A);
12068
12069                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12070                  * register */
12071                 found = I915_READ(SFUSE_STRAP);
12072
12073                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12074                         intel_ddi_init(dev, PORT_B);
12075                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12076                         intel_ddi_init(dev, PORT_C);
12077                 if (found & SFUSE_STRAP_DDID_DETECTED)
12078                         intel_ddi_init(dev, PORT_D);
12079         } else if (HAS_PCH_SPLIT(dev)) {
12080                 int found;
12081                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12082
12083                 if (has_edp_a(dev))
12084                         intel_dp_init(dev, DP_A, PORT_A);
12085
12086                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12087                         /* PCH SDVOB multiplex with HDMIB */
12088                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12089                         if (!found)
12090                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12091                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12092                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12093                 }
12094
12095                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12096                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12097
12098                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12099                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12100
12101                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12102                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12103
12104                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12105                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12106         } else if (IS_VALLEYVIEW(dev)) {
12107                 /*
12108                  * The DP_DETECTED bit is the latched state of the DDC
12109                  * SDA pin at boot. However since eDP doesn't require DDC
12110                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12111                  * eDP ports may have been muxed to an alternate function.
12112                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12113                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12114                  * detect eDP ports.
12115                  */
12116                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12117                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12118                                         PORT_B);
12119                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12120                     intel_dp_is_edp(dev, PORT_B))
12121                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12122
12123                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12124                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12125                                         PORT_C);
12126                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12127                     intel_dp_is_edp(dev, PORT_C))
12128                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12129
12130                 if (IS_CHERRYVIEW(dev)) {
12131                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12132                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12133                                                 PORT_D);
12134                         /* eDP not supported on port D, so don't check VBT */
12135                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12136                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12137                 }
12138
12139                 intel_dsi_init(dev);
12140         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12141                 bool found = false;
12142
12143                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12144                         DRM_DEBUG_KMS("probing SDVOB\n");
12145                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12146                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12147                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12148                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12149                         }
12150
12151                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12152                                 intel_dp_init(dev, DP_B, PORT_B);
12153                 }
12154
12155                 /* Before G4X SDVOC doesn't have its own detect register */
12156
12157                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12158                         DRM_DEBUG_KMS("probing SDVOC\n");
12159                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12160                 }
12161
12162                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12163
12164                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12165                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12166                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12167                         }
12168                         if (SUPPORTS_INTEGRATED_DP(dev))
12169                                 intel_dp_init(dev, DP_C, PORT_C);
12170                 }
12171
12172                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12173                     (I915_READ(DP_D) & DP_DETECTED))
12174                         intel_dp_init(dev, DP_D, PORT_D);
12175         } else if (IS_GEN2(dev))
12176                 intel_dvo_init(dev);
12177
12178         if (SUPPORTS_TV(dev))
12179                 intel_tv_init(dev);
12180
12181         intel_edp_psr_init(dev);
12182
12183         for_each_intel_encoder(dev, encoder) {
12184                 encoder->base.possible_crtcs = encoder->crtc_mask;
12185                 encoder->base.possible_clones =
12186                         intel_encoder_clones(encoder);
12187         }
12188
12189         intel_init_pch_refclk(dev);
12190
12191         drm_helper_move_panel_connectors_to_head(dev);
12192 }
12193
12194 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12195 {
12196         struct drm_device *dev = fb->dev;
12197         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12198
12199         drm_framebuffer_cleanup(fb);
12200         mutex_lock(&dev->struct_mutex);
12201         WARN_ON(!intel_fb->obj->framebuffer_references--);
12202         drm_gem_object_unreference(&intel_fb->obj->base);
12203         mutex_unlock(&dev->struct_mutex);
12204         kfree(intel_fb);
12205 }
12206
12207 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12208                                                 struct drm_file *file,
12209                                                 unsigned int *handle)
12210 {
12211         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12212         struct drm_i915_gem_object *obj = intel_fb->obj;
12213
12214         return drm_gem_handle_create(file, &obj->base, handle);
12215 }
12216
12217 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12218         .destroy = intel_user_framebuffer_destroy,
12219         .create_handle = intel_user_framebuffer_create_handle,
12220 };
12221
12222 static int intel_framebuffer_init(struct drm_device *dev,
12223                                   struct intel_framebuffer *intel_fb,
12224                                   struct drm_mode_fb_cmd2 *mode_cmd,
12225                                   struct drm_i915_gem_object *obj)
12226 {
12227         int aligned_height;
12228         int pitch_limit;
12229         int ret;
12230
12231         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12232
12233         if (obj->tiling_mode == I915_TILING_Y) {
12234                 DRM_DEBUG("hardware does not support tiling Y\n");
12235                 return -EINVAL;
12236         }
12237
12238         if (mode_cmd->pitches[0] & 63) {
12239                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12240                           mode_cmd->pitches[0]);
12241                 return -EINVAL;
12242         }
12243
12244         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12245                 pitch_limit = 32*1024;
12246         } else if (INTEL_INFO(dev)->gen >= 4) {
12247                 if (obj->tiling_mode)
12248                         pitch_limit = 16*1024;
12249                 else
12250                         pitch_limit = 32*1024;
12251         } else if (INTEL_INFO(dev)->gen >= 3) {
12252                 if (obj->tiling_mode)
12253                         pitch_limit = 8*1024;
12254                 else
12255                         pitch_limit = 16*1024;
12256         } else
12257                 /* XXX DSPC is limited to 4k tiled */
12258                 pitch_limit = 8*1024;
12259
12260         if (mode_cmd->pitches[0] > pitch_limit) {
12261                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12262                           obj->tiling_mode ? "tiled" : "linear",
12263                           mode_cmd->pitches[0], pitch_limit);
12264                 return -EINVAL;
12265         }
12266
12267         if (obj->tiling_mode != I915_TILING_NONE &&
12268             mode_cmd->pitches[0] != obj->stride) {
12269                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12270                           mode_cmd->pitches[0], obj->stride);
12271                 return -EINVAL;
12272         }
12273
12274         /* Reject formats not supported by any plane early. */
12275         switch (mode_cmd->pixel_format) {
12276         case DRM_FORMAT_C8:
12277         case DRM_FORMAT_RGB565:
12278         case DRM_FORMAT_XRGB8888:
12279         case DRM_FORMAT_ARGB8888:
12280                 break;
12281         case DRM_FORMAT_XRGB1555:
12282         case DRM_FORMAT_ARGB1555:
12283                 if (INTEL_INFO(dev)->gen > 3) {
12284                         DRM_DEBUG("unsupported pixel format: %s\n",
12285                                   drm_get_format_name(mode_cmd->pixel_format));
12286                         return -EINVAL;
12287                 }
12288                 break;
12289         case DRM_FORMAT_XBGR8888:
12290         case DRM_FORMAT_ABGR8888:
12291         case DRM_FORMAT_XRGB2101010:
12292         case DRM_FORMAT_ARGB2101010:
12293         case DRM_FORMAT_XBGR2101010:
12294         case DRM_FORMAT_ABGR2101010:
12295                 if (INTEL_INFO(dev)->gen < 4) {
12296                         DRM_DEBUG("unsupported pixel format: %s\n",
12297                                   drm_get_format_name(mode_cmd->pixel_format));
12298                         return -EINVAL;
12299                 }
12300                 break;
12301         case DRM_FORMAT_YUYV:
12302         case DRM_FORMAT_UYVY:
12303         case DRM_FORMAT_YVYU:
12304         case DRM_FORMAT_VYUY:
12305                 if (INTEL_INFO(dev)->gen < 5) {
12306                         DRM_DEBUG("unsupported pixel format: %s\n",
12307                                   drm_get_format_name(mode_cmd->pixel_format));
12308                         return -EINVAL;
12309                 }
12310                 break;
12311         default:
12312                 DRM_DEBUG("unsupported pixel format: %s\n",
12313                           drm_get_format_name(mode_cmd->pixel_format));
12314                 return -EINVAL;
12315         }
12316
12317         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12318         if (mode_cmd->offsets[0] != 0)
12319                 return -EINVAL;
12320
12321         aligned_height = intel_align_height(dev, mode_cmd->height,
12322                                             obj->tiling_mode);
12323         /* FIXME drm helper for size checks (especially planar formats)? */
12324         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12325                 return -EINVAL;
12326
12327         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12328         intel_fb->obj = obj;
12329         intel_fb->obj->framebuffer_references++;
12330
12331         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12332         if (ret) {
12333                 DRM_ERROR("framebuffer init failed %d\n", ret);
12334                 return ret;
12335         }
12336
12337         return 0;
12338 }
12339
12340 static struct drm_framebuffer *
12341 intel_user_framebuffer_create(struct drm_device *dev,
12342                               struct drm_file *filp,
12343                               struct drm_mode_fb_cmd2 *mode_cmd)
12344 {
12345         struct drm_i915_gem_object *obj;
12346
12347         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12348                                                 mode_cmd->handles[0]));
12349         if (&obj->base == NULL)
12350                 return ERR_PTR(-ENOENT);
12351
12352         return intel_framebuffer_create(dev, mode_cmd, obj);
12353 }
12354
12355 #ifndef CONFIG_DRM_I915_FBDEV
12356 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12357 {
12358 }
12359 #endif
12360
12361 static const struct drm_mode_config_funcs intel_mode_funcs = {
12362         .fb_create = intel_user_framebuffer_create,
12363         .output_poll_changed = intel_fbdev_output_poll_changed,
12364 };
12365
12366 /* Set up chip specific display functions */
12367 static void intel_init_display(struct drm_device *dev)
12368 {
12369         struct drm_i915_private *dev_priv = dev->dev_private;
12370
12371         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12372                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12373         else if (IS_CHERRYVIEW(dev))
12374                 dev_priv->display.find_dpll = chv_find_best_dpll;
12375         else if (IS_VALLEYVIEW(dev))
12376                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12377         else if (IS_PINEVIEW(dev))
12378                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12379         else
12380                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12381
12382         if (HAS_DDI(dev)) {
12383                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12384                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12385                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12386                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12387                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12388                 dev_priv->display.off = ironlake_crtc_off;
12389                 if (INTEL_INFO(dev)->gen >= 9)
12390                         dev_priv->display.update_primary_plane =
12391                                 skylake_update_primary_plane;
12392                 else
12393                         dev_priv->display.update_primary_plane =
12394                                 ironlake_update_primary_plane;
12395         } else if (HAS_PCH_SPLIT(dev)) {
12396                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12397                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12398                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12399                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12400                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12401                 dev_priv->display.off = ironlake_crtc_off;
12402                 dev_priv->display.update_primary_plane =
12403                         ironlake_update_primary_plane;
12404         } else if (IS_VALLEYVIEW(dev)) {
12405                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12406                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12407                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12408                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12409                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12410                 dev_priv->display.off = i9xx_crtc_off;
12411                 dev_priv->display.update_primary_plane =
12412                         i9xx_update_primary_plane;
12413         } else {
12414                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12415                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12416                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12417                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12418                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12419                 dev_priv->display.off = i9xx_crtc_off;
12420                 dev_priv->display.update_primary_plane =
12421                         i9xx_update_primary_plane;
12422         }
12423
12424         /* Returns the core display clock speed */
12425         if (IS_VALLEYVIEW(dev))
12426                 dev_priv->display.get_display_clock_speed =
12427                         valleyview_get_display_clock_speed;
12428         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12429                 dev_priv->display.get_display_clock_speed =
12430                         i945_get_display_clock_speed;
12431         else if (IS_I915G(dev))
12432                 dev_priv->display.get_display_clock_speed =
12433                         i915_get_display_clock_speed;
12434         else if (IS_I945GM(dev) || IS_845G(dev))
12435                 dev_priv->display.get_display_clock_speed =
12436                         i9xx_misc_get_display_clock_speed;
12437         else if (IS_PINEVIEW(dev))
12438                 dev_priv->display.get_display_clock_speed =
12439                         pnv_get_display_clock_speed;
12440         else if (IS_I915GM(dev))
12441                 dev_priv->display.get_display_clock_speed =
12442                         i915gm_get_display_clock_speed;
12443         else if (IS_I865G(dev))
12444                 dev_priv->display.get_display_clock_speed =
12445                         i865_get_display_clock_speed;
12446         else if (IS_I85X(dev))
12447                 dev_priv->display.get_display_clock_speed =
12448                         i855_get_display_clock_speed;
12449         else /* 852, 830 */
12450                 dev_priv->display.get_display_clock_speed =
12451                         i830_get_display_clock_speed;
12452
12453         if (IS_GEN5(dev)) {
12454                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12455         } else if (IS_GEN6(dev)) {
12456                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12457                 dev_priv->display.modeset_global_resources =
12458                         snb_modeset_global_resources;
12459         } else if (IS_IVYBRIDGE(dev)) {
12460                 /* FIXME: detect B0+ stepping and use auto training */
12461                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12462                 dev_priv->display.modeset_global_resources =
12463                         ivb_modeset_global_resources;
12464         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12465                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12466                 dev_priv->display.modeset_global_resources =
12467                         haswell_modeset_global_resources;
12468         } else if (IS_VALLEYVIEW(dev)) {
12469                 dev_priv->display.modeset_global_resources =
12470                         valleyview_modeset_global_resources;
12471         } else if (INTEL_INFO(dev)->gen >= 9) {
12472                 dev_priv->display.modeset_global_resources =
12473                         haswell_modeset_global_resources;
12474         }
12475
12476         /* Default just returns -ENODEV to indicate unsupported */
12477         dev_priv->display.queue_flip = intel_default_queue_flip;
12478
12479         switch (INTEL_INFO(dev)->gen) {
12480         case 2:
12481                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12482                 break;
12483
12484         case 3:
12485                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12486                 break;
12487
12488         case 4:
12489         case 5:
12490                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12491                 break;
12492
12493         case 6:
12494                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12495                 break;
12496         case 7:
12497         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12498                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12499                 break;
12500         }
12501
12502         intel_panel_init_backlight_funcs(dev);
12503
12504         mutex_init(&dev_priv->pps_mutex);
12505 }
12506
12507 /*
12508  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12509  * resume, or other times.  This quirk makes sure that's the case for
12510  * affected systems.
12511  */
12512 static void quirk_pipea_force(struct drm_device *dev)
12513 {
12514         struct drm_i915_private *dev_priv = dev->dev_private;
12515
12516         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12517         DRM_INFO("applying pipe a force quirk\n");
12518 }
12519
12520 static void quirk_pipeb_force(struct drm_device *dev)
12521 {
12522         struct drm_i915_private *dev_priv = dev->dev_private;
12523
12524         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12525         DRM_INFO("applying pipe b force quirk\n");
12526 }
12527
12528 /*
12529  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12530  */
12531 static void quirk_ssc_force_disable(struct drm_device *dev)
12532 {
12533         struct drm_i915_private *dev_priv = dev->dev_private;
12534         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12535         DRM_INFO("applying lvds SSC disable quirk\n");
12536 }
12537
12538 /*
12539  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12540  * brightness value
12541  */
12542 static void quirk_invert_brightness(struct drm_device *dev)
12543 {
12544         struct drm_i915_private *dev_priv = dev->dev_private;
12545         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12546         DRM_INFO("applying inverted panel brightness quirk\n");
12547 }
12548
12549 /* Some VBT's incorrectly indicate no backlight is present */
12550 static void quirk_backlight_present(struct drm_device *dev)
12551 {
12552         struct drm_i915_private *dev_priv = dev->dev_private;
12553         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12554         DRM_INFO("applying backlight present quirk\n");
12555 }
12556
12557 struct intel_quirk {
12558         int device;
12559         int subsystem_vendor;
12560         int subsystem_device;
12561         void (*hook)(struct drm_device *dev);
12562 };
12563
12564 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12565 struct intel_dmi_quirk {
12566         void (*hook)(struct drm_device *dev);
12567         const struct dmi_system_id (*dmi_id_list)[];
12568 };
12569
12570 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12571 {
12572         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12573         return 1;
12574 }
12575
12576 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12577         {
12578                 .dmi_id_list = &(const struct dmi_system_id[]) {
12579                         {
12580                                 .callback = intel_dmi_reverse_brightness,
12581                                 .ident = "NCR Corporation",
12582                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12583                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12584                                 },
12585                         },
12586                         { }  /* terminating entry */
12587                 },
12588                 .hook = quirk_invert_brightness,
12589         },
12590 };
12591
12592 static struct intel_quirk intel_quirks[] = {
12593         /* HP Mini needs pipe A force quirk (LP: #322104) */
12594         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12595
12596         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12597         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12598
12599         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12600         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12601
12602         /* 830 needs to leave pipe A & dpll A up */
12603         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12604
12605         /* 830 needs to leave pipe B & dpll B up */
12606         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12607
12608         /* Lenovo U160 cannot use SSC on LVDS */
12609         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12610
12611         /* Sony Vaio Y cannot use SSC on LVDS */
12612         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12613
12614         /* Acer Aspire 5734Z must invert backlight brightness */
12615         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12616
12617         /* Acer/eMachines G725 */
12618         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12619
12620         /* Acer/eMachines e725 */
12621         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12622
12623         /* Acer/Packard Bell NCL20 */
12624         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12625
12626         /* Acer Aspire 4736Z */
12627         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12628
12629         /* Acer Aspire 5336 */
12630         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12631
12632         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12633         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12634
12635         /* Acer C720 Chromebook (Core i3 4005U) */
12636         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12637
12638         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12639         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12640
12641         /* HP Chromebook 14 (Celeron 2955U) */
12642         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12643 };
12644
12645 static void intel_init_quirks(struct drm_device *dev)
12646 {
12647         struct pci_dev *d = dev->pdev;
12648         int i;
12649
12650         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12651                 struct intel_quirk *q = &intel_quirks[i];
12652
12653                 if (d->device == q->device &&
12654                     (d->subsystem_vendor == q->subsystem_vendor ||
12655                      q->subsystem_vendor == PCI_ANY_ID) &&
12656                     (d->subsystem_device == q->subsystem_device ||
12657                      q->subsystem_device == PCI_ANY_ID))
12658                         q->hook(dev);
12659         }
12660         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12661                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12662                         intel_dmi_quirks[i].hook(dev);
12663         }
12664 }
12665
12666 /* Disable the VGA plane that we never use */
12667 static void i915_disable_vga(struct drm_device *dev)
12668 {
12669         struct drm_i915_private *dev_priv = dev->dev_private;
12670         u8 sr1;
12671         u32 vga_reg = i915_vgacntrl_reg(dev);
12672
12673         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12674         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12675         outb(SR01, VGA_SR_INDEX);
12676         sr1 = inb(VGA_SR_DATA);
12677         outb(sr1 | 1<<5, VGA_SR_DATA);
12678         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12679         udelay(300);
12680
12681         /*
12682          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12683          * from S3 without preserving (some of?) the other bits.
12684          */
12685         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12686         POSTING_READ(vga_reg);
12687 }
12688
12689 void intel_modeset_init_hw(struct drm_device *dev)
12690 {
12691         intel_prepare_ddi(dev);
12692
12693         if (IS_VALLEYVIEW(dev))
12694                 vlv_update_cdclk(dev);
12695
12696         intel_init_clock_gating(dev);
12697
12698         intel_enable_gt_powersave(dev);
12699 }
12700
12701 void intel_modeset_init(struct drm_device *dev)
12702 {
12703         struct drm_i915_private *dev_priv = dev->dev_private;
12704         int sprite, ret;
12705         enum pipe pipe;
12706         struct intel_crtc *crtc;
12707
12708         drm_mode_config_init(dev);
12709
12710         dev->mode_config.min_width = 0;
12711         dev->mode_config.min_height = 0;
12712
12713         dev->mode_config.preferred_depth = 24;
12714         dev->mode_config.prefer_shadow = 1;
12715
12716         dev->mode_config.funcs = &intel_mode_funcs;
12717
12718         intel_init_quirks(dev);
12719
12720         intel_init_pm(dev);
12721
12722         if (INTEL_INFO(dev)->num_pipes == 0)
12723                 return;
12724
12725         intel_init_display(dev);
12726         intel_init_audio(dev);
12727
12728         if (IS_GEN2(dev)) {
12729                 dev->mode_config.max_width = 2048;
12730                 dev->mode_config.max_height = 2048;
12731         } else if (IS_GEN3(dev)) {
12732                 dev->mode_config.max_width = 4096;
12733                 dev->mode_config.max_height = 4096;
12734         } else {
12735                 dev->mode_config.max_width = 8192;
12736                 dev->mode_config.max_height = 8192;
12737         }
12738
12739         if (IS_845G(dev) || IS_I865G(dev)) {
12740                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12741                 dev->mode_config.cursor_height = 1023;
12742         } else if (IS_GEN2(dev)) {
12743                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12744                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12745         } else {
12746                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12747                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12748         }
12749
12750         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12751
12752         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12753                       INTEL_INFO(dev)->num_pipes,
12754                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12755
12756         for_each_pipe(dev_priv, pipe) {
12757                 intel_crtc_init(dev, pipe);
12758                 for_each_sprite(pipe, sprite) {
12759                         ret = intel_plane_init(dev, pipe, sprite);
12760                         if (ret)
12761                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12762                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12763                 }
12764         }
12765
12766         intel_init_dpio(dev);
12767
12768         intel_shared_dpll_init(dev);
12769
12770         /* save the BIOS value before clobbering it */
12771         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12772         /* Just disable it once at startup */
12773         i915_disable_vga(dev);
12774         intel_setup_outputs(dev);
12775
12776         /* Just in case the BIOS is doing something questionable. */
12777         intel_disable_fbc(dev);
12778
12779         drm_modeset_lock_all(dev);
12780         intel_modeset_setup_hw_state(dev, false);
12781         drm_modeset_unlock_all(dev);
12782
12783         for_each_intel_crtc(dev, crtc) {
12784                 if (!crtc->active)
12785                         continue;
12786
12787                 /*
12788                  * Note that reserving the BIOS fb up front prevents us
12789                  * from stuffing other stolen allocations like the ring
12790                  * on top.  This prevents some ugliness at boot time, and
12791                  * can even allow for smooth boot transitions if the BIOS
12792                  * fb is large enough for the active pipe configuration.
12793                  */
12794                 if (dev_priv->display.get_plane_config) {
12795                         dev_priv->display.get_plane_config(crtc,
12796                                                            &crtc->plane_config);
12797                         /*
12798                          * If the fb is shared between multiple heads, we'll
12799                          * just get the first one.
12800                          */
12801                         intel_find_plane_obj(crtc, &crtc->plane_config);
12802                 }
12803         }
12804 }
12805
12806 static void intel_enable_pipe_a(struct drm_device *dev)
12807 {
12808         struct intel_connector *connector;
12809         struct drm_connector *crt = NULL;
12810         struct intel_load_detect_pipe load_detect_temp;
12811         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12812
12813         /* We can't just switch on the pipe A, we need to set things up with a
12814          * proper mode and output configuration. As a gross hack, enable pipe A
12815          * by enabling the load detect pipe once. */
12816         list_for_each_entry(connector,
12817                             &dev->mode_config.connector_list,
12818                             base.head) {
12819                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12820                         crt = &connector->base;
12821                         break;
12822                 }
12823         }
12824
12825         if (!crt)
12826                 return;
12827
12828         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12829                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12830 }
12831
12832 static bool
12833 intel_check_plane_mapping(struct intel_crtc *crtc)
12834 {
12835         struct drm_device *dev = crtc->base.dev;
12836         struct drm_i915_private *dev_priv = dev->dev_private;
12837         u32 reg, val;
12838
12839         if (INTEL_INFO(dev)->num_pipes == 1)
12840                 return true;
12841
12842         reg = DSPCNTR(!crtc->plane);
12843         val = I915_READ(reg);
12844
12845         if ((val & DISPLAY_PLANE_ENABLE) &&
12846             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12847                 return false;
12848
12849         return true;
12850 }
12851
12852 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12853 {
12854         struct drm_device *dev = crtc->base.dev;
12855         struct drm_i915_private *dev_priv = dev->dev_private;
12856         u32 reg;
12857
12858         /* Clear any frame start delays used for debugging left by the BIOS */
12859         reg = PIPECONF(crtc->config.cpu_transcoder);
12860         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12861
12862         /* restore vblank interrupts to correct state */
12863         if (crtc->active) {
12864                 update_scanline_offset(crtc);
12865                 drm_vblank_on(dev, crtc->pipe);
12866         } else
12867                 drm_vblank_off(dev, crtc->pipe);
12868
12869         /* We need to sanitize the plane -> pipe mapping first because this will
12870          * disable the crtc (and hence change the state) if it is wrong. Note
12871          * that gen4+ has a fixed plane -> pipe mapping.  */
12872         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12873                 struct intel_connector *connector;
12874                 bool plane;
12875
12876                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12877                               crtc->base.base.id);
12878
12879                 /* Pipe has the wrong plane attached and the plane is active.
12880                  * Temporarily change the plane mapping and disable everything
12881                  * ...  */
12882                 plane = crtc->plane;
12883                 crtc->plane = !plane;
12884                 crtc->primary_enabled = true;
12885                 dev_priv->display.crtc_disable(&crtc->base);
12886                 crtc->plane = plane;
12887
12888                 /* ... and break all links. */
12889                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12890                                     base.head) {
12891                         if (connector->encoder->base.crtc != &crtc->base)
12892                                 continue;
12893
12894                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12895                         connector->base.encoder = NULL;
12896                 }
12897                 /* multiple connectors may have the same encoder:
12898                  *  handle them and break crtc link separately */
12899                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12900                                     base.head)
12901                         if (connector->encoder->base.crtc == &crtc->base) {
12902                                 connector->encoder->base.crtc = NULL;
12903                                 connector->encoder->connectors_active = false;
12904                         }
12905
12906                 WARN_ON(crtc->active);
12907                 crtc->base.enabled = false;
12908         }
12909
12910         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12911             crtc->pipe == PIPE_A && !crtc->active) {
12912                 /* BIOS forgot to enable pipe A, this mostly happens after
12913                  * resume. Force-enable the pipe to fix this, the update_dpms
12914                  * call below we restore the pipe to the right state, but leave
12915                  * the required bits on. */
12916                 intel_enable_pipe_a(dev);
12917         }
12918
12919         /* Adjust the state of the output pipe according to whether we
12920          * have active connectors/encoders. */
12921         intel_crtc_update_dpms(&crtc->base);
12922
12923         if (crtc->active != crtc->base.enabled) {
12924                 struct intel_encoder *encoder;
12925
12926                 /* This can happen either due to bugs in the get_hw_state
12927                  * functions or because the pipe is force-enabled due to the
12928                  * pipe A quirk. */
12929                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12930                               crtc->base.base.id,
12931                               crtc->base.enabled ? "enabled" : "disabled",
12932                               crtc->active ? "enabled" : "disabled");
12933
12934                 crtc->base.enabled = crtc->active;
12935
12936                 /* Because we only establish the connector -> encoder ->
12937                  * crtc links if something is active, this means the
12938                  * crtc is now deactivated. Break the links. connector
12939                  * -> encoder links are only establish when things are
12940                  *  actually up, hence no need to break them. */
12941                 WARN_ON(crtc->active);
12942
12943                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12944                         WARN_ON(encoder->connectors_active);
12945                         encoder->base.crtc = NULL;
12946                 }
12947         }
12948
12949         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12950                 /*
12951                  * We start out with underrun reporting disabled to avoid races.
12952                  * For correct bookkeeping mark this on active crtcs.
12953                  *
12954                  * Also on gmch platforms we dont have any hardware bits to
12955                  * disable the underrun reporting. Which means we need to start
12956                  * out with underrun reporting disabled also on inactive pipes,
12957                  * since otherwise we'll complain about the garbage we read when
12958                  * e.g. coming up after runtime pm.
12959                  *
12960                  * No protection against concurrent access is required - at
12961                  * worst a fifo underrun happens which also sets this to false.
12962                  */
12963                 crtc->cpu_fifo_underrun_disabled = true;
12964                 crtc->pch_fifo_underrun_disabled = true;
12965         }
12966 }
12967
12968 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12969 {
12970         struct intel_connector *connector;
12971         struct drm_device *dev = encoder->base.dev;
12972
12973         /* We need to check both for a crtc link (meaning that the
12974          * encoder is active and trying to read from a pipe) and the
12975          * pipe itself being active. */
12976         bool has_active_crtc = encoder->base.crtc &&
12977                 to_intel_crtc(encoder->base.crtc)->active;
12978
12979         if (encoder->connectors_active && !has_active_crtc) {
12980                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12981                               encoder->base.base.id,
12982                               encoder->base.name);
12983
12984                 /* Connector is active, but has no active pipe. This is
12985                  * fallout from our resume register restoring. Disable
12986                  * the encoder manually again. */
12987                 if (encoder->base.crtc) {
12988                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12989                                       encoder->base.base.id,
12990                                       encoder->base.name);
12991                         encoder->disable(encoder);
12992                         if (encoder->post_disable)
12993                                 encoder->post_disable(encoder);
12994                 }
12995                 encoder->base.crtc = NULL;
12996                 encoder->connectors_active = false;
12997
12998                 /* Inconsistent output/port/pipe state happens presumably due to
12999                  * a bug in one of the get_hw_state functions. Or someplace else
13000                  * in our code, like the register restore mess on resume. Clamp
13001                  * things to off as a safer default. */
13002                 list_for_each_entry(connector,
13003                                     &dev->mode_config.connector_list,
13004                                     base.head) {
13005                         if (connector->encoder != encoder)
13006                                 continue;
13007                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13008                         connector->base.encoder = NULL;
13009                 }
13010         }
13011         /* Enabled encoders without active connectors will be fixed in
13012          * the crtc fixup. */
13013 }
13014
13015 void i915_redisable_vga_power_on(struct drm_device *dev)
13016 {
13017         struct drm_i915_private *dev_priv = dev->dev_private;
13018         u32 vga_reg = i915_vgacntrl_reg(dev);
13019
13020         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13021                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13022                 i915_disable_vga(dev);
13023         }
13024 }
13025
13026 void i915_redisable_vga(struct drm_device *dev)
13027 {
13028         struct drm_i915_private *dev_priv = dev->dev_private;
13029
13030         /* This function can be called both from intel_modeset_setup_hw_state or
13031          * at a very early point in our resume sequence, where the power well
13032          * structures are not yet restored. Since this function is at a very
13033          * paranoid "someone might have enabled VGA while we were not looking"
13034          * level, just check if the power well is enabled instead of trying to
13035          * follow the "don't touch the power well if we don't need it" policy
13036          * the rest of the driver uses. */
13037         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13038                 return;
13039
13040         i915_redisable_vga_power_on(dev);
13041 }
13042
13043 static bool primary_get_hw_state(struct intel_crtc *crtc)
13044 {
13045         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13046
13047         if (!crtc->active)
13048                 return false;
13049
13050         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13051 }
13052
13053 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13054 {
13055         struct drm_i915_private *dev_priv = dev->dev_private;
13056         enum pipe pipe;
13057         struct intel_crtc *crtc;
13058         struct intel_encoder *encoder;
13059         struct intel_connector *connector;
13060         int i;
13061
13062         for_each_intel_crtc(dev, crtc) {
13063                 memset(&crtc->config, 0, sizeof(crtc->config));
13064
13065                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13066
13067                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13068                                                                  &crtc->config);
13069
13070                 crtc->base.enabled = crtc->active;
13071                 crtc->primary_enabled = primary_get_hw_state(crtc);
13072
13073                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13074                               crtc->base.base.id,
13075                               crtc->active ? "enabled" : "disabled");
13076         }
13077
13078         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13079                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13080
13081                 pll->on = pll->get_hw_state(dev_priv, pll,
13082                                             &pll->config.hw_state);
13083                 pll->active = 0;
13084                 pll->config.crtc_mask = 0;
13085                 for_each_intel_crtc(dev, crtc) {
13086                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13087                                 pll->active++;
13088                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13089                         }
13090                 }
13091
13092                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13093                               pll->name, pll->config.crtc_mask, pll->on);
13094
13095                 if (pll->config.crtc_mask)
13096                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13097         }
13098
13099         for_each_intel_encoder(dev, encoder) {
13100                 pipe = 0;
13101
13102                 if (encoder->get_hw_state(encoder, &pipe)) {
13103                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13104                         encoder->base.crtc = &crtc->base;
13105                         encoder->get_config(encoder, &crtc->config);
13106                 } else {
13107                         encoder->base.crtc = NULL;
13108                 }
13109
13110                 encoder->connectors_active = false;
13111                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13112                               encoder->base.base.id,
13113                               encoder->base.name,
13114                               encoder->base.crtc ? "enabled" : "disabled",
13115                               pipe_name(pipe));
13116         }
13117
13118         list_for_each_entry(connector, &dev->mode_config.connector_list,
13119                             base.head) {
13120                 if (connector->get_hw_state(connector)) {
13121                         connector->base.dpms = DRM_MODE_DPMS_ON;
13122                         connector->encoder->connectors_active = true;
13123                         connector->base.encoder = &connector->encoder->base;
13124                 } else {
13125                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13126                         connector->base.encoder = NULL;
13127                 }
13128                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13129                               connector->base.base.id,
13130                               connector->base.name,
13131                               connector->base.encoder ? "enabled" : "disabled");
13132         }
13133 }
13134
13135 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13136  * and i915 state tracking structures. */
13137 void intel_modeset_setup_hw_state(struct drm_device *dev,
13138                                   bool force_restore)
13139 {
13140         struct drm_i915_private *dev_priv = dev->dev_private;
13141         enum pipe pipe;
13142         struct intel_crtc *crtc;
13143         struct intel_encoder *encoder;
13144         int i;
13145
13146         intel_modeset_readout_hw_state(dev);
13147
13148         /*
13149          * Now that we have the config, copy it to each CRTC struct
13150          * Note that this could go away if we move to using crtc_config
13151          * checking everywhere.
13152          */
13153         for_each_intel_crtc(dev, crtc) {
13154                 if (crtc->active && i915.fastboot) {
13155                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13156                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13157                                       crtc->base.base.id);
13158                         drm_mode_debug_printmodeline(&crtc->base.mode);
13159                 }
13160         }
13161
13162         /* HW state is read out, now we need to sanitize this mess. */
13163         for_each_intel_encoder(dev, encoder) {
13164                 intel_sanitize_encoder(encoder);
13165         }
13166
13167         for_each_pipe(dev_priv, pipe) {
13168                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13169                 intel_sanitize_crtc(crtc);
13170                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13171         }
13172
13173         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13174                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13175
13176                 if (!pll->on || pll->active)
13177                         continue;
13178
13179                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13180
13181                 pll->disable(dev_priv, pll);
13182                 pll->on = false;
13183         }
13184
13185         if (HAS_PCH_SPLIT(dev))
13186                 ilk_wm_get_hw_state(dev);
13187
13188         if (force_restore) {
13189                 i915_redisable_vga(dev);
13190
13191                 /*
13192                  * We need to use raw interfaces for restoring state to avoid
13193                  * checking (bogus) intermediate states.
13194                  */
13195                 for_each_pipe(dev_priv, pipe) {
13196                         struct drm_crtc *crtc =
13197                                 dev_priv->pipe_to_crtc_mapping[pipe];
13198
13199                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13200                                          crtc->primary->fb);
13201                 }
13202         } else {
13203                 intel_modeset_update_staged_output_state(dev);
13204         }
13205
13206         intel_modeset_check_state(dev);
13207 }
13208
13209 void intel_modeset_gem_init(struct drm_device *dev)
13210 {
13211         struct drm_crtc *c;
13212         struct drm_i915_gem_object *obj;
13213
13214         mutex_lock(&dev->struct_mutex);
13215         intel_init_gt_powersave(dev);
13216         mutex_unlock(&dev->struct_mutex);
13217
13218         intel_modeset_init_hw(dev);
13219
13220         intel_setup_overlay(dev);
13221
13222         /*
13223          * Make sure any fbs we allocated at startup are properly
13224          * pinned & fenced.  When we do the allocation it's too early
13225          * for this.
13226          */
13227         mutex_lock(&dev->struct_mutex);
13228         for_each_crtc(dev, c) {
13229                 obj = intel_fb_obj(c->primary->fb);
13230                 if (obj == NULL)
13231                         continue;
13232
13233                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13234                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13235                                   to_intel_crtc(c)->pipe);
13236                         drm_framebuffer_unreference(c->primary->fb);
13237                         c->primary->fb = NULL;
13238                 }
13239         }
13240         mutex_unlock(&dev->struct_mutex);
13241 }
13242
13243 void intel_connector_unregister(struct intel_connector *intel_connector)
13244 {
13245         struct drm_connector *connector = &intel_connector->base;
13246
13247         intel_panel_destroy_backlight(connector);
13248         drm_connector_unregister(connector);
13249 }
13250
13251 void intel_modeset_cleanup(struct drm_device *dev)
13252 {
13253         struct drm_i915_private *dev_priv = dev->dev_private;
13254         struct drm_connector *connector;
13255
13256         /*
13257          * Interrupts and polling as the first thing to avoid creating havoc.
13258          * Too much stuff here (turning of rps, connectors, ...) would
13259          * experience fancy races otherwise.
13260          */
13261         intel_irq_uninstall(dev_priv);
13262
13263         /*
13264          * Due to the hpd irq storm handling the hotplug work can re-arm the
13265          * poll handlers. Hence disable polling after hpd handling is shut down.
13266          */
13267         drm_kms_helper_poll_fini(dev);
13268
13269         mutex_lock(&dev->struct_mutex);
13270
13271         intel_unregister_dsm_handler();
13272
13273         intel_disable_fbc(dev);
13274
13275         intel_disable_gt_powersave(dev);
13276
13277         ironlake_teardown_rc6(dev);
13278
13279         mutex_unlock(&dev->struct_mutex);
13280
13281         /* flush any delayed tasks or pending work */
13282         flush_scheduled_work();
13283
13284         /* destroy the backlight and sysfs files before encoders/connectors */
13285         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13286                 struct intel_connector *intel_connector;
13287
13288                 intel_connector = to_intel_connector(connector);
13289                 intel_connector->unregister(intel_connector);
13290         }
13291
13292         drm_mode_config_cleanup(dev);
13293
13294         intel_cleanup_overlay(dev);
13295
13296         mutex_lock(&dev->struct_mutex);
13297         intel_cleanup_gt_powersave(dev);
13298         mutex_unlock(&dev->struct_mutex);
13299 }
13300
13301 /*
13302  * Return which encoder is currently attached for connector.
13303  */
13304 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13305 {
13306         return &intel_attached_encoder(connector)->base;
13307 }
13308
13309 void intel_connector_attach_encoder(struct intel_connector *connector,
13310                                     struct intel_encoder *encoder)
13311 {
13312         connector->encoder = encoder;
13313         drm_mode_connector_attach_encoder(&connector->base,
13314                                           &encoder->base);
13315 }
13316
13317 /*
13318  * set vga decode state - true == enable VGA decode
13319  */
13320 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13321 {
13322         struct drm_i915_private *dev_priv = dev->dev_private;
13323         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13324         u16 gmch_ctrl;
13325
13326         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13327                 DRM_ERROR("failed to read control word\n");
13328                 return -EIO;
13329         }
13330
13331         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13332                 return 0;
13333
13334         if (state)
13335                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13336         else
13337                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13338
13339         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13340                 DRM_ERROR("failed to write control word\n");
13341                 return -EIO;
13342         }
13343
13344         return 0;
13345 }
13346
13347 struct intel_display_error_state {
13348
13349         u32 power_well_driver;
13350
13351         int num_transcoders;
13352
13353         struct intel_cursor_error_state {
13354                 u32 control;
13355                 u32 position;
13356                 u32 base;
13357                 u32 size;
13358         } cursor[I915_MAX_PIPES];
13359
13360         struct intel_pipe_error_state {
13361                 bool power_domain_on;
13362                 u32 source;
13363                 u32 stat;
13364         } pipe[I915_MAX_PIPES];
13365
13366         struct intel_plane_error_state {
13367                 u32 control;
13368                 u32 stride;
13369                 u32 size;
13370                 u32 pos;
13371                 u32 addr;
13372                 u32 surface;
13373                 u32 tile_offset;
13374         } plane[I915_MAX_PIPES];
13375
13376         struct intel_transcoder_error_state {
13377                 bool power_domain_on;
13378                 enum transcoder cpu_transcoder;
13379
13380                 u32 conf;
13381
13382                 u32 htotal;
13383                 u32 hblank;
13384                 u32 hsync;
13385                 u32 vtotal;
13386                 u32 vblank;
13387                 u32 vsync;
13388         } transcoder[4];
13389 };
13390
13391 struct intel_display_error_state *
13392 intel_display_capture_error_state(struct drm_device *dev)
13393 {
13394         struct drm_i915_private *dev_priv = dev->dev_private;
13395         struct intel_display_error_state *error;
13396         int transcoders[] = {
13397                 TRANSCODER_A,
13398                 TRANSCODER_B,
13399                 TRANSCODER_C,
13400                 TRANSCODER_EDP,
13401         };
13402         int i;
13403
13404         if (INTEL_INFO(dev)->num_pipes == 0)
13405                 return NULL;
13406
13407         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13408         if (error == NULL)
13409                 return NULL;
13410
13411         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13412                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13413
13414         for_each_pipe(dev_priv, i) {
13415                 error->pipe[i].power_domain_on =
13416                         __intel_display_power_is_enabled(dev_priv,
13417                                                          POWER_DOMAIN_PIPE(i));
13418                 if (!error->pipe[i].power_domain_on)
13419                         continue;
13420
13421                 error->cursor[i].control = I915_READ(CURCNTR(i));
13422                 error->cursor[i].position = I915_READ(CURPOS(i));
13423                 error->cursor[i].base = I915_READ(CURBASE(i));
13424
13425                 error->plane[i].control = I915_READ(DSPCNTR(i));
13426                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13427                 if (INTEL_INFO(dev)->gen <= 3) {
13428                         error->plane[i].size = I915_READ(DSPSIZE(i));
13429                         error->plane[i].pos = I915_READ(DSPPOS(i));
13430                 }
13431                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13432                         error->plane[i].addr = I915_READ(DSPADDR(i));
13433                 if (INTEL_INFO(dev)->gen >= 4) {
13434                         error->plane[i].surface = I915_READ(DSPSURF(i));
13435                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13436                 }
13437
13438                 error->pipe[i].source = I915_READ(PIPESRC(i));
13439
13440                 if (HAS_GMCH_DISPLAY(dev))
13441                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13442         }
13443
13444         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13445         if (HAS_DDI(dev_priv->dev))
13446                 error->num_transcoders++; /* Account for eDP. */
13447
13448         for (i = 0; i < error->num_transcoders; i++) {
13449                 enum transcoder cpu_transcoder = transcoders[i];
13450
13451                 error->transcoder[i].power_domain_on =
13452                         __intel_display_power_is_enabled(dev_priv,
13453                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13454                 if (!error->transcoder[i].power_domain_on)
13455                         continue;
13456
13457                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13458
13459                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13460                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13461                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13462                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13463                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13464                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13465                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13466         }
13467
13468         return error;
13469 }
13470
13471 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13472
13473 void
13474 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13475                                 struct drm_device *dev,
13476                                 struct intel_display_error_state *error)
13477 {
13478         struct drm_i915_private *dev_priv = dev->dev_private;
13479         int i;
13480
13481         if (!error)
13482                 return;
13483
13484         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13485         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13486                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13487                            error->power_well_driver);
13488         for_each_pipe(dev_priv, i) {
13489                 err_printf(m, "Pipe [%d]:\n", i);
13490                 err_printf(m, "  Power: %s\n",
13491                            error->pipe[i].power_domain_on ? "on" : "off");
13492                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13493                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13494
13495                 err_printf(m, "Plane [%d]:\n", i);
13496                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13497                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13498                 if (INTEL_INFO(dev)->gen <= 3) {
13499                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13500                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13501                 }
13502                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13503                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13504                 if (INTEL_INFO(dev)->gen >= 4) {
13505                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13506                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13507                 }
13508
13509                 err_printf(m, "Cursor [%d]:\n", i);
13510                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13511                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13512                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13513         }
13514
13515         for (i = 0; i < error->num_transcoders; i++) {
13516                 err_printf(m, "CPU transcoder: %c\n",
13517                            transcoder_name(error->transcoder[i].cpu_transcoder));
13518                 err_printf(m, "  Power: %s\n",
13519                            error->transcoder[i].power_domain_on ? "on" : "off");
13520                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13521                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13522                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13523                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13524                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13525                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13526                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13527         }
13528 }
13529
13530 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13531 {
13532         struct intel_crtc *crtc;
13533
13534         for_each_intel_crtc(dev, crtc) {
13535                 struct intel_unpin_work *work;
13536
13537                 spin_lock_irq(&dev->event_lock);
13538
13539                 work = crtc->unpin_work;
13540
13541                 if (work && work->event &&
13542                     work->event->base.file_priv == file) {
13543                         kfree(work->event);
13544                         work->event = NULL;
13545                 }
13546
13547                 spin_unlock_irq(&dev->event_lock);
13548         }
13549 }