2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
72 static const uint32_t intel_cursor_formats[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc);
98 static void chv_prepare_pll(struct intel_crtc *crtc);
100 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
102 if (!connector->mst_port)
103 return connector->encoder;
105 return &connector->mst_port->mst_encoders[pipe]->base;
114 int p2_slow, p2_fast;
117 typedef struct intel_limit intel_limit_t;
119 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_pch_rawclk(struct drm_device *dev)
126 struct drm_i915_private *dev_priv = dev->dev_private;
128 WARN_ON(!HAS_PCH_SPLIT(dev));
130 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 static inline u32 /* units of 100MHz */
134 intel_fdi_link_freq(struct drm_device *dev)
137 struct drm_i915_private *dev_priv = dev->dev_private;
138 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 static const intel_limit_t intel_limits_i8xx_dac = {
144 .dot = { .min = 25000, .max = 350000 },
145 .vco = { .min = 908000, .max = 1512000 },
146 .n = { .min = 2, .max = 16 },
147 .m = { .min = 96, .max = 140 },
148 .m1 = { .min = 18, .max = 26 },
149 .m2 = { .min = 6, .max = 16 },
150 .p = { .min = 4, .max = 128 },
151 .p1 = { .min = 2, .max = 33 },
152 .p2 = { .dot_limit = 165000,
153 .p2_slow = 4, .p2_fast = 2 },
156 static const intel_limit_t intel_limits_i8xx_dvo = {
157 .dot = { .min = 25000, .max = 350000 },
158 .vco = { .min = 908000, .max = 1512000 },
159 .n = { .min = 2, .max = 16 },
160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 4 },
169 static const intel_limit_t intel_limits_i8xx_lvds = {
170 .dot = { .min = 25000, .max = 350000 },
171 .vco = { .min = 908000, .max = 1512000 },
172 .n = { .min = 2, .max = 16 },
173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 1, .max = 6 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 14, .p2_fast = 7 },
182 static const intel_limit_t intel_limits_i9xx_sdvo = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 5, .max = 80 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 200000,
192 .p2_slow = 10, .p2_fast = 5 },
195 static const intel_limit_t intel_limits_i9xx_lvds = {
196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
202 .p = { .min = 7, .max = 98 },
203 .p1 = { .min = 1, .max = 8 },
204 .p2 = { .dot_limit = 112000,
205 .p2_slow = 14, .p2_fast = 7 },
209 static const intel_limit_t intel_limits_g4x_sdvo = {
210 .dot = { .min = 25000, .max = 270000 },
211 .vco = { .min = 1750000, .max = 3500000},
212 .n = { .min = 1, .max = 4 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 10, .max = 30 },
217 .p1 = { .min = 1, .max = 3},
218 .p2 = { .dot_limit = 270000,
224 static const intel_limit_t intel_limits_g4x_hdmi = {
225 .dot = { .min = 22000, .max = 400000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 16, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 5, .max = 80 },
232 .p1 = { .min = 1, .max = 8},
233 .p2 = { .dot_limit = 165000,
234 .p2_slow = 10, .p2_fast = 5 },
237 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
238 .dot = { .min = 20000, .max = 115000 },
239 .vco = { .min = 1750000, .max = 3500000 },
240 .n = { .min = 1, .max = 3 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 17, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 28, .max = 112 },
245 .p1 = { .min = 2, .max = 8 },
246 .p2 = { .dot_limit = 0,
247 .p2_slow = 14, .p2_fast = 14
251 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
252 .dot = { .min = 80000, .max = 224000 },
253 .vco = { .min = 1750000, .max = 3500000 },
254 .n = { .min = 1, .max = 3 },
255 .m = { .min = 104, .max = 138 },
256 .m1 = { .min = 17, .max = 23 },
257 .m2 = { .min = 5, .max = 11 },
258 .p = { .min = 14, .max = 42 },
259 .p1 = { .min = 2, .max = 6 },
260 .p2 = { .dot_limit = 0,
261 .p2_slow = 7, .p2_fast = 7
265 static const intel_limit_t intel_limits_pineview_sdvo = {
266 .dot = { .min = 20000, .max = 400000},
267 .vco = { .min = 1700000, .max = 3500000 },
268 /* Pineview's Ncounter is a ring counter */
269 .n = { .min = 3, .max = 6 },
270 .m = { .min = 2, .max = 256 },
271 /* Pineview only has one combined m divider, which we treat as m2. */
272 .m1 = { .min = 0, .max = 0 },
273 .m2 = { .min = 0, .max = 254 },
274 .p = { .min = 5, .max = 80 },
275 .p1 = { .min = 1, .max = 8 },
276 .p2 = { .dot_limit = 200000,
277 .p2_slow = 10, .p2_fast = 5 },
280 static const intel_limit_t intel_limits_pineview_lvds = {
281 .dot = { .min = 20000, .max = 400000 },
282 .vco = { .min = 1700000, .max = 3500000 },
283 .n = { .min = 3, .max = 6 },
284 .m = { .min = 2, .max = 256 },
285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 7, .max = 112 },
288 .p1 = { .min = 1, .max = 8 },
289 .p2 = { .dot_limit = 112000,
290 .p2_slow = 14, .p2_fast = 14 },
293 /* Ironlake / Sandybridge
295 * We calculate clock using (register_value + 2) for N/M1/M2, so here
296 * the range value for them is (actual_value - 2).
298 static const intel_limit_t intel_limits_ironlake_dac = {
299 .dot = { .min = 25000, .max = 350000 },
300 .vco = { .min = 1760000, .max = 3510000 },
301 .n = { .min = 1, .max = 5 },
302 .m = { .min = 79, .max = 127 },
303 .m1 = { .min = 12, .max = 22 },
304 .m2 = { .min = 5, .max = 9 },
305 .p = { .min = 5, .max = 80 },
306 .p1 = { .min = 1, .max = 8 },
307 .p2 = { .dot_limit = 225000,
308 .p2_slow = 10, .p2_fast = 5 },
311 static const intel_limit_t intel_limits_ironlake_single_lvds = {
312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 79, .max = 118 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 28, .max = 112 },
319 .p1 = { .min = 2, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 14, .p2_fast = 14 },
324 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 127 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 14, .max = 56 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 7, .p2_fast = 7 },
337 /* LVDS 100mhz refclk limits. */
338 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
339 .dot = { .min = 25000, .max = 350000 },
340 .vco = { .min = 1760000, .max = 3510000 },
341 .n = { .min = 1, .max = 2 },
342 .m = { .min = 79, .max = 126 },
343 .m1 = { .min = 12, .max = 22 },
344 .m2 = { .min = 5, .max = 9 },
345 .p = { .min = 28, .max = 112 },
346 .p1 = { .min = 2, .max = 8 },
347 .p2 = { .dot_limit = 225000,
348 .p2_slow = 14, .p2_fast = 14 },
351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 3 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 14, .max = 42 },
359 .p1 = { .min = 2, .max = 6 },
360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 7, .p2_fast = 7 },
364 static const intel_limit_t intel_limits_vlv = {
366 * These are the data rate limits (measured in fast clocks)
367 * since those are the strictest limits we have. The fast
368 * clock and actual rate limits are more relaxed, so checking
369 * them would make no difference.
371 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m1 = { .min = 2, .max = 3 },
375 .m2 = { .min = 11, .max = 156 },
376 .p1 = { .min = 2, .max = 3 },
377 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 static const intel_limit_t intel_limits_chv = {
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
387 .dot = { .min = 25000 * 5, .max = 540000 * 5},
388 .vco = { .min = 4860000, .max = 6700000 },
389 .n = { .min = 1, .max = 1 },
390 .m1 = { .min = 2, .max = 2 },
391 .m2 = { .min = 24 << 22, .max = 175 << 22 },
392 .p1 = { .min = 2, .max = 4 },
393 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 static void vlv_clock(int refclk, intel_clock_t *clock)
398 clock->m = clock->m1 * clock->m2;
399 clock->p = clock->p1 * clock->p2;
400 if (WARN_ON(clock->n == 0 || clock->p == 0))
402 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
403 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
407 * Returns whether any output on the specified pipe is of the specified type
409 static bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
411 struct drm_device *dev = crtc->base.dev;
412 struct intel_encoder *encoder;
414 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
415 if (encoder->type == type)
421 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
424 struct drm_device *dev = crtc->base.dev;
425 const intel_limit_t *limit;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
432 limit = &intel_limits_ironlake_dual_lvds;
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
437 limit = &intel_limits_ironlake_single_lvds;
440 limit = &intel_limits_ironlake_dac;
445 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
466 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
468 struct drm_device *dev = crtc->base.dev;
469 const intel_limit_t *limit;
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_CHERRYVIEW(dev)) {
481 limit = &intel_limits_chv;
482 } else if (IS_VALLEYVIEW(dev)) {
483 limit = &intel_limits_vlv;
484 } else if (!IS_GEN2(dev)) {
485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
486 limit = &intel_limits_i9xx_lvds;
488 limit = &intel_limits_i9xx_sdvo;
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i8xx_lvds;
492 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
493 limit = &intel_limits_i8xx_dvo;
495 limit = &intel_limits_i8xx_dac;
500 /* m1 is reserved as 0 in Pineview, n is a ring counter */
501 static void pineview_clock(int refclk, intel_clock_t *clock)
503 clock->m = clock->m2 + 2;
504 clock->p = clock->p1 * clock->p2;
505 if (WARN_ON(clock->n == 0 || clock->p == 0))
507 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
508 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
511 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
513 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
516 static void i9xx_clock(int refclk, intel_clock_t *clock)
518 clock->m = i9xx_dpll_compute_m(clock);
519 clock->p = clock->p1 * clock->p2;
520 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
522 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
523 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
526 static void chv_clock(int refclk, intel_clock_t *clock)
528 clock->m = clock->m1 * clock->m2;
529 clock->p = clock->p1 * clock->p2;
530 if (WARN_ON(clock->n == 0 || clock->p == 0))
532 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
534 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
537 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
543 static bool intel_PLL_is_valid(struct drm_device *dev,
544 const intel_limit_t *limit,
545 const intel_clock_t *clock)
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
550 INTELPllInvalid("p1 out of range\n");
551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
552 INTELPllInvalid("m2 out of range\n");
553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
554 INTELPllInvalid("m1 out of range\n");
556 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
557 if (clock->m1 <= clock->m2)
558 INTELPllInvalid("m1 <= m2\n");
560 if (!IS_VALLEYVIEW(dev)) {
561 if (clock->p < limit->p.min || limit->p.max < clock->p)
562 INTELPllInvalid("p out of range\n");
563 if (clock->m < limit->m.min || limit->m.max < clock->m)
564 INTELPllInvalid("m out of range\n");
567 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
568 INTELPllInvalid("vco out of range\n");
569 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
570 * connector, etc., rather than just a single range.
572 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
573 INTELPllInvalid("dot out of range\n");
579 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
580 int target, int refclk, intel_clock_t *match_clock,
581 intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->base.dev;
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
596 clock.p2 = limit->p2.p2_slow;
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
601 clock.p2 = limit->p2.p2_fast;
604 memset(best_clock, 0, sizeof(*best_clock));
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 if (clock.m2 >= clock.m1)
612 for (clock.n = limit->n.min;
613 clock.n <= limit->n.max; clock.n++) {
614 for (clock.p1 = limit->p1.min;
615 clock.p1 <= limit->p1.max; clock.p1++) {
618 i9xx_clock(refclk, &clock);
619 if (!intel_PLL_is_valid(dev, limit,
623 clock.p != match_clock->p)
626 this_err = abs(clock.dot - target);
627 if (this_err < err) {
636 return (err != target);
640 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
641 int target, int refclk, intel_clock_t *match_clock,
642 intel_clock_t *best_clock)
644 struct drm_device *dev = crtc->base.dev;
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
657 clock.p2 = limit->p2.p2_slow;
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
662 clock.p2 = limit->p2.p2_fast;
665 memset(best_clock, 0, sizeof(*best_clock));
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 for (clock.n = limit->n.min;
672 clock.n <= limit->n.max; clock.n++) {
673 for (clock.p1 = limit->p1.min;
674 clock.p1 <= limit->p1.max; clock.p1++) {
677 pineview_clock(refclk, &clock);
678 if (!intel_PLL_is_valid(dev, limit,
682 clock.p != match_clock->p)
685 this_err = abs(clock.dot - target);
686 if (this_err < err) {
695 return (err != target);
699 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
700 int target, int refclk, intel_clock_t *match_clock,
701 intel_clock_t *best_clock)
703 struct drm_device *dev = crtc->base.dev;
707 /* approximately equals target * 0.00585 */
708 int err_most = (target >> 8) + (target >> 9);
711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
712 if (intel_is_dual_link_lvds(dev))
713 clock.p2 = limit->p2.p2_fast;
715 clock.p2 = limit->p2.p2_slow;
717 if (target < limit->p2.dot_limit)
718 clock.p2 = limit->p2.p2_slow;
720 clock.p2 = limit->p2.p2_fast;
723 memset(best_clock, 0, sizeof(*best_clock));
724 max_n = limit->n.max;
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
727 /* based on hardware requirement, prefere larger m1,m2 */
728 for (clock.m1 = limit->m1.max;
729 clock.m1 >= limit->m1.min; clock.m1--) {
730 for (clock.m2 = limit->m2.max;
731 clock.m2 >= limit->m2.min; clock.m2--) {
732 for (clock.p1 = limit->p1.max;
733 clock.p1 >= limit->p1.min; clock.p1--) {
736 i9xx_clock(refclk, &clock);
737 if (!intel_PLL_is_valid(dev, limit,
741 this_err = abs(clock.dot - target);
742 if (this_err < err_most) {
756 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
760 struct drm_device *dev = crtc->base.dev;
762 unsigned int bestppm = 1000000;
763 /* min update 19.2 MHz */
764 int max_n = min(limit->n.max, refclk / 19200);
767 target *= 5; /* fast clock */
769 memset(best_clock, 0, sizeof(*best_clock));
771 /* based on hardware requirement, prefer smaller n to precision */
772 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
773 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
774 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
775 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
776 clock.p = clock.p1 * clock.p2;
777 /* based on hardware requirement, prefer bigger m1,m2 values */
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
779 unsigned int ppm, diff;
781 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
784 vlv_clock(refclk, &clock);
786 if (!intel_PLL_is_valid(dev, limit,
790 diff = abs(clock.dot - target);
791 ppm = div_u64(1000000ULL * diff, target);
793 if (ppm < 100 && clock.p > best_clock->p) {
799 if (bestppm >= 10 && ppm < bestppm - 10) {
813 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
817 struct drm_device *dev = crtc->base.dev;
822 memset(best_clock, 0, sizeof(*best_clock));
825 * Based on hardware doc, the n always set to 1, and m1 always
826 * set to 2. If requires to support 200Mhz refclk, we need to
827 * revisit this because n may not 1 anymore.
829 clock.n = 1, clock.m1 = 2;
830 target *= 5; /* fast clock */
832 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
833 for (clock.p2 = limit->p2.p2_fast;
834 clock.p2 >= limit->p2.p2_slow;
835 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
837 clock.p = clock.p1 * clock.p2;
839 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
840 clock.n) << 22, refclk * clock.m1);
842 if (m2 > INT_MAX/clock.m1)
847 chv_clock(refclk, &clock);
849 if (!intel_PLL_is_valid(dev, limit, &clock))
852 /* based on hardware requirement, prefer bigger p
854 if (clock.p > best_clock->p) {
864 bool intel_crtc_active(struct drm_crtc *crtc)
866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
868 /* Be paranoid as we can arrive here with only partial
869 * state retrieved from the hardware during setup.
871 * We can ditch the adjusted_mode.crtc_clock check as soon
872 * as Haswell has gained clock readout/fastboot support.
874 * We can ditch the crtc->primary->fb check as soon as we can
875 * properly reconstruct framebuffers.
877 return intel_crtc->active && crtc->primary->fb &&
878 intel_crtc->config.adjusted_mode.crtc_clock;
881 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
884 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887 return intel_crtc->config.cpu_transcoder;
890 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
892 struct drm_i915_private *dev_priv = dev->dev_private;
893 u32 reg = PIPEDSL(pipe);
898 line_mask = DSL_LINEMASK_GEN2;
900 line_mask = DSL_LINEMASK_GEN3;
902 line1 = I915_READ(reg) & line_mask;
904 line2 = I915_READ(reg) & line_mask;
906 return line1 == line2;
910 * intel_wait_for_pipe_off - wait for pipe to turn off
911 * @crtc: crtc whose pipe to wait for
913 * After disabling a pipe, we can't wait for vblank in the usual way,
914 * spinning on the vblank interrupt status bit, since we won't actually
915 * see an interrupt when the pipe is disabled.
918 * wait for the pipe register state bit to turn off
921 * wait for the display line value to settle (it usually
922 * ends up stopping at the start of the next frame).
925 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
927 struct drm_device *dev = crtc->base.dev;
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
930 enum pipe pipe = crtc->pipe;
932 if (INTEL_INFO(dev)->gen >= 4) {
933 int reg = PIPECONF(cpu_transcoder);
935 /* Wait for the Pipe State to go off */
936 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
938 WARN(1, "pipe_off wait timed out\n");
940 /* Wait for the display line to settle */
941 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
942 WARN(1, "pipe_off wait timed out\n");
947 * ibx_digital_port_connected - is the specified port connected?
948 * @dev_priv: i915 private structure
949 * @port: the port to test
951 * Returns true if @port is connected, false otherwise.
953 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
954 struct intel_digital_port *port)
958 if (HAS_PCH_IBX(dev_priv->dev)) {
959 switch (port->port) {
961 bit = SDE_PORTB_HOTPLUG;
964 bit = SDE_PORTC_HOTPLUG;
967 bit = SDE_PORTD_HOTPLUG;
973 switch (port->port) {
975 bit = SDE_PORTB_HOTPLUG_CPT;
978 bit = SDE_PORTC_HOTPLUG_CPT;
981 bit = SDE_PORTD_HOTPLUG_CPT;
988 return I915_READ(SDEISR) & bit;
991 static const char *state_string(bool enabled)
993 return enabled ? "on" : "off";
996 /* Only for pre-ILK configs */
997 void assert_pll(struct drm_i915_private *dev_priv,
998 enum pipe pipe, bool state)
1005 val = I915_READ(reg);
1006 cur_state = !!(val & DPLL_VCO_ENABLE);
1007 WARN(cur_state != state,
1008 "PLL state assertion failure (expected %s, current %s)\n",
1009 state_string(state), state_string(cur_state));
1012 /* XXX: the dsi pll is shared between MIPI DSI ports */
1013 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1018 mutex_lock(&dev_priv->dpio_lock);
1019 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1020 mutex_unlock(&dev_priv->dpio_lock);
1022 cur_state = val & DSI_PLL_VCO_EN;
1023 WARN(cur_state != state,
1024 "DSI PLL state assertion failure (expected %s, current %s)\n",
1025 state_string(state), state_string(cur_state));
1027 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1028 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1030 struct intel_shared_dpll *
1031 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1033 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1035 if (crtc->config.shared_dpll < 0)
1038 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1042 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1043 struct intel_shared_dpll *pll,
1047 struct intel_dpll_hw_state hw_state;
1050 "asserting DPLL %s with no DPLL\n", state_string(state)))
1053 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1054 WARN(cur_state != state,
1055 "%s assertion failure (expected %s, current %s)\n",
1056 pll->name, state_string(state), state_string(cur_state));
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, bool state)
1065 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068 if (HAS_DDI(dev_priv->dev)) {
1069 /* DDI does not have a specific FDI_TX register */
1070 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1071 val = I915_READ(reg);
1072 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074 reg = FDI_TX_CTL(pipe);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & FDI_TX_ENABLE);
1078 WARN(cur_state != state,
1079 "FDI TX state assertion failure (expected %s, current %s)\n",
1080 state_string(state), state_string(cur_state));
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1092 reg = FDI_RX_CTL(pipe);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & FDI_RX_ENABLE);
1095 WARN(cur_state != state,
1096 "FDI RX state assertion failure (expected %s, current %s)\n",
1097 state_string(state), state_string(cur_state));
1099 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1100 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1102 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1108 /* ILK FDI PLL is always enabled */
1109 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1112 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1113 if (HAS_DDI(dev_priv->dev))
1116 reg = FDI_TX_CTL(pipe);
1117 val = I915_READ(reg);
1118 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1121 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1128 reg = FDI_RX_CTL(pipe);
1129 val = I915_READ(reg);
1130 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1131 WARN(cur_state != state,
1132 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1136 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1139 struct drm_device *dev = dev_priv->dev;
1142 enum pipe panel_pipe = PIPE_A;
1145 if (WARN_ON(HAS_DDI(dev)))
1148 if (HAS_PCH_SPLIT(dev)) {
1151 pp_reg = PCH_PP_CONTROL;
1152 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1154 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1155 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1156 panel_pipe = PIPE_B;
1157 /* XXX: else fix for eDP */
1158 } else if (IS_VALLEYVIEW(dev)) {
1159 /* presumably write lock depends on pipe, not port select */
1160 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1163 pp_reg = PP_CONTROL;
1164 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1165 panel_pipe = PIPE_B;
1168 val = I915_READ(pp_reg);
1169 if (!(val & PANEL_POWER_ON) ||
1170 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1173 WARN(panel_pipe == pipe && locked,
1174 "panel assertion failure, pipe %c regs locked\n",
1178 static void assert_cursor(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
1181 struct drm_device *dev = dev_priv->dev;
1184 if (IS_845G(dev) || IS_I865G(dev))
1185 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1187 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1189 WARN(cur_state != state,
1190 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191 pipe_name(pipe), state_string(state), state_string(cur_state));
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, bool state)
1202 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1205 /* if we need the pipe quirk it must be always on */
1206 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1207 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1210 if (!intel_display_power_is_enabled(dev_priv,
1211 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1214 reg = PIPECONF(cpu_transcoder);
1215 val = I915_READ(reg);
1216 cur_state = !!(val & PIPECONF_ENABLE);
1219 WARN(cur_state != state,
1220 "pipe %c assertion failure (expected %s, current %s)\n",
1221 pipe_name(pipe), state_string(state), state_string(cur_state));
1224 static void assert_plane(struct drm_i915_private *dev_priv,
1225 enum plane plane, bool state)
1231 reg = DSPCNTR(plane);
1232 val = I915_READ(reg);
1233 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1234 WARN(cur_state != state,
1235 "plane %c assertion failure (expected %s, current %s)\n",
1236 plane_name(plane), state_string(state), state_string(cur_state));
1239 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1240 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1245 struct drm_device *dev = dev_priv->dev;
1250 /* Primary planes are fixed to pipes on gen4+ */
1251 if (INTEL_INFO(dev)->gen >= 4) {
1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN(val & DISPLAY_PLANE_ENABLE,
1255 "plane %c assertion failure, should be disabled but not\n",
1260 /* Need to check both planes against the pipe */
1261 for_each_pipe(dev_priv, i) {
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
1272 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1275 struct drm_device *dev = dev_priv->dev;
1279 if (INTEL_INFO(dev)->gen >= 9) {
1280 for_each_sprite(pipe, sprite) {
1281 val = I915_READ(PLANE_CTL(pipe, sprite));
1282 WARN(val & PLANE_CTL_ENABLE,
1283 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1284 sprite, pipe_name(pipe));
1286 } else if (IS_VALLEYVIEW(dev)) {
1287 for_each_sprite(pipe, sprite) {
1288 reg = SPCNTR(pipe, sprite);
1289 val = I915_READ(reg);
1290 WARN(val & SP_ENABLE,
1291 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1292 sprite_name(pipe, sprite), pipe_name(pipe));
1294 } else if (INTEL_INFO(dev)->gen >= 7) {
1296 val = I915_READ(reg);
1297 WARN(val & SPRITE_ENABLE,
1298 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1299 plane_name(pipe), pipe_name(pipe));
1300 } else if (INTEL_INFO(dev)->gen >= 5) {
1301 reg = DVSCNTR(pipe);
1302 val = I915_READ(reg);
1303 WARN(val & DVS_ENABLE,
1304 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1305 plane_name(pipe), pipe_name(pipe));
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1311 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312 drm_crtc_vblank_put(crtc);
1315 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1320 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1322 val = I915_READ(PCH_DREF_CONTROL);
1323 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1324 DREF_SUPERSPREAD_SOURCE_MASK));
1325 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1328 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1335 reg = PCH_TRANSCONF(pipe);
1336 val = I915_READ(reg);
1337 enabled = !!(val & TRANS_ENABLE);
1339 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1343 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 port_sel, u32 val)
1346 if ((val & DP_PORT_EN) == 0)
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1351 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1352 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1354 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1355 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1358 if ((val & DP_PIPE_MASK) != (pipe << 30))
1364 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, u32 val)
1367 if ((val & SDVO_ENABLE) == 0)
1370 if (HAS_PCH_CPT(dev_priv->dev)) {
1371 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1373 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1374 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1377 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1383 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, u32 val)
1386 if ((val & LVDS_PORT_EN) == 0)
1389 if (HAS_PCH_CPT(dev_priv->dev)) {
1390 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1393 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1399 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe, u32 val)
1402 if ((val & ADPA_DAC_ENABLE) == 0)
1404 if (HAS_PCH_CPT(dev_priv->dev)) {
1405 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1408 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1414 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1415 enum pipe pipe, int reg, u32 port_sel)
1417 u32 val = I915_READ(reg);
1418 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1419 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1420 reg, pipe_name(pipe));
1422 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1423 && (val & DP_PIPEB_SELECT),
1424 "IBX PCH dp port still using transcoder B\n");
1427 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, int reg)
1430 u32 val = I915_READ(reg);
1431 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1432 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1433 reg, pipe_name(pipe));
1435 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1436 && (val & SDVO_PIPE_B_SELECT),
1437 "IBX PCH hdmi port still using transcoder B\n");
1440 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1446 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1447 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1448 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1451 val = I915_READ(reg);
1452 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1453 "PCH VGA enabled on transcoder %c, should be disabled\n",
1457 val = I915_READ(reg);
1458 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1459 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1462 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1463 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1464 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1467 static void intel_init_dpio(struct drm_device *dev)
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1471 if (!IS_VALLEYVIEW(dev))
1475 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1476 * CHV x1 PHY (DP/HDMI D)
1477 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1479 if (IS_CHERRYVIEW(dev)) {
1480 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1481 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1483 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1487 static void vlv_enable_pll(struct intel_crtc *crtc)
1489 struct drm_device *dev = crtc->base.dev;
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491 int reg = DPLL(crtc->pipe);
1492 u32 dpll = crtc->config.dpll_hw_state.dpll;
1494 assert_pipe_disabled(dev_priv, crtc->pipe);
1496 /* No really, not for ILK+ */
1497 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1499 /* PLL is protected by panel, make sure we can write it */
1500 if (IS_MOBILE(dev_priv->dev))
1501 assert_panel_unlocked(dev_priv, crtc->pipe);
1503 I915_WRITE(reg, dpll);
1507 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1508 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1510 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1511 POSTING_READ(DPLL_MD(crtc->pipe));
1513 /* We do this three times for luck */
1514 I915_WRITE(reg, dpll);
1516 udelay(150); /* wait for warmup */
1517 I915_WRITE(reg, dpll);
1519 udelay(150); /* wait for warmup */
1520 I915_WRITE(reg, dpll);
1522 udelay(150); /* wait for warmup */
1525 static void chv_enable_pll(struct intel_crtc *crtc)
1527 struct drm_device *dev = crtc->base.dev;
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529 int pipe = crtc->pipe;
1530 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1533 assert_pipe_disabled(dev_priv, crtc->pipe);
1535 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1537 mutex_lock(&dev_priv->dpio_lock);
1539 /* Enable back the 10bit clock to display controller */
1540 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541 tmp |= DPIO_DCLKP_EN;
1542 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1545 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1550 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1552 /* Check PLL is locked */
1553 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554 DRM_ERROR("PLL %d failed to lock\n", pipe);
1556 /* not sure when this should be written */
1557 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1558 POSTING_READ(DPLL_MD(pipe));
1560 mutex_unlock(&dev_priv->dpio_lock);
1563 static int intel_num_dvo_pipes(struct drm_device *dev)
1565 struct intel_crtc *crtc;
1568 for_each_intel_crtc(dev, crtc)
1569 count += crtc->active &&
1570 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1575 static void i9xx_enable_pll(struct intel_crtc *crtc)
1577 struct drm_device *dev = crtc->base.dev;
1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579 int reg = DPLL(crtc->pipe);
1580 u32 dpll = crtc->config.dpll_hw_state.dpll;
1582 assert_pipe_disabled(dev_priv, crtc->pipe);
1584 /* No really, not for ILK+ */
1585 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1587 /* PLL is protected by panel, make sure we can write it */
1588 if (IS_MOBILE(dev) && !IS_I830(dev))
1589 assert_panel_unlocked(dev_priv, crtc->pipe);
1591 /* Enable DVO 2x clock on both PLLs if necessary */
1592 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1594 * It appears to be important that we don't enable this
1595 * for the current pipe before otherwise configuring the
1596 * PLL. No idea how this should be handled if multiple
1597 * DVO outputs are enabled simultaneosly.
1599 dpll |= DPLL_DVO_2X_MODE;
1600 I915_WRITE(DPLL(!crtc->pipe),
1601 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1604 /* Wait for the clocks to stabilize. */
1608 if (INTEL_INFO(dev)->gen >= 4) {
1609 I915_WRITE(DPLL_MD(crtc->pipe),
1610 crtc->config.dpll_hw_state.dpll_md);
1612 /* The pixel multiplier can only be updated once the
1613 * DPLL is enabled and the clocks are stable.
1615 * So write it again.
1617 I915_WRITE(reg, dpll);
1620 /* We do this three times for luck */
1621 I915_WRITE(reg, dpll);
1623 udelay(150); /* wait for warmup */
1624 I915_WRITE(reg, dpll);
1626 udelay(150); /* wait for warmup */
1627 I915_WRITE(reg, dpll);
1629 udelay(150); /* wait for warmup */
1633 * i9xx_disable_pll - disable a PLL
1634 * @dev_priv: i915 private structure
1635 * @pipe: pipe PLL to disable
1637 * Disable the PLL for @pipe, making sure the pipe is off first.
1639 * Note! This is for pre-ILK only.
1641 static void i9xx_disable_pll(struct intel_crtc *crtc)
1643 struct drm_device *dev = crtc->base.dev;
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 enum pipe pipe = crtc->pipe;
1647 /* Disable DVO 2x clock on both PLLs if necessary */
1649 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1650 intel_num_dvo_pipes(dev) == 1) {
1651 I915_WRITE(DPLL(PIPE_B),
1652 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1653 I915_WRITE(DPLL(PIPE_A),
1654 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1657 /* Don't disable pipe or pipe PLLs if needed */
1658 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1659 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1662 /* Make sure the pipe isn't still relying on us */
1663 assert_pipe_disabled(dev_priv, pipe);
1665 I915_WRITE(DPLL(pipe), 0);
1666 POSTING_READ(DPLL(pipe));
1669 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1673 /* Make sure the pipe isn't still relying on us */
1674 assert_pipe_disabled(dev_priv, pipe);
1677 * Leave integrated clock source and reference clock enabled for pipe B.
1678 * The latter is needed for VGA hotplug / manual detection.
1681 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1682 I915_WRITE(DPLL(pipe), val);
1683 POSTING_READ(DPLL(pipe));
1687 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1689 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv, pipe);
1695 /* Set PLL en = 0 */
1696 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1698 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1699 I915_WRITE(DPLL(pipe), val);
1700 POSTING_READ(DPLL(pipe));
1702 mutex_lock(&dev_priv->dpio_lock);
1704 /* Disable 10bit clock to display controller */
1705 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1706 val &= ~DPIO_DCLKP_EN;
1707 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1709 /* disable left/right clock distribution */
1710 if (pipe != PIPE_B) {
1711 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1712 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1713 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1716 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1717 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1720 mutex_unlock(&dev_priv->dpio_lock);
1723 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1724 struct intel_digital_port *dport)
1729 switch (dport->port) {
1731 port_mask = DPLL_PORTB_READY_MASK;
1735 port_mask = DPLL_PORTC_READY_MASK;
1739 port_mask = DPLL_PORTD_READY_MASK;
1740 dpll_reg = DPIO_PHY_STATUS;
1746 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1747 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1748 port_name(dport->port), I915_READ(dpll_reg));
1751 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1753 struct drm_device *dev = crtc->base.dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
1755 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1757 if (WARN_ON(pll == NULL))
1760 WARN_ON(!pll->refcount);
1761 if (pll->active == 0) {
1762 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1764 assert_shared_dpll_disabled(dev_priv, pll);
1766 pll->mode_set(dev_priv, pll);
1771 * intel_enable_shared_dpll - enable PCH PLL
1772 * @dev_priv: i915 private structure
1773 * @pipe: pipe PLL to enable
1775 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1776 * drives the transcoder clock.
1778 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1780 struct drm_device *dev = crtc->base.dev;
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1784 if (WARN_ON(pll == NULL))
1787 if (WARN_ON(pll->refcount == 0))
1790 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1791 pll->name, pll->active, pll->on,
1792 crtc->base.base.id);
1794 if (pll->active++) {
1796 assert_shared_dpll_enabled(dev_priv, pll);
1801 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1803 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1804 pll->enable(dev_priv, pll);
1808 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1810 struct drm_device *dev = crtc->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1814 /* PCH only available on ILK+ */
1815 BUG_ON(INTEL_INFO(dev)->gen < 5);
1816 if (WARN_ON(pll == NULL))
1819 if (WARN_ON(pll->refcount == 0))
1822 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1823 pll->name, pll->active, pll->on,
1824 crtc->base.base.id);
1826 if (WARN_ON(pll->active == 0)) {
1827 assert_shared_dpll_disabled(dev_priv, pll);
1831 assert_shared_dpll_enabled(dev_priv, pll);
1836 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1837 pll->disable(dev_priv, pll);
1840 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1843 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 struct drm_device *dev = dev_priv->dev;
1847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849 uint32_t reg, val, pipeconf_val;
1851 /* PCH only available on ILK+ */
1852 BUG_ON(!HAS_PCH_SPLIT(dev));
1854 /* Make sure PCH DPLL is enabled */
1855 assert_shared_dpll_enabled(dev_priv,
1856 intel_crtc_to_shared_dpll(intel_crtc));
1858 /* FDI must be feeding us bits for PCH ports */
1859 assert_fdi_tx_enabled(dev_priv, pipe);
1860 assert_fdi_rx_enabled(dev_priv, pipe);
1862 if (HAS_PCH_CPT(dev)) {
1863 /* Workaround: Set the timing override bit before enabling the
1864 * pch transcoder. */
1865 reg = TRANS_CHICKEN2(pipe);
1866 val = I915_READ(reg);
1867 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1868 I915_WRITE(reg, val);
1871 reg = PCH_TRANSCONF(pipe);
1872 val = I915_READ(reg);
1873 pipeconf_val = I915_READ(PIPECONF(pipe));
1875 if (HAS_PCH_IBX(dev_priv->dev)) {
1877 * make the BPC in transcoder be consistent with
1878 * that in pipeconf reg.
1880 val &= ~PIPECONF_BPC_MASK;
1881 val |= pipeconf_val & PIPECONF_BPC_MASK;
1884 val &= ~TRANS_INTERLACE_MASK;
1885 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1886 if (HAS_PCH_IBX(dev_priv->dev) &&
1887 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1888 val |= TRANS_LEGACY_INTERLACED_ILK;
1890 val |= TRANS_INTERLACED;
1892 val |= TRANS_PROGRESSIVE;
1894 I915_WRITE(reg, val | TRANS_ENABLE);
1895 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1896 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1899 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900 enum transcoder cpu_transcoder)
1902 u32 val, pipeconf_val;
1904 /* PCH only available on ILK+ */
1905 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1907 /* FDI must be feeding us bits for PCH ports */
1908 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1909 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1911 /* Workaround: set timing override bit. */
1912 val = I915_READ(_TRANSA_CHICKEN2);
1913 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1914 I915_WRITE(_TRANSA_CHICKEN2, val);
1917 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1919 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1920 PIPECONF_INTERLACED_ILK)
1921 val |= TRANS_INTERLACED;
1923 val |= TRANS_PROGRESSIVE;
1925 I915_WRITE(LPT_TRANSCONF, val);
1926 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1927 DRM_ERROR("Failed to enable PCH transcoder\n");
1930 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1933 struct drm_device *dev = dev_priv->dev;
1936 /* FDI relies on the transcoder */
1937 assert_fdi_tx_disabled(dev_priv, pipe);
1938 assert_fdi_rx_disabled(dev_priv, pipe);
1940 /* Ports must be off as well */
1941 assert_pch_ports_disabled(dev_priv, pipe);
1943 reg = PCH_TRANSCONF(pipe);
1944 val = I915_READ(reg);
1945 val &= ~TRANS_ENABLE;
1946 I915_WRITE(reg, val);
1947 /* wait for PCH transcoder off, transcoder state */
1948 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1949 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1951 if (!HAS_PCH_IBX(dev)) {
1952 /* Workaround: Clear the timing override chicken bit again. */
1953 reg = TRANS_CHICKEN2(pipe);
1954 val = I915_READ(reg);
1955 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1956 I915_WRITE(reg, val);
1960 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1964 val = I915_READ(LPT_TRANSCONF);
1965 val &= ~TRANS_ENABLE;
1966 I915_WRITE(LPT_TRANSCONF, val);
1967 /* wait for PCH transcoder off, transcoder state */
1968 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1969 DRM_ERROR("Failed to disable PCH transcoder\n");
1971 /* Workaround: clear timing override bit. */
1972 val = I915_READ(_TRANSA_CHICKEN2);
1973 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1974 I915_WRITE(_TRANSA_CHICKEN2, val);
1978 * intel_enable_pipe - enable a pipe, asserting requirements
1979 * @crtc: crtc responsible for the pipe
1981 * Enable @crtc's pipe, making sure that various hardware specific requirements
1982 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1984 static void intel_enable_pipe(struct intel_crtc *crtc)
1986 struct drm_device *dev = crtc->base.dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 enum pipe pipe = crtc->pipe;
1989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1991 enum pipe pch_transcoder;
1995 assert_planes_disabled(dev_priv, pipe);
1996 assert_cursor_disabled(dev_priv, pipe);
1997 assert_sprites_disabled(dev_priv, pipe);
1999 if (HAS_PCH_LPT(dev_priv->dev))
2000 pch_transcoder = TRANSCODER_A;
2002 pch_transcoder = pipe;
2005 * A pipe without a PLL won't actually be able to drive bits from
2006 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2009 if (!HAS_PCH_SPLIT(dev_priv->dev))
2010 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2011 assert_dsi_pll_enabled(dev_priv);
2013 assert_pll_enabled(dev_priv, pipe);
2015 if (crtc->config.has_pch_encoder) {
2016 /* if driving the PCH, we need FDI enabled */
2017 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2018 assert_fdi_tx_pll_enabled(dev_priv,
2019 (enum pipe) cpu_transcoder);
2021 /* FIXME: assert CPU port conditions for SNB+ */
2024 reg = PIPECONF(cpu_transcoder);
2025 val = I915_READ(reg);
2026 if (val & PIPECONF_ENABLE) {
2027 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2028 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2032 I915_WRITE(reg, val | PIPECONF_ENABLE);
2037 * intel_disable_pipe - disable a pipe, asserting requirements
2038 * @crtc: crtc whose pipes is to be disabled
2040 * Disable the pipe of @crtc, making sure that various hardware
2041 * specific requirements are met, if applicable, e.g. plane
2042 * disabled, panel fitter off, etc.
2044 * Will wait until the pipe has shut down before returning.
2046 static void intel_disable_pipe(struct intel_crtc *crtc)
2048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2049 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2050 enum pipe pipe = crtc->pipe;
2055 * Make sure planes won't keep trying to pump pixels to us,
2056 * or we might hang the display.
2058 assert_planes_disabled(dev_priv, pipe);
2059 assert_cursor_disabled(dev_priv, pipe);
2060 assert_sprites_disabled(dev_priv, pipe);
2062 reg = PIPECONF(cpu_transcoder);
2063 val = I915_READ(reg);
2064 if ((val & PIPECONF_ENABLE) == 0)
2068 * Double wide has implications for planes
2069 * so best keep it disabled when not needed.
2071 if (crtc->config.double_wide)
2072 val &= ~PIPECONF_DOUBLE_WIDE;
2074 /* Don't disable pipe or pipe PLLs if needed */
2075 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2076 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2077 val &= ~PIPECONF_ENABLE;
2079 I915_WRITE(reg, val);
2080 if ((val & PIPECONF_ENABLE) == 0)
2081 intel_wait_for_pipe_off(crtc);
2085 * Plane regs are double buffered, going from enabled->disabled needs a
2086 * trigger in order to latch. The display address reg provides this.
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2091 struct drm_device *dev = dev_priv->dev;
2092 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2094 I915_WRITE(reg, I915_READ(reg));
2099 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100 * @plane: plane to be enabled
2101 * @crtc: crtc for the plane
2103 * Enable @plane on @crtc, making sure that the pipe is running first.
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106 struct drm_crtc *crtc)
2108 struct drm_device *dev = plane->dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2115 if (intel_crtc->primary_enabled)
2118 intel_crtc->primary_enabled = true;
2120 dev_priv->display.update_primary_plane(crtc, plane->fb,
2124 * BDW signals flip done immediately if the plane
2125 * is disabled, even if the plane enable is already
2126 * armed to occur at the next vblank :(
2128 if (IS_BROADWELL(dev))
2129 intel_wait_for_vblank(dev, intel_crtc->pipe);
2133 * intel_disable_primary_hw_plane - disable the primary hardware plane
2134 * @plane: plane to be disabled
2135 * @crtc: crtc for the plane
2137 * Disable @plane on @crtc, making sure that the pipe is running first.
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140 struct drm_crtc *crtc)
2142 struct drm_device *dev = plane->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2148 if (!intel_crtc->primary_enabled)
2151 intel_crtc->primary_enabled = false;
2153 dev_priv->display.update_primary_plane(crtc, plane->fb,
2157 static bool need_vtd_wa(struct drm_device *dev)
2159 #ifdef CONFIG_INTEL_IOMMU
2160 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2170 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171 return ALIGN(height, tile_height);
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176 struct drm_i915_gem_object *obj,
2177 struct intel_engine_cs *pipelined)
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2183 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2185 switch (obj->tiling_mode) {
2186 case I915_TILING_NONE:
2187 if (INTEL_INFO(dev)->gen >= 9)
2188 alignment = 256 * 1024;
2189 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2190 alignment = 128 * 1024;
2191 else if (INTEL_INFO(dev)->gen >= 4)
2192 alignment = 4 * 1024;
2194 alignment = 64 * 1024;
2197 if (INTEL_INFO(dev)->gen >= 9)
2198 alignment = 256 * 1024;
2200 /* pin() will align the object as required by fence */
2205 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2211 /* Note that the w/a also requires 64 PTE of padding following the
2212 * bo. We currently fill all unused PTE with the shadow page and so
2213 * we should always have valid PTE following the scanout preventing
2216 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2217 alignment = 256 * 1024;
2220 * Global gtt pte registers are special registers which actually forward
2221 * writes to a chunk of system memory. Which means that there is no risk
2222 * that the register values disappear as soon as we call
2223 * intel_runtime_pm_put(), so it is correct to wrap only the
2224 * pin/unpin/fence and not more.
2226 intel_runtime_pm_get(dev_priv);
2228 dev_priv->mm.interruptible = false;
2229 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2231 goto err_interruptible;
2233 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234 * fence, whereas 965+ only requires a fence if using
2235 * framebuffer compression. For simplicity, we always install
2236 * a fence as the cost is not that onerous.
2238 ret = i915_gem_object_get_fence(obj);
2242 i915_gem_object_pin_fence(obj);
2244 dev_priv->mm.interruptible = true;
2245 intel_runtime_pm_put(dev_priv);
2249 i915_gem_object_unpin_from_display_plane(obj);
2251 dev_priv->mm.interruptible = true;
2252 intel_runtime_pm_put(dev_priv);
2256 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2258 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2260 i915_gem_object_unpin_fence(obj);
2261 i915_gem_object_unpin_from_display_plane(obj);
2264 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2265 * is assumed to be a power-of-two. */
2266 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2267 unsigned int tiling_mode,
2271 if (tiling_mode != I915_TILING_NONE) {
2272 unsigned int tile_rows, tiles;
2277 tiles = *x / (512/cpp);
2280 return tile_rows * pitch * 8 + tiles * 4096;
2282 unsigned int offset;
2284 offset = *y * pitch + *x * cpp;
2286 *x = (offset & 4095) / cpp;
2287 return offset & -4096;
2291 int intel_format_to_fourcc(int format)
2294 case DISPPLANE_8BPP:
2295 return DRM_FORMAT_C8;
2296 case DISPPLANE_BGRX555:
2297 return DRM_FORMAT_XRGB1555;
2298 case DISPPLANE_BGRX565:
2299 return DRM_FORMAT_RGB565;
2301 case DISPPLANE_BGRX888:
2302 return DRM_FORMAT_XRGB8888;
2303 case DISPPLANE_RGBX888:
2304 return DRM_FORMAT_XBGR8888;
2305 case DISPPLANE_BGRX101010:
2306 return DRM_FORMAT_XRGB2101010;
2307 case DISPPLANE_RGBX101010:
2308 return DRM_FORMAT_XBGR2101010;
2312 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2313 struct intel_plane_config *plane_config)
2315 struct drm_device *dev = crtc->base.dev;
2316 struct drm_i915_gem_object *obj = NULL;
2317 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2318 u32 base = plane_config->base;
2320 if (plane_config->size == 0)
2323 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2324 plane_config->size);
2328 if (plane_config->tiled) {
2329 obj->tiling_mode = I915_TILING_X;
2330 obj->stride = crtc->base.primary->fb->pitches[0];
2333 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2334 mode_cmd.width = crtc->base.primary->fb->width;
2335 mode_cmd.height = crtc->base.primary->fb->height;
2336 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2338 mutex_lock(&dev->struct_mutex);
2340 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2342 DRM_DEBUG_KMS("intel fb init failed\n");
2346 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2347 mutex_unlock(&dev->struct_mutex);
2349 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2353 drm_gem_object_unreference(&obj->base);
2354 mutex_unlock(&dev->struct_mutex);
2358 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2359 struct intel_plane_config *plane_config)
2361 struct drm_device *dev = intel_crtc->base.dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *i;
2365 struct drm_i915_gem_object *obj;
2367 if (!intel_crtc->base.primary->fb)
2370 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2373 kfree(intel_crtc->base.primary->fb);
2374 intel_crtc->base.primary->fb = NULL;
2377 * Failed to alloc the obj, check to see if we should share
2378 * an fb with another CRTC instead
2380 for_each_crtc(dev, c) {
2381 i = to_intel_crtc(c);
2383 if (c == &intel_crtc->base)
2389 obj = intel_fb_obj(c->primary->fb);
2393 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2394 if (obj->tiling_mode != I915_TILING_NONE)
2395 dev_priv->preserve_bios_swizzle = true;
2397 drm_framebuffer_reference(c->primary->fb);
2398 intel_crtc->base.primary->fb = c->primary->fb;
2399 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2405 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2406 struct drm_framebuffer *fb,
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 struct drm_i915_gem_object *obj;
2413 int plane = intel_crtc->plane;
2414 unsigned long linear_offset;
2416 u32 reg = DSPCNTR(plane);
2419 if (!intel_crtc->primary_enabled) {
2421 if (INTEL_INFO(dev)->gen >= 4)
2422 I915_WRITE(DSPSURF(plane), 0);
2424 I915_WRITE(DSPADDR(plane), 0);
2429 obj = intel_fb_obj(fb);
2430 if (WARN_ON(obj == NULL))
2433 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2435 dspcntr = DISPPLANE_GAMMA_ENABLE;
2437 dspcntr |= DISPLAY_PLANE_ENABLE;
2439 if (INTEL_INFO(dev)->gen < 4) {
2440 if (intel_crtc->pipe == PIPE_B)
2441 dspcntr |= DISPPLANE_SEL_PIPE_B;
2443 /* pipesrc and dspsize control the size that is scaled from,
2444 * which should always be the user's requested size.
2446 I915_WRITE(DSPSIZE(plane),
2447 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2448 (intel_crtc->config.pipe_src_w - 1));
2449 I915_WRITE(DSPPOS(plane), 0);
2452 switch (fb->pixel_format) {
2454 dspcntr |= DISPPLANE_8BPP;
2456 case DRM_FORMAT_XRGB1555:
2457 case DRM_FORMAT_ARGB1555:
2458 dspcntr |= DISPPLANE_BGRX555;
2460 case DRM_FORMAT_RGB565:
2461 dspcntr |= DISPPLANE_BGRX565;
2463 case DRM_FORMAT_XRGB8888:
2464 case DRM_FORMAT_ARGB8888:
2465 dspcntr |= DISPPLANE_BGRX888;
2467 case DRM_FORMAT_XBGR8888:
2468 case DRM_FORMAT_ABGR8888:
2469 dspcntr |= DISPPLANE_RGBX888;
2471 case DRM_FORMAT_XRGB2101010:
2472 case DRM_FORMAT_ARGB2101010:
2473 dspcntr |= DISPPLANE_BGRX101010;
2475 case DRM_FORMAT_XBGR2101010:
2476 case DRM_FORMAT_ABGR2101010:
2477 dspcntr |= DISPPLANE_RGBX101010;
2483 if (INTEL_INFO(dev)->gen >= 4 &&
2484 obj->tiling_mode != I915_TILING_NONE)
2485 dspcntr |= DISPPLANE_TILED;
2488 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2490 linear_offset = y * fb->pitches[0] + x * pixel_size;
2492 if (INTEL_INFO(dev)->gen >= 4) {
2493 intel_crtc->dspaddr_offset =
2494 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2497 linear_offset -= intel_crtc->dspaddr_offset;
2499 intel_crtc->dspaddr_offset = linear_offset;
2502 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2503 dspcntr |= DISPPLANE_ROTATE_180;
2505 x += (intel_crtc->config.pipe_src_w - 1);
2506 y += (intel_crtc->config.pipe_src_h - 1);
2508 /* Finding the last pixel of the last line of the display
2509 data and adding to linear_offset*/
2511 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2512 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2515 I915_WRITE(reg, dspcntr);
2517 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2520 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2521 if (INTEL_INFO(dev)->gen >= 4) {
2522 I915_WRITE(DSPSURF(plane),
2523 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2524 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525 I915_WRITE(DSPLINOFF(plane), linear_offset);
2527 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2531 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2532 struct drm_framebuffer *fb,
2535 struct drm_device *dev = crtc->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2538 struct drm_i915_gem_object *obj;
2539 int plane = intel_crtc->plane;
2540 unsigned long linear_offset;
2542 u32 reg = DSPCNTR(plane);
2545 if (!intel_crtc->primary_enabled) {
2547 I915_WRITE(DSPSURF(plane), 0);
2552 obj = intel_fb_obj(fb);
2553 if (WARN_ON(obj == NULL))
2556 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2558 dspcntr = DISPPLANE_GAMMA_ENABLE;
2560 dspcntr |= DISPLAY_PLANE_ENABLE;
2562 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2563 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2565 switch (fb->pixel_format) {
2567 dspcntr |= DISPPLANE_8BPP;
2569 case DRM_FORMAT_RGB565:
2570 dspcntr |= DISPPLANE_BGRX565;
2572 case DRM_FORMAT_XRGB8888:
2573 case DRM_FORMAT_ARGB8888:
2574 dspcntr |= DISPPLANE_BGRX888;
2576 case DRM_FORMAT_XBGR8888:
2577 case DRM_FORMAT_ABGR8888:
2578 dspcntr |= DISPPLANE_RGBX888;
2580 case DRM_FORMAT_XRGB2101010:
2581 case DRM_FORMAT_ARGB2101010:
2582 dspcntr |= DISPPLANE_BGRX101010;
2584 case DRM_FORMAT_XBGR2101010:
2585 case DRM_FORMAT_ABGR2101010:
2586 dspcntr |= DISPPLANE_RGBX101010;
2592 if (obj->tiling_mode != I915_TILING_NONE)
2593 dspcntr |= DISPPLANE_TILED;
2595 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2596 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2598 linear_offset = y * fb->pitches[0] + x * pixel_size;
2599 intel_crtc->dspaddr_offset =
2600 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2603 linear_offset -= intel_crtc->dspaddr_offset;
2604 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2605 dspcntr |= DISPPLANE_ROTATE_180;
2607 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2608 x += (intel_crtc->config.pipe_src_w - 1);
2609 y += (intel_crtc->config.pipe_src_h - 1);
2611 /* Finding the last pixel of the last line of the display
2612 data and adding to linear_offset*/
2614 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2615 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2619 I915_WRITE(reg, dspcntr);
2621 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2622 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2624 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2625 I915_WRITE(DSPSURF(plane),
2626 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2627 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2628 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2630 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2631 I915_WRITE(DSPLINOFF(plane), linear_offset);
2636 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2637 struct drm_framebuffer *fb,
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 struct intel_framebuffer *intel_fb;
2644 struct drm_i915_gem_object *obj;
2645 int pipe = intel_crtc->pipe;
2646 u32 plane_ctl, stride;
2648 if (!intel_crtc->primary_enabled) {
2649 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2650 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2651 POSTING_READ(PLANE_CTL(pipe, 0));
2655 plane_ctl = PLANE_CTL_ENABLE |
2656 PLANE_CTL_PIPE_GAMMA_ENABLE |
2657 PLANE_CTL_PIPE_CSC_ENABLE;
2659 switch (fb->pixel_format) {
2660 case DRM_FORMAT_RGB565:
2661 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2663 case DRM_FORMAT_XRGB8888:
2664 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2666 case DRM_FORMAT_XBGR8888:
2667 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2668 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2670 case DRM_FORMAT_XRGB2101010:
2671 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2673 case DRM_FORMAT_XBGR2101010:
2674 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2675 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2681 intel_fb = to_intel_framebuffer(fb);
2682 obj = intel_fb->obj;
2685 * The stride is either expressed as a multiple of 64 bytes chunks for
2686 * linear buffers or in number of tiles for tiled buffers.
2688 switch (obj->tiling_mode) {
2689 case I915_TILING_NONE:
2690 stride = fb->pitches[0] >> 6;
2693 plane_ctl |= PLANE_CTL_TILED_X;
2694 stride = fb->pitches[0] >> 9;
2700 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2701 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2702 plane_ctl |= PLANE_CTL_ROTATE_180;
2704 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2706 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2707 i915_gem_obj_ggtt_offset(obj),
2708 x, y, fb->width, fb->height,
2711 I915_WRITE(PLANE_POS(pipe, 0), 0);
2712 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2713 I915_WRITE(PLANE_SIZE(pipe, 0),
2714 (intel_crtc->config.pipe_src_h - 1) << 16 |
2715 (intel_crtc->config.pipe_src_w - 1));
2716 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2717 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2719 POSTING_READ(PLANE_SURF(pipe, 0));
2722 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2724 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2725 int x, int y, enum mode_set_atomic state)
2727 struct drm_device *dev = crtc->dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2730 if (dev_priv->display.disable_fbc)
2731 dev_priv->display.disable_fbc(dev);
2733 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2738 void intel_display_handle_reset(struct drm_device *dev)
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct drm_crtc *crtc;
2744 * Flips in the rings have been nuked by the reset,
2745 * so complete all pending flips so that user space
2746 * will get its events and not get stuck.
2748 * Also update the base address of all primary
2749 * planes to the the last fb to make sure we're
2750 * showing the correct fb after a reset.
2752 * Need to make two loops over the crtcs so that we
2753 * don't try to grab a crtc mutex before the
2754 * pending_flip_queue really got woken up.
2757 for_each_crtc(dev, crtc) {
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759 enum plane plane = intel_crtc->plane;
2761 intel_prepare_page_flip(dev, plane);
2762 intel_finish_page_flip_plane(dev, plane);
2765 for_each_crtc(dev, crtc) {
2766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 drm_modeset_lock(&crtc->mutex, NULL);
2770 * FIXME: Once we have proper support for primary planes (and
2771 * disabling them without disabling the entire crtc) allow again
2772 * a NULL crtc->primary->fb.
2774 if (intel_crtc->active && crtc->primary->fb)
2775 dev_priv->display.update_primary_plane(crtc,
2779 drm_modeset_unlock(&crtc->mutex);
2784 intel_finish_fb(struct drm_framebuffer *old_fb)
2786 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2787 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2788 bool was_interruptible = dev_priv->mm.interruptible;
2791 /* Big Hammer, we also need to ensure that any pending
2792 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2793 * current scanout is retired before unpinning the old
2796 * This should only fail upon a hung GPU, in which case we
2797 * can safely continue.
2799 dev_priv->mm.interruptible = false;
2800 ret = i915_gem_object_finish_gpu(obj);
2801 dev_priv->mm.interruptible = was_interruptible;
2806 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2808 struct drm_device *dev = crtc->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2813 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2814 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2817 spin_lock_irq(&dev->event_lock);
2818 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2819 spin_unlock_irq(&dev->event_lock);
2824 static void intel_update_pipe_size(struct intel_crtc *crtc)
2826 struct drm_device *dev = crtc->base.dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 const struct drm_display_mode *adjusted_mode;
2834 * Update pipe size and adjust fitter if needed: the reason for this is
2835 * that in compute_mode_changes we check the native mode (not the pfit
2836 * mode) to see if we can flip rather than do a full mode set. In the
2837 * fastboot case, we'll flip, but if we don't update the pipesrc and
2838 * pfit state, we'll end up with a big fb scanned out into the wrong
2841 * To fix this properly, we need to hoist the checks up into
2842 * compute_mode_changes (or above), check the actual pfit state and
2843 * whether the platform allows pfit disable with pipe active, and only
2844 * then update the pipesrc and pfit state, even on the flip path.
2847 adjusted_mode = &crtc->config.adjusted_mode;
2849 I915_WRITE(PIPESRC(crtc->pipe),
2850 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2851 (adjusted_mode->crtc_vdisplay - 1));
2852 if (!crtc->config.pch_pfit.enabled &&
2853 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2854 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2855 I915_WRITE(PF_CTL(crtc->pipe), 0);
2856 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2857 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2859 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2860 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2864 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2865 struct drm_framebuffer *fb)
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870 enum pipe pipe = intel_crtc->pipe;
2871 struct drm_framebuffer *old_fb = crtc->primary->fb;
2872 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2873 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2876 if (intel_crtc_has_pending_flip(crtc)) {
2877 DRM_ERROR("pipe is still busy with an old pageflip\n");
2883 DRM_ERROR("No FB bound\n");
2887 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2888 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2889 plane_name(intel_crtc->plane),
2890 INTEL_INFO(dev)->num_pipes);
2894 mutex_lock(&dev->struct_mutex);
2895 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2897 i915_gem_track_fb(old_obj, obj,
2898 INTEL_FRONTBUFFER_PRIMARY(pipe));
2899 mutex_unlock(&dev->struct_mutex);
2901 DRM_ERROR("pin & fence failed\n");
2905 intel_update_pipe_size(intel_crtc);
2907 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2909 if (intel_crtc->active)
2910 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2912 crtc->primary->fb = fb;
2917 if (intel_crtc->active && old_fb != fb)
2918 intel_wait_for_vblank(dev, intel_crtc->pipe);
2919 mutex_lock(&dev->struct_mutex);
2920 intel_unpin_fb_obj(old_obj);
2921 mutex_unlock(&dev->struct_mutex);
2924 mutex_lock(&dev->struct_mutex);
2925 intel_update_fbc(dev);
2926 mutex_unlock(&dev->struct_mutex);
2931 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936 int pipe = intel_crtc->pipe;
2939 /* enable normal train */
2940 reg = FDI_TX_CTL(pipe);
2941 temp = I915_READ(reg);
2942 if (IS_IVYBRIDGE(dev)) {
2943 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2944 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2946 temp &= ~FDI_LINK_TRAIN_NONE;
2947 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2949 I915_WRITE(reg, temp);
2951 reg = FDI_RX_CTL(pipe);
2952 temp = I915_READ(reg);
2953 if (HAS_PCH_CPT(dev)) {
2954 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2955 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2957 temp &= ~FDI_LINK_TRAIN_NONE;
2958 temp |= FDI_LINK_TRAIN_NONE;
2960 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2962 /* wait one idle pattern time */
2966 /* IVB wants error correction enabled */
2967 if (IS_IVYBRIDGE(dev))
2968 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2969 FDI_FE_ERRC_ENABLE);
2972 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2974 return crtc->base.enabled && crtc->active &&
2975 crtc->config.has_pch_encoder;
2978 static void ivb_modeset_global_resources(struct drm_device *dev)
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 struct intel_crtc *pipe_B_crtc =
2982 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2983 struct intel_crtc *pipe_C_crtc =
2984 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2988 * When everything is off disable fdi C so that we could enable fdi B
2989 * with all lanes. Note that we don't care about enabled pipes without
2990 * an enabled pch encoder.
2992 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2993 !pipe_has_enabled_pch(pipe_C_crtc)) {
2994 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2995 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2997 temp = I915_READ(SOUTH_CHICKEN1);
2998 temp &= ~FDI_BC_BIFURCATION_SELECT;
2999 DRM_DEBUG_KMS("disabling fdi C rx\n");
3000 I915_WRITE(SOUTH_CHICKEN1, temp);
3004 /* The FDI link training functions for ILK/Ibexpeak. */
3005 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3007 struct drm_device *dev = crtc->dev;
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010 int pipe = intel_crtc->pipe;
3011 u32 reg, temp, tries;
3013 /* FDI needs bits from pipe first */
3014 assert_pipe_enabled(dev_priv, pipe);
3016 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3018 reg = FDI_RX_IMR(pipe);
3019 temp = I915_READ(reg);
3020 temp &= ~FDI_RX_SYMBOL_LOCK;
3021 temp &= ~FDI_RX_BIT_LOCK;
3022 I915_WRITE(reg, temp);
3026 /* enable CPU FDI TX and PCH FDI RX */
3027 reg = FDI_TX_CTL(pipe);
3028 temp = I915_READ(reg);
3029 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3030 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3031 temp &= ~FDI_LINK_TRAIN_NONE;
3032 temp |= FDI_LINK_TRAIN_PATTERN_1;
3033 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3035 reg = FDI_RX_CTL(pipe);
3036 temp = I915_READ(reg);
3037 temp &= ~FDI_LINK_TRAIN_NONE;
3038 temp |= FDI_LINK_TRAIN_PATTERN_1;
3039 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3044 /* Ironlake workaround, enable clock pointer after FDI enable*/
3045 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3046 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3047 FDI_RX_PHASE_SYNC_POINTER_EN);
3049 reg = FDI_RX_IIR(pipe);
3050 for (tries = 0; tries < 5; tries++) {
3051 temp = I915_READ(reg);
3052 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3054 if ((temp & FDI_RX_BIT_LOCK)) {
3055 DRM_DEBUG_KMS("FDI train 1 done.\n");
3056 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3061 DRM_ERROR("FDI train 1 fail!\n");
3064 reg = FDI_TX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_2;
3068 I915_WRITE(reg, temp);
3070 reg = FDI_RX_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~FDI_LINK_TRAIN_NONE;
3073 temp |= FDI_LINK_TRAIN_PATTERN_2;
3074 I915_WRITE(reg, temp);
3079 reg = FDI_RX_IIR(pipe);
3080 for (tries = 0; tries < 5; tries++) {
3081 temp = I915_READ(reg);
3082 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3084 if (temp & FDI_RX_SYMBOL_LOCK) {
3085 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3086 DRM_DEBUG_KMS("FDI train 2 done.\n");
3091 DRM_ERROR("FDI train 2 fail!\n");
3093 DRM_DEBUG_KMS("FDI train done\n");
3097 static const int snb_b_fdi_train_param[] = {
3098 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3099 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3100 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3101 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3104 /* The FDI link training functions for SNB/Cougarpoint. */
3105 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3107 struct drm_device *dev = crtc->dev;
3108 struct drm_i915_private *dev_priv = dev->dev_private;
3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110 int pipe = intel_crtc->pipe;
3111 u32 reg, temp, i, retry;
3113 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3115 reg = FDI_RX_IMR(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~FDI_RX_SYMBOL_LOCK;
3118 temp &= ~FDI_RX_BIT_LOCK;
3119 I915_WRITE(reg, temp);
3124 /* enable CPU FDI TX and PCH FDI RX */
3125 reg = FDI_TX_CTL(pipe);
3126 temp = I915_READ(reg);
3127 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3128 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_PATTERN_1;
3131 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3133 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3134 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3136 I915_WRITE(FDI_RX_MISC(pipe),
3137 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3139 reg = FDI_RX_CTL(pipe);
3140 temp = I915_READ(reg);
3141 if (HAS_PCH_CPT(dev)) {
3142 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3143 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3145 temp &= ~FDI_LINK_TRAIN_NONE;
3146 temp |= FDI_LINK_TRAIN_PATTERN_1;
3148 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3153 for (i = 0; i < 4; i++) {
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3157 temp |= snb_b_fdi_train_param[i];
3158 I915_WRITE(reg, temp);
3163 for (retry = 0; retry < 5; retry++) {
3164 reg = FDI_RX_IIR(pipe);
3165 temp = I915_READ(reg);
3166 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3167 if (temp & FDI_RX_BIT_LOCK) {
3168 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3169 DRM_DEBUG_KMS("FDI train 1 done.\n");
3178 DRM_ERROR("FDI train 1 fail!\n");
3181 reg = FDI_TX_CTL(pipe);
3182 temp = I915_READ(reg);
3183 temp &= ~FDI_LINK_TRAIN_NONE;
3184 temp |= FDI_LINK_TRAIN_PATTERN_2;
3186 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3188 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3190 I915_WRITE(reg, temp);
3192 reg = FDI_RX_CTL(pipe);
3193 temp = I915_READ(reg);
3194 if (HAS_PCH_CPT(dev)) {
3195 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3196 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3198 temp &= ~FDI_LINK_TRAIN_NONE;
3199 temp |= FDI_LINK_TRAIN_PATTERN_2;
3201 I915_WRITE(reg, temp);
3206 for (i = 0; i < 4; i++) {
3207 reg = FDI_TX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3210 temp |= snb_b_fdi_train_param[i];
3211 I915_WRITE(reg, temp);
3216 for (retry = 0; retry < 5; retry++) {
3217 reg = FDI_RX_IIR(pipe);
3218 temp = I915_READ(reg);
3219 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3220 if (temp & FDI_RX_SYMBOL_LOCK) {
3221 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3222 DRM_DEBUG_KMS("FDI train 2 done.\n");
3231 DRM_ERROR("FDI train 2 fail!\n");
3233 DRM_DEBUG_KMS("FDI train done.\n");
3236 /* Manual link training for Ivy Bridge A0 parts */
3237 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 int pipe = intel_crtc->pipe;
3243 u32 reg, temp, i, j;
3245 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3247 reg = FDI_RX_IMR(pipe);
3248 temp = I915_READ(reg);
3249 temp &= ~FDI_RX_SYMBOL_LOCK;
3250 temp &= ~FDI_RX_BIT_LOCK;
3251 I915_WRITE(reg, temp);
3256 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3257 I915_READ(FDI_RX_IIR(pipe)));
3259 /* Try each vswing and preemphasis setting twice before moving on */
3260 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3261 /* disable first in case we need to retry */
3262 reg = FDI_TX_CTL(pipe);
3263 temp = I915_READ(reg);
3264 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3265 temp &= ~FDI_TX_ENABLE;
3266 I915_WRITE(reg, temp);
3268 reg = FDI_RX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 temp &= ~FDI_LINK_TRAIN_AUTO;
3271 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3272 temp &= ~FDI_RX_ENABLE;
3273 I915_WRITE(reg, temp);
3275 /* enable CPU FDI TX and PCH FDI RX */
3276 reg = FDI_TX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3279 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3280 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3281 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3282 temp |= snb_b_fdi_train_param[j/2];
3283 temp |= FDI_COMPOSITE_SYNC;
3284 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3286 I915_WRITE(FDI_RX_MISC(pipe),
3287 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3289 reg = FDI_RX_CTL(pipe);
3290 temp = I915_READ(reg);
3291 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3292 temp |= FDI_COMPOSITE_SYNC;
3293 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3296 udelay(1); /* should be 0.5us */
3298 for (i = 0; i < 4; i++) {
3299 reg = FDI_RX_IIR(pipe);
3300 temp = I915_READ(reg);
3301 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3303 if (temp & FDI_RX_BIT_LOCK ||
3304 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3305 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3306 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3310 udelay(1); /* should be 0.5us */
3313 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3318 reg = FDI_TX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3321 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3322 I915_WRITE(reg, temp);
3324 reg = FDI_RX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3327 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3328 I915_WRITE(reg, temp);
3331 udelay(2); /* should be 1.5us */
3333 for (i = 0; i < 4; i++) {
3334 reg = FDI_RX_IIR(pipe);
3335 temp = I915_READ(reg);
3336 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3338 if (temp & FDI_RX_SYMBOL_LOCK ||
3339 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3340 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3341 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3345 udelay(2); /* should be 1.5us */
3348 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3352 DRM_DEBUG_KMS("FDI train done.\n");
3355 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3357 struct drm_device *dev = intel_crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 int pipe = intel_crtc->pipe;
3363 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3364 reg = FDI_RX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3367 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3368 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3369 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3374 /* Switch from Rawclk to PCDclk */
3375 temp = I915_READ(reg);
3376 I915_WRITE(reg, temp | FDI_PCDCLK);
3381 /* Enable CPU FDI TX PLL, always on for Ironlake */
3382 reg = FDI_TX_CTL(pipe);
3383 temp = I915_READ(reg);
3384 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3385 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3392 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3394 struct drm_device *dev = intel_crtc->base.dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 int pipe = intel_crtc->pipe;
3399 /* Switch from PCDclk to Rawclk */
3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3404 /* Disable CPU FDI TX PLL */
3405 reg = FDI_TX_CTL(pipe);
3406 temp = I915_READ(reg);
3407 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3412 reg = FDI_RX_CTL(pipe);
3413 temp = I915_READ(reg);
3414 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3416 /* Wait for the clocks to turn off. */
3421 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 int pipe = intel_crtc->pipe;
3429 /* disable CPU FDI tx and PCH FDI rx */
3430 reg = FDI_TX_CTL(pipe);
3431 temp = I915_READ(reg);
3432 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3435 reg = FDI_RX_CTL(pipe);
3436 temp = I915_READ(reg);
3437 temp &= ~(0x7 << 16);
3438 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3439 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3444 /* Ironlake workaround, disable clock pointer after downing FDI */
3445 if (HAS_PCH_IBX(dev))
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3448 /* still set train pattern 1 */
3449 reg = FDI_TX_CTL(pipe);
3450 temp = I915_READ(reg);
3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_1;
3453 I915_WRITE(reg, temp);
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 if (HAS_PCH_CPT(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_1;
3464 /* BPC in FDI rx is consistent with that in PIPECONF */
3465 temp &= ~(0x07 << 16);
3466 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467 I915_WRITE(reg, temp);
3473 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3475 struct intel_crtc *crtc;
3477 /* Note that we don't need to be called with mode_config.lock here
3478 * as our list of CRTC objects is static for the lifetime of the
3479 * device and so cannot disappear as we iterate. Similarly, we can
3480 * happily treat the predicates as racy, atomic checks as userspace
3481 * cannot claim and pin a new fb without at least acquring the
3482 * struct_mutex and so serialising with us.
3484 for_each_intel_crtc(dev, crtc) {
3485 if (atomic_read(&crtc->unpin_work_count) == 0)
3488 if (crtc->unpin_work)
3489 intel_wait_for_vblank(dev, crtc->pipe);
3497 static void page_flip_completed(struct intel_crtc *intel_crtc)
3499 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3500 struct intel_unpin_work *work = intel_crtc->unpin_work;
3502 /* ensure that the unpin work is consistent wrt ->pending. */
3504 intel_crtc->unpin_work = NULL;
3507 drm_send_vblank_event(intel_crtc->base.dev,
3511 drm_crtc_vblank_put(&intel_crtc->base);
3513 wake_up_all(&dev_priv->pending_flip_queue);
3514 queue_work(dev_priv->wq, &work->work);
3516 trace_i915_flip_complete(intel_crtc->plane,
3517 work->pending_flip_obj);
3520 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3525 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3526 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3527 !intel_crtc_has_pending_flip(crtc),
3529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531 spin_lock_irq(&dev->event_lock);
3532 if (intel_crtc->unpin_work) {
3533 WARN_ONCE(1, "Removing stuck page flip\n");
3534 page_flip_completed(intel_crtc);
3536 spin_unlock_irq(&dev->event_lock);
3539 if (crtc->primary->fb) {
3540 mutex_lock(&dev->struct_mutex);
3541 intel_finish_fb(crtc->primary->fb);
3542 mutex_unlock(&dev->struct_mutex);
3546 /* Program iCLKIP clock to the desired frequency */
3547 static void lpt_program_iclkip(struct drm_crtc *crtc)
3549 struct drm_device *dev = crtc->dev;
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3552 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3555 mutex_lock(&dev_priv->dpio_lock);
3557 /* It is necessary to ungate the pixclk gate prior to programming
3558 * the divisors, and gate it back when it is done.
3560 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3562 /* Disable SSCCTL */
3563 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3564 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3568 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3569 if (clock == 20000) {
3574 /* The iCLK virtual clock root frequency is in MHz,
3575 * but the adjusted_mode->crtc_clock in in KHz. To get the
3576 * divisors, it is necessary to divide one by another, so we
3577 * convert the virtual clock precision to KHz here for higher
3580 u32 iclk_virtual_root_freq = 172800 * 1000;
3581 u32 iclk_pi_range = 64;
3582 u32 desired_divisor, msb_divisor_value, pi_value;
3584 desired_divisor = (iclk_virtual_root_freq / clock);
3585 msb_divisor_value = desired_divisor / iclk_pi_range;
3586 pi_value = desired_divisor % iclk_pi_range;
3589 divsel = msb_divisor_value - 2;
3590 phaseinc = pi_value;
3593 /* This should not happen with any sane values */
3594 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3595 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3596 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3597 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3599 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3606 /* Program SSCDIVINTPHASE6 */
3607 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3608 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3609 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3610 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3611 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3612 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3613 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3614 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3616 /* Program SSCAUXDIV */
3617 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3618 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3619 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3620 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3622 /* Enable modulator and associated divider */
3623 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3624 temp &= ~SBI_SSCCTL_DISABLE;
3625 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3627 /* Wait for initialization time */
3630 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3632 mutex_unlock(&dev_priv->dpio_lock);
3635 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3636 enum pipe pch_transcoder)
3638 struct drm_device *dev = crtc->base.dev;
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3642 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3643 I915_READ(HTOTAL(cpu_transcoder)));
3644 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3645 I915_READ(HBLANK(cpu_transcoder)));
3646 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3647 I915_READ(HSYNC(cpu_transcoder)));
3649 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3650 I915_READ(VTOTAL(cpu_transcoder)));
3651 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3652 I915_READ(VBLANK(cpu_transcoder)));
3653 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3654 I915_READ(VSYNC(cpu_transcoder)));
3655 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3656 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3659 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3664 temp = I915_READ(SOUTH_CHICKEN1);
3665 if (temp & FDI_BC_BIFURCATION_SELECT)
3668 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3669 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3671 temp |= FDI_BC_BIFURCATION_SELECT;
3672 DRM_DEBUG_KMS("enabling fdi C rx\n");
3673 I915_WRITE(SOUTH_CHICKEN1, temp);
3674 POSTING_READ(SOUTH_CHICKEN1);
3677 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3679 struct drm_device *dev = intel_crtc->base.dev;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3682 switch (intel_crtc->pipe) {
3686 if (intel_crtc->config.fdi_lanes > 2)
3687 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3689 cpt_enable_fdi_bc_bifurcation(dev);
3693 cpt_enable_fdi_bc_bifurcation(dev);
3702 * Enable PCH resources required for PCH ports:
3704 * - FDI training & RX/TX
3705 * - update transcoder timings
3706 * - DP transcoding bits
3709 static void ironlake_pch_enable(struct drm_crtc *crtc)
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714 int pipe = intel_crtc->pipe;
3717 assert_pch_transcoder_disabled(dev_priv, pipe);
3719 if (IS_IVYBRIDGE(dev))
3720 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3722 /* Write the TU size bits before fdi link training, so that error
3723 * detection works. */
3724 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3725 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3727 /* For PCH output, training FDI link */
3728 dev_priv->display.fdi_link_train(crtc);
3730 /* We need to program the right clock selection before writing the pixel
3731 * mutliplier into the DPLL. */
3732 if (HAS_PCH_CPT(dev)) {
3735 temp = I915_READ(PCH_DPLL_SEL);
3736 temp |= TRANS_DPLL_ENABLE(pipe);
3737 sel = TRANS_DPLLB_SEL(pipe);
3738 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3742 I915_WRITE(PCH_DPLL_SEL, temp);
3745 /* XXX: pch pll's can be enabled any time before we enable the PCH
3746 * transcoder, and we actually should do this to not upset any PCH
3747 * transcoder that already use the clock when we share it.
3749 * Note that enable_shared_dpll tries to do the right thing, but
3750 * get_shared_dpll unconditionally resets the pll - we need that to have
3751 * the right LVDS enable sequence. */
3752 intel_enable_shared_dpll(intel_crtc);
3754 /* set transcoder timing, panel must allow it */
3755 assert_panel_unlocked(dev_priv, pipe);
3756 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3758 intel_fdi_normal_train(crtc);
3760 /* For PCH DP, enable TRANS_DP_CTL */
3761 if (HAS_PCH_CPT(dev) &&
3762 (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3763 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3764 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3765 reg = TRANS_DP_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3768 TRANS_DP_SYNC_MASK |
3770 temp |= (TRANS_DP_OUTPUT_ENABLE |
3771 TRANS_DP_ENH_FRAMING);
3772 temp |= bpc << 9; /* same format but at 11:9 */
3774 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3775 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3776 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3777 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3779 switch (intel_trans_dp_port_sel(crtc)) {
3781 temp |= TRANS_DP_PORT_SEL_B;
3784 temp |= TRANS_DP_PORT_SEL_C;
3787 temp |= TRANS_DP_PORT_SEL_D;
3793 I915_WRITE(reg, temp);
3796 ironlake_enable_pch_transcoder(dev_priv, pipe);
3799 static void lpt_pch_enable(struct drm_crtc *crtc)
3801 struct drm_device *dev = crtc->dev;
3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3806 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3808 lpt_program_iclkip(crtc);
3810 /* Set transcoder timing. */
3811 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3813 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3816 void intel_put_shared_dpll(struct intel_crtc *crtc)
3818 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3823 if (pll->refcount == 0) {
3824 WARN(1, "bad %s refcount\n", pll->name);
3828 if (--pll->refcount == 0) {
3830 WARN_ON(pll->active);
3833 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3836 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3838 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3839 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3840 enum intel_dpll_id i;
3843 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3844 crtc->base.base.id, pll->name);
3845 intel_put_shared_dpll(crtc);
3848 if (HAS_PCH_IBX(dev_priv->dev)) {
3849 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3850 i = (enum intel_dpll_id) crtc->pipe;
3851 pll = &dev_priv->shared_dplls[i];
3853 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3854 crtc->base.base.id, pll->name);
3856 WARN_ON(pll->refcount);
3861 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3862 pll = &dev_priv->shared_dplls[i];
3864 /* Only want to check enabled timings first */
3865 if (pll->refcount == 0)
3868 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3869 sizeof(pll->hw_state)) == 0) {
3870 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3872 pll->name, pll->refcount, pll->active);
3878 /* Ok no matching timings, maybe there's a free one? */
3879 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3880 pll = &dev_priv->shared_dplls[i];
3881 if (pll->refcount == 0) {
3882 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3883 crtc->base.base.id, pll->name);
3891 if (pll->refcount == 0)
3892 pll->hw_state = crtc->config.dpll_hw_state;
3894 crtc->config.shared_dpll = i;
3895 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3896 pipe_name(crtc->pipe));
3903 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 int dslreg = PIPEDSL(pipe);
3909 temp = I915_READ(dslreg);
3911 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3912 if (wait_for(I915_READ(dslreg) != temp, 5))
3913 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3917 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3919 struct drm_device *dev = crtc->base.dev;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 int pipe = crtc->pipe;
3923 if (crtc->config.pch_pfit.enabled) {
3924 /* Force use of hard-coded filter coefficients
3925 * as some pre-programmed values are broken,
3928 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3929 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3930 PF_PIPE_SEL_IVB(pipe));
3932 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3933 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3934 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3938 static void intel_enable_planes(struct drm_crtc *crtc)
3940 struct drm_device *dev = crtc->dev;
3941 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3942 struct drm_plane *plane;
3943 struct intel_plane *intel_plane;
3945 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3946 intel_plane = to_intel_plane(plane);
3947 if (intel_plane->pipe == pipe)
3948 intel_plane_restore(&intel_plane->base);
3952 static void intel_disable_planes(struct drm_crtc *crtc)
3954 struct drm_device *dev = crtc->dev;
3955 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3956 struct drm_plane *plane;
3957 struct intel_plane *intel_plane;
3959 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3960 intel_plane = to_intel_plane(plane);
3961 if (intel_plane->pipe == pipe)
3962 intel_plane_disable(&intel_plane->base);
3966 void hsw_enable_ips(struct intel_crtc *crtc)
3968 struct drm_device *dev = crtc->base.dev;
3969 struct drm_i915_private *dev_priv = dev->dev_private;
3971 if (!crtc->config.ips_enabled)
3974 /* We can only enable IPS after we enable a plane and wait for a vblank */
3975 intel_wait_for_vblank(dev, crtc->pipe);
3977 assert_plane_enabled(dev_priv, crtc->plane);
3978 if (IS_BROADWELL(dev)) {
3979 mutex_lock(&dev_priv->rps.hw_lock);
3980 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3981 mutex_unlock(&dev_priv->rps.hw_lock);
3982 /* Quoting Art Runyan: "its not safe to expect any particular
3983 * value in IPS_CTL bit 31 after enabling IPS through the
3984 * mailbox." Moreover, the mailbox may return a bogus state,
3985 * so we need to just enable it and continue on.
3988 I915_WRITE(IPS_CTL, IPS_ENABLE);
3989 /* The bit only becomes 1 in the next vblank, so this wait here
3990 * is essentially intel_wait_for_vblank. If we don't have this
3991 * and don't wait for vblanks until the end of crtc_enable, then
3992 * the HW state readout code will complain that the expected
3993 * IPS_CTL value is not the one we read. */
3994 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3995 DRM_ERROR("Timed out waiting for IPS enable\n");
3999 void hsw_disable_ips(struct intel_crtc *crtc)
4001 struct drm_device *dev = crtc->base.dev;
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4004 if (!crtc->config.ips_enabled)
4007 assert_plane_enabled(dev_priv, crtc->plane);
4008 if (IS_BROADWELL(dev)) {
4009 mutex_lock(&dev_priv->rps.hw_lock);
4010 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4011 mutex_unlock(&dev_priv->rps.hw_lock);
4012 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4013 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4014 DRM_ERROR("Timed out waiting for IPS disable\n");
4016 I915_WRITE(IPS_CTL, 0);
4017 POSTING_READ(IPS_CTL);
4020 /* We need to wait for a vblank before we can disable the plane. */
4021 intel_wait_for_vblank(dev, crtc->pipe);
4024 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4025 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4027 struct drm_device *dev = crtc->dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4030 enum pipe pipe = intel_crtc->pipe;
4031 int palreg = PALETTE(pipe);
4033 bool reenable_ips = false;
4035 /* The clocks have to be on to load the palette. */
4036 if (!crtc->enabled || !intel_crtc->active)
4039 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4040 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4041 assert_dsi_pll_enabled(dev_priv);
4043 assert_pll_enabled(dev_priv, pipe);
4046 /* use legacy palette for Ironlake */
4047 if (!HAS_GMCH_DISPLAY(dev))
4048 palreg = LGC_PALETTE(pipe);
4050 /* Workaround : Do not read or write the pipe palette/gamma data while
4051 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4053 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4054 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4055 GAMMA_MODE_MODE_SPLIT)) {
4056 hsw_disable_ips(intel_crtc);
4057 reenable_ips = true;
4060 for (i = 0; i < 256; i++) {
4061 I915_WRITE(palreg + 4 * i,
4062 (intel_crtc->lut_r[i] << 16) |
4063 (intel_crtc->lut_g[i] << 8) |
4064 intel_crtc->lut_b[i]);
4068 hsw_enable_ips(intel_crtc);
4071 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4073 if (!enable && intel_crtc->overlay) {
4074 struct drm_device *dev = intel_crtc->base.dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4077 mutex_lock(&dev->struct_mutex);
4078 dev_priv->mm.interruptible = false;
4079 (void) intel_overlay_switch_off(intel_crtc->overlay);
4080 dev_priv->mm.interruptible = true;
4081 mutex_unlock(&dev->struct_mutex);
4084 /* Let userspace switch the overlay on again. In most cases userspace
4085 * has to recompute where to put it anyway.
4089 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4091 struct drm_device *dev = crtc->dev;
4092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 int pipe = intel_crtc->pipe;
4095 intel_enable_primary_hw_plane(crtc->primary, crtc);
4096 intel_enable_planes(crtc);
4097 intel_crtc_update_cursor(crtc, true);
4098 intel_crtc_dpms_overlay(intel_crtc, true);
4100 hsw_enable_ips(intel_crtc);
4102 mutex_lock(&dev->struct_mutex);
4103 intel_update_fbc(dev);
4104 mutex_unlock(&dev->struct_mutex);
4107 * FIXME: Once we grow proper nuclear flip support out of this we need
4108 * to compute the mask of flip planes precisely. For the time being
4109 * consider this a flip from a NULL plane.
4111 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4114 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119 int pipe = intel_crtc->pipe;
4120 int plane = intel_crtc->plane;
4122 intel_crtc_wait_for_pending_flips(crtc);
4124 if (dev_priv->fbc.plane == plane)
4125 intel_disable_fbc(dev);
4127 hsw_disable_ips(intel_crtc);
4129 intel_crtc_dpms_overlay(intel_crtc, false);
4130 intel_crtc_update_cursor(crtc, false);
4131 intel_disable_planes(crtc);
4132 intel_disable_primary_hw_plane(crtc->primary, crtc);
4135 * FIXME: Once we grow proper nuclear flip support out of this we need
4136 * to compute the mask of flip planes precisely. For the time being
4137 * consider this a flip to a NULL plane.
4139 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4142 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4144 struct drm_device *dev = crtc->dev;
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147 struct intel_encoder *encoder;
4148 int pipe = intel_crtc->pipe;
4150 WARN_ON(!crtc->enabled);
4152 if (intel_crtc->active)
4155 if (intel_crtc->config.has_pch_encoder)
4156 intel_prepare_shared_dpll(intel_crtc);
4158 if (intel_crtc->config.has_dp_encoder)
4159 intel_dp_set_m_n(intel_crtc);
4161 intel_set_pipe_timings(intel_crtc);
4163 if (intel_crtc->config.has_pch_encoder) {
4164 intel_cpu_transcoder_set_m_n(intel_crtc,
4165 &intel_crtc->config.fdi_m_n, NULL);
4168 ironlake_set_pipeconf(crtc);
4170 intel_crtc->active = true;
4172 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 if (encoder->pre_enable)
4177 encoder->pre_enable(encoder);
4179 if (intel_crtc->config.has_pch_encoder) {
4180 /* Note: FDI PLL enabling _must_ be done before we enable the
4181 * cpu pipes, hence this is separate from all the other fdi/pch
4183 ironlake_fdi_pll_enable(intel_crtc);
4185 assert_fdi_tx_disabled(dev_priv, pipe);
4186 assert_fdi_rx_disabled(dev_priv, pipe);
4189 ironlake_pfit_enable(intel_crtc);
4192 * On ILK+ LUT must be loaded before the pipe is running but with
4195 intel_crtc_load_lut(crtc);
4197 intel_update_watermarks(crtc);
4198 intel_enable_pipe(intel_crtc);
4200 if (intel_crtc->config.has_pch_encoder)
4201 ironlake_pch_enable(crtc);
4203 for_each_encoder_on_crtc(dev, crtc, encoder)
4204 encoder->enable(encoder);
4206 if (HAS_PCH_CPT(dev))
4207 cpt_verify_modeset(dev, intel_crtc->pipe);
4209 assert_vblank_disabled(crtc);
4210 drm_crtc_vblank_on(crtc);
4212 intel_crtc_enable_planes(crtc);
4215 /* IPS only exists on ULT machines and is tied to pipe A. */
4216 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4218 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4222 * This implements the workaround described in the "notes" section of the mode
4223 * set sequence documentation. When going from no pipes or single pipe to
4224 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4225 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4227 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4229 struct drm_device *dev = crtc->base.dev;
4230 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4232 /* We want to get the other_active_crtc only if there's only 1 other
4234 for_each_intel_crtc(dev, crtc_it) {
4235 if (!crtc_it->active || crtc_it == crtc)
4238 if (other_active_crtc)
4241 other_active_crtc = crtc_it;
4243 if (!other_active_crtc)
4246 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4247 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4250 static void haswell_crtc_enable(struct drm_crtc *crtc)
4252 struct drm_device *dev = crtc->dev;
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4255 struct intel_encoder *encoder;
4256 int pipe = intel_crtc->pipe;
4258 WARN_ON(!crtc->enabled);
4260 if (intel_crtc->active)
4263 if (intel_crtc_to_shared_dpll(intel_crtc))
4264 intel_enable_shared_dpll(intel_crtc);
4266 if (intel_crtc->config.has_dp_encoder)
4267 intel_dp_set_m_n(intel_crtc);
4269 intel_set_pipe_timings(intel_crtc);
4271 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4272 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4273 intel_crtc->config.pixel_multiplier - 1);
4276 if (intel_crtc->config.has_pch_encoder) {
4277 intel_cpu_transcoder_set_m_n(intel_crtc,
4278 &intel_crtc->config.fdi_m_n, NULL);
4281 haswell_set_pipeconf(crtc);
4283 intel_set_pipe_csc(crtc);
4285 intel_crtc->active = true;
4287 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4288 for_each_encoder_on_crtc(dev, crtc, encoder)
4289 if (encoder->pre_enable)
4290 encoder->pre_enable(encoder);
4292 if (intel_crtc->config.has_pch_encoder) {
4293 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4295 dev_priv->display.fdi_link_train(crtc);
4298 intel_ddi_enable_pipe_clock(intel_crtc);
4300 ironlake_pfit_enable(intel_crtc);
4303 * On ILK+ LUT must be loaded before the pipe is running but with
4306 intel_crtc_load_lut(crtc);
4308 intel_ddi_set_pipe_settings(crtc);
4309 intel_ddi_enable_transcoder_func(crtc);
4311 intel_update_watermarks(crtc);
4312 intel_enable_pipe(intel_crtc);
4314 if (intel_crtc->config.has_pch_encoder)
4315 lpt_pch_enable(crtc);
4317 if (intel_crtc->config.dp_encoder_is_mst)
4318 intel_ddi_set_vc_payload_alloc(crtc, true);
4320 for_each_encoder_on_crtc(dev, crtc, encoder) {
4321 encoder->enable(encoder);
4322 intel_opregion_notify_encoder(encoder, true);
4325 assert_vblank_disabled(crtc);
4326 drm_crtc_vblank_on(crtc);
4328 /* If we change the relative order between pipe/planes enabling, we need
4329 * to change the workaround. */
4330 haswell_mode_set_planes_workaround(intel_crtc);
4331 intel_crtc_enable_planes(crtc);
4334 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4336 struct drm_device *dev = crtc->base.dev;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338 int pipe = crtc->pipe;
4340 /* To avoid upsetting the power well on haswell only disable the pfit if
4341 * it's in use. The hw state code will make sure we get this right. */
4342 if (crtc->config.pch_pfit.enabled) {
4343 I915_WRITE(PF_CTL(pipe), 0);
4344 I915_WRITE(PF_WIN_POS(pipe), 0);
4345 I915_WRITE(PF_WIN_SZ(pipe), 0);
4349 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4351 struct drm_device *dev = crtc->dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354 struct intel_encoder *encoder;
4355 int pipe = intel_crtc->pipe;
4358 if (!intel_crtc->active)
4361 intel_crtc_disable_planes(crtc);
4363 drm_crtc_vblank_off(crtc);
4364 assert_vblank_disabled(crtc);
4366 for_each_encoder_on_crtc(dev, crtc, encoder)
4367 encoder->disable(encoder);
4369 if (intel_crtc->config.has_pch_encoder)
4370 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4372 intel_disable_pipe(intel_crtc);
4374 ironlake_pfit_disable(intel_crtc);
4376 for_each_encoder_on_crtc(dev, crtc, encoder)
4377 if (encoder->post_disable)
4378 encoder->post_disable(encoder);
4380 if (intel_crtc->config.has_pch_encoder) {
4381 ironlake_fdi_disable(crtc);
4383 ironlake_disable_pch_transcoder(dev_priv, pipe);
4384 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4386 if (HAS_PCH_CPT(dev)) {
4387 /* disable TRANS_DP_CTL */
4388 reg = TRANS_DP_CTL(pipe);
4389 temp = I915_READ(reg);
4390 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4391 TRANS_DP_PORT_SEL_MASK);
4392 temp |= TRANS_DP_PORT_SEL_NONE;
4393 I915_WRITE(reg, temp);
4395 /* disable DPLL_SEL */
4396 temp = I915_READ(PCH_DPLL_SEL);
4397 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4398 I915_WRITE(PCH_DPLL_SEL, temp);
4401 /* disable PCH DPLL */
4402 intel_disable_shared_dpll(intel_crtc);
4404 ironlake_fdi_pll_disable(intel_crtc);
4407 intel_crtc->active = false;
4408 intel_update_watermarks(crtc);
4410 mutex_lock(&dev->struct_mutex);
4411 intel_update_fbc(dev);
4412 mutex_unlock(&dev->struct_mutex);
4415 static void haswell_crtc_disable(struct drm_crtc *crtc)
4417 struct drm_device *dev = crtc->dev;
4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4420 struct intel_encoder *encoder;
4421 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4423 if (!intel_crtc->active)
4426 intel_crtc_disable_planes(crtc);
4428 drm_crtc_vblank_off(crtc);
4429 assert_vblank_disabled(crtc);
4431 for_each_encoder_on_crtc(dev, crtc, encoder) {
4432 intel_opregion_notify_encoder(encoder, false);
4433 encoder->disable(encoder);
4436 if (intel_crtc->config.has_pch_encoder)
4437 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4439 intel_disable_pipe(intel_crtc);
4441 if (intel_crtc->config.dp_encoder_is_mst)
4442 intel_ddi_set_vc_payload_alloc(crtc, false);
4444 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4446 ironlake_pfit_disable(intel_crtc);
4448 intel_ddi_disable_pipe_clock(intel_crtc);
4450 if (intel_crtc->config.has_pch_encoder) {
4451 lpt_disable_pch_transcoder(dev_priv);
4452 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4454 intel_ddi_fdi_disable(crtc);
4457 for_each_encoder_on_crtc(dev, crtc, encoder)
4458 if (encoder->post_disable)
4459 encoder->post_disable(encoder);
4461 intel_crtc->active = false;
4462 intel_update_watermarks(crtc);
4464 mutex_lock(&dev->struct_mutex);
4465 intel_update_fbc(dev);
4466 mutex_unlock(&dev->struct_mutex);
4468 if (intel_crtc_to_shared_dpll(intel_crtc))
4469 intel_disable_shared_dpll(intel_crtc);
4472 static void ironlake_crtc_off(struct drm_crtc *crtc)
4474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475 intel_put_shared_dpll(intel_crtc);
4479 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4481 struct drm_device *dev = crtc->base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 struct intel_crtc_config *pipe_config = &crtc->config;
4485 if (!crtc->config.gmch_pfit.control)
4489 * The panel fitter should only be adjusted whilst the pipe is disabled,
4490 * according to register description and PRM.
4492 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4493 assert_pipe_disabled(dev_priv, crtc->pipe);
4495 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4496 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4498 /* Border color in case we don't scale up to the full screen. Black by
4499 * default, change to something else for debugging. */
4500 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4503 static enum intel_display_power_domain port_to_power_domain(enum port port)
4507 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4509 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4511 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4513 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4516 return POWER_DOMAIN_PORT_OTHER;
4520 #define for_each_power_domain(domain, mask) \
4521 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4522 if ((1 << (domain)) & (mask))
4524 enum intel_display_power_domain
4525 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4527 struct drm_device *dev = intel_encoder->base.dev;
4528 struct intel_digital_port *intel_dig_port;
4530 switch (intel_encoder->type) {
4531 case INTEL_OUTPUT_UNKNOWN:
4532 /* Only DDI platforms should ever use this output type */
4533 WARN_ON_ONCE(!HAS_DDI(dev));
4534 case INTEL_OUTPUT_DISPLAYPORT:
4535 case INTEL_OUTPUT_HDMI:
4536 case INTEL_OUTPUT_EDP:
4537 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4538 return port_to_power_domain(intel_dig_port->port);
4539 case INTEL_OUTPUT_DP_MST:
4540 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4541 return port_to_power_domain(intel_dig_port->port);
4542 case INTEL_OUTPUT_ANALOG:
4543 return POWER_DOMAIN_PORT_CRT;
4544 case INTEL_OUTPUT_DSI:
4545 return POWER_DOMAIN_PORT_DSI;
4547 return POWER_DOMAIN_PORT_OTHER;
4551 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4553 struct drm_device *dev = crtc->dev;
4554 struct intel_encoder *intel_encoder;
4555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556 enum pipe pipe = intel_crtc->pipe;
4558 enum transcoder transcoder;
4560 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4562 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4563 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4564 if (intel_crtc->config.pch_pfit.enabled ||
4565 intel_crtc->config.pch_pfit.force_thru)
4566 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4568 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4569 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4574 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4578 struct intel_crtc *crtc;
4581 * First get all needed power domains, then put all unneeded, to avoid
4582 * any unnecessary toggling of the power wells.
4584 for_each_intel_crtc(dev, crtc) {
4585 enum intel_display_power_domain domain;
4587 if (!crtc->base.enabled)
4590 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4592 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4593 intel_display_power_get(dev_priv, domain);
4596 for_each_intel_crtc(dev, crtc) {
4597 enum intel_display_power_domain domain;
4599 for_each_power_domain(domain, crtc->enabled_power_domains)
4600 intel_display_power_put(dev_priv, domain);
4602 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4605 intel_display_set_init_power(dev_priv, false);
4608 /* returns HPLL frequency in kHz */
4609 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4611 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4613 /* Obtain SKU information */
4614 mutex_lock(&dev_priv->dpio_lock);
4615 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4616 CCK_FUSE_HPLL_FREQ_MASK;
4617 mutex_unlock(&dev_priv->dpio_lock);
4619 return vco_freq[hpll_freq] * 1000;
4622 static void vlv_update_cdclk(struct drm_device *dev)
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4626 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4627 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4628 dev_priv->vlv_cdclk_freq);
4631 * Program the gmbus_freq based on the cdclk frequency.
4632 * BSpec erroneously claims we should aim for 4MHz, but
4633 * in fact 1MHz is the correct frequency.
4635 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4638 /* Adjust CDclk dividers to allow high res or save power if possible */
4639 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4644 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4646 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4648 else if (cdclk == 266667)
4653 mutex_lock(&dev_priv->rps.hw_lock);
4654 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4655 val &= ~DSPFREQGUAR_MASK;
4656 val |= (cmd << DSPFREQGUAR_SHIFT);
4657 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4658 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4659 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4661 DRM_ERROR("timed out waiting for CDclk change\n");
4663 mutex_unlock(&dev_priv->rps.hw_lock);
4665 if (cdclk == 400000) {
4668 vco = valleyview_get_vco(dev_priv);
4669 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4671 mutex_lock(&dev_priv->dpio_lock);
4672 /* adjust cdclk divider */
4673 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4674 val &= ~DISPLAY_FREQUENCY_VALUES;
4676 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4678 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4679 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4681 DRM_ERROR("timed out waiting for CDclk change\n");
4682 mutex_unlock(&dev_priv->dpio_lock);
4685 mutex_lock(&dev_priv->dpio_lock);
4686 /* adjust self-refresh exit latency value */
4687 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4691 * For high bandwidth configs, we set a higher latency in the bunit
4692 * so that the core display fetch happens in time to avoid underruns.
4694 if (cdclk == 400000)
4695 val |= 4500 / 250; /* 4.5 usec */
4697 val |= 3000 / 250; /* 3.0 usec */
4698 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4699 mutex_unlock(&dev_priv->dpio_lock);
4701 vlv_update_cdclk(dev);
4704 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4706 struct drm_i915_private *dev_priv = dev->dev_private;
4709 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4730 mutex_lock(&dev_priv->rps.hw_lock);
4731 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4732 val &= ~DSPFREQGUAR_MASK_CHV;
4733 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4734 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4735 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4736 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4738 DRM_ERROR("timed out waiting for CDclk change\n");
4740 mutex_unlock(&dev_priv->rps.hw_lock);
4742 vlv_update_cdclk(dev);
4745 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4748 int vco = valleyview_get_vco(dev_priv);
4749 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4751 /* FIXME: Punit isn't quite ready yet */
4752 if (IS_CHERRYVIEW(dev_priv->dev))
4756 * Really only a few cases to deal with, as only 4 CDclks are supported:
4759 * 320/333MHz (depends on HPLL freq)
4761 * So we check to see whether we're above 90% of the lower bin and
4764 * We seem to get an unstable or solid color picture at 200MHz.
4765 * Not sure what's wrong. For now use 200MHz only when all pipes
4768 if (max_pixclk > freq_320*9/10)
4770 else if (max_pixclk > 266667*9/10)
4772 else if (max_pixclk > 0)
4778 /* compute the max pixel clock for new configuration */
4779 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4781 struct drm_device *dev = dev_priv->dev;
4782 struct intel_crtc *intel_crtc;
4785 for_each_intel_crtc(dev, intel_crtc) {
4786 if (intel_crtc->new_enabled)
4787 max_pixclk = max(max_pixclk,
4788 intel_crtc->new_config->adjusted_mode.crtc_clock);
4794 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4795 unsigned *prepare_pipes)
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 struct intel_crtc *intel_crtc;
4799 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4801 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4802 dev_priv->vlv_cdclk_freq)
4805 /* disable/enable all currently active pipes while we change cdclk */
4806 for_each_intel_crtc(dev, intel_crtc)
4807 if (intel_crtc->base.enabled)
4808 *prepare_pipes |= (1 << intel_crtc->pipe);
4811 static void valleyview_modeset_global_resources(struct drm_device *dev)
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4815 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4817 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4818 if (IS_CHERRYVIEW(dev))
4819 cherryview_set_cdclk(dev, req_cdclk);
4821 valleyview_set_cdclk(dev, req_cdclk);
4824 modeset_update_crtc_power_domains(dev);
4827 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4829 struct drm_device *dev = crtc->dev;
4830 struct drm_i915_private *dev_priv = to_i915(dev);
4831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832 struct intel_encoder *encoder;
4833 int pipe = intel_crtc->pipe;
4836 WARN_ON(!crtc->enabled);
4838 if (intel_crtc->active)
4841 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4844 if (IS_CHERRYVIEW(dev))
4845 chv_prepare_pll(intel_crtc);
4847 vlv_prepare_pll(intel_crtc);
4850 if (intel_crtc->config.has_dp_encoder)
4851 intel_dp_set_m_n(intel_crtc);
4853 intel_set_pipe_timings(intel_crtc);
4855 i9xx_set_pipeconf(intel_crtc);
4857 intel_crtc->active = true;
4859 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4861 for_each_encoder_on_crtc(dev, crtc, encoder)
4862 if (encoder->pre_pll_enable)
4863 encoder->pre_pll_enable(encoder);
4866 if (IS_CHERRYVIEW(dev))
4867 chv_enable_pll(intel_crtc);
4869 vlv_enable_pll(intel_crtc);
4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
4876 i9xx_pfit_enable(intel_crtc);
4878 intel_crtc_load_lut(crtc);
4880 intel_update_watermarks(crtc);
4881 intel_enable_pipe(intel_crtc);
4883 for_each_encoder_on_crtc(dev, crtc, encoder)
4884 encoder->enable(encoder);
4886 assert_vblank_disabled(crtc);
4887 drm_crtc_vblank_on(crtc);
4889 intel_crtc_enable_planes(crtc);
4891 /* Underruns don't raise interrupts, so check manually. */
4892 i9xx_check_fifo_underruns(dev_priv);
4895 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4897 struct drm_device *dev = crtc->base.dev;
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4900 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4901 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4904 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4906 struct drm_device *dev = crtc->dev;
4907 struct drm_i915_private *dev_priv = to_i915(dev);
4908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909 struct intel_encoder *encoder;
4910 int pipe = intel_crtc->pipe;
4912 WARN_ON(!crtc->enabled);
4914 if (intel_crtc->active)
4917 i9xx_set_pll_dividers(intel_crtc);
4919 if (intel_crtc->config.has_dp_encoder)
4920 intel_dp_set_m_n(intel_crtc);
4922 intel_set_pipe_timings(intel_crtc);
4924 i9xx_set_pipeconf(intel_crtc);
4926 intel_crtc->active = true;
4929 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4931 for_each_encoder_on_crtc(dev, crtc, encoder)
4932 if (encoder->pre_enable)
4933 encoder->pre_enable(encoder);
4935 i9xx_enable_pll(intel_crtc);
4937 i9xx_pfit_enable(intel_crtc);
4939 intel_crtc_load_lut(crtc);
4941 intel_update_watermarks(crtc);
4942 intel_enable_pipe(intel_crtc);
4944 for_each_encoder_on_crtc(dev, crtc, encoder)
4945 encoder->enable(encoder);
4947 assert_vblank_disabled(crtc);
4948 drm_crtc_vblank_on(crtc);
4950 intel_crtc_enable_planes(crtc);
4953 * Gen2 reports pipe underruns whenever all planes are disabled.
4954 * So don't enable underrun reporting before at least some planes
4956 * FIXME: Need to fix the logic to work when we turn off all planes
4957 * but leave the pipe running.
4960 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4962 /* Underruns don't raise interrupts, so check manually. */
4963 i9xx_check_fifo_underruns(dev_priv);
4966 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4968 struct drm_device *dev = crtc->base.dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4971 if (!crtc->config.gmch_pfit.control)
4974 assert_pipe_disabled(dev_priv, crtc->pipe);
4976 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4977 I915_READ(PFIT_CONTROL));
4978 I915_WRITE(PFIT_CONTROL, 0);
4981 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4983 struct drm_device *dev = crtc->dev;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986 struct intel_encoder *encoder;
4987 int pipe = intel_crtc->pipe;
4989 if (!intel_crtc->active)
4993 * Gen2 reports pipe underruns whenever all planes are disabled.
4994 * So diasble underrun reporting before all the planes get disabled.
4995 * FIXME: Need to fix the logic to work when we turn off all planes
4996 * but leave the pipe running.
4999 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5002 * Vblank time updates from the shadow to live plane control register
5003 * are blocked if the memory self-refresh mode is active at that
5004 * moment. So to make sure the plane gets truly disabled, disable
5005 * first the self-refresh mode. The self-refresh enable bit in turn
5006 * will be checked/applied by the HW only at the next frame start
5007 * event which is after the vblank start event, so we need to have a
5008 * wait-for-vblank between disabling the plane and the pipe.
5010 intel_set_memory_cxsr(dev_priv, false);
5011 intel_crtc_disable_planes(crtc);
5014 * On gen2 planes are double buffered but the pipe isn't, so we must
5015 * wait for planes to fully turn off before disabling the pipe.
5016 * We also need to wait on all gmch platforms because of the
5017 * self-refresh mode constraint explained above.
5019 intel_wait_for_vblank(dev, pipe);
5021 drm_crtc_vblank_off(crtc);
5022 assert_vblank_disabled(crtc);
5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 encoder->disable(encoder);
5027 intel_disable_pipe(intel_crtc);
5029 i9xx_pfit_disable(intel_crtc);
5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 if (encoder->post_disable)
5033 encoder->post_disable(encoder);
5035 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5036 if (IS_CHERRYVIEW(dev))
5037 chv_disable_pll(dev_priv, pipe);
5038 else if (IS_VALLEYVIEW(dev))
5039 vlv_disable_pll(dev_priv, pipe);
5041 i9xx_disable_pll(intel_crtc);
5045 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5047 intel_crtc->active = false;
5048 intel_update_watermarks(crtc);
5050 mutex_lock(&dev->struct_mutex);
5051 intel_update_fbc(dev);
5052 mutex_unlock(&dev->struct_mutex);
5055 static void i9xx_crtc_off(struct drm_crtc *crtc)
5059 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5062 struct drm_device *dev = crtc->dev;
5063 struct drm_i915_master_private *master_priv;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 int pipe = intel_crtc->pipe;
5067 if (!dev->primary->master)
5070 master_priv = dev->primary->master->driver_priv;
5071 if (!master_priv->sarea_priv)
5076 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5077 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5080 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5081 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5084 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5089 /* Master function to enable/disable CRTC and corresponding power wells */
5090 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095 enum intel_display_power_domain domain;
5096 unsigned long domains;
5099 if (!intel_crtc->active) {
5100 domains = get_crtc_power_domains(crtc);
5101 for_each_power_domain(domain, domains)
5102 intel_display_power_get(dev_priv, domain);
5103 intel_crtc->enabled_power_domains = domains;
5105 dev_priv->display.crtc_enable(crtc);
5108 if (intel_crtc->active) {
5109 dev_priv->display.crtc_disable(crtc);
5111 domains = intel_crtc->enabled_power_domains;
5112 for_each_power_domain(domain, domains)
5113 intel_display_power_put(dev_priv, domain);
5114 intel_crtc->enabled_power_domains = 0;
5120 * Sets the power management mode of the pipe and plane.
5122 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5124 struct drm_device *dev = crtc->dev;
5125 struct intel_encoder *intel_encoder;
5126 bool enable = false;
5128 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5129 enable |= intel_encoder->connectors_active;
5131 intel_crtc_control(crtc, enable);
5133 intel_crtc_update_sarea(crtc, enable);
5136 static void intel_crtc_disable(struct drm_crtc *crtc)
5138 struct drm_device *dev = crtc->dev;
5139 struct drm_connector *connector;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5142 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5144 /* crtc should still be enabled when we disable it. */
5145 WARN_ON(!crtc->enabled);
5147 dev_priv->display.crtc_disable(crtc);
5148 intel_crtc_update_sarea(crtc, false);
5149 dev_priv->display.off(crtc);
5151 if (crtc->primary->fb) {
5152 mutex_lock(&dev->struct_mutex);
5153 intel_unpin_fb_obj(old_obj);
5154 i915_gem_track_fb(old_obj, NULL,
5155 INTEL_FRONTBUFFER_PRIMARY(pipe));
5156 mutex_unlock(&dev->struct_mutex);
5157 crtc->primary->fb = NULL;
5160 /* Update computed state. */
5161 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5162 if (!connector->encoder || !connector->encoder->crtc)
5165 if (connector->encoder->crtc != crtc)
5168 connector->dpms = DRM_MODE_DPMS_OFF;
5169 to_intel_encoder(connector->encoder)->connectors_active = false;
5173 void intel_encoder_destroy(struct drm_encoder *encoder)
5175 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5177 drm_encoder_cleanup(encoder);
5178 kfree(intel_encoder);
5181 /* Simple dpms helper for encoders with just one connector, no cloning and only
5182 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5183 * state of the entire output pipe. */
5184 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5186 if (mode == DRM_MODE_DPMS_ON) {
5187 encoder->connectors_active = true;
5189 intel_crtc_update_dpms(encoder->base.crtc);
5191 encoder->connectors_active = false;
5193 intel_crtc_update_dpms(encoder->base.crtc);
5197 /* Cross check the actual hw state with our own modeset state tracking (and it's
5198 * internal consistency). */
5199 static void intel_connector_check_state(struct intel_connector *connector)
5201 if (connector->get_hw_state(connector)) {
5202 struct intel_encoder *encoder = connector->encoder;
5203 struct drm_crtc *crtc;
5204 bool encoder_enabled;
5207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5208 connector->base.base.id,
5209 connector->base.name);
5211 /* there is no real hw state for MST connectors */
5212 if (connector->mst_port)
5215 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5216 "wrong connector dpms state\n");
5217 WARN(connector->base.encoder != &encoder->base,
5218 "active connector not linked to encoder\n");
5221 WARN(!encoder->connectors_active,
5222 "encoder->connectors_active not set\n");
5224 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5225 WARN(!encoder_enabled, "encoder not enabled\n");
5226 if (WARN_ON(!encoder->base.crtc))
5229 crtc = encoder->base.crtc;
5231 WARN(!crtc->enabled, "crtc not enabled\n");
5232 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5233 WARN(pipe != to_intel_crtc(crtc)->pipe,
5234 "encoder active on the wrong pipe\n");
5239 /* Even simpler default implementation, if there's really no special case to
5241 void intel_connector_dpms(struct drm_connector *connector, int mode)
5243 /* All the simple cases only support two dpms states. */
5244 if (mode != DRM_MODE_DPMS_ON)
5245 mode = DRM_MODE_DPMS_OFF;
5247 if (mode == connector->dpms)
5250 connector->dpms = mode;
5252 /* Only need to change hw state when actually enabled */
5253 if (connector->encoder)
5254 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5256 intel_modeset_check_state(connector->dev);
5259 /* Simple connector->get_hw_state implementation for encoders that support only
5260 * one connector and no cloning and hence the encoder state determines the state
5261 * of the connector. */
5262 bool intel_connector_get_hw_state(struct intel_connector *connector)
5265 struct intel_encoder *encoder = connector->encoder;
5267 return encoder->get_hw_state(encoder, &pipe);
5270 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5271 struct intel_crtc_config *pipe_config)
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274 struct intel_crtc *pipe_B_crtc =
5275 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5277 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5278 pipe_name(pipe), pipe_config->fdi_lanes);
5279 if (pipe_config->fdi_lanes > 4) {
5280 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5281 pipe_name(pipe), pipe_config->fdi_lanes);
5285 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5286 if (pipe_config->fdi_lanes > 2) {
5287 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5288 pipe_config->fdi_lanes);
5295 if (INTEL_INFO(dev)->num_pipes == 2)
5298 /* Ivybridge 3 pipe is really complicated */
5303 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5304 pipe_config->fdi_lanes > 2) {
5305 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5306 pipe_name(pipe), pipe_config->fdi_lanes);
5311 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5312 pipe_B_crtc->config.fdi_lanes <= 2) {
5313 if (pipe_config->fdi_lanes > 2) {
5314 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5315 pipe_name(pipe), pipe_config->fdi_lanes);
5319 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5329 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5330 struct intel_crtc_config *pipe_config)
5332 struct drm_device *dev = intel_crtc->base.dev;
5333 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5334 int lane, link_bw, fdi_dotclock;
5335 bool setup_ok, needs_recompute = false;
5338 /* FDI is a binary signal running at ~2.7GHz, encoding
5339 * each output octet as 10 bits. The actual frequency
5340 * is stored as a divider into a 100MHz clock, and the
5341 * mode pixel clock is stored in units of 1KHz.
5342 * Hence the bw of each lane in terms of the mode signal
5345 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5347 fdi_dotclock = adjusted_mode->crtc_clock;
5349 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5350 pipe_config->pipe_bpp);
5352 pipe_config->fdi_lanes = lane;
5354 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5355 link_bw, &pipe_config->fdi_m_n);
5357 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5358 intel_crtc->pipe, pipe_config);
5359 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5360 pipe_config->pipe_bpp -= 2*3;
5361 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5362 pipe_config->pipe_bpp);
5363 needs_recompute = true;
5364 pipe_config->bw_constrained = true;
5369 if (needs_recompute)
5372 return setup_ok ? 0 : -EINVAL;
5375 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5376 struct intel_crtc_config *pipe_config)
5378 pipe_config->ips_enabled = i915.enable_ips &&
5379 hsw_crtc_supports_ips(crtc) &&
5380 pipe_config->pipe_bpp <= 24;
5383 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5384 struct intel_crtc_config *pipe_config)
5386 struct drm_device *dev = crtc->base.dev;
5387 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5389 /* FIXME should check pixel clock limits on all platforms */
5390 if (INTEL_INFO(dev)->gen < 4) {
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5393 dev_priv->display.get_display_clock_speed(dev);
5396 * Enable pixel doubling when the dot clock
5397 * is > 90% of the (display) core speed.
5399 * GDG double wide on either pipe,
5400 * otherwise pipe A only.
5402 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5403 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5405 pipe_config->double_wide = true;
5408 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5413 * Pipe horizontal size must be even in:
5415 * - LVDS dual channel mode
5416 * - Double wide pipe
5418 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5420 pipe_config->pipe_src_w &= ~1;
5422 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5423 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5425 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5426 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5429 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5430 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5431 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5432 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5434 pipe_config->pipe_bpp = 8*3;
5438 hsw_compute_ips_config(crtc, pipe_config);
5441 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5442 * old clock survives for now.
5444 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5445 pipe_config->shared_dpll = crtc->config.shared_dpll;
5447 if (pipe_config->has_pch_encoder)
5448 return ironlake_fdi_compute_config(crtc, pipe_config);
5453 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 int vco = valleyview_get_vco(dev_priv);
5460 /* FIXME: Punit isn't quite ready yet */
5461 if (IS_CHERRYVIEW(dev))
5464 mutex_lock(&dev_priv->dpio_lock);
5465 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5466 mutex_unlock(&dev_priv->dpio_lock);
5468 divider = val & DISPLAY_FREQUENCY_VALUES;
5470 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5471 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5472 "cdclk change in progress\n");
5474 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5477 static int i945_get_display_clock_speed(struct drm_device *dev)
5482 static int i915_get_display_clock_speed(struct drm_device *dev)
5487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5492 static int pnv_get_display_clock_speed(struct drm_device *dev)
5496 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5498 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5499 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5501 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5503 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5505 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5508 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5509 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5511 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5516 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5520 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5522 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5525 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5526 case GC_DISPLAY_CLOCK_333_MHZ:
5529 case GC_DISPLAY_CLOCK_190_200_MHZ:
5535 static int i865_get_display_clock_speed(struct drm_device *dev)
5540 static int i855_get_display_clock_speed(struct drm_device *dev)
5543 /* Assume that the hardware is in the high speed state. This
5544 * should be the default.
5546 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5547 case GC_CLOCK_133_200:
5548 case GC_CLOCK_100_200:
5550 case GC_CLOCK_166_250:
5552 case GC_CLOCK_100_133:
5556 /* Shouldn't happen */
5560 static int i830_get_display_clock_speed(struct drm_device *dev)
5566 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5568 while (*num > DATA_LINK_M_N_MASK ||
5569 *den > DATA_LINK_M_N_MASK) {
5575 static void compute_m_n(unsigned int m, unsigned int n,
5576 uint32_t *ret_m, uint32_t *ret_n)
5578 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5579 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5580 intel_reduce_m_n_ratio(ret_m, ret_n);
5584 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5585 int pixel_clock, int link_clock,
5586 struct intel_link_m_n *m_n)
5590 compute_m_n(bits_per_pixel * pixel_clock,
5591 link_clock * nlanes * 8,
5592 &m_n->gmch_m, &m_n->gmch_n);
5594 compute_m_n(pixel_clock, link_clock,
5595 &m_n->link_m, &m_n->link_n);
5598 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5600 if (i915.panel_use_ssc >= 0)
5601 return i915.panel_use_ssc != 0;
5602 return dev_priv->vbt.lvds_use_ssc
5603 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5606 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5608 struct drm_device *dev = crtc->base.dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5612 if (IS_VALLEYVIEW(dev)) {
5614 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5615 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5616 refclk = dev_priv->vbt.lvds_ssc_freq;
5617 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5618 } else if (!IS_GEN2(dev)) {
5627 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5629 return (1 << dpll->n) << 16 | dpll->m2;
5632 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5634 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5637 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5638 intel_clock_t *reduced_clock)
5640 struct drm_device *dev = crtc->base.dev;
5643 if (IS_PINEVIEW(dev)) {
5644 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5646 fp2 = pnv_dpll_compute_fp(reduced_clock);
5648 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5650 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5653 crtc->config.dpll_hw_state.fp0 = fp;
5655 crtc->lowfreq_avail = false;
5656 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5657 reduced_clock && i915.powersave) {
5658 crtc->config.dpll_hw_state.fp1 = fp2;
5659 crtc->lowfreq_avail = true;
5661 crtc->config.dpll_hw_state.fp1 = fp;
5665 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5671 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5672 * and set it to a reasonable value instead.
5674 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5675 reg_val &= 0xffffff00;
5676 reg_val |= 0x00000030;
5677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5679 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5680 reg_val &= 0x8cffffff;
5681 reg_val = 0x8c000000;
5682 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5684 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5685 reg_val &= 0xffffff00;
5686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5688 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5689 reg_val &= 0x00ffffff;
5690 reg_val |= 0xb0000000;
5691 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5694 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5695 struct intel_link_m_n *m_n)
5697 struct drm_device *dev = crtc->base.dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 int pipe = crtc->pipe;
5701 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5702 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5703 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5704 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5707 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5708 struct intel_link_m_n *m_n,
5709 struct intel_link_m_n *m2_n2)
5711 struct drm_device *dev = crtc->base.dev;
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 int pipe = crtc->pipe;
5714 enum transcoder transcoder = crtc->config.cpu_transcoder;
5716 if (INTEL_INFO(dev)->gen >= 5) {
5717 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5718 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5719 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5720 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5721 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5722 * for gen < 8) and if DRRS is supported (to make sure the
5723 * registers are not unnecessarily accessed).
5725 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5726 crtc->config.has_drrs) {
5727 I915_WRITE(PIPE_DATA_M2(transcoder),
5728 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5729 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5730 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5731 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5734 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5736 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5737 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5741 void intel_dp_set_m_n(struct intel_crtc *crtc)
5743 if (crtc->config.has_pch_encoder)
5744 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5746 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5747 &crtc->config.dp_m2_n2);
5750 static void vlv_update_pll(struct intel_crtc *crtc)
5755 * Enable DPIO clock input. We should never disable the reference
5756 * clock for pipe B, since VGA hotplug / manual detection depends
5759 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5760 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5761 /* We should never disable this, set it here for state tracking */
5762 if (crtc->pipe == PIPE_B)
5763 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5764 dpll |= DPLL_VCO_ENABLE;
5765 crtc->config.dpll_hw_state.dpll = dpll;
5767 dpll_md = (crtc->config.pixel_multiplier - 1)
5768 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5769 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5772 static void vlv_prepare_pll(struct intel_crtc *crtc)
5774 struct drm_device *dev = crtc->base.dev;
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5776 int pipe = crtc->pipe;
5778 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5779 u32 coreclk, reg_val;
5781 mutex_lock(&dev_priv->dpio_lock);
5783 bestn = crtc->config.dpll.n;
5784 bestm1 = crtc->config.dpll.m1;
5785 bestm2 = crtc->config.dpll.m2;
5786 bestp1 = crtc->config.dpll.p1;
5787 bestp2 = crtc->config.dpll.p2;
5789 /* See eDP HDMI DPIO driver vbios notes doc */
5791 /* PLL B needs special handling */
5793 vlv_pllb_recal_opamp(dev_priv, pipe);
5795 /* Set up Tx target for periodic Rcomp update */
5796 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5798 /* Disable target IRef on PLL */
5799 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5800 reg_val &= 0x00ffffff;
5801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5803 /* Disable fast lock */
5804 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5806 /* Set idtafcrecal before PLL is enabled */
5807 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5808 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5809 mdiv |= ((bestn << DPIO_N_SHIFT));
5810 mdiv |= (1 << DPIO_K_SHIFT);
5813 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5814 * but we don't support that).
5815 * Note: don't use the DAC post divider as it seems unstable.
5817 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5818 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5820 mdiv |= DPIO_ENABLE_CALIBRATION;
5821 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5823 /* Set HBR and RBR LPF coefficients */
5824 if (crtc->config.port_clock == 162000 ||
5825 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5826 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5833 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5834 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5835 /* Use SSC source */
5837 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5840 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5842 } else { /* HDMI or VGA */
5843 /* Use bend source */
5845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5848 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5852 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5853 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5854 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5855 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5856 coreclk |= 0x01000000;
5857 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5859 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5860 mutex_unlock(&dev_priv->dpio_lock);
5863 static void chv_update_pll(struct intel_crtc *crtc)
5865 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5866 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5868 if (crtc->pipe != PIPE_A)
5869 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5871 crtc->config.dpll_hw_state.dpll_md =
5872 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5875 static void chv_prepare_pll(struct intel_crtc *crtc)
5877 struct drm_device *dev = crtc->base.dev;
5878 struct drm_i915_private *dev_priv = dev->dev_private;
5879 int pipe = crtc->pipe;
5880 int dpll_reg = DPLL(crtc->pipe);
5881 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5882 u32 loopfilter, intcoeff;
5883 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5886 bestn = crtc->config.dpll.n;
5887 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5888 bestm1 = crtc->config.dpll.m1;
5889 bestm2 = crtc->config.dpll.m2 >> 22;
5890 bestp1 = crtc->config.dpll.p1;
5891 bestp2 = crtc->config.dpll.p2;
5894 * Enable Refclk and SSC
5896 I915_WRITE(dpll_reg,
5897 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5899 mutex_lock(&dev_priv->dpio_lock);
5901 /* p1 and p2 divider */
5902 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5903 5 << DPIO_CHV_S1_DIV_SHIFT |
5904 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5905 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5906 1 << DPIO_CHV_K_DIV_SHIFT);
5908 /* Feedback post-divider - m2 */
5909 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5911 /* Feedback refclk divider - n and m1 */
5912 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5913 DPIO_CHV_M1_DIV_BY_2 |
5914 1 << DPIO_CHV_N_DIV_SHIFT);
5916 /* M2 fraction division */
5917 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5919 /* M2 fraction division enable */
5920 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5921 DPIO_CHV_FRAC_DIV_EN |
5922 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5925 refclk = i9xx_get_refclk(crtc, 0);
5926 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5927 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5928 if (refclk == 100000)
5930 else if (refclk == 38400)
5934 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5935 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5938 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5939 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5942 mutex_unlock(&dev_priv->dpio_lock);
5945 static void i9xx_update_pll(struct intel_crtc *crtc,
5946 intel_clock_t *reduced_clock,
5949 struct drm_device *dev = crtc->base.dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5953 struct dpll *clock = &crtc->config.dpll;
5955 i9xx_update_pll_dividers(crtc, reduced_clock);
5957 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5958 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5960 dpll = DPLL_VGA_MODE_DIS;
5962 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5963 dpll |= DPLLB_MODE_LVDS;
5965 dpll |= DPLLB_MODE_DAC_SERIAL;
5967 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5968 dpll |= (crtc->config.pixel_multiplier - 1)
5969 << SDVO_MULTIPLIER_SHIFT_HIRES;
5973 dpll |= DPLL_SDVO_HIGH_SPEED;
5975 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5976 dpll |= DPLL_SDVO_HIGH_SPEED;
5978 /* compute bitmask from p1 value */
5979 if (IS_PINEVIEW(dev))
5980 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5982 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5983 if (IS_G4X(dev) && reduced_clock)
5984 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5986 switch (clock->p2) {
5988 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5991 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5994 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5997 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6000 if (INTEL_INFO(dev)->gen >= 4)
6001 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6003 if (crtc->config.sdvo_tv_clock)
6004 dpll |= PLL_REF_INPUT_TVCLKINBC;
6005 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6006 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6007 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6009 dpll |= PLL_REF_INPUT_DREFCLK;
6011 dpll |= DPLL_VCO_ENABLE;
6012 crtc->config.dpll_hw_state.dpll = dpll;
6014 if (INTEL_INFO(dev)->gen >= 4) {
6015 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6016 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6021 static void i8xx_update_pll(struct intel_crtc *crtc,
6022 intel_clock_t *reduced_clock,
6025 struct drm_device *dev = crtc->base.dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6028 struct dpll *clock = &crtc->config.dpll;
6030 i9xx_update_pll_dividers(crtc, reduced_clock);
6032 dpll = DPLL_VGA_MODE_DIS;
6034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6038 dpll |= PLL_P1_DIVIDE_BY_TWO;
6040 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6042 dpll |= PLL_P2_DIVIDE_BY_4;
6045 if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6046 dpll |= DPLL_DVO_2X_MODE;
6048 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6049 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6050 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6052 dpll |= PLL_REF_INPUT_DREFCLK;
6054 dpll |= DPLL_VCO_ENABLE;
6055 crtc->config.dpll_hw_state.dpll = dpll;
6058 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6060 struct drm_device *dev = intel_crtc->base.dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 enum pipe pipe = intel_crtc->pipe;
6063 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6064 struct drm_display_mode *adjusted_mode =
6065 &intel_crtc->config.adjusted_mode;
6066 uint32_t crtc_vtotal, crtc_vblank_end;
6069 /* We need to be careful not to changed the adjusted mode, for otherwise
6070 * the hw state checker will get angry at the mismatch. */
6071 crtc_vtotal = adjusted_mode->crtc_vtotal;
6072 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6074 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6075 /* the chip adds 2 halflines automatically */
6077 crtc_vblank_end -= 1;
6079 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6080 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6082 vsyncshift = adjusted_mode->crtc_hsync_start -
6083 adjusted_mode->crtc_htotal / 2;
6085 vsyncshift += adjusted_mode->crtc_htotal;
6088 if (INTEL_INFO(dev)->gen > 3)
6089 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6091 I915_WRITE(HTOTAL(cpu_transcoder),
6092 (adjusted_mode->crtc_hdisplay - 1) |
6093 ((adjusted_mode->crtc_htotal - 1) << 16));
6094 I915_WRITE(HBLANK(cpu_transcoder),
6095 (adjusted_mode->crtc_hblank_start - 1) |
6096 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6097 I915_WRITE(HSYNC(cpu_transcoder),
6098 (adjusted_mode->crtc_hsync_start - 1) |
6099 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6101 I915_WRITE(VTOTAL(cpu_transcoder),
6102 (adjusted_mode->crtc_vdisplay - 1) |
6103 ((crtc_vtotal - 1) << 16));
6104 I915_WRITE(VBLANK(cpu_transcoder),
6105 (adjusted_mode->crtc_vblank_start - 1) |
6106 ((crtc_vblank_end - 1) << 16));
6107 I915_WRITE(VSYNC(cpu_transcoder),
6108 (adjusted_mode->crtc_vsync_start - 1) |
6109 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6111 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6112 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6113 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6115 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6116 (pipe == PIPE_B || pipe == PIPE_C))
6117 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6119 /* pipesrc controls the size that is scaled from, which should
6120 * always be the user's requested size.
6122 I915_WRITE(PIPESRC(pipe),
6123 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6124 (intel_crtc->config.pipe_src_h - 1));
6127 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6128 struct intel_crtc_config *pipe_config)
6130 struct drm_device *dev = crtc->base.dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6135 tmp = I915_READ(HTOTAL(cpu_transcoder));
6136 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6137 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6138 tmp = I915_READ(HBLANK(cpu_transcoder));
6139 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6140 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6141 tmp = I915_READ(HSYNC(cpu_transcoder));
6142 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6143 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6145 tmp = I915_READ(VTOTAL(cpu_transcoder));
6146 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6147 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6148 tmp = I915_READ(VBLANK(cpu_transcoder));
6149 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6150 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6151 tmp = I915_READ(VSYNC(cpu_transcoder));
6152 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6153 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6155 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6156 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6157 pipe_config->adjusted_mode.crtc_vtotal += 1;
6158 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6161 tmp = I915_READ(PIPESRC(crtc->pipe));
6162 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6163 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6165 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6166 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6169 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6170 struct intel_crtc_config *pipe_config)
6172 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6173 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6174 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6175 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6177 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6178 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6179 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6180 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6182 mode->flags = pipe_config->adjusted_mode.flags;
6184 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6185 mode->flags |= pipe_config->adjusted_mode.flags;
6188 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6190 struct drm_device *dev = intel_crtc->base.dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6196 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6197 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6198 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6200 if (intel_crtc->config.double_wide)
6201 pipeconf |= PIPECONF_DOUBLE_WIDE;
6203 /* only g4x and later have fancy bpc/dither controls */
6204 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6205 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6206 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6207 pipeconf |= PIPECONF_DITHER_EN |
6208 PIPECONF_DITHER_TYPE_SP;
6210 switch (intel_crtc->config.pipe_bpp) {
6212 pipeconf |= PIPECONF_6BPC;
6215 pipeconf |= PIPECONF_8BPC;
6218 pipeconf |= PIPECONF_10BPC;
6221 /* Case prevented by intel_choose_pipe_bpp_dither. */
6226 if (HAS_PIPE_CXSR(dev)) {
6227 if (intel_crtc->lowfreq_avail) {
6228 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6229 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6231 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6235 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6236 if (INTEL_INFO(dev)->gen < 4 ||
6237 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6238 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6240 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6242 pipeconf |= PIPECONF_PROGRESSIVE;
6244 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6245 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6247 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6248 POSTING_READ(PIPECONF(intel_crtc->pipe));
6251 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6253 struct drm_framebuffer *fb)
6255 struct drm_device *dev = crtc->base.dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 int refclk, num_connectors = 0;
6258 intel_clock_t clock, reduced_clock;
6259 bool ok, has_reduced_clock = false;
6260 bool is_lvds = false, is_dsi = false;
6261 struct intel_encoder *encoder;
6262 const intel_limit_t *limit;
6264 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6265 switch (encoder->type) {
6266 case INTEL_OUTPUT_LVDS:
6269 case INTEL_OUTPUT_DSI:
6280 if (!crtc->config.clock_set) {
6281 refclk = i9xx_get_refclk(crtc, num_connectors);
6284 * Returns a set of divisors for the desired target clock with
6285 * the given refclk, or FALSE. The returned values represent
6286 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6289 limit = intel_limit(crtc, refclk);
6290 ok = dev_priv->display.find_dpll(limit, crtc,
6291 crtc->config.port_clock,
6292 refclk, NULL, &clock);
6294 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6298 if (is_lvds && dev_priv->lvds_downclock_avail) {
6300 * Ensure we match the reduced clock's P to the target
6301 * clock. If the clocks don't match, we can't switch
6302 * the display clock by using the FP0/FP1. In such case
6303 * we will disable the LVDS downclock feature.
6306 dev_priv->display.find_dpll(limit, crtc,
6307 dev_priv->lvds_downclock,
6311 /* Compat-code for transition, will disappear. */
6312 crtc->config.dpll.n = clock.n;
6313 crtc->config.dpll.m1 = clock.m1;
6314 crtc->config.dpll.m2 = clock.m2;
6315 crtc->config.dpll.p1 = clock.p1;
6316 crtc->config.dpll.p2 = clock.p2;
6320 i8xx_update_pll(crtc,
6321 has_reduced_clock ? &reduced_clock : NULL,
6323 } else if (IS_CHERRYVIEW(dev)) {
6324 chv_update_pll(crtc);
6325 } else if (IS_VALLEYVIEW(dev)) {
6326 vlv_update_pll(crtc);
6328 i9xx_update_pll(crtc,
6329 has_reduced_clock ? &reduced_clock : NULL,
6336 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6337 struct intel_crtc_config *pipe_config)
6339 struct drm_device *dev = crtc->base.dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6343 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6346 tmp = I915_READ(PFIT_CONTROL);
6347 if (!(tmp & PFIT_ENABLE))
6350 /* Check whether the pfit is attached to our pipe. */
6351 if (INTEL_INFO(dev)->gen < 4) {
6352 if (crtc->pipe != PIPE_B)
6355 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6359 pipe_config->gmch_pfit.control = tmp;
6360 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6361 if (INTEL_INFO(dev)->gen < 5)
6362 pipe_config->gmch_pfit.lvds_border_bits =
6363 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6366 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6367 struct intel_crtc_config *pipe_config)
6369 struct drm_device *dev = crtc->base.dev;
6370 struct drm_i915_private *dev_priv = dev->dev_private;
6371 int pipe = pipe_config->cpu_transcoder;
6372 intel_clock_t clock;
6374 int refclk = 100000;
6376 /* In case of MIPI DPLL will not even be used */
6377 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6380 mutex_lock(&dev_priv->dpio_lock);
6381 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6382 mutex_unlock(&dev_priv->dpio_lock);
6384 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6385 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6386 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6387 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6388 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6390 vlv_clock(refclk, &clock);
6392 /* clock.dot is the fast clock */
6393 pipe_config->port_clock = clock.dot / 5;
6396 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6397 struct intel_plane_config *plane_config)
6399 struct drm_device *dev = crtc->base.dev;
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6401 u32 val, base, offset;
6402 int pipe = crtc->pipe, plane = crtc->plane;
6403 int fourcc, pixel_format;
6406 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6407 if (!crtc->base.primary->fb) {
6408 DRM_DEBUG_KMS("failed to alloc fb\n");
6412 val = I915_READ(DSPCNTR(plane));
6414 if (INTEL_INFO(dev)->gen >= 4)
6415 if (val & DISPPLANE_TILED)
6416 plane_config->tiled = true;
6418 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6419 fourcc = intel_format_to_fourcc(pixel_format);
6420 crtc->base.primary->fb->pixel_format = fourcc;
6421 crtc->base.primary->fb->bits_per_pixel =
6422 drm_format_plane_cpp(fourcc, 0) * 8;
6424 if (INTEL_INFO(dev)->gen >= 4) {
6425 if (plane_config->tiled)
6426 offset = I915_READ(DSPTILEOFF(plane));
6428 offset = I915_READ(DSPLINOFF(plane));
6429 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6431 base = I915_READ(DSPADDR(plane));
6433 plane_config->base = base;
6435 val = I915_READ(PIPESRC(pipe));
6436 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6437 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6439 val = I915_READ(DSPSTRIDE(pipe));
6440 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6442 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6443 plane_config->tiled);
6445 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6448 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6449 pipe, plane, crtc->base.primary->fb->width,
6450 crtc->base.primary->fb->height,
6451 crtc->base.primary->fb->bits_per_pixel, base,
6452 crtc->base.primary->fb->pitches[0],
6453 plane_config->size);
6457 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6458 struct intel_crtc_config *pipe_config)
6460 struct drm_device *dev = crtc->base.dev;
6461 struct drm_i915_private *dev_priv = dev->dev_private;
6462 int pipe = pipe_config->cpu_transcoder;
6463 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6464 intel_clock_t clock;
6465 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6466 int refclk = 100000;
6468 mutex_lock(&dev_priv->dpio_lock);
6469 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6470 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6471 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6472 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6473 mutex_unlock(&dev_priv->dpio_lock);
6475 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6476 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6477 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6478 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6479 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6481 chv_clock(refclk, &clock);
6483 /* clock.dot is the fast clock */
6484 pipe_config->port_clock = clock.dot / 5;
6487 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6488 struct intel_crtc_config *pipe_config)
6490 struct drm_device *dev = crtc->base.dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6494 if (!intel_display_power_is_enabled(dev_priv,
6495 POWER_DOMAIN_PIPE(crtc->pipe)))
6498 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6499 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6501 tmp = I915_READ(PIPECONF(crtc->pipe));
6502 if (!(tmp & PIPECONF_ENABLE))
6505 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6506 switch (tmp & PIPECONF_BPC_MASK) {
6508 pipe_config->pipe_bpp = 18;
6511 pipe_config->pipe_bpp = 24;
6513 case PIPECONF_10BPC:
6514 pipe_config->pipe_bpp = 30;
6521 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6522 pipe_config->limited_color_range = true;
6524 if (INTEL_INFO(dev)->gen < 4)
6525 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6527 intel_get_pipe_timings(crtc, pipe_config);
6529 i9xx_get_pfit_config(crtc, pipe_config);
6531 if (INTEL_INFO(dev)->gen >= 4) {
6532 tmp = I915_READ(DPLL_MD(crtc->pipe));
6533 pipe_config->pixel_multiplier =
6534 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6535 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6536 pipe_config->dpll_hw_state.dpll_md = tmp;
6537 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6538 tmp = I915_READ(DPLL(crtc->pipe));
6539 pipe_config->pixel_multiplier =
6540 ((tmp & SDVO_MULTIPLIER_MASK)
6541 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6543 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6544 * port and will be fixed up in the encoder->get_config
6546 pipe_config->pixel_multiplier = 1;
6548 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6549 if (!IS_VALLEYVIEW(dev)) {
6551 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6552 * on 830. Filter it out here so that we don't
6553 * report errors due to that.
6556 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6558 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6559 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6561 /* Mask out read-only status bits. */
6562 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6563 DPLL_PORTC_READY_MASK |
6564 DPLL_PORTB_READY_MASK);
6567 if (IS_CHERRYVIEW(dev))
6568 chv_crtc_clock_get(crtc, pipe_config);
6569 else if (IS_VALLEYVIEW(dev))
6570 vlv_crtc_clock_get(crtc, pipe_config);
6572 i9xx_crtc_clock_get(crtc, pipe_config);
6577 static void ironlake_init_pch_refclk(struct drm_device *dev)
6579 struct drm_i915_private *dev_priv = dev->dev_private;
6580 struct intel_encoder *encoder;
6582 bool has_lvds = false;
6583 bool has_cpu_edp = false;
6584 bool has_panel = false;
6585 bool has_ck505 = false;
6586 bool can_ssc = false;
6588 /* We need to take the global config into account */
6589 for_each_intel_encoder(dev, encoder) {
6590 switch (encoder->type) {
6591 case INTEL_OUTPUT_LVDS:
6595 case INTEL_OUTPUT_EDP:
6597 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6603 if (HAS_PCH_IBX(dev)) {
6604 has_ck505 = dev_priv->vbt.display_clock_mode;
6605 can_ssc = has_ck505;
6611 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6612 has_panel, has_lvds, has_ck505);
6614 /* Ironlake: try to setup display ref clock before DPLL
6615 * enabling. This is only under driver's control after
6616 * PCH B stepping, previous chipset stepping should be
6617 * ignoring this setting.
6619 val = I915_READ(PCH_DREF_CONTROL);
6621 /* As we must carefully and slowly disable/enable each source in turn,
6622 * compute the final state we want first and check if we need to
6623 * make any changes at all.
6626 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6628 final |= DREF_NONSPREAD_CK505_ENABLE;
6630 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6632 final &= ~DREF_SSC_SOURCE_MASK;
6633 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6634 final &= ~DREF_SSC1_ENABLE;
6637 final |= DREF_SSC_SOURCE_ENABLE;
6639 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6640 final |= DREF_SSC1_ENABLE;
6643 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6644 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6646 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6648 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6650 final |= DREF_SSC_SOURCE_DISABLE;
6651 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6657 /* Always enable nonspread source */
6658 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6661 val |= DREF_NONSPREAD_CK505_ENABLE;
6663 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6666 val &= ~DREF_SSC_SOURCE_MASK;
6667 val |= DREF_SSC_SOURCE_ENABLE;
6669 /* SSC must be turned on before enabling the CPU output */
6670 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6671 DRM_DEBUG_KMS("Using SSC on panel\n");
6672 val |= DREF_SSC1_ENABLE;
6674 val &= ~DREF_SSC1_ENABLE;
6676 /* Get SSC going before enabling the outputs */
6677 I915_WRITE(PCH_DREF_CONTROL, val);
6678 POSTING_READ(PCH_DREF_CONTROL);
6681 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6683 /* Enable CPU source on CPU attached eDP */
6685 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6686 DRM_DEBUG_KMS("Using SSC on eDP\n");
6687 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6689 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6691 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6693 I915_WRITE(PCH_DREF_CONTROL, val);
6694 POSTING_READ(PCH_DREF_CONTROL);
6697 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6699 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6701 /* Turn off CPU output */
6702 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6704 I915_WRITE(PCH_DREF_CONTROL, val);
6705 POSTING_READ(PCH_DREF_CONTROL);
6708 /* Turn off the SSC source */
6709 val &= ~DREF_SSC_SOURCE_MASK;
6710 val |= DREF_SSC_SOURCE_DISABLE;
6713 val &= ~DREF_SSC1_ENABLE;
6715 I915_WRITE(PCH_DREF_CONTROL, val);
6716 POSTING_READ(PCH_DREF_CONTROL);
6720 BUG_ON(val != final);
6723 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6727 tmp = I915_READ(SOUTH_CHICKEN2);
6728 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6729 I915_WRITE(SOUTH_CHICKEN2, tmp);
6731 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6732 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6733 DRM_ERROR("FDI mPHY reset assert timeout\n");
6735 tmp = I915_READ(SOUTH_CHICKEN2);
6736 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6737 I915_WRITE(SOUTH_CHICKEN2, tmp);
6739 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6740 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6741 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6744 /* WaMPhyProgramming:hsw */
6745 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6749 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6750 tmp &= ~(0xFF << 24);
6751 tmp |= (0x12 << 24);
6752 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6754 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6756 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6758 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6760 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6762 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6763 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6764 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6766 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6767 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6768 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6770 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6773 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6775 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6778 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6780 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6783 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6785 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6788 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6790 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6791 tmp &= ~(0xFF << 16);
6792 tmp |= (0x1C << 16);
6793 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6795 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6796 tmp &= ~(0xFF << 16);
6797 tmp |= (0x1C << 16);
6798 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6800 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6802 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6804 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6806 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6808 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6809 tmp &= ~(0xF << 28);
6811 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6813 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6814 tmp &= ~(0xF << 28);
6816 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6819 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6820 * Programming" based on the parameters passed:
6821 * - Sequence to enable CLKOUT_DP
6822 * - Sequence to enable CLKOUT_DP without spread
6823 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6825 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6828 struct drm_i915_private *dev_priv = dev->dev_private;
6831 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6833 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6834 with_fdi, "LP PCH doesn't have FDI\n"))
6837 mutex_lock(&dev_priv->dpio_lock);
6839 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6840 tmp &= ~SBI_SSCCTL_DISABLE;
6841 tmp |= SBI_SSCCTL_PATHALT;
6842 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6847 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6848 tmp &= ~SBI_SSCCTL_PATHALT;
6849 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6852 lpt_reset_fdi_mphy(dev_priv);
6853 lpt_program_fdi_mphy(dev_priv);
6857 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6858 SBI_GEN0 : SBI_DBUFF0;
6859 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6860 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6861 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6863 mutex_unlock(&dev_priv->dpio_lock);
6866 /* Sequence to disable CLKOUT_DP */
6867 static void lpt_disable_clkout_dp(struct drm_device *dev)
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6872 mutex_lock(&dev_priv->dpio_lock);
6874 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6875 SBI_GEN0 : SBI_DBUFF0;
6876 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6877 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6878 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6880 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6881 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6882 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6883 tmp |= SBI_SSCCTL_PATHALT;
6884 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6887 tmp |= SBI_SSCCTL_DISABLE;
6888 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6891 mutex_unlock(&dev_priv->dpio_lock);
6894 static void lpt_init_pch_refclk(struct drm_device *dev)
6896 struct intel_encoder *encoder;
6897 bool has_vga = false;
6899 for_each_intel_encoder(dev, encoder) {
6900 switch (encoder->type) {
6901 case INTEL_OUTPUT_ANALOG:
6908 lpt_enable_clkout_dp(dev, true, true);
6910 lpt_disable_clkout_dp(dev);
6914 * Initialize reference clocks when the driver loads
6916 void intel_init_pch_refclk(struct drm_device *dev)
6918 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6919 ironlake_init_pch_refclk(dev);
6920 else if (HAS_PCH_LPT(dev))
6921 lpt_init_pch_refclk(dev);
6924 static int ironlake_get_refclk(struct drm_crtc *crtc)
6926 struct drm_device *dev = crtc->dev;
6927 struct drm_i915_private *dev_priv = dev->dev_private;
6928 struct intel_encoder *encoder;
6929 int num_connectors = 0;
6930 bool is_lvds = false;
6932 for_each_encoder_on_crtc(dev, crtc, encoder) {
6933 switch (encoder->type) {
6934 case INTEL_OUTPUT_LVDS:
6941 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6942 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6943 dev_priv->vbt.lvds_ssc_freq);
6944 return dev_priv->vbt.lvds_ssc_freq;
6950 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6952 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6954 int pipe = intel_crtc->pipe;
6959 switch (intel_crtc->config.pipe_bpp) {
6961 val |= PIPECONF_6BPC;
6964 val |= PIPECONF_8BPC;
6967 val |= PIPECONF_10BPC;
6970 val |= PIPECONF_12BPC;
6973 /* Case prevented by intel_choose_pipe_bpp_dither. */
6977 if (intel_crtc->config.dither)
6978 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6980 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6981 val |= PIPECONF_INTERLACED_ILK;
6983 val |= PIPECONF_PROGRESSIVE;
6985 if (intel_crtc->config.limited_color_range)
6986 val |= PIPECONF_COLOR_RANGE_SELECT;
6988 I915_WRITE(PIPECONF(pipe), val);
6989 POSTING_READ(PIPECONF(pipe));
6993 * Set up the pipe CSC unit.
6995 * Currently only full range RGB to limited range RGB conversion
6996 * is supported, but eventually this should handle various
6997 * RGB<->YCbCr scenarios as well.
6999 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7001 struct drm_device *dev = crtc->dev;
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7004 int pipe = intel_crtc->pipe;
7005 uint16_t coeff = 0x7800; /* 1.0 */
7008 * TODO: Check what kind of values actually come out of the pipe
7009 * with these coeff/postoff values and adjust to get the best
7010 * accuracy. Perhaps we even need to take the bpc value into
7014 if (intel_crtc->config.limited_color_range)
7015 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7018 * GY/GU and RY/RU should be the other way around according
7019 * to BSpec, but reality doesn't agree. Just set them up in
7020 * a way that results in the correct picture.
7022 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7023 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7025 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7026 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7028 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7029 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7031 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7032 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7033 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7035 if (INTEL_INFO(dev)->gen > 6) {
7036 uint16_t postoff = 0;
7038 if (intel_crtc->config.limited_color_range)
7039 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7041 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7042 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7043 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7045 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7047 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7049 if (intel_crtc->config.limited_color_range)
7050 mode |= CSC_BLACK_SCREEN_OFFSET;
7052 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7056 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7058 struct drm_device *dev = crtc->dev;
7059 struct drm_i915_private *dev_priv = dev->dev_private;
7060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7061 enum pipe pipe = intel_crtc->pipe;
7062 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7067 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7068 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7070 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7071 val |= PIPECONF_INTERLACED_ILK;
7073 val |= PIPECONF_PROGRESSIVE;
7075 I915_WRITE(PIPECONF(cpu_transcoder), val);
7076 POSTING_READ(PIPECONF(cpu_transcoder));
7078 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7079 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7081 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7084 switch (intel_crtc->config.pipe_bpp) {
7086 val |= PIPEMISC_DITHER_6_BPC;
7089 val |= PIPEMISC_DITHER_8_BPC;
7092 val |= PIPEMISC_DITHER_10_BPC;
7095 val |= PIPEMISC_DITHER_12_BPC;
7098 /* Case prevented by pipe_config_set_bpp. */
7102 if (intel_crtc->config.dither)
7103 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7105 I915_WRITE(PIPEMISC(pipe), val);
7109 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7110 intel_clock_t *clock,
7111 bool *has_reduced_clock,
7112 intel_clock_t *reduced_clock)
7114 struct drm_device *dev = crtc->dev;
7115 struct drm_i915_private *dev_priv = dev->dev_private;
7116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7118 const intel_limit_t *limit;
7119 bool ret, is_lvds = false;
7121 is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7123 refclk = ironlake_get_refclk(crtc);
7126 * Returns a set of divisors for the desired target clock with the given
7127 * refclk, or FALSE. The returned values represent the clock equation:
7128 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7130 limit = intel_limit(intel_crtc, refclk);
7131 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7132 intel_crtc->config.port_clock,
7133 refclk, NULL, clock);
7137 if (is_lvds && dev_priv->lvds_downclock_avail) {
7139 * Ensure we match the reduced clock's P to the target clock.
7140 * If the clocks don't match, we can't switch the display clock
7141 * by using the FP0/FP1. In such case we will disable the LVDS
7142 * downclock feature.
7144 *has_reduced_clock =
7145 dev_priv->display.find_dpll(limit, intel_crtc,
7146 dev_priv->lvds_downclock,
7154 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7157 * Account for spread spectrum to avoid
7158 * oversubscribing the link. Max center spread
7159 * is 2.5%; use 5% for safety's sake.
7161 u32 bps = target_clock * bpp * 21 / 20;
7162 return DIV_ROUND_UP(bps, link_bw * 8);
7165 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7167 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7170 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7172 intel_clock_t *reduced_clock, u32 *fp2)
7174 struct drm_crtc *crtc = &intel_crtc->base;
7175 struct drm_device *dev = crtc->dev;
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177 struct intel_encoder *intel_encoder;
7179 int factor, num_connectors = 0;
7180 bool is_lvds = false, is_sdvo = false;
7182 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7183 switch (intel_encoder->type) {
7184 case INTEL_OUTPUT_LVDS:
7187 case INTEL_OUTPUT_SDVO:
7188 case INTEL_OUTPUT_HDMI:
7196 /* Enable autotuning of the PLL clock (if permissible) */
7199 if ((intel_panel_use_ssc(dev_priv) &&
7200 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7201 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7203 } else if (intel_crtc->config.sdvo_tv_clock)
7206 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7209 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7215 dpll |= DPLLB_MODE_LVDS;
7217 dpll |= DPLLB_MODE_DAC_SERIAL;
7219 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7220 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7223 dpll |= DPLL_SDVO_HIGH_SPEED;
7224 if (intel_crtc->config.has_dp_encoder)
7225 dpll |= DPLL_SDVO_HIGH_SPEED;
7227 /* compute bitmask from p1 value */
7228 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7230 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7232 switch (intel_crtc->config.dpll.p2) {
7234 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7237 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7240 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7243 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7247 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7248 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7250 dpll |= PLL_REF_INPUT_DREFCLK;
7252 return dpll | DPLL_VCO_ENABLE;
7255 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7257 struct drm_framebuffer *fb)
7259 struct drm_device *dev = crtc->base.dev;
7260 intel_clock_t clock, reduced_clock;
7261 u32 dpll = 0, fp = 0, fp2 = 0;
7262 bool ok, has_reduced_clock = false;
7263 bool is_lvds = false;
7264 struct intel_shared_dpll *pll;
7266 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7268 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7269 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7271 ok = ironlake_compute_clocks(&crtc->base, &clock,
7272 &has_reduced_clock, &reduced_clock);
7273 if (!ok && !crtc->config.clock_set) {
7274 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7277 /* Compat-code for transition, will disappear. */
7278 if (!crtc->config.clock_set) {
7279 crtc->config.dpll.n = clock.n;
7280 crtc->config.dpll.m1 = clock.m1;
7281 crtc->config.dpll.m2 = clock.m2;
7282 crtc->config.dpll.p1 = clock.p1;
7283 crtc->config.dpll.p2 = clock.p2;
7286 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7287 if (crtc->config.has_pch_encoder) {
7288 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7289 if (has_reduced_clock)
7290 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7292 dpll = ironlake_compute_dpll(crtc,
7293 &fp, &reduced_clock,
7294 has_reduced_clock ? &fp2 : NULL);
7296 crtc->config.dpll_hw_state.dpll = dpll;
7297 crtc->config.dpll_hw_state.fp0 = fp;
7298 if (has_reduced_clock)
7299 crtc->config.dpll_hw_state.fp1 = fp2;
7301 crtc->config.dpll_hw_state.fp1 = fp;
7303 pll = intel_get_shared_dpll(crtc);
7305 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7306 pipe_name(crtc->pipe));
7310 intel_put_shared_dpll(crtc);
7312 if (is_lvds && has_reduced_clock && i915.powersave)
7313 crtc->lowfreq_avail = true;
7315 crtc->lowfreq_avail = false;
7320 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7321 struct intel_link_m_n *m_n)
7323 struct drm_device *dev = crtc->base.dev;
7324 struct drm_i915_private *dev_priv = dev->dev_private;
7325 enum pipe pipe = crtc->pipe;
7327 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7328 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7329 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7331 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7332 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7333 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7336 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7337 enum transcoder transcoder,
7338 struct intel_link_m_n *m_n,
7339 struct intel_link_m_n *m2_n2)
7341 struct drm_device *dev = crtc->base.dev;
7342 struct drm_i915_private *dev_priv = dev->dev_private;
7343 enum pipe pipe = crtc->pipe;
7345 if (INTEL_INFO(dev)->gen >= 5) {
7346 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7347 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7348 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7350 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7351 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7352 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7353 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7354 * gen < 8) and if DRRS is supported (to make sure the
7355 * registers are not unnecessarily read).
7357 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7358 crtc->config.has_drrs) {
7359 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7360 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7361 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7363 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7364 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7365 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7368 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7369 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7370 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7372 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7373 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7374 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7378 void intel_dp_get_m_n(struct intel_crtc *crtc,
7379 struct intel_crtc_config *pipe_config)
7381 if (crtc->config.has_pch_encoder)
7382 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7384 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7385 &pipe_config->dp_m_n,
7386 &pipe_config->dp_m2_n2);
7389 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7390 struct intel_crtc_config *pipe_config)
7392 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7393 &pipe_config->fdi_m_n, NULL);
7396 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7397 struct intel_crtc_config *pipe_config)
7399 struct drm_device *dev = crtc->base.dev;
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7403 tmp = I915_READ(PF_CTL(crtc->pipe));
7405 if (tmp & PF_ENABLE) {
7406 pipe_config->pch_pfit.enabled = true;
7407 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7408 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7410 /* We currently do not free assignements of panel fitters on
7411 * ivb/hsw (since we don't use the higher upscaling modes which
7412 * differentiates them) so just WARN about this case for now. */
7414 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7415 PF_PIPE_SEL_IVB(crtc->pipe));
7420 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7421 struct intel_plane_config *plane_config)
7423 struct drm_device *dev = crtc->base.dev;
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425 u32 val, base, offset;
7426 int pipe = crtc->pipe, plane = crtc->plane;
7427 int fourcc, pixel_format;
7430 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7431 if (!crtc->base.primary->fb) {
7432 DRM_DEBUG_KMS("failed to alloc fb\n");
7436 val = I915_READ(DSPCNTR(plane));
7438 if (INTEL_INFO(dev)->gen >= 4)
7439 if (val & DISPPLANE_TILED)
7440 plane_config->tiled = true;
7442 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7443 fourcc = intel_format_to_fourcc(pixel_format);
7444 crtc->base.primary->fb->pixel_format = fourcc;
7445 crtc->base.primary->fb->bits_per_pixel =
7446 drm_format_plane_cpp(fourcc, 0) * 8;
7448 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7449 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7450 offset = I915_READ(DSPOFFSET(plane));
7452 if (plane_config->tiled)
7453 offset = I915_READ(DSPTILEOFF(plane));
7455 offset = I915_READ(DSPLINOFF(plane));
7457 plane_config->base = base;
7459 val = I915_READ(PIPESRC(pipe));
7460 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7461 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7463 val = I915_READ(DSPSTRIDE(pipe));
7464 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7466 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7467 plane_config->tiled);
7469 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7472 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7473 pipe, plane, crtc->base.primary->fb->width,
7474 crtc->base.primary->fb->height,
7475 crtc->base.primary->fb->bits_per_pixel, base,
7476 crtc->base.primary->fb->pitches[0],
7477 plane_config->size);
7480 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7481 struct intel_crtc_config *pipe_config)
7483 struct drm_device *dev = crtc->base.dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7487 if (!intel_display_power_is_enabled(dev_priv,
7488 POWER_DOMAIN_PIPE(crtc->pipe)))
7491 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7492 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7494 tmp = I915_READ(PIPECONF(crtc->pipe));
7495 if (!(tmp & PIPECONF_ENABLE))
7498 switch (tmp & PIPECONF_BPC_MASK) {
7500 pipe_config->pipe_bpp = 18;
7503 pipe_config->pipe_bpp = 24;
7505 case PIPECONF_10BPC:
7506 pipe_config->pipe_bpp = 30;
7508 case PIPECONF_12BPC:
7509 pipe_config->pipe_bpp = 36;
7515 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7516 pipe_config->limited_color_range = true;
7518 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7519 struct intel_shared_dpll *pll;
7521 pipe_config->has_pch_encoder = true;
7523 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7524 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7525 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7527 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7529 if (HAS_PCH_IBX(dev_priv->dev)) {
7530 pipe_config->shared_dpll =
7531 (enum intel_dpll_id) crtc->pipe;
7533 tmp = I915_READ(PCH_DPLL_SEL);
7534 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7535 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7537 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7540 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7542 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7543 &pipe_config->dpll_hw_state));
7545 tmp = pipe_config->dpll_hw_state.dpll;
7546 pipe_config->pixel_multiplier =
7547 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7548 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7550 ironlake_pch_clock_get(crtc, pipe_config);
7552 pipe_config->pixel_multiplier = 1;
7555 intel_get_pipe_timings(crtc, pipe_config);
7557 ironlake_get_pfit_config(crtc, pipe_config);
7562 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7564 struct drm_device *dev = dev_priv->dev;
7565 struct intel_crtc *crtc;
7567 for_each_intel_crtc(dev, crtc)
7568 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7569 pipe_name(crtc->pipe));
7571 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7572 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7573 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7574 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7575 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7576 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7577 "CPU PWM1 enabled\n");
7578 if (IS_HASWELL(dev))
7579 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7580 "CPU PWM2 enabled\n");
7581 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7582 "PCH PWM1 enabled\n");
7583 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7584 "Utility pin enabled\n");
7585 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7588 * In theory we can still leave IRQs enabled, as long as only the HPD
7589 * interrupts remain enabled. We used to check for that, but since it's
7590 * gen-specific and since we only disable LCPLL after we fully disable
7591 * the interrupts, the check below should be enough.
7593 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7596 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7598 struct drm_device *dev = dev_priv->dev;
7600 if (IS_HASWELL(dev))
7601 return I915_READ(D_COMP_HSW);
7603 return I915_READ(D_COMP_BDW);
7606 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7608 struct drm_device *dev = dev_priv->dev;
7610 if (IS_HASWELL(dev)) {
7611 mutex_lock(&dev_priv->rps.hw_lock);
7612 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7614 DRM_ERROR("Failed to write to D_COMP\n");
7615 mutex_unlock(&dev_priv->rps.hw_lock);
7617 I915_WRITE(D_COMP_BDW, val);
7618 POSTING_READ(D_COMP_BDW);
7623 * This function implements pieces of two sequences from BSpec:
7624 * - Sequence for display software to disable LCPLL
7625 * - Sequence for display software to allow package C8+
7626 * The steps implemented here are just the steps that actually touch the LCPLL
7627 * register. Callers should take care of disabling all the display engine
7628 * functions, doing the mode unset, fixing interrupts, etc.
7630 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7631 bool switch_to_fclk, bool allow_power_down)
7635 assert_can_disable_lcpll(dev_priv);
7637 val = I915_READ(LCPLL_CTL);
7639 if (switch_to_fclk) {
7640 val |= LCPLL_CD_SOURCE_FCLK;
7641 I915_WRITE(LCPLL_CTL, val);
7643 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7644 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7645 DRM_ERROR("Switching to FCLK failed\n");
7647 val = I915_READ(LCPLL_CTL);
7650 val |= LCPLL_PLL_DISABLE;
7651 I915_WRITE(LCPLL_CTL, val);
7652 POSTING_READ(LCPLL_CTL);
7654 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7655 DRM_ERROR("LCPLL still locked\n");
7657 val = hsw_read_dcomp(dev_priv);
7658 val |= D_COMP_COMP_DISABLE;
7659 hsw_write_dcomp(dev_priv, val);
7662 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7664 DRM_ERROR("D_COMP RCOMP still in progress\n");
7666 if (allow_power_down) {
7667 val = I915_READ(LCPLL_CTL);
7668 val |= LCPLL_POWER_DOWN_ALLOW;
7669 I915_WRITE(LCPLL_CTL, val);
7670 POSTING_READ(LCPLL_CTL);
7675 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7678 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7682 val = I915_READ(LCPLL_CTL);
7684 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7685 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7689 * Make sure we're not on PC8 state before disabling PC8, otherwise
7690 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7692 * The other problem is that hsw_restore_lcpll() is called as part of
7693 * the runtime PM resume sequence, so we can't just call
7694 * gen6_gt_force_wake_get() because that function calls
7695 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7696 * while we are on the resume sequence. So to solve this problem we have
7697 * to call special forcewake code that doesn't touch runtime PM and
7698 * doesn't enable the forcewake delayed work.
7700 spin_lock_irq(&dev_priv->uncore.lock);
7701 if (dev_priv->uncore.forcewake_count++ == 0)
7702 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7703 spin_unlock_irq(&dev_priv->uncore.lock);
7705 if (val & LCPLL_POWER_DOWN_ALLOW) {
7706 val &= ~LCPLL_POWER_DOWN_ALLOW;
7707 I915_WRITE(LCPLL_CTL, val);
7708 POSTING_READ(LCPLL_CTL);
7711 val = hsw_read_dcomp(dev_priv);
7712 val |= D_COMP_COMP_FORCE;
7713 val &= ~D_COMP_COMP_DISABLE;
7714 hsw_write_dcomp(dev_priv, val);
7716 val = I915_READ(LCPLL_CTL);
7717 val &= ~LCPLL_PLL_DISABLE;
7718 I915_WRITE(LCPLL_CTL, val);
7720 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7721 DRM_ERROR("LCPLL not locked yet\n");
7723 if (val & LCPLL_CD_SOURCE_FCLK) {
7724 val = I915_READ(LCPLL_CTL);
7725 val &= ~LCPLL_CD_SOURCE_FCLK;
7726 I915_WRITE(LCPLL_CTL, val);
7728 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7729 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7730 DRM_ERROR("Switching back to LCPLL failed\n");
7733 /* See the big comment above. */
7734 spin_lock_irq(&dev_priv->uncore.lock);
7735 if (--dev_priv->uncore.forcewake_count == 0)
7736 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7737 spin_unlock_irq(&dev_priv->uncore.lock);
7741 * Package states C8 and deeper are really deep PC states that can only be
7742 * reached when all the devices on the system allow it, so even if the graphics
7743 * device allows PC8+, it doesn't mean the system will actually get to these
7744 * states. Our driver only allows PC8+ when going into runtime PM.
7746 * The requirements for PC8+ are that all the outputs are disabled, the power
7747 * well is disabled and most interrupts are disabled, and these are also
7748 * requirements for runtime PM. When these conditions are met, we manually do
7749 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7750 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7753 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7754 * the state of some registers, so when we come back from PC8+ we need to
7755 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7756 * need to take care of the registers kept by RC6. Notice that this happens even
7757 * if we don't put the device in PCI D3 state (which is what currently happens
7758 * because of the runtime PM support).
7760 * For more, read "Display Sequences for Package C8" on the hardware
7763 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7765 struct drm_device *dev = dev_priv->dev;
7768 DRM_DEBUG_KMS("Enabling package C8+\n");
7770 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7771 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7772 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7773 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7776 lpt_disable_clkout_dp(dev);
7777 hsw_disable_lcpll(dev_priv, true, true);
7780 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7782 struct drm_device *dev = dev_priv->dev;
7785 DRM_DEBUG_KMS("Disabling package C8+\n");
7787 hsw_restore_lcpll(dev_priv);
7788 lpt_init_pch_refclk(dev);
7790 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7791 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7792 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7793 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7796 intel_prepare_ddi(dev);
7799 static void snb_modeset_global_resources(struct drm_device *dev)
7801 modeset_update_crtc_power_domains(dev);
7804 static void haswell_modeset_global_resources(struct drm_device *dev)
7806 modeset_update_crtc_power_domains(dev);
7809 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7811 struct drm_framebuffer *fb)
7813 if (!intel_ddi_pll_select(crtc))
7816 crtc->lowfreq_avail = false;
7821 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7823 struct intel_crtc_config *pipe_config)
7825 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7827 switch (pipe_config->ddi_pll_sel) {
7828 case PORT_CLK_SEL_WRPLL1:
7829 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7831 case PORT_CLK_SEL_WRPLL2:
7832 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7837 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7838 struct intel_crtc_config *pipe_config)
7840 struct drm_device *dev = crtc->base.dev;
7841 struct drm_i915_private *dev_priv = dev->dev_private;
7842 struct intel_shared_dpll *pll;
7846 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7848 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7850 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7852 if (pipe_config->shared_dpll >= 0) {
7853 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7855 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7856 &pipe_config->dpll_hw_state));
7860 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7861 * DDI E. So just check whether this pipe is wired to DDI E and whether
7862 * the PCH transcoder is on.
7864 if (INTEL_INFO(dev)->gen < 9 &&
7865 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7866 pipe_config->has_pch_encoder = true;
7868 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7869 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7870 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7872 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7876 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7877 struct intel_crtc_config *pipe_config)
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 enum intel_display_power_domain pfit_domain;
7884 if (!intel_display_power_is_enabled(dev_priv,
7885 POWER_DOMAIN_PIPE(crtc->pipe)))
7888 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7889 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7891 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7892 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7893 enum pipe trans_edp_pipe;
7894 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7896 WARN(1, "unknown pipe linked to edp transcoder\n");
7897 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7898 case TRANS_DDI_EDP_INPUT_A_ON:
7899 trans_edp_pipe = PIPE_A;
7901 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7902 trans_edp_pipe = PIPE_B;
7904 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7905 trans_edp_pipe = PIPE_C;
7909 if (trans_edp_pipe == crtc->pipe)
7910 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7913 if (!intel_display_power_is_enabled(dev_priv,
7914 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7917 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7918 if (!(tmp & PIPECONF_ENABLE))
7921 haswell_get_ddi_port_state(crtc, pipe_config);
7923 intel_get_pipe_timings(crtc, pipe_config);
7925 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7926 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7927 ironlake_get_pfit_config(crtc, pipe_config);
7929 if (IS_HASWELL(dev))
7930 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7931 (I915_READ(IPS_CTL) & IPS_ENABLE);
7933 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7934 pipe_config->pixel_multiplier =
7935 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7937 pipe_config->pixel_multiplier = 1;
7946 } hdmi_audio_clock[] = {
7947 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7948 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7949 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7950 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7951 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7952 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7953 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7954 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7955 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7956 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7959 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7960 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7964 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7965 if (mode->clock == hdmi_audio_clock[i].clock)
7969 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7970 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7974 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7975 hdmi_audio_clock[i].clock,
7976 hdmi_audio_clock[i].config);
7978 return hdmi_audio_clock[i].config;
7981 static bool intel_eld_uptodate(struct drm_connector *connector,
7982 int reg_eldv, uint32_t bits_eldv,
7983 int reg_elda, uint32_t bits_elda,
7986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7987 uint8_t *eld = connector->eld;
7990 i = I915_READ(reg_eldv);
7999 i = I915_READ(reg_elda);
8001 I915_WRITE(reg_elda, i);
8003 for (i = 0; i < eld[2]; i++)
8004 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8010 static void g4x_write_eld(struct drm_connector *connector,
8011 struct drm_crtc *crtc,
8012 struct drm_display_mode *mode)
8014 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8015 uint8_t *eld = connector->eld;
8020 i = I915_READ(G4X_AUD_VID_DID);
8022 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8023 eldv = G4X_ELDV_DEVCL_DEVBLC;
8025 eldv = G4X_ELDV_DEVCTG;
8027 if (intel_eld_uptodate(connector,
8028 G4X_AUD_CNTL_ST, eldv,
8029 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8030 G4X_HDMIW_HDMIEDID))
8033 i = I915_READ(G4X_AUD_CNTL_ST);
8034 i &= ~(eldv | G4X_ELD_ADDR);
8035 len = (i >> 9) & 0x1f; /* ELD buffer size */
8036 I915_WRITE(G4X_AUD_CNTL_ST, i);
8041 len = min_t(uint8_t, eld[2], len);
8042 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8043 for (i = 0; i < len; i++)
8044 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8046 i = I915_READ(G4X_AUD_CNTL_ST);
8048 I915_WRITE(G4X_AUD_CNTL_ST, i);
8051 static void haswell_write_eld(struct drm_connector *connector,
8052 struct drm_crtc *crtc,
8053 struct drm_display_mode *mode)
8055 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8057 uint8_t *eld = connector->eld;
8061 int pipe = to_intel_crtc(crtc)->pipe;
8064 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8065 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8066 int aud_config = HSW_AUD_CFG(pipe);
8067 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8069 /* Audio output enable */
8070 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8071 tmp = I915_READ(aud_cntrl_st2);
8072 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8073 I915_WRITE(aud_cntrl_st2, tmp);
8074 POSTING_READ(aud_cntrl_st2);
8076 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8078 /* Set ELD valid state */
8079 tmp = I915_READ(aud_cntrl_st2);
8080 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8081 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8082 I915_WRITE(aud_cntrl_st2, tmp);
8083 tmp = I915_READ(aud_cntrl_st2);
8084 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8086 /* Enable HDMI mode */
8087 tmp = I915_READ(aud_config);
8088 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8089 /* clear N_programing_enable and N_value_index */
8090 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8091 I915_WRITE(aud_config, tmp);
8093 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8095 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8097 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8098 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8099 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8100 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8102 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8105 if (intel_eld_uptodate(connector,
8106 aud_cntrl_st2, eldv,
8107 aud_cntl_st, IBX_ELD_ADDRESS,
8111 i = I915_READ(aud_cntrl_st2);
8113 I915_WRITE(aud_cntrl_st2, i);
8118 i = I915_READ(aud_cntl_st);
8119 i &= ~IBX_ELD_ADDRESS;
8120 I915_WRITE(aud_cntl_st, i);
8121 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8122 DRM_DEBUG_DRIVER("port num:%d\n", i);
8124 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8125 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8126 for (i = 0; i < len; i++)
8127 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8129 i = I915_READ(aud_cntrl_st2);
8131 I915_WRITE(aud_cntrl_st2, i);
8135 static void ironlake_write_eld(struct drm_connector *connector,
8136 struct drm_crtc *crtc,
8137 struct drm_display_mode *mode)
8139 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8141 uint8_t *eld = connector->eld;
8149 int pipe = to_intel_crtc(crtc)->pipe;
8151 if (HAS_PCH_IBX(connector->dev)) {
8152 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8153 aud_config = IBX_AUD_CFG(pipe);
8154 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8155 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8156 } else if (IS_VALLEYVIEW(connector->dev)) {
8157 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8158 aud_config = VLV_AUD_CFG(pipe);
8159 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8160 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8162 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8163 aud_config = CPT_AUD_CFG(pipe);
8164 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8165 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8168 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8170 if (IS_VALLEYVIEW(connector->dev)) {
8171 struct intel_encoder *intel_encoder;
8172 struct intel_digital_port *intel_dig_port;
8174 intel_encoder = intel_attached_encoder(connector);
8175 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8176 i = intel_dig_port->port;
8178 i = I915_READ(aud_cntl_st);
8179 i = (i >> 29) & DIP_PORT_SEL_MASK;
8180 /* DIP_Port_Select, 0x1 = PortB */
8184 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8185 /* operate blindly on all ports */
8186 eldv = IBX_ELD_VALIDB;
8187 eldv |= IBX_ELD_VALIDB << 4;
8188 eldv |= IBX_ELD_VALIDB << 8;
8190 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8191 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8194 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8195 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8196 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8197 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8199 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8202 if (intel_eld_uptodate(connector,
8203 aud_cntrl_st2, eldv,
8204 aud_cntl_st, IBX_ELD_ADDRESS,
8208 i = I915_READ(aud_cntrl_st2);
8210 I915_WRITE(aud_cntrl_st2, i);
8215 i = I915_READ(aud_cntl_st);
8216 i &= ~IBX_ELD_ADDRESS;
8217 I915_WRITE(aud_cntl_st, i);
8219 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8220 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8221 for (i = 0; i < len; i++)
8222 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8224 i = I915_READ(aud_cntrl_st2);
8226 I915_WRITE(aud_cntrl_st2, i);
8229 void intel_write_eld(struct drm_encoder *encoder,
8230 struct drm_display_mode *mode)
8232 struct drm_crtc *crtc = encoder->crtc;
8233 struct drm_connector *connector;
8234 struct drm_device *dev = encoder->dev;
8235 struct drm_i915_private *dev_priv = dev->dev_private;
8237 connector = drm_select_eld(encoder, mode);
8241 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8244 connector->encoder->base.id,
8245 connector->encoder->name);
8247 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8249 if (dev_priv->display.write_eld)
8250 dev_priv->display.write_eld(connector, crtc, mode);
8253 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8255 struct drm_device *dev = crtc->dev;
8256 struct drm_i915_private *dev_priv = dev->dev_private;
8257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8258 uint32_t cntl = 0, size = 0;
8261 unsigned int width = intel_crtc->cursor_width;
8262 unsigned int height = intel_crtc->cursor_height;
8263 unsigned int stride = roundup_pow_of_two(width) * 4;
8267 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8278 cntl |= CURSOR_ENABLE |
8279 CURSOR_GAMMA_ENABLE |
8280 CURSOR_FORMAT_ARGB |
8281 CURSOR_STRIDE(stride);
8283 size = (height << 12) | width;
8286 if (intel_crtc->cursor_cntl != 0 &&
8287 (intel_crtc->cursor_base != base ||
8288 intel_crtc->cursor_size != size ||
8289 intel_crtc->cursor_cntl != cntl)) {
8290 /* On these chipsets we can only modify the base/size/stride
8291 * whilst the cursor is disabled.
8293 I915_WRITE(_CURACNTR, 0);
8294 POSTING_READ(_CURACNTR);
8295 intel_crtc->cursor_cntl = 0;
8298 if (intel_crtc->cursor_base != base) {
8299 I915_WRITE(_CURABASE, base);
8300 intel_crtc->cursor_base = base;
8303 if (intel_crtc->cursor_size != size) {
8304 I915_WRITE(CURSIZE, size);
8305 intel_crtc->cursor_size = size;
8308 if (intel_crtc->cursor_cntl != cntl) {
8309 I915_WRITE(_CURACNTR, cntl);
8310 POSTING_READ(_CURACNTR);
8311 intel_crtc->cursor_cntl = cntl;
8315 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8317 struct drm_device *dev = crtc->dev;
8318 struct drm_i915_private *dev_priv = dev->dev_private;
8319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8320 int pipe = intel_crtc->pipe;
8325 cntl = MCURSOR_GAMMA_ENABLE;
8326 switch (intel_crtc->cursor_width) {
8328 cntl |= CURSOR_MODE_64_ARGB_AX;
8331 cntl |= CURSOR_MODE_128_ARGB_AX;
8334 cntl |= CURSOR_MODE_256_ARGB_AX;
8340 cntl |= pipe << 28; /* Connect to correct pipe */
8342 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8343 cntl |= CURSOR_PIPE_CSC_ENABLE;
8346 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8347 cntl |= CURSOR_ROTATE_180;
8349 if (intel_crtc->cursor_cntl != cntl) {
8350 I915_WRITE(CURCNTR(pipe), cntl);
8351 POSTING_READ(CURCNTR(pipe));
8352 intel_crtc->cursor_cntl = cntl;
8355 /* and commit changes on next vblank */
8356 I915_WRITE(CURBASE(pipe), base);
8357 POSTING_READ(CURBASE(pipe));
8359 intel_crtc->cursor_base = base;
8362 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8363 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8366 struct drm_device *dev = crtc->dev;
8367 struct drm_i915_private *dev_priv = dev->dev_private;
8368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8369 int pipe = intel_crtc->pipe;
8370 int x = crtc->cursor_x;
8371 int y = crtc->cursor_y;
8372 u32 base = 0, pos = 0;
8375 base = intel_crtc->cursor_addr;
8377 if (x >= intel_crtc->config.pipe_src_w)
8380 if (y >= intel_crtc->config.pipe_src_h)
8384 if (x + intel_crtc->cursor_width <= 0)
8387 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8390 pos |= x << CURSOR_X_SHIFT;
8393 if (y + intel_crtc->cursor_height <= 0)
8396 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8399 pos |= y << CURSOR_Y_SHIFT;
8401 if (base == 0 && intel_crtc->cursor_base == 0)
8404 I915_WRITE(CURPOS(pipe), pos);
8406 /* ILK+ do this automagically */
8407 if (HAS_GMCH_DISPLAY(dev) &&
8408 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8409 base += (intel_crtc->cursor_height *
8410 intel_crtc->cursor_width - 1) * 4;
8413 if (IS_845G(dev) || IS_I865G(dev))
8414 i845_update_cursor(crtc, base);
8416 i9xx_update_cursor(crtc, base);
8419 static bool cursor_size_ok(struct drm_device *dev,
8420 uint32_t width, uint32_t height)
8422 if (width == 0 || height == 0)
8426 * 845g/865g are special in that they are only limited by
8427 * the width of their cursors, the height is arbitrary up to
8428 * the precision of the register. Everything else requires
8429 * square cursors, limited to a few power-of-two sizes.
8431 if (IS_845G(dev) || IS_I865G(dev)) {
8432 if ((width & 63) != 0)
8435 if (width > (IS_845G(dev) ? 64 : 512))
8441 switch (width | height) {
8456 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8457 struct drm_i915_gem_object *obj,
8458 uint32_t width, uint32_t height)
8460 struct drm_device *dev = crtc->dev;
8461 struct drm_i915_private *dev_priv = dev->dev_private;
8462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8463 enum pipe pipe = intel_crtc->pipe;
8468 /* if we want to turn off the cursor ignore width and height */
8470 DRM_DEBUG_KMS("cursor off\n");
8472 mutex_lock(&dev->struct_mutex);
8476 /* we only need to pin inside GTT if cursor is non-phy */
8477 mutex_lock(&dev->struct_mutex);
8478 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8482 * Global gtt pte registers are special registers which actually
8483 * forward writes to a chunk of system memory. Which means that
8484 * there is no risk that the register values disappear as soon
8485 * as we call intel_runtime_pm_put(), so it is correct to wrap
8486 * only the pin/unpin/fence and not more.
8488 intel_runtime_pm_get(dev_priv);
8490 /* Note that the w/a also requires 2 PTE of padding following
8491 * the bo. We currently fill all unused PTE with the shadow
8492 * page and so we should always have valid PTE following the
8493 * cursor preventing the VT-d warning.
8496 if (need_vtd_wa(dev))
8497 alignment = 64*1024;
8499 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8501 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8502 intel_runtime_pm_put(dev_priv);
8506 ret = i915_gem_object_put_fence(obj);
8508 DRM_DEBUG_KMS("failed to release fence for cursor");
8509 intel_runtime_pm_put(dev_priv);
8513 addr = i915_gem_obj_ggtt_offset(obj);
8515 intel_runtime_pm_put(dev_priv);
8517 int align = IS_I830(dev) ? 16 * 1024 : 256;
8518 ret = i915_gem_object_attach_phys(obj, align);
8520 DRM_DEBUG_KMS("failed to attach phys object\n");
8523 addr = obj->phys_handle->busaddr;
8527 if (intel_crtc->cursor_bo) {
8528 if (!INTEL_INFO(dev)->cursor_needs_physical)
8529 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8532 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8533 INTEL_FRONTBUFFER_CURSOR(pipe));
8534 mutex_unlock(&dev->struct_mutex);
8536 old_width = intel_crtc->cursor_width;
8538 intel_crtc->cursor_addr = addr;
8539 intel_crtc->cursor_bo = obj;
8540 intel_crtc->cursor_width = width;
8541 intel_crtc->cursor_height = height;
8543 if (intel_crtc->active) {
8544 if (old_width != width)
8545 intel_update_watermarks(crtc);
8546 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8548 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8553 i915_gem_object_unpin_from_display_plane(obj);
8555 mutex_unlock(&dev->struct_mutex);
8559 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8560 u16 *blue, uint32_t start, uint32_t size)
8562 int end = (start + size > 256) ? 256 : start + size, i;
8563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 for (i = start; i < end; i++) {
8566 intel_crtc->lut_r[i] = red[i] >> 8;
8567 intel_crtc->lut_g[i] = green[i] >> 8;
8568 intel_crtc->lut_b[i] = blue[i] >> 8;
8571 intel_crtc_load_lut(crtc);
8574 /* VESA 640x480x72Hz mode to set on the pipe */
8575 static struct drm_display_mode load_detect_mode = {
8576 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8577 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8580 struct drm_framebuffer *
8581 __intel_framebuffer_create(struct drm_device *dev,
8582 struct drm_mode_fb_cmd2 *mode_cmd,
8583 struct drm_i915_gem_object *obj)
8585 struct intel_framebuffer *intel_fb;
8588 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8590 drm_gem_object_unreference_unlocked(&obj->base);
8591 return ERR_PTR(-ENOMEM);
8594 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8598 return &intel_fb->base;
8600 drm_gem_object_unreference_unlocked(&obj->base);
8603 return ERR_PTR(ret);
8606 static struct drm_framebuffer *
8607 intel_framebuffer_create(struct drm_device *dev,
8608 struct drm_mode_fb_cmd2 *mode_cmd,
8609 struct drm_i915_gem_object *obj)
8611 struct drm_framebuffer *fb;
8614 ret = i915_mutex_lock_interruptible(dev);
8616 return ERR_PTR(ret);
8617 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8618 mutex_unlock(&dev->struct_mutex);
8624 intel_framebuffer_pitch_for_width(int width, int bpp)
8626 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8627 return ALIGN(pitch, 64);
8631 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8633 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8634 return PAGE_ALIGN(pitch * mode->vdisplay);
8637 static struct drm_framebuffer *
8638 intel_framebuffer_create_for_mode(struct drm_device *dev,
8639 struct drm_display_mode *mode,
8642 struct drm_i915_gem_object *obj;
8643 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8645 obj = i915_gem_alloc_object(dev,
8646 intel_framebuffer_size_for_mode(mode, bpp));
8648 return ERR_PTR(-ENOMEM);
8650 mode_cmd.width = mode->hdisplay;
8651 mode_cmd.height = mode->vdisplay;
8652 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8654 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8656 return intel_framebuffer_create(dev, &mode_cmd, obj);
8659 static struct drm_framebuffer *
8660 mode_fits_in_fbdev(struct drm_device *dev,
8661 struct drm_display_mode *mode)
8663 #ifdef CONFIG_DRM_I915_FBDEV
8664 struct drm_i915_private *dev_priv = dev->dev_private;
8665 struct drm_i915_gem_object *obj;
8666 struct drm_framebuffer *fb;
8668 if (!dev_priv->fbdev)
8671 if (!dev_priv->fbdev->fb)
8674 obj = dev_priv->fbdev->fb->obj;
8677 fb = &dev_priv->fbdev->fb->base;
8678 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8679 fb->bits_per_pixel))
8682 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8691 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8692 struct drm_display_mode *mode,
8693 struct intel_load_detect_pipe *old,
8694 struct drm_modeset_acquire_ctx *ctx)
8696 struct intel_crtc *intel_crtc;
8697 struct intel_encoder *intel_encoder =
8698 intel_attached_encoder(connector);
8699 struct drm_crtc *possible_crtc;
8700 struct drm_encoder *encoder = &intel_encoder->base;
8701 struct drm_crtc *crtc = NULL;
8702 struct drm_device *dev = encoder->dev;
8703 struct drm_framebuffer *fb;
8704 struct drm_mode_config *config = &dev->mode_config;
8707 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8708 connector->base.id, connector->name,
8709 encoder->base.id, encoder->name);
8712 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8717 * Algorithm gets a little messy:
8719 * - if the connector already has an assigned crtc, use it (but make
8720 * sure it's on first)
8722 * - try to find the first unused crtc that can drive this connector,
8723 * and use that if we find one
8726 /* See if we already have a CRTC for this connector */
8727 if (encoder->crtc) {
8728 crtc = encoder->crtc;
8730 ret = drm_modeset_lock(&crtc->mutex, ctx);
8734 old->dpms_mode = connector->dpms;
8735 old->load_detect_temp = false;
8737 /* Make sure the crtc and connector are running */
8738 if (connector->dpms != DRM_MODE_DPMS_ON)
8739 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8744 /* Find an unused one (if possible) */
8745 for_each_crtc(dev, possible_crtc) {
8747 if (!(encoder->possible_crtcs & (1 << i)))
8749 if (possible_crtc->enabled)
8751 /* This can occur when applying the pipe A quirk on resume. */
8752 if (to_intel_crtc(possible_crtc)->new_enabled)
8755 crtc = possible_crtc;
8760 * If we didn't find an unused CRTC, don't use any.
8763 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8767 ret = drm_modeset_lock(&crtc->mutex, ctx);
8770 intel_encoder->new_crtc = to_intel_crtc(crtc);
8771 to_intel_connector(connector)->new_encoder = intel_encoder;
8773 intel_crtc = to_intel_crtc(crtc);
8774 intel_crtc->new_enabled = true;
8775 intel_crtc->new_config = &intel_crtc->config;
8776 old->dpms_mode = connector->dpms;
8777 old->load_detect_temp = true;
8778 old->release_fb = NULL;
8781 mode = &load_detect_mode;
8783 /* We need a framebuffer large enough to accommodate all accesses
8784 * that the plane may generate whilst we perform load detection.
8785 * We can not rely on the fbcon either being present (we get called
8786 * during its initialisation to detect all boot displays, or it may
8787 * not even exist) or that it is large enough to satisfy the
8790 fb = mode_fits_in_fbdev(dev, mode);
8792 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8793 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8794 old->release_fb = fb;
8796 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8798 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8802 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8803 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8804 if (old->release_fb)
8805 old->release_fb->funcs->destroy(old->release_fb);
8809 /* let the connector get through one full cycle before testing */
8810 intel_wait_for_vblank(dev, intel_crtc->pipe);
8814 intel_crtc->new_enabled = crtc->enabled;
8815 if (intel_crtc->new_enabled)
8816 intel_crtc->new_config = &intel_crtc->config;
8818 intel_crtc->new_config = NULL;
8820 if (ret == -EDEADLK) {
8821 drm_modeset_backoff(ctx);
8828 void intel_release_load_detect_pipe(struct drm_connector *connector,
8829 struct intel_load_detect_pipe *old)
8831 struct intel_encoder *intel_encoder =
8832 intel_attached_encoder(connector);
8833 struct drm_encoder *encoder = &intel_encoder->base;
8834 struct drm_crtc *crtc = encoder->crtc;
8835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8837 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8838 connector->base.id, connector->name,
8839 encoder->base.id, encoder->name);
8841 if (old->load_detect_temp) {
8842 to_intel_connector(connector)->new_encoder = NULL;
8843 intel_encoder->new_crtc = NULL;
8844 intel_crtc->new_enabled = false;
8845 intel_crtc->new_config = NULL;
8846 intel_set_mode(crtc, NULL, 0, 0, NULL);
8848 if (old->release_fb) {
8849 drm_framebuffer_unregister_private(old->release_fb);
8850 drm_framebuffer_unreference(old->release_fb);
8856 /* Switch crtc and encoder back off if necessary */
8857 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8858 connector->funcs->dpms(connector, old->dpms_mode);
8861 static int i9xx_pll_refclk(struct drm_device *dev,
8862 const struct intel_crtc_config *pipe_config)
8864 struct drm_i915_private *dev_priv = dev->dev_private;
8865 u32 dpll = pipe_config->dpll_hw_state.dpll;
8867 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8868 return dev_priv->vbt.lvds_ssc_freq;
8869 else if (HAS_PCH_SPLIT(dev))
8871 else if (!IS_GEN2(dev))
8877 /* Returns the clock of the currently programmed mode of the given pipe. */
8878 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8879 struct intel_crtc_config *pipe_config)
8881 struct drm_device *dev = crtc->base.dev;
8882 struct drm_i915_private *dev_priv = dev->dev_private;
8883 int pipe = pipe_config->cpu_transcoder;
8884 u32 dpll = pipe_config->dpll_hw_state.dpll;
8886 intel_clock_t clock;
8887 int refclk = i9xx_pll_refclk(dev, pipe_config);
8889 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8890 fp = pipe_config->dpll_hw_state.fp0;
8892 fp = pipe_config->dpll_hw_state.fp1;
8894 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8895 if (IS_PINEVIEW(dev)) {
8896 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8897 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8899 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8900 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8903 if (!IS_GEN2(dev)) {
8904 if (IS_PINEVIEW(dev))
8905 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8906 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8908 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8909 DPLL_FPA01_P1_POST_DIV_SHIFT);
8911 switch (dpll & DPLL_MODE_MASK) {
8912 case DPLLB_MODE_DAC_SERIAL:
8913 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8916 case DPLLB_MODE_LVDS:
8917 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8921 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8922 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8926 if (IS_PINEVIEW(dev))
8927 pineview_clock(refclk, &clock);
8929 i9xx_clock(refclk, &clock);
8931 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8932 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8936 DPLL_FPA01_P1_POST_DIV_SHIFT);
8938 if (lvds & LVDS_CLKB_POWER_UP)
8943 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8946 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8947 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8949 if (dpll & PLL_P2_DIVIDE_BY_4)
8955 i9xx_clock(refclk, &clock);
8959 * This value includes pixel_multiplier. We will use
8960 * port_clock to compute adjusted_mode.crtc_clock in the
8961 * encoder's get_config() function.
8963 pipe_config->port_clock = clock.dot;
8966 int intel_dotclock_calculate(int link_freq,
8967 const struct intel_link_m_n *m_n)
8970 * The calculation for the data clock is:
8971 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8972 * But we want to avoid losing precison if possible, so:
8973 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8975 * and the link clock is simpler:
8976 * link_clock = (m * link_clock) / n
8982 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8985 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8986 struct intel_crtc_config *pipe_config)
8988 struct drm_device *dev = crtc->base.dev;
8990 /* read out port_clock from the DPLL */
8991 i9xx_crtc_clock_get(crtc, pipe_config);
8994 * This value does not include pixel_multiplier.
8995 * We will check that port_clock and adjusted_mode.crtc_clock
8996 * agree once we know their relationship in the encoder's
8997 * get_config() function.
8999 pipe_config->adjusted_mode.crtc_clock =
9000 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9001 &pipe_config->fdi_m_n);
9004 /** Returns the currently programmed mode of the given pipe. */
9005 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9006 struct drm_crtc *crtc)
9008 struct drm_i915_private *dev_priv = dev->dev_private;
9009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9010 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
9011 struct drm_display_mode *mode;
9012 struct intel_crtc_config pipe_config;
9013 int htot = I915_READ(HTOTAL(cpu_transcoder));
9014 int hsync = I915_READ(HSYNC(cpu_transcoder));
9015 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9016 int vsync = I915_READ(VSYNC(cpu_transcoder));
9017 enum pipe pipe = intel_crtc->pipe;
9019 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9024 * Construct a pipe_config sufficient for getting the clock info
9025 * back out of crtc_clock_get.
9027 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9028 * to use a real value here instead.
9030 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9031 pipe_config.pixel_multiplier = 1;
9032 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9033 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9034 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9035 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9037 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9038 mode->hdisplay = (htot & 0xffff) + 1;
9039 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9040 mode->hsync_start = (hsync & 0xffff) + 1;
9041 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9042 mode->vdisplay = (vtot & 0xffff) + 1;
9043 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9044 mode->vsync_start = (vsync & 0xffff) + 1;
9045 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9047 drm_mode_set_name(mode);
9052 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9054 struct drm_device *dev = crtc->dev;
9055 struct drm_i915_private *dev_priv = dev->dev_private;
9056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9058 if (!HAS_GMCH_DISPLAY(dev))
9061 if (!dev_priv->lvds_downclock_avail)
9065 * Since this is called by a timer, we should never get here in
9068 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9069 int pipe = intel_crtc->pipe;
9070 int dpll_reg = DPLL(pipe);
9073 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9075 assert_panel_unlocked(dev_priv, pipe);
9077 dpll = I915_READ(dpll_reg);
9078 dpll |= DISPLAY_RATE_SELECT_FPA1;
9079 I915_WRITE(dpll_reg, dpll);
9080 intel_wait_for_vblank(dev, pipe);
9081 dpll = I915_READ(dpll_reg);
9082 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9083 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9088 void intel_mark_busy(struct drm_device *dev)
9090 struct drm_i915_private *dev_priv = dev->dev_private;
9092 if (dev_priv->mm.busy)
9095 intel_runtime_pm_get(dev_priv);
9096 i915_update_gfx_val(dev_priv);
9097 dev_priv->mm.busy = true;
9100 void intel_mark_idle(struct drm_device *dev)
9102 struct drm_i915_private *dev_priv = dev->dev_private;
9103 struct drm_crtc *crtc;
9105 if (!dev_priv->mm.busy)
9108 dev_priv->mm.busy = false;
9110 if (!i915.powersave)
9113 for_each_crtc(dev, crtc) {
9114 if (!crtc->primary->fb)
9117 intel_decrease_pllclock(crtc);
9120 if (INTEL_INFO(dev)->gen >= 6)
9121 gen6_rps_idle(dev->dev_private);
9124 intel_runtime_pm_put(dev_priv);
9127 static void intel_crtc_destroy(struct drm_crtc *crtc)
9129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9130 struct drm_device *dev = crtc->dev;
9131 struct intel_unpin_work *work;
9133 spin_lock_irq(&dev->event_lock);
9134 work = intel_crtc->unpin_work;
9135 intel_crtc->unpin_work = NULL;
9136 spin_unlock_irq(&dev->event_lock);
9139 cancel_work_sync(&work->work);
9143 drm_crtc_cleanup(crtc);
9148 static void intel_unpin_work_fn(struct work_struct *__work)
9150 struct intel_unpin_work *work =
9151 container_of(__work, struct intel_unpin_work, work);
9152 struct drm_device *dev = work->crtc->dev;
9153 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9155 mutex_lock(&dev->struct_mutex);
9156 intel_unpin_fb_obj(work->old_fb_obj);
9157 drm_gem_object_unreference(&work->pending_flip_obj->base);
9158 drm_gem_object_unreference(&work->old_fb_obj->base);
9160 intel_update_fbc(dev);
9161 mutex_unlock(&dev->struct_mutex);
9163 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9165 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9166 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9171 static void do_intel_finish_page_flip(struct drm_device *dev,
9172 struct drm_crtc *crtc)
9174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9175 struct intel_unpin_work *work;
9176 unsigned long flags;
9178 /* Ignore early vblank irqs */
9179 if (intel_crtc == NULL)
9183 * This is called both by irq handlers and the reset code (to complete
9184 * lost pageflips) so needs the full irqsave spinlocks.
9186 spin_lock_irqsave(&dev->event_lock, flags);
9187 work = intel_crtc->unpin_work;
9189 /* Ensure we don't miss a work->pending update ... */
9192 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9193 spin_unlock_irqrestore(&dev->event_lock, flags);
9197 page_flip_completed(intel_crtc);
9199 spin_unlock_irqrestore(&dev->event_lock, flags);
9202 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9204 struct drm_i915_private *dev_priv = dev->dev_private;
9205 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9207 do_intel_finish_page_flip(dev, crtc);
9210 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9212 struct drm_i915_private *dev_priv = dev->dev_private;
9213 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9215 do_intel_finish_page_flip(dev, crtc);
9218 /* Is 'a' after or equal to 'b'? */
9219 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9221 return !((a - b) & 0x80000000);
9224 static bool page_flip_finished(struct intel_crtc *crtc)
9226 struct drm_device *dev = crtc->base.dev;
9227 struct drm_i915_private *dev_priv = dev->dev_private;
9230 * The relevant registers doen't exist on pre-ctg.
9231 * As the flip done interrupt doesn't trigger for mmio
9232 * flips on gmch platforms, a flip count check isn't
9233 * really needed there. But since ctg has the registers,
9234 * include it in the check anyway.
9236 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9240 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9241 * used the same base address. In that case the mmio flip might
9242 * have completed, but the CS hasn't even executed the flip yet.
9244 * A flip count check isn't enough as the CS might have updated
9245 * the base address just after start of vblank, but before we
9246 * managed to process the interrupt. This means we'd complete the
9249 * Combining both checks should get us a good enough result. It may
9250 * still happen that the CS flip has been executed, but has not
9251 * yet actually completed. But in case the base address is the same
9252 * anyway, we don't really care.
9254 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9255 crtc->unpin_work->gtt_offset &&
9256 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9257 crtc->unpin_work->flip_count);
9260 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 struct intel_crtc *intel_crtc =
9264 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9265 unsigned long flags;
9269 * This is called both by irq handlers and the reset code (to complete
9270 * lost pageflips) so needs the full irqsave spinlocks.
9272 * NB: An MMIO update of the plane base pointer will also
9273 * generate a page-flip completion irq, i.e. every modeset
9274 * is also accompanied by a spurious intel_prepare_page_flip().
9276 spin_lock_irqsave(&dev->event_lock, flags);
9277 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9278 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9279 spin_unlock_irqrestore(&dev->event_lock, flags);
9282 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9284 /* Ensure that the work item is consistent when activating it ... */
9286 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9287 /* and that it is marked active as soon as the irq could fire. */
9291 static int intel_gen2_queue_flip(struct drm_device *dev,
9292 struct drm_crtc *crtc,
9293 struct drm_framebuffer *fb,
9294 struct drm_i915_gem_object *obj,
9295 struct intel_engine_cs *ring,
9298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9302 ret = intel_ring_begin(ring, 6);
9306 /* Can't queue multiple flips, so wait for the previous
9307 * one to finish before executing the next.
9309 if (intel_crtc->plane)
9310 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9312 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9313 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9314 intel_ring_emit(ring, MI_NOOP);
9315 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9317 intel_ring_emit(ring, fb->pitches[0]);
9318 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9319 intel_ring_emit(ring, 0); /* aux display base address, unused */
9321 intel_mark_page_flip_active(intel_crtc);
9322 __intel_ring_advance(ring);
9326 static int intel_gen3_queue_flip(struct drm_device *dev,
9327 struct drm_crtc *crtc,
9328 struct drm_framebuffer *fb,
9329 struct drm_i915_gem_object *obj,
9330 struct intel_engine_cs *ring,
9333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9337 ret = intel_ring_begin(ring, 6);
9341 if (intel_crtc->plane)
9342 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9344 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9345 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9346 intel_ring_emit(ring, MI_NOOP);
9347 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9348 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9349 intel_ring_emit(ring, fb->pitches[0]);
9350 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9351 intel_ring_emit(ring, MI_NOOP);
9353 intel_mark_page_flip_active(intel_crtc);
9354 __intel_ring_advance(ring);
9358 static int intel_gen4_queue_flip(struct drm_device *dev,
9359 struct drm_crtc *crtc,
9360 struct drm_framebuffer *fb,
9361 struct drm_i915_gem_object *obj,
9362 struct intel_engine_cs *ring,
9365 struct drm_i915_private *dev_priv = dev->dev_private;
9366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9367 uint32_t pf, pipesrc;
9370 ret = intel_ring_begin(ring, 4);
9374 /* i965+ uses the linear or tiled offsets from the
9375 * Display Registers (which do not change across a page-flip)
9376 * so we need only reprogram the base address.
9378 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9380 intel_ring_emit(ring, fb->pitches[0]);
9381 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9384 /* XXX Enabling the panel-fitter across page-flip is so far
9385 * untested on non-native modes, so ignore it for now.
9386 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9389 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9390 intel_ring_emit(ring, pf | pipesrc);
9392 intel_mark_page_flip_active(intel_crtc);
9393 __intel_ring_advance(ring);
9397 static int intel_gen6_queue_flip(struct drm_device *dev,
9398 struct drm_crtc *crtc,
9399 struct drm_framebuffer *fb,
9400 struct drm_i915_gem_object *obj,
9401 struct intel_engine_cs *ring,
9404 struct drm_i915_private *dev_priv = dev->dev_private;
9405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9406 uint32_t pf, pipesrc;
9409 ret = intel_ring_begin(ring, 4);
9413 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9414 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9415 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9416 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9418 /* Contrary to the suggestions in the documentation,
9419 * "Enable Panel Fitter" does not seem to be required when page
9420 * flipping with a non-native mode, and worse causes a normal
9422 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9425 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9426 intel_ring_emit(ring, pf | pipesrc);
9428 intel_mark_page_flip_active(intel_crtc);
9429 __intel_ring_advance(ring);
9433 static int intel_gen7_queue_flip(struct drm_device *dev,
9434 struct drm_crtc *crtc,
9435 struct drm_framebuffer *fb,
9436 struct drm_i915_gem_object *obj,
9437 struct intel_engine_cs *ring,
9440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9441 uint32_t plane_bit = 0;
9444 switch (intel_crtc->plane) {
9446 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9449 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9452 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9455 WARN_ONCE(1, "unknown plane in flip command\n");
9460 if (ring->id == RCS) {
9463 * On Gen 8, SRM is now taking an extra dword to accommodate
9464 * 48bits addresses, and we need a NOOP for the batch size to
9472 * BSpec MI_DISPLAY_FLIP for IVB:
9473 * "The full packet must be contained within the same cache line."
9475 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9476 * cacheline, if we ever start emitting more commands before
9477 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9478 * then do the cacheline alignment, and finally emit the
9481 ret = intel_ring_cacheline_align(ring);
9485 ret = intel_ring_begin(ring, len);
9489 /* Unmask the flip-done completion message. Note that the bspec says that
9490 * we should do this for both the BCS and RCS, and that we must not unmask
9491 * more than one flip event at any time (or ensure that one flip message
9492 * can be sent by waiting for flip-done prior to queueing new flips).
9493 * Experimentation says that BCS works despite DERRMR masking all
9494 * flip-done completion events and that unmasking all planes at once
9495 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9496 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9498 if (ring->id == RCS) {
9499 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9500 intel_ring_emit(ring, DERRMR);
9501 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9502 DERRMR_PIPEB_PRI_FLIP_DONE |
9503 DERRMR_PIPEC_PRI_FLIP_DONE));
9505 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9506 MI_SRM_LRM_GLOBAL_GTT);
9508 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9509 MI_SRM_LRM_GLOBAL_GTT);
9510 intel_ring_emit(ring, DERRMR);
9511 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9513 intel_ring_emit(ring, 0);
9514 intel_ring_emit(ring, MI_NOOP);
9518 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9519 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9520 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9521 intel_ring_emit(ring, (MI_NOOP));
9523 intel_mark_page_flip_active(intel_crtc);
9524 __intel_ring_advance(ring);
9528 static bool use_mmio_flip(struct intel_engine_cs *ring,
9529 struct drm_i915_gem_object *obj)
9532 * This is not being used for older platforms, because
9533 * non-availability of flip done interrupt forces us to use
9534 * CS flips. Older platforms derive flip done using some clever
9535 * tricks involving the flip_pending status bits and vblank irqs.
9536 * So using MMIO flips there would disrupt this mechanism.
9542 if (INTEL_INFO(ring->dev)->gen < 5)
9545 if (i915.use_mmio_flip < 0)
9547 else if (i915.use_mmio_flip > 0)
9549 else if (i915.enable_execlists)
9552 return ring != obj->ring;
9555 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9557 struct drm_device *dev = intel_crtc->base.dev;
9558 struct drm_i915_private *dev_priv = dev->dev_private;
9559 struct intel_framebuffer *intel_fb =
9560 to_intel_framebuffer(intel_crtc->base.primary->fb);
9561 struct drm_i915_gem_object *obj = intel_fb->obj;
9565 intel_mark_page_flip_active(intel_crtc);
9567 reg = DSPCNTR(intel_crtc->plane);
9568 dspcntr = I915_READ(reg);
9570 if (obj->tiling_mode != I915_TILING_NONE)
9571 dspcntr |= DISPPLANE_TILED;
9573 dspcntr &= ~DISPPLANE_TILED;
9575 I915_WRITE(reg, dspcntr);
9577 I915_WRITE(DSPSURF(intel_crtc->plane),
9578 intel_crtc->unpin_work->gtt_offset);
9579 POSTING_READ(DSPSURF(intel_crtc->plane));
9582 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9584 struct intel_engine_cs *ring;
9587 lockdep_assert_held(&obj->base.dev->struct_mutex);
9589 if (!obj->last_write_seqno)
9594 if (i915_seqno_passed(ring->get_seqno(ring, true),
9595 obj->last_write_seqno))
9598 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9602 if (WARN_ON(!ring->irq_get(ring)))
9608 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9610 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9611 struct intel_crtc *intel_crtc;
9612 unsigned long irq_flags;
9615 seqno = ring->get_seqno(ring, false);
9617 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9618 for_each_intel_crtc(ring->dev, intel_crtc) {
9619 struct intel_mmio_flip *mmio_flip;
9621 mmio_flip = &intel_crtc->mmio_flip;
9622 if (mmio_flip->seqno == 0)
9625 if (ring->id != mmio_flip->ring_id)
9628 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9629 intel_do_mmio_flip(intel_crtc);
9630 mmio_flip->seqno = 0;
9631 ring->irq_put(ring);
9634 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9637 static int intel_queue_mmio_flip(struct drm_device *dev,
9638 struct drm_crtc *crtc,
9639 struct drm_framebuffer *fb,
9640 struct drm_i915_gem_object *obj,
9641 struct intel_engine_cs *ring,
9644 struct drm_i915_private *dev_priv = dev->dev_private;
9645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9648 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9651 ret = intel_postpone_flip(obj);
9655 intel_do_mmio_flip(intel_crtc);
9659 spin_lock_irq(&dev_priv->mmio_flip_lock);
9660 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9661 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9662 spin_unlock_irq(&dev_priv->mmio_flip_lock);
9665 * Double check to catch cases where irq fired before
9666 * mmio flip data was ready
9668 intel_notify_mmio_flip(obj->ring);
9672 static int intel_default_queue_flip(struct drm_device *dev,
9673 struct drm_crtc *crtc,
9674 struct drm_framebuffer *fb,
9675 struct drm_i915_gem_object *obj,
9676 struct intel_engine_cs *ring,
9682 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9683 struct drm_crtc *crtc)
9685 struct drm_i915_private *dev_priv = dev->dev_private;
9686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9687 struct intel_unpin_work *work = intel_crtc->unpin_work;
9690 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9693 if (!work->enable_stall_check)
9696 if (work->flip_ready_vblank == 0) {
9697 if (work->flip_queued_ring &&
9698 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9699 work->flip_queued_seqno))
9702 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9705 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9708 /* Potential stall - if we see that the flip has happened,
9709 * assume a missed interrupt. */
9710 if (INTEL_INFO(dev)->gen >= 4)
9711 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9713 addr = I915_READ(DSPADDR(intel_crtc->plane));
9715 /* There is a potential issue here with a false positive after a flip
9716 * to the same address. We could address this by checking for a
9717 * non-incrementing frame counter.
9719 return addr == work->gtt_offset;
9722 void intel_check_page_flip(struct drm_device *dev, int pipe)
9724 struct drm_i915_private *dev_priv = dev->dev_private;
9725 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9733 spin_lock(&dev->event_lock);
9734 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9735 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9736 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9737 page_flip_completed(intel_crtc);
9739 spin_unlock(&dev->event_lock);
9742 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9743 struct drm_framebuffer *fb,
9744 struct drm_pending_vblank_event *event,
9745 uint32_t page_flip_flags)
9747 struct drm_device *dev = crtc->dev;
9748 struct drm_i915_private *dev_priv = dev->dev_private;
9749 struct drm_framebuffer *old_fb = crtc->primary->fb;
9750 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9752 enum pipe pipe = intel_crtc->pipe;
9753 struct intel_unpin_work *work;
9754 struct intel_engine_cs *ring;
9758 * drm_mode_page_flip_ioctl() should already catch this, but double
9759 * check to be safe. In the future we may enable pageflipping from
9760 * a disabled primary plane.
9762 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9765 /* Can't change pixel format via MI display flips. */
9766 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9770 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9771 * Note that pitch changes could also affect these register.
9773 if (INTEL_INFO(dev)->gen > 3 &&
9774 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9775 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9778 if (i915_terminally_wedged(&dev_priv->gpu_error))
9781 work = kzalloc(sizeof(*work), GFP_KERNEL);
9785 work->event = event;
9787 work->old_fb_obj = intel_fb_obj(old_fb);
9788 INIT_WORK(&work->work, intel_unpin_work_fn);
9790 ret = drm_crtc_vblank_get(crtc);
9794 /* We borrow the event spin lock for protecting unpin_work */
9795 spin_lock_irq(&dev->event_lock);
9796 if (intel_crtc->unpin_work) {
9797 /* Before declaring the flip queue wedged, check if
9798 * the hardware completed the operation behind our backs.
9800 if (__intel_pageflip_stall_check(dev, crtc)) {
9801 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9802 page_flip_completed(intel_crtc);
9804 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9805 spin_unlock_irq(&dev->event_lock);
9807 drm_crtc_vblank_put(crtc);
9812 intel_crtc->unpin_work = work;
9813 spin_unlock_irq(&dev->event_lock);
9815 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9816 flush_workqueue(dev_priv->wq);
9818 ret = i915_mutex_lock_interruptible(dev);
9822 /* Reference the objects for the scheduled work. */
9823 drm_gem_object_reference(&work->old_fb_obj->base);
9824 drm_gem_object_reference(&obj->base);
9826 crtc->primary->fb = fb;
9828 work->pending_flip_obj = obj;
9830 atomic_inc(&intel_crtc->unpin_work_count);
9831 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9833 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9834 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9836 if (IS_VALLEYVIEW(dev)) {
9837 ring = &dev_priv->ring[BCS];
9838 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9839 /* vlv: DISPLAY_FLIP fails to change tiling */
9841 } else if (IS_IVYBRIDGE(dev)) {
9842 ring = &dev_priv->ring[BCS];
9843 } else if (INTEL_INFO(dev)->gen >= 7) {
9845 if (ring == NULL || ring->id != RCS)
9846 ring = &dev_priv->ring[BCS];
9848 ring = &dev_priv->ring[RCS];
9851 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9853 goto cleanup_pending;
9856 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9858 if (use_mmio_flip(ring, obj)) {
9859 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9864 work->flip_queued_seqno = obj->last_write_seqno;
9865 work->flip_queued_ring = obj->ring;
9867 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9872 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9873 work->flip_queued_ring = ring;
9876 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9877 work->enable_stall_check = true;
9879 i915_gem_track_fb(work->old_fb_obj, obj,
9880 INTEL_FRONTBUFFER_PRIMARY(pipe));
9882 intel_disable_fbc(dev);
9883 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9884 mutex_unlock(&dev->struct_mutex);
9886 trace_i915_flip_request(intel_crtc->plane, obj);
9891 intel_unpin_fb_obj(obj);
9893 atomic_dec(&intel_crtc->unpin_work_count);
9894 crtc->primary->fb = old_fb;
9895 drm_gem_object_unreference(&work->old_fb_obj->base);
9896 drm_gem_object_unreference(&obj->base);
9897 mutex_unlock(&dev->struct_mutex);
9900 spin_lock_irq(&dev->event_lock);
9901 intel_crtc->unpin_work = NULL;
9902 spin_unlock_irq(&dev->event_lock);
9904 drm_crtc_vblank_put(crtc);
9910 intel_crtc_wait_for_pending_flips(crtc);
9911 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9912 if (ret == 0 && event) {
9913 spin_lock_irq(&dev->event_lock);
9914 drm_send_vblank_event(dev, pipe, event);
9915 spin_unlock_irq(&dev->event_lock);
9921 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9922 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9923 .load_lut = intel_crtc_load_lut,
9927 * intel_modeset_update_staged_output_state
9929 * Updates the staged output configuration state, e.g. after we've read out the
9932 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9934 struct intel_crtc *crtc;
9935 struct intel_encoder *encoder;
9936 struct intel_connector *connector;
9938 list_for_each_entry(connector, &dev->mode_config.connector_list,
9940 connector->new_encoder =
9941 to_intel_encoder(connector->base.encoder);
9944 for_each_intel_encoder(dev, encoder) {
9946 to_intel_crtc(encoder->base.crtc);
9949 for_each_intel_crtc(dev, crtc) {
9950 crtc->new_enabled = crtc->base.enabled;
9952 if (crtc->new_enabled)
9953 crtc->new_config = &crtc->config;
9955 crtc->new_config = NULL;
9960 * intel_modeset_commit_output_state
9962 * This function copies the stage display pipe configuration to the real one.
9964 static void intel_modeset_commit_output_state(struct drm_device *dev)
9966 struct intel_crtc *crtc;
9967 struct intel_encoder *encoder;
9968 struct intel_connector *connector;
9970 list_for_each_entry(connector, &dev->mode_config.connector_list,
9972 connector->base.encoder = &connector->new_encoder->base;
9975 for_each_intel_encoder(dev, encoder) {
9976 encoder->base.crtc = &encoder->new_crtc->base;
9979 for_each_intel_crtc(dev, crtc) {
9980 crtc->base.enabled = crtc->new_enabled;
9985 connected_sink_compute_bpp(struct intel_connector *connector,
9986 struct intel_crtc_config *pipe_config)
9988 int bpp = pipe_config->pipe_bpp;
9990 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9991 connector->base.base.id,
9992 connector->base.name);
9994 /* Don't use an invalid EDID bpc value */
9995 if (connector->base.display_info.bpc &&
9996 connector->base.display_info.bpc * 3 < bpp) {
9997 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9998 bpp, connector->base.display_info.bpc*3);
9999 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10002 /* Clamp bpp to 8 on screens without EDID 1.4 */
10003 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10004 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10006 pipe_config->pipe_bpp = 24;
10011 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10012 struct drm_framebuffer *fb,
10013 struct intel_crtc_config *pipe_config)
10015 struct drm_device *dev = crtc->base.dev;
10016 struct intel_connector *connector;
10019 switch (fb->pixel_format) {
10020 case DRM_FORMAT_C8:
10021 bpp = 8*3; /* since we go through a colormap */
10023 case DRM_FORMAT_XRGB1555:
10024 case DRM_FORMAT_ARGB1555:
10025 /* checked in intel_framebuffer_init already */
10026 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10028 case DRM_FORMAT_RGB565:
10029 bpp = 6*3; /* min is 18bpp */
10031 case DRM_FORMAT_XBGR8888:
10032 case DRM_FORMAT_ABGR8888:
10033 /* checked in intel_framebuffer_init already */
10034 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10036 case DRM_FORMAT_XRGB8888:
10037 case DRM_FORMAT_ARGB8888:
10040 case DRM_FORMAT_XRGB2101010:
10041 case DRM_FORMAT_ARGB2101010:
10042 case DRM_FORMAT_XBGR2101010:
10043 case DRM_FORMAT_ABGR2101010:
10044 /* checked in intel_framebuffer_init already */
10045 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10049 /* TODO: gen4+ supports 16 bpc floating point, too. */
10051 DRM_DEBUG_KMS("unsupported depth\n");
10055 pipe_config->pipe_bpp = bpp;
10057 /* Clamp display bpp to EDID value */
10058 list_for_each_entry(connector, &dev->mode_config.connector_list,
10060 if (!connector->new_encoder ||
10061 connector->new_encoder->new_crtc != crtc)
10064 connected_sink_compute_bpp(connector, pipe_config);
10070 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10072 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10073 "type: 0x%x flags: 0x%x\n",
10075 mode->crtc_hdisplay, mode->crtc_hsync_start,
10076 mode->crtc_hsync_end, mode->crtc_htotal,
10077 mode->crtc_vdisplay, mode->crtc_vsync_start,
10078 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10081 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10082 struct intel_crtc_config *pipe_config,
10083 const char *context)
10085 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10086 context, pipe_name(crtc->pipe));
10088 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10089 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10090 pipe_config->pipe_bpp, pipe_config->dither);
10091 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10092 pipe_config->has_pch_encoder,
10093 pipe_config->fdi_lanes,
10094 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10095 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10096 pipe_config->fdi_m_n.tu);
10097 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10098 pipe_config->has_dp_encoder,
10099 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10100 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10101 pipe_config->dp_m_n.tu);
10103 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10104 pipe_config->has_dp_encoder,
10105 pipe_config->dp_m2_n2.gmch_m,
10106 pipe_config->dp_m2_n2.gmch_n,
10107 pipe_config->dp_m2_n2.link_m,
10108 pipe_config->dp_m2_n2.link_n,
10109 pipe_config->dp_m2_n2.tu);
10111 DRM_DEBUG_KMS("requested mode:\n");
10112 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10113 DRM_DEBUG_KMS("adjusted mode:\n");
10114 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10115 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10116 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10117 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10118 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10119 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10120 pipe_config->gmch_pfit.control,
10121 pipe_config->gmch_pfit.pgm_ratios,
10122 pipe_config->gmch_pfit.lvds_border_bits);
10123 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10124 pipe_config->pch_pfit.pos,
10125 pipe_config->pch_pfit.size,
10126 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10127 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10128 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10131 static bool encoders_cloneable(const struct intel_encoder *a,
10132 const struct intel_encoder *b)
10134 /* masks could be asymmetric, so check both ways */
10135 return a == b || (a->cloneable & (1 << b->type) &&
10136 b->cloneable & (1 << a->type));
10139 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10140 struct intel_encoder *encoder)
10142 struct drm_device *dev = crtc->base.dev;
10143 struct intel_encoder *source_encoder;
10145 for_each_intel_encoder(dev, source_encoder) {
10146 if (source_encoder->new_crtc != crtc)
10149 if (!encoders_cloneable(encoder, source_encoder))
10156 static bool check_encoder_cloning(struct intel_crtc *crtc)
10158 struct drm_device *dev = crtc->base.dev;
10159 struct intel_encoder *encoder;
10161 for_each_intel_encoder(dev, encoder) {
10162 if (encoder->new_crtc != crtc)
10165 if (!check_single_encoder_cloning(crtc, encoder))
10172 static struct intel_crtc_config *
10173 intel_modeset_pipe_config(struct drm_crtc *crtc,
10174 struct drm_framebuffer *fb,
10175 struct drm_display_mode *mode)
10177 struct drm_device *dev = crtc->dev;
10178 struct intel_encoder *encoder;
10179 struct intel_crtc_config *pipe_config;
10180 int plane_bpp, ret = -EINVAL;
10183 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10184 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10185 return ERR_PTR(-EINVAL);
10188 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10190 return ERR_PTR(-ENOMEM);
10192 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10193 drm_mode_copy(&pipe_config->requested_mode, mode);
10195 pipe_config->cpu_transcoder =
10196 (enum transcoder) to_intel_crtc(crtc)->pipe;
10197 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10200 * Sanitize sync polarity flags based on requested ones. If neither
10201 * positive or negative polarity is requested, treat this as meaning
10202 * negative polarity.
10204 if (!(pipe_config->adjusted_mode.flags &
10205 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10206 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10208 if (!(pipe_config->adjusted_mode.flags &
10209 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10210 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10212 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10213 * plane pixel format and any sink constraints into account. Returns the
10214 * source plane bpp so that dithering can be selected on mismatches
10215 * after encoders and crtc also have had their say. */
10216 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10222 * Determine the real pipe dimensions. Note that stereo modes can
10223 * increase the actual pipe size due to the frame doubling and
10224 * insertion of additional space for blanks between the frame. This
10225 * is stored in the crtc timings. We use the requested mode to do this
10226 * computation to clearly distinguish it from the adjusted mode, which
10227 * can be changed by the connectors in the below retry loop.
10229 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10230 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10231 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10234 /* Ensure the port clock defaults are reset when retrying. */
10235 pipe_config->port_clock = 0;
10236 pipe_config->pixel_multiplier = 1;
10238 /* Fill in default crtc timings, allow encoders to overwrite them. */
10239 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10241 /* Pass our mode to the connectors and the CRTC to give them a chance to
10242 * adjust it according to limitations or connector properties, and also
10243 * a chance to reject the mode entirely.
10245 for_each_intel_encoder(dev, encoder) {
10247 if (&encoder->new_crtc->base != crtc)
10250 if (!(encoder->compute_config(encoder, pipe_config))) {
10251 DRM_DEBUG_KMS("Encoder config failure\n");
10256 /* Set default port clock if not overwritten by the encoder. Needs to be
10257 * done afterwards in case the encoder adjusts the mode. */
10258 if (!pipe_config->port_clock)
10259 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10260 * pipe_config->pixel_multiplier;
10262 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10264 DRM_DEBUG_KMS("CRTC fixup failed\n");
10268 if (ret == RETRY) {
10269 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10274 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10276 goto encoder_retry;
10279 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10280 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10281 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10283 return pipe_config;
10285 kfree(pipe_config);
10286 return ERR_PTR(ret);
10289 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10290 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10292 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10293 unsigned *prepare_pipes, unsigned *disable_pipes)
10295 struct intel_crtc *intel_crtc;
10296 struct drm_device *dev = crtc->dev;
10297 struct intel_encoder *encoder;
10298 struct intel_connector *connector;
10299 struct drm_crtc *tmp_crtc;
10301 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10303 /* Check which crtcs have changed outputs connected to them, these need
10304 * to be part of the prepare_pipes mask. We don't (yet) support global
10305 * modeset across multiple crtcs, so modeset_pipes will only have one
10306 * bit set at most. */
10307 list_for_each_entry(connector, &dev->mode_config.connector_list,
10309 if (connector->base.encoder == &connector->new_encoder->base)
10312 if (connector->base.encoder) {
10313 tmp_crtc = connector->base.encoder->crtc;
10315 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10318 if (connector->new_encoder)
10320 1 << connector->new_encoder->new_crtc->pipe;
10323 for_each_intel_encoder(dev, encoder) {
10324 if (encoder->base.crtc == &encoder->new_crtc->base)
10327 if (encoder->base.crtc) {
10328 tmp_crtc = encoder->base.crtc;
10330 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10333 if (encoder->new_crtc)
10334 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10337 /* Check for pipes that will be enabled/disabled ... */
10338 for_each_intel_crtc(dev, intel_crtc) {
10339 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10342 if (!intel_crtc->new_enabled)
10343 *disable_pipes |= 1 << intel_crtc->pipe;
10345 *prepare_pipes |= 1 << intel_crtc->pipe;
10349 /* set_mode is also used to update properties on life display pipes. */
10350 intel_crtc = to_intel_crtc(crtc);
10351 if (intel_crtc->new_enabled)
10352 *prepare_pipes |= 1 << intel_crtc->pipe;
10355 * For simplicity do a full modeset on any pipe where the output routing
10356 * changed. We could be more clever, but that would require us to be
10357 * more careful with calling the relevant encoder->mode_set functions.
10359 if (*prepare_pipes)
10360 *modeset_pipes = *prepare_pipes;
10362 /* ... and mask these out. */
10363 *modeset_pipes &= ~(*disable_pipes);
10364 *prepare_pipes &= ~(*disable_pipes);
10367 * HACK: We don't (yet) fully support global modesets. intel_set_config
10368 * obies this rule, but the modeset restore mode of
10369 * intel_modeset_setup_hw_state does not.
10371 *modeset_pipes &= 1 << intel_crtc->pipe;
10372 *prepare_pipes &= 1 << intel_crtc->pipe;
10374 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10375 *modeset_pipes, *prepare_pipes, *disable_pipes);
10378 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10380 struct drm_encoder *encoder;
10381 struct drm_device *dev = crtc->dev;
10383 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10384 if (encoder->crtc == crtc)
10391 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10393 struct intel_encoder *intel_encoder;
10394 struct intel_crtc *intel_crtc;
10395 struct drm_connector *connector;
10397 for_each_intel_encoder(dev, intel_encoder) {
10398 if (!intel_encoder->base.crtc)
10401 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10403 if (prepare_pipes & (1 << intel_crtc->pipe))
10404 intel_encoder->connectors_active = false;
10407 intel_modeset_commit_output_state(dev);
10409 /* Double check state. */
10410 for_each_intel_crtc(dev, intel_crtc) {
10411 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10412 WARN_ON(intel_crtc->new_config &&
10413 intel_crtc->new_config != &intel_crtc->config);
10414 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10417 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10418 if (!connector->encoder || !connector->encoder->crtc)
10421 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10423 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10424 struct drm_property *dpms_property =
10425 dev->mode_config.dpms_property;
10427 connector->dpms = DRM_MODE_DPMS_ON;
10428 drm_object_property_set_value(&connector->base,
10432 intel_encoder = to_intel_encoder(connector->encoder);
10433 intel_encoder->connectors_active = true;
10439 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10443 if (clock1 == clock2)
10446 if (!clock1 || !clock2)
10449 diff = abs(clock1 - clock2);
10451 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10457 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10458 list_for_each_entry((intel_crtc), \
10459 &(dev)->mode_config.crtc_list, \
10461 if (mask & (1 <<(intel_crtc)->pipe))
10464 intel_pipe_config_compare(struct drm_device *dev,
10465 struct intel_crtc_config *current_config,
10466 struct intel_crtc_config *pipe_config)
10468 #define PIPE_CONF_CHECK_X(name) \
10469 if (current_config->name != pipe_config->name) { \
10470 DRM_ERROR("mismatch in " #name " " \
10471 "(expected 0x%08x, found 0x%08x)\n", \
10472 current_config->name, \
10473 pipe_config->name); \
10477 #define PIPE_CONF_CHECK_I(name) \
10478 if (current_config->name != pipe_config->name) { \
10479 DRM_ERROR("mismatch in " #name " " \
10480 "(expected %i, found %i)\n", \
10481 current_config->name, \
10482 pipe_config->name); \
10486 /* This is required for BDW+ where there is only one set of registers for
10487 * switching between high and low RR.
10488 * This macro can be used whenever a comparison has to be made between one
10489 * hw state and multiple sw state variables.
10491 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10492 if ((current_config->name != pipe_config->name) && \
10493 (current_config->alt_name != pipe_config->name)) { \
10494 DRM_ERROR("mismatch in " #name " " \
10495 "(expected %i or %i, found %i)\n", \
10496 current_config->name, \
10497 current_config->alt_name, \
10498 pipe_config->name); \
10502 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10503 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10504 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10505 "(expected %i, found %i)\n", \
10506 current_config->name & (mask), \
10507 pipe_config->name & (mask)); \
10511 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10512 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10513 DRM_ERROR("mismatch in " #name " " \
10514 "(expected %i, found %i)\n", \
10515 current_config->name, \
10516 pipe_config->name); \
10520 #define PIPE_CONF_QUIRK(quirk) \
10521 ((current_config->quirks | pipe_config->quirks) & (quirk))
10523 PIPE_CONF_CHECK_I(cpu_transcoder);
10525 PIPE_CONF_CHECK_I(has_pch_encoder);
10526 PIPE_CONF_CHECK_I(fdi_lanes);
10527 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10528 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10529 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10530 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10531 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10533 PIPE_CONF_CHECK_I(has_dp_encoder);
10535 if (INTEL_INFO(dev)->gen < 8) {
10536 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10537 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10538 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10539 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10540 PIPE_CONF_CHECK_I(dp_m_n.tu);
10542 if (current_config->has_drrs) {
10543 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10544 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10545 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10546 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10547 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10550 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10551 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10552 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10553 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10554 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10557 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10558 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10559 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10560 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10561 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10562 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10564 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10565 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10566 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10567 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10568 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10569 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10571 PIPE_CONF_CHECK_I(pixel_multiplier);
10572 PIPE_CONF_CHECK_I(has_hdmi_sink);
10573 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10574 IS_VALLEYVIEW(dev))
10575 PIPE_CONF_CHECK_I(limited_color_range);
10577 PIPE_CONF_CHECK_I(has_audio);
10579 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10580 DRM_MODE_FLAG_INTERLACE);
10582 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10583 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10584 DRM_MODE_FLAG_PHSYNC);
10585 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10586 DRM_MODE_FLAG_NHSYNC);
10587 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10588 DRM_MODE_FLAG_PVSYNC);
10589 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10590 DRM_MODE_FLAG_NVSYNC);
10593 PIPE_CONF_CHECK_I(pipe_src_w);
10594 PIPE_CONF_CHECK_I(pipe_src_h);
10597 * FIXME: BIOS likes to set up a cloned config with lvds+external
10598 * screen. Since we don't yet re-compute the pipe config when moving
10599 * just the lvds port away to another pipe the sw tracking won't match.
10601 * Proper atomic modesets with recomputed global state will fix this.
10602 * Until then just don't check gmch state for inherited modes.
10604 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10605 PIPE_CONF_CHECK_I(gmch_pfit.control);
10606 /* pfit ratios are autocomputed by the hw on gen4+ */
10607 if (INTEL_INFO(dev)->gen < 4)
10608 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10609 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10612 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10613 if (current_config->pch_pfit.enabled) {
10614 PIPE_CONF_CHECK_I(pch_pfit.pos);
10615 PIPE_CONF_CHECK_I(pch_pfit.size);
10618 /* BDW+ don't expose a synchronous way to read the state */
10619 if (IS_HASWELL(dev))
10620 PIPE_CONF_CHECK_I(ips_enabled);
10622 PIPE_CONF_CHECK_I(double_wide);
10624 PIPE_CONF_CHECK_X(ddi_pll_sel);
10626 PIPE_CONF_CHECK_I(shared_dpll);
10627 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10628 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10629 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10630 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10631 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10633 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10634 PIPE_CONF_CHECK_I(pipe_bpp);
10636 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10637 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10639 #undef PIPE_CONF_CHECK_X
10640 #undef PIPE_CONF_CHECK_I
10641 #undef PIPE_CONF_CHECK_I_ALT
10642 #undef PIPE_CONF_CHECK_FLAGS
10643 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10644 #undef PIPE_CONF_QUIRK
10650 check_connector_state(struct drm_device *dev)
10652 struct intel_connector *connector;
10654 list_for_each_entry(connector, &dev->mode_config.connector_list,
10656 /* This also checks the encoder/connector hw state with the
10657 * ->get_hw_state callbacks. */
10658 intel_connector_check_state(connector);
10660 WARN(&connector->new_encoder->base != connector->base.encoder,
10661 "connector's staged encoder doesn't match current encoder\n");
10666 check_encoder_state(struct drm_device *dev)
10668 struct intel_encoder *encoder;
10669 struct intel_connector *connector;
10671 for_each_intel_encoder(dev, encoder) {
10672 bool enabled = false;
10673 bool active = false;
10674 enum pipe pipe, tracked_pipe;
10676 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10677 encoder->base.base.id,
10678 encoder->base.name);
10680 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10681 "encoder's stage crtc doesn't match current crtc\n");
10682 WARN(encoder->connectors_active && !encoder->base.crtc,
10683 "encoder's active_connectors set, but no crtc\n");
10685 list_for_each_entry(connector, &dev->mode_config.connector_list,
10687 if (connector->base.encoder != &encoder->base)
10690 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10694 * for MST connectors if we unplug the connector is gone
10695 * away but the encoder is still connected to a crtc
10696 * until a modeset happens in response to the hotplug.
10698 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10701 WARN(!!encoder->base.crtc != enabled,
10702 "encoder's enabled state mismatch "
10703 "(expected %i, found %i)\n",
10704 !!encoder->base.crtc, enabled);
10705 WARN(active && !encoder->base.crtc,
10706 "active encoder with no crtc\n");
10708 WARN(encoder->connectors_active != active,
10709 "encoder's computed active state doesn't match tracked active state "
10710 "(expected %i, found %i)\n", active, encoder->connectors_active);
10712 active = encoder->get_hw_state(encoder, &pipe);
10713 WARN(active != encoder->connectors_active,
10714 "encoder's hw state doesn't match sw tracking "
10715 "(expected %i, found %i)\n",
10716 encoder->connectors_active, active);
10718 if (!encoder->base.crtc)
10721 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10722 WARN(active && pipe != tracked_pipe,
10723 "active encoder's pipe doesn't match"
10724 "(expected %i, found %i)\n",
10725 tracked_pipe, pipe);
10731 check_crtc_state(struct drm_device *dev)
10733 struct drm_i915_private *dev_priv = dev->dev_private;
10734 struct intel_crtc *crtc;
10735 struct intel_encoder *encoder;
10736 struct intel_crtc_config pipe_config;
10738 for_each_intel_crtc(dev, crtc) {
10739 bool enabled = false;
10740 bool active = false;
10742 memset(&pipe_config, 0, sizeof(pipe_config));
10744 DRM_DEBUG_KMS("[CRTC:%d]\n",
10745 crtc->base.base.id);
10747 WARN(crtc->active && !crtc->base.enabled,
10748 "active crtc, but not enabled in sw tracking\n");
10750 for_each_intel_encoder(dev, encoder) {
10751 if (encoder->base.crtc != &crtc->base)
10754 if (encoder->connectors_active)
10758 WARN(active != crtc->active,
10759 "crtc's computed active state doesn't match tracked active state "
10760 "(expected %i, found %i)\n", active, crtc->active);
10761 WARN(enabled != crtc->base.enabled,
10762 "crtc's computed enabled state doesn't match tracked enabled state "
10763 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10765 active = dev_priv->display.get_pipe_config(crtc,
10768 /* hw state is inconsistent with the pipe quirk */
10769 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10770 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10771 active = crtc->active;
10773 for_each_intel_encoder(dev, encoder) {
10775 if (encoder->base.crtc != &crtc->base)
10777 if (encoder->get_hw_state(encoder, &pipe))
10778 encoder->get_config(encoder, &pipe_config);
10781 WARN(crtc->active != active,
10782 "crtc active state doesn't match with hw state "
10783 "(expected %i, found %i)\n", crtc->active, active);
10786 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10787 WARN(1, "pipe state doesn't match!\n");
10788 intel_dump_pipe_config(crtc, &pipe_config,
10790 intel_dump_pipe_config(crtc, &crtc->config,
10797 check_shared_dpll_state(struct drm_device *dev)
10799 struct drm_i915_private *dev_priv = dev->dev_private;
10800 struct intel_crtc *crtc;
10801 struct intel_dpll_hw_state dpll_hw_state;
10804 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10805 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10806 int enabled_crtcs = 0, active_crtcs = 0;
10809 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10811 DRM_DEBUG_KMS("%s\n", pll->name);
10813 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10815 WARN(pll->active > pll->refcount,
10816 "more active pll users than references: %i vs %i\n",
10817 pll->active, pll->refcount);
10818 WARN(pll->active && !pll->on,
10819 "pll in active use but not on in sw tracking\n");
10820 WARN(pll->on && !pll->active,
10821 "pll in on but not on in use in sw tracking\n");
10822 WARN(pll->on != active,
10823 "pll on state mismatch (expected %i, found %i)\n",
10826 for_each_intel_crtc(dev, crtc) {
10827 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10829 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10832 WARN(pll->active != active_crtcs,
10833 "pll active crtcs mismatch (expected %i, found %i)\n",
10834 pll->active, active_crtcs);
10835 WARN(pll->refcount != enabled_crtcs,
10836 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10837 pll->refcount, enabled_crtcs);
10839 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10840 sizeof(dpll_hw_state)),
10841 "pll hw state mismatch\n");
10846 intel_modeset_check_state(struct drm_device *dev)
10848 check_connector_state(dev);
10849 check_encoder_state(dev);
10850 check_crtc_state(dev);
10851 check_shared_dpll_state(dev);
10854 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10858 * FDI already provided one idea for the dotclock.
10859 * Yell if the encoder disagrees.
10861 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10862 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10863 pipe_config->adjusted_mode.crtc_clock, dotclock);
10866 static void update_scanline_offset(struct intel_crtc *crtc)
10868 struct drm_device *dev = crtc->base.dev;
10871 * The scanline counter increments at the leading edge of hsync.
10873 * On most platforms it starts counting from vtotal-1 on the
10874 * first active line. That means the scanline counter value is
10875 * always one less than what we would expect. Ie. just after
10876 * start of vblank, which also occurs at start of hsync (on the
10877 * last active line), the scanline counter will read vblank_start-1.
10879 * On gen2 the scanline counter starts counting from 1 instead
10880 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10881 * to keep the value positive), instead of adding one.
10883 * On HSW+ the behaviour of the scanline counter depends on the output
10884 * type. For DP ports it behaves like most other platforms, but on HDMI
10885 * there's an extra 1 line difference. So we need to add two instead of
10886 * one to the value.
10888 if (IS_GEN2(dev)) {
10889 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10892 vtotal = mode->crtc_vtotal;
10893 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10896 crtc->scanline_offset = vtotal - 1;
10897 } else if (HAS_DDI(dev) &&
10898 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10899 crtc->scanline_offset = 2;
10901 crtc->scanline_offset = 1;
10904 static int __intel_set_mode(struct drm_crtc *crtc,
10905 struct drm_display_mode *mode,
10906 int x, int y, struct drm_framebuffer *fb)
10908 struct drm_device *dev = crtc->dev;
10909 struct drm_i915_private *dev_priv = dev->dev_private;
10910 struct drm_display_mode *saved_mode;
10911 struct intel_crtc_config *pipe_config = NULL;
10912 struct intel_crtc *intel_crtc;
10913 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10916 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10920 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10921 &prepare_pipes, &disable_pipes);
10923 *saved_mode = crtc->mode;
10925 /* Hack: Because we don't (yet) support global modeset on multiple
10926 * crtcs, we don't keep track of the new mode for more than one crtc.
10927 * Hence simply check whether any bit is set in modeset_pipes in all the
10928 * pieces of code that are not yet converted to deal with mutliple crtcs
10929 * changing their mode at the same time. */
10930 if (modeset_pipes) {
10931 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10932 if (IS_ERR(pipe_config)) {
10933 ret = PTR_ERR(pipe_config);
10934 pipe_config = NULL;
10938 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10940 to_intel_crtc(crtc)->new_config = pipe_config;
10944 * See if the config requires any additional preparation, e.g.
10945 * to adjust global state with pipes off. We need to do this
10946 * here so we can get the modeset_pipe updated config for the new
10947 * mode set on this crtc. For other crtcs we need to use the
10948 * adjusted_mode bits in the crtc directly.
10950 if (IS_VALLEYVIEW(dev)) {
10951 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10953 /* may have added more to prepare_pipes than we should */
10954 prepare_pipes &= ~disable_pipes;
10957 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10958 intel_crtc_disable(&intel_crtc->base);
10960 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10961 if (intel_crtc->base.enabled)
10962 dev_priv->display.crtc_disable(&intel_crtc->base);
10965 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10966 * to set it here already despite that we pass it down the callchain.
10968 if (modeset_pipes) {
10969 crtc->mode = *mode;
10970 /* mode_set/enable/disable functions rely on a correct pipe
10972 to_intel_crtc(crtc)->config = *pipe_config;
10973 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10976 * Calculate and store various constants which
10977 * are later needed by vblank and swap-completion
10978 * timestamping. They are derived from true hwmode.
10980 drm_calc_timestamping_constants(crtc,
10981 &pipe_config->adjusted_mode);
10984 /* Only after disabling all output pipelines that will be changed can we
10985 * update the the output configuration. */
10986 intel_modeset_update_state(dev, prepare_pipes);
10988 if (dev_priv->display.modeset_global_resources)
10989 dev_priv->display.modeset_global_resources(dev);
10991 /* Set up the DPLL and any encoders state that needs to adjust or depend
10994 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10995 struct drm_framebuffer *old_fb = crtc->primary->fb;
10996 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10997 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10999 mutex_lock(&dev->struct_mutex);
11000 ret = intel_pin_and_fence_fb_obj(dev,
11004 DRM_ERROR("pin & fence failed\n");
11005 mutex_unlock(&dev->struct_mutex);
11009 intel_unpin_fb_obj(old_obj);
11010 i915_gem_track_fb(old_obj, obj,
11011 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11012 mutex_unlock(&dev->struct_mutex);
11014 crtc->primary->fb = fb;
11018 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
11023 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11024 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11025 update_scanline_offset(intel_crtc);
11027 dev_priv->display.crtc_enable(&intel_crtc->base);
11030 /* FIXME: add subpixel order */
11032 if (ret && crtc->enabled)
11033 crtc->mode = *saved_mode;
11036 kfree(pipe_config);
11041 static int intel_set_mode(struct drm_crtc *crtc,
11042 struct drm_display_mode *mode,
11043 int x, int y, struct drm_framebuffer *fb)
11047 ret = __intel_set_mode(crtc, mode, x, y, fb);
11050 intel_modeset_check_state(crtc->dev);
11055 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11057 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11060 #undef for_each_intel_crtc_masked
11062 static void intel_set_config_free(struct intel_set_config *config)
11067 kfree(config->save_connector_encoders);
11068 kfree(config->save_encoder_crtcs);
11069 kfree(config->save_crtc_enabled);
11073 static int intel_set_config_save_state(struct drm_device *dev,
11074 struct intel_set_config *config)
11076 struct drm_crtc *crtc;
11077 struct drm_encoder *encoder;
11078 struct drm_connector *connector;
11081 config->save_crtc_enabled =
11082 kcalloc(dev->mode_config.num_crtc,
11083 sizeof(bool), GFP_KERNEL);
11084 if (!config->save_crtc_enabled)
11087 config->save_encoder_crtcs =
11088 kcalloc(dev->mode_config.num_encoder,
11089 sizeof(struct drm_crtc *), GFP_KERNEL);
11090 if (!config->save_encoder_crtcs)
11093 config->save_connector_encoders =
11094 kcalloc(dev->mode_config.num_connector,
11095 sizeof(struct drm_encoder *), GFP_KERNEL);
11096 if (!config->save_connector_encoders)
11099 /* Copy data. Note that driver private data is not affected.
11100 * Should anything bad happen only the expected state is
11101 * restored, not the drivers personal bookkeeping.
11104 for_each_crtc(dev, crtc) {
11105 config->save_crtc_enabled[count++] = crtc->enabled;
11109 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11110 config->save_encoder_crtcs[count++] = encoder->crtc;
11114 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11115 config->save_connector_encoders[count++] = connector->encoder;
11121 static void intel_set_config_restore_state(struct drm_device *dev,
11122 struct intel_set_config *config)
11124 struct intel_crtc *crtc;
11125 struct intel_encoder *encoder;
11126 struct intel_connector *connector;
11130 for_each_intel_crtc(dev, crtc) {
11131 crtc->new_enabled = config->save_crtc_enabled[count++];
11133 if (crtc->new_enabled)
11134 crtc->new_config = &crtc->config;
11136 crtc->new_config = NULL;
11140 for_each_intel_encoder(dev, encoder) {
11141 encoder->new_crtc =
11142 to_intel_crtc(config->save_encoder_crtcs[count++]);
11146 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11147 connector->new_encoder =
11148 to_intel_encoder(config->save_connector_encoders[count++]);
11153 is_crtc_connector_off(struct drm_mode_set *set)
11157 if (set->num_connectors == 0)
11160 if (WARN_ON(set->connectors == NULL))
11163 for (i = 0; i < set->num_connectors; i++)
11164 if (set->connectors[i]->encoder &&
11165 set->connectors[i]->encoder->crtc == set->crtc &&
11166 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11173 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11174 struct intel_set_config *config)
11177 /* We should be able to check here if the fb has the same properties
11178 * and then just flip_or_move it */
11179 if (is_crtc_connector_off(set)) {
11180 config->mode_changed = true;
11181 } else if (set->crtc->primary->fb != set->fb) {
11183 * If we have no fb, we can only flip as long as the crtc is
11184 * active, otherwise we need a full mode set. The crtc may
11185 * be active if we've only disabled the primary plane, or
11186 * in fastboot situations.
11188 if (set->crtc->primary->fb == NULL) {
11189 struct intel_crtc *intel_crtc =
11190 to_intel_crtc(set->crtc);
11192 if (intel_crtc->active) {
11193 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11194 config->fb_changed = true;
11196 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11197 config->mode_changed = true;
11199 } else if (set->fb == NULL) {
11200 config->mode_changed = true;
11201 } else if (set->fb->pixel_format !=
11202 set->crtc->primary->fb->pixel_format) {
11203 config->mode_changed = true;
11205 config->fb_changed = true;
11209 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11210 config->fb_changed = true;
11212 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11213 DRM_DEBUG_KMS("modes are different, full mode set\n");
11214 drm_mode_debug_printmodeline(&set->crtc->mode);
11215 drm_mode_debug_printmodeline(set->mode);
11216 config->mode_changed = true;
11219 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11220 set->crtc->base.id, config->mode_changed, config->fb_changed);
11224 intel_modeset_stage_output_state(struct drm_device *dev,
11225 struct drm_mode_set *set,
11226 struct intel_set_config *config)
11228 struct intel_connector *connector;
11229 struct intel_encoder *encoder;
11230 struct intel_crtc *crtc;
11233 /* The upper layers ensure that we either disable a crtc or have a list
11234 * of connectors. For paranoia, double-check this. */
11235 WARN_ON(!set->fb && (set->num_connectors != 0));
11236 WARN_ON(set->fb && (set->num_connectors == 0));
11238 list_for_each_entry(connector, &dev->mode_config.connector_list,
11240 /* Otherwise traverse passed in connector list and get encoders
11242 for (ro = 0; ro < set->num_connectors; ro++) {
11243 if (set->connectors[ro] == &connector->base) {
11244 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11249 /* If we disable the crtc, disable all its connectors. Also, if
11250 * the connector is on the changing crtc but not on the new
11251 * connector list, disable it. */
11252 if ((!set->fb || ro == set->num_connectors) &&
11253 connector->base.encoder &&
11254 connector->base.encoder->crtc == set->crtc) {
11255 connector->new_encoder = NULL;
11257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11258 connector->base.base.id,
11259 connector->base.name);
11263 if (&connector->new_encoder->base != connector->base.encoder) {
11264 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11265 config->mode_changed = true;
11268 /* connector->new_encoder is now updated for all connectors. */
11270 /* Update crtc of enabled connectors. */
11271 list_for_each_entry(connector, &dev->mode_config.connector_list,
11273 struct drm_crtc *new_crtc;
11275 if (!connector->new_encoder)
11278 new_crtc = connector->new_encoder->base.crtc;
11280 for (ro = 0; ro < set->num_connectors; ro++) {
11281 if (set->connectors[ro] == &connector->base)
11282 new_crtc = set->crtc;
11285 /* Make sure the new CRTC will work with the encoder */
11286 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11290 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11292 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11293 connector->base.base.id,
11294 connector->base.name,
11295 new_crtc->base.id);
11298 /* Check for any encoders that needs to be disabled. */
11299 for_each_intel_encoder(dev, encoder) {
11300 int num_connectors = 0;
11301 list_for_each_entry(connector,
11302 &dev->mode_config.connector_list,
11304 if (connector->new_encoder == encoder) {
11305 WARN_ON(!connector->new_encoder->new_crtc);
11310 if (num_connectors == 0)
11311 encoder->new_crtc = NULL;
11312 else if (num_connectors > 1)
11315 /* Only now check for crtc changes so we don't miss encoders
11316 * that will be disabled. */
11317 if (&encoder->new_crtc->base != encoder->base.crtc) {
11318 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11319 config->mode_changed = true;
11322 /* Now we've also updated encoder->new_crtc for all encoders. */
11323 list_for_each_entry(connector, &dev->mode_config.connector_list,
11325 if (connector->new_encoder)
11326 if (connector->new_encoder != connector->encoder)
11327 connector->encoder = connector->new_encoder;
11329 for_each_intel_crtc(dev, crtc) {
11330 crtc->new_enabled = false;
11332 for_each_intel_encoder(dev, encoder) {
11333 if (encoder->new_crtc == crtc) {
11334 crtc->new_enabled = true;
11339 if (crtc->new_enabled != crtc->base.enabled) {
11340 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11341 crtc->new_enabled ? "en" : "dis");
11342 config->mode_changed = true;
11345 if (crtc->new_enabled)
11346 crtc->new_config = &crtc->config;
11348 crtc->new_config = NULL;
11354 static void disable_crtc_nofb(struct intel_crtc *crtc)
11356 struct drm_device *dev = crtc->base.dev;
11357 struct intel_encoder *encoder;
11358 struct intel_connector *connector;
11360 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11361 pipe_name(crtc->pipe));
11363 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11364 if (connector->new_encoder &&
11365 connector->new_encoder->new_crtc == crtc)
11366 connector->new_encoder = NULL;
11369 for_each_intel_encoder(dev, encoder) {
11370 if (encoder->new_crtc == crtc)
11371 encoder->new_crtc = NULL;
11374 crtc->new_enabled = false;
11375 crtc->new_config = NULL;
11378 static int intel_crtc_set_config(struct drm_mode_set *set)
11380 struct drm_device *dev;
11381 struct drm_mode_set save_set;
11382 struct intel_set_config *config;
11386 BUG_ON(!set->crtc);
11387 BUG_ON(!set->crtc->helper_private);
11389 /* Enforce sane interface api - has been abused by the fb helper. */
11390 BUG_ON(!set->mode && set->fb);
11391 BUG_ON(set->fb && set->num_connectors == 0);
11394 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11395 set->crtc->base.id, set->fb->base.id,
11396 (int)set->num_connectors, set->x, set->y);
11398 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11401 dev = set->crtc->dev;
11404 config = kzalloc(sizeof(*config), GFP_KERNEL);
11408 ret = intel_set_config_save_state(dev, config);
11412 save_set.crtc = set->crtc;
11413 save_set.mode = &set->crtc->mode;
11414 save_set.x = set->crtc->x;
11415 save_set.y = set->crtc->y;
11416 save_set.fb = set->crtc->primary->fb;
11418 /* Compute whether we need a full modeset, only an fb base update or no
11419 * change at all. In the future we might also check whether only the
11420 * mode changed, e.g. for LVDS where we only change the panel fitter in
11422 intel_set_config_compute_mode_changes(set, config);
11424 ret = intel_modeset_stage_output_state(dev, set, config);
11428 if (config->mode_changed) {
11429 ret = intel_set_mode(set->crtc, set->mode,
11430 set->x, set->y, set->fb);
11431 } else if (config->fb_changed) {
11432 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11434 intel_crtc_wait_for_pending_flips(set->crtc);
11436 ret = intel_pipe_set_base(set->crtc,
11437 set->x, set->y, set->fb);
11440 * We need to make sure the primary plane is re-enabled if it
11441 * has previously been turned off.
11443 if (!intel_crtc->primary_enabled && ret == 0) {
11444 WARN_ON(!intel_crtc->active);
11445 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11449 * In the fastboot case this may be our only check of the
11450 * state after boot. It would be better to only do it on
11451 * the first update, but we don't have a nice way of doing that
11452 * (and really, set_config isn't used much for high freq page
11453 * flipping, so increasing its cost here shouldn't be a big
11456 if (i915.fastboot && ret == 0)
11457 intel_modeset_check_state(set->crtc->dev);
11461 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11462 set->crtc->base.id, ret);
11464 intel_set_config_restore_state(dev, config);
11467 * HACK: if the pipe was on, but we didn't have a framebuffer,
11468 * force the pipe off to avoid oopsing in the modeset code
11469 * due to fb==NULL. This should only happen during boot since
11470 * we don't yet reconstruct the FB from the hardware state.
11472 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11473 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11475 /* Try to restore the config */
11476 if (config->mode_changed &&
11477 intel_set_mode(save_set.crtc, save_set.mode,
11478 save_set.x, save_set.y, save_set.fb))
11479 DRM_ERROR("failed to restore config after modeset failure\n");
11483 intel_set_config_free(config);
11487 static const struct drm_crtc_funcs intel_crtc_funcs = {
11488 .gamma_set = intel_crtc_gamma_set,
11489 .set_config = intel_crtc_set_config,
11490 .destroy = intel_crtc_destroy,
11491 .page_flip = intel_crtc_page_flip,
11494 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11495 struct intel_shared_dpll *pll,
11496 struct intel_dpll_hw_state *hw_state)
11500 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11503 val = I915_READ(PCH_DPLL(pll->id));
11504 hw_state->dpll = val;
11505 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11506 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11508 return val & DPLL_VCO_ENABLE;
11511 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11512 struct intel_shared_dpll *pll)
11514 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11515 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11518 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11519 struct intel_shared_dpll *pll)
11521 /* PCH refclock must be enabled first */
11522 ibx_assert_pch_refclk_enabled(dev_priv);
11524 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11526 /* Wait for the clocks to stabilize. */
11527 POSTING_READ(PCH_DPLL(pll->id));
11530 /* The pixel multiplier can only be updated once the
11531 * DPLL is enabled and the clocks are stable.
11533 * So write it again.
11535 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11536 POSTING_READ(PCH_DPLL(pll->id));
11540 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11541 struct intel_shared_dpll *pll)
11543 struct drm_device *dev = dev_priv->dev;
11544 struct intel_crtc *crtc;
11546 /* Make sure no transcoder isn't still depending on us. */
11547 for_each_intel_crtc(dev, crtc) {
11548 if (intel_crtc_to_shared_dpll(crtc) == pll)
11549 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11552 I915_WRITE(PCH_DPLL(pll->id), 0);
11553 POSTING_READ(PCH_DPLL(pll->id));
11557 static char *ibx_pch_dpll_names[] = {
11562 static void ibx_pch_dpll_init(struct drm_device *dev)
11564 struct drm_i915_private *dev_priv = dev->dev_private;
11567 dev_priv->num_shared_dpll = 2;
11569 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11570 dev_priv->shared_dplls[i].id = i;
11571 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11572 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11573 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11574 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11575 dev_priv->shared_dplls[i].get_hw_state =
11576 ibx_pch_dpll_get_hw_state;
11580 static void intel_shared_dpll_init(struct drm_device *dev)
11582 struct drm_i915_private *dev_priv = dev->dev_private;
11585 intel_ddi_pll_init(dev);
11586 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11587 ibx_pch_dpll_init(dev);
11589 dev_priv->num_shared_dpll = 0;
11591 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11595 intel_primary_plane_disable(struct drm_plane *plane)
11597 struct drm_device *dev = plane->dev;
11598 struct intel_crtc *intel_crtc;
11603 BUG_ON(!plane->crtc);
11605 intel_crtc = to_intel_crtc(plane->crtc);
11608 * Even though we checked plane->fb above, it's still possible that
11609 * the primary plane has been implicitly disabled because the crtc
11610 * coordinates given weren't visible, or because we detected
11611 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11612 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11613 * In either case, we need to unpin the FB and let the fb pointer get
11614 * updated, but otherwise we don't need to touch the hardware.
11616 if (!intel_crtc->primary_enabled)
11617 goto disable_unpin;
11619 intel_crtc_wait_for_pending_flips(plane->crtc);
11620 intel_disable_primary_hw_plane(plane, plane->crtc);
11623 mutex_lock(&dev->struct_mutex);
11624 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11625 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11626 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11627 mutex_unlock(&dev->struct_mutex);
11634 intel_check_primary_plane(struct drm_plane *plane,
11635 struct intel_plane_state *state)
11637 struct drm_crtc *crtc = state->crtc;
11638 struct drm_framebuffer *fb = state->fb;
11639 struct drm_rect *dest = &state->dst;
11640 struct drm_rect *src = &state->src;
11641 const struct drm_rect *clip = &state->clip;
11643 return drm_plane_helper_check_update(plane, crtc, fb,
11645 DRM_PLANE_HELPER_NO_SCALING,
11646 DRM_PLANE_HELPER_NO_SCALING,
11647 false, true, &state->visible);
11651 intel_commit_primary_plane(struct drm_plane *plane,
11652 struct intel_plane_state *state)
11654 struct drm_crtc *crtc = state->crtc;
11655 struct drm_framebuffer *fb = state->fb;
11656 struct drm_device *dev = crtc->dev;
11657 struct drm_i915_private *dev_priv = dev->dev_private;
11658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11659 enum pipe pipe = intel_crtc->pipe;
11660 struct drm_framebuffer *old_fb = plane->fb;
11661 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11662 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11663 struct intel_plane *intel_plane = to_intel_plane(plane);
11664 struct drm_rect *src = &state->src;
11667 intel_crtc_wait_for_pending_flips(crtc);
11669 if (intel_crtc_has_pending_flip(crtc)) {
11670 DRM_ERROR("pipe is still busy with an old pageflip\n");
11674 if (plane->fb != fb) {
11675 mutex_lock(&dev->struct_mutex);
11676 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11678 i915_gem_track_fb(old_obj, obj,
11679 INTEL_FRONTBUFFER_PRIMARY(pipe));
11680 mutex_unlock(&dev->struct_mutex);
11682 DRM_DEBUG_KMS("pin & fence failed\n");
11687 crtc->primary->fb = fb;
11691 intel_plane->crtc_x = state->orig_dst.x1;
11692 intel_plane->crtc_y = state->orig_dst.y1;
11693 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11694 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11695 intel_plane->src_x = state->orig_src.x1;
11696 intel_plane->src_y = state->orig_src.y1;
11697 intel_plane->src_w = drm_rect_width(&state->orig_src);
11698 intel_plane->src_h = drm_rect_height(&state->orig_src);
11699 intel_plane->obj = obj;
11701 if (intel_crtc->active) {
11703 * FBC does not work on some platforms for rotated
11704 * planes, so disable it when rotation is not 0 and
11705 * update it when rotation is set back to 0.
11707 * FIXME: This is redundant with the fbc update done in
11708 * the primary plane enable function except that that
11709 * one is done too late. We eventually need to unify
11712 if (intel_crtc->primary_enabled &&
11713 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11714 dev_priv->fbc.plane == intel_crtc->plane &&
11715 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11716 intel_disable_fbc(dev);
11719 if (state->visible) {
11720 bool was_enabled = intel_crtc->primary_enabled;
11722 /* FIXME: kill this fastboot hack */
11723 intel_update_pipe_size(intel_crtc);
11725 intel_crtc->primary_enabled = true;
11727 dev_priv->display.update_primary_plane(crtc, plane->fb,
11731 * BDW signals flip done immediately if the plane
11732 * is disabled, even if the plane enable is already
11733 * armed to occur at the next vblank :(
11735 if (IS_BROADWELL(dev) && !was_enabled)
11736 intel_wait_for_vblank(dev, intel_crtc->pipe);
11739 * If clipping results in a non-visible primary plane,
11740 * we'll disable the primary plane. Note that this is
11741 * a bit different than what happens if userspace
11742 * explicitly disables the plane by passing fb=0
11743 * because plane->fb still gets set and pinned.
11745 intel_disable_primary_hw_plane(plane, crtc);
11748 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11750 mutex_lock(&dev->struct_mutex);
11751 intel_update_fbc(dev);
11752 mutex_unlock(&dev->struct_mutex);
11755 if (old_fb && old_fb != fb) {
11756 if (intel_crtc->active)
11757 intel_wait_for_vblank(dev, intel_crtc->pipe);
11759 mutex_lock(&dev->struct_mutex);
11760 intel_unpin_fb_obj(old_obj);
11761 mutex_unlock(&dev->struct_mutex);
11768 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11769 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11770 unsigned int crtc_w, unsigned int crtc_h,
11771 uint32_t src_x, uint32_t src_y,
11772 uint32_t src_w, uint32_t src_h)
11774 struct intel_plane_state state;
11775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11781 /* sample coordinates in 16.16 fixed point */
11782 state.src.x1 = src_x;
11783 state.src.x2 = src_x + src_w;
11784 state.src.y1 = src_y;
11785 state.src.y2 = src_y + src_h;
11787 /* integer pixels */
11788 state.dst.x1 = crtc_x;
11789 state.dst.x2 = crtc_x + crtc_w;
11790 state.dst.y1 = crtc_y;
11791 state.dst.y2 = crtc_y + crtc_h;
11795 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11796 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11798 state.orig_src = state.src;
11799 state.orig_dst = state.dst;
11801 ret = intel_check_primary_plane(plane, &state);
11805 intel_commit_primary_plane(plane, &state);
11810 /* Common destruction function for both primary and cursor planes */
11811 static void intel_plane_destroy(struct drm_plane *plane)
11813 struct intel_plane *intel_plane = to_intel_plane(plane);
11814 drm_plane_cleanup(plane);
11815 kfree(intel_plane);
11818 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11819 .update_plane = intel_primary_plane_setplane,
11820 .disable_plane = intel_primary_plane_disable,
11821 .destroy = intel_plane_destroy,
11822 .set_property = intel_plane_set_property
11825 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11828 struct intel_plane *primary;
11829 const uint32_t *intel_primary_formats;
11832 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11833 if (primary == NULL)
11836 primary->can_scale = false;
11837 primary->max_downscale = 1;
11838 primary->pipe = pipe;
11839 primary->plane = pipe;
11840 primary->rotation = BIT(DRM_ROTATE_0);
11841 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11842 primary->plane = !pipe;
11844 if (INTEL_INFO(dev)->gen <= 3) {
11845 intel_primary_formats = intel_primary_formats_gen2;
11846 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11848 intel_primary_formats = intel_primary_formats_gen4;
11849 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11852 drm_universal_plane_init(dev, &primary->base, 0,
11853 &intel_primary_plane_funcs,
11854 intel_primary_formats, num_formats,
11855 DRM_PLANE_TYPE_PRIMARY);
11857 if (INTEL_INFO(dev)->gen >= 4) {
11858 if (!dev->mode_config.rotation_property)
11859 dev->mode_config.rotation_property =
11860 drm_mode_create_rotation_property(dev,
11861 BIT(DRM_ROTATE_0) |
11862 BIT(DRM_ROTATE_180));
11863 if (dev->mode_config.rotation_property)
11864 drm_object_attach_property(&primary->base.base,
11865 dev->mode_config.rotation_property,
11866 primary->rotation);
11869 return &primary->base;
11873 intel_cursor_plane_disable(struct drm_plane *plane)
11878 BUG_ON(!plane->crtc);
11880 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11884 intel_check_cursor_plane(struct drm_plane *plane,
11885 struct intel_plane_state *state)
11887 struct drm_crtc *crtc = state->crtc;
11888 struct drm_device *dev = crtc->dev;
11889 struct drm_framebuffer *fb = state->fb;
11890 struct drm_rect *dest = &state->dst;
11891 struct drm_rect *src = &state->src;
11892 const struct drm_rect *clip = &state->clip;
11893 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11894 int crtc_w, crtc_h;
11898 ret = drm_plane_helper_check_update(plane, crtc, fb,
11900 DRM_PLANE_HELPER_NO_SCALING,
11901 DRM_PLANE_HELPER_NO_SCALING,
11902 true, true, &state->visible);
11907 /* if we want to turn off the cursor ignore width and height */
11911 /* Check for which cursor types we support */
11912 crtc_w = drm_rect_width(&state->orig_dst);
11913 crtc_h = drm_rect_height(&state->orig_dst);
11914 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11915 DRM_DEBUG("Cursor dimension not supported\n");
11919 stride = roundup_pow_of_two(crtc_w) * 4;
11920 if (obj->base.size < stride * crtc_h) {
11921 DRM_DEBUG_KMS("buffer is too small\n");
11925 if (fb == crtc->cursor->fb)
11928 /* we only need to pin inside GTT if cursor is non-phy */
11929 mutex_lock(&dev->struct_mutex);
11930 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11931 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11934 mutex_unlock(&dev->struct_mutex);
11940 intel_commit_cursor_plane(struct drm_plane *plane,
11941 struct intel_plane_state *state)
11943 struct drm_crtc *crtc = state->crtc;
11944 struct drm_framebuffer *fb = state->fb;
11945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11946 struct intel_plane *intel_plane = to_intel_plane(plane);
11947 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11948 struct drm_i915_gem_object *obj = intel_fb->obj;
11949 int crtc_w, crtc_h;
11951 crtc->cursor_x = state->orig_dst.x1;
11952 crtc->cursor_y = state->orig_dst.y1;
11954 intel_plane->crtc_x = state->orig_dst.x1;
11955 intel_plane->crtc_y = state->orig_dst.y1;
11956 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11957 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11958 intel_plane->src_x = state->orig_src.x1;
11959 intel_plane->src_y = state->orig_src.y1;
11960 intel_plane->src_w = drm_rect_width(&state->orig_src);
11961 intel_plane->src_h = drm_rect_height(&state->orig_src);
11962 intel_plane->obj = obj;
11964 if (fb != crtc->cursor->fb) {
11965 crtc_w = drm_rect_width(&state->orig_dst);
11966 crtc_h = drm_rect_height(&state->orig_dst);
11967 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11969 intel_crtc_update_cursor(crtc, state->visible);
11971 intel_frontbuffer_flip(crtc->dev,
11972 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11979 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11980 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11981 unsigned int crtc_w, unsigned int crtc_h,
11982 uint32_t src_x, uint32_t src_y,
11983 uint32_t src_w, uint32_t src_h)
11985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11986 struct intel_plane_state state;
11992 /* sample coordinates in 16.16 fixed point */
11993 state.src.x1 = src_x;
11994 state.src.x2 = src_x + src_w;
11995 state.src.y1 = src_y;
11996 state.src.y2 = src_y + src_h;
11998 /* integer pixels */
11999 state.dst.x1 = crtc_x;
12000 state.dst.x2 = crtc_x + crtc_w;
12001 state.dst.y1 = crtc_y;
12002 state.dst.y2 = crtc_y + crtc_h;
12006 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12007 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12009 state.orig_src = state.src;
12010 state.orig_dst = state.dst;
12012 ret = intel_check_cursor_plane(plane, &state);
12016 return intel_commit_cursor_plane(plane, &state);
12019 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12020 .update_plane = intel_cursor_plane_update,
12021 .disable_plane = intel_cursor_plane_disable,
12022 .destroy = intel_plane_destroy,
12023 .set_property = intel_plane_set_property,
12026 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12029 struct intel_plane *cursor;
12031 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12032 if (cursor == NULL)
12035 cursor->can_scale = false;
12036 cursor->max_downscale = 1;
12037 cursor->pipe = pipe;
12038 cursor->plane = pipe;
12039 cursor->rotation = BIT(DRM_ROTATE_0);
12041 drm_universal_plane_init(dev, &cursor->base, 0,
12042 &intel_cursor_plane_funcs,
12043 intel_cursor_formats,
12044 ARRAY_SIZE(intel_cursor_formats),
12045 DRM_PLANE_TYPE_CURSOR);
12047 if (INTEL_INFO(dev)->gen >= 4) {
12048 if (!dev->mode_config.rotation_property)
12049 dev->mode_config.rotation_property =
12050 drm_mode_create_rotation_property(dev,
12051 BIT(DRM_ROTATE_0) |
12052 BIT(DRM_ROTATE_180));
12053 if (dev->mode_config.rotation_property)
12054 drm_object_attach_property(&cursor->base.base,
12055 dev->mode_config.rotation_property,
12059 return &cursor->base;
12062 static void intel_crtc_init(struct drm_device *dev, int pipe)
12064 struct drm_i915_private *dev_priv = dev->dev_private;
12065 struct intel_crtc *intel_crtc;
12066 struct drm_plane *primary = NULL;
12067 struct drm_plane *cursor = NULL;
12070 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12071 if (intel_crtc == NULL)
12074 primary = intel_primary_plane_create(dev, pipe);
12078 cursor = intel_cursor_plane_create(dev, pipe);
12082 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12083 cursor, &intel_crtc_funcs);
12087 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12088 for (i = 0; i < 256; i++) {
12089 intel_crtc->lut_r[i] = i;
12090 intel_crtc->lut_g[i] = i;
12091 intel_crtc->lut_b[i] = i;
12095 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12096 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12098 intel_crtc->pipe = pipe;
12099 intel_crtc->plane = pipe;
12100 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12101 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12102 intel_crtc->plane = !pipe;
12105 intel_crtc->cursor_base = ~0;
12106 intel_crtc->cursor_cntl = ~0;
12107 intel_crtc->cursor_size = ~0;
12109 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12110 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12111 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12112 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12114 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12116 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12121 drm_plane_cleanup(primary);
12123 drm_plane_cleanup(cursor);
12127 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12129 struct drm_encoder *encoder = connector->base.encoder;
12130 struct drm_device *dev = connector->base.dev;
12132 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12135 return INVALID_PIPE;
12137 return to_intel_crtc(encoder->crtc)->pipe;
12140 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12141 struct drm_file *file)
12143 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12144 struct drm_crtc *drmmode_crtc;
12145 struct intel_crtc *crtc;
12147 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12150 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12152 if (!drmmode_crtc) {
12153 DRM_ERROR("no such CRTC id\n");
12157 crtc = to_intel_crtc(drmmode_crtc);
12158 pipe_from_crtc_id->pipe = crtc->pipe;
12163 static int intel_encoder_clones(struct intel_encoder *encoder)
12165 struct drm_device *dev = encoder->base.dev;
12166 struct intel_encoder *source_encoder;
12167 int index_mask = 0;
12170 for_each_intel_encoder(dev, source_encoder) {
12171 if (encoders_cloneable(encoder, source_encoder))
12172 index_mask |= (1 << entry);
12180 static bool has_edp_a(struct drm_device *dev)
12182 struct drm_i915_private *dev_priv = dev->dev_private;
12184 if (!IS_MOBILE(dev))
12187 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12190 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12196 const char *intel_output_name(int output)
12198 static const char *names[] = {
12199 [INTEL_OUTPUT_UNUSED] = "Unused",
12200 [INTEL_OUTPUT_ANALOG] = "Analog",
12201 [INTEL_OUTPUT_DVO] = "DVO",
12202 [INTEL_OUTPUT_SDVO] = "SDVO",
12203 [INTEL_OUTPUT_LVDS] = "LVDS",
12204 [INTEL_OUTPUT_TVOUT] = "TV",
12205 [INTEL_OUTPUT_HDMI] = "HDMI",
12206 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12207 [INTEL_OUTPUT_EDP] = "eDP",
12208 [INTEL_OUTPUT_DSI] = "DSI",
12209 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12212 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12215 return names[output];
12218 static bool intel_crt_present(struct drm_device *dev)
12220 struct drm_i915_private *dev_priv = dev->dev_private;
12222 if (INTEL_INFO(dev)->gen >= 9)
12225 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12228 if (IS_CHERRYVIEW(dev))
12231 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12237 static void intel_setup_outputs(struct drm_device *dev)
12239 struct drm_i915_private *dev_priv = dev->dev_private;
12240 struct intel_encoder *encoder;
12241 bool dpd_is_edp = false;
12243 intel_lvds_init(dev);
12245 if (intel_crt_present(dev))
12246 intel_crt_init(dev);
12248 if (HAS_DDI(dev)) {
12251 /* Haswell uses DDI functions to detect digital outputs */
12252 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12253 /* DDI A only supports eDP */
12255 intel_ddi_init(dev, PORT_A);
12257 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12259 found = I915_READ(SFUSE_STRAP);
12261 if (found & SFUSE_STRAP_DDIB_DETECTED)
12262 intel_ddi_init(dev, PORT_B);
12263 if (found & SFUSE_STRAP_DDIC_DETECTED)
12264 intel_ddi_init(dev, PORT_C);
12265 if (found & SFUSE_STRAP_DDID_DETECTED)
12266 intel_ddi_init(dev, PORT_D);
12267 } else if (HAS_PCH_SPLIT(dev)) {
12269 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12271 if (has_edp_a(dev))
12272 intel_dp_init(dev, DP_A, PORT_A);
12274 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12275 /* PCH SDVOB multiplex with HDMIB */
12276 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12278 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12279 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12280 intel_dp_init(dev, PCH_DP_B, PORT_B);
12283 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12284 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12286 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12287 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12289 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12290 intel_dp_init(dev, PCH_DP_C, PORT_C);
12292 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12293 intel_dp_init(dev, PCH_DP_D, PORT_D);
12294 } else if (IS_VALLEYVIEW(dev)) {
12296 * The DP_DETECTED bit is the latched state of the DDC
12297 * SDA pin at boot. However since eDP doesn't require DDC
12298 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12299 * eDP ports may have been muxed to an alternate function.
12300 * Thus we can't rely on the DP_DETECTED bit alone to detect
12301 * eDP ports. Consult the VBT as well as DP_DETECTED to
12302 * detect eDP ports.
12304 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12305 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12307 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12308 intel_dp_is_edp(dev, PORT_B))
12309 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12311 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12312 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12314 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12315 intel_dp_is_edp(dev, PORT_C))
12316 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12318 if (IS_CHERRYVIEW(dev)) {
12319 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12320 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12322 /* eDP not supported on port D, so don't check VBT */
12323 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12324 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12327 intel_dsi_init(dev);
12328 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12329 bool found = false;
12331 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12332 DRM_DEBUG_KMS("probing SDVOB\n");
12333 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12334 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12335 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12336 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12339 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12340 intel_dp_init(dev, DP_B, PORT_B);
12343 /* Before G4X SDVOC doesn't have its own detect register */
12345 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12346 DRM_DEBUG_KMS("probing SDVOC\n");
12347 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12350 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12352 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12353 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12354 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12356 if (SUPPORTS_INTEGRATED_DP(dev))
12357 intel_dp_init(dev, DP_C, PORT_C);
12360 if (SUPPORTS_INTEGRATED_DP(dev) &&
12361 (I915_READ(DP_D) & DP_DETECTED))
12362 intel_dp_init(dev, DP_D, PORT_D);
12363 } else if (IS_GEN2(dev))
12364 intel_dvo_init(dev);
12366 if (SUPPORTS_TV(dev))
12367 intel_tv_init(dev);
12369 intel_edp_psr_init(dev);
12371 for_each_intel_encoder(dev, encoder) {
12372 encoder->base.possible_crtcs = encoder->crtc_mask;
12373 encoder->base.possible_clones =
12374 intel_encoder_clones(encoder);
12377 intel_init_pch_refclk(dev);
12379 drm_helper_move_panel_connectors_to_head(dev);
12382 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12384 struct drm_device *dev = fb->dev;
12385 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12387 drm_framebuffer_cleanup(fb);
12388 mutex_lock(&dev->struct_mutex);
12389 WARN_ON(!intel_fb->obj->framebuffer_references--);
12390 drm_gem_object_unreference(&intel_fb->obj->base);
12391 mutex_unlock(&dev->struct_mutex);
12395 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12396 struct drm_file *file,
12397 unsigned int *handle)
12399 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12400 struct drm_i915_gem_object *obj = intel_fb->obj;
12402 return drm_gem_handle_create(file, &obj->base, handle);
12405 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12406 .destroy = intel_user_framebuffer_destroy,
12407 .create_handle = intel_user_framebuffer_create_handle,
12410 static int intel_framebuffer_init(struct drm_device *dev,
12411 struct intel_framebuffer *intel_fb,
12412 struct drm_mode_fb_cmd2 *mode_cmd,
12413 struct drm_i915_gem_object *obj)
12415 int aligned_height;
12419 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12421 if (obj->tiling_mode == I915_TILING_Y) {
12422 DRM_DEBUG("hardware does not support tiling Y\n");
12426 if (mode_cmd->pitches[0] & 63) {
12427 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12428 mode_cmd->pitches[0]);
12432 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12433 pitch_limit = 32*1024;
12434 } else if (INTEL_INFO(dev)->gen >= 4) {
12435 if (obj->tiling_mode)
12436 pitch_limit = 16*1024;
12438 pitch_limit = 32*1024;
12439 } else if (INTEL_INFO(dev)->gen >= 3) {
12440 if (obj->tiling_mode)
12441 pitch_limit = 8*1024;
12443 pitch_limit = 16*1024;
12445 /* XXX DSPC is limited to 4k tiled */
12446 pitch_limit = 8*1024;
12448 if (mode_cmd->pitches[0] > pitch_limit) {
12449 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12450 obj->tiling_mode ? "tiled" : "linear",
12451 mode_cmd->pitches[0], pitch_limit);
12455 if (obj->tiling_mode != I915_TILING_NONE &&
12456 mode_cmd->pitches[0] != obj->stride) {
12457 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12458 mode_cmd->pitches[0], obj->stride);
12462 /* Reject formats not supported by any plane early. */
12463 switch (mode_cmd->pixel_format) {
12464 case DRM_FORMAT_C8:
12465 case DRM_FORMAT_RGB565:
12466 case DRM_FORMAT_XRGB8888:
12467 case DRM_FORMAT_ARGB8888:
12469 case DRM_FORMAT_XRGB1555:
12470 case DRM_FORMAT_ARGB1555:
12471 if (INTEL_INFO(dev)->gen > 3) {
12472 DRM_DEBUG("unsupported pixel format: %s\n",
12473 drm_get_format_name(mode_cmd->pixel_format));
12477 case DRM_FORMAT_XBGR8888:
12478 case DRM_FORMAT_ABGR8888:
12479 case DRM_FORMAT_XRGB2101010:
12480 case DRM_FORMAT_ARGB2101010:
12481 case DRM_FORMAT_XBGR2101010:
12482 case DRM_FORMAT_ABGR2101010:
12483 if (INTEL_INFO(dev)->gen < 4) {
12484 DRM_DEBUG("unsupported pixel format: %s\n",
12485 drm_get_format_name(mode_cmd->pixel_format));
12489 case DRM_FORMAT_YUYV:
12490 case DRM_FORMAT_UYVY:
12491 case DRM_FORMAT_YVYU:
12492 case DRM_FORMAT_VYUY:
12493 if (INTEL_INFO(dev)->gen < 5) {
12494 DRM_DEBUG("unsupported pixel format: %s\n",
12495 drm_get_format_name(mode_cmd->pixel_format));
12500 DRM_DEBUG("unsupported pixel format: %s\n",
12501 drm_get_format_name(mode_cmd->pixel_format));
12505 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12506 if (mode_cmd->offsets[0] != 0)
12509 aligned_height = intel_align_height(dev, mode_cmd->height,
12511 /* FIXME drm helper for size checks (especially planar formats)? */
12512 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12515 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12516 intel_fb->obj = obj;
12517 intel_fb->obj->framebuffer_references++;
12519 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12521 DRM_ERROR("framebuffer init failed %d\n", ret);
12528 static struct drm_framebuffer *
12529 intel_user_framebuffer_create(struct drm_device *dev,
12530 struct drm_file *filp,
12531 struct drm_mode_fb_cmd2 *mode_cmd)
12533 struct drm_i915_gem_object *obj;
12535 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12536 mode_cmd->handles[0]));
12537 if (&obj->base == NULL)
12538 return ERR_PTR(-ENOENT);
12540 return intel_framebuffer_create(dev, mode_cmd, obj);
12543 #ifndef CONFIG_DRM_I915_FBDEV
12544 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12549 static const struct drm_mode_config_funcs intel_mode_funcs = {
12550 .fb_create = intel_user_framebuffer_create,
12551 .output_poll_changed = intel_fbdev_output_poll_changed,
12554 /* Set up chip specific display functions */
12555 static void intel_init_display(struct drm_device *dev)
12557 struct drm_i915_private *dev_priv = dev->dev_private;
12559 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12560 dev_priv->display.find_dpll = g4x_find_best_dpll;
12561 else if (IS_CHERRYVIEW(dev))
12562 dev_priv->display.find_dpll = chv_find_best_dpll;
12563 else if (IS_VALLEYVIEW(dev))
12564 dev_priv->display.find_dpll = vlv_find_best_dpll;
12565 else if (IS_PINEVIEW(dev))
12566 dev_priv->display.find_dpll = pnv_find_best_dpll;
12568 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12570 if (HAS_DDI(dev)) {
12571 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12572 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12573 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12574 dev_priv->display.crtc_enable = haswell_crtc_enable;
12575 dev_priv->display.crtc_disable = haswell_crtc_disable;
12576 dev_priv->display.off = ironlake_crtc_off;
12577 if (INTEL_INFO(dev)->gen >= 9)
12578 dev_priv->display.update_primary_plane =
12579 skylake_update_primary_plane;
12581 dev_priv->display.update_primary_plane =
12582 ironlake_update_primary_plane;
12583 } else if (HAS_PCH_SPLIT(dev)) {
12584 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12585 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12586 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12587 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12588 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12589 dev_priv->display.off = ironlake_crtc_off;
12590 dev_priv->display.update_primary_plane =
12591 ironlake_update_primary_plane;
12592 } else if (IS_VALLEYVIEW(dev)) {
12593 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12594 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12595 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12596 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12597 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12598 dev_priv->display.off = i9xx_crtc_off;
12599 dev_priv->display.update_primary_plane =
12600 i9xx_update_primary_plane;
12602 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12603 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12604 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12605 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12606 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12607 dev_priv->display.off = i9xx_crtc_off;
12608 dev_priv->display.update_primary_plane =
12609 i9xx_update_primary_plane;
12612 /* Returns the core display clock speed */
12613 if (IS_VALLEYVIEW(dev))
12614 dev_priv->display.get_display_clock_speed =
12615 valleyview_get_display_clock_speed;
12616 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12617 dev_priv->display.get_display_clock_speed =
12618 i945_get_display_clock_speed;
12619 else if (IS_I915G(dev))
12620 dev_priv->display.get_display_clock_speed =
12621 i915_get_display_clock_speed;
12622 else if (IS_I945GM(dev) || IS_845G(dev))
12623 dev_priv->display.get_display_clock_speed =
12624 i9xx_misc_get_display_clock_speed;
12625 else if (IS_PINEVIEW(dev))
12626 dev_priv->display.get_display_clock_speed =
12627 pnv_get_display_clock_speed;
12628 else if (IS_I915GM(dev))
12629 dev_priv->display.get_display_clock_speed =
12630 i915gm_get_display_clock_speed;
12631 else if (IS_I865G(dev))
12632 dev_priv->display.get_display_clock_speed =
12633 i865_get_display_clock_speed;
12634 else if (IS_I85X(dev))
12635 dev_priv->display.get_display_clock_speed =
12636 i855_get_display_clock_speed;
12637 else /* 852, 830 */
12638 dev_priv->display.get_display_clock_speed =
12639 i830_get_display_clock_speed;
12642 dev_priv->display.write_eld = g4x_write_eld;
12643 } else if (IS_GEN5(dev)) {
12644 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12645 dev_priv->display.write_eld = ironlake_write_eld;
12646 } else if (IS_GEN6(dev)) {
12647 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12648 dev_priv->display.write_eld = ironlake_write_eld;
12649 dev_priv->display.modeset_global_resources =
12650 snb_modeset_global_resources;
12651 } else if (IS_IVYBRIDGE(dev)) {
12652 /* FIXME: detect B0+ stepping and use auto training */
12653 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12654 dev_priv->display.write_eld = ironlake_write_eld;
12655 dev_priv->display.modeset_global_resources =
12656 ivb_modeset_global_resources;
12657 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12658 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12659 dev_priv->display.write_eld = haswell_write_eld;
12660 dev_priv->display.modeset_global_resources =
12661 haswell_modeset_global_resources;
12662 } else if (IS_VALLEYVIEW(dev)) {
12663 dev_priv->display.modeset_global_resources =
12664 valleyview_modeset_global_resources;
12665 dev_priv->display.write_eld = ironlake_write_eld;
12666 } else if (INTEL_INFO(dev)->gen >= 9) {
12667 dev_priv->display.write_eld = haswell_write_eld;
12668 dev_priv->display.modeset_global_resources =
12669 haswell_modeset_global_resources;
12672 /* Default just returns -ENODEV to indicate unsupported */
12673 dev_priv->display.queue_flip = intel_default_queue_flip;
12675 switch (INTEL_INFO(dev)->gen) {
12677 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12681 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12686 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12690 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12693 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12694 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12698 intel_panel_init_backlight_funcs(dev);
12700 mutex_init(&dev_priv->pps_mutex);
12704 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12705 * resume, or other times. This quirk makes sure that's the case for
12706 * affected systems.
12708 static void quirk_pipea_force(struct drm_device *dev)
12710 struct drm_i915_private *dev_priv = dev->dev_private;
12712 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12713 DRM_INFO("applying pipe a force quirk\n");
12716 static void quirk_pipeb_force(struct drm_device *dev)
12718 struct drm_i915_private *dev_priv = dev->dev_private;
12720 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12721 DRM_INFO("applying pipe b force quirk\n");
12725 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12727 static void quirk_ssc_force_disable(struct drm_device *dev)
12729 struct drm_i915_private *dev_priv = dev->dev_private;
12730 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12731 DRM_INFO("applying lvds SSC disable quirk\n");
12735 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12738 static void quirk_invert_brightness(struct drm_device *dev)
12740 struct drm_i915_private *dev_priv = dev->dev_private;
12741 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12742 DRM_INFO("applying inverted panel brightness quirk\n");
12745 /* Some VBT's incorrectly indicate no backlight is present */
12746 static void quirk_backlight_present(struct drm_device *dev)
12748 struct drm_i915_private *dev_priv = dev->dev_private;
12749 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12750 DRM_INFO("applying backlight present quirk\n");
12753 struct intel_quirk {
12755 int subsystem_vendor;
12756 int subsystem_device;
12757 void (*hook)(struct drm_device *dev);
12760 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12761 struct intel_dmi_quirk {
12762 void (*hook)(struct drm_device *dev);
12763 const struct dmi_system_id (*dmi_id_list)[];
12766 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12768 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12772 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12774 .dmi_id_list = &(const struct dmi_system_id[]) {
12776 .callback = intel_dmi_reverse_brightness,
12777 .ident = "NCR Corporation",
12778 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12779 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12782 { } /* terminating entry */
12784 .hook = quirk_invert_brightness,
12788 static struct intel_quirk intel_quirks[] = {
12789 /* HP Mini needs pipe A force quirk (LP: #322104) */
12790 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12792 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12793 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12795 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12796 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12798 /* 830 needs to leave pipe A & dpll A up */
12799 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12801 /* 830 needs to leave pipe B & dpll B up */
12802 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12804 /* Lenovo U160 cannot use SSC on LVDS */
12805 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12807 /* Sony Vaio Y cannot use SSC on LVDS */
12808 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12810 /* Acer Aspire 5734Z must invert backlight brightness */
12811 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12813 /* Acer/eMachines G725 */
12814 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12816 /* Acer/eMachines e725 */
12817 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12819 /* Acer/Packard Bell NCL20 */
12820 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12822 /* Acer Aspire 4736Z */
12823 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12825 /* Acer Aspire 5336 */
12826 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12828 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12829 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12831 /* Acer C720 Chromebook (Core i3 4005U) */
12832 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12834 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12835 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12837 /* HP Chromebook 14 (Celeron 2955U) */
12838 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12841 static void intel_init_quirks(struct drm_device *dev)
12843 struct pci_dev *d = dev->pdev;
12846 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12847 struct intel_quirk *q = &intel_quirks[i];
12849 if (d->device == q->device &&
12850 (d->subsystem_vendor == q->subsystem_vendor ||
12851 q->subsystem_vendor == PCI_ANY_ID) &&
12852 (d->subsystem_device == q->subsystem_device ||
12853 q->subsystem_device == PCI_ANY_ID))
12856 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12857 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12858 intel_dmi_quirks[i].hook(dev);
12862 /* Disable the VGA plane that we never use */
12863 static void i915_disable_vga(struct drm_device *dev)
12865 struct drm_i915_private *dev_priv = dev->dev_private;
12867 u32 vga_reg = i915_vgacntrl_reg(dev);
12869 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12870 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12871 outb(SR01, VGA_SR_INDEX);
12872 sr1 = inb(VGA_SR_DATA);
12873 outb(sr1 | 1<<5, VGA_SR_DATA);
12874 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12878 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12879 * from S3 without preserving (some of?) the other bits.
12881 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12882 POSTING_READ(vga_reg);
12885 void intel_modeset_init_hw(struct drm_device *dev)
12887 intel_prepare_ddi(dev);
12889 if (IS_VALLEYVIEW(dev))
12890 vlv_update_cdclk(dev);
12892 intel_init_clock_gating(dev);
12894 intel_enable_gt_powersave(dev);
12897 void intel_modeset_init(struct drm_device *dev)
12899 struct drm_i915_private *dev_priv = dev->dev_private;
12902 struct intel_crtc *crtc;
12904 drm_mode_config_init(dev);
12906 dev->mode_config.min_width = 0;
12907 dev->mode_config.min_height = 0;
12909 dev->mode_config.preferred_depth = 24;
12910 dev->mode_config.prefer_shadow = 1;
12912 dev->mode_config.funcs = &intel_mode_funcs;
12914 intel_init_quirks(dev);
12916 intel_init_pm(dev);
12918 if (INTEL_INFO(dev)->num_pipes == 0)
12921 intel_init_display(dev);
12923 if (IS_GEN2(dev)) {
12924 dev->mode_config.max_width = 2048;
12925 dev->mode_config.max_height = 2048;
12926 } else if (IS_GEN3(dev)) {
12927 dev->mode_config.max_width = 4096;
12928 dev->mode_config.max_height = 4096;
12930 dev->mode_config.max_width = 8192;
12931 dev->mode_config.max_height = 8192;
12934 if (IS_845G(dev) || IS_I865G(dev)) {
12935 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12936 dev->mode_config.cursor_height = 1023;
12937 } else if (IS_GEN2(dev)) {
12938 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12939 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12941 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12942 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12945 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12947 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12948 INTEL_INFO(dev)->num_pipes,
12949 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12951 for_each_pipe(dev_priv, pipe) {
12952 intel_crtc_init(dev, pipe);
12953 for_each_sprite(pipe, sprite) {
12954 ret = intel_plane_init(dev, pipe, sprite);
12956 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12957 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12961 intel_init_dpio(dev);
12963 intel_shared_dpll_init(dev);
12965 /* save the BIOS value before clobbering it */
12966 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12967 /* Just disable it once at startup */
12968 i915_disable_vga(dev);
12969 intel_setup_outputs(dev);
12971 /* Just in case the BIOS is doing something questionable. */
12972 intel_disable_fbc(dev);
12974 drm_modeset_lock_all(dev);
12975 intel_modeset_setup_hw_state(dev, false);
12976 drm_modeset_unlock_all(dev);
12978 for_each_intel_crtc(dev, crtc) {
12983 * Note that reserving the BIOS fb up front prevents us
12984 * from stuffing other stolen allocations like the ring
12985 * on top. This prevents some ugliness at boot time, and
12986 * can even allow for smooth boot transitions if the BIOS
12987 * fb is large enough for the active pipe configuration.
12989 if (dev_priv->display.get_plane_config) {
12990 dev_priv->display.get_plane_config(crtc,
12991 &crtc->plane_config);
12993 * If the fb is shared between multiple heads, we'll
12994 * just get the first one.
12996 intel_find_plane_obj(crtc, &crtc->plane_config);
13001 static void intel_enable_pipe_a(struct drm_device *dev)
13003 struct intel_connector *connector;
13004 struct drm_connector *crt = NULL;
13005 struct intel_load_detect_pipe load_detect_temp;
13006 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13008 /* We can't just switch on the pipe A, we need to set things up with a
13009 * proper mode and output configuration. As a gross hack, enable pipe A
13010 * by enabling the load detect pipe once. */
13011 list_for_each_entry(connector,
13012 &dev->mode_config.connector_list,
13014 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13015 crt = &connector->base;
13023 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13024 intel_release_load_detect_pipe(crt, &load_detect_temp);
13028 intel_check_plane_mapping(struct intel_crtc *crtc)
13030 struct drm_device *dev = crtc->base.dev;
13031 struct drm_i915_private *dev_priv = dev->dev_private;
13034 if (INTEL_INFO(dev)->num_pipes == 1)
13037 reg = DSPCNTR(!crtc->plane);
13038 val = I915_READ(reg);
13040 if ((val & DISPLAY_PLANE_ENABLE) &&
13041 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13047 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13049 struct drm_device *dev = crtc->base.dev;
13050 struct drm_i915_private *dev_priv = dev->dev_private;
13053 /* Clear any frame start delays used for debugging left by the BIOS */
13054 reg = PIPECONF(crtc->config.cpu_transcoder);
13055 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13057 /* restore vblank interrupts to correct state */
13058 if (crtc->active) {
13059 update_scanline_offset(crtc);
13060 drm_vblank_on(dev, crtc->pipe);
13062 drm_vblank_off(dev, crtc->pipe);
13064 /* We need to sanitize the plane -> pipe mapping first because this will
13065 * disable the crtc (and hence change the state) if it is wrong. Note
13066 * that gen4+ has a fixed plane -> pipe mapping. */
13067 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13068 struct intel_connector *connector;
13071 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13072 crtc->base.base.id);
13074 /* Pipe has the wrong plane attached and the plane is active.
13075 * Temporarily change the plane mapping and disable everything
13077 plane = crtc->plane;
13078 crtc->plane = !plane;
13079 crtc->primary_enabled = true;
13080 dev_priv->display.crtc_disable(&crtc->base);
13081 crtc->plane = plane;
13083 /* ... and break all links. */
13084 list_for_each_entry(connector, &dev->mode_config.connector_list,
13086 if (connector->encoder->base.crtc != &crtc->base)
13089 connector->base.dpms = DRM_MODE_DPMS_OFF;
13090 connector->base.encoder = NULL;
13092 /* multiple connectors may have the same encoder:
13093 * handle them and break crtc link separately */
13094 list_for_each_entry(connector, &dev->mode_config.connector_list,
13096 if (connector->encoder->base.crtc == &crtc->base) {
13097 connector->encoder->base.crtc = NULL;
13098 connector->encoder->connectors_active = false;
13101 WARN_ON(crtc->active);
13102 crtc->base.enabled = false;
13105 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13106 crtc->pipe == PIPE_A && !crtc->active) {
13107 /* BIOS forgot to enable pipe A, this mostly happens after
13108 * resume. Force-enable the pipe to fix this, the update_dpms
13109 * call below we restore the pipe to the right state, but leave
13110 * the required bits on. */
13111 intel_enable_pipe_a(dev);
13114 /* Adjust the state of the output pipe according to whether we
13115 * have active connectors/encoders. */
13116 intel_crtc_update_dpms(&crtc->base);
13118 if (crtc->active != crtc->base.enabled) {
13119 struct intel_encoder *encoder;
13121 /* This can happen either due to bugs in the get_hw_state
13122 * functions or because the pipe is force-enabled due to the
13124 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13125 crtc->base.base.id,
13126 crtc->base.enabled ? "enabled" : "disabled",
13127 crtc->active ? "enabled" : "disabled");
13129 crtc->base.enabled = crtc->active;
13131 /* Because we only establish the connector -> encoder ->
13132 * crtc links if something is active, this means the
13133 * crtc is now deactivated. Break the links. connector
13134 * -> encoder links are only establish when things are
13135 * actually up, hence no need to break them. */
13136 WARN_ON(crtc->active);
13138 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13139 WARN_ON(encoder->connectors_active);
13140 encoder->base.crtc = NULL;
13144 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13146 * We start out with underrun reporting disabled to avoid races.
13147 * For correct bookkeeping mark this on active crtcs.
13149 * Also on gmch platforms we dont have any hardware bits to
13150 * disable the underrun reporting. Which means we need to start
13151 * out with underrun reporting disabled also on inactive pipes,
13152 * since otherwise we'll complain about the garbage we read when
13153 * e.g. coming up after runtime pm.
13155 * No protection against concurrent access is required - at
13156 * worst a fifo underrun happens which also sets this to false.
13158 crtc->cpu_fifo_underrun_disabled = true;
13159 crtc->pch_fifo_underrun_disabled = true;
13163 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13165 struct intel_connector *connector;
13166 struct drm_device *dev = encoder->base.dev;
13168 /* We need to check both for a crtc link (meaning that the
13169 * encoder is active and trying to read from a pipe) and the
13170 * pipe itself being active. */
13171 bool has_active_crtc = encoder->base.crtc &&
13172 to_intel_crtc(encoder->base.crtc)->active;
13174 if (encoder->connectors_active && !has_active_crtc) {
13175 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13176 encoder->base.base.id,
13177 encoder->base.name);
13179 /* Connector is active, but has no active pipe. This is
13180 * fallout from our resume register restoring. Disable
13181 * the encoder manually again. */
13182 if (encoder->base.crtc) {
13183 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13184 encoder->base.base.id,
13185 encoder->base.name);
13186 encoder->disable(encoder);
13187 if (encoder->post_disable)
13188 encoder->post_disable(encoder);
13190 encoder->base.crtc = NULL;
13191 encoder->connectors_active = false;
13193 /* Inconsistent output/port/pipe state happens presumably due to
13194 * a bug in one of the get_hw_state functions. Or someplace else
13195 * in our code, like the register restore mess on resume. Clamp
13196 * things to off as a safer default. */
13197 list_for_each_entry(connector,
13198 &dev->mode_config.connector_list,
13200 if (connector->encoder != encoder)
13202 connector->base.dpms = DRM_MODE_DPMS_OFF;
13203 connector->base.encoder = NULL;
13206 /* Enabled encoders without active connectors will be fixed in
13207 * the crtc fixup. */
13210 void i915_redisable_vga_power_on(struct drm_device *dev)
13212 struct drm_i915_private *dev_priv = dev->dev_private;
13213 u32 vga_reg = i915_vgacntrl_reg(dev);
13215 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13216 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13217 i915_disable_vga(dev);
13221 void i915_redisable_vga(struct drm_device *dev)
13223 struct drm_i915_private *dev_priv = dev->dev_private;
13225 /* This function can be called both from intel_modeset_setup_hw_state or
13226 * at a very early point in our resume sequence, where the power well
13227 * structures are not yet restored. Since this function is at a very
13228 * paranoid "someone might have enabled VGA while we were not looking"
13229 * level, just check if the power well is enabled instead of trying to
13230 * follow the "don't touch the power well if we don't need it" policy
13231 * the rest of the driver uses. */
13232 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13235 i915_redisable_vga_power_on(dev);
13238 static bool primary_get_hw_state(struct intel_crtc *crtc)
13240 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13245 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13248 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13250 struct drm_i915_private *dev_priv = dev->dev_private;
13252 struct intel_crtc *crtc;
13253 struct intel_encoder *encoder;
13254 struct intel_connector *connector;
13257 for_each_intel_crtc(dev, crtc) {
13258 memset(&crtc->config, 0, sizeof(crtc->config));
13260 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13262 crtc->active = dev_priv->display.get_pipe_config(crtc,
13265 crtc->base.enabled = crtc->active;
13266 crtc->primary_enabled = primary_get_hw_state(crtc);
13268 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13269 crtc->base.base.id,
13270 crtc->active ? "enabled" : "disabled");
13273 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13274 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13276 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13278 for_each_intel_crtc(dev, crtc) {
13279 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13282 pll->refcount = pll->active;
13284 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13285 pll->name, pll->refcount, pll->on);
13288 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13291 for_each_intel_encoder(dev, encoder) {
13294 if (encoder->get_hw_state(encoder, &pipe)) {
13295 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13296 encoder->base.crtc = &crtc->base;
13297 encoder->get_config(encoder, &crtc->config);
13299 encoder->base.crtc = NULL;
13302 encoder->connectors_active = false;
13303 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13304 encoder->base.base.id,
13305 encoder->base.name,
13306 encoder->base.crtc ? "enabled" : "disabled",
13310 list_for_each_entry(connector, &dev->mode_config.connector_list,
13312 if (connector->get_hw_state(connector)) {
13313 connector->base.dpms = DRM_MODE_DPMS_ON;
13314 connector->encoder->connectors_active = true;
13315 connector->base.encoder = &connector->encoder->base;
13317 connector->base.dpms = DRM_MODE_DPMS_OFF;
13318 connector->base.encoder = NULL;
13320 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13321 connector->base.base.id,
13322 connector->base.name,
13323 connector->base.encoder ? "enabled" : "disabled");
13327 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13328 * and i915 state tracking structures. */
13329 void intel_modeset_setup_hw_state(struct drm_device *dev,
13330 bool force_restore)
13332 struct drm_i915_private *dev_priv = dev->dev_private;
13334 struct intel_crtc *crtc;
13335 struct intel_encoder *encoder;
13338 intel_modeset_readout_hw_state(dev);
13341 * Now that we have the config, copy it to each CRTC struct
13342 * Note that this could go away if we move to using crtc_config
13343 * checking everywhere.
13345 for_each_intel_crtc(dev, crtc) {
13346 if (crtc->active && i915.fastboot) {
13347 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13348 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13349 crtc->base.base.id);
13350 drm_mode_debug_printmodeline(&crtc->base.mode);
13354 /* HW state is read out, now we need to sanitize this mess. */
13355 for_each_intel_encoder(dev, encoder) {
13356 intel_sanitize_encoder(encoder);
13359 for_each_pipe(dev_priv, pipe) {
13360 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13361 intel_sanitize_crtc(crtc);
13362 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13365 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13366 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13368 if (!pll->on || pll->active)
13371 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13373 pll->disable(dev_priv, pll);
13377 if (HAS_PCH_SPLIT(dev))
13378 ilk_wm_get_hw_state(dev);
13380 if (force_restore) {
13381 i915_redisable_vga(dev);
13384 * We need to use raw interfaces for restoring state to avoid
13385 * checking (bogus) intermediate states.
13387 for_each_pipe(dev_priv, pipe) {
13388 struct drm_crtc *crtc =
13389 dev_priv->pipe_to_crtc_mapping[pipe];
13391 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13392 crtc->primary->fb);
13395 intel_modeset_update_staged_output_state(dev);
13398 intel_modeset_check_state(dev);
13401 void intel_modeset_gem_init(struct drm_device *dev)
13403 struct drm_crtc *c;
13404 struct drm_i915_gem_object *obj;
13406 mutex_lock(&dev->struct_mutex);
13407 intel_init_gt_powersave(dev);
13408 mutex_unlock(&dev->struct_mutex);
13410 intel_modeset_init_hw(dev);
13412 intel_setup_overlay(dev);
13415 * Make sure any fbs we allocated at startup are properly
13416 * pinned & fenced. When we do the allocation it's too early
13419 mutex_lock(&dev->struct_mutex);
13420 for_each_crtc(dev, c) {
13421 obj = intel_fb_obj(c->primary->fb);
13425 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13426 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13427 to_intel_crtc(c)->pipe);
13428 drm_framebuffer_unreference(c->primary->fb);
13429 c->primary->fb = NULL;
13432 mutex_unlock(&dev->struct_mutex);
13435 void intel_connector_unregister(struct intel_connector *intel_connector)
13437 struct drm_connector *connector = &intel_connector->base;
13439 intel_panel_destroy_backlight(connector);
13440 drm_connector_unregister(connector);
13443 void intel_modeset_cleanup(struct drm_device *dev)
13445 struct drm_i915_private *dev_priv = dev->dev_private;
13446 struct drm_connector *connector;
13449 * Interrupts and polling as the first thing to avoid creating havoc.
13450 * Too much stuff here (turning of rps, connectors, ...) would
13451 * experience fancy races otherwise.
13453 intel_irq_uninstall(dev_priv);
13456 * Due to the hpd irq storm handling the hotplug work can re-arm the
13457 * poll handlers. Hence disable polling after hpd handling is shut down.
13459 drm_kms_helper_poll_fini(dev);
13461 mutex_lock(&dev->struct_mutex);
13463 intel_unregister_dsm_handler();
13465 intel_disable_fbc(dev);
13467 intel_disable_gt_powersave(dev);
13469 ironlake_teardown_rc6(dev);
13471 mutex_unlock(&dev->struct_mutex);
13473 /* flush any delayed tasks or pending work */
13474 flush_scheduled_work();
13476 /* destroy the backlight and sysfs files before encoders/connectors */
13477 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13478 struct intel_connector *intel_connector;
13480 intel_connector = to_intel_connector(connector);
13481 intel_connector->unregister(intel_connector);
13484 drm_mode_config_cleanup(dev);
13486 intel_cleanup_overlay(dev);
13488 mutex_lock(&dev->struct_mutex);
13489 intel_cleanup_gt_powersave(dev);
13490 mutex_unlock(&dev->struct_mutex);
13494 * Return which encoder is currently attached for connector.
13496 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13498 return &intel_attached_encoder(connector)->base;
13501 void intel_connector_attach_encoder(struct intel_connector *connector,
13502 struct intel_encoder *encoder)
13504 connector->encoder = encoder;
13505 drm_mode_connector_attach_encoder(&connector->base,
13510 * set vga decode state - true == enable VGA decode
13512 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13514 struct drm_i915_private *dev_priv = dev->dev_private;
13515 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13518 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13519 DRM_ERROR("failed to read control word\n");
13523 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13527 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13529 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13531 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13532 DRM_ERROR("failed to write control word\n");
13539 struct intel_display_error_state {
13541 u32 power_well_driver;
13543 int num_transcoders;
13545 struct intel_cursor_error_state {
13550 } cursor[I915_MAX_PIPES];
13552 struct intel_pipe_error_state {
13553 bool power_domain_on;
13556 } pipe[I915_MAX_PIPES];
13558 struct intel_plane_error_state {
13566 } plane[I915_MAX_PIPES];
13568 struct intel_transcoder_error_state {
13569 bool power_domain_on;
13570 enum transcoder cpu_transcoder;
13583 struct intel_display_error_state *
13584 intel_display_capture_error_state(struct drm_device *dev)
13586 struct drm_i915_private *dev_priv = dev->dev_private;
13587 struct intel_display_error_state *error;
13588 int transcoders[] = {
13596 if (INTEL_INFO(dev)->num_pipes == 0)
13599 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13603 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13604 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13606 for_each_pipe(dev_priv, i) {
13607 error->pipe[i].power_domain_on =
13608 __intel_display_power_is_enabled(dev_priv,
13609 POWER_DOMAIN_PIPE(i));
13610 if (!error->pipe[i].power_domain_on)
13613 error->cursor[i].control = I915_READ(CURCNTR(i));
13614 error->cursor[i].position = I915_READ(CURPOS(i));
13615 error->cursor[i].base = I915_READ(CURBASE(i));
13617 error->plane[i].control = I915_READ(DSPCNTR(i));
13618 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13619 if (INTEL_INFO(dev)->gen <= 3) {
13620 error->plane[i].size = I915_READ(DSPSIZE(i));
13621 error->plane[i].pos = I915_READ(DSPPOS(i));
13623 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13624 error->plane[i].addr = I915_READ(DSPADDR(i));
13625 if (INTEL_INFO(dev)->gen >= 4) {
13626 error->plane[i].surface = I915_READ(DSPSURF(i));
13627 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13630 error->pipe[i].source = I915_READ(PIPESRC(i));
13632 if (HAS_GMCH_DISPLAY(dev))
13633 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13636 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13637 if (HAS_DDI(dev_priv->dev))
13638 error->num_transcoders++; /* Account for eDP. */
13640 for (i = 0; i < error->num_transcoders; i++) {
13641 enum transcoder cpu_transcoder = transcoders[i];
13643 error->transcoder[i].power_domain_on =
13644 __intel_display_power_is_enabled(dev_priv,
13645 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13646 if (!error->transcoder[i].power_domain_on)
13649 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13651 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13652 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13653 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13654 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13655 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13656 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13657 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13663 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13666 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13667 struct drm_device *dev,
13668 struct intel_display_error_state *error)
13670 struct drm_i915_private *dev_priv = dev->dev_private;
13676 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13677 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13678 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13679 error->power_well_driver);
13680 for_each_pipe(dev_priv, i) {
13681 err_printf(m, "Pipe [%d]:\n", i);
13682 err_printf(m, " Power: %s\n",
13683 error->pipe[i].power_domain_on ? "on" : "off");
13684 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13685 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13687 err_printf(m, "Plane [%d]:\n", i);
13688 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13689 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13690 if (INTEL_INFO(dev)->gen <= 3) {
13691 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13692 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13694 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13695 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13696 if (INTEL_INFO(dev)->gen >= 4) {
13697 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13698 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13701 err_printf(m, "Cursor [%d]:\n", i);
13702 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13703 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13704 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13707 for (i = 0; i < error->num_transcoders; i++) {
13708 err_printf(m, "CPU transcoder: %c\n",
13709 transcoder_name(error->transcoder[i].cpu_transcoder));
13710 err_printf(m, " Power: %s\n",
13711 error->transcoder[i].power_domain_on ? "on" : "off");
13712 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13713 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13714 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13715 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13716 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13717 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13718 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13722 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13724 struct intel_crtc *crtc;
13726 for_each_intel_crtc(dev, crtc) {
13727 struct intel_unpin_work *work;
13729 spin_lock_irq(&dev->event_lock);
13731 work = crtc->unpin_work;
13733 if (work && work->event &&
13734 work->event->base.file_priv == file) {
13735 kfree(work->event);
13736 work->event = NULL;
13739 spin_unlock_irq(&dev->event_lock);