2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
72 static const uint32_t intel_cursor_formats[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
104 if (!connector->mst_port)
105 return connector->encoder;
107 return &connector->mst_port->mst_encoders[pipe]->base;
116 int p2_slow, p2_fast;
119 typedef struct intel_limit intel_limit_t;
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_pch_rawclk(struct drm_device *dev)
128 struct drm_i915_private *dev_priv = dev->dev_private;
130 WARN_ON(!HAS_PCH_SPLIT(dev));
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
366 static const intel_limit_t intel_limits_vlv = {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv = {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 static void vlv_clock(int refclk, intel_clock_t *clock)
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
452 limit = &intel_limits_ironlake_dual_lvds;
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
457 limit = &intel_limits_ironlake_single_lvds;
460 limit = &intel_limits_ironlake_dac;
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
508 limit = &intel_limits_i9xx_sdvo;
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
515 limit = &intel_limits_i8xx_dac;
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
546 static void chv_clock(int refclk, intel_clock_t *clock)
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
603 struct drm_device *dev = crtc->base.dev;
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
616 clock.p2 = limit->p2.p2_slow;
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
621 clock.p2 = limit->p2.p2_fast;
624 memset(best_clock, 0, sizeof(*best_clock));
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
643 clock.p != match_clock->p)
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
656 return (err != target);
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
664 struct drm_device *dev = crtc->base.dev;
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
677 clock.p2 = limit->p2.p2_slow;
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
682 clock.p2 = limit->p2.p2_fast;
685 memset(best_clock, 0, sizeof(*best_clock));
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
702 clock.p != match_clock->p)
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
715 return (err != target);
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
723 struct drm_device *dev = crtc->base.dev;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
735 clock.p2 = limit->p2.p2_slow;
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
740 clock.p2 = limit->p2.p2_fast;
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
780 struct drm_device *dev = crtc->base.dev;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
787 target *= 5; /* fast clock */
789 memset(best_clock, 0, sizeof(*best_clock));
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
804 vlv_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
813 if (ppm < 100 && clock.p > best_clock->p) {
819 if (bestppm >= 10 && ppm < bestppm - 10) {
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
837 struct drm_device *dev = crtc->base.dev;
842 memset(best_clock, 0, sizeof(*best_clock));
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
857 clock.p = clock.p1 * clock.p2;
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
862 if (m2 > INT_MAX/clock.m1)
867 chv_clock(refclk, &clock);
869 if (!intel_PLL_is_valid(dev, limit, &clock))
872 /* based on hardware requirement, prefer bigger p
874 if (clock.p > best_clock->p) {
884 bool intel_crtc_active(struct drm_crtc *crtc)
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
907 return intel_crtc->config.cpu_transcoder;
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
918 line_mask = DSL_LINEMASK_GEN2;
920 line_mask = DSL_LINEMASK_GEN3;
922 line1 = I915_READ(reg) & line_mask;
924 line2 = I915_READ(reg) & line_mask;
926 return line1 == line2;
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
938 * wait for the pipe register state bit to turn off
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
958 WARN(1, "pipe_off wait timed out\n");
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
971 * Returns true if @port is connected, false otherwise.
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
981 bit = SDE_PORTB_HOTPLUG;
984 bit = SDE_PORTC_HOTPLUG;
987 bit = SDE_PORTD_HOTPLUG;
993 switch (port->port) {
995 bit = SDE_PORTB_HOTPLUG_CPT;
998 bit = SDE_PORTC_HOTPLUG_CPT;
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1008 return I915_READ(SDEISR) & bit;
1011 static const char *state_string(bool enabled)
1013 return enabled ? "on" : "off";
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1055 if (crtc->config.shared_dpll < 0)
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1067 struct intel_dpll_hw_state hw_state;
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1159 struct drm_device *dev = dev_priv->dev;
1162 enum pipe panel_pipe = PIPE_A;
1165 if (WARN_ON(HAS_DDI(dev)))
1168 if (HAS_PCH_SPLIT(dev)) {
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1201 struct drm_device *dev = dev_priv->dev;
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1265 struct drm_device *dev = dev_priv->dev;
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1295 struct drm_device *dev = dev_priv->dev;
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1366 if ((val & DP_PORT_EN) == 0)
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1387 if ((val & SDVO_ENABLE) == 0)
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1406 if ((val & LVDS_PORT_EN) == 0)
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 static void intel_init_dpio(struct drm_device *dev)
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1491 if (!IS_VALLEYVIEW(dev))
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1524 I915_WRITE(reg, dpll);
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1543 udelay(150); /* wait for warmup */
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1559 mutex_lock(&dev_priv->dpio_lock);
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1582 mutex_unlock(&dev_priv->dpio_lock);
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1587 struct intel_crtc *crtc;
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg, dpll);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1724 mutex_lock(&dev_priv->dpio_lock);
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1742 mutex_unlock(&dev_priv->dpio_lock);
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1751 switch (dport->port) {
1753 port_mask = DPLL_PORTB_READY_MASK;
1757 port_mask = DPLL_PORTC_READY_MASK;
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1779 if (WARN_ON(pll == NULL))
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1788 pll->mode_set(dev_priv, pll);
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1806 if (WARN_ON(pll == NULL))
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1816 if (pll->active++) {
1818 assert_shared_dpll_enabled(dev_priv, pll);
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1853 assert_shared_dpll_enabled(dev_priv, pll);
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1912 val |= TRANS_INTERLACED;
1914 val |= TRANS_PROGRESSIVE;
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1924 u32 val, pipeconf_val;
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1945 val |= TRANS_PROGRESSIVE;
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 struct drm_device *dev = dev_priv->dev;
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013 enum pipe pch_transcoder;
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2024 pch_transcoder = pipe;
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2035 assert_pll_enabled(dev_priv, pipe);
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2043 /* FIXME: assert CPU port conditions for SNB+ */
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2066 * Will wait until the pipe has shut down before returning.
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2116 I915_WRITE(reg, I915_READ(reg));
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2137 if (intel_crtc->primary_enabled)
2140 intel_crtc->primary_enabled = true;
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2170 if (!intel_crtc->primary_enabled)
2173 intel_crtc->primary_enabled = false;
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2179 static bool need_vtd_wa(struct drm_device *dev)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198 struct drm_i915_gem_object *obj,
2199 struct intel_engine_cs *pipelined)
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2205 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2207 switch (obj->tiling_mode) {
2208 case I915_TILING_NONE:
2209 if (INTEL_INFO(dev)->gen >= 9)
2210 alignment = 256 * 1024;
2211 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212 alignment = 128 * 1024;
2213 else if (INTEL_INFO(dev)->gen >= 4)
2214 alignment = 4 * 1024;
2216 alignment = 64 * 1024;
2219 if (INTEL_INFO(dev)->gen >= 9)
2220 alignment = 256 * 1024;
2222 /* pin() will align the object as required by fence */
2227 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2233 /* Note that the w/a also requires 64 PTE of padding following the
2234 * bo. We currently fill all unused PTE with the shadow page and so
2235 * we should always have valid PTE following the scanout preventing
2238 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239 alignment = 256 * 1024;
2242 * Global gtt pte registers are special registers which actually forward
2243 * writes to a chunk of system memory. Which means that there is no risk
2244 * that the register values disappear as soon as we call
2245 * intel_runtime_pm_put(), so it is correct to wrap only the
2246 * pin/unpin/fence and not more.
2248 intel_runtime_pm_get(dev_priv);
2250 dev_priv->mm.interruptible = false;
2251 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2253 goto err_interruptible;
2255 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256 * fence, whereas 965+ only requires a fence if using
2257 * framebuffer compression. For simplicity, we always install
2258 * a fence as the cost is not that onerous.
2260 ret = i915_gem_object_get_fence(obj);
2264 i915_gem_object_pin_fence(obj);
2266 dev_priv->mm.interruptible = true;
2267 intel_runtime_pm_put(dev_priv);
2271 i915_gem_object_unpin_from_display_plane(obj);
2273 dev_priv->mm.interruptible = true;
2274 intel_runtime_pm_put(dev_priv);
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2280 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2282 i915_gem_object_unpin_fence(obj);
2283 i915_gem_object_unpin_from_display_plane(obj);
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287 * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289 unsigned int tiling_mode,
2293 if (tiling_mode != I915_TILING_NONE) {
2294 unsigned int tile_rows, tiles;
2299 tiles = *x / (512/cpp);
2302 return tile_rows * pitch * 8 + tiles * 4096;
2304 unsigned int offset;
2306 offset = *y * pitch + *x * cpp;
2308 *x = (offset & 4095) / cpp;
2309 return offset & -4096;
2313 int intel_format_to_fourcc(int format)
2316 case DISPPLANE_8BPP:
2317 return DRM_FORMAT_C8;
2318 case DISPPLANE_BGRX555:
2319 return DRM_FORMAT_XRGB1555;
2320 case DISPPLANE_BGRX565:
2321 return DRM_FORMAT_RGB565;
2323 case DISPPLANE_BGRX888:
2324 return DRM_FORMAT_XRGB8888;
2325 case DISPPLANE_RGBX888:
2326 return DRM_FORMAT_XBGR8888;
2327 case DISPPLANE_BGRX101010:
2328 return DRM_FORMAT_XRGB2101010;
2329 case DISPPLANE_RGBX101010:
2330 return DRM_FORMAT_XBGR2101010;
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335 struct intel_plane_config *plane_config)
2337 struct drm_device *dev = crtc->base.dev;
2338 struct drm_i915_gem_object *obj = NULL;
2339 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340 u32 base = plane_config->base;
2342 if (plane_config->size == 0)
2345 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346 plane_config->size);
2350 if (plane_config->tiled) {
2351 obj->tiling_mode = I915_TILING_X;
2352 obj->stride = crtc->base.primary->fb->pitches[0];
2355 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356 mode_cmd.width = crtc->base.primary->fb->width;
2357 mode_cmd.height = crtc->base.primary->fb->height;
2358 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2360 mutex_lock(&dev->struct_mutex);
2362 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2364 DRM_DEBUG_KMS("intel fb init failed\n");
2368 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369 mutex_unlock(&dev->struct_mutex);
2371 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2375 drm_gem_object_unreference(&obj->base);
2376 mutex_unlock(&dev->struct_mutex);
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381 struct intel_plane_config *plane_config)
2383 struct drm_device *dev = intel_crtc->base.dev;
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *i;
2387 struct drm_i915_gem_object *obj;
2389 if (!intel_crtc->base.primary->fb)
2392 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 kfree(intel_crtc->base.primary->fb);
2396 intel_crtc->base.primary->fb = NULL;
2399 * Failed to alloc the obj, check to see if we should share
2400 * an fb with another CRTC instead
2402 for_each_crtc(dev, c) {
2403 i = to_intel_crtc(c);
2405 if (c == &intel_crtc->base)
2411 obj = intel_fb_obj(c->primary->fb);
2415 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416 if (obj->tiling_mode != I915_TILING_NONE)
2417 dev_priv->preserve_bios_swizzle = true;
2419 drm_framebuffer_reference(c->primary->fb);
2420 intel_crtc->base.primary->fb = c->primary->fb;
2421 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428 struct drm_framebuffer *fb,
2431 struct drm_device *dev = crtc->dev;
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434 struct drm_i915_gem_object *obj;
2435 int plane = intel_crtc->plane;
2436 unsigned long linear_offset;
2438 u32 reg = DSPCNTR(plane);
2441 if (!intel_crtc->primary_enabled) {
2443 if (INTEL_INFO(dev)->gen >= 4)
2444 I915_WRITE(DSPSURF(plane), 0);
2446 I915_WRITE(DSPADDR(plane), 0);
2451 obj = intel_fb_obj(fb);
2452 if (WARN_ON(obj == NULL))
2455 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2457 dspcntr = DISPPLANE_GAMMA_ENABLE;
2459 dspcntr |= DISPLAY_PLANE_ENABLE;
2461 if (INTEL_INFO(dev)->gen < 4) {
2462 if (intel_crtc->pipe == PIPE_B)
2463 dspcntr |= DISPPLANE_SEL_PIPE_B;
2465 /* pipesrc and dspsize control the size that is scaled from,
2466 * which should always be the user's requested size.
2468 I915_WRITE(DSPSIZE(plane),
2469 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470 (intel_crtc->config.pipe_src_w - 1));
2471 I915_WRITE(DSPPOS(plane), 0);
2472 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473 I915_WRITE(PRIMSIZE(plane),
2474 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475 (intel_crtc->config.pipe_src_w - 1));
2476 I915_WRITE(PRIMPOS(plane), 0);
2477 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480 switch (fb->pixel_format) {
2482 dspcntr |= DISPPLANE_8BPP;
2484 case DRM_FORMAT_XRGB1555:
2485 case DRM_FORMAT_ARGB1555:
2486 dspcntr |= DISPPLANE_BGRX555;
2488 case DRM_FORMAT_RGB565:
2489 dspcntr |= DISPPLANE_BGRX565;
2491 case DRM_FORMAT_XRGB8888:
2492 case DRM_FORMAT_ARGB8888:
2493 dspcntr |= DISPPLANE_BGRX888;
2495 case DRM_FORMAT_XBGR8888:
2496 case DRM_FORMAT_ABGR8888:
2497 dspcntr |= DISPPLANE_RGBX888;
2499 case DRM_FORMAT_XRGB2101010:
2500 case DRM_FORMAT_ARGB2101010:
2501 dspcntr |= DISPPLANE_BGRX101010;
2503 case DRM_FORMAT_XBGR2101010:
2504 case DRM_FORMAT_ABGR2101010:
2505 dspcntr |= DISPPLANE_RGBX101010;
2511 if (INTEL_INFO(dev)->gen >= 4 &&
2512 obj->tiling_mode != I915_TILING_NONE)
2513 dspcntr |= DISPPLANE_TILED;
2516 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2518 linear_offset = y * fb->pitches[0] + x * pixel_size;
2520 if (INTEL_INFO(dev)->gen >= 4) {
2521 intel_crtc->dspaddr_offset =
2522 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 linear_offset -= intel_crtc->dspaddr_offset;
2527 intel_crtc->dspaddr_offset = linear_offset;
2530 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531 dspcntr |= DISPPLANE_ROTATE_180;
2533 x += (intel_crtc->config.pipe_src_w - 1);
2534 y += (intel_crtc->config.pipe_src_h - 1);
2536 /* Finding the last pixel of the last line of the display
2537 data and adding to linear_offset*/
2539 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 I915_WRITE(reg, dspcntr);
2545 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2548 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549 if (INTEL_INFO(dev)->gen >= 4) {
2550 I915_WRITE(DSPSURF(plane),
2551 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553 I915_WRITE(DSPLINOFF(plane), linear_offset);
2555 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560 struct drm_framebuffer *fb,
2563 struct drm_device *dev = crtc->dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566 struct drm_i915_gem_object *obj;
2567 int plane = intel_crtc->plane;
2568 unsigned long linear_offset;
2570 u32 reg = DSPCNTR(plane);
2573 if (!intel_crtc->primary_enabled) {
2575 I915_WRITE(DSPSURF(plane), 0);
2580 obj = intel_fb_obj(fb);
2581 if (WARN_ON(obj == NULL))
2584 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2586 dspcntr = DISPPLANE_GAMMA_ENABLE;
2588 dspcntr |= DISPLAY_PLANE_ENABLE;
2590 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2593 switch (fb->pixel_format) {
2595 dspcntr |= DISPPLANE_8BPP;
2597 case DRM_FORMAT_RGB565:
2598 dspcntr |= DISPPLANE_BGRX565;
2600 case DRM_FORMAT_XRGB8888:
2601 case DRM_FORMAT_ARGB8888:
2602 dspcntr |= DISPPLANE_BGRX888;
2604 case DRM_FORMAT_XBGR8888:
2605 case DRM_FORMAT_ABGR8888:
2606 dspcntr |= DISPPLANE_RGBX888;
2608 case DRM_FORMAT_XRGB2101010:
2609 case DRM_FORMAT_ARGB2101010:
2610 dspcntr |= DISPPLANE_BGRX101010;
2612 case DRM_FORMAT_XBGR2101010:
2613 case DRM_FORMAT_ABGR2101010:
2614 dspcntr |= DISPPLANE_RGBX101010;
2620 if (obj->tiling_mode != I915_TILING_NONE)
2621 dspcntr |= DISPPLANE_TILED;
2623 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2626 linear_offset = y * fb->pitches[0] + x * pixel_size;
2627 intel_crtc->dspaddr_offset =
2628 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631 linear_offset -= intel_crtc->dspaddr_offset;
2632 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633 dspcntr |= DISPPLANE_ROTATE_180;
2635 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636 x += (intel_crtc->config.pipe_src_w - 1);
2637 y += (intel_crtc->config.pipe_src_h - 1);
2639 /* Finding the last pixel of the last line of the display
2640 data and adding to linear_offset*/
2642 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2647 I915_WRITE(reg, dspcntr);
2649 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2652 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653 I915_WRITE(DSPSURF(plane),
2654 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2658 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659 I915_WRITE(DSPLINOFF(plane), linear_offset);
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665 struct drm_framebuffer *fb,
2668 struct drm_device *dev = crtc->dev;
2669 struct drm_i915_private *dev_priv = dev->dev_private;
2670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671 struct intel_framebuffer *intel_fb;
2672 struct drm_i915_gem_object *obj;
2673 int pipe = intel_crtc->pipe;
2674 u32 plane_ctl, stride;
2676 if (!intel_crtc->primary_enabled) {
2677 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679 POSTING_READ(PLANE_CTL(pipe, 0));
2683 plane_ctl = PLANE_CTL_ENABLE |
2684 PLANE_CTL_PIPE_GAMMA_ENABLE |
2685 PLANE_CTL_PIPE_CSC_ENABLE;
2687 switch (fb->pixel_format) {
2688 case DRM_FORMAT_RGB565:
2689 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2691 case DRM_FORMAT_XRGB8888:
2692 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2694 case DRM_FORMAT_XBGR8888:
2695 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2698 case DRM_FORMAT_XRGB2101010:
2699 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2701 case DRM_FORMAT_XBGR2101010:
2702 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2709 intel_fb = to_intel_framebuffer(fb);
2710 obj = intel_fb->obj;
2713 * The stride is either expressed as a multiple of 64 bytes chunks for
2714 * linear buffers or in number of tiles for tiled buffers.
2716 switch (obj->tiling_mode) {
2717 case I915_TILING_NONE:
2718 stride = fb->pitches[0] >> 6;
2721 plane_ctl |= PLANE_CTL_TILED_X;
2722 stride = fb->pitches[0] >> 9;
2728 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730 plane_ctl |= PLANE_CTL_ROTATE_180;
2732 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2734 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735 i915_gem_obj_ggtt_offset(obj),
2736 x, y, fb->width, fb->height,
2739 I915_WRITE(PLANE_POS(pipe, 0), 0);
2740 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741 I915_WRITE(PLANE_SIZE(pipe, 0),
2742 (intel_crtc->config.pipe_src_h - 1) << 16 |
2743 (intel_crtc->config.pipe_src_w - 1));
2744 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2747 POSTING_READ(PLANE_SURF(pipe, 0));
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753 int x, int y, enum mode_set_atomic state)
2755 struct drm_device *dev = crtc->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2758 if (dev_priv->display.disable_fbc)
2759 dev_priv->display.disable_fbc(dev);
2761 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2766 void intel_display_handle_reset(struct drm_device *dev)
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct drm_crtc *crtc;
2772 * Flips in the rings have been nuked by the reset,
2773 * so complete all pending flips so that user space
2774 * will get its events and not get stuck.
2776 * Also update the base address of all primary
2777 * planes to the the last fb to make sure we're
2778 * showing the correct fb after a reset.
2780 * Need to make two loops over the crtcs so that we
2781 * don't try to grab a crtc mutex before the
2782 * pending_flip_queue really got woken up.
2785 for_each_crtc(dev, crtc) {
2786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787 enum plane plane = intel_crtc->plane;
2789 intel_prepare_page_flip(dev, plane);
2790 intel_finish_page_flip_plane(dev, plane);
2793 for_each_crtc(dev, crtc) {
2794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2796 drm_modeset_lock(&crtc->mutex, NULL);
2798 * FIXME: Once we have proper support for primary planes (and
2799 * disabling them without disabling the entire crtc) allow again
2800 * a NULL crtc->primary->fb.
2802 if (intel_crtc->active && crtc->primary->fb)
2803 dev_priv->display.update_primary_plane(crtc,
2807 drm_modeset_unlock(&crtc->mutex);
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2814 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816 bool was_interruptible = dev_priv->mm.interruptible;
2819 /* Big Hammer, we also need to ensure that any pending
2820 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821 * current scanout is retired before unpinning the old
2824 * This should only fail upon a hung GPU, in which case we
2825 * can safely continue.
2827 dev_priv->mm.interruptible = false;
2828 ret = i915_gem_object_finish_gpu(obj);
2829 dev_priv->mm.interruptible = was_interruptible;
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2836 struct drm_device *dev = crtc->dev;
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 spin_lock_irq(&dev->event_lock);
2846 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847 spin_unlock_irq(&dev->event_lock);
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2854 struct drm_device *dev = crtc->base.dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856 const struct drm_display_mode *adjusted_mode;
2862 * Update pipe size and adjust fitter if needed: the reason for this is
2863 * that in compute_mode_changes we check the native mode (not the pfit
2864 * mode) to see if we can flip rather than do a full mode set. In the
2865 * fastboot case, we'll flip, but if we don't update the pipesrc and
2866 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * To fix this properly, we need to hoist the checks up into
2870 * compute_mode_changes (or above), check the actual pfit state and
2871 * whether the platform allows pfit disable with pipe active, and only
2872 * then update the pipesrc and pfit state, even on the flip path.
2875 adjusted_mode = &crtc->config.adjusted_mode;
2877 I915_WRITE(PIPESRC(crtc->pipe),
2878 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879 (adjusted_mode->crtc_vdisplay - 1));
2880 if (!crtc->config.pch_pfit.enabled &&
2881 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2887 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893 struct drm_framebuffer *fb)
2895 struct drm_device *dev = crtc->dev;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898 enum pipe pipe = intel_crtc->pipe;
2899 struct drm_framebuffer *old_fb = crtc->primary->fb;
2900 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2904 if (intel_crtc_has_pending_flip(crtc)) {
2905 DRM_ERROR("pipe is still busy with an old pageflip\n");
2911 DRM_ERROR("No FB bound\n");
2915 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917 plane_name(intel_crtc->plane),
2918 INTEL_INFO(dev)->num_pipes);
2922 mutex_lock(&dev->struct_mutex);
2923 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2925 i915_gem_track_fb(old_obj, obj,
2926 INTEL_FRONTBUFFER_PRIMARY(pipe));
2927 mutex_unlock(&dev->struct_mutex);
2929 DRM_ERROR("pin & fence failed\n");
2933 intel_update_pipe_size(intel_crtc);
2935 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2937 if (intel_crtc->active)
2938 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940 crtc->primary->fb = fb;
2945 if (intel_crtc->active && old_fb != fb)
2946 intel_wait_for_vblank(dev, intel_crtc->pipe);
2947 mutex_lock(&dev->struct_mutex);
2948 intel_unpin_fb_obj(old_obj);
2949 mutex_unlock(&dev->struct_mutex);
2952 mutex_lock(&dev->struct_mutex);
2953 intel_update_fbc(dev);
2954 mutex_unlock(&dev->struct_mutex);
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964 int pipe = intel_crtc->pipe;
2967 /* enable normal train */
2968 reg = FDI_TX_CTL(pipe);
2969 temp = I915_READ(reg);
2970 if (IS_IVYBRIDGE(dev)) {
2971 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974 temp &= ~FDI_LINK_TRAIN_NONE;
2975 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977 I915_WRITE(reg, temp);
2979 reg = FDI_RX_CTL(pipe);
2980 temp = I915_READ(reg);
2981 if (HAS_PCH_CPT(dev)) {
2982 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 temp &= ~FDI_LINK_TRAIN_NONE;
2986 temp |= FDI_LINK_TRAIN_NONE;
2988 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990 /* wait one idle pattern time */
2994 /* IVB wants error correction enabled */
2995 if (IS_IVYBRIDGE(dev))
2996 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997 FDI_FE_ERRC_ENABLE);
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 return crtc->base.enabled && crtc->active &&
3003 crtc->config.has_pch_encoder;
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 struct intel_crtc *pipe_B_crtc =
3010 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011 struct intel_crtc *pipe_C_crtc =
3012 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3016 * When everything is off disable fdi C so that we could enable fdi B
3017 * with all lanes. Note that we don't care about enabled pipes without
3018 * an enabled pch encoder.
3020 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021 !pipe_has_enabled_pch(pipe_C_crtc)) {
3022 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025 temp = I915_READ(SOUTH_CHICKEN1);
3026 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028 I915_WRITE(SOUTH_CHICKEN1, temp);
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
3039 u32 reg, temp, tries;
3041 /* FDI needs bits from pipe first */
3042 assert_pipe_enabled(dev_priv, pipe);
3044 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 reg = FDI_RX_IMR(pipe);
3047 temp = I915_READ(reg);
3048 temp &= ~FDI_RX_SYMBOL_LOCK;
3049 temp &= ~FDI_RX_BIT_LOCK;
3050 I915_WRITE(reg, temp);
3054 /* enable CPU FDI TX and PCH FDI RX */
3055 reg = FDI_TX_CTL(pipe);
3056 temp = I915_READ(reg);
3057 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059 temp &= ~FDI_LINK_TRAIN_NONE;
3060 temp |= FDI_LINK_TRAIN_PATTERN_1;
3061 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063 reg = FDI_RX_CTL(pipe);
3064 temp = I915_READ(reg);
3065 temp &= ~FDI_LINK_TRAIN_NONE;
3066 temp |= FDI_LINK_TRAIN_PATTERN_1;
3067 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3072 /* Ironlake workaround, enable clock pointer after FDI enable*/
3073 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075 FDI_RX_PHASE_SYNC_POINTER_EN);
3077 reg = FDI_RX_IIR(pipe);
3078 for (tries = 0; tries < 5; tries++) {
3079 temp = I915_READ(reg);
3080 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082 if ((temp & FDI_RX_BIT_LOCK)) {
3083 DRM_DEBUG_KMS("FDI train 1 done.\n");
3084 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3089 DRM_ERROR("FDI train 1 fail!\n");
3092 reg = FDI_TX_CTL(pipe);
3093 temp = I915_READ(reg);
3094 temp &= ~FDI_LINK_TRAIN_NONE;
3095 temp |= FDI_LINK_TRAIN_PATTERN_2;
3096 I915_WRITE(reg, temp);
3098 reg = FDI_RX_CTL(pipe);
3099 temp = I915_READ(reg);
3100 temp &= ~FDI_LINK_TRAIN_NONE;
3101 temp |= FDI_LINK_TRAIN_PATTERN_2;
3102 I915_WRITE(reg, temp);
3107 reg = FDI_RX_IIR(pipe);
3108 for (tries = 0; tries < 5; tries++) {
3109 temp = I915_READ(reg);
3110 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112 if (temp & FDI_RX_SYMBOL_LOCK) {
3113 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114 DRM_DEBUG_KMS("FDI train 2 done.\n");
3119 DRM_ERROR("FDI train 2 fail!\n");
3121 DRM_DEBUG_KMS("FDI train done\n");
3125 static const int snb_b_fdi_train_param[] = {
3126 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 struct drm_device *dev = crtc->dev;
3136 struct drm_i915_private *dev_priv = dev->dev_private;
3137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138 int pipe = intel_crtc->pipe;
3139 u32 reg, temp, i, retry;
3141 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 reg = FDI_RX_IMR(pipe);
3144 temp = I915_READ(reg);
3145 temp &= ~FDI_RX_SYMBOL_LOCK;
3146 temp &= ~FDI_RX_BIT_LOCK;
3147 I915_WRITE(reg, temp);
3152 /* enable CPU FDI TX and PCH FDI RX */
3153 reg = FDI_TX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157 temp &= ~FDI_LINK_TRAIN_NONE;
3158 temp |= FDI_LINK_TRAIN_PATTERN_1;
3159 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164 I915_WRITE(FDI_RX_MISC(pipe),
3165 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167 reg = FDI_RX_CTL(pipe);
3168 temp = I915_READ(reg);
3169 if (HAS_PCH_CPT(dev)) {
3170 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 temp &= ~FDI_LINK_TRAIN_NONE;
3174 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3181 for (i = 0; i < 4; i++) {
3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185 temp |= snb_b_fdi_train_param[i];
3186 I915_WRITE(reg, temp);
3191 for (retry = 0; retry < 5; retry++) {
3192 reg = FDI_RX_IIR(pipe);
3193 temp = I915_READ(reg);
3194 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195 if (temp & FDI_RX_BIT_LOCK) {
3196 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197 DRM_DEBUG_KMS("FDI train 1 done.\n");
3206 DRM_ERROR("FDI train 1 fail!\n");
3209 reg = FDI_TX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 temp &= ~FDI_LINK_TRAIN_NONE;
3212 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 I915_WRITE(reg, temp);
3220 reg = FDI_RX_CTL(pipe);
3221 temp = I915_READ(reg);
3222 if (HAS_PCH_CPT(dev)) {
3223 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 temp &= ~FDI_LINK_TRAIN_NONE;
3227 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 I915_WRITE(reg, temp);
3234 for (i = 0; i < 4; i++) {
3235 reg = FDI_TX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238 temp |= snb_b_fdi_train_param[i];
3239 I915_WRITE(reg, temp);
3244 for (retry = 0; retry < 5; retry++) {
3245 reg = FDI_RX_IIR(pipe);
3246 temp = I915_READ(reg);
3247 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248 if (temp & FDI_RX_SYMBOL_LOCK) {
3249 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250 DRM_DEBUG_KMS("FDI train 2 done.\n");
3259 DRM_ERROR("FDI train 2 fail!\n");
3261 DRM_DEBUG_KMS("FDI train done.\n");
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270 int pipe = intel_crtc->pipe;
3271 u32 reg, temp, i, j;
3273 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 reg = FDI_RX_IMR(pipe);
3276 temp = I915_READ(reg);
3277 temp &= ~FDI_RX_SYMBOL_LOCK;
3278 temp &= ~FDI_RX_BIT_LOCK;
3279 I915_WRITE(reg, temp);
3284 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285 I915_READ(FDI_RX_IIR(pipe)));
3287 /* Try each vswing and preemphasis setting twice before moving on */
3288 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289 /* disable first in case we need to retry */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293 temp &= ~FDI_TX_ENABLE;
3294 I915_WRITE(reg, temp);
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 temp &= ~FDI_LINK_TRAIN_AUTO;
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp &= ~FDI_RX_ENABLE;
3301 I915_WRITE(reg, temp);
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310 temp |= snb_b_fdi_train_param[j/2];
3311 temp |= FDI_COMPOSITE_SYNC;
3312 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314 I915_WRITE(FDI_RX_MISC(pipe),
3315 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317 reg = FDI_RX_CTL(pipe);
3318 temp = I915_READ(reg);
3319 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320 temp |= FDI_COMPOSITE_SYNC;
3321 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3324 udelay(1); /* should be 0.5us */
3326 for (i = 0; i < 4; i++) {
3327 reg = FDI_RX_IIR(pipe);
3328 temp = I915_READ(reg);
3329 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331 if (temp & FDI_RX_BIT_LOCK ||
3332 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3338 udelay(1); /* should be 0.5us */
3341 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350 I915_WRITE(reg, temp);
3352 reg = FDI_RX_CTL(pipe);
3353 temp = I915_READ(reg);
3354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356 I915_WRITE(reg, temp);
3359 udelay(2); /* should be 1.5us */
3361 for (i = 0; i < 4; i++) {
3362 reg = FDI_RX_IIR(pipe);
3363 temp = I915_READ(reg);
3364 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366 if (temp & FDI_RX_SYMBOL_LOCK ||
3367 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3373 udelay(2); /* should be 1.5us */
3376 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3380 DRM_DEBUG_KMS("FDI train done.\n");
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 struct drm_device *dev = intel_crtc->base.dev;
3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 int pipe = intel_crtc->pipe;
3391 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392 reg = FDI_RX_CTL(pipe);
3393 temp = I915_READ(reg);
3394 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3402 /* Switch from Rawclk to PCDclk */
3403 temp = I915_READ(reg);
3404 I915_WRITE(reg, temp | FDI_PCDCLK);
3409 /* Enable CPU FDI TX PLL, always on for Ironlake */
3410 reg = FDI_TX_CTL(pipe);
3411 temp = I915_READ(reg);
3412 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 struct drm_device *dev = intel_crtc->base.dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 int pipe = intel_crtc->pipe;
3427 /* Switch from PCDclk to Rawclk */
3428 reg = FDI_RX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432 /* Disable CPU FDI TX PLL */
3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
3442 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444 /* Wait for the clocks to turn off. */
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454 int pipe = intel_crtc->pipe;
3457 /* disable CPU FDI tx and PCH FDI rx */
3458 reg = FDI_TX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3463 reg = FDI_RX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~(0x7 << 16);
3466 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3472 /* Ironlake workaround, disable clock pointer after downing FDI */
3473 if (HAS_PCH_IBX(dev))
3474 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476 /* still set train pattern 1 */
3477 reg = FDI_TX_CTL(pipe);
3478 temp = I915_READ(reg);
3479 temp &= ~FDI_LINK_TRAIN_NONE;
3480 temp |= FDI_LINK_TRAIN_PATTERN_1;
3481 I915_WRITE(reg, temp);
3483 reg = FDI_RX_CTL(pipe);
3484 temp = I915_READ(reg);
3485 if (HAS_PCH_CPT(dev)) {
3486 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 /* BPC in FDI rx is consistent with that in PIPECONF */
3493 temp &= ~(0x07 << 16);
3494 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495 I915_WRITE(reg, temp);
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 struct intel_crtc *crtc;
3505 /* Note that we don't need to be called with mode_config.lock here
3506 * as our list of CRTC objects is static for the lifetime of the
3507 * device and so cannot disappear as we iterate. Similarly, we can
3508 * happily treat the predicates as racy, atomic checks as userspace
3509 * cannot claim and pin a new fb without at least acquring the
3510 * struct_mutex and so serialising with us.
3512 for_each_intel_crtc(dev, crtc) {
3513 if (atomic_read(&crtc->unpin_work_count) == 0)
3516 if (crtc->unpin_work)
3517 intel_wait_for_vblank(dev, crtc->pipe);
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530 /* ensure that the unpin work is consistent wrt ->pending. */
3532 intel_crtc->unpin_work = NULL;
3535 drm_send_vblank_event(intel_crtc->base.dev,
3539 drm_crtc_vblank_put(&intel_crtc->base);
3541 wake_up_all(&dev_priv->pending_flip_queue);
3542 queue_work(dev_priv->wq, &work->work);
3544 trace_i915_flip_complete(intel_crtc->plane,
3545 work->pending_flip_obj);
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 struct drm_device *dev = crtc->dev;
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3553 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555 !intel_crtc_has_pending_flip(crtc),
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559 spin_lock_irq(&dev->event_lock);
3560 if (intel_crtc->unpin_work) {
3561 WARN_ONCE(1, "Removing stuck page flip\n");
3562 page_flip_completed(intel_crtc);
3564 spin_unlock_irq(&dev->event_lock);
3567 if (crtc->primary->fb) {
3568 mutex_lock(&dev->struct_mutex);
3569 intel_finish_fb(crtc->primary->fb);
3570 mutex_unlock(&dev->struct_mutex);
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 struct drm_device *dev = crtc->dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3583 mutex_lock(&dev_priv->dpio_lock);
3585 /* It is necessary to ungate the pixclk gate prior to programming
3586 * the divisors, and gate it back when it is done.
3588 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590 /* Disable SSCCTL */
3591 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3596 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597 if (clock == 20000) {
3602 /* The iCLK virtual clock root frequency is in MHz,
3603 * but the adjusted_mode->crtc_clock in in KHz. To get the
3604 * divisors, it is necessary to divide one by another, so we
3605 * convert the virtual clock precision to KHz here for higher
3608 u32 iclk_virtual_root_freq = 172800 * 1000;
3609 u32 iclk_pi_range = 64;
3610 u32 desired_divisor, msb_divisor_value, pi_value;
3612 desired_divisor = (iclk_virtual_root_freq / clock);
3613 msb_divisor_value = desired_divisor / iclk_pi_range;
3614 pi_value = desired_divisor % iclk_pi_range;
3617 divsel = msb_divisor_value - 2;
3618 phaseinc = pi_value;
3621 /* This should not happen with any sane values */
3622 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3634 /* Program SSCDIVINTPHASE6 */
3635 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644 /* Program SSCAUXDIV */
3645 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650 /* Enable modulator and associated divider */
3651 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652 temp &= ~SBI_SSCCTL_DISABLE;
3653 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655 /* Wait for initialization time */
3658 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660 mutex_unlock(&dev_priv->dpio_lock);
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664 enum pipe pch_transcoder)
3666 struct drm_device *dev = crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671 I915_READ(HTOTAL(cpu_transcoder)));
3672 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673 I915_READ(HBLANK(cpu_transcoder)));
3674 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675 I915_READ(HSYNC(cpu_transcoder)));
3677 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678 I915_READ(VTOTAL(cpu_transcoder)));
3679 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680 I915_READ(VBLANK(cpu_transcoder)));
3681 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682 I915_READ(VSYNC(cpu_transcoder)));
3683 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3692 temp = I915_READ(SOUTH_CHICKEN1);
3693 if (temp & FDI_BC_BIFURCATION_SELECT)
3696 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699 temp |= FDI_BC_BIFURCATION_SELECT;
3700 DRM_DEBUG_KMS("enabling fdi C rx\n");
3701 I915_WRITE(SOUTH_CHICKEN1, temp);
3702 POSTING_READ(SOUTH_CHICKEN1);
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 struct drm_device *dev = intel_crtc->base.dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3710 switch (intel_crtc->pipe) {
3714 if (intel_crtc->config.fdi_lanes > 2)
3715 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 cpt_enable_fdi_bc_bifurcation(dev);
3721 cpt_enable_fdi_bc_bifurcation(dev);
3730 * Enable PCH resources required for PCH ports:
3732 * - FDI training & RX/TX
3733 * - update transcoder timings
3734 * - DP transcoding bits
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742 int pipe = intel_crtc->pipe;
3745 assert_pch_transcoder_disabled(dev_priv, pipe);
3747 if (IS_IVYBRIDGE(dev))
3748 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750 /* Write the TU size bits before fdi link training, so that error
3751 * detection works. */
3752 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755 /* For PCH output, training FDI link */
3756 dev_priv->display.fdi_link_train(crtc);
3758 /* We need to program the right clock selection before writing the pixel
3759 * mutliplier into the DPLL. */
3760 if (HAS_PCH_CPT(dev)) {
3763 temp = I915_READ(PCH_DPLL_SEL);
3764 temp |= TRANS_DPLL_ENABLE(pipe);
3765 sel = TRANS_DPLLB_SEL(pipe);
3766 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3770 I915_WRITE(PCH_DPLL_SEL, temp);
3773 /* XXX: pch pll's can be enabled any time before we enable the PCH
3774 * transcoder, and we actually should do this to not upset any PCH
3775 * transcoder that already use the clock when we share it.
3777 * Note that enable_shared_dpll tries to do the right thing, but
3778 * get_shared_dpll unconditionally resets the pll - we need that to have
3779 * the right LVDS enable sequence. */
3780 intel_enable_shared_dpll(intel_crtc);
3782 /* set transcoder timing, panel must allow it */
3783 assert_panel_unlocked(dev_priv, pipe);
3784 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786 intel_fdi_normal_train(crtc);
3788 /* For PCH DP, enable TRANS_DP_CTL */
3789 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791 reg = TRANS_DP_CTL(pipe);
3792 temp = I915_READ(reg);
3793 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794 TRANS_DP_SYNC_MASK |
3796 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797 TRANS_DP_ENH_FRAMING);
3798 temp |= bpc << 9; /* same format but at 11:9 */
3800 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805 switch (intel_trans_dp_port_sel(crtc)) {
3807 temp |= TRANS_DP_PORT_SEL_B;
3810 temp |= TRANS_DP_PORT_SEL_C;
3813 temp |= TRANS_DP_PORT_SEL_D;
3819 I915_WRITE(reg, temp);
3822 ironlake_enable_pch_transcoder(dev_priv, pipe);
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3832 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834 lpt_program_iclkip(crtc);
3836 /* Set transcoder timing. */
3837 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3849 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3850 WARN(1, "bad %s crtc mask\n", pll->name);
3854 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3855 if (pll->config.crtc_mask == 0) {
3857 WARN_ON(pll->active);
3860 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3863 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3865 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3866 struct intel_shared_dpll *pll;
3867 enum intel_dpll_id i;
3869 if (HAS_PCH_IBX(dev_priv->dev)) {
3870 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3871 i = (enum intel_dpll_id) crtc->pipe;
3872 pll = &dev_priv->shared_dplls[i];
3874 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3875 crtc->base.base.id, pll->name);
3877 WARN_ON(pll->new_config->crtc_mask);
3882 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3883 pll = &dev_priv->shared_dplls[i];
3885 /* Only want to check enabled timings first */
3886 if (pll->new_config->crtc_mask == 0)
3889 if (memcmp(&crtc->new_config->dpll_hw_state,
3890 &pll->new_config->hw_state,
3891 sizeof(pll->new_config->hw_state)) == 0) {
3892 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3893 crtc->base.base.id, pll->name,
3894 pll->new_config->crtc_mask,
3900 /* Ok no matching timings, maybe there's a free one? */
3901 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3902 pll = &dev_priv->shared_dplls[i];
3903 if (pll->new_config->crtc_mask == 0) {
3904 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3905 crtc->base.base.id, pll->name);
3913 if (pll->new_config->crtc_mask == 0)
3914 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3916 crtc->new_config->shared_dpll = i;
3917 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3918 pipe_name(crtc->pipe));
3920 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3926 * intel_shared_dpll_start_config - start a new PLL staged config
3927 * @dev_priv: DRM device
3928 * @clear_pipes: mask of pipes that will have their PLLs freed
3930 * Starts a new PLL staged config, copying the current config but
3931 * releasing the references of pipes specified in clear_pipes.
3933 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3934 unsigned clear_pipes)
3936 struct intel_shared_dpll *pll;
3937 enum intel_dpll_id i;
3939 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940 pll = &dev_priv->shared_dplls[i];
3942 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944 if (!pll->new_config)
3947 pll->new_config->crtc_mask &= ~clear_pipes;
3954 pll = &dev_priv->shared_dplls[i];
3955 pll->new_config = NULL;
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3963 struct intel_shared_dpll *pll;
3964 enum intel_dpll_id i;
3966 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967 pll = &dev_priv->shared_dplls[i];
3969 WARN_ON(pll->new_config == &pll->config);
3971 pll->config = *pll->new_config;
3972 kfree(pll->new_config);
3973 pll->new_config = NULL;
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3979 struct intel_shared_dpll *pll;
3980 enum intel_dpll_id i;
3982 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983 pll = &dev_priv->shared_dplls[i];
3985 WARN_ON(pll->new_config == &pll->config);
3987 kfree(pll->new_config);
3988 pll->new_config = NULL;
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3994 struct drm_i915_private *dev_priv = dev->dev_private;
3995 int dslreg = PIPEDSL(pipe);
3998 temp = I915_READ(dslreg);
4000 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001 if (wait_for(I915_READ(dslreg) != temp, 5))
4002 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4006 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4008 struct drm_device *dev = crtc->base.dev;
4009 struct drm_i915_private *dev_priv = dev->dev_private;
4010 int pipe = crtc->pipe;
4012 if (crtc->config.pch_pfit.enabled) {
4013 /* Force use of hard-coded filter coefficients
4014 * as some pre-programmed values are broken,
4017 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4018 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4019 PF_PIPE_SEL_IVB(pipe));
4021 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4022 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4023 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4027 static void intel_enable_planes(struct drm_crtc *crtc)
4029 struct drm_device *dev = crtc->dev;
4030 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4031 struct drm_plane *plane;
4032 struct intel_plane *intel_plane;
4034 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4035 intel_plane = to_intel_plane(plane);
4036 if (intel_plane->pipe == pipe)
4037 intel_plane_restore(&intel_plane->base);
4041 static void intel_disable_planes(struct drm_crtc *crtc)
4043 struct drm_device *dev = crtc->dev;
4044 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4045 struct drm_plane *plane;
4046 struct intel_plane *intel_plane;
4048 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4049 intel_plane = to_intel_plane(plane);
4050 if (intel_plane->pipe == pipe)
4051 intel_plane_disable(&intel_plane->base);
4055 void hsw_enable_ips(struct intel_crtc *crtc)
4057 struct drm_device *dev = crtc->base.dev;
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4060 if (!crtc->config.ips_enabled)
4063 /* We can only enable IPS after we enable a plane and wait for a vblank */
4064 intel_wait_for_vblank(dev, crtc->pipe);
4066 assert_plane_enabled(dev_priv, crtc->plane);
4067 if (IS_BROADWELL(dev)) {
4068 mutex_lock(&dev_priv->rps.hw_lock);
4069 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4070 mutex_unlock(&dev_priv->rps.hw_lock);
4071 /* Quoting Art Runyan: "its not safe to expect any particular
4072 * value in IPS_CTL bit 31 after enabling IPS through the
4073 * mailbox." Moreover, the mailbox may return a bogus state,
4074 * so we need to just enable it and continue on.
4077 I915_WRITE(IPS_CTL, IPS_ENABLE);
4078 /* The bit only becomes 1 in the next vblank, so this wait here
4079 * is essentially intel_wait_for_vblank. If we don't have this
4080 * and don't wait for vblanks until the end of crtc_enable, then
4081 * the HW state readout code will complain that the expected
4082 * IPS_CTL value is not the one we read. */
4083 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4084 DRM_ERROR("Timed out waiting for IPS enable\n");
4088 void hsw_disable_ips(struct intel_crtc *crtc)
4090 struct drm_device *dev = crtc->base.dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4093 if (!crtc->config.ips_enabled)
4096 assert_plane_enabled(dev_priv, crtc->plane);
4097 if (IS_BROADWELL(dev)) {
4098 mutex_lock(&dev_priv->rps.hw_lock);
4099 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4100 mutex_unlock(&dev_priv->rps.hw_lock);
4101 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4102 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4103 DRM_ERROR("Timed out waiting for IPS disable\n");
4105 I915_WRITE(IPS_CTL, 0);
4106 POSTING_READ(IPS_CTL);
4109 /* We need to wait for a vblank before we can disable the plane. */
4110 intel_wait_for_vblank(dev, crtc->pipe);
4113 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4114 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119 enum pipe pipe = intel_crtc->pipe;
4120 int palreg = PALETTE(pipe);
4122 bool reenable_ips = false;
4124 /* The clocks have to be on to load the palette. */
4125 if (!crtc->enabled || !intel_crtc->active)
4128 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4129 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4130 assert_dsi_pll_enabled(dev_priv);
4132 assert_pll_enabled(dev_priv, pipe);
4135 /* use legacy palette for Ironlake */
4136 if (!HAS_GMCH_DISPLAY(dev))
4137 palreg = LGC_PALETTE(pipe);
4139 /* Workaround : Do not read or write the pipe palette/gamma data while
4140 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4142 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4143 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4144 GAMMA_MODE_MODE_SPLIT)) {
4145 hsw_disable_ips(intel_crtc);
4146 reenable_ips = true;
4149 for (i = 0; i < 256; i++) {
4150 I915_WRITE(palreg + 4 * i,
4151 (intel_crtc->lut_r[i] << 16) |
4152 (intel_crtc->lut_g[i] << 8) |
4153 intel_crtc->lut_b[i]);
4157 hsw_enable_ips(intel_crtc);
4160 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4162 if (!enable && intel_crtc->overlay) {
4163 struct drm_device *dev = intel_crtc->base.dev;
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4166 mutex_lock(&dev->struct_mutex);
4167 dev_priv->mm.interruptible = false;
4168 (void) intel_overlay_switch_off(intel_crtc->overlay);
4169 dev_priv->mm.interruptible = true;
4170 mutex_unlock(&dev->struct_mutex);
4173 /* Let userspace switch the overlay on again. In most cases userspace
4174 * has to recompute where to put it anyway.
4178 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4180 struct drm_device *dev = crtc->dev;
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 int pipe = intel_crtc->pipe;
4184 intel_enable_primary_hw_plane(crtc->primary, crtc);
4185 intel_enable_planes(crtc);
4186 intel_crtc_update_cursor(crtc, true);
4187 intel_crtc_dpms_overlay(intel_crtc, true);
4189 hsw_enable_ips(intel_crtc);
4191 mutex_lock(&dev->struct_mutex);
4192 intel_update_fbc(dev);
4193 mutex_unlock(&dev->struct_mutex);
4196 * FIXME: Once we grow proper nuclear flip support out of this we need
4197 * to compute the mask of flip planes precisely. For the time being
4198 * consider this a flip from a NULL plane.
4200 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4203 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 int pipe = intel_crtc->pipe;
4209 int plane = intel_crtc->plane;
4211 intel_crtc_wait_for_pending_flips(crtc);
4213 if (dev_priv->fbc.plane == plane)
4214 intel_disable_fbc(dev);
4216 hsw_disable_ips(intel_crtc);
4218 intel_crtc_dpms_overlay(intel_crtc, false);
4219 intel_crtc_update_cursor(crtc, false);
4220 intel_disable_planes(crtc);
4221 intel_disable_primary_hw_plane(crtc->primary, crtc);
4224 * FIXME: Once we grow proper nuclear flip support out of this we need
4225 * to compute the mask of flip planes precisely. For the time being
4226 * consider this a flip to a NULL plane.
4228 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4231 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236 struct intel_encoder *encoder;
4237 int pipe = intel_crtc->pipe;
4239 WARN_ON(!crtc->enabled);
4241 if (intel_crtc->active)
4244 if (intel_crtc->config.has_pch_encoder)
4245 intel_prepare_shared_dpll(intel_crtc);
4247 if (intel_crtc->config.has_dp_encoder)
4248 intel_dp_set_m_n(intel_crtc);
4250 intel_set_pipe_timings(intel_crtc);
4252 if (intel_crtc->config.has_pch_encoder) {
4253 intel_cpu_transcoder_set_m_n(intel_crtc,
4254 &intel_crtc->config.fdi_m_n, NULL);
4257 ironlake_set_pipeconf(crtc);
4259 intel_crtc->active = true;
4261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4262 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4264 for_each_encoder_on_crtc(dev, crtc, encoder)
4265 if (encoder->pre_enable)
4266 encoder->pre_enable(encoder);
4268 if (intel_crtc->config.has_pch_encoder) {
4269 /* Note: FDI PLL enabling _must_ be done before we enable the
4270 * cpu pipes, hence this is separate from all the other fdi/pch
4272 ironlake_fdi_pll_enable(intel_crtc);
4274 assert_fdi_tx_disabled(dev_priv, pipe);
4275 assert_fdi_rx_disabled(dev_priv, pipe);
4278 ironlake_pfit_enable(intel_crtc);
4281 * On ILK+ LUT must be loaded before the pipe is running but with
4284 intel_crtc_load_lut(crtc);
4286 intel_update_watermarks(crtc);
4287 intel_enable_pipe(intel_crtc);
4289 if (intel_crtc->config.has_pch_encoder)
4290 ironlake_pch_enable(crtc);
4292 for_each_encoder_on_crtc(dev, crtc, encoder)
4293 encoder->enable(encoder);
4295 if (HAS_PCH_CPT(dev))
4296 cpt_verify_modeset(dev, intel_crtc->pipe);
4298 assert_vblank_disabled(crtc);
4299 drm_crtc_vblank_on(crtc);
4301 intel_crtc_enable_planes(crtc);
4304 /* IPS only exists on ULT machines and is tied to pipe A. */
4305 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4307 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4311 * This implements the workaround described in the "notes" section of the mode
4312 * set sequence documentation. When going from no pipes or single pipe to
4313 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4314 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4316 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4318 struct drm_device *dev = crtc->base.dev;
4319 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4321 /* We want to get the other_active_crtc only if there's only 1 other
4323 for_each_intel_crtc(dev, crtc_it) {
4324 if (!crtc_it->active || crtc_it == crtc)
4327 if (other_active_crtc)
4330 other_active_crtc = crtc_it;
4332 if (!other_active_crtc)
4335 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4336 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4339 static void haswell_crtc_enable(struct drm_crtc *crtc)
4341 struct drm_device *dev = crtc->dev;
4342 struct drm_i915_private *dev_priv = dev->dev_private;
4343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344 struct intel_encoder *encoder;
4345 int pipe = intel_crtc->pipe;
4347 WARN_ON(!crtc->enabled);
4349 if (intel_crtc->active)
4352 if (intel_crtc_to_shared_dpll(intel_crtc))
4353 intel_enable_shared_dpll(intel_crtc);
4355 if (intel_crtc->config.has_dp_encoder)
4356 intel_dp_set_m_n(intel_crtc);
4358 intel_set_pipe_timings(intel_crtc);
4360 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4361 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4362 intel_crtc->config.pixel_multiplier - 1);
4365 if (intel_crtc->config.has_pch_encoder) {
4366 intel_cpu_transcoder_set_m_n(intel_crtc,
4367 &intel_crtc->config.fdi_m_n, NULL);
4370 haswell_set_pipeconf(crtc);
4372 intel_set_pipe_csc(crtc);
4374 intel_crtc->active = true;
4376 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4377 for_each_encoder_on_crtc(dev, crtc, encoder)
4378 if (encoder->pre_enable)
4379 encoder->pre_enable(encoder);
4381 if (intel_crtc->config.has_pch_encoder) {
4382 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4384 dev_priv->display.fdi_link_train(crtc);
4387 intel_ddi_enable_pipe_clock(intel_crtc);
4389 ironlake_pfit_enable(intel_crtc);
4392 * On ILK+ LUT must be loaded before the pipe is running but with
4395 intel_crtc_load_lut(crtc);
4397 intel_ddi_set_pipe_settings(crtc);
4398 intel_ddi_enable_transcoder_func(crtc);
4400 intel_update_watermarks(crtc);
4401 intel_enable_pipe(intel_crtc);
4403 if (intel_crtc->config.has_pch_encoder)
4404 lpt_pch_enable(crtc);
4406 if (intel_crtc->config.dp_encoder_is_mst)
4407 intel_ddi_set_vc_payload_alloc(crtc, true);
4409 for_each_encoder_on_crtc(dev, crtc, encoder) {
4410 encoder->enable(encoder);
4411 intel_opregion_notify_encoder(encoder, true);
4414 assert_vblank_disabled(crtc);
4415 drm_crtc_vblank_on(crtc);
4417 /* If we change the relative order between pipe/planes enabling, we need
4418 * to change the workaround. */
4419 haswell_mode_set_planes_workaround(intel_crtc);
4420 intel_crtc_enable_planes(crtc);
4423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4425 struct drm_device *dev = crtc->base.dev;
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 int pipe = crtc->pipe;
4429 /* To avoid upsetting the power well on haswell only disable the pfit if
4430 * it's in use. The hw state code will make sure we get this right. */
4431 if (crtc->config.pch_pfit.enabled) {
4432 I915_WRITE(PF_CTL(pipe), 0);
4433 I915_WRITE(PF_WIN_POS(pipe), 0);
4434 I915_WRITE(PF_WIN_SZ(pipe), 0);
4438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4440 struct drm_device *dev = crtc->dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443 struct intel_encoder *encoder;
4444 int pipe = intel_crtc->pipe;
4447 if (!intel_crtc->active)
4450 intel_crtc_disable_planes(crtc);
4452 drm_crtc_vblank_off(crtc);
4453 assert_vblank_disabled(crtc);
4455 for_each_encoder_on_crtc(dev, crtc, encoder)
4456 encoder->disable(encoder);
4458 if (intel_crtc->config.has_pch_encoder)
4459 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4461 intel_disable_pipe(intel_crtc);
4463 ironlake_pfit_disable(intel_crtc);
4465 for_each_encoder_on_crtc(dev, crtc, encoder)
4466 if (encoder->post_disable)
4467 encoder->post_disable(encoder);
4469 if (intel_crtc->config.has_pch_encoder) {
4470 ironlake_fdi_disable(crtc);
4472 ironlake_disable_pch_transcoder(dev_priv, pipe);
4473 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4475 if (HAS_PCH_CPT(dev)) {
4476 /* disable TRANS_DP_CTL */
4477 reg = TRANS_DP_CTL(pipe);
4478 temp = I915_READ(reg);
4479 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4480 TRANS_DP_PORT_SEL_MASK);
4481 temp |= TRANS_DP_PORT_SEL_NONE;
4482 I915_WRITE(reg, temp);
4484 /* disable DPLL_SEL */
4485 temp = I915_READ(PCH_DPLL_SEL);
4486 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4487 I915_WRITE(PCH_DPLL_SEL, temp);
4490 /* disable PCH DPLL */
4491 intel_disable_shared_dpll(intel_crtc);
4493 ironlake_fdi_pll_disable(intel_crtc);
4496 intel_crtc->active = false;
4497 intel_update_watermarks(crtc);
4499 mutex_lock(&dev->struct_mutex);
4500 intel_update_fbc(dev);
4501 mutex_unlock(&dev->struct_mutex);
4504 static void haswell_crtc_disable(struct drm_crtc *crtc)
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509 struct intel_encoder *encoder;
4510 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4512 if (!intel_crtc->active)
4515 intel_crtc_disable_planes(crtc);
4517 drm_crtc_vblank_off(crtc);
4518 assert_vblank_disabled(crtc);
4520 for_each_encoder_on_crtc(dev, crtc, encoder) {
4521 intel_opregion_notify_encoder(encoder, false);
4522 encoder->disable(encoder);
4525 if (intel_crtc->config.has_pch_encoder)
4526 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4528 intel_disable_pipe(intel_crtc);
4530 if (intel_crtc->config.dp_encoder_is_mst)
4531 intel_ddi_set_vc_payload_alloc(crtc, false);
4533 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4535 ironlake_pfit_disable(intel_crtc);
4537 intel_ddi_disable_pipe_clock(intel_crtc);
4539 if (intel_crtc->config.has_pch_encoder) {
4540 lpt_disable_pch_transcoder(dev_priv);
4541 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4543 intel_ddi_fdi_disable(crtc);
4546 for_each_encoder_on_crtc(dev, crtc, encoder)
4547 if (encoder->post_disable)
4548 encoder->post_disable(encoder);
4550 intel_crtc->active = false;
4551 intel_update_watermarks(crtc);
4553 mutex_lock(&dev->struct_mutex);
4554 intel_update_fbc(dev);
4555 mutex_unlock(&dev->struct_mutex);
4557 if (intel_crtc_to_shared_dpll(intel_crtc))
4558 intel_disable_shared_dpll(intel_crtc);
4561 static void ironlake_crtc_off(struct drm_crtc *crtc)
4563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4564 intel_put_shared_dpll(intel_crtc);
4568 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4570 struct drm_device *dev = crtc->base.dev;
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 struct intel_crtc_config *pipe_config = &crtc->config;
4574 if (!crtc->config.gmch_pfit.control)
4578 * The panel fitter should only be adjusted whilst the pipe is disabled,
4579 * according to register description and PRM.
4581 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4582 assert_pipe_disabled(dev_priv, crtc->pipe);
4584 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4585 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4587 /* Border color in case we don't scale up to the full screen. Black by
4588 * default, change to something else for debugging. */
4589 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4592 static enum intel_display_power_domain port_to_power_domain(enum port port)
4596 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4598 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4600 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4602 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4605 return POWER_DOMAIN_PORT_OTHER;
4609 #define for_each_power_domain(domain, mask) \
4610 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4611 if ((1 << (domain)) & (mask))
4613 enum intel_display_power_domain
4614 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4616 struct drm_device *dev = intel_encoder->base.dev;
4617 struct intel_digital_port *intel_dig_port;
4619 switch (intel_encoder->type) {
4620 case INTEL_OUTPUT_UNKNOWN:
4621 /* Only DDI platforms should ever use this output type */
4622 WARN_ON_ONCE(!HAS_DDI(dev));
4623 case INTEL_OUTPUT_DISPLAYPORT:
4624 case INTEL_OUTPUT_HDMI:
4625 case INTEL_OUTPUT_EDP:
4626 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4627 return port_to_power_domain(intel_dig_port->port);
4628 case INTEL_OUTPUT_DP_MST:
4629 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4630 return port_to_power_domain(intel_dig_port->port);
4631 case INTEL_OUTPUT_ANALOG:
4632 return POWER_DOMAIN_PORT_CRT;
4633 case INTEL_OUTPUT_DSI:
4634 return POWER_DOMAIN_PORT_DSI;
4636 return POWER_DOMAIN_PORT_OTHER;
4640 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4642 struct drm_device *dev = crtc->dev;
4643 struct intel_encoder *intel_encoder;
4644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645 enum pipe pipe = intel_crtc->pipe;
4647 enum transcoder transcoder;
4649 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4651 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4652 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4653 if (intel_crtc->config.pch_pfit.enabled ||
4654 intel_crtc->config.pch_pfit.force_thru)
4655 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4657 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4658 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4663 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4667 struct intel_crtc *crtc;
4670 * First get all needed power domains, then put all unneeded, to avoid
4671 * any unnecessary toggling of the power wells.
4673 for_each_intel_crtc(dev, crtc) {
4674 enum intel_display_power_domain domain;
4676 if (!crtc->base.enabled)
4679 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4681 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4682 intel_display_power_get(dev_priv, domain);
4685 for_each_intel_crtc(dev, crtc) {
4686 enum intel_display_power_domain domain;
4688 for_each_power_domain(domain, crtc->enabled_power_domains)
4689 intel_display_power_put(dev_priv, domain);
4691 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4694 intel_display_set_init_power(dev_priv, false);
4697 /* returns HPLL frequency in kHz */
4698 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4700 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4702 /* Obtain SKU information */
4703 mutex_lock(&dev_priv->dpio_lock);
4704 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4705 CCK_FUSE_HPLL_FREQ_MASK;
4706 mutex_unlock(&dev_priv->dpio_lock);
4708 return vco_freq[hpll_freq] * 1000;
4711 static void vlv_update_cdclk(struct drm_device *dev)
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4715 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4716 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4717 dev_priv->vlv_cdclk_freq);
4720 * Program the gmbus_freq based on the cdclk frequency.
4721 * BSpec erroneously claims we should aim for 4MHz, but
4722 * in fact 1MHz is the correct frequency.
4724 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4727 /* Adjust CDclk dividers to allow high res or save power if possible */
4728 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4733 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4735 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4737 else if (cdclk == 266667)
4742 mutex_lock(&dev_priv->rps.hw_lock);
4743 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4744 val &= ~DSPFREQGUAR_MASK;
4745 val |= (cmd << DSPFREQGUAR_SHIFT);
4746 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4747 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4748 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4750 DRM_ERROR("timed out waiting for CDclk change\n");
4752 mutex_unlock(&dev_priv->rps.hw_lock);
4754 if (cdclk == 400000) {
4757 vco = valleyview_get_vco(dev_priv);
4758 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4760 mutex_lock(&dev_priv->dpio_lock);
4761 /* adjust cdclk divider */
4762 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4763 val &= ~DISPLAY_FREQUENCY_VALUES;
4765 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4767 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4768 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4770 DRM_ERROR("timed out waiting for CDclk change\n");
4771 mutex_unlock(&dev_priv->dpio_lock);
4774 mutex_lock(&dev_priv->dpio_lock);
4775 /* adjust self-refresh exit latency value */
4776 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4780 * For high bandwidth configs, we set a higher latency in the bunit
4781 * so that the core display fetch happens in time to avoid underruns.
4783 if (cdclk == 400000)
4784 val |= 4500 / 250; /* 4.5 usec */
4786 val |= 3000 / 250; /* 3.0 usec */
4787 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4788 mutex_unlock(&dev_priv->dpio_lock);
4790 vlv_update_cdclk(dev);
4793 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4798 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4819 mutex_lock(&dev_priv->rps.hw_lock);
4820 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4821 val &= ~DSPFREQGUAR_MASK_CHV;
4822 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4823 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4824 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4825 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4827 DRM_ERROR("timed out waiting for CDclk change\n");
4829 mutex_unlock(&dev_priv->rps.hw_lock);
4831 vlv_update_cdclk(dev);
4834 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4837 int vco = valleyview_get_vco(dev_priv);
4838 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4840 /* FIXME: Punit isn't quite ready yet */
4841 if (IS_CHERRYVIEW(dev_priv->dev))
4845 * Really only a few cases to deal with, as only 4 CDclks are supported:
4848 * 320/333MHz (depends on HPLL freq)
4850 * So we check to see whether we're above 90% of the lower bin and
4853 * We seem to get an unstable or solid color picture at 200MHz.
4854 * Not sure what's wrong. For now use 200MHz only when all pipes
4857 if (max_pixclk > freq_320*9/10)
4859 else if (max_pixclk > 266667*9/10)
4861 else if (max_pixclk > 0)
4867 /* compute the max pixel clock for new configuration */
4868 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4870 struct drm_device *dev = dev_priv->dev;
4871 struct intel_crtc *intel_crtc;
4874 for_each_intel_crtc(dev, intel_crtc) {
4875 if (intel_crtc->new_enabled)
4876 max_pixclk = max(max_pixclk,
4877 intel_crtc->new_config->adjusted_mode.crtc_clock);
4883 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4884 unsigned *prepare_pipes)
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct intel_crtc *intel_crtc;
4888 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4890 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4891 dev_priv->vlv_cdclk_freq)
4894 /* disable/enable all currently active pipes while we change cdclk */
4895 for_each_intel_crtc(dev, intel_crtc)
4896 if (intel_crtc->base.enabled)
4897 *prepare_pipes |= (1 << intel_crtc->pipe);
4900 static void valleyview_modeset_global_resources(struct drm_device *dev)
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4904 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4906 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4907 if (IS_CHERRYVIEW(dev))
4908 cherryview_set_cdclk(dev, req_cdclk);
4910 valleyview_set_cdclk(dev, req_cdclk);
4913 modeset_update_crtc_power_domains(dev);
4916 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4918 struct drm_device *dev = crtc->dev;
4919 struct drm_i915_private *dev_priv = to_i915(dev);
4920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 struct intel_encoder *encoder;
4922 int pipe = intel_crtc->pipe;
4925 WARN_ON(!crtc->enabled);
4927 if (intel_crtc->active)
4930 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4933 if (IS_CHERRYVIEW(dev))
4934 chv_prepare_pll(intel_crtc, &intel_crtc->config);
4936 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4939 if (intel_crtc->config.has_dp_encoder)
4940 intel_dp_set_m_n(intel_crtc);
4942 intel_set_pipe_timings(intel_crtc);
4944 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4947 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4948 I915_WRITE(CHV_CANVAS(pipe), 0);
4951 i9xx_set_pipeconf(intel_crtc);
4953 intel_crtc->active = true;
4955 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957 for_each_encoder_on_crtc(dev, crtc, encoder)
4958 if (encoder->pre_pll_enable)
4959 encoder->pre_pll_enable(encoder);
4962 if (IS_CHERRYVIEW(dev))
4963 chv_enable_pll(intel_crtc, &intel_crtc->config);
4965 vlv_enable_pll(intel_crtc, &intel_crtc->config);
4968 for_each_encoder_on_crtc(dev, crtc, encoder)
4969 if (encoder->pre_enable)
4970 encoder->pre_enable(encoder);
4972 i9xx_pfit_enable(intel_crtc);
4974 intel_crtc_load_lut(crtc);
4976 intel_update_watermarks(crtc);
4977 intel_enable_pipe(intel_crtc);
4979 for_each_encoder_on_crtc(dev, crtc, encoder)
4980 encoder->enable(encoder);
4982 assert_vblank_disabled(crtc);
4983 drm_crtc_vblank_on(crtc);
4985 intel_crtc_enable_planes(crtc);
4987 /* Underruns don't raise interrupts, so check manually. */
4988 i9xx_check_fifo_underruns(dev_priv);
4991 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4993 struct drm_device *dev = crtc->base.dev;
4994 struct drm_i915_private *dev_priv = dev->dev_private;
4996 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4997 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
5000 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5002 struct drm_device *dev = crtc->dev;
5003 struct drm_i915_private *dev_priv = to_i915(dev);
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005 struct intel_encoder *encoder;
5006 int pipe = intel_crtc->pipe;
5008 WARN_ON(!crtc->enabled);
5010 if (intel_crtc->active)
5013 i9xx_set_pll_dividers(intel_crtc);
5015 if (intel_crtc->config.has_dp_encoder)
5016 intel_dp_set_m_n(intel_crtc);
5018 intel_set_pipe_timings(intel_crtc);
5020 i9xx_set_pipeconf(intel_crtc);
5022 intel_crtc->active = true;
5025 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5027 for_each_encoder_on_crtc(dev, crtc, encoder)
5028 if (encoder->pre_enable)
5029 encoder->pre_enable(encoder);
5031 i9xx_enable_pll(intel_crtc);
5033 i9xx_pfit_enable(intel_crtc);
5035 intel_crtc_load_lut(crtc);
5037 intel_update_watermarks(crtc);
5038 intel_enable_pipe(intel_crtc);
5040 for_each_encoder_on_crtc(dev, crtc, encoder)
5041 encoder->enable(encoder);
5043 assert_vblank_disabled(crtc);
5044 drm_crtc_vblank_on(crtc);
5046 intel_crtc_enable_planes(crtc);
5049 * Gen2 reports pipe underruns whenever all planes are disabled.
5050 * So don't enable underrun reporting before at least some planes
5052 * FIXME: Need to fix the logic to work when we turn off all planes
5053 * but leave the pipe running.
5056 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058 /* Underruns don't raise interrupts, so check manually. */
5059 i9xx_check_fifo_underruns(dev_priv);
5062 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5064 struct drm_device *dev = crtc->base.dev;
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5067 if (!crtc->config.gmch_pfit.control)
5070 assert_pipe_disabled(dev_priv, crtc->pipe);
5072 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5073 I915_READ(PFIT_CONTROL));
5074 I915_WRITE(PFIT_CONTROL, 0);
5077 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082 struct intel_encoder *encoder;
5083 int pipe = intel_crtc->pipe;
5085 if (!intel_crtc->active)
5089 * Gen2 reports pipe underruns whenever all planes are disabled.
5090 * So diasble underrun reporting before all the planes get disabled.
5091 * FIXME: Need to fix the logic to work when we turn off all planes
5092 * but leave the pipe running.
5095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5098 * Vblank time updates from the shadow to live plane control register
5099 * are blocked if the memory self-refresh mode is active at that
5100 * moment. So to make sure the plane gets truly disabled, disable
5101 * first the self-refresh mode. The self-refresh enable bit in turn
5102 * will be checked/applied by the HW only at the next frame start
5103 * event which is after the vblank start event, so we need to have a
5104 * wait-for-vblank between disabling the plane and the pipe.
5106 intel_set_memory_cxsr(dev_priv, false);
5107 intel_crtc_disable_planes(crtc);
5110 * On gen2 planes are double buffered but the pipe isn't, so we must
5111 * wait for planes to fully turn off before disabling the pipe.
5112 * We also need to wait on all gmch platforms because of the
5113 * self-refresh mode constraint explained above.
5115 intel_wait_for_vblank(dev, pipe);
5117 drm_crtc_vblank_off(crtc);
5118 assert_vblank_disabled(crtc);
5120 for_each_encoder_on_crtc(dev, crtc, encoder)
5121 encoder->disable(encoder);
5123 intel_disable_pipe(intel_crtc);
5125 i9xx_pfit_disable(intel_crtc);
5127 for_each_encoder_on_crtc(dev, crtc, encoder)
5128 if (encoder->post_disable)
5129 encoder->post_disable(encoder);
5131 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5132 if (IS_CHERRYVIEW(dev))
5133 chv_disable_pll(dev_priv, pipe);
5134 else if (IS_VALLEYVIEW(dev))
5135 vlv_disable_pll(dev_priv, pipe);
5137 i9xx_disable_pll(intel_crtc);
5141 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5143 intel_crtc->active = false;
5144 intel_update_watermarks(crtc);
5146 mutex_lock(&dev->struct_mutex);
5147 intel_update_fbc(dev);
5148 mutex_unlock(&dev->struct_mutex);
5151 static void i9xx_crtc_off(struct drm_crtc *crtc)
5155 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5158 struct drm_device *dev = crtc->dev;
5159 struct drm_i915_master_private *master_priv;
5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161 int pipe = intel_crtc->pipe;
5163 if (!dev->primary->master)
5166 master_priv = dev->primary->master->driver_priv;
5167 if (!master_priv->sarea_priv)
5172 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5173 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5176 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5177 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5180 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5185 /* Master function to enable/disable CRTC and corresponding power wells */
5186 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191 enum intel_display_power_domain domain;
5192 unsigned long domains;
5195 if (!intel_crtc->active) {
5196 domains = get_crtc_power_domains(crtc);
5197 for_each_power_domain(domain, domains)
5198 intel_display_power_get(dev_priv, domain);
5199 intel_crtc->enabled_power_domains = domains;
5201 dev_priv->display.crtc_enable(crtc);
5204 if (intel_crtc->active) {
5205 dev_priv->display.crtc_disable(crtc);
5207 domains = intel_crtc->enabled_power_domains;
5208 for_each_power_domain(domain, domains)
5209 intel_display_power_put(dev_priv, domain);
5210 intel_crtc->enabled_power_domains = 0;
5216 * Sets the power management mode of the pipe and plane.
5218 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5220 struct drm_device *dev = crtc->dev;
5221 struct intel_encoder *intel_encoder;
5222 bool enable = false;
5224 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225 enable |= intel_encoder->connectors_active;
5227 intel_crtc_control(crtc, enable);
5229 intel_crtc_update_sarea(crtc, enable);
5232 static void intel_crtc_disable(struct drm_crtc *crtc)
5234 struct drm_device *dev = crtc->dev;
5235 struct drm_connector *connector;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
5237 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5238 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5240 /* crtc should still be enabled when we disable it. */
5241 WARN_ON(!crtc->enabled);
5243 dev_priv->display.crtc_disable(crtc);
5244 intel_crtc_update_sarea(crtc, false);
5245 dev_priv->display.off(crtc);
5247 if (crtc->primary->fb) {
5248 mutex_lock(&dev->struct_mutex);
5249 intel_unpin_fb_obj(old_obj);
5250 i915_gem_track_fb(old_obj, NULL,
5251 INTEL_FRONTBUFFER_PRIMARY(pipe));
5252 mutex_unlock(&dev->struct_mutex);
5253 crtc->primary->fb = NULL;
5256 /* Update computed state. */
5257 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258 if (!connector->encoder || !connector->encoder->crtc)
5261 if (connector->encoder->crtc != crtc)
5264 connector->dpms = DRM_MODE_DPMS_OFF;
5265 to_intel_encoder(connector->encoder)->connectors_active = false;
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5271 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5273 drm_encoder_cleanup(encoder);
5274 kfree(intel_encoder);
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279 * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5282 if (mode == DRM_MODE_DPMS_ON) {
5283 encoder->connectors_active = true;
5285 intel_crtc_update_dpms(encoder->base.crtc);
5287 encoder->connectors_active = false;
5289 intel_crtc_update_dpms(encoder->base.crtc);
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294 * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5297 if (connector->get_hw_state(connector)) {
5298 struct intel_encoder *encoder = connector->encoder;
5299 struct drm_crtc *crtc;
5300 bool encoder_enabled;
5303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304 connector->base.base.id,
5305 connector->base.name);
5307 /* there is no real hw state for MST connectors */
5308 if (connector->mst_port)
5311 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312 "wrong connector dpms state\n");
5313 WARN(connector->base.encoder != &encoder->base,
5314 "active connector not linked to encoder\n");
5317 WARN(!encoder->connectors_active,
5318 "encoder->connectors_active not set\n");
5320 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321 WARN(!encoder_enabled, "encoder not enabled\n");
5322 if (WARN_ON(!encoder->base.crtc))
5325 crtc = encoder->base.crtc;
5327 WARN(!crtc->enabled, "crtc not enabled\n");
5328 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329 WARN(pipe != to_intel_crtc(crtc)->pipe,
5330 "encoder active on the wrong pipe\n");
5335 /* Even simpler default implementation, if there's really no special case to
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5339 /* All the simple cases only support two dpms states. */
5340 if (mode != DRM_MODE_DPMS_ON)
5341 mode = DRM_MODE_DPMS_OFF;
5343 if (mode == connector->dpms)
5346 connector->dpms = mode;
5348 /* Only need to change hw state when actually enabled */
5349 if (connector->encoder)
5350 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5352 intel_modeset_check_state(connector->dev);
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356 * one connector and no cloning and hence the encoder state determines the state
5357 * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5361 struct intel_encoder *encoder = connector->encoder;
5363 return encoder->get_hw_state(encoder, &pipe);
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367 struct intel_crtc_config *pipe_config)
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_crtc *pipe_B_crtc =
5371 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374 pipe_name(pipe), pipe_config->fdi_lanes);
5375 if (pipe_config->fdi_lanes > 4) {
5376 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377 pipe_name(pipe), pipe_config->fdi_lanes);
5381 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382 if (pipe_config->fdi_lanes > 2) {
5383 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384 pipe_config->fdi_lanes);
5391 if (INTEL_INFO(dev)->num_pipes == 2)
5394 /* Ivybridge 3 pipe is really complicated */
5399 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400 pipe_config->fdi_lanes > 2) {
5401 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402 pipe_name(pipe), pipe_config->fdi_lanes);
5407 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408 pipe_B_crtc->config.fdi_lanes <= 2) {
5409 if (pipe_config->fdi_lanes > 2) {
5410 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411 pipe_name(pipe), pipe_config->fdi_lanes);
5415 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426 struct intel_crtc_config *pipe_config)
5428 struct drm_device *dev = intel_crtc->base.dev;
5429 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430 int lane, link_bw, fdi_dotclock;
5431 bool setup_ok, needs_recompute = false;
5434 /* FDI is a binary signal running at ~2.7GHz, encoding
5435 * each output octet as 10 bits. The actual frequency
5436 * is stored as a divider into a 100MHz clock, and the
5437 * mode pixel clock is stored in units of 1KHz.
5438 * Hence the bw of each lane in terms of the mode signal
5441 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5443 fdi_dotclock = adjusted_mode->crtc_clock;
5445 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446 pipe_config->pipe_bpp);
5448 pipe_config->fdi_lanes = lane;
5450 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451 link_bw, &pipe_config->fdi_m_n);
5453 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454 intel_crtc->pipe, pipe_config);
5455 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456 pipe_config->pipe_bpp -= 2*3;
5457 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458 pipe_config->pipe_bpp);
5459 needs_recompute = true;
5460 pipe_config->bw_constrained = true;
5465 if (needs_recompute)
5468 return setup_ok ? 0 : -EINVAL;
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472 struct intel_crtc_config *pipe_config)
5474 pipe_config->ips_enabled = i915.enable_ips &&
5475 hsw_crtc_supports_ips(crtc) &&
5476 pipe_config->pipe_bpp <= 24;
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480 struct intel_crtc_config *pipe_config)
5482 struct drm_device *dev = crtc->base.dev;
5483 struct drm_i915_private *dev_priv = dev->dev_private;
5484 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5486 /* FIXME should check pixel clock limits on all platforms */
5487 if (INTEL_INFO(dev)->gen < 4) {
5489 dev_priv->display.get_display_clock_speed(dev);
5492 * Enable pixel doubling when the dot clock
5493 * is > 90% of the (display) core speed.
5495 * GDG double wide on either pipe,
5496 * otherwise pipe A only.
5498 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5501 pipe_config->double_wide = true;
5504 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5509 * Pipe horizontal size must be even in:
5511 * - LVDS dual channel mode
5512 * - Double wide pipe
5514 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516 pipe_config->pipe_src_w &= ~1;
5518 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5521 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5525 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5530 pipe_config->pipe_bpp = 8*3;
5534 hsw_compute_ips_config(crtc, pipe_config);
5537 * XXX: PCH/WRPLL clock sharing is done in ->mode_set if ->compute_clock is not
5538 * set, so make sure the old clock survives for now.
5540 if (dev_priv->display.crtc_compute_clock == NULL &&
5541 (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)))
5542 pipe_config->shared_dpll = crtc->config.shared_dpll;
5544 if (pipe_config->has_pch_encoder)
5545 return ironlake_fdi_compute_config(crtc, pipe_config);
5550 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5552 struct drm_i915_private *dev_priv = dev->dev_private;
5553 int vco = valleyview_get_vco(dev_priv);
5557 /* FIXME: Punit isn't quite ready yet */
5558 if (IS_CHERRYVIEW(dev))
5561 mutex_lock(&dev_priv->dpio_lock);
5562 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5563 mutex_unlock(&dev_priv->dpio_lock);
5565 divider = val & DISPLAY_FREQUENCY_VALUES;
5567 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5568 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5569 "cdclk change in progress\n");
5571 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5574 static int i945_get_display_clock_speed(struct drm_device *dev)
5579 static int i915_get_display_clock_speed(struct drm_device *dev)
5584 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5589 static int pnv_get_display_clock_speed(struct drm_device *dev)
5593 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5595 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5596 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5598 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5600 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5602 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5605 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5606 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5608 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5613 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5617 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5619 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5622 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5623 case GC_DISPLAY_CLOCK_333_MHZ:
5626 case GC_DISPLAY_CLOCK_190_200_MHZ:
5632 static int i865_get_display_clock_speed(struct drm_device *dev)
5637 static int i855_get_display_clock_speed(struct drm_device *dev)
5640 /* Assume that the hardware is in the high speed state. This
5641 * should be the default.
5643 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5644 case GC_CLOCK_133_200:
5645 case GC_CLOCK_100_200:
5647 case GC_CLOCK_166_250:
5649 case GC_CLOCK_100_133:
5653 /* Shouldn't happen */
5657 static int i830_get_display_clock_speed(struct drm_device *dev)
5663 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5665 while (*num > DATA_LINK_M_N_MASK ||
5666 *den > DATA_LINK_M_N_MASK) {
5672 static void compute_m_n(unsigned int m, unsigned int n,
5673 uint32_t *ret_m, uint32_t *ret_n)
5675 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5676 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5677 intel_reduce_m_n_ratio(ret_m, ret_n);
5681 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5682 int pixel_clock, int link_clock,
5683 struct intel_link_m_n *m_n)
5687 compute_m_n(bits_per_pixel * pixel_clock,
5688 link_clock * nlanes * 8,
5689 &m_n->gmch_m, &m_n->gmch_n);
5691 compute_m_n(pixel_clock, link_clock,
5692 &m_n->link_m, &m_n->link_n);
5695 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5697 if (i915.panel_use_ssc >= 0)
5698 return i915.panel_use_ssc != 0;
5699 return dev_priv->vbt.lvds_use_ssc
5700 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5703 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5705 struct drm_device *dev = crtc->base.dev;
5706 struct drm_i915_private *dev_priv = dev->dev_private;
5709 if (IS_VALLEYVIEW(dev)) {
5711 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5712 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5713 refclk = dev_priv->vbt.lvds_ssc_freq;
5714 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5715 } else if (!IS_GEN2(dev)) {
5724 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5726 return (1 << dpll->n) << 16 | dpll->m2;
5729 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5731 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5734 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5735 intel_clock_t *reduced_clock)
5737 struct drm_device *dev = crtc->base.dev;
5740 if (IS_PINEVIEW(dev)) {
5741 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5743 fp2 = pnv_dpll_compute_fp(reduced_clock);
5745 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5747 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5750 crtc->config.dpll_hw_state.fp0 = fp;
5752 crtc->lowfreq_avail = false;
5753 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5754 reduced_clock && i915.powersave) {
5755 crtc->config.dpll_hw_state.fp1 = fp2;
5756 crtc->lowfreq_avail = true;
5758 crtc->config.dpll_hw_state.fp1 = fp;
5762 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5768 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5769 * and set it to a reasonable value instead.
5771 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5772 reg_val &= 0xffffff00;
5773 reg_val |= 0x00000030;
5774 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5777 reg_val &= 0x8cffffff;
5778 reg_val = 0x8c000000;
5779 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5781 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5782 reg_val &= 0xffffff00;
5783 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5785 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5786 reg_val &= 0x00ffffff;
5787 reg_val |= 0xb0000000;
5788 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5791 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5792 struct intel_link_m_n *m_n)
5794 struct drm_device *dev = crtc->base.dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 int pipe = crtc->pipe;
5798 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5799 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5800 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5801 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5804 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5805 struct intel_link_m_n *m_n,
5806 struct intel_link_m_n *m2_n2)
5808 struct drm_device *dev = crtc->base.dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 int pipe = crtc->pipe;
5811 enum transcoder transcoder = crtc->config.cpu_transcoder;
5813 if (INTEL_INFO(dev)->gen >= 5) {
5814 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5815 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5816 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5817 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5818 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5819 * for gen < 8) and if DRRS is supported (to make sure the
5820 * registers are not unnecessarily accessed).
5822 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5823 crtc->config.has_drrs) {
5824 I915_WRITE(PIPE_DATA_M2(transcoder),
5825 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5826 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5827 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5828 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5831 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5832 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5833 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5834 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5838 void intel_dp_set_m_n(struct intel_crtc *crtc)
5840 if (crtc->config.has_pch_encoder)
5841 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5843 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5844 &crtc->config.dp_m2_n2);
5847 static void vlv_update_pll(struct intel_crtc *crtc,
5848 struct intel_crtc_config *pipe_config)
5853 * Enable DPIO clock input. We should never disable the reference
5854 * clock for pipe B, since VGA hotplug / manual detection depends
5857 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5858 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5859 /* We should never disable this, set it here for state tracking */
5860 if (crtc->pipe == PIPE_B)
5861 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5862 dpll |= DPLL_VCO_ENABLE;
5863 pipe_config->dpll_hw_state.dpll = dpll;
5865 dpll_md = (pipe_config->pixel_multiplier - 1)
5866 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5867 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5870 static void vlv_prepare_pll(struct intel_crtc *crtc,
5871 const struct intel_crtc_config *pipe_config)
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 int pipe = crtc->pipe;
5877 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5878 u32 coreclk, reg_val;
5880 mutex_lock(&dev_priv->dpio_lock);
5882 bestn = pipe_config->dpll.n;
5883 bestm1 = pipe_config->dpll.m1;
5884 bestm2 = pipe_config->dpll.m2;
5885 bestp1 = pipe_config->dpll.p1;
5886 bestp2 = pipe_config->dpll.p2;
5888 /* See eDP HDMI DPIO driver vbios notes doc */
5890 /* PLL B needs special handling */
5892 vlv_pllb_recal_opamp(dev_priv, pipe);
5894 /* Set up Tx target for periodic Rcomp update */
5895 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5897 /* Disable target IRef on PLL */
5898 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5899 reg_val &= 0x00ffffff;
5900 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5902 /* Disable fast lock */
5903 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5905 /* Set idtafcrecal before PLL is enabled */
5906 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5907 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5908 mdiv |= ((bestn << DPIO_N_SHIFT));
5909 mdiv |= (1 << DPIO_K_SHIFT);
5912 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5913 * but we don't support that).
5914 * Note: don't use the DAC post divider as it seems unstable.
5916 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5917 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5919 mdiv |= DPIO_ENABLE_CALIBRATION;
5920 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5922 /* Set HBR and RBR LPF coefficients */
5923 if (pipe_config->port_clock == 162000 ||
5924 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5925 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5926 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5932 if (crtc->config.has_dp_encoder) {
5933 /* Use SSC source */
5935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5940 } else { /* HDMI or VGA */
5941 /* Use bend source */
5943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5950 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5951 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5952 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5953 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5954 coreclk |= 0x01000000;
5955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5958 mutex_unlock(&dev_priv->dpio_lock);
5961 static void chv_update_pll(struct intel_crtc *crtc,
5962 struct intel_crtc_config *pipe_config)
5964 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5965 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5967 if (crtc->pipe != PIPE_A)
5968 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5970 pipe_config->dpll_hw_state.dpll_md =
5971 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5974 static void chv_prepare_pll(struct intel_crtc *crtc,
5975 const struct intel_crtc_config *pipe_config)
5977 struct drm_device *dev = crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 int pipe = crtc->pipe;
5980 int dpll_reg = DPLL(crtc->pipe);
5981 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5982 u32 loopfilter, intcoeff;
5983 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5986 bestn = pipe_config->dpll.n;
5987 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5988 bestm1 = pipe_config->dpll.m1;
5989 bestm2 = pipe_config->dpll.m2 >> 22;
5990 bestp1 = pipe_config->dpll.p1;
5991 bestp2 = pipe_config->dpll.p2;
5994 * Enable Refclk and SSC
5996 I915_WRITE(dpll_reg,
5997 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5999 mutex_lock(&dev_priv->dpio_lock);
6001 /* p1 and p2 divider */
6002 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6003 5 << DPIO_CHV_S1_DIV_SHIFT |
6004 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6005 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6006 1 << DPIO_CHV_K_DIV_SHIFT);
6008 /* Feedback post-divider - m2 */
6009 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6011 /* Feedback refclk divider - n and m1 */
6012 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6013 DPIO_CHV_M1_DIV_BY_2 |
6014 1 << DPIO_CHV_N_DIV_SHIFT);
6016 /* M2 fraction division */
6017 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6019 /* M2 fraction division enable */
6020 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6021 DPIO_CHV_FRAC_DIV_EN |
6022 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6025 refclk = i9xx_get_refclk(crtc, 0);
6026 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6027 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6028 if (refclk == 100000)
6030 else if (refclk == 38400)
6034 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6038 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6039 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6042 mutex_unlock(&dev_priv->dpio_lock);
6046 * vlv_force_pll_on - forcibly enable just the PLL
6047 * @dev_priv: i915 private structure
6048 * @pipe: pipe PLL to enable
6049 * @dpll: PLL configuration
6051 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6052 * in cases where we need the PLL enabled even when @pipe is not going to
6055 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6056 const struct dpll *dpll)
6058 struct intel_crtc *crtc =
6059 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6060 struct intel_crtc_config pipe_config = {
6061 .pixel_multiplier = 1,
6065 if (IS_CHERRYVIEW(dev)) {
6066 chv_update_pll(crtc, &pipe_config);
6067 chv_prepare_pll(crtc, &pipe_config);
6068 chv_enable_pll(crtc, &pipe_config);
6070 vlv_update_pll(crtc, &pipe_config);
6071 vlv_prepare_pll(crtc, &pipe_config);
6072 vlv_enable_pll(crtc, &pipe_config);
6077 * vlv_force_pll_off - forcibly disable just the PLL
6078 * @dev_priv: i915 private structure
6079 * @pipe: pipe PLL to disable
6081 * Disable the PLL for @pipe. To be used in cases where we need
6082 * the PLL enabled even when @pipe is not going to be enabled.
6084 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6086 if (IS_CHERRYVIEW(dev))
6087 chv_disable_pll(to_i915(dev), pipe);
6089 vlv_disable_pll(to_i915(dev), pipe);
6092 static void i9xx_update_pll(struct intel_crtc *crtc,
6093 intel_clock_t *reduced_clock,
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6100 struct dpll *clock = &crtc->new_config->dpll;
6102 i9xx_update_pll_dividers(crtc, reduced_clock);
6104 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6105 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6107 dpll = DPLL_VGA_MODE_DIS;
6109 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6110 dpll |= DPLLB_MODE_LVDS;
6112 dpll |= DPLLB_MODE_DAC_SERIAL;
6114 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6115 dpll |= (crtc->new_config->pixel_multiplier - 1)
6116 << SDVO_MULTIPLIER_SHIFT_HIRES;
6120 dpll |= DPLL_SDVO_HIGH_SPEED;
6122 if (crtc->new_config->has_dp_encoder)
6123 dpll |= DPLL_SDVO_HIGH_SPEED;
6125 /* compute bitmask from p1 value */
6126 if (IS_PINEVIEW(dev))
6127 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6129 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6130 if (IS_G4X(dev) && reduced_clock)
6131 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6133 switch (clock->p2) {
6135 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6138 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6141 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6144 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6147 if (INTEL_INFO(dev)->gen >= 4)
6148 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6150 if (crtc->new_config->sdvo_tv_clock)
6151 dpll |= PLL_REF_INPUT_TVCLKINBC;
6152 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6153 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6154 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6156 dpll |= PLL_REF_INPUT_DREFCLK;
6158 dpll |= DPLL_VCO_ENABLE;
6159 crtc->new_config->dpll_hw_state.dpll = dpll;
6161 if (INTEL_INFO(dev)->gen >= 4) {
6162 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6163 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6164 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6168 static void i8xx_update_pll(struct intel_crtc *crtc,
6169 intel_clock_t *reduced_clock,
6172 struct drm_device *dev = crtc->base.dev;
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6175 struct dpll *clock = &crtc->new_config->dpll;
6177 i9xx_update_pll_dividers(crtc, reduced_clock);
6179 dpll = DPLL_VGA_MODE_DIS;
6181 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6182 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6185 dpll |= PLL_P1_DIVIDE_BY_TWO;
6187 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6189 dpll |= PLL_P2_DIVIDE_BY_4;
6192 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6193 dpll |= DPLL_DVO_2X_MODE;
6195 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6196 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6197 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6199 dpll |= PLL_REF_INPUT_DREFCLK;
6201 dpll |= DPLL_VCO_ENABLE;
6202 crtc->new_config->dpll_hw_state.dpll = dpll;
6205 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6207 struct drm_device *dev = intel_crtc->base.dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 enum pipe pipe = intel_crtc->pipe;
6210 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6211 struct drm_display_mode *adjusted_mode =
6212 &intel_crtc->config.adjusted_mode;
6213 uint32_t crtc_vtotal, crtc_vblank_end;
6216 /* We need to be careful not to changed the adjusted mode, for otherwise
6217 * the hw state checker will get angry at the mismatch. */
6218 crtc_vtotal = adjusted_mode->crtc_vtotal;
6219 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6221 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6222 /* the chip adds 2 halflines automatically */
6224 crtc_vblank_end -= 1;
6226 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6227 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6229 vsyncshift = adjusted_mode->crtc_hsync_start -
6230 adjusted_mode->crtc_htotal / 2;
6232 vsyncshift += adjusted_mode->crtc_htotal;
6235 if (INTEL_INFO(dev)->gen > 3)
6236 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6238 I915_WRITE(HTOTAL(cpu_transcoder),
6239 (adjusted_mode->crtc_hdisplay - 1) |
6240 ((adjusted_mode->crtc_htotal - 1) << 16));
6241 I915_WRITE(HBLANK(cpu_transcoder),
6242 (adjusted_mode->crtc_hblank_start - 1) |
6243 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6244 I915_WRITE(HSYNC(cpu_transcoder),
6245 (adjusted_mode->crtc_hsync_start - 1) |
6246 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6248 I915_WRITE(VTOTAL(cpu_transcoder),
6249 (adjusted_mode->crtc_vdisplay - 1) |
6250 ((crtc_vtotal - 1) << 16));
6251 I915_WRITE(VBLANK(cpu_transcoder),
6252 (adjusted_mode->crtc_vblank_start - 1) |
6253 ((crtc_vblank_end - 1) << 16));
6254 I915_WRITE(VSYNC(cpu_transcoder),
6255 (adjusted_mode->crtc_vsync_start - 1) |
6256 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6258 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6259 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6260 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6262 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6263 (pipe == PIPE_B || pipe == PIPE_C))
6264 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6266 /* pipesrc controls the size that is scaled from, which should
6267 * always be the user's requested size.
6269 I915_WRITE(PIPESRC(pipe),
6270 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6271 (intel_crtc->config.pipe_src_h - 1));
6274 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6275 struct intel_crtc_config *pipe_config)
6277 struct drm_device *dev = crtc->base.dev;
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6282 tmp = I915_READ(HTOTAL(cpu_transcoder));
6283 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6284 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6285 tmp = I915_READ(HBLANK(cpu_transcoder));
6286 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6287 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6288 tmp = I915_READ(HSYNC(cpu_transcoder));
6289 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6290 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6292 tmp = I915_READ(VTOTAL(cpu_transcoder));
6293 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6294 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6295 tmp = I915_READ(VBLANK(cpu_transcoder));
6296 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6297 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6298 tmp = I915_READ(VSYNC(cpu_transcoder));
6299 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6300 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6302 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6303 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6304 pipe_config->adjusted_mode.crtc_vtotal += 1;
6305 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6308 tmp = I915_READ(PIPESRC(crtc->pipe));
6309 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6310 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6312 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6313 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6316 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6317 struct intel_crtc_config *pipe_config)
6319 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6320 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6321 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6322 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6324 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6325 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6326 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6327 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6329 mode->flags = pipe_config->adjusted_mode.flags;
6331 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6332 mode->flags |= pipe_config->adjusted_mode.flags;
6335 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6337 struct drm_device *dev = intel_crtc->base.dev;
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6343 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6344 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6345 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6347 if (intel_crtc->config.double_wide)
6348 pipeconf |= PIPECONF_DOUBLE_WIDE;
6350 /* only g4x and later have fancy bpc/dither controls */
6351 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6352 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6353 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6354 pipeconf |= PIPECONF_DITHER_EN |
6355 PIPECONF_DITHER_TYPE_SP;
6357 switch (intel_crtc->config.pipe_bpp) {
6359 pipeconf |= PIPECONF_6BPC;
6362 pipeconf |= PIPECONF_8BPC;
6365 pipeconf |= PIPECONF_10BPC;
6368 /* Case prevented by intel_choose_pipe_bpp_dither. */
6373 if (HAS_PIPE_CXSR(dev)) {
6374 if (intel_crtc->lowfreq_avail) {
6375 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6376 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6378 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6382 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6383 if (INTEL_INFO(dev)->gen < 4 ||
6384 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6385 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6387 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6389 pipeconf |= PIPECONF_PROGRESSIVE;
6391 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6392 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6394 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6395 POSTING_READ(PIPECONF(intel_crtc->pipe));
6398 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6400 struct drm_framebuffer *fb)
6402 struct drm_device *dev = crtc->base.dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 int refclk, num_connectors = 0;
6405 intel_clock_t clock, reduced_clock;
6406 bool ok, has_reduced_clock = false;
6407 bool is_lvds = false, is_dsi = false;
6408 struct intel_encoder *encoder;
6409 const intel_limit_t *limit;
6411 for_each_intel_encoder(dev, encoder) {
6412 if (encoder->new_crtc != crtc)
6415 switch (encoder->type) {
6416 case INTEL_OUTPUT_LVDS:
6419 case INTEL_OUTPUT_DSI:
6432 if (!crtc->new_config->clock_set) {
6433 refclk = i9xx_get_refclk(crtc, num_connectors);
6436 * Returns a set of divisors for the desired target clock with
6437 * the given refclk, or FALSE. The returned values represent
6438 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6441 limit = intel_limit(crtc, refclk);
6442 ok = dev_priv->display.find_dpll(limit, crtc,
6443 crtc->new_config->port_clock,
6444 refclk, NULL, &clock);
6446 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6450 if (is_lvds && dev_priv->lvds_downclock_avail) {
6452 * Ensure we match the reduced clock's P to the target
6453 * clock. If the clocks don't match, we can't switch
6454 * the display clock by using the FP0/FP1. In such case
6455 * we will disable the LVDS downclock feature.
6458 dev_priv->display.find_dpll(limit, crtc,
6459 dev_priv->lvds_downclock,
6463 /* Compat-code for transition, will disappear. */
6464 crtc->new_config->dpll.n = clock.n;
6465 crtc->new_config->dpll.m1 = clock.m1;
6466 crtc->new_config->dpll.m2 = clock.m2;
6467 crtc->new_config->dpll.p1 = clock.p1;
6468 crtc->new_config->dpll.p2 = clock.p2;
6472 i8xx_update_pll(crtc,
6473 has_reduced_clock ? &reduced_clock : NULL,
6475 } else if (IS_CHERRYVIEW(dev)) {
6476 chv_update_pll(crtc, crtc->new_config);
6477 } else if (IS_VALLEYVIEW(dev)) {
6478 vlv_update_pll(crtc, crtc->new_config);
6480 i9xx_update_pll(crtc,
6481 has_reduced_clock ? &reduced_clock : NULL,
6488 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6489 struct intel_crtc_config *pipe_config)
6491 struct drm_device *dev = crtc->base.dev;
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6495 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6498 tmp = I915_READ(PFIT_CONTROL);
6499 if (!(tmp & PFIT_ENABLE))
6502 /* Check whether the pfit is attached to our pipe. */
6503 if (INTEL_INFO(dev)->gen < 4) {
6504 if (crtc->pipe != PIPE_B)
6507 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6511 pipe_config->gmch_pfit.control = tmp;
6512 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6513 if (INTEL_INFO(dev)->gen < 5)
6514 pipe_config->gmch_pfit.lvds_border_bits =
6515 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6518 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6519 struct intel_crtc_config *pipe_config)
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 int pipe = pipe_config->cpu_transcoder;
6524 intel_clock_t clock;
6526 int refclk = 100000;
6528 /* In case of MIPI DPLL will not even be used */
6529 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6532 mutex_lock(&dev_priv->dpio_lock);
6533 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6534 mutex_unlock(&dev_priv->dpio_lock);
6536 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6537 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6538 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6539 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6540 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6542 vlv_clock(refclk, &clock);
6544 /* clock.dot is the fast clock */
6545 pipe_config->port_clock = clock.dot / 5;
6548 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6549 struct intel_plane_config *plane_config)
6551 struct drm_device *dev = crtc->base.dev;
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 u32 val, base, offset;
6554 int pipe = crtc->pipe, plane = crtc->plane;
6555 int fourcc, pixel_format;
6558 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6559 if (!crtc->base.primary->fb) {
6560 DRM_DEBUG_KMS("failed to alloc fb\n");
6564 val = I915_READ(DSPCNTR(plane));
6566 if (INTEL_INFO(dev)->gen >= 4)
6567 if (val & DISPPLANE_TILED)
6568 plane_config->tiled = true;
6570 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6571 fourcc = intel_format_to_fourcc(pixel_format);
6572 crtc->base.primary->fb->pixel_format = fourcc;
6573 crtc->base.primary->fb->bits_per_pixel =
6574 drm_format_plane_cpp(fourcc, 0) * 8;
6576 if (INTEL_INFO(dev)->gen >= 4) {
6577 if (plane_config->tiled)
6578 offset = I915_READ(DSPTILEOFF(plane));
6580 offset = I915_READ(DSPLINOFF(plane));
6581 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6583 base = I915_READ(DSPADDR(plane));
6585 plane_config->base = base;
6587 val = I915_READ(PIPESRC(pipe));
6588 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6589 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6591 val = I915_READ(DSPSTRIDE(pipe));
6592 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6594 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6595 plane_config->tiled);
6597 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6600 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6601 pipe, plane, crtc->base.primary->fb->width,
6602 crtc->base.primary->fb->height,
6603 crtc->base.primary->fb->bits_per_pixel, base,
6604 crtc->base.primary->fb->pitches[0],
6605 plane_config->size);
6609 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6610 struct intel_crtc_config *pipe_config)
6612 struct drm_device *dev = crtc->base.dev;
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614 int pipe = pipe_config->cpu_transcoder;
6615 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6616 intel_clock_t clock;
6617 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6618 int refclk = 100000;
6620 mutex_lock(&dev_priv->dpio_lock);
6621 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6622 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6623 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6624 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6625 mutex_unlock(&dev_priv->dpio_lock);
6627 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6628 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6629 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6630 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6631 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6633 chv_clock(refclk, &clock);
6635 /* clock.dot is the fast clock */
6636 pipe_config->port_clock = clock.dot / 5;
6639 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6640 struct intel_crtc_config *pipe_config)
6642 struct drm_device *dev = crtc->base.dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6646 if (!intel_display_power_is_enabled(dev_priv,
6647 POWER_DOMAIN_PIPE(crtc->pipe)))
6650 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6651 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6653 tmp = I915_READ(PIPECONF(crtc->pipe));
6654 if (!(tmp & PIPECONF_ENABLE))
6657 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6658 switch (tmp & PIPECONF_BPC_MASK) {
6660 pipe_config->pipe_bpp = 18;
6663 pipe_config->pipe_bpp = 24;
6665 case PIPECONF_10BPC:
6666 pipe_config->pipe_bpp = 30;
6673 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6674 pipe_config->limited_color_range = true;
6676 if (INTEL_INFO(dev)->gen < 4)
6677 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6679 intel_get_pipe_timings(crtc, pipe_config);
6681 i9xx_get_pfit_config(crtc, pipe_config);
6683 if (INTEL_INFO(dev)->gen >= 4) {
6684 tmp = I915_READ(DPLL_MD(crtc->pipe));
6685 pipe_config->pixel_multiplier =
6686 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6687 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6688 pipe_config->dpll_hw_state.dpll_md = tmp;
6689 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6690 tmp = I915_READ(DPLL(crtc->pipe));
6691 pipe_config->pixel_multiplier =
6692 ((tmp & SDVO_MULTIPLIER_MASK)
6693 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6695 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6696 * port and will be fixed up in the encoder->get_config
6698 pipe_config->pixel_multiplier = 1;
6700 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6701 if (!IS_VALLEYVIEW(dev)) {
6703 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6704 * on 830. Filter it out here so that we don't
6705 * report errors due to that.
6708 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6710 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6711 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6713 /* Mask out read-only status bits. */
6714 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6715 DPLL_PORTC_READY_MASK |
6716 DPLL_PORTB_READY_MASK);
6719 if (IS_CHERRYVIEW(dev))
6720 chv_crtc_clock_get(crtc, pipe_config);
6721 else if (IS_VALLEYVIEW(dev))
6722 vlv_crtc_clock_get(crtc, pipe_config);
6724 i9xx_crtc_clock_get(crtc, pipe_config);
6729 static void ironlake_init_pch_refclk(struct drm_device *dev)
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 struct intel_encoder *encoder;
6734 bool has_lvds = false;
6735 bool has_cpu_edp = false;
6736 bool has_panel = false;
6737 bool has_ck505 = false;
6738 bool can_ssc = false;
6740 /* We need to take the global config into account */
6741 for_each_intel_encoder(dev, encoder) {
6742 switch (encoder->type) {
6743 case INTEL_OUTPUT_LVDS:
6747 case INTEL_OUTPUT_EDP:
6749 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6757 if (HAS_PCH_IBX(dev)) {
6758 has_ck505 = dev_priv->vbt.display_clock_mode;
6759 can_ssc = has_ck505;
6765 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6766 has_panel, has_lvds, has_ck505);
6768 /* Ironlake: try to setup display ref clock before DPLL
6769 * enabling. This is only under driver's control after
6770 * PCH B stepping, previous chipset stepping should be
6771 * ignoring this setting.
6773 val = I915_READ(PCH_DREF_CONTROL);
6775 /* As we must carefully and slowly disable/enable each source in turn,
6776 * compute the final state we want first and check if we need to
6777 * make any changes at all.
6780 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6782 final |= DREF_NONSPREAD_CK505_ENABLE;
6784 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6786 final &= ~DREF_SSC_SOURCE_MASK;
6787 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6788 final &= ~DREF_SSC1_ENABLE;
6791 final |= DREF_SSC_SOURCE_ENABLE;
6793 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6794 final |= DREF_SSC1_ENABLE;
6797 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6798 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6800 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6802 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6804 final |= DREF_SSC_SOURCE_DISABLE;
6805 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6811 /* Always enable nonspread source */
6812 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6815 val |= DREF_NONSPREAD_CK505_ENABLE;
6817 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6820 val &= ~DREF_SSC_SOURCE_MASK;
6821 val |= DREF_SSC_SOURCE_ENABLE;
6823 /* SSC must be turned on before enabling the CPU output */
6824 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6825 DRM_DEBUG_KMS("Using SSC on panel\n");
6826 val |= DREF_SSC1_ENABLE;
6828 val &= ~DREF_SSC1_ENABLE;
6830 /* Get SSC going before enabling the outputs */
6831 I915_WRITE(PCH_DREF_CONTROL, val);
6832 POSTING_READ(PCH_DREF_CONTROL);
6835 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6837 /* Enable CPU source on CPU attached eDP */
6839 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6840 DRM_DEBUG_KMS("Using SSC on eDP\n");
6841 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6843 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6845 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6847 I915_WRITE(PCH_DREF_CONTROL, val);
6848 POSTING_READ(PCH_DREF_CONTROL);
6851 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6853 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6855 /* Turn off CPU output */
6856 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6858 I915_WRITE(PCH_DREF_CONTROL, val);
6859 POSTING_READ(PCH_DREF_CONTROL);
6862 /* Turn off the SSC source */
6863 val &= ~DREF_SSC_SOURCE_MASK;
6864 val |= DREF_SSC_SOURCE_DISABLE;
6867 val &= ~DREF_SSC1_ENABLE;
6869 I915_WRITE(PCH_DREF_CONTROL, val);
6870 POSTING_READ(PCH_DREF_CONTROL);
6874 BUG_ON(val != final);
6877 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6881 tmp = I915_READ(SOUTH_CHICKEN2);
6882 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6883 I915_WRITE(SOUTH_CHICKEN2, tmp);
6885 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6886 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6887 DRM_ERROR("FDI mPHY reset assert timeout\n");
6889 tmp = I915_READ(SOUTH_CHICKEN2);
6890 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6891 I915_WRITE(SOUTH_CHICKEN2, tmp);
6893 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6894 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6895 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6898 /* WaMPhyProgramming:hsw */
6899 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6903 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6904 tmp &= ~(0xFF << 24);
6905 tmp |= (0x12 << 24);
6906 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6908 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6910 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6912 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6914 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6916 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6917 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6918 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6920 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6921 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6922 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6924 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6927 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6929 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6932 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6934 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6937 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6939 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6942 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6944 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6945 tmp &= ~(0xFF << 16);
6946 tmp |= (0x1C << 16);
6947 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6949 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6950 tmp &= ~(0xFF << 16);
6951 tmp |= (0x1C << 16);
6952 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6954 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6956 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6958 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6960 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6962 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6963 tmp &= ~(0xF << 28);
6965 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6967 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6968 tmp &= ~(0xF << 28);
6970 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6973 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6974 * Programming" based on the parameters passed:
6975 * - Sequence to enable CLKOUT_DP
6976 * - Sequence to enable CLKOUT_DP without spread
6977 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6979 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6985 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6987 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6988 with_fdi, "LP PCH doesn't have FDI\n"))
6991 mutex_lock(&dev_priv->dpio_lock);
6993 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994 tmp &= ~SBI_SSCCTL_DISABLE;
6995 tmp |= SBI_SSCCTL_PATHALT;
6996 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7001 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7002 tmp &= ~SBI_SSCCTL_PATHALT;
7003 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7006 lpt_reset_fdi_mphy(dev_priv);
7007 lpt_program_fdi_mphy(dev_priv);
7011 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7012 SBI_GEN0 : SBI_DBUFF0;
7013 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7014 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7015 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7017 mutex_unlock(&dev_priv->dpio_lock);
7020 /* Sequence to disable CLKOUT_DP */
7021 static void lpt_disable_clkout_dp(struct drm_device *dev)
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7026 mutex_lock(&dev_priv->dpio_lock);
7028 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7029 SBI_GEN0 : SBI_DBUFF0;
7030 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7031 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7032 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7034 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7035 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7036 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7037 tmp |= SBI_SSCCTL_PATHALT;
7038 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7041 tmp |= SBI_SSCCTL_DISABLE;
7042 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7045 mutex_unlock(&dev_priv->dpio_lock);
7048 static void lpt_init_pch_refclk(struct drm_device *dev)
7050 struct intel_encoder *encoder;
7051 bool has_vga = false;
7053 for_each_intel_encoder(dev, encoder) {
7054 switch (encoder->type) {
7055 case INTEL_OUTPUT_ANALOG:
7064 lpt_enable_clkout_dp(dev, true, true);
7066 lpt_disable_clkout_dp(dev);
7070 * Initialize reference clocks when the driver loads
7072 void intel_init_pch_refclk(struct drm_device *dev)
7074 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7075 ironlake_init_pch_refclk(dev);
7076 else if (HAS_PCH_LPT(dev))
7077 lpt_init_pch_refclk(dev);
7080 static int ironlake_get_refclk(struct drm_crtc *crtc)
7082 struct drm_device *dev = crtc->dev;
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7084 struct intel_encoder *encoder;
7085 int num_connectors = 0;
7086 bool is_lvds = false;
7088 for_each_intel_encoder(dev, encoder) {
7089 if (encoder->new_crtc != to_intel_crtc(crtc))
7092 switch (encoder->type) {
7093 case INTEL_OUTPUT_LVDS:
7102 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7103 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7104 dev_priv->vbt.lvds_ssc_freq);
7105 return dev_priv->vbt.lvds_ssc_freq;
7111 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7113 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7115 int pipe = intel_crtc->pipe;
7120 switch (intel_crtc->config.pipe_bpp) {
7122 val |= PIPECONF_6BPC;
7125 val |= PIPECONF_8BPC;
7128 val |= PIPECONF_10BPC;
7131 val |= PIPECONF_12BPC;
7134 /* Case prevented by intel_choose_pipe_bpp_dither. */
7138 if (intel_crtc->config.dither)
7139 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7141 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7142 val |= PIPECONF_INTERLACED_ILK;
7144 val |= PIPECONF_PROGRESSIVE;
7146 if (intel_crtc->config.limited_color_range)
7147 val |= PIPECONF_COLOR_RANGE_SELECT;
7149 I915_WRITE(PIPECONF(pipe), val);
7150 POSTING_READ(PIPECONF(pipe));
7154 * Set up the pipe CSC unit.
7156 * Currently only full range RGB to limited range RGB conversion
7157 * is supported, but eventually this should handle various
7158 * RGB<->YCbCr scenarios as well.
7160 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7162 struct drm_device *dev = crtc->dev;
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165 int pipe = intel_crtc->pipe;
7166 uint16_t coeff = 0x7800; /* 1.0 */
7169 * TODO: Check what kind of values actually come out of the pipe
7170 * with these coeff/postoff values and adjust to get the best
7171 * accuracy. Perhaps we even need to take the bpc value into
7175 if (intel_crtc->config.limited_color_range)
7176 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7179 * GY/GU and RY/RU should be the other way around according
7180 * to BSpec, but reality doesn't agree. Just set them up in
7181 * a way that results in the correct picture.
7183 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7184 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7186 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7187 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7189 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7190 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7192 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7193 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7194 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7196 if (INTEL_INFO(dev)->gen > 6) {
7197 uint16_t postoff = 0;
7199 if (intel_crtc->config.limited_color_range)
7200 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7202 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7203 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7204 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7206 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7208 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7210 if (intel_crtc->config.limited_color_range)
7211 mode |= CSC_BLACK_SCREEN_OFFSET;
7213 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7217 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7219 struct drm_device *dev = crtc->dev;
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7222 enum pipe pipe = intel_crtc->pipe;
7223 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7228 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7229 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7231 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7232 val |= PIPECONF_INTERLACED_ILK;
7234 val |= PIPECONF_PROGRESSIVE;
7236 I915_WRITE(PIPECONF(cpu_transcoder), val);
7237 POSTING_READ(PIPECONF(cpu_transcoder));
7239 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7240 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7242 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7245 switch (intel_crtc->config.pipe_bpp) {
7247 val |= PIPEMISC_DITHER_6_BPC;
7250 val |= PIPEMISC_DITHER_8_BPC;
7253 val |= PIPEMISC_DITHER_10_BPC;
7256 val |= PIPEMISC_DITHER_12_BPC;
7259 /* Case prevented by pipe_config_set_bpp. */
7263 if (intel_crtc->config.dither)
7264 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7266 I915_WRITE(PIPEMISC(pipe), val);
7270 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7271 intel_clock_t *clock,
7272 bool *has_reduced_clock,
7273 intel_clock_t *reduced_clock)
7275 struct drm_device *dev = crtc->dev;
7276 struct drm_i915_private *dev_priv = dev->dev_private;
7277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7279 const intel_limit_t *limit;
7280 bool ret, is_lvds = false;
7282 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7284 refclk = ironlake_get_refclk(crtc);
7287 * Returns a set of divisors for the desired target clock with the given
7288 * refclk, or FALSE. The returned values represent the clock equation:
7289 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7291 limit = intel_limit(intel_crtc, refclk);
7292 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7293 intel_crtc->new_config->port_clock,
7294 refclk, NULL, clock);
7298 if (is_lvds && dev_priv->lvds_downclock_avail) {
7300 * Ensure we match the reduced clock's P to the target clock.
7301 * If the clocks don't match, we can't switch the display clock
7302 * by using the FP0/FP1. In such case we will disable the LVDS
7303 * downclock feature.
7305 *has_reduced_clock =
7306 dev_priv->display.find_dpll(limit, intel_crtc,
7307 dev_priv->lvds_downclock,
7315 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7318 * Account for spread spectrum to avoid
7319 * oversubscribing the link. Max center spread
7320 * is 2.5%; use 5% for safety's sake.
7322 u32 bps = target_clock * bpp * 21 / 20;
7323 return DIV_ROUND_UP(bps, link_bw * 8);
7326 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7328 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7331 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7333 intel_clock_t *reduced_clock, u32 *fp2)
7335 struct drm_crtc *crtc = &intel_crtc->base;
7336 struct drm_device *dev = crtc->dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 struct intel_encoder *intel_encoder;
7340 int factor, num_connectors = 0;
7341 bool is_lvds = false, is_sdvo = false;
7343 for_each_intel_encoder(dev, intel_encoder) {
7344 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7347 switch (intel_encoder->type) {
7348 case INTEL_OUTPUT_LVDS:
7351 case INTEL_OUTPUT_SDVO:
7352 case INTEL_OUTPUT_HDMI:
7362 /* Enable autotuning of the PLL clock (if permissible) */
7365 if ((intel_panel_use_ssc(dev_priv) &&
7366 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7367 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7369 } else if (intel_crtc->new_config->sdvo_tv_clock)
7372 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7375 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7381 dpll |= DPLLB_MODE_LVDS;
7383 dpll |= DPLLB_MODE_DAC_SERIAL;
7385 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7386 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7389 dpll |= DPLL_SDVO_HIGH_SPEED;
7390 if (intel_crtc->new_config->has_dp_encoder)
7391 dpll |= DPLL_SDVO_HIGH_SPEED;
7393 /* compute bitmask from p1 value */
7394 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7396 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7398 switch (intel_crtc->new_config->dpll.p2) {
7400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7406 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7409 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7413 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7414 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7416 dpll |= PLL_REF_INPUT_DREFCLK;
7418 return dpll | DPLL_VCO_ENABLE;
7421 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7423 struct drm_device *dev = crtc->base.dev;
7424 intel_clock_t clock, reduced_clock;
7425 u32 dpll = 0, fp = 0, fp2 = 0;
7426 bool ok, has_reduced_clock = false;
7427 bool is_lvds = false;
7428 struct intel_shared_dpll *pll;
7430 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7432 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7433 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7435 ok = ironlake_compute_clocks(&crtc->base, &clock,
7436 &has_reduced_clock, &reduced_clock);
7437 if (!ok && !crtc->new_config->clock_set) {
7438 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7441 /* Compat-code for transition, will disappear. */
7442 if (!crtc->new_config->clock_set) {
7443 crtc->new_config->dpll.n = clock.n;
7444 crtc->new_config->dpll.m1 = clock.m1;
7445 crtc->new_config->dpll.m2 = clock.m2;
7446 crtc->new_config->dpll.p1 = clock.p1;
7447 crtc->new_config->dpll.p2 = clock.p2;
7450 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7451 if (crtc->new_config->has_pch_encoder) {
7452 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7453 if (has_reduced_clock)
7454 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7456 dpll = ironlake_compute_dpll(crtc,
7457 &fp, &reduced_clock,
7458 has_reduced_clock ? &fp2 : NULL);
7460 crtc->new_config->dpll_hw_state.dpll = dpll;
7461 crtc->new_config->dpll_hw_state.fp0 = fp;
7462 if (has_reduced_clock)
7463 crtc->new_config->dpll_hw_state.fp1 = fp2;
7465 crtc->new_config->dpll_hw_state.fp1 = fp;
7467 pll = intel_get_shared_dpll(crtc);
7469 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7470 pipe_name(crtc->pipe));
7475 if (is_lvds && has_reduced_clock && i915.powersave)
7476 crtc->lowfreq_avail = true;
7478 crtc->lowfreq_avail = false;
7483 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7484 struct intel_link_m_n *m_n)
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 enum pipe pipe = crtc->pipe;
7490 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7491 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7492 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7494 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7495 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7496 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7499 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7500 enum transcoder transcoder,
7501 struct intel_link_m_n *m_n,
7502 struct intel_link_m_n *m2_n2)
7504 struct drm_device *dev = crtc->base.dev;
7505 struct drm_i915_private *dev_priv = dev->dev_private;
7506 enum pipe pipe = crtc->pipe;
7508 if (INTEL_INFO(dev)->gen >= 5) {
7509 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7510 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7511 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7513 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7514 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7515 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7516 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7517 * gen < 8) and if DRRS is supported (to make sure the
7518 * registers are not unnecessarily read).
7520 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7521 crtc->config.has_drrs) {
7522 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7523 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7524 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7526 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7527 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7528 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7531 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7532 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7533 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7535 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7536 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7537 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7541 void intel_dp_get_m_n(struct intel_crtc *crtc,
7542 struct intel_crtc_config *pipe_config)
7544 if (crtc->config.has_pch_encoder)
7545 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7547 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7548 &pipe_config->dp_m_n,
7549 &pipe_config->dp_m2_n2);
7552 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7553 struct intel_crtc_config *pipe_config)
7555 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7556 &pipe_config->fdi_m_n, NULL);
7559 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7560 struct intel_crtc_config *pipe_config)
7562 struct drm_device *dev = crtc->base.dev;
7563 struct drm_i915_private *dev_priv = dev->dev_private;
7566 tmp = I915_READ(PF_CTL(crtc->pipe));
7568 if (tmp & PF_ENABLE) {
7569 pipe_config->pch_pfit.enabled = true;
7570 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7571 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7573 /* We currently do not free assignements of panel fitters on
7574 * ivb/hsw (since we don't use the higher upscaling modes which
7575 * differentiates them) so just WARN about this case for now. */
7577 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7578 PF_PIPE_SEL_IVB(crtc->pipe));
7583 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7584 struct intel_plane_config *plane_config)
7586 struct drm_device *dev = crtc->base.dev;
7587 struct drm_i915_private *dev_priv = dev->dev_private;
7588 u32 val, base, offset;
7589 int pipe = crtc->pipe, plane = crtc->plane;
7590 int fourcc, pixel_format;
7593 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7594 if (!crtc->base.primary->fb) {
7595 DRM_DEBUG_KMS("failed to alloc fb\n");
7599 val = I915_READ(DSPCNTR(plane));
7601 if (INTEL_INFO(dev)->gen >= 4)
7602 if (val & DISPPLANE_TILED)
7603 plane_config->tiled = true;
7605 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7606 fourcc = intel_format_to_fourcc(pixel_format);
7607 crtc->base.primary->fb->pixel_format = fourcc;
7608 crtc->base.primary->fb->bits_per_pixel =
7609 drm_format_plane_cpp(fourcc, 0) * 8;
7611 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7612 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7613 offset = I915_READ(DSPOFFSET(plane));
7615 if (plane_config->tiled)
7616 offset = I915_READ(DSPTILEOFF(plane));
7618 offset = I915_READ(DSPLINOFF(plane));
7620 plane_config->base = base;
7622 val = I915_READ(PIPESRC(pipe));
7623 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7624 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7626 val = I915_READ(DSPSTRIDE(pipe));
7627 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7629 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7630 plane_config->tiled);
7632 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7635 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7636 pipe, plane, crtc->base.primary->fb->width,
7637 crtc->base.primary->fb->height,
7638 crtc->base.primary->fb->bits_per_pixel, base,
7639 crtc->base.primary->fb->pitches[0],
7640 plane_config->size);
7643 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7644 struct intel_crtc_config *pipe_config)
7646 struct drm_device *dev = crtc->base.dev;
7647 struct drm_i915_private *dev_priv = dev->dev_private;
7650 if (!intel_display_power_is_enabled(dev_priv,
7651 POWER_DOMAIN_PIPE(crtc->pipe)))
7654 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7655 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7657 tmp = I915_READ(PIPECONF(crtc->pipe));
7658 if (!(tmp & PIPECONF_ENABLE))
7661 switch (tmp & PIPECONF_BPC_MASK) {
7663 pipe_config->pipe_bpp = 18;
7666 pipe_config->pipe_bpp = 24;
7668 case PIPECONF_10BPC:
7669 pipe_config->pipe_bpp = 30;
7671 case PIPECONF_12BPC:
7672 pipe_config->pipe_bpp = 36;
7678 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7679 pipe_config->limited_color_range = true;
7681 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7682 struct intel_shared_dpll *pll;
7684 pipe_config->has_pch_encoder = true;
7686 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7687 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7688 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7690 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7692 if (HAS_PCH_IBX(dev_priv->dev)) {
7693 pipe_config->shared_dpll =
7694 (enum intel_dpll_id) crtc->pipe;
7696 tmp = I915_READ(PCH_DPLL_SEL);
7697 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7698 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7700 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7703 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7705 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7706 &pipe_config->dpll_hw_state));
7708 tmp = pipe_config->dpll_hw_state.dpll;
7709 pipe_config->pixel_multiplier =
7710 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7711 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7713 ironlake_pch_clock_get(crtc, pipe_config);
7715 pipe_config->pixel_multiplier = 1;
7718 intel_get_pipe_timings(crtc, pipe_config);
7720 ironlake_get_pfit_config(crtc, pipe_config);
7725 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7727 struct drm_device *dev = dev_priv->dev;
7728 struct intel_crtc *crtc;
7730 for_each_intel_crtc(dev, crtc)
7731 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7732 pipe_name(crtc->pipe));
7734 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7735 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7736 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7737 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7738 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7739 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7740 "CPU PWM1 enabled\n");
7741 if (IS_HASWELL(dev))
7742 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7743 "CPU PWM2 enabled\n");
7744 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7745 "PCH PWM1 enabled\n");
7746 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7747 "Utility pin enabled\n");
7748 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7751 * In theory we can still leave IRQs enabled, as long as only the HPD
7752 * interrupts remain enabled. We used to check for that, but since it's
7753 * gen-specific and since we only disable LCPLL after we fully disable
7754 * the interrupts, the check below should be enough.
7756 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7759 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7761 struct drm_device *dev = dev_priv->dev;
7763 if (IS_HASWELL(dev))
7764 return I915_READ(D_COMP_HSW);
7766 return I915_READ(D_COMP_BDW);
7769 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7771 struct drm_device *dev = dev_priv->dev;
7773 if (IS_HASWELL(dev)) {
7774 mutex_lock(&dev_priv->rps.hw_lock);
7775 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7777 DRM_ERROR("Failed to write to D_COMP\n");
7778 mutex_unlock(&dev_priv->rps.hw_lock);
7780 I915_WRITE(D_COMP_BDW, val);
7781 POSTING_READ(D_COMP_BDW);
7786 * This function implements pieces of two sequences from BSpec:
7787 * - Sequence for display software to disable LCPLL
7788 * - Sequence for display software to allow package C8+
7789 * The steps implemented here are just the steps that actually touch the LCPLL
7790 * register. Callers should take care of disabling all the display engine
7791 * functions, doing the mode unset, fixing interrupts, etc.
7793 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7794 bool switch_to_fclk, bool allow_power_down)
7798 assert_can_disable_lcpll(dev_priv);
7800 val = I915_READ(LCPLL_CTL);
7802 if (switch_to_fclk) {
7803 val |= LCPLL_CD_SOURCE_FCLK;
7804 I915_WRITE(LCPLL_CTL, val);
7806 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7807 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7808 DRM_ERROR("Switching to FCLK failed\n");
7810 val = I915_READ(LCPLL_CTL);
7813 val |= LCPLL_PLL_DISABLE;
7814 I915_WRITE(LCPLL_CTL, val);
7815 POSTING_READ(LCPLL_CTL);
7817 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7818 DRM_ERROR("LCPLL still locked\n");
7820 val = hsw_read_dcomp(dev_priv);
7821 val |= D_COMP_COMP_DISABLE;
7822 hsw_write_dcomp(dev_priv, val);
7825 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7827 DRM_ERROR("D_COMP RCOMP still in progress\n");
7829 if (allow_power_down) {
7830 val = I915_READ(LCPLL_CTL);
7831 val |= LCPLL_POWER_DOWN_ALLOW;
7832 I915_WRITE(LCPLL_CTL, val);
7833 POSTING_READ(LCPLL_CTL);
7838 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7841 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7845 val = I915_READ(LCPLL_CTL);
7847 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7848 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7852 * Make sure we're not on PC8 state before disabling PC8, otherwise
7853 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7855 * The other problem is that hsw_restore_lcpll() is called as part of
7856 * the runtime PM resume sequence, so we can't just call
7857 * gen6_gt_force_wake_get() because that function calls
7858 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7859 * while we are on the resume sequence. So to solve this problem we have
7860 * to call special forcewake code that doesn't touch runtime PM and
7861 * doesn't enable the forcewake delayed work.
7863 spin_lock_irq(&dev_priv->uncore.lock);
7864 if (dev_priv->uncore.forcewake_count++ == 0)
7865 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7866 spin_unlock_irq(&dev_priv->uncore.lock);
7868 if (val & LCPLL_POWER_DOWN_ALLOW) {
7869 val &= ~LCPLL_POWER_DOWN_ALLOW;
7870 I915_WRITE(LCPLL_CTL, val);
7871 POSTING_READ(LCPLL_CTL);
7874 val = hsw_read_dcomp(dev_priv);
7875 val |= D_COMP_COMP_FORCE;
7876 val &= ~D_COMP_COMP_DISABLE;
7877 hsw_write_dcomp(dev_priv, val);
7879 val = I915_READ(LCPLL_CTL);
7880 val &= ~LCPLL_PLL_DISABLE;
7881 I915_WRITE(LCPLL_CTL, val);
7883 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7884 DRM_ERROR("LCPLL not locked yet\n");
7886 if (val & LCPLL_CD_SOURCE_FCLK) {
7887 val = I915_READ(LCPLL_CTL);
7888 val &= ~LCPLL_CD_SOURCE_FCLK;
7889 I915_WRITE(LCPLL_CTL, val);
7891 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7892 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7893 DRM_ERROR("Switching back to LCPLL failed\n");
7896 /* See the big comment above. */
7897 spin_lock_irq(&dev_priv->uncore.lock);
7898 if (--dev_priv->uncore.forcewake_count == 0)
7899 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7900 spin_unlock_irq(&dev_priv->uncore.lock);
7904 * Package states C8 and deeper are really deep PC states that can only be
7905 * reached when all the devices on the system allow it, so even if the graphics
7906 * device allows PC8+, it doesn't mean the system will actually get to these
7907 * states. Our driver only allows PC8+ when going into runtime PM.
7909 * The requirements for PC8+ are that all the outputs are disabled, the power
7910 * well is disabled and most interrupts are disabled, and these are also
7911 * requirements for runtime PM. When these conditions are met, we manually do
7912 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7913 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7916 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7917 * the state of some registers, so when we come back from PC8+ we need to
7918 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7919 * need to take care of the registers kept by RC6. Notice that this happens even
7920 * if we don't put the device in PCI D3 state (which is what currently happens
7921 * because of the runtime PM support).
7923 * For more, read "Display Sequences for Package C8" on the hardware
7926 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7928 struct drm_device *dev = dev_priv->dev;
7931 DRM_DEBUG_KMS("Enabling package C8+\n");
7933 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7934 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7935 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7936 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7939 lpt_disable_clkout_dp(dev);
7940 hsw_disable_lcpll(dev_priv, true, true);
7943 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7945 struct drm_device *dev = dev_priv->dev;
7948 DRM_DEBUG_KMS("Disabling package C8+\n");
7950 hsw_restore_lcpll(dev_priv);
7951 lpt_init_pch_refclk(dev);
7953 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7954 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7955 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7956 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7959 intel_prepare_ddi(dev);
7962 static void snb_modeset_global_resources(struct drm_device *dev)
7964 modeset_update_crtc_power_domains(dev);
7967 static void haswell_modeset_global_resources(struct drm_device *dev)
7969 modeset_update_crtc_power_domains(dev);
7972 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7974 if (!intel_ddi_pll_select(crtc))
7977 crtc->lowfreq_avail = false;
7982 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7984 struct intel_crtc_config *pipe_config)
7986 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7988 switch (pipe_config->ddi_pll_sel) {
7989 case PORT_CLK_SEL_WRPLL1:
7990 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7992 case PORT_CLK_SEL_WRPLL2:
7993 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7998 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7999 struct intel_crtc_config *pipe_config)
8001 struct drm_device *dev = crtc->base.dev;
8002 struct drm_i915_private *dev_priv = dev->dev_private;
8003 struct intel_shared_dpll *pll;
8007 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8009 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8011 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8013 if (pipe_config->shared_dpll >= 0) {
8014 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8016 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8017 &pipe_config->dpll_hw_state));
8021 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8022 * DDI E. So just check whether this pipe is wired to DDI E and whether
8023 * the PCH transcoder is on.
8025 if (INTEL_INFO(dev)->gen < 9 &&
8026 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8027 pipe_config->has_pch_encoder = true;
8029 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8030 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8031 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8033 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8037 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8038 struct intel_crtc_config *pipe_config)
8040 struct drm_device *dev = crtc->base.dev;
8041 struct drm_i915_private *dev_priv = dev->dev_private;
8042 enum intel_display_power_domain pfit_domain;
8045 if (!intel_display_power_is_enabled(dev_priv,
8046 POWER_DOMAIN_PIPE(crtc->pipe)))
8049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8050 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8052 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8053 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8054 enum pipe trans_edp_pipe;
8055 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8057 WARN(1, "unknown pipe linked to edp transcoder\n");
8058 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8059 case TRANS_DDI_EDP_INPUT_A_ON:
8060 trans_edp_pipe = PIPE_A;
8062 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8063 trans_edp_pipe = PIPE_B;
8065 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8066 trans_edp_pipe = PIPE_C;
8070 if (trans_edp_pipe == crtc->pipe)
8071 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8074 if (!intel_display_power_is_enabled(dev_priv,
8075 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8078 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8079 if (!(tmp & PIPECONF_ENABLE))
8082 haswell_get_ddi_port_state(crtc, pipe_config);
8084 intel_get_pipe_timings(crtc, pipe_config);
8086 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8087 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8088 ironlake_get_pfit_config(crtc, pipe_config);
8090 if (IS_HASWELL(dev))
8091 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8092 (I915_READ(IPS_CTL) & IPS_ENABLE);
8094 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8095 pipe_config->pixel_multiplier =
8096 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8098 pipe_config->pixel_multiplier = 1;
8104 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8106 struct drm_device *dev = crtc->dev;
8107 struct drm_i915_private *dev_priv = dev->dev_private;
8108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109 uint32_t cntl = 0, size = 0;
8112 unsigned int width = intel_crtc->cursor_width;
8113 unsigned int height = intel_crtc->cursor_height;
8114 unsigned int stride = roundup_pow_of_two(width) * 4;
8118 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8129 cntl |= CURSOR_ENABLE |
8130 CURSOR_GAMMA_ENABLE |
8131 CURSOR_FORMAT_ARGB |
8132 CURSOR_STRIDE(stride);
8134 size = (height << 12) | width;
8137 if (intel_crtc->cursor_cntl != 0 &&
8138 (intel_crtc->cursor_base != base ||
8139 intel_crtc->cursor_size != size ||
8140 intel_crtc->cursor_cntl != cntl)) {
8141 /* On these chipsets we can only modify the base/size/stride
8142 * whilst the cursor is disabled.
8144 I915_WRITE(_CURACNTR, 0);
8145 POSTING_READ(_CURACNTR);
8146 intel_crtc->cursor_cntl = 0;
8149 if (intel_crtc->cursor_base != base) {
8150 I915_WRITE(_CURABASE, base);
8151 intel_crtc->cursor_base = base;
8154 if (intel_crtc->cursor_size != size) {
8155 I915_WRITE(CURSIZE, size);
8156 intel_crtc->cursor_size = size;
8159 if (intel_crtc->cursor_cntl != cntl) {
8160 I915_WRITE(_CURACNTR, cntl);
8161 POSTING_READ(_CURACNTR);
8162 intel_crtc->cursor_cntl = cntl;
8166 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8168 struct drm_device *dev = crtc->dev;
8169 struct drm_i915_private *dev_priv = dev->dev_private;
8170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8171 int pipe = intel_crtc->pipe;
8176 cntl = MCURSOR_GAMMA_ENABLE;
8177 switch (intel_crtc->cursor_width) {
8179 cntl |= CURSOR_MODE_64_ARGB_AX;
8182 cntl |= CURSOR_MODE_128_ARGB_AX;
8185 cntl |= CURSOR_MODE_256_ARGB_AX;
8191 cntl |= pipe << 28; /* Connect to correct pipe */
8193 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8194 cntl |= CURSOR_PIPE_CSC_ENABLE;
8197 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8198 cntl |= CURSOR_ROTATE_180;
8200 if (intel_crtc->cursor_cntl != cntl) {
8201 I915_WRITE(CURCNTR(pipe), cntl);
8202 POSTING_READ(CURCNTR(pipe));
8203 intel_crtc->cursor_cntl = cntl;
8206 /* and commit changes on next vblank */
8207 I915_WRITE(CURBASE(pipe), base);
8208 POSTING_READ(CURBASE(pipe));
8210 intel_crtc->cursor_base = base;
8213 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8214 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8217 struct drm_device *dev = crtc->dev;
8218 struct drm_i915_private *dev_priv = dev->dev_private;
8219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8220 int pipe = intel_crtc->pipe;
8221 int x = crtc->cursor_x;
8222 int y = crtc->cursor_y;
8223 u32 base = 0, pos = 0;
8226 base = intel_crtc->cursor_addr;
8228 if (x >= intel_crtc->config.pipe_src_w)
8231 if (y >= intel_crtc->config.pipe_src_h)
8235 if (x + intel_crtc->cursor_width <= 0)
8238 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8241 pos |= x << CURSOR_X_SHIFT;
8244 if (y + intel_crtc->cursor_height <= 0)
8247 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8250 pos |= y << CURSOR_Y_SHIFT;
8252 if (base == 0 && intel_crtc->cursor_base == 0)
8255 I915_WRITE(CURPOS(pipe), pos);
8257 /* ILK+ do this automagically */
8258 if (HAS_GMCH_DISPLAY(dev) &&
8259 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8260 base += (intel_crtc->cursor_height *
8261 intel_crtc->cursor_width - 1) * 4;
8264 if (IS_845G(dev) || IS_I865G(dev))
8265 i845_update_cursor(crtc, base);
8267 i9xx_update_cursor(crtc, base);
8270 static bool cursor_size_ok(struct drm_device *dev,
8271 uint32_t width, uint32_t height)
8273 if (width == 0 || height == 0)
8277 * 845g/865g are special in that they are only limited by
8278 * the width of their cursors, the height is arbitrary up to
8279 * the precision of the register. Everything else requires
8280 * square cursors, limited to a few power-of-two sizes.
8282 if (IS_845G(dev) || IS_I865G(dev)) {
8283 if ((width & 63) != 0)
8286 if (width > (IS_845G(dev) ? 64 : 512))
8292 switch (width | height) {
8307 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8308 struct drm_i915_gem_object *obj,
8309 uint32_t width, uint32_t height)
8311 struct drm_device *dev = crtc->dev;
8312 struct drm_i915_private *dev_priv = dev->dev_private;
8313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8314 enum pipe pipe = intel_crtc->pipe;
8319 /* if we want to turn off the cursor ignore width and height */
8321 DRM_DEBUG_KMS("cursor off\n");
8323 mutex_lock(&dev->struct_mutex);
8327 /* we only need to pin inside GTT if cursor is non-phy */
8328 mutex_lock(&dev->struct_mutex);
8329 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8333 * Global gtt pte registers are special registers which actually
8334 * forward writes to a chunk of system memory. Which means that
8335 * there is no risk that the register values disappear as soon
8336 * as we call intel_runtime_pm_put(), so it is correct to wrap
8337 * only the pin/unpin/fence and not more.
8339 intel_runtime_pm_get(dev_priv);
8341 /* Note that the w/a also requires 2 PTE of padding following
8342 * the bo. We currently fill all unused PTE with the shadow
8343 * page and so we should always have valid PTE following the
8344 * cursor preventing the VT-d warning.
8347 if (need_vtd_wa(dev))
8348 alignment = 64*1024;
8350 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8352 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8353 intel_runtime_pm_put(dev_priv);
8357 ret = i915_gem_object_put_fence(obj);
8359 DRM_DEBUG_KMS("failed to release fence for cursor");
8360 intel_runtime_pm_put(dev_priv);
8364 addr = i915_gem_obj_ggtt_offset(obj);
8366 intel_runtime_pm_put(dev_priv);
8368 int align = IS_I830(dev) ? 16 * 1024 : 256;
8369 ret = i915_gem_object_attach_phys(obj, align);
8371 DRM_DEBUG_KMS("failed to attach phys object\n");
8374 addr = obj->phys_handle->busaddr;
8378 if (intel_crtc->cursor_bo) {
8379 if (!INTEL_INFO(dev)->cursor_needs_physical)
8380 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8383 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8384 INTEL_FRONTBUFFER_CURSOR(pipe));
8385 mutex_unlock(&dev->struct_mutex);
8387 old_width = intel_crtc->cursor_width;
8389 intel_crtc->cursor_addr = addr;
8390 intel_crtc->cursor_bo = obj;
8391 intel_crtc->cursor_width = width;
8392 intel_crtc->cursor_height = height;
8394 if (intel_crtc->active) {
8395 if (old_width != width)
8396 intel_update_watermarks(crtc);
8397 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8399 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8404 i915_gem_object_unpin_from_display_plane(obj);
8406 mutex_unlock(&dev->struct_mutex);
8410 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8411 u16 *blue, uint32_t start, uint32_t size)
8413 int end = (start + size > 256) ? 256 : start + size, i;
8414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8416 for (i = start; i < end; i++) {
8417 intel_crtc->lut_r[i] = red[i] >> 8;
8418 intel_crtc->lut_g[i] = green[i] >> 8;
8419 intel_crtc->lut_b[i] = blue[i] >> 8;
8422 intel_crtc_load_lut(crtc);
8425 /* VESA 640x480x72Hz mode to set on the pipe */
8426 static struct drm_display_mode load_detect_mode = {
8427 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8428 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8431 struct drm_framebuffer *
8432 __intel_framebuffer_create(struct drm_device *dev,
8433 struct drm_mode_fb_cmd2 *mode_cmd,
8434 struct drm_i915_gem_object *obj)
8436 struct intel_framebuffer *intel_fb;
8439 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8441 drm_gem_object_unreference_unlocked(&obj->base);
8442 return ERR_PTR(-ENOMEM);
8445 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8449 return &intel_fb->base;
8451 drm_gem_object_unreference_unlocked(&obj->base);
8454 return ERR_PTR(ret);
8457 static struct drm_framebuffer *
8458 intel_framebuffer_create(struct drm_device *dev,
8459 struct drm_mode_fb_cmd2 *mode_cmd,
8460 struct drm_i915_gem_object *obj)
8462 struct drm_framebuffer *fb;
8465 ret = i915_mutex_lock_interruptible(dev);
8467 return ERR_PTR(ret);
8468 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8469 mutex_unlock(&dev->struct_mutex);
8475 intel_framebuffer_pitch_for_width(int width, int bpp)
8477 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8478 return ALIGN(pitch, 64);
8482 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8484 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8485 return PAGE_ALIGN(pitch * mode->vdisplay);
8488 static struct drm_framebuffer *
8489 intel_framebuffer_create_for_mode(struct drm_device *dev,
8490 struct drm_display_mode *mode,
8493 struct drm_i915_gem_object *obj;
8494 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8496 obj = i915_gem_alloc_object(dev,
8497 intel_framebuffer_size_for_mode(mode, bpp));
8499 return ERR_PTR(-ENOMEM);
8501 mode_cmd.width = mode->hdisplay;
8502 mode_cmd.height = mode->vdisplay;
8503 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8505 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8507 return intel_framebuffer_create(dev, &mode_cmd, obj);
8510 static struct drm_framebuffer *
8511 mode_fits_in_fbdev(struct drm_device *dev,
8512 struct drm_display_mode *mode)
8514 #ifdef CONFIG_DRM_I915_FBDEV
8515 struct drm_i915_private *dev_priv = dev->dev_private;
8516 struct drm_i915_gem_object *obj;
8517 struct drm_framebuffer *fb;
8519 if (!dev_priv->fbdev)
8522 if (!dev_priv->fbdev->fb)
8525 obj = dev_priv->fbdev->fb->obj;
8528 fb = &dev_priv->fbdev->fb->base;
8529 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8530 fb->bits_per_pixel))
8533 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8542 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8543 struct drm_display_mode *mode,
8544 struct intel_load_detect_pipe *old,
8545 struct drm_modeset_acquire_ctx *ctx)
8547 struct intel_crtc *intel_crtc;
8548 struct intel_encoder *intel_encoder =
8549 intel_attached_encoder(connector);
8550 struct drm_crtc *possible_crtc;
8551 struct drm_encoder *encoder = &intel_encoder->base;
8552 struct drm_crtc *crtc = NULL;
8553 struct drm_device *dev = encoder->dev;
8554 struct drm_framebuffer *fb;
8555 struct drm_mode_config *config = &dev->mode_config;
8558 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8559 connector->base.id, connector->name,
8560 encoder->base.id, encoder->name);
8563 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8568 * Algorithm gets a little messy:
8570 * - if the connector already has an assigned crtc, use it (but make
8571 * sure it's on first)
8573 * - try to find the first unused crtc that can drive this connector,
8574 * and use that if we find one
8577 /* See if we already have a CRTC for this connector */
8578 if (encoder->crtc) {
8579 crtc = encoder->crtc;
8581 ret = drm_modeset_lock(&crtc->mutex, ctx);
8585 old->dpms_mode = connector->dpms;
8586 old->load_detect_temp = false;
8588 /* Make sure the crtc and connector are running */
8589 if (connector->dpms != DRM_MODE_DPMS_ON)
8590 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8595 /* Find an unused one (if possible) */
8596 for_each_crtc(dev, possible_crtc) {
8598 if (!(encoder->possible_crtcs & (1 << i)))
8600 if (possible_crtc->enabled)
8602 /* This can occur when applying the pipe A quirk on resume. */
8603 if (to_intel_crtc(possible_crtc)->new_enabled)
8606 crtc = possible_crtc;
8611 * If we didn't find an unused CRTC, don't use any.
8614 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8618 ret = drm_modeset_lock(&crtc->mutex, ctx);
8621 intel_encoder->new_crtc = to_intel_crtc(crtc);
8622 to_intel_connector(connector)->new_encoder = intel_encoder;
8624 intel_crtc = to_intel_crtc(crtc);
8625 intel_crtc->new_enabled = true;
8626 intel_crtc->new_config = &intel_crtc->config;
8627 old->dpms_mode = connector->dpms;
8628 old->load_detect_temp = true;
8629 old->release_fb = NULL;
8632 mode = &load_detect_mode;
8634 /* We need a framebuffer large enough to accommodate all accesses
8635 * that the plane may generate whilst we perform load detection.
8636 * We can not rely on the fbcon either being present (we get called
8637 * during its initialisation to detect all boot displays, or it may
8638 * not even exist) or that it is large enough to satisfy the
8641 fb = mode_fits_in_fbdev(dev, mode);
8643 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8644 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8645 old->release_fb = fb;
8647 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8649 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8653 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8654 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8655 if (old->release_fb)
8656 old->release_fb->funcs->destroy(old->release_fb);
8660 /* let the connector get through one full cycle before testing */
8661 intel_wait_for_vblank(dev, intel_crtc->pipe);
8665 intel_crtc->new_enabled = crtc->enabled;
8666 if (intel_crtc->new_enabled)
8667 intel_crtc->new_config = &intel_crtc->config;
8669 intel_crtc->new_config = NULL;
8671 if (ret == -EDEADLK) {
8672 drm_modeset_backoff(ctx);
8679 void intel_release_load_detect_pipe(struct drm_connector *connector,
8680 struct intel_load_detect_pipe *old)
8682 struct intel_encoder *intel_encoder =
8683 intel_attached_encoder(connector);
8684 struct drm_encoder *encoder = &intel_encoder->base;
8685 struct drm_crtc *crtc = encoder->crtc;
8686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8688 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8689 connector->base.id, connector->name,
8690 encoder->base.id, encoder->name);
8692 if (old->load_detect_temp) {
8693 to_intel_connector(connector)->new_encoder = NULL;
8694 intel_encoder->new_crtc = NULL;
8695 intel_crtc->new_enabled = false;
8696 intel_crtc->new_config = NULL;
8697 intel_set_mode(crtc, NULL, 0, 0, NULL);
8699 if (old->release_fb) {
8700 drm_framebuffer_unregister_private(old->release_fb);
8701 drm_framebuffer_unreference(old->release_fb);
8707 /* Switch crtc and encoder back off if necessary */
8708 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8709 connector->funcs->dpms(connector, old->dpms_mode);
8712 static int i9xx_pll_refclk(struct drm_device *dev,
8713 const struct intel_crtc_config *pipe_config)
8715 struct drm_i915_private *dev_priv = dev->dev_private;
8716 u32 dpll = pipe_config->dpll_hw_state.dpll;
8718 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8719 return dev_priv->vbt.lvds_ssc_freq;
8720 else if (HAS_PCH_SPLIT(dev))
8722 else if (!IS_GEN2(dev))
8728 /* Returns the clock of the currently programmed mode of the given pipe. */
8729 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8730 struct intel_crtc_config *pipe_config)
8732 struct drm_device *dev = crtc->base.dev;
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734 int pipe = pipe_config->cpu_transcoder;
8735 u32 dpll = pipe_config->dpll_hw_state.dpll;
8737 intel_clock_t clock;
8738 int refclk = i9xx_pll_refclk(dev, pipe_config);
8740 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8741 fp = pipe_config->dpll_hw_state.fp0;
8743 fp = pipe_config->dpll_hw_state.fp1;
8745 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8746 if (IS_PINEVIEW(dev)) {
8747 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8748 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8750 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8751 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8754 if (!IS_GEN2(dev)) {
8755 if (IS_PINEVIEW(dev))
8756 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8757 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8759 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8760 DPLL_FPA01_P1_POST_DIV_SHIFT);
8762 switch (dpll & DPLL_MODE_MASK) {
8763 case DPLLB_MODE_DAC_SERIAL:
8764 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8767 case DPLLB_MODE_LVDS:
8768 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8772 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8773 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8777 if (IS_PINEVIEW(dev))
8778 pineview_clock(refclk, &clock);
8780 i9xx_clock(refclk, &clock);
8782 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8783 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8786 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8787 DPLL_FPA01_P1_POST_DIV_SHIFT);
8789 if (lvds & LVDS_CLKB_POWER_UP)
8794 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8797 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8798 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8800 if (dpll & PLL_P2_DIVIDE_BY_4)
8806 i9xx_clock(refclk, &clock);
8810 * This value includes pixel_multiplier. We will use
8811 * port_clock to compute adjusted_mode.crtc_clock in the
8812 * encoder's get_config() function.
8814 pipe_config->port_clock = clock.dot;
8817 int intel_dotclock_calculate(int link_freq,
8818 const struct intel_link_m_n *m_n)
8821 * The calculation for the data clock is:
8822 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8823 * But we want to avoid losing precison if possible, so:
8824 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8826 * and the link clock is simpler:
8827 * link_clock = (m * link_clock) / n
8833 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8836 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8837 struct intel_crtc_config *pipe_config)
8839 struct drm_device *dev = crtc->base.dev;
8841 /* read out port_clock from the DPLL */
8842 i9xx_crtc_clock_get(crtc, pipe_config);
8845 * This value does not include pixel_multiplier.
8846 * We will check that port_clock and adjusted_mode.crtc_clock
8847 * agree once we know their relationship in the encoder's
8848 * get_config() function.
8850 pipe_config->adjusted_mode.crtc_clock =
8851 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8852 &pipe_config->fdi_m_n);
8855 /** Returns the currently programmed mode of the given pipe. */
8856 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8857 struct drm_crtc *crtc)
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8861 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8862 struct drm_display_mode *mode;
8863 struct intel_crtc_config pipe_config;
8864 int htot = I915_READ(HTOTAL(cpu_transcoder));
8865 int hsync = I915_READ(HSYNC(cpu_transcoder));
8866 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8867 int vsync = I915_READ(VSYNC(cpu_transcoder));
8868 enum pipe pipe = intel_crtc->pipe;
8870 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8875 * Construct a pipe_config sufficient for getting the clock info
8876 * back out of crtc_clock_get.
8878 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8879 * to use a real value here instead.
8881 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8882 pipe_config.pixel_multiplier = 1;
8883 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8884 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8885 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8886 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8888 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8889 mode->hdisplay = (htot & 0xffff) + 1;
8890 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8891 mode->hsync_start = (hsync & 0xffff) + 1;
8892 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8893 mode->vdisplay = (vtot & 0xffff) + 1;
8894 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8895 mode->vsync_start = (vsync & 0xffff) + 1;
8896 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8898 drm_mode_set_name(mode);
8903 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8905 struct drm_device *dev = crtc->dev;
8906 struct drm_i915_private *dev_priv = dev->dev_private;
8907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8909 if (!HAS_GMCH_DISPLAY(dev))
8912 if (!dev_priv->lvds_downclock_avail)
8916 * Since this is called by a timer, we should never get here in
8919 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8920 int pipe = intel_crtc->pipe;
8921 int dpll_reg = DPLL(pipe);
8924 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8926 assert_panel_unlocked(dev_priv, pipe);
8928 dpll = I915_READ(dpll_reg);
8929 dpll |= DISPLAY_RATE_SELECT_FPA1;
8930 I915_WRITE(dpll_reg, dpll);
8931 intel_wait_for_vblank(dev, pipe);
8932 dpll = I915_READ(dpll_reg);
8933 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8934 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8939 void intel_mark_busy(struct drm_device *dev)
8941 struct drm_i915_private *dev_priv = dev->dev_private;
8943 if (dev_priv->mm.busy)
8946 intel_runtime_pm_get(dev_priv);
8947 i915_update_gfx_val(dev_priv);
8948 dev_priv->mm.busy = true;
8951 void intel_mark_idle(struct drm_device *dev)
8953 struct drm_i915_private *dev_priv = dev->dev_private;
8954 struct drm_crtc *crtc;
8956 if (!dev_priv->mm.busy)
8959 dev_priv->mm.busy = false;
8961 if (!i915.powersave)
8964 for_each_crtc(dev, crtc) {
8965 if (!crtc->primary->fb)
8968 intel_decrease_pllclock(crtc);
8971 if (INTEL_INFO(dev)->gen >= 6)
8972 gen6_rps_idle(dev->dev_private);
8975 intel_runtime_pm_put(dev_priv);
8978 static void intel_crtc_destroy(struct drm_crtc *crtc)
8980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8981 struct drm_device *dev = crtc->dev;
8982 struct intel_unpin_work *work;
8984 spin_lock_irq(&dev->event_lock);
8985 work = intel_crtc->unpin_work;
8986 intel_crtc->unpin_work = NULL;
8987 spin_unlock_irq(&dev->event_lock);
8990 cancel_work_sync(&work->work);
8994 drm_crtc_cleanup(crtc);
8999 static void intel_unpin_work_fn(struct work_struct *__work)
9001 struct intel_unpin_work *work =
9002 container_of(__work, struct intel_unpin_work, work);
9003 struct drm_device *dev = work->crtc->dev;
9004 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9006 mutex_lock(&dev->struct_mutex);
9007 intel_unpin_fb_obj(work->old_fb_obj);
9008 drm_gem_object_unreference(&work->pending_flip_obj->base);
9009 drm_gem_object_unreference(&work->old_fb_obj->base);
9011 intel_update_fbc(dev);
9012 mutex_unlock(&dev->struct_mutex);
9014 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9016 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9017 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9022 static void do_intel_finish_page_flip(struct drm_device *dev,
9023 struct drm_crtc *crtc)
9025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9026 struct intel_unpin_work *work;
9027 unsigned long flags;
9029 /* Ignore early vblank irqs */
9030 if (intel_crtc == NULL)
9034 * This is called both by irq handlers and the reset code (to complete
9035 * lost pageflips) so needs the full irqsave spinlocks.
9037 spin_lock_irqsave(&dev->event_lock, flags);
9038 work = intel_crtc->unpin_work;
9040 /* Ensure we don't miss a work->pending update ... */
9043 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9044 spin_unlock_irqrestore(&dev->event_lock, flags);
9048 page_flip_completed(intel_crtc);
9050 spin_unlock_irqrestore(&dev->event_lock, flags);
9053 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9055 struct drm_i915_private *dev_priv = dev->dev_private;
9056 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9058 do_intel_finish_page_flip(dev, crtc);
9061 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9063 struct drm_i915_private *dev_priv = dev->dev_private;
9064 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9066 do_intel_finish_page_flip(dev, crtc);
9069 /* Is 'a' after or equal to 'b'? */
9070 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9072 return !((a - b) & 0x80000000);
9075 static bool page_flip_finished(struct intel_crtc *crtc)
9077 struct drm_device *dev = crtc->base.dev;
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9081 * The relevant registers doen't exist on pre-ctg.
9082 * As the flip done interrupt doesn't trigger for mmio
9083 * flips on gmch platforms, a flip count check isn't
9084 * really needed there. But since ctg has the registers,
9085 * include it in the check anyway.
9087 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9091 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9092 * used the same base address. In that case the mmio flip might
9093 * have completed, but the CS hasn't even executed the flip yet.
9095 * A flip count check isn't enough as the CS might have updated
9096 * the base address just after start of vblank, but before we
9097 * managed to process the interrupt. This means we'd complete the
9100 * Combining both checks should get us a good enough result. It may
9101 * still happen that the CS flip has been executed, but has not
9102 * yet actually completed. But in case the base address is the same
9103 * anyway, we don't really care.
9105 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9106 crtc->unpin_work->gtt_offset &&
9107 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9108 crtc->unpin_work->flip_count);
9111 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 struct intel_crtc *intel_crtc =
9115 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9116 unsigned long flags;
9120 * This is called both by irq handlers and the reset code (to complete
9121 * lost pageflips) so needs the full irqsave spinlocks.
9123 * NB: An MMIO update of the plane base pointer will also
9124 * generate a page-flip completion irq, i.e. every modeset
9125 * is also accompanied by a spurious intel_prepare_page_flip().
9127 spin_lock_irqsave(&dev->event_lock, flags);
9128 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9129 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9130 spin_unlock_irqrestore(&dev->event_lock, flags);
9133 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9135 /* Ensure that the work item is consistent when activating it ... */
9137 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9138 /* and that it is marked active as soon as the irq could fire. */
9142 static int intel_gen2_queue_flip(struct drm_device *dev,
9143 struct drm_crtc *crtc,
9144 struct drm_framebuffer *fb,
9145 struct drm_i915_gem_object *obj,
9146 struct intel_engine_cs *ring,
9149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9153 ret = intel_ring_begin(ring, 6);
9157 /* Can't queue multiple flips, so wait for the previous
9158 * one to finish before executing the next.
9160 if (intel_crtc->plane)
9161 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9163 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9164 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9165 intel_ring_emit(ring, MI_NOOP);
9166 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9167 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9168 intel_ring_emit(ring, fb->pitches[0]);
9169 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9170 intel_ring_emit(ring, 0); /* aux display base address, unused */
9172 intel_mark_page_flip_active(intel_crtc);
9173 __intel_ring_advance(ring);
9177 static int intel_gen3_queue_flip(struct drm_device *dev,
9178 struct drm_crtc *crtc,
9179 struct drm_framebuffer *fb,
9180 struct drm_i915_gem_object *obj,
9181 struct intel_engine_cs *ring,
9184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9188 ret = intel_ring_begin(ring, 6);
9192 if (intel_crtc->plane)
9193 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9195 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9196 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9197 intel_ring_emit(ring, MI_NOOP);
9198 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9199 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9200 intel_ring_emit(ring, fb->pitches[0]);
9201 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9202 intel_ring_emit(ring, MI_NOOP);
9204 intel_mark_page_flip_active(intel_crtc);
9205 __intel_ring_advance(ring);
9209 static int intel_gen4_queue_flip(struct drm_device *dev,
9210 struct drm_crtc *crtc,
9211 struct drm_framebuffer *fb,
9212 struct drm_i915_gem_object *obj,
9213 struct intel_engine_cs *ring,
9216 struct drm_i915_private *dev_priv = dev->dev_private;
9217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9218 uint32_t pf, pipesrc;
9221 ret = intel_ring_begin(ring, 4);
9225 /* i965+ uses the linear or tiled offsets from the
9226 * Display Registers (which do not change across a page-flip)
9227 * so we need only reprogram the base address.
9229 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9230 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9231 intel_ring_emit(ring, fb->pitches[0]);
9232 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9235 /* XXX Enabling the panel-fitter across page-flip is so far
9236 * untested on non-native modes, so ignore it for now.
9237 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9240 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9241 intel_ring_emit(ring, pf | pipesrc);
9243 intel_mark_page_flip_active(intel_crtc);
9244 __intel_ring_advance(ring);
9248 static int intel_gen6_queue_flip(struct drm_device *dev,
9249 struct drm_crtc *crtc,
9250 struct drm_framebuffer *fb,
9251 struct drm_i915_gem_object *obj,
9252 struct intel_engine_cs *ring,
9255 struct drm_i915_private *dev_priv = dev->dev_private;
9256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9257 uint32_t pf, pipesrc;
9260 ret = intel_ring_begin(ring, 4);
9264 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9265 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9266 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9267 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9269 /* Contrary to the suggestions in the documentation,
9270 * "Enable Panel Fitter" does not seem to be required when page
9271 * flipping with a non-native mode, and worse causes a normal
9273 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9276 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9277 intel_ring_emit(ring, pf | pipesrc);
9279 intel_mark_page_flip_active(intel_crtc);
9280 __intel_ring_advance(ring);
9284 static int intel_gen7_queue_flip(struct drm_device *dev,
9285 struct drm_crtc *crtc,
9286 struct drm_framebuffer *fb,
9287 struct drm_i915_gem_object *obj,
9288 struct intel_engine_cs *ring,
9291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9292 uint32_t plane_bit = 0;
9295 switch (intel_crtc->plane) {
9297 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9300 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9303 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9306 WARN_ONCE(1, "unknown plane in flip command\n");
9311 if (ring->id == RCS) {
9314 * On Gen 8, SRM is now taking an extra dword to accommodate
9315 * 48bits addresses, and we need a NOOP for the batch size to
9323 * BSpec MI_DISPLAY_FLIP for IVB:
9324 * "The full packet must be contained within the same cache line."
9326 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9327 * cacheline, if we ever start emitting more commands before
9328 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9329 * then do the cacheline alignment, and finally emit the
9332 ret = intel_ring_cacheline_align(ring);
9336 ret = intel_ring_begin(ring, len);
9340 /* Unmask the flip-done completion message. Note that the bspec says that
9341 * we should do this for both the BCS and RCS, and that we must not unmask
9342 * more than one flip event at any time (or ensure that one flip message
9343 * can be sent by waiting for flip-done prior to queueing new flips).
9344 * Experimentation says that BCS works despite DERRMR masking all
9345 * flip-done completion events and that unmasking all planes at once
9346 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9347 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9349 if (ring->id == RCS) {
9350 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9351 intel_ring_emit(ring, DERRMR);
9352 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9353 DERRMR_PIPEB_PRI_FLIP_DONE |
9354 DERRMR_PIPEC_PRI_FLIP_DONE));
9356 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9357 MI_SRM_LRM_GLOBAL_GTT);
9359 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9360 MI_SRM_LRM_GLOBAL_GTT);
9361 intel_ring_emit(ring, DERRMR);
9362 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9364 intel_ring_emit(ring, 0);
9365 intel_ring_emit(ring, MI_NOOP);
9369 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9370 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9371 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9372 intel_ring_emit(ring, (MI_NOOP));
9374 intel_mark_page_flip_active(intel_crtc);
9375 __intel_ring_advance(ring);
9379 static bool use_mmio_flip(struct intel_engine_cs *ring,
9380 struct drm_i915_gem_object *obj)
9383 * This is not being used for older platforms, because
9384 * non-availability of flip done interrupt forces us to use
9385 * CS flips. Older platforms derive flip done using some clever
9386 * tricks involving the flip_pending status bits and vblank irqs.
9387 * So using MMIO flips there would disrupt this mechanism.
9393 if (INTEL_INFO(ring->dev)->gen < 5)
9396 if (i915.use_mmio_flip < 0)
9398 else if (i915.use_mmio_flip > 0)
9400 else if (i915.enable_execlists)
9403 return ring != obj->ring;
9406 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9408 struct drm_device *dev = intel_crtc->base.dev;
9409 struct drm_i915_private *dev_priv = dev->dev_private;
9410 struct intel_framebuffer *intel_fb =
9411 to_intel_framebuffer(intel_crtc->base.primary->fb);
9412 struct drm_i915_gem_object *obj = intel_fb->obj;
9416 intel_mark_page_flip_active(intel_crtc);
9418 reg = DSPCNTR(intel_crtc->plane);
9419 dspcntr = I915_READ(reg);
9421 if (obj->tiling_mode != I915_TILING_NONE)
9422 dspcntr |= DISPPLANE_TILED;
9424 dspcntr &= ~DISPPLANE_TILED;
9426 I915_WRITE(reg, dspcntr);
9428 I915_WRITE(DSPSURF(intel_crtc->plane),
9429 intel_crtc->unpin_work->gtt_offset);
9430 POSTING_READ(DSPSURF(intel_crtc->plane));
9433 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9435 struct intel_engine_cs *ring;
9438 lockdep_assert_held(&obj->base.dev->struct_mutex);
9440 if (!obj->last_write_seqno)
9445 if (i915_seqno_passed(ring->get_seqno(ring, true),
9446 obj->last_write_seqno))
9449 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9453 if (WARN_ON(!ring->irq_get(ring)))
9459 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9461 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9462 struct intel_crtc *intel_crtc;
9463 unsigned long irq_flags;
9466 seqno = ring->get_seqno(ring, false);
9468 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9469 for_each_intel_crtc(ring->dev, intel_crtc) {
9470 struct intel_mmio_flip *mmio_flip;
9472 mmio_flip = &intel_crtc->mmio_flip;
9473 if (mmio_flip->seqno == 0)
9476 if (ring->id != mmio_flip->ring_id)
9479 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9480 intel_do_mmio_flip(intel_crtc);
9481 mmio_flip->seqno = 0;
9482 ring->irq_put(ring);
9485 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9488 static int intel_queue_mmio_flip(struct drm_device *dev,
9489 struct drm_crtc *crtc,
9490 struct drm_framebuffer *fb,
9491 struct drm_i915_gem_object *obj,
9492 struct intel_engine_cs *ring,
9495 struct drm_i915_private *dev_priv = dev->dev_private;
9496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9499 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9502 ret = intel_postpone_flip(obj);
9506 intel_do_mmio_flip(intel_crtc);
9510 spin_lock_irq(&dev_priv->mmio_flip_lock);
9511 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9512 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9513 spin_unlock_irq(&dev_priv->mmio_flip_lock);
9516 * Double check to catch cases where irq fired before
9517 * mmio flip data was ready
9519 intel_notify_mmio_flip(obj->ring);
9523 static int intel_default_queue_flip(struct drm_device *dev,
9524 struct drm_crtc *crtc,
9525 struct drm_framebuffer *fb,
9526 struct drm_i915_gem_object *obj,
9527 struct intel_engine_cs *ring,
9533 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9534 struct drm_crtc *crtc)
9536 struct drm_i915_private *dev_priv = dev->dev_private;
9537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9538 struct intel_unpin_work *work = intel_crtc->unpin_work;
9541 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9544 if (!work->enable_stall_check)
9547 if (work->flip_ready_vblank == 0) {
9548 if (work->flip_queued_ring &&
9549 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9550 work->flip_queued_seqno))
9553 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9556 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9559 /* Potential stall - if we see that the flip has happened,
9560 * assume a missed interrupt. */
9561 if (INTEL_INFO(dev)->gen >= 4)
9562 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9564 addr = I915_READ(DSPADDR(intel_crtc->plane));
9566 /* There is a potential issue here with a false positive after a flip
9567 * to the same address. We could address this by checking for a
9568 * non-incrementing frame counter.
9570 return addr == work->gtt_offset;
9573 void intel_check_page_flip(struct drm_device *dev, int pipe)
9575 struct drm_i915_private *dev_priv = dev->dev_private;
9576 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9584 spin_lock(&dev->event_lock);
9585 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9586 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9587 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9588 page_flip_completed(intel_crtc);
9590 spin_unlock(&dev->event_lock);
9593 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9594 struct drm_framebuffer *fb,
9595 struct drm_pending_vblank_event *event,
9596 uint32_t page_flip_flags)
9598 struct drm_device *dev = crtc->dev;
9599 struct drm_i915_private *dev_priv = dev->dev_private;
9600 struct drm_framebuffer *old_fb = crtc->primary->fb;
9601 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9603 enum pipe pipe = intel_crtc->pipe;
9604 struct intel_unpin_work *work;
9605 struct intel_engine_cs *ring;
9609 * drm_mode_page_flip_ioctl() should already catch this, but double
9610 * check to be safe. In the future we may enable pageflipping from
9611 * a disabled primary plane.
9613 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9616 /* Can't change pixel format via MI display flips. */
9617 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9621 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9622 * Note that pitch changes could also affect these register.
9624 if (INTEL_INFO(dev)->gen > 3 &&
9625 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9626 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9629 if (i915_terminally_wedged(&dev_priv->gpu_error))
9632 work = kzalloc(sizeof(*work), GFP_KERNEL);
9636 work->event = event;
9638 work->old_fb_obj = intel_fb_obj(old_fb);
9639 INIT_WORK(&work->work, intel_unpin_work_fn);
9641 ret = drm_crtc_vblank_get(crtc);
9645 /* We borrow the event spin lock for protecting unpin_work */
9646 spin_lock_irq(&dev->event_lock);
9647 if (intel_crtc->unpin_work) {
9648 /* Before declaring the flip queue wedged, check if
9649 * the hardware completed the operation behind our backs.
9651 if (__intel_pageflip_stall_check(dev, crtc)) {
9652 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9653 page_flip_completed(intel_crtc);
9655 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9656 spin_unlock_irq(&dev->event_lock);
9658 drm_crtc_vblank_put(crtc);
9663 intel_crtc->unpin_work = work;
9664 spin_unlock_irq(&dev->event_lock);
9666 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9667 flush_workqueue(dev_priv->wq);
9669 ret = i915_mutex_lock_interruptible(dev);
9673 /* Reference the objects for the scheduled work. */
9674 drm_gem_object_reference(&work->old_fb_obj->base);
9675 drm_gem_object_reference(&obj->base);
9677 crtc->primary->fb = fb;
9679 work->pending_flip_obj = obj;
9681 atomic_inc(&intel_crtc->unpin_work_count);
9682 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9684 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9685 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9687 if (IS_VALLEYVIEW(dev)) {
9688 ring = &dev_priv->ring[BCS];
9689 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9690 /* vlv: DISPLAY_FLIP fails to change tiling */
9692 } else if (IS_IVYBRIDGE(dev)) {
9693 ring = &dev_priv->ring[BCS];
9694 } else if (INTEL_INFO(dev)->gen >= 7) {
9696 if (ring == NULL || ring->id != RCS)
9697 ring = &dev_priv->ring[BCS];
9699 ring = &dev_priv->ring[RCS];
9702 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9704 goto cleanup_pending;
9707 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9709 if (use_mmio_flip(ring, obj)) {
9710 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9715 work->flip_queued_seqno = obj->last_write_seqno;
9716 work->flip_queued_ring = obj->ring;
9718 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9723 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9724 work->flip_queued_ring = ring;
9727 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9728 work->enable_stall_check = true;
9730 i915_gem_track_fb(work->old_fb_obj, obj,
9731 INTEL_FRONTBUFFER_PRIMARY(pipe));
9733 intel_disable_fbc(dev);
9734 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9735 mutex_unlock(&dev->struct_mutex);
9737 trace_i915_flip_request(intel_crtc->plane, obj);
9742 intel_unpin_fb_obj(obj);
9744 atomic_dec(&intel_crtc->unpin_work_count);
9745 crtc->primary->fb = old_fb;
9746 drm_gem_object_unreference(&work->old_fb_obj->base);
9747 drm_gem_object_unreference(&obj->base);
9748 mutex_unlock(&dev->struct_mutex);
9751 spin_lock_irq(&dev->event_lock);
9752 intel_crtc->unpin_work = NULL;
9753 spin_unlock_irq(&dev->event_lock);
9755 drm_crtc_vblank_put(crtc);
9761 intel_crtc_wait_for_pending_flips(crtc);
9762 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9763 if (ret == 0 && event) {
9764 spin_lock_irq(&dev->event_lock);
9765 drm_send_vblank_event(dev, pipe, event);
9766 spin_unlock_irq(&dev->event_lock);
9772 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9773 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9774 .load_lut = intel_crtc_load_lut,
9778 * intel_modeset_update_staged_output_state
9780 * Updates the staged output configuration state, e.g. after we've read out the
9783 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9785 struct intel_crtc *crtc;
9786 struct intel_encoder *encoder;
9787 struct intel_connector *connector;
9789 list_for_each_entry(connector, &dev->mode_config.connector_list,
9791 connector->new_encoder =
9792 to_intel_encoder(connector->base.encoder);
9795 for_each_intel_encoder(dev, encoder) {
9797 to_intel_crtc(encoder->base.crtc);
9800 for_each_intel_crtc(dev, crtc) {
9801 crtc->new_enabled = crtc->base.enabled;
9803 if (crtc->new_enabled)
9804 crtc->new_config = &crtc->config;
9806 crtc->new_config = NULL;
9811 * intel_modeset_commit_output_state
9813 * This function copies the stage display pipe configuration to the real one.
9815 static void intel_modeset_commit_output_state(struct drm_device *dev)
9817 struct intel_crtc *crtc;
9818 struct intel_encoder *encoder;
9819 struct intel_connector *connector;
9821 list_for_each_entry(connector, &dev->mode_config.connector_list,
9823 connector->base.encoder = &connector->new_encoder->base;
9826 for_each_intel_encoder(dev, encoder) {
9827 encoder->base.crtc = &encoder->new_crtc->base;
9830 for_each_intel_crtc(dev, crtc) {
9831 crtc->base.enabled = crtc->new_enabled;
9836 connected_sink_compute_bpp(struct intel_connector *connector,
9837 struct intel_crtc_config *pipe_config)
9839 int bpp = pipe_config->pipe_bpp;
9841 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9842 connector->base.base.id,
9843 connector->base.name);
9845 /* Don't use an invalid EDID bpc value */
9846 if (connector->base.display_info.bpc &&
9847 connector->base.display_info.bpc * 3 < bpp) {
9848 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9849 bpp, connector->base.display_info.bpc*3);
9850 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9853 /* Clamp bpp to 8 on screens without EDID 1.4 */
9854 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9855 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9857 pipe_config->pipe_bpp = 24;
9862 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9863 struct drm_framebuffer *fb,
9864 struct intel_crtc_config *pipe_config)
9866 struct drm_device *dev = crtc->base.dev;
9867 struct intel_connector *connector;
9870 switch (fb->pixel_format) {
9872 bpp = 8*3; /* since we go through a colormap */
9874 case DRM_FORMAT_XRGB1555:
9875 case DRM_FORMAT_ARGB1555:
9876 /* checked in intel_framebuffer_init already */
9877 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9879 case DRM_FORMAT_RGB565:
9880 bpp = 6*3; /* min is 18bpp */
9882 case DRM_FORMAT_XBGR8888:
9883 case DRM_FORMAT_ABGR8888:
9884 /* checked in intel_framebuffer_init already */
9885 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9887 case DRM_FORMAT_XRGB8888:
9888 case DRM_FORMAT_ARGB8888:
9891 case DRM_FORMAT_XRGB2101010:
9892 case DRM_FORMAT_ARGB2101010:
9893 case DRM_FORMAT_XBGR2101010:
9894 case DRM_FORMAT_ABGR2101010:
9895 /* checked in intel_framebuffer_init already */
9896 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9900 /* TODO: gen4+ supports 16 bpc floating point, too. */
9902 DRM_DEBUG_KMS("unsupported depth\n");
9906 pipe_config->pipe_bpp = bpp;
9908 /* Clamp display bpp to EDID value */
9909 list_for_each_entry(connector, &dev->mode_config.connector_list,
9911 if (!connector->new_encoder ||
9912 connector->new_encoder->new_crtc != crtc)
9915 connected_sink_compute_bpp(connector, pipe_config);
9921 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9923 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9924 "type: 0x%x flags: 0x%x\n",
9926 mode->crtc_hdisplay, mode->crtc_hsync_start,
9927 mode->crtc_hsync_end, mode->crtc_htotal,
9928 mode->crtc_vdisplay, mode->crtc_vsync_start,
9929 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9932 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9933 struct intel_crtc_config *pipe_config,
9934 const char *context)
9936 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9937 context, pipe_name(crtc->pipe));
9939 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9940 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9941 pipe_config->pipe_bpp, pipe_config->dither);
9942 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9943 pipe_config->has_pch_encoder,
9944 pipe_config->fdi_lanes,
9945 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9946 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9947 pipe_config->fdi_m_n.tu);
9948 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9949 pipe_config->has_dp_encoder,
9950 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9951 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9952 pipe_config->dp_m_n.tu);
9954 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9955 pipe_config->has_dp_encoder,
9956 pipe_config->dp_m2_n2.gmch_m,
9957 pipe_config->dp_m2_n2.gmch_n,
9958 pipe_config->dp_m2_n2.link_m,
9959 pipe_config->dp_m2_n2.link_n,
9960 pipe_config->dp_m2_n2.tu);
9962 DRM_DEBUG_KMS("requested mode:\n");
9963 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9964 DRM_DEBUG_KMS("adjusted mode:\n");
9965 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9966 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9967 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9968 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9969 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9970 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9971 pipe_config->gmch_pfit.control,
9972 pipe_config->gmch_pfit.pgm_ratios,
9973 pipe_config->gmch_pfit.lvds_border_bits);
9974 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9975 pipe_config->pch_pfit.pos,
9976 pipe_config->pch_pfit.size,
9977 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9978 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9979 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9982 static bool encoders_cloneable(const struct intel_encoder *a,
9983 const struct intel_encoder *b)
9985 /* masks could be asymmetric, so check both ways */
9986 return a == b || (a->cloneable & (1 << b->type) &&
9987 b->cloneable & (1 << a->type));
9990 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9991 struct intel_encoder *encoder)
9993 struct drm_device *dev = crtc->base.dev;
9994 struct intel_encoder *source_encoder;
9996 for_each_intel_encoder(dev, source_encoder) {
9997 if (source_encoder->new_crtc != crtc)
10000 if (!encoders_cloneable(encoder, source_encoder))
10007 static bool check_encoder_cloning(struct intel_crtc *crtc)
10009 struct drm_device *dev = crtc->base.dev;
10010 struct intel_encoder *encoder;
10012 for_each_intel_encoder(dev, encoder) {
10013 if (encoder->new_crtc != crtc)
10016 if (!check_single_encoder_cloning(crtc, encoder))
10023 static struct intel_crtc_config *
10024 intel_modeset_pipe_config(struct drm_crtc *crtc,
10025 struct drm_framebuffer *fb,
10026 struct drm_display_mode *mode)
10028 struct drm_device *dev = crtc->dev;
10029 struct intel_encoder *encoder;
10030 struct intel_crtc_config *pipe_config;
10031 int plane_bpp, ret = -EINVAL;
10034 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10035 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10036 return ERR_PTR(-EINVAL);
10039 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10041 return ERR_PTR(-ENOMEM);
10043 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10044 drm_mode_copy(&pipe_config->requested_mode, mode);
10046 pipe_config->cpu_transcoder =
10047 (enum transcoder) to_intel_crtc(crtc)->pipe;
10048 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10051 * Sanitize sync polarity flags based on requested ones. If neither
10052 * positive or negative polarity is requested, treat this as meaning
10053 * negative polarity.
10055 if (!(pipe_config->adjusted_mode.flags &
10056 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10057 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10059 if (!(pipe_config->adjusted_mode.flags &
10060 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10061 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10063 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10064 * plane pixel format and any sink constraints into account. Returns the
10065 * source plane bpp so that dithering can be selected on mismatches
10066 * after encoders and crtc also have had their say. */
10067 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10073 * Determine the real pipe dimensions. Note that stereo modes can
10074 * increase the actual pipe size due to the frame doubling and
10075 * insertion of additional space for blanks between the frame. This
10076 * is stored in the crtc timings. We use the requested mode to do this
10077 * computation to clearly distinguish it from the adjusted mode, which
10078 * can be changed by the connectors in the below retry loop.
10080 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10081 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10082 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10085 /* Ensure the port clock defaults are reset when retrying. */
10086 pipe_config->port_clock = 0;
10087 pipe_config->pixel_multiplier = 1;
10089 /* Fill in default crtc timings, allow encoders to overwrite them. */
10090 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10092 /* Pass our mode to the connectors and the CRTC to give them a chance to
10093 * adjust it according to limitations or connector properties, and also
10094 * a chance to reject the mode entirely.
10096 for_each_intel_encoder(dev, encoder) {
10098 if (&encoder->new_crtc->base != crtc)
10101 if (!(encoder->compute_config(encoder, pipe_config))) {
10102 DRM_DEBUG_KMS("Encoder config failure\n");
10107 /* Set default port clock if not overwritten by the encoder. Needs to be
10108 * done afterwards in case the encoder adjusts the mode. */
10109 if (!pipe_config->port_clock)
10110 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10111 * pipe_config->pixel_multiplier;
10113 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10115 DRM_DEBUG_KMS("CRTC fixup failed\n");
10119 if (ret == RETRY) {
10120 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10125 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10127 goto encoder_retry;
10130 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10131 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10132 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10134 return pipe_config;
10136 kfree(pipe_config);
10137 return ERR_PTR(ret);
10140 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10141 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10143 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10144 unsigned *prepare_pipes, unsigned *disable_pipes)
10146 struct intel_crtc *intel_crtc;
10147 struct drm_device *dev = crtc->dev;
10148 struct intel_encoder *encoder;
10149 struct intel_connector *connector;
10150 struct drm_crtc *tmp_crtc;
10152 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10154 /* Check which crtcs have changed outputs connected to them, these need
10155 * to be part of the prepare_pipes mask. We don't (yet) support global
10156 * modeset across multiple crtcs, so modeset_pipes will only have one
10157 * bit set at most. */
10158 list_for_each_entry(connector, &dev->mode_config.connector_list,
10160 if (connector->base.encoder == &connector->new_encoder->base)
10163 if (connector->base.encoder) {
10164 tmp_crtc = connector->base.encoder->crtc;
10166 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10169 if (connector->new_encoder)
10171 1 << connector->new_encoder->new_crtc->pipe;
10174 for_each_intel_encoder(dev, encoder) {
10175 if (encoder->base.crtc == &encoder->new_crtc->base)
10178 if (encoder->base.crtc) {
10179 tmp_crtc = encoder->base.crtc;
10181 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10184 if (encoder->new_crtc)
10185 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10188 /* Check for pipes that will be enabled/disabled ... */
10189 for_each_intel_crtc(dev, intel_crtc) {
10190 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10193 if (!intel_crtc->new_enabled)
10194 *disable_pipes |= 1 << intel_crtc->pipe;
10196 *prepare_pipes |= 1 << intel_crtc->pipe;
10200 /* set_mode is also used to update properties on life display pipes. */
10201 intel_crtc = to_intel_crtc(crtc);
10202 if (intel_crtc->new_enabled)
10203 *prepare_pipes |= 1 << intel_crtc->pipe;
10206 * For simplicity do a full modeset on any pipe where the output routing
10207 * changed. We could be more clever, but that would require us to be
10208 * more careful with calling the relevant encoder->mode_set functions.
10210 if (*prepare_pipes)
10211 *modeset_pipes = *prepare_pipes;
10213 /* ... and mask these out. */
10214 *modeset_pipes &= ~(*disable_pipes);
10215 *prepare_pipes &= ~(*disable_pipes);
10218 * HACK: We don't (yet) fully support global modesets. intel_set_config
10219 * obies this rule, but the modeset restore mode of
10220 * intel_modeset_setup_hw_state does not.
10222 *modeset_pipes &= 1 << intel_crtc->pipe;
10223 *prepare_pipes &= 1 << intel_crtc->pipe;
10225 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10226 *modeset_pipes, *prepare_pipes, *disable_pipes);
10229 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10231 struct drm_encoder *encoder;
10232 struct drm_device *dev = crtc->dev;
10234 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10235 if (encoder->crtc == crtc)
10242 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10244 struct intel_encoder *intel_encoder;
10245 struct intel_crtc *intel_crtc;
10246 struct drm_connector *connector;
10248 for_each_intel_encoder(dev, intel_encoder) {
10249 if (!intel_encoder->base.crtc)
10252 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10254 if (prepare_pipes & (1 << intel_crtc->pipe))
10255 intel_encoder->connectors_active = false;
10258 intel_modeset_commit_output_state(dev);
10260 /* Double check state. */
10261 for_each_intel_crtc(dev, intel_crtc) {
10262 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10263 WARN_ON(intel_crtc->new_config &&
10264 intel_crtc->new_config != &intel_crtc->config);
10265 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10268 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10269 if (!connector->encoder || !connector->encoder->crtc)
10272 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10274 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10275 struct drm_property *dpms_property =
10276 dev->mode_config.dpms_property;
10278 connector->dpms = DRM_MODE_DPMS_ON;
10279 drm_object_property_set_value(&connector->base,
10283 intel_encoder = to_intel_encoder(connector->encoder);
10284 intel_encoder->connectors_active = true;
10290 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10294 if (clock1 == clock2)
10297 if (!clock1 || !clock2)
10300 diff = abs(clock1 - clock2);
10302 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10308 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10309 list_for_each_entry((intel_crtc), \
10310 &(dev)->mode_config.crtc_list, \
10312 if (mask & (1 <<(intel_crtc)->pipe))
10315 intel_pipe_config_compare(struct drm_device *dev,
10316 struct intel_crtc_config *current_config,
10317 struct intel_crtc_config *pipe_config)
10319 #define PIPE_CONF_CHECK_X(name) \
10320 if (current_config->name != pipe_config->name) { \
10321 DRM_ERROR("mismatch in " #name " " \
10322 "(expected 0x%08x, found 0x%08x)\n", \
10323 current_config->name, \
10324 pipe_config->name); \
10328 #define PIPE_CONF_CHECK_I(name) \
10329 if (current_config->name != pipe_config->name) { \
10330 DRM_ERROR("mismatch in " #name " " \
10331 "(expected %i, found %i)\n", \
10332 current_config->name, \
10333 pipe_config->name); \
10337 /* This is required for BDW+ where there is only one set of registers for
10338 * switching between high and low RR.
10339 * This macro can be used whenever a comparison has to be made between one
10340 * hw state and multiple sw state variables.
10342 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10343 if ((current_config->name != pipe_config->name) && \
10344 (current_config->alt_name != pipe_config->name)) { \
10345 DRM_ERROR("mismatch in " #name " " \
10346 "(expected %i or %i, found %i)\n", \
10347 current_config->name, \
10348 current_config->alt_name, \
10349 pipe_config->name); \
10353 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10354 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10355 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10356 "(expected %i, found %i)\n", \
10357 current_config->name & (mask), \
10358 pipe_config->name & (mask)); \
10362 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10363 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10364 DRM_ERROR("mismatch in " #name " " \
10365 "(expected %i, found %i)\n", \
10366 current_config->name, \
10367 pipe_config->name); \
10371 #define PIPE_CONF_QUIRK(quirk) \
10372 ((current_config->quirks | pipe_config->quirks) & (quirk))
10374 PIPE_CONF_CHECK_I(cpu_transcoder);
10376 PIPE_CONF_CHECK_I(has_pch_encoder);
10377 PIPE_CONF_CHECK_I(fdi_lanes);
10378 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10379 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10380 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10381 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10382 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10384 PIPE_CONF_CHECK_I(has_dp_encoder);
10386 if (INTEL_INFO(dev)->gen < 8) {
10387 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10388 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10389 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10390 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10391 PIPE_CONF_CHECK_I(dp_m_n.tu);
10393 if (current_config->has_drrs) {
10394 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10395 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10396 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10397 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10398 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10401 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10402 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10403 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10404 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10405 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10408 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10409 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10410 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10411 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10412 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10413 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10415 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10416 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10417 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10418 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10419 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10420 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10422 PIPE_CONF_CHECK_I(pixel_multiplier);
10423 PIPE_CONF_CHECK_I(has_hdmi_sink);
10424 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10425 IS_VALLEYVIEW(dev))
10426 PIPE_CONF_CHECK_I(limited_color_range);
10428 PIPE_CONF_CHECK_I(has_audio);
10430 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10431 DRM_MODE_FLAG_INTERLACE);
10433 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10434 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10435 DRM_MODE_FLAG_PHSYNC);
10436 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10437 DRM_MODE_FLAG_NHSYNC);
10438 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10439 DRM_MODE_FLAG_PVSYNC);
10440 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10441 DRM_MODE_FLAG_NVSYNC);
10444 PIPE_CONF_CHECK_I(pipe_src_w);
10445 PIPE_CONF_CHECK_I(pipe_src_h);
10448 * FIXME: BIOS likes to set up a cloned config with lvds+external
10449 * screen. Since we don't yet re-compute the pipe config when moving
10450 * just the lvds port away to another pipe the sw tracking won't match.
10452 * Proper atomic modesets with recomputed global state will fix this.
10453 * Until then just don't check gmch state for inherited modes.
10455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10456 PIPE_CONF_CHECK_I(gmch_pfit.control);
10457 /* pfit ratios are autocomputed by the hw on gen4+ */
10458 if (INTEL_INFO(dev)->gen < 4)
10459 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10460 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10463 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10464 if (current_config->pch_pfit.enabled) {
10465 PIPE_CONF_CHECK_I(pch_pfit.pos);
10466 PIPE_CONF_CHECK_I(pch_pfit.size);
10469 /* BDW+ don't expose a synchronous way to read the state */
10470 if (IS_HASWELL(dev))
10471 PIPE_CONF_CHECK_I(ips_enabled);
10473 PIPE_CONF_CHECK_I(double_wide);
10475 PIPE_CONF_CHECK_X(ddi_pll_sel);
10477 PIPE_CONF_CHECK_I(shared_dpll);
10478 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10479 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10480 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10481 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10482 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10484 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10485 PIPE_CONF_CHECK_I(pipe_bpp);
10487 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10488 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10490 #undef PIPE_CONF_CHECK_X
10491 #undef PIPE_CONF_CHECK_I
10492 #undef PIPE_CONF_CHECK_I_ALT
10493 #undef PIPE_CONF_CHECK_FLAGS
10494 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10495 #undef PIPE_CONF_QUIRK
10501 check_connector_state(struct drm_device *dev)
10503 struct intel_connector *connector;
10505 list_for_each_entry(connector, &dev->mode_config.connector_list,
10507 /* This also checks the encoder/connector hw state with the
10508 * ->get_hw_state callbacks. */
10509 intel_connector_check_state(connector);
10511 WARN(&connector->new_encoder->base != connector->base.encoder,
10512 "connector's staged encoder doesn't match current encoder\n");
10517 check_encoder_state(struct drm_device *dev)
10519 struct intel_encoder *encoder;
10520 struct intel_connector *connector;
10522 for_each_intel_encoder(dev, encoder) {
10523 bool enabled = false;
10524 bool active = false;
10525 enum pipe pipe, tracked_pipe;
10527 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10528 encoder->base.base.id,
10529 encoder->base.name);
10531 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10532 "encoder's stage crtc doesn't match current crtc\n");
10533 WARN(encoder->connectors_active && !encoder->base.crtc,
10534 "encoder's active_connectors set, but no crtc\n");
10536 list_for_each_entry(connector, &dev->mode_config.connector_list,
10538 if (connector->base.encoder != &encoder->base)
10541 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10545 * for MST connectors if we unplug the connector is gone
10546 * away but the encoder is still connected to a crtc
10547 * until a modeset happens in response to the hotplug.
10549 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10552 WARN(!!encoder->base.crtc != enabled,
10553 "encoder's enabled state mismatch "
10554 "(expected %i, found %i)\n",
10555 !!encoder->base.crtc, enabled);
10556 WARN(active && !encoder->base.crtc,
10557 "active encoder with no crtc\n");
10559 WARN(encoder->connectors_active != active,
10560 "encoder's computed active state doesn't match tracked active state "
10561 "(expected %i, found %i)\n", active, encoder->connectors_active);
10563 active = encoder->get_hw_state(encoder, &pipe);
10564 WARN(active != encoder->connectors_active,
10565 "encoder's hw state doesn't match sw tracking "
10566 "(expected %i, found %i)\n",
10567 encoder->connectors_active, active);
10569 if (!encoder->base.crtc)
10572 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10573 WARN(active && pipe != tracked_pipe,
10574 "active encoder's pipe doesn't match"
10575 "(expected %i, found %i)\n",
10576 tracked_pipe, pipe);
10582 check_crtc_state(struct drm_device *dev)
10584 struct drm_i915_private *dev_priv = dev->dev_private;
10585 struct intel_crtc *crtc;
10586 struct intel_encoder *encoder;
10587 struct intel_crtc_config pipe_config;
10589 for_each_intel_crtc(dev, crtc) {
10590 bool enabled = false;
10591 bool active = false;
10593 memset(&pipe_config, 0, sizeof(pipe_config));
10595 DRM_DEBUG_KMS("[CRTC:%d]\n",
10596 crtc->base.base.id);
10598 WARN(crtc->active && !crtc->base.enabled,
10599 "active crtc, but not enabled in sw tracking\n");
10601 for_each_intel_encoder(dev, encoder) {
10602 if (encoder->base.crtc != &crtc->base)
10605 if (encoder->connectors_active)
10609 WARN(active != crtc->active,
10610 "crtc's computed active state doesn't match tracked active state "
10611 "(expected %i, found %i)\n", active, crtc->active);
10612 WARN(enabled != crtc->base.enabled,
10613 "crtc's computed enabled state doesn't match tracked enabled state "
10614 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10616 active = dev_priv->display.get_pipe_config(crtc,
10619 /* hw state is inconsistent with the pipe quirk */
10620 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10621 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10622 active = crtc->active;
10624 for_each_intel_encoder(dev, encoder) {
10626 if (encoder->base.crtc != &crtc->base)
10628 if (encoder->get_hw_state(encoder, &pipe))
10629 encoder->get_config(encoder, &pipe_config);
10632 WARN(crtc->active != active,
10633 "crtc active state doesn't match with hw state "
10634 "(expected %i, found %i)\n", crtc->active, active);
10637 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10638 WARN(1, "pipe state doesn't match!\n");
10639 intel_dump_pipe_config(crtc, &pipe_config,
10641 intel_dump_pipe_config(crtc, &crtc->config,
10648 check_shared_dpll_state(struct drm_device *dev)
10650 struct drm_i915_private *dev_priv = dev->dev_private;
10651 struct intel_crtc *crtc;
10652 struct intel_dpll_hw_state dpll_hw_state;
10655 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10656 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10657 int enabled_crtcs = 0, active_crtcs = 0;
10660 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10662 DRM_DEBUG_KMS("%s\n", pll->name);
10664 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10666 WARN(pll->active > hweight32(pll->config.crtc_mask),
10667 "more active pll users than references: %i vs %i\n",
10668 pll->active, hweight32(pll->config.crtc_mask));
10669 WARN(pll->active && !pll->on,
10670 "pll in active use but not on in sw tracking\n");
10671 WARN(pll->on && !pll->active,
10672 "pll in on but not on in use in sw tracking\n");
10673 WARN(pll->on != active,
10674 "pll on state mismatch (expected %i, found %i)\n",
10677 for_each_intel_crtc(dev, crtc) {
10678 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10680 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10683 WARN(pll->active != active_crtcs,
10684 "pll active crtcs mismatch (expected %i, found %i)\n",
10685 pll->active, active_crtcs);
10686 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10687 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10688 hweight32(pll->config.crtc_mask), enabled_crtcs);
10690 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10691 sizeof(dpll_hw_state)),
10692 "pll hw state mismatch\n");
10697 intel_modeset_check_state(struct drm_device *dev)
10699 check_connector_state(dev);
10700 check_encoder_state(dev);
10701 check_crtc_state(dev);
10702 check_shared_dpll_state(dev);
10705 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10709 * FDI already provided one idea for the dotclock.
10710 * Yell if the encoder disagrees.
10712 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10713 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10714 pipe_config->adjusted_mode.crtc_clock, dotclock);
10717 static void update_scanline_offset(struct intel_crtc *crtc)
10719 struct drm_device *dev = crtc->base.dev;
10722 * The scanline counter increments at the leading edge of hsync.
10724 * On most platforms it starts counting from vtotal-1 on the
10725 * first active line. That means the scanline counter value is
10726 * always one less than what we would expect. Ie. just after
10727 * start of vblank, which also occurs at start of hsync (on the
10728 * last active line), the scanline counter will read vblank_start-1.
10730 * On gen2 the scanline counter starts counting from 1 instead
10731 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10732 * to keep the value positive), instead of adding one.
10734 * On HSW+ the behaviour of the scanline counter depends on the output
10735 * type. For DP ports it behaves like most other platforms, but on HDMI
10736 * there's an extra 1 line difference. So we need to add two instead of
10737 * one to the value.
10739 if (IS_GEN2(dev)) {
10740 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10743 vtotal = mode->crtc_vtotal;
10744 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10747 crtc->scanline_offset = vtotal - 1;
10748 } else if (HAS_DDI(dev) &&
10749 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10750 crtc->scanline_offset = 2;
10752 crtc->scanline_offset = 1;
10755 static int __intel_set_mode(struct drm_crtc *crtc,
10756 struct drm_display_mode *mode,
10757 int x, int y, struct drm_framebuffer *fb)
10759 struct drm_device *dev = crtc->dev;
10760 struct drm_i915_private *dev_priv = dev->dev_private;
10761 struct drm_display_mode *saved_mode;
10762 struct intel_crtc_config *pipe_config = NULL;
10763 struct intel_crtc *intel_crtc;
10764 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10767 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10771 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10772 &prepare_pipes, &disable_pipes);
10774 *saved_mode = crtc->mode;
10776 /* Hack: Because we don't (yet) support global modeset on multiple
10777 * crtcs, we don't keep track of the new mode for more than one crtc.
10778 * Hence simply check whether any bit is set in modeset_pipes in all the
10779 * pieces of code that are not yet converted to deal with mutliple crtcs
10780 * changing their mode at the same time. */
10781 if (modeset_pipes) {
10782 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10783 if (IS_ERR(pipe_config)) {
10784 ret = PTR_ERR(pipe_config);
10785 pipe_config = NULL;
10789 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10791 to_intel_crtc(crtc)->new_config = pipe_config;
10795 * See if the config requires any additional preparation, e.g.
10796 * to adjust global state with pipes off. We need to do this
10797 * here so we can get the modeset_pipe updated config for the new
10798 * mode set on this crtc. For other crtcs we need to use the
10799 * adjusted_mode bits in the crtc directly.
10801 if (IS_VALLEYVIEW(dev)) {
10802 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10804 /* may have added more to prepare_pipes than we should */
10805 prepare_pipes &= ~disable_pipes;
10808 if (dev_priv->display.crtc_compute_clock) {
10809 unsigned clear_pipes = modeset_pipes | disable_pipes;
10811 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10815 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10816 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10818 intel_shared_dpll_abort_config(dev_priv);
10824 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10825 intel_crtc_disable(&intel_crtc->base);
10827 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10828 if (intel_crtc->base.enabled)
10829 dev_priv->display.crtc_disable(&intel_crtc->base);
10832 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10833 * to set it here already despite that we pass it down the callchain.
10835 if (modeset_pipes) {
10836 crtc->mode = *mode;
10837 /* mode_set/enable/disable functions rely on a correct pipe
10839 to_intel_crtc(crtc)->config = *pipe_config;
10840 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10843 * Calculate and store various constants which
10844 * are later needed by vblank and swap-completion
10845 * timestamping. They are derived from true hwmode.
10847 drm_calc_timestamping_constants(crtc,
10848 &pipe_config->adjusted_mode);
10851 if (dev_priv->display.crtc_compute_clock)
10852 intel_shared_dpll_commit(dev_priv);
10854 /* Only after disabling all output pipelines that will be changed can we
10855 * update the the output configuration. */
10856 intel_modeset_update_state(dev, prepare_pipes);
10858 if (dev_priv->display.modeset_global_resources)
10859 dev_priv->display.modeset_global_resources(dev);
10861 /* Set up the DPLL and any encoders state that needs to adjust or depend
10864 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10865 struct drm_framebuffer *old_fb = crtc->primary->fb;
10866 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10867 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10869 mutex_lock(&dev->struct_mutex);
10870 ret = intel_pin_and_fence_fb_obj(dev,
10874 DRM_ERROR("pin & fence failed\n");
10875 mutex_unlock(&dev->struct_mutex);
10879 intel_unpin_fb_obj(old_obj);
10880 i915_gem_track_fb(old_obj, obj,
10881 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10882 mutex_unlock(&dev->struct_mutex);
10884 crtc->primary->fb = fb;
10888 if (dev_priv->display.crtc_mode_set) {
10889 ret = dev_priv->display.crtc_mode_set(intel_crtc,
10896 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10897 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10898 update_scanline_offset(intel_crtc);
10900 dev_priv->display.crtc_enable(&intel_crtc->base);
10903 /* FIXME: add subpixel order */
10905 if (ret && crtc->enabled)
10906 crtc->mode = *saved_mode;
10909 kfree(pipe_config);
10914 static int intel_set_mode(struct drm_crtc *crtc,
10915 struct drm_display_mode *mode,
10916 int x, int y, struct drm_framebuffer *fb)
10920 ret = __intel_set_mode(crtc, mode, x, y, fb);
10923 intel_modeset_check_state(crtc->dev);
10928 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10930 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10933 #undef for_each_intel_crtc_masked
10935 static void intel_set_config_free(struct intel_set_config *config)
10940 kfree(config->save_connector_encoders);
10941 kfree(config->save_encoder_crtcs);
10942 kfree(config->save_crtc_enabled);
10946 static int intel_set_config_save_state(struct drm_device *dev,
10947 struct intel_set_config *config)
10949 struct drm_crtc *crtc;
10950 struct drm_encoder *encoder;
10951 struct drm_connector *connector;
10954 config->save_crtc_enabled =
10955 kcalloc(dev->mode_config.num_crtc,
10956 sizeof(bool), GFP_KERNEL);
10957 if (!config->save_crtc_enabled)
10960 config->save_encoder_crtcs =
10961 kcalloc(dev->mode_config.num_encoder,
10962 sizeof(struct drm_crtc *), GFP_KERNEL);
10963 if (!config->save_encoder_crtcs)
10966 config->save_connector_encoders =
10967 kcalloc(dev->mode_config.num_connector,
10968 sizeof(struct drm_encoder *), GFP_KERNEL);
10969 if (!config->save_connector_encoders)
10972 /* Copy data. Note that driver private data is not affected.
10973 * Should anything bad happen only the expected state is
10974 * restored, not the drivers personal bookkeeping.
10977 for_each_crtc(dev, crtc) {
10978 config->save_crtc_enabled[count++] = crtc->enabled;
10982 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10983 config->save_encoder_crtcs[count++] = encoder->crtc;
10987 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10988 config->save_connector_encoders[count++] = connector->encoder;
10994 static void intel_set_config_restore_state(struct drm_device *dev,
10995 struct intel_set_config *config)
10997 struct intel_crtc *crtc;
10998 struct intel_encoder *encoder;
10999 struct intel_connector *connector;
11003 for_each_intel_crtc(dev, crtc) {
11004 crtc->new_enabled = config->save_crtc_enabled[count++];
11006 if (crtc->new_enabled)
11007 crtc->new_config = &crtc->config;
11009 crtc->new_config = NULL;
11013 for_each_intel_encoder(dev, encoder) {
11014 encoder->new_crtc =
11015 to_intel_crtc(config->save_encoder_crtcs[count++]);
11019 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11020 connector->new_encoder =
11021 to_intel_encoder(config->save_connector_encoders[count++]);
11026 is_crtc_connector_off(struct drm_mode_set *set)
11030 if (set->num_connectors == 0)
11033 if (WARN_ON(set->connectors == NULL))
11036 for (i = 0; i < set->num_connectors; i++)
11037 if (set->connectors[i]->encoder &&
11038 set->connectors[i]->encoder->crtc == set->crtc &&
11039 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11046 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11047 struct intel_set_config *config)
11050 /* We should be able to check here if the fb has the same properties
11051 * and then just flip_or_move it */
11052 if (is_crtc_connector_off(set)) {
11053 config->mode_changed = true;
11054 } else if (set->crtc->primary->fb != set->fb) {
11056 * If we have no fb, we can only flip as long as the crtc is
11057 * active, otherwise we need a full mode set. The crtc may
11058 * be active if we've only disabled the primary plane, or
11059 * in fastboot situations.
11061 if (set->crtc->primary->fb == NULL) {
11062 struct intel_crtc *intel_crtc =
11063 to_intel_crtc(set->crtc);
11065 if (intel_crtc->active) {
11066 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11067 config->fb_changed = true;
11069 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11070 config->mode_changed = true;
11072 } else if (set->fb == NULL) {
11073 config->mode_changed = true;
11074 } else if (set->fb->pixel_format !=
11075 set->crtc->primary->fb->pixel_format) {
11076 config->mode_changed = true;
11078 config->fb_changed = true;
11082 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11083 config->fb_changed = true;
11085 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11086 DRM_DEBUG_KMS("modes are different, full mode set\n");
11087 drm_mode_debug_printmodeline(&set->crtc->mode);
11088 drm_mode_debug_printmodeline(set->mode);
11089 config->mode_changed = true;
11092 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11093 set->crtc->base.id, config->mode_changed, config->fb_changed);
11097 intel_modeset_stage_output_state(struct drm_device *dev,
11098 struct drm_mode_set *set,
11099 struct intel_set_config *config)
11101 struct intel_connector *connector;
11102 struct intel_encoder *encoder;
11103 struct intel_crtc *crtc;
11106 /* The upper layers ensure that we either disable a crtc or have a list
11107 * of connectors. For paranoia, double-check this. */
11108 WARN_ON(!set->fb && (set->num_connectors != 0));
11109 WARN_ON(set->fb && (set->num_connectors == 0));
11111 list_for_each_entry(connector, &dev->mode_config.connector_list,
11113 /* Otherwise traverse passed in connector list and get encoders
11115 for (ro = 0; ro < set->num_connectors; ro++) {
11116 if (set->connectors[ro] == &connector->base) {
11117 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11122 /* If we disable the crtc, disable all its connectors. Also, if
11123 * the connector is on the changing crtc but not on the new
11124 * connector list, disable it. */
11125 if ((!set->fb || ro == set->num_connectors) &&
11126 connector->base.encoder &&
11127 connector->base.encoder->crtc == set->crtc) {
11128 connector->new_encoder = NULL;
11130 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11131 connector->base.base.id,
11132 connector->base.name);
11136 if (&connector->new_encoder->base != connector->base.encoder) {
11137 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11138 config->mode_changed = true;
11141 /* connector->new_encoder is now updated for all connectors. */
11143 /* Update crtc of enabled connectors. */
11144 list_for_each_entry(connector, &dev->mode_config.connector_list,
11146 struct drm_crtc *new_crtc;
11148 if (!connector->new_encoder)
11151 new_crtc = connector->new_encoder->base.crtc;
11153 for (ro = 0; ro < set->num_connectors; ro++) {
11154 if (set->connectors[ro] == &connector->base)
11155 new_crtc = set->crtc;
11158 /* Make sure the new CRTC will work with the encoder */
11159 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11163 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11165 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11166 connector->base.base.id,
11167 connector->base.name,
11168 new_crtc->base.id);
11171 /* Check for any encoders that needs to be disabled. */
11172 for_each_intel_encoder(dev, encoder) {
11173 int num_connectors = 0;
11174 list_for_each_entry(connector,
11175 &dev->mode_config.connector_list,
11177 if (connector->new_encoder == encoder) {
11178 WARN_ON(!connector->new_encoder->new_crtc);
11183 if (num_connectors == 0)
11184 encoder->new_crtc = NULL;
11185 else if (num_connectors > 1)
11188 /* Only now check for crtc changes so we don't miss encoders
11189 * that will be disabled. */
11190 if (&encoder->new_crtc->base != encoder->base.crtc) {
11191 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11192 config->mode_changed = true;
11195 /* Now we've also updated encoder->new_crtc for all encoders. */
11196 list_for_each_entry(connector, &dev->mode_config.connector_list,
11198 if (connector->new_encoder)
11199 if (connector->new_encoder != connector->encoder)
11200 connector->encoder = connector->new_encoder;
11202 for_each_intel_crtc(dev, crtc) {
11203 crtc->new_enabled = false;
11205 for_each_intel_encoder(dev, encoder) {
11206 if (encoder->new_crtc == crtc) {
11207 crtc->new_enabled = true;
11212 if (crtc->new_enabled != crtc->base.enabled) {
11213 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11214 crtc->new_enabled ? "en" : "dis");
11215 config->mode_changed = true;
11218 if (crtc->new_enabled)
11219 crtc->new_config = &crtc->config;
11221 crtc->new_config = NULL;
11227 static void disable_crtc_nofb(struct intel_crtc *crtc)
11229 struct drm_device *dev = crtc->base.dev;
11230 struct intel_encoder *encoder;
11231 struct intel_connector *connector;
11233 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11234 pipe_name(crtc->pipe));
11236 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11237 if (connector->new_encoder &&
11238 connector->new_encoder->new_crtc == crtc)
11239 connector->new_encoder = NULL;
11242 for_each_intel_encoder(dev, encoder) {
11243 if (encoder->new_crtc == crtc)
11244 encoder->new_crtc = NULL;
11247 crtc->new_enabled = false;
11248 crtc->new_config = NULL;
11251 static int intel_crtc_set_config(struct drm_mode_set *set)
11253 struct drm_device *dev;
11254 struct drm_mode_set save_set;
11255 struct intel_set_config *config;
11259 BUG_ON(!set->crtc);
11260 BUG_ON(!set->crtc->helper_private);
11262 /* Enforce sane interface api - has been abused by the fb helper. */
11263 BUG_ON(!set->mode && set->fb);
11264 BUG_ON(set->fb && set->num_connectors == 0);
11267 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11268 set->crtc->base.id, set->fb->base.id,
11269 (int)set->num_connectors, set->x, set->y);
11271 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11274 dev = set->crtc->dev;
11277 config = kzalloc(sizeof(*config), GFP_KERNEL);
11281 ret = intel_set_config_save_state(dev, config);
11285 save_set.crtc = set->crtc;
11286 save_set.mode = &set->crtc->mode;
11287 save_set.x = set->crtc->x;
11288 save_set.y = set->crtc->y;
11289 save_set.fb = set->crtc->primary->fb;
11291 /* Compute whether we need a full modeset, only an fb base update or no
11292 * change at all. In the future we might also check whether only the
11293 * mode changed, e.g. for LVDS where we only change the panel fitter in
11295 intel_set_config_compute_mode_changes(set, config);
11297 ret = intel_modeset_stage_output_state(dev, set, config);
11301 if (config->mode_changed) {
11302 ret = intel_set_mode(set->crtc, set->mode,
11303 set->x, set->y, set->fb);
11304 } else if (config->fb_changed) {
11305 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11307 intel_crtc_wait_for_pending_flips(set->crtc);
11309 ret = intel_pipe_set_base(set->crtc,
11310 set->x, set->y, set->fb);
11313 * We need to make sure the primary plane is re-enabled if it
11314 * has previously been turned off.
11316 if (!intel_crtc->primary_enabled && ret == 0) {
11317 WARN_ON(!intel_crtc->active);
11318 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11322 * In the fastboot case this may be our only check of the
11323 * state after boot. It would be better to only do it on
11324 * the first update, but we don't have a nice way of doing that
11325 * (and really, set_config isn't used much for high freq page
11326 * flipping, so increasing its cost here shouldn't be a big
11329 if (i915.fastboot && ret == 0)
11330 intel_modeset_check_state(set->crtc->dev);
11334 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11335 set->crtc->base.id, ret);
11337 intel_set_config_restore_state(dev, config);
11340 * HACK: if the pipe was on, but we didn't have a framebuffer,
11341 * force the pipe off to avoid oopsing in the modeset code
11342 * due to fb==NULL. This should only happen during boot since
11343 * we don't yet reconstruct the FB from the hardware state.
11345 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11346 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11348 /* Try to restore the config */
11349 if (config->mode_changed &&
11350 intel_set_mode(save_set.crtc, save_set.mode,
11351 save_set.x, save_set.y, save_set.fb))
11352 DRM_ERROR("failed to restore config after modeset failure\n");
11356 intel_set_config_free(config);
11360 static const struct drm_crtc_funcs intel_crtc_funcs = {
11361 .gamma_set = intel_crtc_gamma_set,
11362 .set_config = intel_crtc_set_config,
11363 .destroy = intel_crtc_destroy,
11364 .page_flip = intel_crtc_page_flip,
11367 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11368 struct intel_shared_dpll *pll,
11369 struct intel_dpll_hw_state *hw_state)
11373 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11376 val = I915_READ(PCH_DPLL(pll->id));
11377 hw_state->dpll = val;
11378 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11379 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11381 return val & DPLL_VCO_ENABLE;
11384 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11385 struct intel_shared_dpll *pll)
11387 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11388 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11391 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11392 struct intel_shared_dpll *pll)
11394 /* PCH refclock must be enabled first */
11395 ibx_assert_pch_refclk_enabled(dev_priv);
11397 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11399 /* Wait for the clocks to stabilize. */
11400 POSTING_READ(PCH_DPLL(pll->id));
11403 /* The pixel multiplier can only be updated once the
11404 * DPLL is enabled and the clocks are stable.
11406 * So write it again.
11408 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11409 POSTING_READ(PCH_DPLL(pll->id));
11413 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11414 struct intel_shared_dpll *pll)
11416 struct drm_device *dev = dev_priv->dev;
11417 struct intel_crtc *crtc;
11419 /* Make sure no transcoder isn't still depending on us. */
11420 for_each_intel_crtc(dev, crtc) {
11421 if (intel_crtc_to_shared_dpll(crtc) == pll)
11422 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11425 I915_WRITE(PCH_DPLL(pll->id), 0);
11426 POSTING_READ(PCH_DPLL(pll->id));
11430 static char *ibx_pch_dpll_names[] = {
11435 static void ibx_pch_dpll_init(struct drm_device *dev)
11437 struct drm_i915_private *dev_priv = dev->dev_private;
11440 dev_priv->num_shared_dpll = 2;
11442 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11443 dev_priv->shared_dplls[i].id = i;
11444 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11445 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11446 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11447 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11448 dev_priv->shared_dplls[i].get_hw_state =
11449 ibx_pch_dpll_get_hw_state;
11453 static void intel_shared_dpll_init(struct drm_device *dev)
11455 struct drm_i915_private *dev_priv = dev->dev_private;
11458 intel_ddi_pll_init(dev);
11459 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11460 ibx_pch_dpll_init(dev);
11462 dev_priv->num_shared_dpll = 0;
11464 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11468 intel_primary_plane_disable(struct drm_plane *plane)
11470 struct drm_device *dev = plane->dev;
11471 struct intel_crtc *intel_crtc;
11476 BUG_ON(!plane->crtc);
11478 intel_crtc = to_intel_crtc(plane->crtc);
11481 * Even though we checked plane->fb above, it's still possible that
11482 * the primary plane has been implicitly disabled because the crtc
11483 * coordinates given weren't visible, or because we detected
11484 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11485 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11486 * In either case, we need to unpin the FB and let the fb pointer get
11487 * updated, but otherwise we don't need to touch the hardware.
11489 if (!intel_crtc->primary_enabled)
11490 goto disable_unpin;
11492 intel_crtc_wait_for_pending_flips(plane->crtc);
11493 intel_disable_primary_hw_plane(plane, plane->crtc);
11496 mutex_lock(&dev->struct_mutex);
11497 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11498 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11499 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11500 mutex_unlock(&dev->struct_mutex);
11507 intel_check_primary_plane(struct drm_plane *plane,
11508 struct intel_plane_state *state)
11510 struct drm_crtc *crtc = state->crtc;
11511 struct drm_framebuffer *fb = state->fb;
11512 struct drm_rect *dest = &state->dst;
11513 struct drm_rect *src = &state->src;
11514 const struct drm_rect *clip = &state->clip;
11516 return drm_plane_helper_check_update(plane, crtc, fb,
11518 DRM_PLANE_HELPER_NO_SCALING,
11519 DRM_PLANE_HELPER_NO_SCALING,
11520 false, true, &state->visible);
11524 intel_prepare_primary_plane(struct drm_plane *plane,
11525 struct intel_plane_state *state)
11527 struct drm_crtc *crtc = state->crtc;
11528 struct drm_framebuffer *fb = state->fb;
11529 struct drm_device *dev = crtc->dev;
11530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11531 enum pipe pipe = intel_crtc->pipe;
11532 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11533 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11536 intel_crtc_wait_for_pending_flips(crtc);
11538 if (intel_crtc_has_pending_flip(crtc)) {
11539 DRM_ERROR("pipe is still busy with an old pageflip\n");
11543 if (old_obj != obj) {
11544 mutex_lock(&dev->struct_mutex);
11545 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11547 i915_gem_track_fb(old_obj, obj,
11548 INTEL_FRONTBUFFER_PRIMARY(pipe));
11549 mutex_unlock(&dev->struct_mutex);
11551 DRM_DEBUG_KMS("pin & fence failed\n");
11560 intel_commit_primary_plane(struct drm_plane *plane,
11561 struct intel_plane_state *state)
11563 struct drm_crtc *crtc = state->crtc;
11564 struct drm_framebuffer *fb = state->fb;
11565 struct drm_device *dev = crtc->dev;
11566 struct drm_i915_private *dev_priv = dev->dev_private;
11567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11568 enum pipe pipe = intel_crtc->pipe;
11569 struct drm_framebuffer *old_fb = plane->fb;
11570 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11571 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11572 struct intel_plane *intel_plane = to_intel_plane(plane);
11573 struct drm_rect *src = &state->src;
11575 crtc->primary->fb = fb;
11579 intel_plane->crtc_x = state->orig_dst.x1;
11580 intel_plane->crtc_y = state->orig_dst.y1;
11581 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11582 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11583 intel_plane->src_x = state->orig_src.x1;
11584 intel_plane->src_y = state->orig_src.y1;
11585 intel_plane->src_w = drm_rect_width(&state->orig_src);
11586 intel_plane->src_h = drm_rect_height(&state->orig_src);
11587 intel_plane->obj = obj;
11589 if (intel_crtc->active) {
11591 * FBC does not work on some platforms for rotated
11592 * planes, so disable it when rotation is not 0 and
11593 * update it when rotation is set back to 0.
11595 * FIXME: This is redundant with the fbc update done in
11596 * the primary plane enable function except that that
11597 * one is done too late. We eventually need to unify
11600 if (intel_crtc->primary_enabled &&
11601 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11602 dev_priv->fbc.plane == intel_crtc->plane &&
11603 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11604 intel_disable_fbc(dev);
11607 if (state->visible) {
11608 bool was_enabled = intel_crtc->primary_enabled;
11610 /* FIXME: kill this fastboot hack */
11611 intel_update_pipe_size(intel_crtc);
11613 intel_crtc->primary_enabled = true;
11615 dev_priv->display.update_primary_plane(crtc, plane->fb,
11619 * BDW signals flip done immediately if the plane
11620 * is disabled, even if the plane enable is already
11621 * armed to occur at the next vblank :(
11623 if (IS_BROADWELL(dev) && !was_enabled)
11624 intel_wait_for_vblank(dev, intel_crtc->pipe);
11627 * If clipping results in a non-visible primary plane,
11628 * we'll disable the primary plane. Note that this is
11629 * a bit different than what happens if userspace
11630 * explicitly disables the plane by passing fb=0
11631 * because plane->fb still gets set and pinned.
11633 intel_disable_primary_hw_plane(plane, crtc);
11636 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11638 mutex_lock(&dev->struct_mutex);
11639 intel_update_fbc(dev);
11640 mutex_unlock(&dev->struct_mutex);
11643 if (old_fb && old_fb != fb) {
11644 if (intel_crtc->active)
11645 intel_wait_for_vblank(dev, intel_crtc->pipe);
11647 mutex_lock(&dev->struct_mutex);
11648 intel_unpin_fb_obj(old_obj);
11649 mutex_unlock(&dev->struct_mutex);
11654 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11655 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11656 unsigned int crtc_w, unsigned int crtc_h,
11657 uint32_t src_x, uint32_t src_y,
11658 uint32_t src_w, uint32_t src_h)
11660 struct intel_plane_state state;
11661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11667 /* sample coordinates in 16.16 fixed point */
11668 state.src.x1 = src_x;
11669 state.src.x2 = src_x + src_w;
11670 state.src.y1 = src_y;
11671 state.src.y2 = src_y + src_h;
11673 /* integer pixels */
11674 state.dst.x1 = crtc_x;
11675 state.dst.x2 = crtc_x + crtc_w;
11676 state.dst.y1 = crtc_y;
11677 state.dst.y2 = crtc_y + crtc_h;
11681 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11682 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11684 state.orig_src = state.src;
11685 state.orig_dst = state.dst;
11687 ret = intel_check_primary_plane(plane, &state);
11691 ret = intel_prepare_primary_plane(plane, &state);
11695 intel_commit_primary_plane(plane, &state);
11700 /* Common destruction function for both primary and cursor planes */
11701 static void intel_plane_destroy(struct drm_plane *plane)
11703 struct intel_plane *intel_plane = to_intel_plane(plane);
11704 drm_plane_cleanup(plane);
11705 kfree(intel_plane);
11708 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11709 .update_plane = intel_primary_plane_setplane,
11710 .disable_plane = intel_primary_plane_disable,
11711 .destroy = intel_plane_destroy,
11712 .set_property = intel_plane_set_property
11715 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11718 struct intel_plane *primary;
11719 const uint32_t *intel_primary_formats;
11722 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11723 if (primary == NULL)
11726 primary->can_scale = false;
11727 primary->max_downscale = 1;
11728 primary->pipe = pipe;
11729 primary->plane = pipe;
11730 primary->rotation = BIT(DRM_ROTATE_0);
11731 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11732 primary->plane = !pipe;
11734 if (INTEL_INFO(dev)->gen <= 3) {
11735 intel_primary_formats = intel_primary_formats_gen2;
11736 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11738 intel_primary_formats = intel_primary_formats_gen4;
11739 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11742 drm_universal_plane_init(dev, &primary->base, 0,
11743 &intel_primary_plane_funcs,
11744 intel_primary_formats, num_formats,
11745 DRM_PLANE_TYPE_PRIMARY);
11747 if (INTEL_INFO(dev)->gen >= 4) {
11748 if (!dev->mode_config.rotation_property)
11749 dev->mode_config.rotation_property =
11750 drm_mode_create_rotation_property(dev,
11751 BIT(DRM_ROTATE_0) |
11752 BIT(DRM_ROTATE_180));
11753 if (dev->mode_config.rotation_property)
11754 drm_object_attach_property(&primary->base.base,
11755 dev->mode_config.rotation_property,
11756 primary->rotation);
11759 return &primary->base;
11763 intel_cursor_plane_disable(struct drm_plane *plane)
11768 BUG_ON(!plane->crtc);
11770 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11774 intel_check_cursor_plane(struct drm_plane *plane,
11775 struct intel_plane_state *state)
11777 struct drm_crtc *crtc = state->crtc;
11778 struct drm_device *dev = crtc->dev;
11779 struct drm_framebuffer *fb = state->fb;
11780 struct drm_rect *dest = &state->dst;
11781 struct drm_rect *src = &state->src;
11782 const struct drm_rect *clip = &state->clip;
11783 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11784 int crtc_w, crtc_h;
11788 ret = drm_plane_helper_check_update(plane, crtc, fb,
11790 DRM_PLANE_HELPER_NO_SCALING,
11791 DRM_PLANE_HELPER_NO_SCALING,
11792 true, true, &state->visible);
11797 /* if we want to turn off the cursor ignore width and height */
11801 /* Check for which cursor types we support */
11802 crtc_w = drm_rect_width(&state->orig_dst);
11803 crtc_h = drm_rect_height(&state->orig_dst);
11804 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11805 DRM_DEBUG("Cursor dimension not supported\n");
11809 stride = roundup_pow_of_two(crtc_w) * 4;
11810 if (obj->base.size < stride * crtc_h) {
11811 DRM_DEBUG_KMS("buffer is too small\n");
11815 if (fb == crtc->cursor->fb)
11818 /* we only need to pin inside GTT if cursor is non-phy */
11819 mutex_lock(&dev->struct_mutex);
11820 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11821 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11824 mutex_unlock(&dev->struct_mutex);
11830 intel_commit_cursor_plane(struct drm_plane *plane,
11831 struct intel_plane_state *state)
11833 struct drm_crtc *crtc = state->crtc;
11834 struct drm_framebuffer *fb = state->fb;
11835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11836 struct intel_plane *intel_plane = to_intel_plane(plane);
11837 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11838 struct drm_i915_gem_object *obj = intel_fb->obj;
11839 int crtc_w, crtc_h;
11841 crtc->cursor_x = state->orig_dst.x1;
11842 crtc->cursor_y = state->orig_dst.y1;
11844 intel_plane->crtc_x = state->orig_dst.x1;
11845 intel_plane->crtc_y = state->orig_dst.y1;
11846 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11847 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11848 intel_plane->src_x = state->orig_src.x1;
11849 intel_plane->src_y = state->orig_src.y1;
11850 intel_plane->src_w = drm_rect_width(&state->orig_src);
11851 intel_plane->src_h = drm_rect_height(&state->orig_src);
11852 intel_plane->obj = obj;
11854 if (fb != crtc->cursor->fb) {
11855 crtc_w = drm_rect_width(&state->orig_dst);
11856 crtc_h = drm_rect_height(&state->orig_dst);
11857 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11859 intel_crtc_update_cursor(crtc, state->visible);
11861 intel_frontbuffer_flip(crtc->dev,
11862 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11869 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11870 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11871 unsigned int crtc_w, unsigned int crtc_h,
11872 uint32_t src_x, uint32_t src_y,
11873 uint32_t src_w, uint32_t src_h)
11875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11876 struct intel_plane_state state;
11882 /* sample coordinates in 16.16 fixed point */
11883 state.src.x1 = src_x;
11884 state.src.x2 = src_x + src_w;
11885 state.src.y1 = src_y;
11886 state.src.y2 = src_y + src_h;
11888 /* integer pixels */
11889 state.dst.x1 = crtc_x;
11890 state.dst.x2 = crtc_x + crtc_w;
11891 state.dst.y1 = crtc_y;
11892 state.dst.y2 = crtc_y + crtc_h;
11896 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11897 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11899 state.orig_src = state.src;
11900 state.orig_dst = state.dst;
11902 ret = intel_check_cursor_plane(plane, &state);
11906 return intel_commit_cursor_plane(plane, &state);
11909 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11910 .update_plane = intel_cursor_plane_update,
11911 .disable_plane = intel_cursor_plane_disable,
11912 .destroy = intel_plane_destroy,
11913 .set_property = intel_plane_set_property,
11916 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11919 struct intel_plane *cursor;
11921 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11922 if (cursor == NULL)
11925 cursor->can_scale = false;
11926 cursor->max_downscale = 1;
11927 cursor->pipe = pipe;
11928 cursor->plane = pipe;
11929 cursor->rotation = BIT(DRM_ROTATE_0);
11931 drm_universal_plane_init(dev, &cursor->base, 0,
11932 &intel_cursor_plane_funcs,
11933 intel_cursor_formats,
11934 ARRAY_SIZE(intel_cursor_formats),
11935 DRM_PLANE_TYPE_CURSOR);
11937 if (INTEL_INFO(dev)->gen >= 4) {
11938 if (!dev->mode_config.rotation_property)
11939 dev->mode_config.rotation_property =
11940 drm_mode_create_rotation_property(dev,
11941 BIT(DRM_ROTATE_0) |
11942 BIT(DRM_ROTATE_180));
11943 if (dev->mode_config.rotation_property)
11944 drm_object_attach_property(&cursor->base.base,
11945 dev->mode_config.rotation_property,
11949 return &cursor->base;
11952 static void intel_crtc_init(struct drm_device *dev, int pipe)
11954 struct drm_i915_private *dev_priv = dev->dev_private;
11955 struct intel_crtc *intel_crtc;
11956 struct drm_plane *primary = NULL;
11957 struct drm_plane *cursor = NULL;
11960 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11961 if (intel_crtc == NULL)
11964 primary = intel_primary_plane_create(dev, pipe);
11968 cursor = intel_cursor_plane_create(dev, pipe);
11972 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11973 cursor, &intel_crtc_funcs);
11977 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11978 for (i = 0; i < 256; i++) {
11979 intel_crtc->lut_r[i] = i;
11980 intel_crtc->lut_g[i] = i;
11981 intel_crtc->lut_b[i] = i;
11985 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11986 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11988 intel_crtc->pipe = pipe;
11989 intel_crtc->plane = pipe;
11990 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11991 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11992 intel_crtc->plane = !pipe;
11995 intel_crtc->cursor_base = ~0;
11996 intel_crtc->cursor_cntl = ~0;
11997 intel_crtc->cursor_size = ~0;
11999 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12000 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12001 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12002 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12004 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12006 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12011 drm_plane_cleanup(primary);
12013 drm_plane_cleanup(cursor);
12017 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12019 struct drm_encoder *encoder = connector->base.encoder;
12020 struct drm_device *dev = connector->base.dev;
12022 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12025 return INVALID_PIPE;
12027 return to_intel_crtc(encoder->crtc)->pipe;
12030 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12031 struct drm_file *file)
12033 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12034 struct drm_crtc *drmmode_crtc;
12035 struct intel_crtc *crtc;
12037 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12040 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12042 if (!drmmode_crtc) {
12043 DRM_ERROR("no such CRTC id\n");
12047 crtc = to_intel_crtc(drmmode_crtc);
12048 pipe_from_crtc_id->pipe = crtc->pipe;
12053 static int intel_encoder_clones(struct intel_encoder *encoder)
12055 struct drm_device *dev = encoder->base.dev;
12056 struct intel_encoder *source_encoder;
12057 int index_mask = 0;
12060 for_each_intel_encoder(dev, source_encoder) {
12061 if (encoders_cloneable(encoder, source_encoder))
12062 index_mask |= (1 << entry);
12070 static bool has_edp_a(struct drm_device *dev)
12072 struct drm_i915_private *dev_priv = dev->dev_private;
12074 if (!IS_MOBILE(dev))
12077 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12080 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12086 const char *intel_output_name(int output)
12088 static const char *names[] = {
12089 [INTEL_OUTPUT_UNUSED] = "Unused",
12090 [INTEL_OUTPUT_ANALOG] = "Analog",
12091 [INTEL_OUTPUT_DVO] = "DVO",
12092 [INTEL_OUTPUT_SDVO] = "SDVO",
12093 [INTEL_OUTPUT_LVDS] = "LVDS",
12094 [INTEL_OUTPUT_TVOUT] = "TV",
12095 [INTEL_OUTPUT_HDMI] = "HDMI",
12096 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12097 [INTEL_OUTPUT_EDP] = "eDP",
12098 [INTEL_OUTPUT_DSI] = "DSI",
12099 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12102 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12105 return names[output];
12108 static bool intel_crt_present(struct drm_device *dev)
12110 struct drm_i915_private *dev_priv = dev->dev_private;
12112 if (INTEL_INFO(dev)->gen >= 9)
12115 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12118 if (IS_CHERRYVIEW(dev))
12121 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12127 static void intel_setup_outputs(struct drm_device *dev)
12129 struct drm_i915_private *dev_priv = dev->dev_private;
12130 struct intel_encoder *encoder;
12131 bool dpd_is_edp = false;
12133 intel_lvds_init(dev);
12135 if (intel_crt_present(dev))
12136 intel_crt_init(dev);
12138 if (HAS_DDI(dev)) {
12141 /* Haswell uses DDI functions to detect digital outputs */
12142 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12143 /* DDI A only supports eDP */
12145 intel_ddi_init(dev, PORT_A);
12147 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12149 found = I915_READ(SFUSE_STRAP);
12151 if (found & SFUSE_STRAP_DDIB_DETECTED)
12152 intel_ddi_init(dev, PORT_B);
12153 if (found & SFUSE_STRAP_DDIC_DETECTED)
12154 intel_ddi_init(dev, PORT_C);
12155 if (found & SFUSE_STRAP_DDID_DETECTED)
12156 intel_ddi_init(dev, PORT_D);
12157 } else if (HAS_PCH_SPLIT(dev)) {
12159 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12161 if (has_edp_a(dev))
12162 intel_dp_init(dev, DP_A, PORT_A);
12164 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12165 /* PCH SDVOB multiplex with HDMIB */
12166 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12168 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12169 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12170 intel_dp_init(dev, PCH_DP_B, PORT_B);
12173 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12174 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12176 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12177 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12179 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12180 intel_dp_init(dev, PCH_DP_C, PORT_C);
12182 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12183 intel_dp_init(dev, PCH_DP_D, PORT_D);
12184 } else if (IS_VALLEYVIEW(dev)) {
12186 * The DP_DETECTED bit is the latched state of the DDC
12187 * SDA pin at boot. However since eDP doesn't require DDC
12188 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12189 * eDP ports may have been muxed to an alternate function.
12190 * Thus we can't rely on the DP_DETECTED bit alone to detect
12191 * eDP ports. Consult the VBT as well as DP_DETECTED to
12192 * detect eDP ports.
12194 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12195 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12197 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12198 intel_dp_is_edp(dev, PORT_B))
12199 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12201 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12202 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12204 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12205 intel_dp_is_edp(dev, PORT_C))
12206 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12208 if (IS_CHERRYVIEW(dev)) {
12209 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12210 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12212 /* eDP not supported on port D, so don't check VBT */
12213 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12214 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12217 intel_dsi_init(dev);
12218 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12219 bool found = false;
12221 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12222 DRM_DEBUG_KMS("probing SDVOB\n");
12223 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12224 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12225 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12226 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12229 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12230 intel_dp_init(dev, DP_B, PORT_B);
12233 /* Before G4X SDVOC doesn't have its own detect register */
12235 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12236 DRM_DEBUG_KMS("probing SDVOC\n");
12237 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12240 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12242 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12243 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12244 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12246 if (SUPPORTS_INTEGRATED_DP(dev))
12247 intel_dp_init(dev, DP_C, PORT_C);
12250 if (SUPPORTS_INTEGRATED_DP(dev) &&
12251 (I915_READ(DP_D) & DP_DETECTED))
12252 intel_dp_init(dev, DP_D, PORT_D);
12253 } else if (IS_GEN2(dev))
12254 intel_dvo_init(dev);
12256 if (SUPPORTS_TV(dev))
12257 intel_tv_init(dev);
12259 intel_edp_psr_init(dev);
12261 for_each_intel_encoder(dev, encoder) {
12262 encoder->base.possible_crtcs = encoder->crtc_mask;
12263 encoder->base.possible_clones =
12264 intel_encoder_clones(encoder);
12267 intel_init_pch_refclk(dev);
12269 drm_helper_move_panel_connectors_to_head(dev);
12272 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12274 struct drm_device *dev = fb->dev;
12275 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12277 drm_framebuffer_cleanup(fb);
12278 mutex_lock(&dev->struct_mutex);
12279 WARN_ON(!intel_fb->obj->framebuffer_references--);
12280 drm_gem_object_unreference(&intel_fb->obj->base);
12281 mutex_unlock(&dev->struct_mutex);
12285 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12286 struct drm_file *file,
12287 unsigned int *handle)
12289 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12290 struct drm_i915_gem_object *obj = intel_fb->obj;
12292 return drm_gem_handle_create(file, &obj->base, handle);
12295 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12296 .destroy = intel_user_framebuffer_destroy,
12297 .create_handle = intel_user_framebuffer_create_handle,
12300 static int intel_framebuffer_init(struct drm_device *dev,
12301 struct intel_framebuffer *intel_fb,
12302 struct drm_mode_fb_cmd2 *mode_cmd,
12303 struct drm_i915_gem_object *obj)
12305 int aligned_height;
12309 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12311 if (obj->tiling_mode == I915_TILING_Y) {
12312 DRM_DEBUG("hardware does not support tiling Y\n");
12316 if (mode_cmd->pitches[0] & 63) {
12317 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12318 mode_cmd->pitches[0]);
12322 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12323 pitch_limit = 32*1024;
12324 } else if (INTEL_INFO(dev)->gen >= 4) {
12325 if (obj->tiling_mode)
12326 pitch_limit = 16*1024;
12328 pitch_limit = 32*1024;
12329 } else if (INTEL_INFO(dev)->gen >= 3) {
12330 if (obj->tiling_mode)
12331 pitch_limit = 8*1024;
12333 pitch_limit = 16*1024;
12335 /* XXX DSPC is limited to 4k tiled */
12336 pitch_limit = 8*1024;
12338 if (mode_cmd->pitches[0] > pitch_limit) {
12339 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12340 obj->tiling_mode ? "tiled" : "linear",
12341 mode_cmd->pitches[0], pitch_limit);
12345 if (obj->tiling_mode != I915_TILING_NONE &&
12346 mode_cmd->pitches[0] != obj->stride) {
12347 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12348 mode_cmd->pitches[0], obj->stride);
12352 /* Reject formats not supported by any plane early. */
12353 switch (mode_cmd->pixel_format) {
12354 case DRM_FORMAT_C8:
12355 case DRM_FORMAT_RGB565:
12356 case DRM_FORMAT_XRGB8888:
12357 case DRM_FORMAT_ARGB8888:
12359 case DRM_FORMAT_XRGB1555:
12360 case DRM_FORMAT_ARGB1555:
12361 if (INTEL_INFO(dev)->gen > 3) {
12362 DRM_DEBUG("unsupported pixel format: %s\n",
12363 drm_get_format_name(mode_cmd->pixel_format));
12367 case DRM_FORMAT_XBGR8888:
12368 case DRM_FORMAT_ABGR8888:
12369 case DRM_FORMAT_XRGB2101010:
12370 case DRM_FORMAT_ARGB2101010:
12371 case DRM_FORMAT_XBGR2101010:
12372 case DRM_FORMAT_ABGR2101010:
12373 if (INTEL_INFO(dev)->gen < 4) {
12374 DRM_DEBUG("unsupported pixel format: %s\n",
12375 drm_get_format_name(mode_cmd->pixel_format));
12379 case DRM_FORMAT_YUYV:
12380 case DRM_FORMAT_UYVY:
12381 case DRM_FORMAT_YVYU:
12382 case DRM_FORMAT_VYUY:
12383 if (INTEL_INFO(dev)->gen < 5) {
12384 DRM_DEBUG("unsupported pixel format: %s\n",
12385 drm_get_format_name(mode_cmd->pixel_format));
12390 DRM_DEBUG("unsupported pixel format: %s\n",
12391 drm_get_format_name(mode_cmd->pixel_format));
12395 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12396 if (mode_cmd->offsets[0] != 0)
12399 aligned_height = intel_align_height(dev, mode_cmd->height,
12401 /* FIXME drm helper for size checks (especially planar formats)? */
12402 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12405 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12406 intel_fb->obj = obj;
12407 intel_fb->obj->framebuffer_references++;
12409 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12411 DRM_ERROR("framebuffer init failed %d\n", ret);
12418 static struct drm_framebuffer *
12419 intel_user_framebuffer_create(struct drm_device *dev,
12420 struct drm_file *filp,
12421 struct drm_mode_fb_cmd2 *mode_cmd)
12423 struct drm_i915_gem_object *obj;
12425 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12426 mode_cmd->handles[0]));
12427 if (&obj->base == NULL)
12428 return ERR_PTR(-ENOENT);
12430 return intel_framebuffer_create(dev, mode_cmd, obj);
12433 #ifndef CONFIG_DRM_I915_FBDEV
12434 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12439 static const struct drm_mode_config_funcs intel_mode_funcs = {
12440 .fb_create = intel_user_framebuffer_create,
12441 .output_poll_changed = intel_fbdev_output_poll_changed,
12444 /* Set up chip specific display functions */
12445 static void intel_init_display(struct drm_device *dev)
12447 struct drm_i915_private *dev_priv = dev->dev_private;
12449 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12450 dev_priv->display.find_dpll = g4x_find_best_dpll;
12451 else if (IS_CHERRYVIEW(dev))
12452 dev_priv->display.find_dpll = chv_find_best_dpll;
12453 else if (IS_VALLEYVIEW(dev))
12454 dev_priv->display.find_dpll = vlv_find_best_dpll;
12455 else if (IS_PINEVIEW(dev))
12456 dev_priv->display.find_dpll = pnv_find_best_dpll;
12458 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12460 if (HAS_DDI(dev)) {
12461 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12462 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12463 dev_priv->display.crtc_compute_clock =
12464 haswell_crtc_compute_clock;
12465 dev_priv->display.crtc_enable = haswell_crtc_enable;
12466 dev_priv->display.crtc_disable = haswell_crtc_disable;
12467 dev_priv->display.off = ironlake_crtc_off;
12468 if (INTEL_INFO(dev)->gen >= 9)
12469 dev_priv->display.update_primary_plane =
12470 skylake_update_primary_plane;
12472 dev_priv->display.update_primary_plane =
12473 ironlake_update_primary_plane;
12474 } else if (HAS_PCH_SPLIT(dev)) {
12475 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12476 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12477 dev_priv->display.crtc_compute_clock =
12478 ironlake_crtc_compute_clock;
12479 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12480 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12481 dev_priv->display.off = ironlake_crtc_off;
12482 dev_priv->display.update_primary_plane =
12483 ironlake_update_primary_plane;
12484 } else if (IS_VALLEYVIEW(dev)) {
12485 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12486 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12487 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12488 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12489 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12490 dev_priv->display.off = i9xx_crtc_off;
12491 dev_priv->display.update_primary_plane =
12492 i9xx_update_primary_plane;
12494 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12495 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12496 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12497 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12498 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12499 dev_priv->display.off = i9xx_crtc_off;
12500 dev_priv->display.update_primary_plane =
12501 i9xx_update_primary_plane;
12504 /* Returns the core display clock speed */
12505 if (IS_VALLEYVIEW(dev))
12506 dev_priv->display.get_display_clock_speed =
12507 valleyview_get_display_clock_speed;
12508 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12509 dev_priv->display.get_display_clock_speed =
12510 i945_get_display_clock_speed;
12511 else if (IS_I915G(dev))
12512 dev_priv->display.get_display_clock_speed =
12513 i915_get_display_clock_speed;
12514 else if (IS_I945GM(dev) || IS_845G(dev))
12515 dev_priv->display.get_display_clock_speed =
12516 i9xx_misc_get_display_clock_speed;
12517 else if (IS_PINEVIEW(dev))
12518 dev_priv->display.get_display_clock_speed =
12519 pnv_get_display_clock_speed;
12520 else if (IS_I915GM(dev))
12521 dev_priv->display.get_display_clock_speed =
12522 i915gm_get_display_clock_speed;
12523 else if (IS_I865G(dev))
12524 dev_priv->display.get_display_clock_speed =
12525 i865_get_display_clock_speed;
12526 else if (IS_I85X(dev))
12527 dev_priv->display.get_display_clock_speed =
12528 i855_get_display_clock_speed;
12529 else /* 852, 830 */
12530 dev_priv->display.get_display_clock_speed =
12531 i830_get_display_clock_speed;
12533 if (IS_GEN5(dev)) {
12534 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12535 } else if (IS_GEN6(dev)) {
12536 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12537 dev_priv->display.modeset_global_resources =
12538 snb_modeset_global_resources;
12539 } else if (IS_IVYBRIDGE(dev)) {
12540 /* FIXME: detect B0+ stepping and use auto training */
12541 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12542 dev_priv->display.modeset_global_resources =
12543 ivb_modeset_global_resources;
12544 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12545 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12546 dev_priv->display.modeset_global_resources =
12547 haswell_modeset_global_resources;
12548 } else if (IS_VALLEYVIEW(dev)) {
12549 dev_priv->display.modeset_global_resources =
12550 valleyview_modeset_global_resources;
12551 } else if (INTEL_INFO(dev)->gen >= 9) {
12552 dev_priv->display.modeset_global_resources =
12553 haswell_modeset_global_resources;
12556 /* Default just returns -ENODEV to indicate unsupported */
12557 dev_priv->display.queue_flip = intel_default_queue_flip;
12559 switch (INTEL_INFO(dev)->gen) {
12561 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12565 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12570 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12574 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12577 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12578 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12582 intel_panel_init_backlight_funcs(dev);
12584 mutex_init(&dev_priv->pps_mutex);
12588 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12589 * resume, or other times. This quirk makes sure that's the case for
12590 * affected systems.
12592 static void quirk_pipea_force(struct drm_device *dev)
12594 struct drm_i915_private *dev_priv = dev->dev_private;
12596 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12597 DRM_INFO("applying pipe a force quirk\n");
12600 static void quirk_pipeb_force(struct drm_device *dev)
12602 struct drm_i915_private *dev_priv = dev->dev_private;
12604 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12605 DRM_INFO("applying pipe b force quirk\n");
12609 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12611 static void quirk_ssc_force_disable(struct drm_device *dev)
12613 struct drm_i915_private *dev_priv = dev->dev_private;
12614 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12615 DRM_INFO("applying lvds SSC disable quirk\n");
12619 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12622 static void quirk_invert_brightness(struct drm_device *dev)
12624 struct drm_i915_private *dev_priv = dev->dev_private;
12625 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12626 DRM_INFO("applying inverted panel brightness quirk\n");
12629 /* Some VBT's incorrectly indicate no backlight is present */
12630 static void quirk_backlight_present(struct drm_device *dev)
12632 struct drm_i915_private *dev_priv = dev->dev_private;
12633 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12634 DRM_INFO("applying backlight present quirk\n");
12637 struct intel_quirk {
12639 int subsystem_vendor;
12640 int subsystem_device;
12641 void (*hook)(struct drm_device *dev);
12644 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12645 struct intel_dmi_quirk {
12646 void (*hook)(struct drm_device *dev);
12647 const struct dmi_system_id (*dmi_id_list)[];
12650 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12652 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12656 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12658 .dmi_id_list = &(const struct dmi_system_id[]) {
12660 .callback = intel_dmi_reverse_brightness,
12661 .ident = "NCR Corporation",
12662 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12663 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12666 { } /* terminating entry */
12668 .hook = quirk_invert_brightness,
12672 static struct intel_quirk intel_quirks[] = {
12673 /* HP Mini needs pipe A force quirk (LP: #322104) */
12674 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12676 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12677 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12679 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12680 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12682 /* 830 needs to leave pipe A & dpll A up */
12683 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12685 /* 830 needs to leave pipe B & dpll B up */
12686 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12688 /* Lenovo U160 cannot use SSC on LVDS */
12689 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12691 /* Sony Vaio Y cannot use SSC on LVDS */
12692 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12694 /* Acer Aspire 5734Z must invert backlight brightness */
12695 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12697 /* Acer/eMachines G725 */
12698 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12700 /* Acer/eMachines e725 */
12701 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12703 /* Acer/Packard Bell NCL20 */
12704 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12706 /* Acer Aspire 4736Z */
12707 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12709 /* Acer Aspire 5336 */
12710 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12712 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12713 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12715 /* Acer C720 Chromebook (Core i3 4005U) */
12716 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12718 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12719 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12721 /* HP Chromebook 14 (Celeron 2955U) */
12722 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12725 static void intel_init_quirks(struct drm_device *dev)
12727 struct pci_dev *d = dev->pdev;
12730 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12731 struct intel_quirk *q = &intel_quirks[i];
12733 if (d->device == q->device &&
12734 (d->subsystem_vendor == q->subsystem_vendor ||
12735 q->subsystem_vendor == PCI_ANY_ID) &&
12736 (d->subsystem_device == q->subsystem_device ||
12737 q->subsystem_device == PCI_ANY_ID))
12740 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12741 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12742 intel_dmi_quirks[i].hook(dev);
12746 /* Disable the VGA plane that we never use */
12747 static void i915_disable_vga(struct drm_device *dev)
12749 struct drm_i915_private *dev_priv = dev->dev_private;
12751 u32 vga_reg = i915_vgacntrl_reg(dev);
12753 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12754 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12755 outb(SR01, VGA_SR_INDEX);
12756 sr1 = inb(VGA_SR_DATA);
12757 outb(sr1 | 1<<5, VGA_SR_DATA);
12758 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12762 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12763 * from S3 without preserving (some of?) the other bits.
12765 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12766 POSTING_READ(vga_reg);
12769 void intel_modeset_init_hw(struct drm_device *dev)
12771 intel_prepare_ddi(dev);
12773 if (IS_VALLEYVIEW(dev))
12774 vlv_update_cdclk(dev);
12776 intel_init_clock_gating(dev);
12778 intel_enable_gt_powersave(dev);
12781 void intel_modeset_init(struct drm_device *dev)
12783 struct drm_i915_private *dev_priv = dev->dev_private;
12786 struct intel_crtc *crtc;
12788 drm_mode_config_init(dev);
12790 dev->mode_config.min_width = 0;
12791 dev->mode_config.min_height = 0;
12793 dev->mode_config.preferred_depth = 24;
12794 dev->mode_config.prefer_shadow = 1;
12796 dev->mode_config.funcs = &intel_mode_funcs;
12798 intel_init_quirks(dev);
12800 intel_init_pm(dev);
12802 if (INTEL_INFO(dev)->num_pipes == 0)
12805 intel_init_display(dev);
12806 intel_init_audio(dev);
12808 if (IS_GEN2(dev)) {
12809 dev->mode_config.max_width = 2048;
12810 dev->mode_config.max_height = 2048;
12811 } else if (IS_GEN3(dev)) {
12812 dev->mode_config.max_width = 4096;
12813 dev->mode_config.max_height = 4096;
12815 dev->mode_config.max_width = 8192;
12816 dev->mode_config.max_height = 8192;
12819 if (IS_845G(dev) || IS_I865G(dev)) {
12820 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12821 dev->mode_config.cursor_height = 1023;
12822 } else if (IS_GEN2(dev)) {
12823 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12824 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12826 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12827 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12830 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12832 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12833 INTEL_INFO(dev)->num_pipes,
12834 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12836 for_each_pipe(dev_priv, pipe) {
12837 intel_crtc_init(dev, pipe);
12838 for_each_sprite(pipe, sprite) {
12839 ret = intel_plane_init(dev, pipe, sprite);
12841 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12842 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12846 intel_init_dpio(dev);
12848 intel_shared_dpll_init(dev);
12850 /* save the BIOS value before clobbering it */
12851 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12852 /* Just disable it once at startup */
12853 i915_disable_vga(dev);
12854 intel_setup_outputs(dev);
12856 /* Just in case the BIOS is doing something questionable. */
12857 intel_disable_fbc(dev);
12859 drm_modeset_lock_all(dev);
12860 intel_modeset_setup_hw_state(dev, false);
12861 drm_modeset_unlock_all(dev);
12863 for_each_intel_crtc(dev, crtc) {
12868 * Note that reserving the BIOS fb up front prevents us
12869 * from stuffing other stolen allocations like the ring
12870 * on top. This prevents some ugliness at boot time, and
12871 * can even allow for smooth boot transitions if the BIOS
12872 * fb is large enough for the active pipe configuration.
12874 if (dev_priv->display.get_plane_config) {
12875 dev_priv->display.get_plane_config(crtc,
12876 &crtc->plane_config);
12878 * If the fb is shared between multiple heads, we'll
12879 * just get the first one.
12881 intel_find_plane_obj(crtc, &crtc->plane_config);
12886 static void intel_enable_pipe_a(struct drm_device *dev)
12888 struct intel_connector *connector;
12889 struct drm_connector *crt = NULL;
12890 struct intel_load_detect_pipe load_detect_temp;
12891 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12893 /* We can't just switch on the pipe A, we need to set things up with a
12894 * proper mode and output configuration. As a gross hack, enable pipe A
12895 * by enabling the load detect pipe once. */
12896 list_for_each_entry(connector,
12897 &dev->mode_config.connector_list,
12899 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12900 crt = &connector->base;
12908 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12909 intel_release_load_detect_pipe(crt, &load_detect_temp);
12913 intel_check_plane_mapping(struct intel_crtc *crtc)
12915 struct drm_device *dev = crtc->base.dev;
12916 struct drm_i915_private *dev_priv = dev->dev_private;
12919 if (INTEL_INFO(dev)->num_pipes == 1)
12922 reg = DSPCNTR(!crtc->plane);
12923 val = I915_READ(reg);
12925 if ((val & DISPLAY_PLANE_ENABLE) &&
12926 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12932 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12934 struct drm_device *dev = crtc->base.dev;
12935 struct drm_i915_private *dev_priv = dev->dev_private;
12938 /* Clear any frame start delays used for debugging left by the BIOS */
12939 reg = PIPECONF(crtc->config.cpu_transcoder);
12940 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12942 /* restore vblank interrupts to correct state */
12943 if (crtc->active) {
12944 update_scanline_offset(crtc);
12945 drm_vblank_on(dev, crtc->pipe);
12947 drm_vblank_off(dev, crtc->pipe);
12949 /* We need to sanitize the plane -> pipe mapping first because this will
12950 * disable the crtc (and hence change the state) if it is wrong. Note
12951 * that gen4+ has a fixed plane -> pipe mapping. */
12952 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12953 struct intel_connector *connector;
12956 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12957 crtc->base.base.id);
12959 /* Pipe has the wrong plane attached and the plane is active.
12960 * Temporarily change the plane mapping and disable everything
12962 plane = crtc->plane;
12963 crtc->plane = !plane;
12964 crtc->primary_enabled = true;
12965 dev_priv->display.crtc_disable(&crtc->base);
12966 crtc->plane = plane;
12968 /* ... and break all links. */
12969 list_for_each_entry(connector, &dev->mode_config.connector_list,
12971 if (connector->encoder->base.crtc != &crtc->base)
12974 connector->base.dpms = DRM_MODE_DPMS_OFF;
12975 connector->base.encoder = NULL;
12977 /* multiple connectors may have the same encoder:
12978 * handle them and break crtc link separately */
12979 list_for_each_entry(connector, &dev->mode_config.connector_list,
12981 if (connector->encoder->base.crtc == &crtc->base) {
12982 connector->encoder->base.crtc = NULL;
12983 connector->encoder->connectors_active = false;
12986 WARN_ON(crtc->active);
12987 crtc->base.enabled = false;
12990 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12991 crtc->pipe == PIPE_A && !crtc->active) {
12992 /* BIOS forgot to enable pipe A, this mostly happens after
12993 * resume. Force-enable the pipe to fix this, the update_dpms
12994 * call below we restore the pipe to the right state, but leave
12995 * the required bits on. */
12996 intel_enable_pipe_a(dev);
12999 /* Adjust the state of the output pipe according to whether we
13000 * have active connectors/encoders. */
13001 intel_crtc_update_dpms(&crtc->base);
13003 if (crtc->active != crtc->base.enabled) {
13004 struct intel_encoder *encoder;
13006 /* This can happen either due to bugs in the get_hw_state
13007 * functions or because the pipe is force-enabled due to the
13009 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13010 crtc->base.base.id,
13011 crtc->base.enabled ? "enabled" : "disabled",
13012 crtc->active ? "enabled" : "disabled");
13014 crtc->base.enabled = crtc->active;
13016 /* Because we only establish the connector -> encoder ->
13017 * crtc links if something is active, this means the
13018 * crtc is now deactivated. Break the links. connector
13019 * -> encoder links are only establish when things are
13020 * actually up, hence no need to break them. */
13021 WARN_ON(crtc->active);
13023 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13024 WARN_ON(encoder->connectors_active);
13025 encoder->base.crtc = NULL;
13029 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13031 * We start out with underrun reporting disabled to avoid races.
13032 * For correct bookkeeping mark this on active crtcs.
13034 * Also on gmch platforms we dont have any hardware bits to
13035 * disable the underrun reporting. Which means we need to start
13036 * out with underrun reporting disabled also on inactive pipes,
13037 * since otherwise we'll complain about the garbage we read when
13038 * e.g. coming up after runtime pm.
13040 * No protection against concurrent access is required - at
13041 * worst a fifo underrun happens which also sets this to false.
13043 crtc->cpu_fifo_underrun_disabled = true;
13044 crtc->pch_fifo_underrun_disabled = true;
13048 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13050 struct intel_connector *connector;
13051 struct drm_device *dev = encoder->base.dev;
13053 /* We need to check both for a crtc link (meaning that the
13054 * encoder is active and trying to read from a pipe) and the
13055 * pipe itself being active. */
13056 bool has_active_crtc = encoder->base.crtc &&
13057 to_intel_crtc(encoder->base.crtc)->active;
13059 if (encoder->connectors_active && !has_active_crtc) {
13060 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13061 encoder->base.base.id,
13062 encoder->base.name);
13064 /* Connector is active, but has no active pipe. This is
13065 * fallout from our resume register restoring. Disable
13066 * the encoder manually again. */
13067 if (encoder->base.crtc) {
13068 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13069 encoder->base.base.id,
13070 encoder->base.name);
13071 encoder->disable(encoder);
13072 if (encoder->post_disable)
13073 encoder->post_disable(encoder);
13075 encoder->base.crtc = NULL;
13076 encoder->connectors_active = false;
13078 /* Inconsistent output/port/pipe state happens presumably due to
13079 * a bug in one of the get_hw_state functions. Or someplace else
13080 * in our code, like the register restore mess on resume. Clamp
13081 * things to off as a safer default. */
13082 list_for_each_entry(connector,
13083 &dev->mode_config.connector_list,
13085 if (connector->encoder != encoder)
13087 connector->base.dpms = DRM_MODE_DPMS_OFF;
13088 connector->base.encoder = NULL;
13091 /* Enabled encoders without active connectors will be fixed in
13092 * the crtc fixup. */
13095 void i915_redisable_vga_power_on(struct drm_device *dev)
13097 struct drm_i915_private *dev_priv = dev->dev_private;
13098 u32 vga_reg = i915_vgacntrl_reg(dev);
13100 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13101 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13102 i915_disable_vga(dev);
13106 void i915_redisable_vga(struct drm_device *dev)
13108 struct drm_i915_private *dev_priv = dev->dev_private;
13110 /* This function can be called both from intel_modeset_setup_hw_state or
13111 * at a very early point in our resume sequence, where the power well
13112 * structures are not yet restored. Since this function is at a very
13113 * paranoid "someone might have enabled VGA while we were not looking"
13114 * level, just check if the power well is enabled instead of trying to
13115 * follow the "don't touch the power well if we don't need it" policy
13116 * the rest of the driver uses. */
13117 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13120 i915_redisable_vga_power_on(dev);
13123 static bool primary_get_hw_state(struct intel_crtc *crtc)
13125 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13130 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13133 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13135 struct drm_i915_private *dev_priv = dev->dev_private;
13137 struct intel_crtc *crtc;
13138 struct intel_encoder *encoder;
13139 struct intel_connector *connector;
13142 for_each_intel_crtc(dev, crtc) {
13143 memset(&crtc->config, 0, sizeof(crtc->config));
13145 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13147 crtc->active = dev_priv->display.get_pipe_config(crtc,
13150 crtc->base.enabled = crtc->active;
13151 crtc->primary_enabled = primary_get_hw_state(crtc);
13153 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13154 crtc->base.base.id,
13155 crtc->active ? "enabled" : "disabled");
13158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13159 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13161 pll->on = pll->get_hw_state(dev_priv, pll,
13162 &pll->config.hw_state);
13164 pll->config.crtc_mask = 0;
13165 for_each_intel_crtc(dev, crtc) {
13166 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13168 pll->config.crtc_mask |= 1 << crtc->pipe;
13172 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13173 pll->name, pll->config.crtc_mask, pll->on);
13175 if (pll->config.crtc_mask)
13176 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13179 for_each_intel_encoder(dev, encoder) {
13182 if (encoder->get_hw_state(encoder, &pipe)) {
13183 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13184 encoder->base.crtc = &crtc->base;
13185 encoder->get_config(encoder, &crtc->config);
13187 encoder->base.crtc = NULL;
13190 encoder->connectors_active = false;
13191 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13192 encoder->base.base.id,
13193 encoder->base.name,
13194 encoder->base.crtc ? "enabled" : "disabled",
13198 list_for_each_entry(connector, &dev->mode_config.connector_list,
13200 if (connector->get_hw_state(connector)) {
13201 connector->base.dpms = DRM_MODE_DPMS_ON;
13202 connector->encoder->connectors_active = true;
13203 connector->base.encoder = &connector->encoder->base;
13205 connector->base.dpms = DRM_MODE_DPMS_OFF;
13206 connector->base.encoder = NULL;
13208 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13209 connector->base.base.id,
13210 connector->base.name,
13211 connector->base.encoder ? "enabled" : "disabled");
13215 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13216 * and i915 state tracking structures. */
13217 void intel_modeset_setup_hw_state(struct drm_device *dev,
13218 bool force_restore)
13220 struct drm_i915_private *dev_priv = dev->dev_private;
13222 struct intel_crtc *crtc;
13223 struct intel_encoder *encoder;
13226 intel_modeset_readout_hw_state(dev);
13229 * Now that we have the config, copy it to each CRTC struct
13230 * Note that this could go away if we move to using crtc_config
13231 * checking everywhere.
13233 for_each_intel_crtc(dev, crtc) {
13234 if (crtc->active && i915.fastboot) {
13235 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13236 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13237 crtc->base.base.id);
13238 drm_mode_debug_printmodeline(&crtc->base.mode);
13242 /* HW state is read out, now we need to sanitize this mess. */
13243 for_each_intel_encoder(dev, encoder) {
13244 intel_sanitize_encoder(encoder);
13247 for_each_pipe(dev_priv, pipe) {
13248 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13249 intel_sanitize_crtc(crtc);
13250 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13253 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13254 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13256 if (!pll->on || pll->active)
13259 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13261 pll->disable(dev_priv, pll);
13265 if (HAS_PCH_SPLIT(dev))
13266 ilk_wm_get_hw_state(dev);
13268 if (force_restore) {
13269 i915_redisable_vga(dev);
13272 * We need to use raw interfaces for restoring state to avoid
13273 * checking (bogus) intermediate states.
13275 for_each_pipe(dev_priv, pipe) {
13276 struct drm_crtc *crtc =
13277 dev_priv->pipe_to_crtc_mapping[pipe];
13279 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13280 crtc->primary->fb);
13283 intel_modeset_update_staged_output_state(dev);
13286 intel_modeset_check_state(dev);
13289 void intel_modeset_gem_init(struct drm_device *dev)
13291 struct drm_crtc *c;
13292 struct drm_i915_gem_object *obj;
13294 mutex_lock(&dev->struct_mutex);
13295 intel_init_gt_powersave(dev);
13296 mutex_unlock(&dev->struct_mutex);
13298 intel_modeset_init_hw(dev);
13300 intel_setup_overlay(dev);
13303 * Make sure any fbs we allocated at startup are properly
13304 * pinned & fenced. When we do the allocation it's too early
13307 mutex_lock(&dev->struct_mutex);
13308 for_each_crtc(dev, c) {
13309 obj = intel_fb_obj(c->primary->fb);
13313 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13314 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13315 to_intel_crtc(c)->pipe);
13316 drm_framebuffer_unreference(c->primary->fb);
13317 c->primary->fb = NULL;
13320 mutex_unlock(&dev->struct_mutex);
13323 void intel_connector_unregister(struct intel_connector *intel_connector)
13325 struct drm_connector *connector = &intel_connector->base;
13327 intel_panel_destroy_backlight(connector);
13328 drm_connector_unregister(connector);
13331 void intel_modeset_cleanup(struct drm_device *dev)
13333 struct drm_i915_private *dev_priv = dev->dev_private;
13334 struct drm_connector *connector;
13337 * Interrupts and polling as the first thing to avoid creating havoc.
13338 * Too much stuff here (turning of rps, connectors, ...) would
13339 * experience fancy races otherwise.
13341 intel_irq_uninstall(dev_priv);
13344 * Due to the hpd irq storm handling the hotplug work can re-arm the
13345 * poll handlers. Hence disable polling after hpd handling is shut down.
13347 drm_kms_helper_poll_fini(dev);
13349 mutex_lock(&dev->struct_mutex);
13351 intel_unregister_dsm_handler();
13353 intel_disable_fbc(dev);
13355 intel_disable_gt_powersave(dev);
13357 ironlake_teardown_rc6(dev);
13359 mutex_unlock(&dev->struct_mutex);
13361 /* flush any delayed tasks or pending work */
13362 flush_scheduled_work();
13364 /* destroy the backlight and sysfs files before encoders/connectors */
13365 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13366 struct intel_connector *intel_connector;
13368 intel_connector = to_intel_connector(connector);
13369 intel_connector->unregister(intel_connector);
13372 drm_mode_config_cleanup(dev);
13374 intel_cleanup_overlay(dev);
13376 mutex_lock(&dev->struct_mutex);
13377 intel_cleanup_gt_powersave(dev);
13378 mutex_unlock(&dev->struct_mutex);
13382 * Return which encoder is currently attached for connector.
13384 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13386 return &intel_attached_encoder(connector)->base;
13389 void intel_connector_attach_encoder(struct intel_connector *connector,
13390 struct intel_encoder *encoder)
13392 connector->encoder = encoder;
13393 drm_mode_connector_attach_encoder(&connector->base,
13398 * set vga decode state - true == enable VGA decode
13400 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13402 struct drm_i915_private *dev_priv = dev->dev_private;
13403 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13406 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13407 DRM_ERROR("failed to read control word\n");
13411 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13415 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13417 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13419 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13420 DRM_ERROR("failed to write control word\n");
13427 struct intel_display_error_state {
13429 u32 power_well_driver;
13431 int num_transcoders;
13433 struct intel_cursor_error_state {
13438 } cursor[I915_MAX_PIPES];
13440 struct intel_pipe_error_state {
13441 bool power_domain_on;
13444 } pipe[I915_MAX_PIPES];
13446 struct intel_plane_error_state {
13454 } plane[I915_MAX_PIPES];
13456 struct intel_transcoder_error_state {
13457 bool power_domain_on;
13458 enum transcoder cpu_transcoder;
13471 struct intel_display_error_state *
13472 intel_display_capture_error_state(struct drm_device *dev)
13474 struct drm_i915_private *dev_priv = dev->dev_private;
13475 struct intel_display_error_state *error;
13476 int transcoders[] = {
13484 if (INTEL_INFO(dev)->num_pipes == 0)
13487 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13491 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13492 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13494 for_each_pipe(dev_priv, i) {
13495 error->pipe[i].power_domain_on =
13496 __intel_display_power_is_enabled(dev_priv,
13497 POWER_DOMAIN_PIPE(i));
13498 if (!error->pipe[i].power_domain_on)
13501 error->cursor[i].control = I915_READ(CURCNTR(i));
13502 error->cursor[i].position = I915_READ(CURPOS(i));
13503 error->cursor[i].base = I915_READ(CURBASE(i));
13505 error->plane[i].control = I915_READ(DSPCNTR(i));
13506 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13507 if (INTEL_INFO(dev)->gen <= 3) {
13508 error->plane[i].size = I915_READ(DSPSIZE(i));
13509 error->plane[i].pos = I915_READ(DSPPOS(i));
13511 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13512 error->plane[i].addr = I915_READ(DSPADDR(i));
13513 if (INTEL_INFO(dev)->gen >= 4) {
13514 error->plane[i].surface = I915_READ(DSPSURF(i));
13515 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13518 error->pipe[i].source = I915_READ(PIPESRC(i));
13520 if (HAS_GMCH_DISPLAY(dev))
13521 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13524 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13525 if (HAS_DDI(dev_priv->dev))
13526 error->num_transcoders++; /* Account for eDP. */
13528 for (i = 0; i < error->num_transcoders; i++) {
13529 enum transcoder cpu_transcoder = transcoders[i];
13531 error->transcoder[i].power_domain_on =
13532 __intel_display_power_is_enabled(dev_priv,
13533 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13534 if (!error->transcoder[i].power_domain_on)
13537 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13539 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13540 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13541 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13542 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13543 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13544 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13545 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13551 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13554 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13555 struct drm_device *dev,
13556 struct intel_display_error_state *error)
13558 struct drm_i915_private *dev_priv = dev->dev_private;
13564 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13565 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13566 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13567 error->power_well_driver);
13568 for_each_pipe(dev_priv, i) {
13569 err_printf(m, "Pipe [%d]:\n", i);
13570 err_printf(m, " Power: %s\n",
13571 error->pipe[i].power_domain_on ? "on" : "off");
13572 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13573 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13575 err_printf(m, "Plane [%d]:\n", i);
13576 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13577 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13578 if (INTEL_INFO(dev)->gen <= 3) {
13579 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13580 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13582 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13583 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13584 if (INTEL_INFO(dev)->gen >= 4) {
13585 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13586 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13589 err_printf(m, "Cursor [%d]:\n", i);
13590 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13591 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13592 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13595 for (i = 0; i < error->num_transcoders; i++) {
13596 err_printf(m, "CPU transcoder: %c\n",
13597 transcoder_name(error->transcoder[i].cpu_transcoder));
13598 err_printf(m, " Power: %s\n",
13599 error->transcoder[i].power_domain_on ? "on" : "off");
13600 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13601 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13602 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13603 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13604 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13605 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13606 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13610 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13612 struct intel_crtc *crtc;
13614 for_each_intel_crtc(dev, crtc) {
13615 struct intel_unpin_work *work;
13617 spin_lock_irq(&dev->event_lock);
13619 work = crtc->unpin_work;
13621 if (work && work->event &&
13622 work->event->base.file_priv == file) {
13623 kfree(work->event);
13624 work->event = NULL;
13627 spin_unlock_irq(&dev->event_lock);