drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198                            struct drm_i915_gem_object *obj,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         u32 alignment;
2203         int ret;
2204
2205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207         switch (obj->tiling_mode) {
2208         case I915_TILING_NONE:
2209                 if (INTEL_INFO(dev)->gen >= 9)
2210                         alignment = 256 * 1024;
2211                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212                         alignment = 128 * 1024;
2213                 else if (INTEL_INFO(dev)->gen >= 4)
2214                         alignment = 4 * 1024;
2215                 else
2216                         alignment = 64 * 1024;
2217                 break;
2218         case I915_TILING_X:
2219                 if (INTEL_INFO(dev)->gen >= 9)
2220                         alignment = 256 * 1024;
2221                 else {
2222                         /* pin() will align the object as required by fence */
2223                         alignment = 0;
2224                 }
2225                 break;
2226         case I915_TILING_Y:
2227                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228                 return -EINVAL;
2229         default:
2230                 BUG();
2231         }
2232
2233         /* Note that the w/a also requires 64 PTE of padding following the
2234          * bo. We currently fill all unused PTE with the shadow page and so
2235          * we should always have valid PTE following the scanout preventing
2236          * the VT-d warning.
2237          */
2238         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239                 alignment = 256 * 1024;
2240
2241         /*
2242          * Global gtt pte registers are special registers which actually forward
2243          * writes to a chunk of system memory. Which means that there is no risk
2244          * that the register values disappear as soon as we call
2245          * intel_runtime_pm_put(), so it is correct to wrap only the
2246          * pin/unpin/fence and not more.
2247          */
2248         intel_runtime_pm_get(dev_priv);
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         intel_runtime_pm_put(dev_priv);
2268         return 0;
2269
2270 err_unpin:
2271         i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282         i915_gem_object_unpin_fence(obj);
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287  * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289                                              unsigned int tiling_mode,
2290                                              unsigned int cpp,
2291                                              unsigned int pitch)
2292 {
2293         if (tiling_mode != I915_TILING_NONE) {
2294                 unsigned int tile_rows, tiles;
2295
2296                 tile_rows = *y / 8;
2297                 *y %= 8;
2298
2299                 tiles = *x / (512/cpp);
2300                 *x %= 512/cpp;
2301
2302                 return tile_rows * pitch * 8 + tiles * 4096;
2303         } else {
2304                 unsigned int offset;
2305
2306                 offset = *y * pitch + *x * cpp;
2307                 *y = 0;
2308                 *x = (offset & 4095) / cpp;
2309                 return offset & -4096;
2310         }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315         switch (format) {
2316         case DISPPLANE_8BPP:
2317                 return DRM_FORMAT_C8;
2318         case DISPPLANE_BGRX555:
2319                 return DRM_FORMAT_XRGB1555;
2320         case DISPPLANE_BGRX565:
2321                 return DRM_FORMAT_RGB565;
2322         default:
2323         case DISPPLANE_BGRX888:
2324                 return DRM_FORMAT_XRGB8888;
2325         case DISPPLANE_RGBX888:
2326                 return DRM_FORMAT_XBGR8888;
2327         case DISPPLANE_BGRX101010:
2328                 return DRM_FORMAT_XRGB2101010;
2329         case DISPPLANE_RGBX101010:
2330                 return DRM_FORMAT_XBGR2101010;
2331         }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335                                   struct intel_plane_config *plane_config)
2336 {
2337         struct drm_device *dev = crtc->base.dev;
2338         struct drm_i915_gem_object *obj = NULL;
2339         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340         u32 base = plane_config->base;
2341
2342         if (plane_config->size == 0)
2343                 return false;
2344
2345         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346                                                              plane_config->size);
2347         if (!obj)
2348                 return false;
2349
2350         if (plane_config->tiled) {
2351                 obj->tiling_mode = I915_TILING_X;
2352                 obj->stride = crtc->base.primary->fb->pitches[0];
2353         }
2354
2355         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356         mode_cmd.width = crtc->base.primary->fb->width;
2357         mode_cmd.height = crtc->base.primary->fb->height;
2358         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360         mutex_lock(&dev->struct_mutex);
2361
2362         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363                                    &mode_cmd, obj)) {
2364                 DRM_DEBUG_KMS("intel fb init failed\n");
2365                 goto out_unref_obj;
2366         }
2367
2368         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369         mutex_unlock(&dev->struct_mutex);
2370
2371         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372         return true;
2373
2374 out_unref_obj:
2375         drm_gem_object_unreference(&obj->base);
2376         mutex_unlock(&dev->struct_mutex);
2377         return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381                                  struct intel_plane_config *plane_config)
2382 {
2383         struct drm_device *dev = intel_crtc->base.dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_crtc *c;
2386         struct intel_crtc *i;
2387         struct drm_i915_gem_object *obj;
2388
2389         if (!intel_crtc->base.primary->fb)
2390                 return;
2391
2392         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393                 return;
2394
2395         kfree(intel_crtc->base.primary->fb);
2396         intel_crtc->base.primary->fb = NULL;
2397
2398         /*
2399          * Failed to alloc the obj, check to see if we should share
2400          * an fb with another CRTC instead
2401          */
2402         for_each_crtc(dev, c) {
2403                 i = to_intel_crtc(c);
2404
2405                 if (c == &intel_crtc->base)
2406                         continue;
2407
2408                 if (!i->active)
2409                         continue;
2410
2411                 obj = intel_fb_obj(c->primary->fb);
2412                 if (obj == NULL)
2413                         continue;
2414
2415                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416                         if (obj->tiling_mode != I915_TILING_NONE)
2417                                 dev_priv->preserve_bios_swizzle = true;
2418
2419                         drm_framebuffer_reference(c->primary->fb);
2420                         intel_crtc->base.primary->fb = c->primary->fb;
2421                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2422                         break;
2423                 }
2424         }
2425 }
2426
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428                                       struct drm_framebuffer *fb,
2429                                       int x, int y)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg = DSPCNTR(plane);
2439         int pixel_size;
2440
2441         if (!intel_crtc->primary_enabled) {
2442                 I915_WRITE(reg, 0);
2443                 if (INTEL_INFO(dev)->gen >= 4)
2444                         I915_WRITE(DSPSURF(plane), 0);
2445                 else
2446                         I915_WRITE(DSPADDR(plane), 0);
2447                 POSTING_READ(reg);
2448                 return;
2449         }
2450
2451         obj = intel_fb_obj(fb);
2452         if (WARN_ON(obj == NULL))
2453                 return;
2454
2455         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
2457         dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
2459         dspcntr |= DISPLAY_PLANE_ENABLE;
2460
2461         if (INTEL_INFO(dev)->gen < 4) {
2462                 if (intel_crtc->pipe == PIPE_B)
2463                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465                 /* pipesrc and dspsize control the size that is scaled from,
2466                  * which should always be the user's requested size.
2467                  */
2468                 I915_WRITE(DSPSIZE(plane),
2469                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470                            (intel_crtc->config.pipe_src_w - 1));
2471                 I915_WRITE(DSPPOS(plane), 0);
2472         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473                 I915_WRITE(PRIMSIZE(plane),
2474                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475                            (intel_crtc->config.pipe_src_w - 1));
2476                 I915_WRITE(PRIMPOS(plane), 0);
2477                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2478         }
2479
2480         switch (fb->pixel_format) {
2481         case DRM_FORMAT_C8:
2482                 dspcntr |= DISPPLANE_8BPP;
2483                 break;
2484         case DRM_FORMAT_XRGB1555:
2485         case DRM_FORMAT_ARGB1555:
2486                 dspcntr |= DISPPLANE_BGRX555;
2487                 break;
2488         case DRM_FORMAT_RGB565:
2489                 dspcntr |= DISPPLANE_BGRX565;
2490                 break;
2491         case DRM_FORMAT_XRGB8888:
2492         case DRM_FORMAT_ARGB8888:
2493                 dspcntr |= DISPPLANE_BGRX888;
2494                 break;
2495         case DRM_FORMAT_XBGR8888:
2496         case DRM_FORMAT_ABGR8888:
2497                 dspcntr |= DISPPLANE_RGBX888;
2498                 break;
2499         case DRM_FORMAT_XRGB2101010:
2500         case DRM_FORMAT_ARGB2101010:
2501                 dspcntr |= DISPPLANE_BGRX101010;
2502                 break;
2503         case DRM_FORMAT_XBGR2101010:
2504         case DRM_FORMAT_ABGR2101010:
2505                 dspcntr |= DISPPLANE_RGBX101010;
2506                 break;
2507         default:
2508                 BUG();
2509         }
2510
2511         if (INTEL_INFO(dev)->gen >= 4 &&
2512             obj->tiling_mode != I915_TILING_NONE)
2513                 dspcntr |= DISPPLANE_TILED;
2514
2515         if (IS_G4X(dev))
2516                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
2518         linear_offset = y * fb->pitches[0] + x * pixel_size;
2519
2520         if (INTEL_INFO(dev)->gen >= 4) {
2521                 intel_crtc->dspaddr_offset =
2522                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2523                                                        pixel_size,
2524                                                        fb->pitches[0]);
2525                 linear_offset -= intel_crtc->dspaddr_offset;
2526         } else {
2527                 intel_crtc->dspaddr_offset = linear_offset;
2528         }
2529
2530         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531                 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533                 x += (intel_crtc->config.pipe_src_w - 1);
2534                 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536                 /* Finding the last pixel of the last line of the display
2537                 data and adding to linear_offset*/
2538                 linear_offset +=
2539                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541         }
2542
2543         I915_WRITE(reg, dspcntr);
2544
2545         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547                       fb->pitches[0]);
2548         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549         if (INTEL_INFO(dev)->gen >= 4) {
2550                 I915_WRITE(DSPSURF(plane),
2551                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2554         } else
2555                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2556         POSTING_READ(reg);
2557 }
2558
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560                                           struct drm_framebuffer *fb,
2561                                           int x, int y)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         struct drm_i915_gem_object *obj;
2567         int plane = intel_crtc->plane;
2568         unsigned long linear_offset;
2569         u32 dspcntr;
2570         u32 reg = DSPCNTR(plane);
2571         int pixel_size;
2572
2573         if (!intel_crtc->primary_enabled) {
2574                 I915_WRITE(reg, 0);
2575                 I915_WRITE(DSPSURF(plane), 0);
2576                 POSTING_READ(reg);
2577                 return;
2578         }
2579
2580         obj = intel_fb_obj(fb);
2581         if (WARN_ON(obj == NULL))
2582                 return;
2583
2584         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
2586         dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
2588         dspcntr |= DISPLAY_PLANE_ENABLE;
2589
2590         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
2593         switch (fb->pixel_format) {
2594         case DRM_FORMAT_C8:
2595                 dspcntr |= DISPPLANE_8BPP;
2596                 break;
2597         case DRM_FORMAT_RGB565:
2598                 dspcntr |= DISPPLANE_BGRX565;
2599                 break;
2600         case DRM_FORMAT_XRGB8888:
2601         case DRM_FORMAT_ARGB8888:
2602                 dspcntr |= DISPPLANE_BGRX888;
2603                 break;
2604         case DRM_FORMAT_XBGR8888:
2605         case DRM_FORMAT_ABGR8888:
2606                 dspcntr |= DISPPLANE_RGBX888;
2607                 break;
2608         case DRM_FORMAT_XRGB2101010:
2609         case DRM_FORMAT_ARGB2101010:
2610                 dspcntr |= DISPPLANE_BGRX101010;
2611                 break;
2612         case DRM_FORMAT_XBGR2101010:
2613         case DRM_FORMAT_ABGR2101010:
2614                 dspcntr |= DISPPLANE_RGBX101010;
2615                 break;
2616         default:
2617                 BUG();
2618         }
2619
2620         if (obj->tiling_mode != I915_TILING_NONE)
2621                 dspcntr |= DISPPLANE_TILED;
2622
2623         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2625
2626         linear_offset = y * fb->pitches[0] + x * pixel_size;
2627         intel_crtc->dspaddr_offset =
2628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629                                                pixel_size,
2630                                                fb->pitches[0]);
2631         linear_offset -= intel_crtc->dspaddr_offset;
2632         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633                 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636                         x += (intel_crtc->config.pipe_src_w - 1);
2637                         y += (intel_crtc->config.pipe_src_h - 1);
2638
2639                         /* Finding the last pixel of the last line of the display
2640                         data and adding to linear_offset*/
2641                         linear_offset +=
2642                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644                 }
2645         }
2646
2647         I915_WRITE(reg, dspcntr);
2648
2649         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651                       fb->pitches[0]);
2652         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653         I915_WRITE(DSPSURF(plane),
2654                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657         } else {
2658                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660         }
2661         POSTING_READ(reg);
2662 }
2663
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665                                          struct drm_framebuffer *fb,
2666                                          int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct intel_framebuffer *intel_fb;
2672         struct drm_i915_gem_object *obj;
2673         int pipe = intel_crtc->pipe;
2674         u32 plane_ctl, stride;
2675
2676         if (!intel_crtc->primary_enabled) {
2677                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679                 POSTING_READ(PLANE_CTL(pipe, 0));
2680                 return;
2681         }
2682
2683         plane_ctl = PLANE_CTL_ENABLE |
2684                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2685                     PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687         switch (fb->pixel_format) {
2688         case DRM_FORMAT_RGB565:
2689                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690                 break;
2691         case DRM_FORMAT_XRGB8888:
2692                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693                 break;
2694         case DRM_FORMAT_XBGR8888:
2695                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697                 break;
2698         case DRM_FORMAT_XRGB2101010:
2699                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700                 break;
2701         case DRM_FORMAT_XBGR2101010:
2702                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704                 break;
2705         default:
2706                 BUG();
2707         }
2708
2709         intel_fb = to_intel_framebuffer(fb);
2710         obj = intel_fb->obj;
2711
2712         /*
2713          * The stride is either expressed as a multiple of 64 bytes chunks for
2714          * linear buffers or in number of tiles for tiled buffers.
2715          */
2716         switch (obj->tiling_mode) {
2717         case I915_TILING_NONE:
2718                 stride = fb->pitches[0] >> 6;
2719                 break;
2720         case I915_TILING_X:
2721                 plane_ctl |= PLANE_CTL_TILED_X;
2722                 stride = fb->pitches[0] >> 9;
2723                 break;
2724         default:
2725                 BUG();
2726         }
2727
2728         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730                 plane_ctl |= PLANE_CTL_ROTATE_180;
2731
2732         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735                       i915_gem_obj_ggtt_offset(obj),
2736                       x, y, fb->width, fb->height,
2737                       fb->pitches[0]);
2738
2739         I915_WRITE(PLANE_POS(pipe, 0), 0);
2740         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741         I915_WRITE(PLANE_SIZE(pipe, 0),
2742                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2743                    (intel_crtc->config.pipe_src_w - 1));
2744         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747         POSTING_READ(PLANE_SURF(pipe, 0));
2748 }
2749
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2751 static int
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753                            int x, int y, enum mode_set_atomic state)
2754 {
2755         struct drm_device *dev = crtc->dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757
2758         if (dev_priv->display.disable_fbc)
2759                 dev_priv->display.disable_fbc(dev);
2760
2761         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763         return 0;
2764 }
2765
2766 void intel_display_handle_reset(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct drm_crtc *crtc;
2770
2771         /*
2772          * Flips in the rings have been nuked by the reset,
2773          * so complete all pending flips so that user space
2774          * will get its events and not get stuck.
2775          *
2776          * Also update the base address of all primary
2777          * planes to the the last fb to make sure we're
2778          * showing the correct fb after a reset.
2779          *
2780          * Need to make two loops over the crtcs so that we
2781          * don't try to grab a crtc mutex before the
2782          * pending_flip_queue really got woken up.
2783          */
2784
2785         for_each_crtc(dev, crtc) {
2786                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787                 enum plane plane = intel_crtc->plane;
2788
2789                 intel_prepare_page_flip(dev, plane);
2790                 intel_finish_page_flip_plane(dev, plane);
2791         }
2792
2793         for_each_crtc(dev, crtc) {
2794                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
2796                 drm_modeset_lock(&crtc->mutex, NULL);
2797                 /*
2798                  * FIXME: Once we have proper support for primary planes (and
2799                  * disabling them without disabling the entire crtc) allow again
2800                  * a NULL crtc->primary->fb.
2801                  */
2802                 if (intel_crtc->active && crtc->primary->fb)
2803                         dev_priv->display.update_primary_plane(crtc,
2804                                                                crtc->primary->fb,
2805                                                                crtc->x,
2806                                                                crtc->y);
2807                 drm_modeset_unlock(&crtc->mutex);
2808         }
2809 }
2810
2811 static int
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2813 {
2814         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816         bool was_interruptible = dev_priv->mm.interruptible;
2817         int ret;
2818
2819         /* Big Hammer, we also need to ensure that any pending
2820          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821          * current scanout is retired before unpinning the old
2822          * framebuffer.
2823          *
2824          * This should only fail upon a hung GPU, in which case we
2825          * can safely continue.
2826          */
2827         dev_priv->mm.interruptible = false;
2828         ret = i915_gem_object_finish_gpu(obj);
2829         dev_priv->mm.interruptible = was_interruptible;
2830
2831         return ret;
2832 }
2833
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irq(&dev->event_lock);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irq(&dev->event_lock);
2848
2849         return pending;
2850 }
2851
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->base.dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         const struct drm_display_mode *adjusted_mode;
2857
2858         if (!i915.fastboot)
2859                 return;
2860
2861         /*
2862          * Update pipe size and adjust fitter if needed: the reason for this is
2863          * that in compute_mode_changes we check the native mode (not the pfit
2864          * mode) to see if we can flip rather than do a full mode set. In the
2865          * fastboot case, we'll flip, but if we don't update the pipesrc and
2866          * pfit state, we'll end up with a big fb scanned out into the wrong
2867          * sized surface.
2868          *
2869          * To fix this properly, we need to hoist the checks up into
2870          * compute_mode_changes (or above), check the actual pfit state and
2871          * whether the platform allows pfit disable with pipe active, and only
2872          * then update the pipesrc and pfit state, even on the flip path.
2873          */
2874
2875         adjusted_mode = &crtc->config.adjusted_mode;
2876
2877         I915_WRITE(PIPESRC(crtc->pipe),
2878                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879                    (adjusted_mode->crtc_vdisplay - 1));
2880         if (!crtc->config.pch_pfit.enabled &&
2881             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886         }
2887         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889 }
2890
2891 static int
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893                     struct drm_framebuffer *fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         enum pipe pipe = intel_crtc->pipe;
2899         struct drm_framebuffer *old_fb = crtc->primary->fb;
2900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2902         int ret;
2903
2904         if (intel_crtc_has_pending_flip(crtc)) {
2905                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906                 return -EBUSY;
2907         }
2908
2909         /* no fb bound */
2910         if (!fb) {
2911                 DRM_ERROR("No FB bound\n");
2912                 return 0;
2913         }
2914
2915         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917                           plane_name(intel_crtc->plane),
2918                           INTEL_INFO(dev)->num_pipes);
2919                 return -EINVAL;
2920         }
2921
2922         mutex_lock(&dev->struct_mutex);
2923         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924         if (ret == 0)
2925                 i915_gem_track_fb(old_obj, obj,
2926                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2927         mutex_unlock(&dev->struct_mutex);
2928         if (ret != 0) {
2929                 DRM_ERROR("pin & fence failed\n");
2930                 return ret;
2931         }
2932
2933         intel_update_pipe_size(intel_crtc);
2934
2935         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2936
2937         if (intel_crtc->active)
2938                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
2940         crtc->primary->fb = fb;
2941         crtc->x = x;
2942         crtc->y = y;
2943
2944         if (old_fb) {
2945                 if (intel_crtc->active && old_fb != fb)
2946                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2947                 mutex_lock(&dev->struct_mutex);
2948                 intel_unpin_fb_obj(old_obj);
2949                 mutex_unlock(&dev->struct_mutex);
2950         }
2951
2952         mutex_lock(&dev->struct_mutex);
2953         intel_update_fbc(dev);
2954         mutex_unlock(&dev->struct_mutex);
2955
2956         return 0;
2957 }
2958
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         int pipe = intel_crtc->pipe;
2965         u32 reg, temp;
2966
2967         /* enable normal train */
2968         reg = FDI_TX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (IS_IVYBRIDGE(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2976         }
2977         I915_WRITE(reg, temp);
2978
2979         reg = FDI_RX_CTL(pipe);
2980         temp = I915_READ(reg);
2981         if (HAS_PCH_CPT(dev)) {
2982                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984         } else {
2985                 temp &= ~FDI_LINK_TRAIN_NONE;
2986                 temp |= FDI_LINK_TRAIN_NONE;
2987         }
2988         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990         /* wait one idle pattern time */
2991         POSTING_READ(reg);
2992         udelay(1000);
2993
2994         /* IVB wants error correction enabled */
2995         if (IS_IVYBRIDGE(dev))
2996                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997                            FDI_FE_ERRC_ENABLE);
2998 }
2999
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3001 {
3002         return crtc->base.enabled && crtc->active &&
3003                 crtc->config.has_pch_encoder;
3004 }
3005
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *pipe_B_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011         struct intel_crtc *pipe_C_crtc =
3012                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013         uint32_t temp;
3014
3015         /*
3016          * When everything is off disable fdi C so that we could enable fdi B
3017          * with all lanes. Note that we don't care about enabled pipes without
3018          * an enabled pch encoder.
3019          */
3020         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021             !pipe_has_enabled_pch(pipe_C_crtc)) {
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025                 temp = I915_READ(SOUTH_CHICKEN1);
3026                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028                 I915_WRITE(SOUTH_CHICKEN1, temp);
3029         }
3030 }
3031
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp, tries;
3040
3041         /* FDI needs bits from pipe first */
3042         assert_pipe_enabled(dev_priv, pipe);
3043
3044         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045            for train result */
3046         reg = FDI_RX_IMR(pipe);
3047         temp = I915_READ(reg);
3048         temp &= ~FDI_RX_SYMBOL_LOCK;
3049         temp &= ~FDI_RX_BIT_LOCK;
3050         I915_WRITE(reg, temp);
3051         I915_READ(reg);
3052         udelay(150);
3053
3054         /* enable CPU FDI TX and PCH FDI RX */
3055         reg = FDI_TX_CTL(pipe);
3056         temp = I915_READ(reg);
3057         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059         temp &= ~FDI_LINK_TRAIN_NONE;
3060         temp |= FDI_LINK_TRAIN_PATTERN_1;
3061         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3062
3063         reg = FDI_RX_CTL(pipe);
3064         temp = I915_READ(reg);
3065         temp &= ~FDI_LINK_TRAIN_NONE;
3066         temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069         POSTING_READ(reg);
3070         udelay(150);
3071
3072         /* Ironlake workaround, enable clock pointer after FDI enable*/
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075                    FDI_RX_PHASE_SYNC_POINTER_EN);
3076
3077         reg = FDI_RX_IIR(pipe);
3078         for (tries = 0; tries < 5; tries++) {
3079                 temp = I915_READ(reg);
3080                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                 if ((temp & FDI_RX_BIT_LOCK)) {
3083                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3084                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                         break;
3086                 }
3087         }
3088         if (tries == 5)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         I915_WRITE(reg, temp);
3097
3098         reg = FDI_RX_CTL(pipe);
3099         temp = I915_READ(reg);
3100         temp &= ~FDI_LINK_TRAIN_NONE;
3101         temp |= FDI_LINK_TRAIN_PATTERN_2;
3102         I915_WRITE(reg, temp);
3103
3104         POSTING_READ(reg);
3105         udelay(150);
3106
3107         reg = FDI_RX_IIR(pipe);
3108         for (tries = 0; tries < 5; tries++) {
3109                 temp = I915_READ(reg);
3110                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112                 if (temp & FDI_RX_SYMBOL_LOCK) {
3113                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3115                         break;
3116                 }
3117         }
3118         if (tries == 5)
3119                 DRM_ERROR("FDI train 2 fail!\n");
3120
3121         DRM_DEBUG_KMS("FDI train done\n");
3122
3123 }
3124
3125 static const int snb_b_fdi_train_param[] = {
3126         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130 };
3131
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134 {
3135         struct drm_device *dev = crtc->dev;
3136         struct drm_i915_private *dev_priv = dev->dev_private;
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp, i, retry;
3140
3141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142            for train result */
3143         reg = FDI_RX_IMR(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_RX_SYMBOL_LOCK;
3146         temp &= ~FDI_RX_BIT_LOCK;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         /* enable CPU FDI TX and PCH FDI RX */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_1;
3159         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160         /* SNB-B */
3161         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3163
3164         I915_WRITE(FDI_RX_MISC(pipe),
3165                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
3167         reg = FDI_RX_CTL(pipe);
3168         temp = I915_READ(reg);
3169         if (HAS_PCH_CPT(dev)) {
3170                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172         } else {
3173                 temp &= ~FDI_LINK_TRAIN_NONE;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175         }
3176         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178         POSTING_READ(reg);
3179         udelay(150);
3180
3181         for (i = 0; i < 4; i++) {
3182                 reg = FDI_TX_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185                 temp |= snb_b_fdi_train_param[i];
3186                 I915_WRITE(reg, temp);
3187
3188                 POSTING_READ(reg);
3189                 udelay(500);
3190
3191                 for (retry = 0; retry < 5; retry++) {
3192                         reg = FDI_RX_IIR(pipe);
3193                         temp = I915_READ(reg);
3194                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195                         if (temp & FDI_RX_BIT_LOCK) {
3196                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198                                 break;
3199                         }
3200                         udelay(50);
3201                 }
3202                 if (retry < 5)
3203                         break;
3204         }
3205         if (i == 4)
3206                 DRM_ERROR("FDI train 1 fail!\n");
3207
3208         /* Train 2 */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_LINK_TRAIN_NONE;
3212         temp |= FDI_LINK_TRAIN_PATTERN_2;
3213         if (IS_GEN6(dev)) {
3214                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215                 /* SNB-B */
3216                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217         }
3218         I915_WRITE(reg, temp);
3219
3220         reg = FDI_RX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (HAS_PCH_CPT(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         POSTING_READ(reg);
3232         udelay(150);
3233
3234         for (i = 0; i < 4; i++) {
3235                 reg = FDI_TX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238                 temp |= snb_b_fdi_train_param[i];
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(500);
3243
3244                 for (retry = 0; retry < 5; retry++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248                         if (temp & FDI_RX_SYMBOL_LOCK) {
3249                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251                                 break;
3252                         }
3253                         udelay(50);
3254                 }
3255                 if (retry < 5)
3256                         break;
3257         }
3258         if (i == 4)
3259                 DRM_ERROR("FDI train 2 fail!\n");
3260
3261         DRM_DEBUG_KMS("FDI train done.\n");
3262 }
3263
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp, i, j;
3272
3273         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274            for train result */
3275         reg = FDI_RX_IMR(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_RX_SYMBOL_LOCK;
3278         temp &= ~FDI_RX_BIT_LOCK;
3279         I915_WRITE(reg, temp);
3280
3281         POSTING_READ(reg);
3282         udelay(150);
3283
3284         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285                       I915_READ(FDI_RX_IIR(pipe)));
3286
3287         /* Try each vswing and preemphasis setting twice before moving on */
3288         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289                 /* disable first in case we need to retry */
3290                 reg = FDI_TX_CTL(pipe);
3291                 temp = I915_READ(reg);
3292                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293                 temp &= ~FDI_TX_ENABLE;
3294                 I915_WRITE(reg, temp);
3295
3296                 reg = FDI_RX_CTL(pipe);
3297                 temp = I915_READ(reg);
3298                 temp &= ~FDI_LINK_TRAIN_AUTO;
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp &= ~FDI_RX_ENABLE;
3301                 I915_WRITE(reg, temp);
3302
3303                 /* enable CPU FDI TX and PCH FDI RX */
3304                 reg = FDI_TX_CTL(pipe);
3305                 temp = I915_READ(reg);
3306                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310                 temp |= snb_b_fdi_train_param[j/2];
3311                 temp |= FDI_COMPOSITE_SYNC;
3312                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314                 I915_WRITE(FDI_RX_MISC(pipe),
3315                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317                 reg = FDI_RX_CTL(pipe);
3318                 temp = I915_READ(reg);
3319                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320                 temp |= FDI_COMPOSITE_SYNC;
3321                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323                 POSTING_READ(reg);
3324                 udelay(1); /* should be 0.5us */
3325
3326                 for (i = 0; i < 4; i++) {
3327                         reg = FDI_RX_IIR(pipe);
3328                         temp = I915_READ(reg);
3329                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331                         if (temp & FDI_RX_BIT_LOCK ||
3332                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335                                               i);
3336                                 break;
3337                         }
3338                         udelay(1); /* should be 0.5us */
3339                 }
3340                 if (i == 4) {
3341                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342                         continue;
3343                 }
3344
3345                 /* Train 2 */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356                 I915_WRITE(reg, temp);
3357
3358                 POSTING_READ(reg);
3359                 udelay(2); /* should be 1.5us */
3360
3361                 for (i = 0; i < 4; i++) {
3362                         reg = FDI_RX_IIR(pipe);
3363                         temp = I915_READ(reg);
3364                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3365
3366                         if (temp & FDI_RX_SYMBOL_LOCK ||
3367                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370                                               i);
3371                                 goto train_done;
3372                         }
3373                         udelay(2); /* should be 1.5us */
3374                 }
3375                 if (i == 4)
3376                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3377         }
3378
3379 train_done:
3380         DRM_DEBUG_KMS("FDI train done.\n");
3381 }
3382
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3384 {
3385         struct drm_device *dev = intel_crtc->base.dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         int pipe = intel_crtc->pipe;
3388         u32 reg, temp;
3389
3390
3391         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392         reg = FDI_RX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399         POSTING_READ(reg);
3400         udelay(200);
3401
3402         /* Switch from Rawclk to PCDclk */
3403         temp = I915_READ(reg);
3404         I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406         POSTING_READ(reg);
3407         udelay(200);
3408
3409         /* Enable CPU FDI TX PLL, always on for Ironlake */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3414
3415                 POSTING_READ(reg);
3416                 udelay(100);
3417         }
3418 }
3419
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp;
3426
3427         /* Switch from PCDclk to Rawclk */
3428         reg = FDI_RX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432         /* Disable CPU FDI TX PLL */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444         /* Wait for the clocks to turn off. */
3445         POSTING_READ(reg);
3446         udelay(100);
3447 }
3448
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         /* disable CPU FDI tx and PCH FDI rx */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461         POSTING_READ(reg);
3462
3463         reg = FDI_RX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~(0x7 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471
3472         /* Ironlake workaround, disable clock pointer after downing FDI */
3473         if (HAS_PCH_IBX(dev))
3474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3475
3476         /* still set train pattern 1 */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_LINK_TRAIN_NONE;
3480         temp |= FDI_LINK_TRAIN_PATTERN_1;
3481         I915_WRITE(reg, temp);
3482
3483         reg = FDI_RX_CTL(pipe);
3484         temp = I915_READ(reg);
3485         if (HAS_PCH_CPT(dev)) {
3486                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488         } else {
3489                 temp &= ~FDI_LINK_TRAIN_NONE;
3490                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491         }
3492         /* BPC in FDI rx is consistent with that in PIPECONF */
3493         temp &= ~(0x07 << 16);
3494         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495         I915_WRITE(reg, temp);
3496
3497         POSTING_READ(reg);
3498         udelay(100);
3499 }
3500
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502 {
3503         struct intel_crtc *crtc;
3504
3505         /* Note that we don't need to be called with mode_config.lock here
3506          * as our list of CRTC objects is static for the lifetime of the
3507          * device and so cannot disappear as we iterate. Similarly, we can
3508          * happily treat the predicates as racy, atomic checks as userspace
3509          * cannot claim and pin a new fb without at least acquring the
3510          * struct_mutex and so serialising with us.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (atomic_read(&crtc->unpin_work_count) == 0)
3514                         continue;
3515
3516                 if (crtc->unpin_work)
3517                         intel_wait_for_vblank(dev, crtc->pipe);
3518
3519                 return true;
3520         }
3521
3522         return false;
3523 }
3524
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3526 {
3527         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528         struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530         /* ensure that the unpin work is consistent wrt ->pending. */
3531         smp_rmb();
3532         intel_crtc->unpin_work = NULL;
3533
3534         if (work->event)
3535                 drm_send_vblank_event(intel_crtc->base.dev,
3536                                       intel_crtc->pipe,
3537                                       work->event);
3538
3539         drm_crtc_vblank_put(&intel_crtc->base);
3540
3541         wake_up_all(&dev_priv->pending_flip_queue);
3542         queue_work(dev_priv->wq, &work->work);
3543
3544         trace_i915_flip_complete(intel_crtc->plane,
3545                                  work->pending_flip_obj);
3546 }
3547
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555                                        !intel_crtc_has_pending_flip(crtc),
3556                                        60*HZ) == 0)) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558
3559                 spin_lock_irq(&dev->event_lock);
3560                 if (intel_crtc->unpin_work) {
3561                         WARN_ONCE(1, "Removing stuck page flip\n");
3562                         page_flip_completed(intel_crtc);
3563                 }
3564                 spin_unlock_irq(&dev->event_lock);
3565         }
3566
3567         if (crtc->primary->fb) {
3568                 mutex_lock(&dev->struct_mutex);
3569                 intel_finish_fb(crtc->primary->fb);
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572 }
3573
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581         u32 temp;
3582
3583         mutex_lock(&dev_priv->dpio_lock);
3584
3585         /* It is necessary to ungate the pixclk gate prior to programming
3586          * the divisors, and gate it back when it is done.
3587          */
3588         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590         /* Disable SSCCTL */
3591         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593                                 SBI_SSCCTL_DISABLE,
3594                         SBI_ICLK);
3595
3596         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597         if (clock == 20000) {
3598                 auxdiv = 1;
3599                 divsel = 0x41;
3600                 phaseinc = 0x20;
3601         } else {
3602                 /* The iCLK virtual clock root frequency is in MHz,
3603                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3604                  * divisors, it is necessary to divide one by another, so we
3605                  * convert the virtual clock precision to KHz here for higher
3606                  * precision.
3607                  */
3608                 u32 iclk_virtual_root_freq = 172800 * 1000;
3609                 u32 iclk_pi_range = 64;
3610                 u32 desired_divisor, msb_divisor_value, pi_value;
3611
3612                 desired_divisor = (iclk_virtual_root_freq / clock);
3613                 msb_divisor_value = desired_divisor / iclk_pi_range;
3614                 pi_value = desired_divisor % iclk_pi_range;
3615
3616                 auxdiv = 0;
3617                 divsel = msb_divisor_value - 2;
3618                 phaseinc = pi_value;
3619         }
3620
3621         /* This should not happen with any sane values */
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3628                         clock,
3629                         auxdiv,
3630                         divsel,
3631                         phasedir,
3632                         phaseinc);
3633
3634         /* Program SSCDIVINTPHASE6 */
3635         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3643
3644         /* Program SSCAUXDIV */
3645         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3649
3650         /* Enable modulator and associated divider */
3651         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652         temp &= ~SBI_SSCCTL_DISABLE;
3653         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3654
3655         /* Wait for initialization time */
3656         udelay(24);
3657
3658         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3659
3660         mutex_unlock(&dev_priv->dpio_lock);
3661 }
3662
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664                                                 enum pipe pch_transcoder)
3665 {
3666         struct drm_device *dev = crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671                    I915_READ(HTOTAL(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673                    I915_READ(HBLANK(cpu_transcoder)));
3674         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675                    I915_READ(HSYNC(cpu_transcoder)));
3676
3677         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678                    I915_READ(VTOTAL(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680                    I915_READ(VBLANK(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682                    I915_READ(VSYNC(cpu_transcoder)));
3683         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685 }
3686
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         uint32_t temp;
3691
3692         temp = I915_READ(SOUTH_CHICKEN1);
3693         if (temp & FDI_BC_BIFURCATION_SELECT)
3694                 return;
3695
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699         temp |= FDI_BC_BIFURCATION_SELECT;
3700         DRM_DEBUG_KMS("enabling fdi C rx\n");
3701         I915_WRITE(SOUTH_CHICKEN1, temp);
3702         POSTING_READ(SOUTH_CHICKEN1);
3703 }
3704
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706 {
3707         struct drm_device *dev = intel_crtc->base.dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         switch (intel_crtc->pipe) {
3711         case PIPE_A:
3712                 break;
3713         case PIPE_B:
3714                 if (intel_crtc->config.fdi_lanes > 2)
3715                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716                 else
3717                         cpt_enable_fdi_bc_bifurcation(dev);
3718
3719                 break;
3720         case PIPE_C:
3721                 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723                 break;
3724         default:
3725                 BUG();
3726         }
3727 }
3728
3729 /*
3730  * Enable PCH resources required for PCH ports:
3731  *   - PCH PLLs
3732  *   - FDI training & RX/TX
3733  *   - update transcoder timings
3734  *   - DP transcoding bits
3735  *   - transcoder
3736  */
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745         assert_pch_transcoder_disabled(dev_priv, pipe);
3746
3747         if (IS_IVYBRIDGE(dev))
3748                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
3750         /* Write the TU size bits before fdi link training, so that error
3751          * detection works. */
3752         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
3755         /* For PCH output, training FDI link */
3756         dev_priv->display.fdi_link_train(crtc);
3757
3758         /* We need to program the right clock selection before writing the pixel
3759          * mutliplier into the DPLL. */
3760         if (HAS_PCH_CPT(dev)) {
3761                 u32 sel;
3762
3763                 temp = I915_READ(PCH_DPLL_SEL);
3764                 temp |= TRANS_DPLL_ENABLE(pipe);
3765                 sel = TRANS_DPLLB_SEL(pipe);
3766                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3767                         temp |= sel;
3768                 else
3769                         temp &= ~sel;
3770                 I915_WRITE(PCH_DPLL_SEL, temp);
3771         }
3772
3773         /* XXX: pch pll's can be enabled any time before we enable the PCH
3774          * transcoder, and we actually should do this to not upset any PCH
3775          * transcoder that already use the clock when we share it.
3776          *
3777          * Note that enable_shared_dpll tries to do the right thing, but
3778          * get_shared_dpll unconditionally resets the pll - we need that to have
3779          * the right LVDS enable sequence. */
3780         intel_enable_shared_dpll(intel_crtc);
3781
3782         /* set transcoder timing, panel must allow it */
3783         assert_panel_unlocked(dev_priv, pipe);
3784         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3785
3786         intel_fdi_normal_train(crtc);
3787
3788         /* For PCH DP, enable TRANS_DP_CTL */
3789         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791                 reg = TRANS_DP_CTL(pipe);
3792                 temp = I915_READ(reg);
3793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794                           TRANS_DP_SYNC_MASK |
3795                           TRANS_DP_BPC_MASK);
3796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797                          TRANS_DP_ENH_FRAMING);
3798                 temp |= bpc << 9; /* same format but at 11:9 */
3799
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3804
3805                 switch (intel_trans_dp_port_sel(crtc)) {
3806                 case PCH_DP_B:
3807                         temp |= TRANS_DP_PORT_SEL_B;
3808                         break;
3809                 case PCH_DP_C:
3810                         temp |= TRANS_DP_PORT_SEL_C;
3811                         break;
3812                 case PCH_DP_D:
3813                         temp |= TRANS_DP_PORT_SEL_D;
3814                         break;
3815                 default:
3816                         BUG();
3817                 }
3818
3819                 I915_WRITE(reg, temp);
3820         }
3821
3822         ironlake_enable_pch_transcoder(dev_priv, pipe);
3823 }
3824
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3833
3834         lpt_program_iclkip(crtc);
3835
3836         /* Set transcoder timing. */
3837         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3838
3839         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3840 }
3841
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3843 {
3844         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3845
3846         if (pll == NULL)
3847                 return;
3848
3849         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3850                 WARN(1, "bad %s crtc mask\n", pll->name);
3851                 return;
3852         }
3853
3854         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3855         if (pll->config.crtc_mask == 0) {
3856                 WARN_ON(pll->on);
3857                 WARN_ON(pll->active);
3858         }
3859
3860         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3861 }
3862
3863 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3864 {
3865         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3866         struct intel_shared_dpll *pll;
3867         enum intel_dpll_id i;
3868
3869         if (HAS_PCH_IBX(dev_priv->dev)) {
3870                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3871                 i = (enum intel_dpll_id) crtc->pipe;
3872                 pll = &dev_priv->shared_dplls[i];
3873
3874                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3875                               crtc->base.base.id, pll->name);
3876
3877                 WARN_ON(pll->new_config->crtc_mask);
3878
3879                 goto found;
3880         }
3881
3882         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3883                 pll = &dev_priv->shared_dplls[i];
3884
3885                 /* Only want to check enabled timings first */
3886                 if (pll->new_config->crtc_mask == 0)
3887                         continue;
3888
3889                 if (memcmp(&crtc->new_config->dpll_hw_state,
3890                            &pll->new_config->hw_state,
3891                            sizeof(pll->new_config->hw_state)) == 0) {
3892                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3893                                       crtc->base.base.id, pll->name,
3894                                       pll->new_config->crtc_mask,
3895                                       pll->active);
3896                         goto found;
3897                 }
3898         }
3899
3900         /* Ok no matching timings, maybe there's a free one? */
3901         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3902                 pll = &dev_priv->shared_dplls[i];
3903                 if (pll->new_config->crtc_mask == 0) {
3904                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3905                                       crtc->base.base.id, pll->name);
3906                         goto found;
3907                 }
3908         }
3909
3910         return NULL;
3911
3912 found:
3913         if (pll->new_config->crtc_mask == 0)
3914                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3915
3916         crtc->new_config->shared_dpll = i;
3917         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3918                          pipe_name(crtc->pipe));
3919
3920         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3921
3922         return pll;
3923 }
3924
3925 /**
3926  * intel_shared_dpll_start_config - start a new PLL staged config
3927  * @dev_priv: DRM device
3928  * @clear_pipes: mask of pipes that will have their PLLs freed
3929  *
3930  * Starts a new PLL staged config, copying the current config but
3931  * releasing the references of pipes specified in clear_pipes.
3932  */
3933 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3934                                           unsigned clear_pipes)
3935 {
3936         struct intel_shared_dpll *pll;
3937         enum intel_dpll_id i;
3938
3939         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940                 pll = &dev_priv->shared_dplls[i];
3941
3942                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3943                                           GFP_KERNEL);
3944                 if (!pll->new_config)
3945                         goto cleanup;
3946
3947                 pll->new_config->crtc_mask &= ~clear_pipes;
3948         }
3949
3950         return 0;
3951
3952 cleanup:
3953         while (--i >= 0) {
3954                 pll = &dev_priv->shared_dplls[i];
3955                 pll->new_config = NULL;
3956         }
3957
3958         return -ENOMEM;
3959 }
3960
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962 {
3963         struct intel_shared_dpll *pll;
3964         enum intel_dpll_id i;
3965
3966         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967                 pll = &dev_priv->shared_dplls[i];
3968
3969                 WARN_ON(pll->new_config == &pll->config);
3970
3971                 pll->config = *pll->new_config;
3972                 kfree(pll->new_config);
3973                 pll->new_config = NULL;
3974         }
3975 }
3976
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978 {
3979         struct intel_shared_dpll *pll;
3980         enum intel_dpll_id i;
3981
3982         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983                 pll = &dev_priv->shared_dplls[i];
3984
3985                 WARN_ON(pll->new_config == &pll->config);
3986
3987                 kfree(pll->new_config);
3988                 pll->new_config = NULL;
3989         }
3990 }
3991
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3993 {
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         int dslreg = PIPEDSL(pipe);
3996         u32 temp;
3997
3998         temp = I915_READ(dslreg);
3999         udelay(500);
4000         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001                 if (wait_for(I915_READ(dslreg) != temp, 5))
4002                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4003         }
4004 }
4005
4006 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4007 {
4008         struct drm_device *dev = crtc->base.dev;
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         int pipe = crtc->pipe;
4011
4012         if (crtc->config.pch_pfit.enabled) {
4013                 /* Force use of hard-coded filter coefficients
4014                  * as some pre-programmed values are broken,
4015                  * e.g. x201.
4016                  */
4017                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4018                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4019                                                  PF_PIPE_SEL_IVB(pipe));
4020                 else
4021                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4022                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4023                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4024         }
4025 }
4026
4027 static void intel_enable_planes(struct drm_crtc *crtc)
4028 {
4029         struct drm_device *dev = crtc->dev;
4030         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4031         struct drm_plane *plane;
4032         struct intel_plane *intel_plane;
4033
4034         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4035                 intel_plane = to_intel_plane(plane);
4036                 if (intel_plane->pipe == pipe)
4037                         intel_plane_restore(&intel_plane->base);
4038         }
4039 }
4040
4041 static void intel_disable_planes(struct drm_crtc *crtc)
4042 {
4043         struct drm_device *dev = crtc->dev;
4044         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4045         struct drm_plane *plane;
4046         struct intel_plane *intel_plane;
4047
4048         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4049                 intel_plane = to_intel_plane(plane);
4050                 if (intel_plane->pipe == pipe)
4051                         intel_plane_disable(&intel_plane->base);
4052         }
4053 }
4054
4055 void hsw_enable_ips(struct intel_crtc *crtc)
4056 {
4057         struct drm_device *dev = crtc->base.dev;
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059
4060         if (!crtc->config.ips_enabled)
4061                 return;
4062
4063         /* We can only enable IPS after we enable a plane and wait for a vblank */
4064         intel_wait_for_vblank(dev, crtc->pipe);
4065
4066         assert_plane_enabled(dev_priv, crtc->plane);
4067         if (IS_BROADWELL(dev)) {
4068                 mutex_lock(&dev_priv->rps.hw_lock);
4069                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4070                 mutex_unlock(&dev_priv->rps.hw_lock);
4071                 /* Quoting Art Runyan: "its not safe to expect any particular
4072                  * value in IPS_CTL bit 31 after enabling IPS through the
4073                  * mailbox." Moreover, the mailbox may return a bogus state,
4074                  * so we need to just enable it and continue on.
4075                  */
4076         } else {
4077                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4078                 /* The bit only becomes 1 in the next vblank, so this wait here
4079                  * is essentially intel_wait_for_vblank. If we don't have this
4080                  * and don't wait for vblanks until the end of crtc_enable, then
4081                  * the HW state readout code will complain that the expected
4082                  * IPS_CTL value is not the one we read. */
4083                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4084                         DRM_ERROR("Timed out waiting for IPS enable\n");
4085         }
4086 }
4087
4088 void hsw_disable_ips(struct intel_crtc *crtc)
4089 {
4090         struct drm_device *dev = crtc->base.dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092
4093         if (!crtc->config.ips_enabled)
4094                 return;
4095
4096         assert_plane_enabled(dev_priv, crtc->plane);
4097         if (IS_BROADWELL(dev)) {
4098                 mutex_lock(&dev_priv->rps.hw_lock);
4099                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4100                 mutex_unlock(&dev_priv->rps.hw_lock);
4101                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4102                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4103                         DRM_ERROR("Timed out waiting for IPS disable\n");
4104         } else {
4105                 I915_WRITE(IPS_CTL, 0);
4106                 POSTING_READ(IPS_CTL);
4107         }
4108
4109         /* We need to wait for a vblank before we can disable the plane. */
4110         intel_wait_for_vblank(dev, crtc->pipe);
4111 }
4112
4113 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4114 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         enum pipe pipe = intel_crtc->pipe;
4120         int palreg = PALETTE(pipe);
4121         int i;
4122         bool reenable_ips = false;
4123
4124         /* The clocks have to be on to load the palette. */
4125         if (!crtc->enabled || !intel_crtc->active)
4126                 return;
4127
4128         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4129                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4130                         assert_dsi_pll_enabled(dev_priv);
4131                 else
4132                         assert_pll_enabled(dev_priv, pipe);
4133         }
4134
4135         /* use legacy palette for Ironlake */
4136         if (!HAS_GMCH_DISPLAY(dev))
4137                 palreg = LGC_PALETTE(pipe);
4138
4139         /* Workaround : Do not read or write the pipe palette/gamma data while
4140          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4141          */
4142         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4143             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4144              GAMMA_MODE_MODE_SPLIT)) {
4145                 hsw_disable_ips(intel_crtc);
4146                 reenable_ips = true;
4147         }
4148
4149         for (i = 0; i < 256; i++) {
4150                 I915_WRITE(palreg + 4 * i,
4151                            (intel_crtc->lut_r[i] << 16) |
4152                            (intel_crtc->lut_g[i] << 8) |
4153                            intel_crtc->lut_b[i]);
4154         }
4155
4156         if (reenable_ips)
4157                 hsw_enable_ips(intel_crtc);
4158 }
4159
4160 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4161 {
4162         if (!enable && intel_crtc->overlay) {
4163                 struct drm_device *dev = intel_crtc->base.dev;
4164                 struct drm_i915_private *dev_priv = dev->dev_private;
4165
4166                 mutex_lock(&dev->struct_mutex);
4167                 dev_priv->mm.interruptible = false;
4168                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4169                 dev_priv->mm.interruptible = true;
4170                 mutex_unlock(&dev->struct_mutex);
4171         }
4172
4173         /* Let userspace switch the overlay on again. In most cases userspace
4174          * has to recompute where to put it anyway.
4175          */
4176 }
4177
4178 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182         int pipe = intel_crtc->pipe;
4183
4184         intel_enable_primary_hw_plane(crtc->primary, crtc);
4185         intel_enable_planes(crtc);
4186         intel_crtc_update_cursor(crtc, true);
4187         intel_crtc_dpms_overlay(intel_crtc, true);
4188
4189         hsw_enable_ips(intel_crtc);
4190
4191         mutex_lock(&dev->struct_mutex);
4192         intel_update_fbc(dev);
4193         mutex_unlock(&dev->struct_mutex);
4194
4195         /*
4196          * FIXME: Once we grow proper nuclear flip support out of this we need
4197          * to compute the mask of flip planes precisely. For the time being
4198          * consider this a flip from a NULL plane.
4199          */
4200         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4201 }
4202
4203 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208         int pipe = intel_crtc->pipe;
4209         int plane = intel_crtc->plane;
4210
4211         intel_crtc_wait_for_pending_flips(crtc);
4212
4213         if (dev_priv->fbc.plane == plane)
4214                 intel_disable_fbc(dev);
4215
4216         hsw_disable_ips(intel_crtc);
4217
4218         intel_crtc_dpms_overlay(intel_crtc, false);
4219         intel_crtc_update_cursor(crtc, false);
4220         intel_disable_planes(crtc);
4221         intel_disable_primary_hw_plane(crtc->primary, crtc);
4222
4223         /*
4224          * FIXME: Once we grow proper nuclear flip support out of this we need
4225          * to compute the mask of flip planes precisely. For the time being
4226          * consider this a flip to a NULL plane.
4227          */
4228         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4229 }
4230
4231 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236         struct intel_encoder *encoder;
4237         int pipe = intel_crtc->pipe;
4238
4239         WARN_ON(!crtc->enabled);
4240
4241         if (intel_crtc->active)
4242                 return;
4243
4244         if (intel_crtc->config.has_pch_encoder)
4245                 intel_prepare_shared_dpll(intel_crtc);
4246
4247         if (intel_crtc->config.has_dp_encoder)
4248                 intel_dp_set_m_n(intel_crtc);
4249
4250         intel_set_pipe_timings(intel_crtc);
4251
4252         if (intel_crtc->config.has_pch_encoder) {
4253                 intel_cpu_transcoder_set_m_n(intel_crtc,
4254                                      &intel_crtc->config.fdi_m_n, NULL);
4255         }
4256
4257         ironlake_set_pipeconf(crtc);
4258
4259         intel_crtc->active = true;
4260
4261         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4262         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4263
4264         for_each_encoder_on_crtc(dev, crtc, encoder)
4265                 if (encoder->pre_enable)
4266                         encoder->pre_enable(encoder);
4267
4268         if (intel_crtc->config.has_pch_encoder) {
4269                 /* Note: FDI PLL enabling _must_ be done before we enable the
4270                  * cpu pipes, hence this is separate from all the other fdi/pch
4271                  * enabling. */
4272                 ironlake_fdi_pll_enable(intel_crtc);
4273         } else {
4274                 assert_fdi_tx_disabled(dev_priv, pipe);
4275                 assert_fdi_rx_disabled(dev_priv, pipe);
4276         }
4277
4278         ironlake_pfit_enable(intel_crtc);
4279
4280         /*
4281          * On ILK+ LUT must be loaded before the pipe is running but with
4282          * clocks enabled
4283          */
4284         intel_crtc_load_lut(crtc);
4285
4286         intel_update_watermarks(crtc);
4287         intel_enable_pipe(intel_crtc);
4288
4289         if (intel_crtc->config.has_pch_encoder)
4290                 ironlake_pch_enable(crtc);
4291
4292         for_each_encoder_on_crtc(dev, crtc, encoder)
4293                 encoder->enable(encoder);
4294
4295         if (HAS_PCH_CPT(dev))
4296                 cpt_verify_modeset(dev, intel_crtc->pipe);
4297
4298         assert_vblank_disabled(crtc);
4299         drm_crtc_vblank_on(crtc);
4300
4301         intel_crtc_enable_planes(crtc);
4302 }
4303
4304 /* IPS only exists on ULT machines and is tied to pipe A. */
4305 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4306 {
4307         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4308 }
4309
4310 /*
4311  * This implements the workaround described in the "notes" section of the mode
4312  * set sequence documentation. When going from no pipes or single pipe to
4313  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4314  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4315  */
4316 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4317 {
4318         struct drm_device *dev = crtc->base.dev;
4319         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4320
4321         /* We want to get the other_active_crtc only if there's only 1 other
4322          * active crtc. */
4323         for_each_intel_crtc(dev, crtc_it) {
4324                 if (!crtc_it->active || crtc_it == crtc)
4325                         continue;
4326
4327                 if (other_active_crtc)
4328                         return;
4329
4330                 other_active_crtc = crtc_it;
4331         }
4332         if (!other_active_crtc)
4333                 return;
4334
4335         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4336         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337 }
4338
4339 static void haswell_crtc_enable(struct drm_crtc *crtc)
4340 {
4341         struct drm_device *dev = crtc->dev;
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344         struct intel_encoder *encoder;
4345         int pipe = intel_crtc->pipe;
4346
4347         WARN_ON(!crtc->enabled);
4348
4349         if (intel_crtc->active)
4350                 return;
4351
4352         if (intel_crtc_to_shared_dpll(intel_crtc))
4353                 intel_enable_shared_dpll(intel_crtc);
4354
4355         if (intel_crtc->config.has_dp_encoder)
4356                 intel_dp_set_m_n(intel_crtc);
4357
4358         intel_set_pipe_timings(intel_crtc);
4359
4360         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4361                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4362                            intel_crtc->config.pixel_multiplier - 1);
4363         }
4364
4365         if (intel_crtc->config.has_pch_encoder) {
4366                 intel_cpu_transcoder_set_m_n(intel_crtc,
4367                                      &intel_crtc->config.fdi_m_n, NULL);
4368         }
4369
4370         haswell_set_pipeconf(crtc);
4371
4372         intel_set_pipe_csc(crtc);
4373
4374         intel_crtc->active = true;
4375
4376         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4377         for_each_encoder_on_crtc(dev, crtc, encoder)
4378                 if (encoder->pre_enable)
4379                         encoder->pre_enable(encoder);
4380
4381         if (intel_crtc->config.has_pch_encoder) {
4382                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4383                                                       true);
4384                 dev_priv->display.fdi_link_train(crtc);
4385         }
4386
4387         intel_ddi_enable_pipe_clock(intel_crtc);
4388
4389         ironlake_pfit_enable(intel_crtc);
4390
4391         /*
4392          * On ILK+ LUT must be loaded before the pipe is running but with
4393          * clocks enabled
4394          */
4395         intel_crtc_load_lut(crtc);
4396
4397         intel_ddi_set_pipe_settings(crtc);
4398         intel_ddi_enable_transcoder_func(crtc);
4399
4400         intel_update_watermarks(crtc);
4401         intel_enable_pipe(intel_crtc);
4402
4403         if (intel_crtc->config.has_pch_encoder)
4404                 lpt_pch_enable(crtc);
4405
4406         if (intel_crtc->config.dp_encoder_is_mst)
4407                 intel_ddi_set_vc_payload_alloc(crtc, true);
4408
4409         for_each_encoder_on_crtc(dev, crtc, encoder) {
4410                 encoder->enable(encoder);
4411                 intel_opregion_notify_encoder(encoder, true);
4412         }
4413
4414         assert_vblank_disabled(crtc);
4415         drm_crtc_vblank_on(crtc);
4416
4417         /* If we change the relative order between pipe/planes enabling, we need
4418          * to change the workaround. */
4419         haswell_mode_set_planes_workaround(intel_crtc);
4420         intel_crtc_enable_planes(crtc);
4421 }
4422
4423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4424 {
4425         struct drm_device *dev = crtc->base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         int pipe = crtc->pipe;
4428
4429         /* To avoid upsetting the power well on haswell only disable the pfit if
4430          * it's in use. The hw state code will make sure we get this right. */
4431         if (crtc->config.pch_pfit.enabled) {
4432                 I915_WRITE(PF_CTL(pipe), 0);
4433                 I915_WRITE(PF_WIN_POS(pipe), 0);
4434                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4435         }
4436 }
4437
4438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4439 {
4440         struct drm_device *dev = crtc->dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443         struct intel_encoder *encoder;
4444         int pipe = intel_crtc->pipe;
4445         u32 reg, temp;
4446
4447         if (!intel_crtc->active)
4448                 return;
4449
4450         intel_crtc_disable_planes(crtc);
4451
4452         drm_crtc_vblank_off(crtc);
4453         assert_vblank_disabled(crtc);
4454
4455         for_each_encoder_on_crtc(dev, crtc, encoder)
4456                 encoder->disable(encoder);
4457
4458         if (intel_crtc->config.has_pch_encoder)
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4460
4461         intel_disable_pipe(intel_crtc);
4462
4463         ironlake_pfit_disable(intel_crtc);
4464
4465         for_each_encoder_on_crtc(dev, crtc, encoder)
4466                 if (encoder->post_disable)
4467                         encoder->post_disable(encoder);
4468
4469         if (intel_crtc->config.has_pch_encoder) {
4470                 ironlake_fdi_disable(crtc);
4471
4472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4473                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4474
4475                 if (HAS_PCH_CPT(dev)) {
4476                         /* disable TRANS_DP_CTL */
4477                         reg = TRANS_DP_CTL(pipe);
4478                         temp = I915_READ(reg);
4479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4480                                   TRANS_DP_PORT_SEL_MASK);
4481                         temp |= TRANS_DP_PORT_SEL_NONE;
4482                         I915_WRITE(reg, temp);
4483
4484                         /* disable DPLL_SEL */
4485                         temp = I915_READ(PCH_DPLL_SEL);
4486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4487                         I915_WRITE(PCH_DPLL_SEL, temp);
4488                 }
4489
4490                 /* disable PCH DPLL */
4491                 intel_disable_shared_dpll(intel_crtc);
4492
4493                 ironlake_fdi_pll_disable(intel_crtc);
4494         }
4495
4496         intel_crtc->active = false;
4497         intel_update_watermarks(crtc);
4498
4499         mutex_lock(&dev->struct_mutex);
4500         intel_update_fbc(dev);
4501         mutex_unlock(&dev->struct_mutex);
4502 }
4503
4504 static void haswell_crtc_disable(struct drm_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509         struct intel_encoder *encoder;
4510         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4511
4512         if (!intel_crtc->active)
4513                 return;
4514
4515         intel_crtc_disable_planes(crtc);
4516
4517         drm_crtc_vblank_off(crtc);
4518         assert_vblank_disabled(crtc);
4519
4520         for_each_encoder_on_crtc(dev, crtc, encoder) {
4521                 intel_opregion_notify_encoder(encoder, false);
4522                 encoder->disable(encoder);
4523         }
4524
4525         if (intel_crtc->config.has_pch_encoder)
4526                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4527                                                       false);
4528         intel_disable_pipe(intel_crtc);
4529
4530         if (intel_crtc->config.dp_encoder_is_mst)
4531                 intel_ddi_set_vc_payload_alloc(crtc, false);
4532
4533         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4534
4535         ironlake_pfit_disable(intel_crtc);
4536
4537         intel_ddi_disable_pipe_clock(intel_crtc);
4538
4539         if (intel_crtc->config.has_pch_encoder) {
4540                 lpt_disable_pch_transcoder(dev_priv);
4541                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4542                                                       true);
4543                 intel_ddi_fdi_disable(crtc);
4544         }
4545
4546         for_each_encoder_on_crtc(dev, crtc, encoder)
4547                 if (encoder->post_disable)
4548                         encoder->post_disable(encoder);
4549
4550         intel_crtc->active = false;
4551         intel_update_watermarks(crtc);
4552
4553         mutex_lock(&dev->struct_mutex);
4554         intel_update_fbc(dev);
4555         mutex_unlock(&dev->struct_mutex);
4556
4557         if (intel_crtc_to_shared_dpll(intel_crtc))
4558                 intel_disable_shared_dpll(intel_crtc);
4559 }
4560
4561 static void ironlake_crtc_off(struct drm_crtc *crtc)
4562 {
4563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4564         intel_put_shared_dpll(intel_crtc);
4565 }
4566
4567
4568 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572         struct intel_crtc_config *pipe_config = &crtc->config;
4573
4574         if (!crtc->config.gmch_pfit.control)
4575                 return;
4576
4577         /*
4578          * The panel fitter should only be adjusted whilst the pipe is disabled,
4579          * according to register description and PRM.
4580          */
4581         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4582         assert_pipe_disabled(dev_priv, crtc->pipe);
4583
4584         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4585         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4586
4587         /* Border color in case we don't scale up to the full screen. Black by
4588          * default, change to something else for debugging. */
4589         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4590 }
4591
4592 static enum intel_display_power_domain port_to_power_domain(enum port port)
4593 {
4594         switch (port) {
4595         case PORT_A:
4596                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4597         case PORT_B:
4598                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4599         case PORT_C:
4600                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4601         case PORT_D:
4602                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4603         default:
4604                 WARN_ON_ONCE(1);
4605                 return POWER_DOMAIN_PORT_OTHER;
4606         }
4607 }
4608
4609 #define for_each_power_domain(domain, mask)                             \
4610         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4611                 if ((1 << (domain)) & (mask))
4612
4613 enum intel_display_power_domain
4614 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4615 {
4616         struct drm_device *dev = intel_encoder->base.dev;
4617         struct intel_digital_port *intel_dig_port;
4618
4619         switch (intel_encoder->type) {
4620         case INTEL_OUTPUT_UNKNOWN:
4621                 /* Only DDI platforms should ever use this output type */
4622                 WARN_ON_ONCE(!HAS_DDI(dev));
4623         case INTEL_OUTPUT_DISPLAYPORT:
4624         case INTEL_OUTPUT_HDMI:
4625         case INTEL_OUTPUT_EDP:
4626                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4627                 return port_to_power_domain(intel_dig_port->port);
4628         case INTEL_OUTPUT_DP_MST:
4629                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4630                 return port_to_power_domain(intel_dig_port->port);
4631         case INTEL_OUTPUT_ANALOG:
4632                 return POWER_DOMAIN_PORT_CRT;
4633         case INTEL_OUTPUT_DSI:
4634                 return POWER_DOMAIN_PORT_DSI;
4635         default:
4636                 return POWER_DOMAIN_PORT_OTHER;
4637         }
4638 }
4639
4640 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct intel_encoder *intel_encoder;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         enum pipe pipe = intel_crtc->pipe;
4646         unsigned long mask;
4647         enum transcoder transcoder;
4648
4649         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4650
4651         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4652         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4653         if (intel_crtc->config.pch_pfit.enabled ||
4654             intel_crtc->config.pch_pfit.force_thru)
4655                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4656
4657         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4658                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4659
4660         return mask;
4661 }
4662
4663 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4664 {
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4667         struct intel_crtc *crtc;
4668
4669         /*
4670          * First get all needed power domains, then put all unneeded, to avoid
4671          * any unnecessary toggling of the power wells.
4672          */
4673         for_each_intel_crtc(dev, crtc) {
4674                 enum intel_display_power_domain domain;
4675
4676                 if (!crtc->base.enabled)
4677                         continue;
4678
4679                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4680
4681                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4682                         intel_display_power_get(dev_priv, domain);
4683         }
4684
4685         for_each_intel_crtc(dev, crtc) {
4686                 enum intel_display_power_domain domain;
4687
4688                 for_each_power_domain(domain, crtc->enabled_power_domains)
4689                         intel_display_power_put(dev_priv, domain);
4690
4691                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4692         }
4693
4694         intel_display_set_init_power(dev_priv, false);
4695 }
4696
4697 /* returns HPLL frequency in kHz */
4698 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4699 {
4700         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4701
4702         /* Obtain SKU information */
4703         mutex_lock(&dev_priv->dpio_lock);
4704         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4705                 CCK_FUSE_HPLL_FREQ_MASK;
4706         mutex_unlock(&dev_priv->dpio_lock);
4707
4708         return vco_freq[hpll_freq] * 1000;
4709 }
4710
4711 static void vlv_update_cdclk(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714
4715         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4716         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4717                          dev_priv->vlv_cdclk_freq);
4718
4719         /*
4720          * Program the gmbus_freq based on the cdclk frequency.
4721          * BSpec erroneously claims we should aim for 4MHz, but
4722          * in fact 1MHz is the correct frequency.
4723          */
4724         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4725 }
4726
4727 /* Adjust CDclk dividers to allow high res or save power if possible */
4728 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4729 {
4730         struct drm_i915_private *dev_priv = dev->dev_private;
4731         u32 val, cmd;
4732
4733         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4734
4735         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4736                 cmd = 2;
4737         else if (cdclk == 266667)
4738                 cmd = 1;
4739         else
4740                 cmd = 0;
4741
4742         mutex_lock(&dev_priv->rps.hw_lock);
4743         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4744         val &= ~DSPFREQGUAR_MASK;
4745         val |= (cmd << DSPFREQGUAR_SHIFT);
4746         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4747         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4748                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4749                      50)) {
4750                 DRM_ERROR("timed out waiting for CDclk change\n");
4751         }
4752         mutex_unlock(&dev_priv->rps.hw_lock);
4753
4754         if (cdclk == 400000) {
4755                 u32 divider, vco;
4756
4757                 vco = valleyview_get_vco(dev_priv);
4758                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4759
4760                 mutex_lock(&dev_priv->dpio_lock);
4761                 /* adjust cdclk divider */
4762                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4763                 val &= ~DISPLAY_FREQUENCY_VALUES;
4764                 val |= divider;
4765                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4766
4767                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4768                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4769                              50))
4770                         DRM_ERROR("timed out waiting for CDclk change\n");
4771                 mutex_unlock(&dev_priv->dpio_lock);
4772         }
4773
4774         mutex_lock(&dev_priv->dpio_lock);
4775         /* adjust self-refresh exit latency value */
4776         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4777         val &= ~0x7f;
4778
4779         /*
4780          * For high bandwidth configs, we set a higher latency in the bunit
4781          * so that the core display fetch happens in time to avoid underruns.
4782          */
4783         if (cdclk == 400000)
4784                 val |= 4500 / 250; /* 4.5 usec */
4785         else
4786                 val |= 3000 / 250; /* 3.0 usec */
4787         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4788         mutex_unlock(&dev_priv->dpio_lock);
4789
4790         vlv_update_cdclk(dev);
4791 }
4792
4793 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         u32 val, cmd;
4797
4798         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4799
4800         switch (cdclk) {
4801         case 400000:
4802                 cmd = 3;
4803                 break;
4804         case 333333:
4805         case 320000:
4806                 cmd = 2;
4807                 break;
4808         case 266667:
4809                 cmd = 1;
4810                 break;
4811         case 200000:
4812                 cmd = 0;
4813                 break;
4814         default:
4815                 WARN_ON(1);
4816                 return;
4817         }
4818
4819         mutex_lock(&dev_priv->rps.hw_lock);
4820         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4821         val &= ~DSPFREQGUAR_MASK_CHV;
4822         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4823         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4824         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4825                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4826                      50)) {
4827                 DRM_ERROR("timed out waiting for CDclk change\n");
4828         }
4829         mutex_unlock(&dev_priv->rps.hw_lock);
4830
4831         vlv_update_cdclk(dev);
4832 }
4833
4834 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4835                                  int max_pixclk)
4836 {
4837         int vco = valleyview_get_vco(dev_priv);
4838         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4839
4840         /* FIXME: Punit isn't quite ready yet */
4841         if (IS_CHERRYVIEW(dev_priv->dev))
4842                 return 400000;
4843
4844         /*
4845          * Really only a few cases to deal with, as only 4 CDclks are supported:
4846          *   200MHz
4847          *   267MHz
4848          *   320/333MHz (depends on HPLL freq)
4849          *   400MHz
4850          * So we check to see whether we're above 90% of the lower bin and
4851          * adjust if needed.
4852          *
4853          * We seem to get an unstable or solid color picture at 200MHz.
4854          * Not sure what's wrong. For now use 200MHz only when all pipes
4855          * are off.
4856          */
4857         if (max_pixclk > freq_320*9/10)
4858                 return 400000;
4859         else if (max_pixclk > 266667*9/10)
4860                 return freq_320;
4861         else if (max_pixclk > 0)
4862                 return 266667;
4863         else
4864                 return 200000;
4865 }
4866
4867 /* compute the max pixel clock for new configuration */
4868 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4869 {
4870         struct drm_device *dev = dev_priv->dev;
4871         struct intel_crtc *intel_crtc;
4872         int max_pixclk = 0;
4873
4874         for_each_intel_crtc(dev, intel_crtc) {
4875                 if (intel_crtc->new_enabled)
4876                         max_pixclk = max(max_pixclk,
4877                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4878         }
4879
4880         return max_pixclk;
4881 }
4882
4883 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4884                                             unsigned *prepare_pipes)
4885 {
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887         struct intel_crtc *intel_crtc;
4888         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4889
4890         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4891             dev_priv->vlv_cdclk_freq)
4892                 return;
4893
4894         /* disable/enable all currently active pipes while we change cdclk */
4895         for_each_intel_crtc(dev, intel_crtc)
4896                 if (intel_crtc->base.enabled)
4897                         *prepare_pipes |= (1 << intel_crtc->pipe);
4898 }
4899
4900 static void valleyview_modeset_global_resources(struct drm_device *dev)
4901 {
4902         struct drm_i915_private *dev_priv = dev->dev_private;
4903         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4904         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4905
4906         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4907                 if (IS_CHERRYVIEW(dev))
4908                         cherryview_set_cdclk(dev, req_cdclk);
4909                 else
4910                         valleyview_set_cdclk(dev, req_cdclk);
4911         }
4912
4913         modeset_update_crtc_power_domains(dev);
4914 }
4915
4916 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4917 {
4918         struct drm_device *dev = crtc->dev;
4919         struct drm_i915_private *dev_priv = to_i915(dev);
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         struct intel_encoder *encoder;
4922         int pipe = intel_crtc->pipe;
4923         bool is_dsi;
4924
4925         WARN_ON(!crtc->enabled);
4926
4927         if (intel_crtc->active)
4928                 return;
4929
4930         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4931
4932         if (!is_dsi) {
4933                 if (IS_CHERRYVIEW(dev))
4934                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4935                 else
4936                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4937         }
4938
4939         if (intel_crtc->config.has_dp_encoder)
4940                 intel_dp_set_m_n(intel_crtc);
4941
4942         intel_set_pipe_timings(intel_crtc);
4943
4944         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4945                 struct drm_i915_private *dev_priv = dev->dev_private;
4946
4947                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4948                 I915_WRITE(CHV_CANVAS(pipe), 0);
4949         }
4950
4951         i9xx_set_pipeconf(intel_crtc);
4952
4953         intel_crtc->active = true;
4954
4955         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4956
4957         for_each_encoder_on_crtc(dev, crtc, encoder)
4958                 if (encoder->pre_pll_enable)
4959                         encoder->pre_pll_enable(encoder);
4960
4961         if (!is_dsi) {
4962                 if (IS_CHERRYVIEW(dev))
4963                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4964                 else
4965                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4966         }
4967
4968         for_each_encoder_on_crtc(dev, crtc, encoder)
4969                 if (encoder->pre_enable)
4970                         encoder->pre_enable(encoder);
4971
4972         i9xx_pfit_enable(intel_crtc);
4973
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_update_watermarks(crtc);
4977         intel_enable_pipe(intel_crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder)
4980                 encoder->enable(encoder);
4981
4982         assert_vblank_disabled(crtc);
4983         drm_crtc_vblank_on(crtc);
4984
4985         intel_crtc_enable_planes(crtc);
4986
4987         /* Underruns don't raise interrupts, so check manually. */
4988         i9xx_check_fifo_underruns(dev_priv);
4989 }
4990
4991 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4992 {
4993         struct drm_device *dev = crtc->base.dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995
4996         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4997         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4998 }
4999
5000 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5001 {
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_private *dev_priv = to_i915(dev);
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005         struct intel_encoder *encoder;
5006         int pipe = intel_crtc->pipe;
5007
5008         WARN_ON(!crtc->enabled);
5009
5010         if (intel_crtc->active)
5011                 return;
5012
5013         i9xx_set_pll_dividers(intel_crtc);
5014
5015         if (intel_crtc->config.has_dp_encoder)
5016                 intel_dp_set_m_n(intel_crtc);
5017
5018         intel_set_pipe_timings(intel_crtc);
5019
5020         i9xx_set_pipeconf(intel_crtc);
5021
5022         intel_crtc->active = true;
5023
5024         if (!IS_GEN2(dev))
5025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->pre_enable)
5029                         encoder->pre_enable(encoder);
5030
5031         i9xx_enable_pll(intel_crtc);
5032
5033         i9xx_pfit_enable(intel_crtc);
5034
5035         intel_crtc_load_lut(crtc);
5036
5037         intel_update_watermarks(crtc);
5038         intel_enable_pipe(intel_crtc);
5039
5040         for_each_encoder_on_crtc(dev, crtc, encoder)
5041                 encoder->enable(encoder);
5042
5043         assert_vblank_disabled(crtc);
5044         drm_crtc_vblank_on(crtc);
5045
5046         intel_crtc_enable_planes(crtc);
5047
5048         /*
5049          * Gen2 reports pipe underruns whenever all planes are disabled.
5050          * So don't enable underrun reporting before at least some planes
5051          * are enabled.
5052          * FIXME: Need to fix the logic to work when we turn off all planes
5053          * but leave the pipe running.
5054          */
5055         if (IS_GEN2(dev))
5056                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5057
5058         /* Underruns don't raise interrupts, so check manually. */
5059         i9xx_check_fifo_underruns(dev_priv);
5060 }
5061
5062 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5063 {
5064         struct drm_device *dev = crtc->base.dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066
5067         if (!crtc->config.gmch_pfit.control)
5068                 return;
5069
5070         assert_pipe_disabled(dev_priv, crtc->pipe);
5071
5072         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5073                          I915_READ(PFIT_CONTROL));
5074         I915_WRITE(PFIT_CONTROL, 0);
5075 }
5076
5077 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5078 {
5079         struct drm_device *dev = crtc->dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         struct intel_encoder *encoder;
5083         int pipe = intel_crtc->pipe;
5084
5085         if (!intel_crtc->active)
5086                 return;
5087
5088         /*
5089          * Gen2 reports pipe underruns whenever all planes are disabled.
5090          * So diasble underrun reporting before all the planes get disabled.
5091          * FIXME: Need to fix the logic to work when we turn off all planes
5092          * but leave the pipe running.
5093          */
5094         if (IS_GEN2(dev))
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5096
5097         /*
5098          * Vblank time updates from the shadow to live plane control register
5099          * are blocked if the memory self-refresh mode is active at that
5100          * moment. So to make sure the plane gets truly disabled, disable
5101          * first the self-refresh mode. The self-refresh enable bit in turn
5102          * will be checked/applied by the HW only at the next frame start
5103          * event which is after the vblank start event, so we need to have a
5104          * wait-for-vblank between disabling the plane and the pipe.
5105          */
5106         intel_set_memory_cxsr(dev_priv, false);
5107         intel_crtc_disable_planes(crtc);
5108
5109         /*
5110          * On gen2 planes are double buffered but the pipe isn't, so we must
5111          * wait for planes to fully turn off before disabling the pipe.
5112          * We also need to wait on all gmch platforms because of the
5113          * self-refresh mode constraint explained above.
5114          */
5115         intel_wait_for_vblank(dev, pipe);
5116
5117         drm_crtc_vblank_off(crtc);
5118         assert_vblank_disabled(crtc);
5119
5120         for_each_encoder_on_crtc(dev, crtc, encoder)
5121                 encoder->disable(encoder);
5122
5123         intel_disable_pipe(intel_crtc);
5124
5125         i9xx_pfit_disable(intel_crtc);
5126
5127         for_each_encoder_on_crtc(dev, crtc, encoder)
5128                 if (encoder->post_disable)
5129                         encoder->post_disable(encoder);
5130
5131         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5132                 if (IS_CHERRYVIEW(dev))
5133                         chv_disable_pll(dev_priv, pipe);
5134                 else if (IS_VALLEYVIEW(dev))
5135                         vlv_disable_pll(dev_priv, pipe);
5136                 else
5137                         i9xx_disable_pll(intel_crtc);
5138         }
5139
5140         if (!IS_GEN2(dev))
5141                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143         intel_crtc->active = false;
5144         intel_update_watermarks(crtc);
5145
5146         mutex_lock(&dev->struct_mutex);
5147         intel_update_fbc(dev);
5148         mutex_unlock(&dev->struct_mutex);
5149 }
5150
5151 static void i9xx_crtc_off(struct drm_crtc *crtc)
5152 {
5153 }
5154
5155 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5156                                     bool enabled)
5157 {
5158         struct drm_device *dev = crtc->dev;
5159         struct drm_i915_master_private *master_priv;
5160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161         int pipe = intel_crtc->pipe;
5162
5163         if (!dev->primary->master)
5164                 return;
5165
5166         master_priv = dev->primary->master->driver_priv;
5167         if (!master_priv->sarea_priv)
5168                 return;
5169
5170         switch (pipe) {
5171         case 0:
5172                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5173                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5174                 break;
5175         case 1:
5176                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5177                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5178                 break;
5179         default:
5180                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5181                 break;
5182         }
5183 }
5184
5185 /* Master function to enable/disable CRTC and corresponding power wells */
5186 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5187 {
5188         struct drm_device *dev = crtc->dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191         enum intel_display_power_domain domain;
5192         unsigned long domains;
5193
5194         if (enable) {
5195                 if (!intel_crtc->active) {
5196                         domains = get_crtc_power_domains(crtc);
5197                         for_each_power_domain(domain, domains)
5198                                 intel_display_power_get(dev_priv, domain);
5199                         intel_crtc->enabled_power_domains = domains;
5200
5201                         dev_priv->display.crtc_enable(crtc);
5202                 }
5203         } else {
5204                 if (intel_crtc->active) {
5205                         dev_priv->display.crtc_disable(crtc);
5206
5207                         domains = intel_crtc->enabled_power_domains;
5208                         for_each_power_domain(domain, domains)
5209                                 intel_display_power_put(dev_priv, domain);
5210                         intel_crtc->enabled_power_domains = 0;
5211                 }
5212         }
5213 }
5214
5215 /**
5216  * Sets the power management mode of the pipe and plane.
5217  */
5218 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5219 {
5220         struct drm_device *dev = crtc->dev;
5221         struct intel_encoder *intel_encoder;
5222         bool enable = false;
5223
5224         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225                 enable |= intel_encoder->connectors_active;
5226
5227         intel_crtc_control(crtc, enable);
5228
5229         intel_crtc_update_sarea(crtc, enable);
5230 }
5231
5232 static void intel_crtc_disable(struct drm_crtc *crtc)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_connector *connector;
5236         struct drm_i915_private *dev_priv = dev->dev_private;
5237         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5238         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5239
5240         /* crtc should still be enabled when we disable it. */
5241         WARN_ON(!crtc->enabled);
5242
5243         dev_priv->display.crtc_disable(crtc);
5244         intel_crtc_update_sarea(crtc, false);
5245         dev_priv->display.off(crtc);
5246
5247         if (crtc->primary->fb) {
5248                 mutex_lock(&dev->struct_mutex);
5249                 intel_unpin_fb_obj(old_obj);
5250                 i915_gem_track_fb(old_obj, NULL,
5251                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5252                 mutex_unlock(&dev->struct_mutex);
5253                 crtc->primary->fb = NULL;
5254         }
5255
5256         /* Update computed state. */
5257         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258                 if (!connector->encoder || !connector->encoder->crtc)
5259                         continue;
5260
5261                 if (connector->encoder->crtc != crtc)
5262                         continue;
5263
5264                 connector->dpms = DRM_MODE_DPMS_OFF;
5265                 to_intel_encoder(connector->encoder)->connectors_active = false;
5266         }
5267 }
5268
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5270 {
5271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273         drm_encoder_cleanup(encoder);
5274         kfree(intel_encoder);
5275 }
5276
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279  * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5281 {
5282         if (mode == DRM_MODE_DPMS_ON) {
5283                 encoder->connectors_active = true;
5284
5285                 intel_crtc_update_dpms(encoder->base.crtc);
5286         } else {
5287                 encoder->connectors_active = false;
5288
5289                 intel_crtc_update_dpms(encoder->base.crtc);
5290         }
5291 }
5292
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294  * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5296 {
5297         if (connector->get_hw_state(connector)) {
5298                 struct intel_encoder *encoder = connector->encoder;
5299                 struct drm_crtc *crtc;
5300                 bool encoder_enabled;
5301                 enum pipe pipe;
5302
5303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304                               connector->base.base.id,
5305                               connector->base.name);
5306
5307                 /* there is no real hw state for MST connectors */
5308                 if (connector->mst_port)
5309                         return;
5310
5311                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312                      "wrong connector dpms state\n");
5313                 WARN(connector->base.encoder != &encoder->base,
5314                      "active connector not linked to encoder\n");
5315
5316                 if (encoder) {
5317                         WARN(!encoder->connectors_active,
5318                              "encoder->connectors_active not set\n");
5319
5320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321                         WARN(!encoder_enabled, "encoder not enabled\n");
5322                         if (WARN_ON(!encoder->base.crtc))
5323                                 return;
5324
5325                         crtc = encoder->base.crtc;
5326
5327                         WARN(!crtc->enabled, "crtc not enabled\n");
5328                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5330                              "encoder active on the wrong pipe\n");
5331                 }
5332         }
5333 }
5334
5335 /* Even simpler default implementation, if there's really no special case to
5336  * consider. */
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5338 {
5339         /* All the simple cases only support two dpms states. */
5340         if (mode != DRM_MODE_DPMS_ON)
5341                 mode = DRM_MODE_DPMS_OFF;
5342
5343         if (mode == connector->dpms)
5344                 return;
5345
5346         connector->dpms = mode;
5347
5348         /* Only need to change hw state when actually enabled */
5349         if (connector->encoder)
5350                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5351
5352         intel_modeset_check_state(connector->dev);
5353 }
5354
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356  * one connector and no cloning and hence the encoder state determines the state
5357  * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5359 {
5360         enum pipe pipe = 0;
5361         struct intel_encoder *encoder = connector->encoder;
5362
5363         return encoder->get_hw_state(encoder, &pipe);
5364 }
5365
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367                                      struct intel_crtc_config *pipe_config)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *pipe_B_crtc =
5371                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374                       pipe_name(pipe), pipe_config->fdi_lanes);
5375         if (pipe_config->fdi_lanes > 4) {
5376                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377                               pipe_name(pipe), pipe_config->fdi_lanes);
5378                 return false;
5379         }
5380
5381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382                 if (pipe_config->fdi_lanes > 2) {
5383                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384                                       pipe_config->fdi_lanes);
5385                         return false;
5386                 } else {
5387                         return true;
5388                 }
5389         }
5390
5391         if (INTEL_INFO(dev)->num_pipes == 2)
5392                 return true;
5393
5394         /* Ivybridge 3 pipe is really complicated */
5395         switch (pipe) {
5396         case PIPE_A:
5397                 return true;
5398         case PIPE_B:
5399                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400                     pipe_config->fdi_lanes > 2) {
5401                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402                                       pipe_name(pipe), pipe_config->fdi_lanes);
5403                         return false;
5404                 }
5405                 return true;
5406         case PIPE_C:
5407                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408                     pipe_B_crtc->config.fdi_lanes <= 2) {
5409                         if (pipe_config->fdi_lanes > 2) {
5410                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411                                               pipe_name(pipe), pipe_config->fdi_lanes);
5412                                 return false;
5413                         }
5414                 } else {
5415                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416                         return false;
5417                 }
5418                 return true;
5419         default:
5420                 BUG();
5421         }
5422 }
5423
5424 #define RETRY 1
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426                                        struct intel_crtc_config *pipe_config)
5427 {
5428         struct drm_device *dev = intel_crtc->base.dev;
5429         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430         int lane, link_bw, fdi_dotclock;
5431         bool setup_ok, needs_recompute = false;
5432
5433 retry:
5434         /* FDI is a binary signal running at ~2.7GHz, encoding
5435          * each output octet as 10 bits. The actual frequency
5436          * is stored as a divider into a 100MHz clock, and the
5437          * mode pixel clock is stored in units of 1KHz.
5438          * Hence the bw of each lane in terms of the mode signal
5439          * is:
5440          */
5441         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
5443         fdi_dotclock = adjusted_mode->crtc_clock;
5444
5445         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446                                            pipe_config->pipe_bpp);
5447
5448         pipe_config->fdi_lanes = lane;
5449
5450         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451                                link_bw, &pipe_config->fdi_m_n);
5452
5453         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454                                             intel_crtc->pipe, pipe_config);
5455         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456                 pipe_config->pipe_bpp -= 2*3;
5457                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458                               pipe_config->pipe_bpp);
5459                 needs_recompute = true;
5460                 pipe_config->bw_constrained = true;
5461
5462                 goto retry;
5463         }
5464
5465         if (needs_recompute)
5466                 return RETRY;
5467
5468         return setup_ok ? 0 : -EINVAL;
5469 }
5470
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472                                    struct intel_crtc_config *pipe_config)
5473 {
5474         pipe_config->ips_enabled = i915.enable_ips &&
5475                                    hsw_crtc_supports_ips(crtc) &&
5476                                    pipe_config->pipe_bpp <= 24;
5477 }
5478
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480                                      struct intel_crtc_config *pipe_config)
5481 {
5482         struct drm_device *dev = crtc->base.dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5485
5486         /* FIXME should check pixel clock limits on all platforms */
5487         if (INTEL_INFO(dev)->gen < 4) {
5488                 int clock_limit =
5489                         dev_priv->display.get_display_clock_speed(dev);
5490
5491                 /*
5492                  * Enable pixel doubling when the dot clock
5493                  * is > 90% of the (display) core speed.
5494                  *
5495                  * GDG double wide on either pipe,
5496                  * otherwise pipe A only.
5497                  */
5498                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5500                         clock_limit *= 2;
5501                         pipe_config->double_wide = true;
5502                 }
5503
5504                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5505                         return -EINVAL;
5506         }
5507
5508         /*
5509          * Pipe horizontal size must be even in:
5510          * - DVO ganged mode
5511          * - LVDS dual channel mode
5512          * - Double wide pipe
5513          */
5514         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516                 pipe_config->pipe_src_w &= ~1;
5517
5518         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5520          */
5521         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5523                 return -EINVAL;
5524
5525         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529                  * for lvds. */
5530                 pipe_config->pipe_bpp = 8*3;
5531         }
5532
5533         if (HAS_IPS(dev))
5534                 hsw_compute_ips_config(crtc, pipe_config);
5535
5536         if (pipe_config->has_pch_encoder)
5537                 return ironlake_fdi_compute_config(crtc, pipe_config);
5538
5539         return 0;
5540 }
5541
5542 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         int vco = valleyview_get_vco(dev_priv);
5546         u32 val;
5547         int divider;
5548
5549         /* FIXME: Punit isn't quite ready yet */
5550         if (IS_CHERRYVIEW(dev))
5551                 return 400000;
5552
5553         mutex_lock(&dev_priv->dpio_lock);
5554         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5555         mutex_unlock(&dev_priv->dpio_lock);
5556
5557         divider = val & DISPLAY_FREQUENCY_VALUES;
5558
5559         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5560              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5561              "cdclk change in progress\n");
5562
5563         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5564 }
5565
5566 static int i945_get_display_clock_speed(struct drm_device *dev)
5567 {
5568         return 400000;
5569 }
5570
5571 static int i915_get_display_clock_speed(struct drm_device *dev)
5572 {
5573         return 333000;
5574 }
5575
5576 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5577 {
5578         return 200000;
5579 }
5580
5581 static int pnv_get_display_clock_speed(struct drm_device *dev)
5582 {
5583         u16 gcfgc = 0;
5584
5585         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5586
5587         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5588         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5589                 return 267000;
5590         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5591                 return 333000;
5592         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5593                 return 444000;
5594         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5595                 return 200000;
5596         default:
5597                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5598         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5599                 return 133000;
5600         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5601                 return 167000;
5602         }
5603 }
5604
5605 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5606 {
5607         u16 gcfgc = 0;
5608
5609         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5610
5611         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5612                 return 133000;
5613         else {
5614                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5615                 case GC_DISPLAY_CLOCK_333_MHZ:
5616                         return 333000;
5617                 default:
5618                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5619                         return 190000;
5620                 }
5621         }
5622 }
5623
5624 static int i865_get_display_clock_speed(struct drm_device *dev)
5625 {
5626         return 266000;
5627 }
5628
5629 static int i855_get_display_clock_speed(struct drm_device *dev)
5630 {
5631         u16 hpllcc = 0;
5632         /* Assume that the hardware is in the high speed state.  This
5633          * should be the default.
5634          */
5635         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5636         case GC_CLOCK_133_200:
5637         case GC_CLOCK_100_200:
5638                 return 200000;
5639         case GC_CLOCK_166_250:
5640                 return 250000;
5641         case GC_CLOCK_100_133:
5642                 return 133000;
5643         }
5644
5645         /* Shouldn't happen */
5646         return 0;
5647 }
5648
5649 static int i830_get_display_clock_speed(struct drm_device *dev)
5650 {
5651         return 133000;
5652 }
5653
5654 static void
5655 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5656 {
5657         while (*num > DATA_LINK_M_N_MASK ||
5658                *den > DATA_LINK_M_N_MASK) {
5659                 *num >>= 1;
5660                 *den >>= 1;
5661         }
5662 }
5663
5664 static void compute_m_n(unsigned int m, unsigned int n,
5665                         uint32_t *ret_m, uint32_t *ret_n)
5666 {
5667         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5668         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5669         intel_reduce_m_n_ratio(ret_m, ret_n);
5670 }
5671
5672 void
5673 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5674                        int pixel_clock, int link_clock,
5675                        struct intel_link_m_n *m_n)
5676 {
5677         m_n->tu = 64;
5678
5679         compute_m_n(bits_per_pixel * pixel_clock,
5680                     link_clock * nlanes * 8,
5681                     &m_n->gmch_m, &m_n->gmch_n);
5682
5683         compute_m_n(pixel_clock, link_clock,
5684                     &m_n->link_m, &m_n->link_n);
5685 }
5686
5687 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5688 {
5689         if (i915.panel_use_ssc >= 0)
5690                 return i915.panel_use_ssc != 0;
5691         return dev_priv->vbt.lvds_use_ssc
5692                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5693 }
5694
5695 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5696 {
5697         struct drm_device *dev = crtc->base.dev;
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         int refclk;
5700
5701         if (IS_VALLEYVIEW(dev)) {
5702                 refclk = 100000;
5703         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5704             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5705                 refclk = dev_priv->vbt.lvds_ssc_freq;
5706                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5707         } else if (!IS_GEN2(dev)) {
5708                 refclk = 96000;
5709         } else {
5710                 refclk = 48000;
5711         }
5712
5713         return refclk;
5714 }
5715
5716 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5717 {
5718         return (1 << dpll->n) << 16 | dpll->m2;
5719 }
5720
5721 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5722 {
5723         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5724 }
5725
5726 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5727                                      intel_clock_t *reduced_clock)
5728 {
5729         struct drm_device *dev = crtc->base.dev;
5730         u32 fp, fp2 = 0;
5731
5732         if (IS_PINEVIEW(dev)) {
5733                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5734                 if (reduced_clock)
5735                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5736         } else {
5737                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5738                 if (reduced_clock)
5739                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5740         }
5741
5742         crtc->config.dpll_hw_state.fp0 = fp;
5743
5744         crtc->lowfreq_avail = false;
5745         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5746             reduced_clock && i915.powersave) {
5747                 crtc->config.dpll_hw_state.fp1 = fp2;
5748                 crtc->lowfreq_avail = true;
5749         } else {
5750                 crtc->config.dpll_hw_state.fp1 = fp;
5751         }
5752 }
5753
5754 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5755                 pipe)
5756 {
5757         u32 reg_val;
5758
5759         /*
5760          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5761          * and set it to a reasonable value instead.
5762          */
5763         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5764         reg_val &= 0xffffff00;
5765         reg_val |= 0x00000030;
5766         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5767
5768         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5769         reg_val &= 0x8cffffff;
5770         reg_val = 0x8c000000;
5771         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5772
5773         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5774         reg_val &= 0xffffff00;
5775         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5776
5777         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5778         reg_val &= 0x00ffffff;
5779         reg_val |= 0xb0000000;
5780         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5781 }
5782
5783 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5784                                          struct intel_link_m_n *m_n)
5785 {
5786         struct drm_device *dev = crtc->base.dev;
5787         struct drm_i915_private *dev_priv = dev->dev_private;
5788         int pipe = crtc->pipe;
5789
5790         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5791         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5792         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5793         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5794 }
5795
5796 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5797                                          struct intel_link_m_n *m_n,
5798                                          struct intel_link_m_n *m2_n2)
5799 {
5800         struct drm_device *dev = crtc->base.dev;
5801         struct drm_i915_private *dev_priv = dev->dev_private;
5802         int pipe = crtc->pipe;
5803         enum transcoder transcoder = crtc->config.cpu_transcoder;
5804
5805         if (INTEL_INFO(dev)->gen >= 5) {
5806                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5807                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5808                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5809                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5810                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5811                  * for gen < 8) and if DRRS is supported (to make sure the
5812                  * registers are not unnecessarily accessed).
5813                  */
5814                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5815                         crtc->config.has_drrs) {
5816                         I915_WRITE(PIPE_DATA_M2(transcoder),
5817                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5818                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5819                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5820                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5821                 }
5822         } else {
5823                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5824                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5825                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5826                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5827         }
5828 }
5829
5830 void intel_dp_set_m_n(struct intel_crtc *crtc)
5831 {
5832         if (crtc->config.has_pch_encoder)
5833                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5834         else
5835                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5836                                                    &crtc->config.dp_m2_n2);
5837 }
5838
5839 static void vlv_update_pll(struct intel_crtc *crtc,
5840                            struct intel_crtc_config *pipe_config)
5841 {
5842         u32 dpll, dpll_md;
5843
5844         /*
5845          * Enable DPIO clock input. We should never disable the reference
5846          * clock for pipe B, since VGA hotplug / manual detection depends
5847          * on it.
5848          */
5849         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5850                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5851         /* We should never disable this, set it here for state tracking */
5852         if (crtc->pipe == PIPE_B)
5853                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5854         dpll |= DPLL_VCO_ENABLE;
5855         pipe_config->dpll_hw_state.dpll = dpll;
5856
5857         dpll_md = (pipe_config->pixel_multiplier - 1)
5858                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5859         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5860 }
5861
5862 static void vlv_prepare_pll(struct intel_crtc *crtc,
5863                             const struct intel_crtc_config *pipe_config)
5864 {
5865         struct drm_device *dev = crtc->base.dev;
5866         struct drm_i915_private *dev_priv = dev->dev_private;
5867         int pipe = crtc->pipe;
5868         u32 mdiv;
5869         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5870         u32 coreclk, reg_val;
5871
5872         mutex_lock(&dev_priv->dpio_lock);
5873
5874         bestn = pipe_config->dpll.n;
5875         bestm1 = pipe_config->dpll.m1;
5876         bestm2 = pipe_config->dpll.m2;
5877         bestp1 = pipe_config->dpll.p1;
5878         bestp2 = pipe_config->dpll.p2;
5879
5880         /* See eDP HDMI DPIO driver vbios notes doc */
5881
5882         /* PLL B needs special handling */
5883         if (pipe == PIPE_B)
5884                 vlv_pllb_recal_opamp(dev_priv, pipe);
5885
5886         /* Set up Tx target for periodic Rcomp update */
5887         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5888
5889         /* Disable target IRef on PLL */
5890         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5891         reg_val &= 0x00ffffff;
5892         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5893
5894         /* Disable fast lock */
5895         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5896
5897         /* Set idtafcrecal before PLL is enabled */
5898         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5899         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5900         mdiv |= ((bestn << DPIO_N_SHIFT));
5901         mdiv |= (1 << DPIO_K_SHIFT);
5902
5903         /*
5904          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5905          * but we don't support that).
5906          * Note: don't use the DAC post divider as it seems unstable.
5907          */
5908         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5909         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5910
5911         mdiv |= DPIO_ENABLE_CALIBRATION;
5912         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5913
5914         /* Set HBR and RBR LPF coefficients */
5915         if (pipe_config->port_clock == 162000 ||
5916             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5917             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5918                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5919                                  0x009f0003);
5920         else
5921                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5922                                  0x00d0000f);
5923
5924         if (crtc->config.has_dp_encoder) {
5925                 /* Use SSC source */
5926                 if (pipe == PIPE_A)
5927                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5928                                          0x0df40000);
5929                 else
5930                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5931                                          0x0df70000);
5932         } else { /* HDMI or VGA */
5933                 /* Use bend source */
5934                 if (pipe == PIPE_A)
5935                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5936                                          0x0df70000);
5937                 else
5938                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5939                                          0x0df40000);
5940         }
5941
5942         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5943         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5944         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5945             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5946                 coreclk |= 0x01000000;
5947         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5948
5949         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5950         mutex_unlock(&dev_priv->dpio_lock);
5951 }
5952
5953 static void chv_update_pll(struct intel_crtc *crtc,
5954                            struct intel_crtc_config *pipe_config)
5955 {
5956         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5957                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5958                 DPLL_VCO_ENABLE;
5959         if (crtc->pipe != PIPE_A)
5960                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5961
5962         pipe_config->dpll_hw_state.dpll_md =
5963                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5964 }
5965
5966 static void chv_prepare_pll(struct intel_crtc *crtc,
5967                             const struct intel_crtc_config *pipe_config)
5968 {
5969         struct drm_device *dev = crtc->base.dev;
5970         struct drm_i915_private *dev_priv = dev->dev_private;
5971         int pipe = crtc->pipe;
5972         int dpll_reg = DPLL(crtc->pipe);
5973         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5974         u32 loopfilter, intcoeff;
5975         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5976         int refclk;
5977
5978         bestn = pipe_config->dpll.n;
5979         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5980         bestm1 = pipe_config->dpll.m1;
5981         bestm2 = pipe_config->dpll.m2 >> 22;
5982         bestp1 = pipe_config->dpll.p1;
5983         bestp2 = pipe_config->dpll.p2;
5984
5985         /*
5986          * Enable Refclk and SSC
5987          */
5988         I915_WRITE(dpll_reg,
5989                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5990
5991         mutex_lock(&dev_priv->dpio_lock);
5992
5993         /* p1 and p2 divider */
5994         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5995                         5 << DPIO_CHV_S1_DIV_SHIFT |
5996                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5997                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5998                         1 << DPIO_CHV_K_DIV_SHIFT);
5999
6000         /* Feedback post-divider - m2 */
6001         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6002
6003         /* Feedback refclk divider - n and m1 */
6004         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6005                         DPIO_CHV_M1_DIV_BY_2 |
6006                         1 << DPIO_CHV_N_DIV_SHIFT);
6007
6008         /* M2 fraction division */
6009         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6010
6011         /* M2 fraction division enable */
6012         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6013                        DPIO_CHV_FRAC_DIV_EN |
6014                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6015
6016         /* Loop filter */
6017         refclk = i9xx_get_refclk(crtc, 0);
6018         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6019                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6020         if (refclk == 100000)
6021                 intcoeff = 11;
6022         else if (refclk == 38400)
6023                 intcoeff = 10;
6024         else
6025                 intcoeff = 9;
6026         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6027         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6028
6029         /* AFC Recal */
6030         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6031                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6032                         DPIO_AFC_RECAL);
6033
6034         mutex_unlock(&dev_priv->dpio_lock);
6035 }
6036
6037 /**
6038  * vlv_force_pll_on - forcibly enable just the PLL
6039  * @dev_priv: i915 private structure
6040  * @pipe: pipe PLL to enable
6041  * @dpll: PLL configuration
6042  *
6043  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6044  * in cases where we need the PLL enabled even when @pipe is not going to
6045  * be enabled.
6046  */
6047 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6048                       const struct dpll *dpll)
6049 {
6050         struct intel_crtc *crtc =
6051                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6052         struct intel_crtc_config pipe_config = {
6053                 .pixel_multiplier = 1,
6054                 .dpll = *dpll,
6055         };
6056
6057         if (IS_CHERRYVIEW(dev)) {
6058                 chv_update_pll(crtc, &pipe_config);
6059                 chv_prepare_pll(crtc, &pipe_config);
6060                 chv_enable_pll(crtc, &pipe_config);
6061         } else {
6062                 vlv_update_pll(crtc, &pipe_config);
6063                 vlv_prepare_pll(crtc, &pipe_config);
6064                 vlv_enable_pll(crtc, &pipe_config);
6065         }
6066 }
6067
6068 /**
6069  * vlv_force_pll_off - forcibly disable just the PLL
6070  * @dev_priv: i915 private structure
6071  * @pipe: pipe PLL to disable
6072  *
6073  * Disable the PLL for @pipe. To be used in cases where we need
6074  * the PLL enabled even when @pipe is not going to be enabled.
6075  */
6076 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6077 {
6078         if (IS_CHERRYVIEW(dev))
6079                 chv_disable_pll(to_i915(dev), pipe);
6080         else
6081                 vlv_disable_pll(to_i915(dev), pipe);
6082 }
6083
6084 static void i9xx_update_pll(struct intel_crtc *crtc,
6085                             intel_clock_t *reduced_clock,
6086                             int num_connectors)
6087 {
6088         struct drm_device *dev = crtc->base.dev;
6089         struct drm_i915_private *dev_priv = dev->dev_private;
6090         u32 dpll;
6091         bool is_sdvo;
6092         struct dpll *clock = &crtc->new_config->dpll;
6093
6094         i9xx_update_pll_dividers(crtc, reduced_clock);
6095
6096         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6097                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6098
6099         dpll = DPLL_VGA_MODE_DIS;
6100
6101         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6102                 dpll |= DPLLB_MODE_LVDS;
6103         else
6104                 dpll |= DPLLB_MODE_DAC_SERIAL;
6105
6106         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6107                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6108                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6109         }
6110
6111         if (is_sdvo)
6112                 dpll |= DPLL_SDVO_HIGH_SPEED;
6113
6114         if (crtc->new_config->has_dp_encoder)
6115                 dpll |= DPLL_SDVO_HIGH_SPEED;
6116
6117         /* compute bitmask from p1 value */
6118         if (IS_PINEVIEW(dev))
6119                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6120         else {
6121                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6122                 if (IS_G4X(dev) && reduced_clock)
6123                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6124         }
6125         switch (clock->p2) {
6126         case 5:
6127                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6128                 break;
6129         case 7:
6130                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6131                 break;
6132         case 10:
6133                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6134                 break;
6135         case 14:
6136                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6137                 break;
6138         }
6139         if (INTEL_INFO(dev)->gen >= 4)
6140                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6141
6142         if (crtc->new_config->sdvo_tv_clock)
6143                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6144         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6145                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6146                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6147         else
6148                 dpll |= PLL_REF_INPUT_DREFCLK;
6149
6150         dpll |= DPLL_VCO_ENABLE;
6151         crtc->new_config->dpll_hw_state.dpll = dpll;
6152
6153         if (INTEL_INFO(dev)->gen >= 4) {
6154                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6155                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6156                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6157         }
6158 }
6159
6160 static void i8xx_update_pll(struct intel_crtc *crtc,
6161                             intel_clock_t *reduced_clock,
6162                             int num_connectors)
6163 {
6164         struct drm_device *dev = crtc->base.dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         u32 dpll;
6167         struct dpll *clock = &crtc->new_config->dpll;
6168
6169         i9xx_update_pll_dividers(crtc, reduced_clock);
6170
6171         dpll = DPLL_VGA_MODE_DIS;
6172
6173         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6174                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6175         } else {
6176                 if (clock->p1 == 2)
6177                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6178                 else
6179                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6180                 if (clock->p2 == 4)
6181                         dpll |= PLL_P2_DIVIDE_BY_4;
6182         }
6183
6184         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6185                 dpll |= DPLL_DVO_2X_MODE;
6186
6187         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6188                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6189                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6190         else
6191                 dpll |= PLL_REF_INPUT_DREFCLK;
6192
6193         dpll |= DPLL_VCO_ENABLE;
6194         crtc->new_config->dpll_hw_state.dpll = dpll;
6195 }
6196
6197 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6198 {
6199         struct drm_device *dev = intel_crtc->base.dev;
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201         enum pipe pipe = intel_crtc->pipe;
6202         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6203         struct drm_display_mode *adjusted_mode =
6204                 &intel_crtc->config.adjusted_mode;
6205         uint32_t crtc_vtotal, crtc_vblank_end;
6206         int vsyncshift = 0;
6207
6208         /* We need to be careful not to changed the adjusted mode, for otherwise
6209          * the hw state checker will get angry at the mismatch. */
6210         crtc_vtotal = adjusted_mode->crtc_vtotal;
6211         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6212
6213         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6214                 /* the chip adds 2 halflines automatically */
6215                 crtc_vtotal -= 1;
6216                 crtc_vblank_end -= 1;
6217
6218                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6219                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6220                 else
6221                         vsyncshift = adjusted_mode->crtc_hsync_start -
6222                                 adjusted_mode->crtc_htotal / 2;
6223                 if (vsyncshift < 0)
6224                         vsyncshift += adjusted_mode->crtc_htotal;
6225         }
6226
6227         if (INTEL_INFO(dev)->gen > 3)
6228                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6229
6230         I915_WRITE(HTOTAL(cpu_transcoder),
6231                    (adjusted_mode->crtc_hdisplay - 1) |
6232                    ((adjusted_mode->crtc_htotal - 1) << 16));
6233         I915_WRITE(HBLANK(cpu_transcoder),
6234                    (adjusted_mode->crtc_hblank_start - 1) |
6235                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6236         I915_WRITE(HSYNC(cpu_transcoder),
6237                    (adjusted_mode->crtc_hsync_start - 1) |
6238                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6239
6240         I915_WRITE(VTOTAL(cpu_transcoder),
6241                    (adjusted_mode->crtc_vdisplay - 1) |
6242                    ((crtc_vtotal - 1) << 16));
6243         I915_WRITE(VBLANK(cpu_transcoder),
6244                    (adjusted_mode->crtc_vblank_start - 1) |
6245                    ((crtc_vblank_end - 1) << 16));
6246         I915_WRITE(VSYNC(cpu_transcoder),
6247                    (adjusted_mode->crtc_vsync_start - 1) |
6248                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6249
6250         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6251          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6252          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6253          * bits. */
6254         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6255             (pipe == PIPE_B || pipe == PIPE_C))
6256                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6257
6258         /* pipesrc controls the size that is scaled from, which should
6259          * always be the user's requested size.
6260          */
6261         I915_WRITE(PIPESRC(pipe),
6262                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6263                    (intel_crtc->config.pipe_src_h - 1));
6264 }
6265
6266 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6267                                    struct intel_crtc_config *pipe_config)
6268 {
6269         struct drm_device *dev = crtc->base.dev;
6270         struct drm_i915_private *dev_priv = dev->dev_private;
6271         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6272         uint32_t tmp;
6273
6274         tmp = I915_READ(HTOTAL(cpu_transcoder));
6275         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6276         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6277         tmp = I915_READ(HBLANK(cpu_transcoder));
6278         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6279         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6280         tmp = I915_READ(HSYNC(cpu_transcoder));
6281         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6282         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6283
6284         tmp = I915_READ(VTOTAL(cpu_transcoder));
6285         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6286         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6287         tmp = I915_READ(VBLANK(cpu_transcoder));
6288         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6289         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6290         tmp = I915_READ(VSYNC(cpu_transcoder));
6291         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6292         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6293
6294         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6295                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6296                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6297                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6298         }
6299
6300         tmp = I915_READ(PIPESRC(crtc->pipe));
6301         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6302         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6303
6304         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6305         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6306 }
6307
6308 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6309                                  struct intel_crtc_config *pipe_config)
6310 {
6311         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6312         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6313         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6314         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6315
6316         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6317         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6318         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6319         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6320
6321         mode->flags = pipe_config->adjusted_mode.flags;
6322
6323         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6324         mode->flags |= pipe_config->adjusted_mode.flags;
6325 }
6326
6327 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6328 {
6329         struct drm_device *dev = intel_crtc->base.dev;
6330         struct drm_i915_private *dev_priv = dev->dev_private;
6331         uint32_t pipeconf;
6332
6333         pipeconf = 0;
6334
6335         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6336             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6337                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6338
6339         if (intel_crtc->config.double_wide)
6340                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6341
6342         /* only g4x and later have fancy bpc/dither controls */
6343         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6344                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6345                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6346                         pipeconf |= PIPECONF_DITHER_EN |
6347                                     PIPECONF_DITHER_TYPE_SP;
6348
6349                 switch (intel_crtc->config.pipe_bpp) {
6350                 case 18:
6351                         pipeconf |= PIPECONF_6BPC;
6352                         break;
6353                 case 24:
6354                         pipeconf |= PIPECONF_8BPC;
6355                         break;
6356                 case 30:
6357                         pipeconf |= PIPECONF_10BPC;
6358                         break;
6359                 default:
6360                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6361                         BUG();
6362                 }
6363         }
6364
6365         if (HAS_PIPE_CXSR(dev)) {
6366                 if (intel_crtc->lowfreq_avail) {
6367                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6368                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6369                 } else {
6370                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6371                 }
6372         }
6373
6374         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6375                 if (INTEL_INFO(dev)->gen < 4 ||
6376                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6377                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6378                 else
6379                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6380         } else
6381                 pipeconf |= PIPECONF_PROGRESSIVE;
6382
6383         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6384                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6385
6386         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6387         POSTING_READ(PIPECONF(intel_crtc->pipe));
6388 }
6389
6390 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6391 {
6392         struct drm_device *dev = crtc->base.dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         int refclk, num_connectors = 0;
6395         intel_clock_t clock, reduced_clock;
6396         bool ok, has_reduced_clock = false;
6397         bool is_lvds = false, is_dsi = false;
6398         struct intel_encoder *encoder;
6399         const intel_limit_t *limit;
6400
6401         for_each_intel_encoder(dev, encoder) {
6402                 if (encoder->new_crtc != crtc)
6403                         continue;
6404
6405                 switch (encoder->type) {
6406                 case INTEL_OUTPUT_LVDS:
6407                         is_lvds = true;
6408                         break;
6409                 case INTEL_OUTPUT_DSI:
6410                         is_dsi = true;
6411                         break;
6412                 default:
6413                         break;
6414                 }
6415
6416                 num_connectors++;
6417         }
6418
6419         if (is_dsi)
6420                 return 0;
6421
6422         if (!crtc->new_config->clock_set) {
6423                 refclk = i9xx_get_refclk(crtc, num_connectors);
6424
6425                 /*
6426                  * Returns a set of divisors for the desired target clock with
6427                  * the given refclk, or FALSE.  The returned values represent
6428                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6429                  * 2) / p1 / p2.
6430                  */
6431                 limit = intel_limit(crtc, refclk);
6432                 ok = dev_priv->display.find_dpll(limit, crtc,
6433                                                  crtc->new_config->port_clock,
6434                                                  refclk, NULL, &clock);
6435                 if (!ok) {
6436                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6437                         return -EINVAL;
6438                 }
6439
6440                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6441                         /*
6442                          * Ensure we match the reduced clock's P to the target
6443                          * clock.  If the clocks don't match, we can't switch
6444                          * the display clock by using the FP0/FP1. In such case
6445                          * we will disable the LVDS downclock feature.
6446                          */
6447                         has_reduced_clock =
6448                                 dev_priv->display.find_dpll(limit, crtc,
6449                                                             dev_priv->lvds_downclock,
6450                                                             refclk, &clock,
6451                                                             &reduced_clock);
6452                 }
6453                 /* Compat-code for transition, will disappear. */
6454                 crtc->new_config->dpll.n = clock.n;
6455                 crtc->new_config->dpll.m1 = clock.m1;
6456                 crtc->new_config->dpll.m2 = clock.m2;
6457                 crtc->new_config->dpll.p1 = clock.p1;
6458                 crtc->new_config->dpll.p2 = clock.p2;
6459         }
6460
6461         if (IS_GEN2(dev)) {
6462                 i8xx_update_pll(crtc,
6463                                 has_reduced_clock ? &reduced_clock : NULL,
6464                                 num_connectors);
6465         } else if (IS_CHERRYVIEW(dev)) {
6466                 chv_update_pll(crtc, crtc->new_config);
6467         } else if (IS_VALLEYVIEW(dev)) {
6468                 vlv_update_pll(crtc, crtc->new_config);
6469         } else {
6470                 i9xx_update_pll(crtc,
6471                                 has_reduced_clock ? &reduced_clock : NULL,
6472                                 num_connectors);
6473         }
6474
6475         return 0;
6476 }
6477
6478 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6479                                  struct intel_crtc_config *pipe_config)
6480 {
6481         struct drm_device *dev = crtc->base.dev;
6482         struct drm_i915_private *dev_priv = dev->dev_private;
6483         uint32_t tmp;
6484
6485         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6486                 return;
6487
6488         tmp = I915_READ(PFIT_CONTROL);
6489         if (!(tmp & PFIT_ENABLE))
6490                 return;
6491
6492         /* Check whether the pfit is attached to our pipe. */
6493         if (INTEL_INFO(dev)->gen < 4) {
6494                 if (crtc->pipe != PIPE_B)
6495                         return;
6496         } else {
6497                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6498                         return;
6499         }
6500
6501         pipe_config->gmch_pfit.control = tmp;
6502         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6503         if (INTEL_INFO(dev)->gen < 5)
6504                 pipe_config->gmch_pfit.lvds_border_bits =
6505                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6506 }
6507
6508 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6509                                struct intel_crtc_config *pipe_config)
6510 {
6511         struct drm_device *dev = crtc->base.dev;
6512         struct drm_i915_private *dev_priv = dev->dev_private;
6513         int pipe = pipe_config->cpu_transcoder;
6514         intel_clock_t clock;
6515         u32 mdiv;
6516         int refclk = 100000;
6517
6518         /* In case of MIPI DPLL will not even be used */
6519         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6520                 return;
6521
6522         mutex_lock(&dev_priv->dpio_lock);
6523         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6524         mutex_unlock(&dev_priv->dpio_lock);
6525
6526         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6527         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6528         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6529         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6530         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6531
6532         vlv_clock(refclk, &clock);
6533
6534         /* clock.dot is the fast clock */
6535         pipe_config->port_clock = clock.dot / 5;
6536 }
6537
6538 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6539                                   struct intel_plane_config *plane_config)
6540 {
6541         struct drm_device *dev = crtc->base.dev;
6542         struct drm_i915_private *dev_priv = dev->dev_private;
6543         u32 val, base, offset;
6544         int pipe = crtc->pipe, plane = crtc->plane;
6545         int fourcc, pixel_format;
6546         int aligned_height;
6547
6548         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6549         if (!crtc->base.primary->fb) {
6550                 DRM_DEBUG_KMS("failed to alloc fb\n");
6551                 return;
6552         }
6553
6554         val = I915_READ(DSPCNTR(plane));
6555
6556         if (INTEL_INFO(dev)->gen >= 4)
6557                 if (val & DISPPLANE_TILED)
6558                         plane_config->tiled = true;
6559
6560         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6561         fourcc = intel_format_to_fourcc(pixel_format);
6562         crtc->base.primary->fb->pixel_format = fourcc;
6563         crtc->base.primary->fb->bits_per_pixel =
6564                 drm_format_plane_cpp(fourcc, 0) * 8;
6565
6566         if (INTEL_INFO(dev)->gen >= 4) {
6567                 if (plane_config->tiled)
6568                         offset = I915_READ(DSPTILEOFF(plane));
6569                 else
6570                         offset = I915_READ(DSPLINOFF(plane));
6571                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6572         } else {
6573                 base = I915_READ(DSPADDR(plane));
6574         }
6575         plane_config->base = base;
6576
6577         val = I915_READ(PIPESRC(pipe));
6578         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6579         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6580
6581         val = I915_READ(DSPSTRIDE(pipe));
6582         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6583
6584         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6585                                             plane_config->tiled);
6586
6587         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6588                                         aligned_height);
6589
6590         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6591                       pipe, plane, crtc->base.primary->fb->width,
6592                       crtc->base.primary->fb->height,
6593                       crtc->base.primary->fb->bits_per_pixel, base,
6594                       crtc->base.primary->fb->pitches[0],
6595                       plane_config->size);
6596
6597 }
6598
6599 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6600                                struct intel_crtc_config *pipe_config)
6601 {
6602         struct drm_device *dev = crtc->base.dev;
6603         struct drm_i915_private *dev_priv = dev->dev_private;
6604         int pipe = pipe_config->cpu_transcoder;
6605         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6606         intel_clock_t clock;
6607         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6608         int refclk = 100000;
6609
6610         mutex_lock(&dev_priv->dpio_lock);
6611         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6612         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6613         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6614         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6615         mutex_unlock(&dev_priv->dpio_lock);
6616
6617         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6618         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6619         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6620         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6621         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6622
6623         chv_clock(refclk, &clock);
6624
6625         /* clock.dot is the fast clock */
6626         pipe_config->port_clock = clock.dot / 5;
6627 }
6628
6629 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6630                                  struct intel_crtc_config *pipe_config)
6631 {
6632         struct drm_device *dev = crtc->base.dev;
6633         struct drm_i915_private *dev_priv = dev->dev_private;
6634         uint32_t tmp;
6635
6636         if (!intel_display_power_is_enabled(dev_priv,
6637                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6638                 return false;
6639
6640         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6641         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6642
6643         tmp = I915_READ(PIPECONF(crtc->pipe));
6644         if (!(tmp & PIPECONF_ENABLE))
6645                 return false;
6646
6647         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6648                 switch (tmp & PIPECONF_BPC_MASK) {
6649                 case PIPECONF_6BPC:
6650                         pipe_config->pipe_bpp = 18;
6651                         break;
6652                 case PIPECONF_8BPC:
6653                         pipe_config->pipe_bpp = 24;
6654                         break;
6655                 case PIPECONF_10BPC:
6656                         pipe_config->pipe_bpp = 30;
6657                         break;
6658                 default:
6659                         break;
6660                 }
6661         }
6662
6663         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6664                 pipe_config->limited_color_range = true;
6665
6666         if (INTEL_INFO(dev)->gen < 4)
6667                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6668
6669         intel_get_pipe_timings(crtc, pipe_config);
6670
6671         i9xx_get_pfit_config(crtc, pipe_config);
6672
6673         if (INTEL_INFO(dev)->gen >= 4) {
6674                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6675                 pipe_config->pixel_multiplier =
6676                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6677                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6678                 pipe_config->dpll_hw_state.dpll_md = tmp;
6679         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6680                 tmp = I915_READ(DPLL(crtc->pipe));
6681                 pipe_config->pixel_multiplier =
6682                         ((tmp & SDVO_MULTIPLIER_MASK)
6683                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6684         } else {
6685                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6686                  * port and will be fixed up in the encoder->get_config
6687                  * function. */
6688                 pipe_config->pixel_multiplier = 1;
6689         }
6690         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6691         if (!IS_VALLEYVIEW(dev)) {
6692                 /*
6693                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6694                  * on 830. Filter it out here so that we don't
6695                  * report errors due to that.
6696                  */
6697                 if (IS_I830(dev))
6698                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6699
6700                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6701                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6702         } else {
6703                 /* Mask out read-only status bits. */
6704                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6705                                                      DPLL_PORTC_READY_MASK |
6706                                                      DPLL_PORTB_READY_MASK);
6707         }
6708
6709         if (IS_CHERRYVIEW(dev))
6710                 chv_crtc_clock_get(crtc, pipe_config);
6711         else if (IS_VALLEYVIEW(dev))
6712                 vlv_crtc_clock_get(crtc, pipe_config);
6713         else
6714                 i9xx_crtc_clock_get(crtc, pipe_config);
6715
6716         return true;
6717 }
6718
6719 static void ironlake_init_pch_refclk(struct drm_device *dev)
6720 {
6721         struct drm_i915_private *dev_priv = dev->dev_private;
6722         struct intel_encoder *encoder;
6723         u32 val, final;
6724         bool has_lvds = false;
6725         bool has_cpu_edp = false;
6726         bool has_panel = false;
6727         bool has_ck505 = false;
6728         bool can_ssc = false;
6729
6730         /* We need to take the global config into account */
6731         for_each_intel_encoder(dev, encoder) {
6732                 switch (encoder->type) {
6733                 case INTEL_OUTPUT_LVDS:
6734                         has_panel = true;
6735                         has_lvds = true;
6736                         break;
6737                 case INTEL_OUTPUT_EDP:
6738                         has_panel = true;
6739                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6740                                 has_cpu_edp = true;
6741                         break;
6742                 default:
6743                         break;
6744                 }
6745         }
6746
6747         if (HAS_PCH_IBX(dev)) {
6748                 has_ck505 = dev_priv->vbt.display_clock_mode;
6749                 can_ssc = has_ck505;
6750         } else {
6751                 has_ck505 = false;
6752                 can_ssc = true;
6753         }
6754
6755         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6756                       has_panel, has_lvds, has_ck505);
6757
6758         /* Ironlake: try to setup display ref clock before DPLL
6759          * enabling. This is only under driver's control after
6760          * PCH B stepping, previous chipset stepping should be
6761          * ignoring this setting.
6762          */
6763         val = I915_READ(PCH_DREF_CONTROL);
6764
6765         /* As we must carefully and slowly disable/enable each source in turn,
6766          * compute the final state we want first and check if we need to
6767          * make any changes at all.
6768          */
6769         final = val;
6770         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6771         if (has_ck505)
6772                 final |= DREF_NONSPREAD_CK505_ENABLE;
6773         else
6774                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6775
6776         final &= ~DREF_SSC_SOURCE_MASK;
6777         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6778         final &= ~DREF_SSC1_ENABLE;
6779
6780         if (has_panel) {
6781                 final |= DREF_SSC_SOURCE_ENABLE;
6782
6783                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6784                         final |= DREF_SSC1_ENABLE;
6785
6786                 if (has_cpu_edp) {
6787                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6788                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6789                         else
6790                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6791                 } else
6792                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6793         } else {
6794                 final |= DREF_SSC_SOURCE_DISABLE;
6795                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796         }
6797
6798         if (final == val)
6799                 return;
6800
6801         /* Always enable nonspread source */
6802         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6803
6804         if (has_ck505)
6805                 val |= DREF_NONSPREAD_CK505_ENABLE;
6806         else
6807                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6808
6809         if (has_panel) {
6810                 val &= ~DREF_SSC_SOURCE_MASK;
6811                 val |= DREF_SSC_SOURCE_ENABLE;
6812
6813                 /* SSC must be turned on before enabling the CPU output  */
6814                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6815                         DRM_DEBUG_KMS("Using SSC on panel\n");
6816                         val |= DREF_SSC1_ENABLE;
6817                 } else
6818                         val &= ~DREF_SSC1_ENABLE;
6819
6820                 /* Get SSC going before enabling the outputs */
6821                 I915_WRITE(PCH_DREF_CONTROL, val);
6822                 POSTING_READ(PCH_DREF_CONTROL);
6823                 udelay(200);
6824
6825                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6826
6827                 /* Enable CPU source on CPU attached eDP */
6828                 if (has_cpu_edp) {
6829                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6830                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6831                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6832                         } else
6833                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6834                 } else
6835                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6836
6837                 I915_WRITE(PCH_DREF_CONTROL, val);
6838                 POSTING_READ(PCH_DREF_CONTROL);
6839                 udelay(200);
6840         } else {
6841                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6842
6843                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6844
6845                 /* Turn off CPU output */
6846                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6847
6848                 I915_WRITE(PCH_DREF_CONTROL, val);
6849                 POSTING_READ(PCH_DREF_CONTROL);
6850                 udelay(200);
6851
6852                 /* Turn off the SSC source */
6853                 val &= ~DREF_SSC_SOURCE_MASK;
6854                 val |= DREF_SSC_SOURCE_DISABLE;
6855
6856                 /* Turn off SSC1 */
6857                 val &= ~DREF_SSC1_ENABLE;
6858
6859                 I915_WRITE(PCH_DREF_CONTROL, val);
6860                 POSTING_READ(PCH_DREF_CONTROL);
6861                 udelay(200);
6862         }
6863
6864         BUG_ON(val != final);
6865 }
6866
6867 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6868 {
6869         uint32_t tmp;
6870
6871         tmp = I915_READ(SOUTH_CHICKEN2);
6872         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6873         I915_WRITE(SOUTH_CHICKEN2, tmp);
6874
6875         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6876                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6877                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6878
6879         tmp = I915_READ(SOUTH_CHICKEN2);
6880         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6881         I915_WRITE(SOUTH_CHICKEN2, tmp);
6882
6883         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6884                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6885                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6886 }
6887
6888 /* WaMPhyProgramming:hsw */
6889 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6890 {
6891         uint32_t tmp;
6892
6893         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6894         tmp &= ~(0xFF << 24);
6895         tmp |= (0x12 << 24);
6896         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6897
6898         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6899         tmp |= (1 << 11);
6900         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6901
6902         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6903         tmp |= (1 << 11);
6904         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6905
6906         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6907         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6908         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6909
6910         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6911         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6912         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6913
6914         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6915         tmp &= ~(7 << 13);
6916         tmp |= (5 << 13);
6917         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6918
6919         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6920         tmp &= ~(7 << 13);
6921         tmp |= (5 << 13);
6922         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6923
6924         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6925         tmp &= ~0xFF;
6926         tmp |= 0x1C;
6927         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6928
6929         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6930         tmp &= ~0xFF;
6931         tmp |= 0x1C;
6932         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6933
6934         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6935         tmp &= ~(0xFF << 16);
6936         tmp |= (0x1C << 16);
6937         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6938
6939         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6940         tmp &= ~(0xFF << 16);
6941         tmp |= (0x1C << 16);
6942         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6943
6944         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6945         tmp |= (1 << 27);
6946         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6947
6948         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6949         tmp |= (1 << 27);
6950         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6951
6952         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6953         tmp &= ~(0xF << 28);
6954         tmp |= (4 << 28);
6955         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6956
6957         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6958         tmp &= ~(0xF << 28);
6959         tmp |= (4 << 28);
6960         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6961 }
6962
6963 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6964  * Programming" based on the parameters passed:
6965  * - Sequence to enable CLKOUT_DP
6966  * - Sequence to enable CLKOUT_DP without spread
6967  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6968  */
6969 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6970                                  bool with_fdi)
6971 {
6972         struct drm_i915_private *dev_priv = dev->dev_private;
6973         uint32_t reg, tmp;
6974
6975         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6976                 with_spread = true;
6977         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6978                  with_fdi, "LP PCH doesn't have FDI\n"))
6979                 with_fdi = false;
6980
6981         mutex_lock(&dev_priv->dpio_lock);
6982
6983         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6984         tmp &= ~SBI_SSCCTL_DISABLE;
6985         tmp |= SBI_SSCCTL_PATHALT;
6986         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6987
6988         udelay(24);
6989
6990         if (with_spread) {
6991                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6992                 tmp &= ~SBI_SSCCTL_PATHALT;
6993                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6994
6995                 if (with_fdi) {
6996                         lpt_reset_fdi_mphy(dev_priv);
6997                         lpt_program_fdi_mphy(dev_priv);
6998                 }
6999         }
7000
7001         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7002                SBI_GEN0 : SBI_DBUFF0;
7003         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7004         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7005         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7006
7007         mutex_unlock(&dev_priv->dpio_lock);
7008 }
7009
7010 /* Sequence to disable CLKOUT_DP */
7011 static void lpt_disable_clkout_dp(struct drm_device *dev)
7012 {
7013         struct drm_i915_private *dev_priv = dev->dev_private;
7014         uint32_t reg, tmp;
7015
7016         mutex_lock(&dev_priv->dpio_lock);
7017
7018         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7019                SBI_GEN0 : SBI_DBUFF0;
7020         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7021         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7022         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7023
7024         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7025         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7026                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7027                         tmp |= SBI_SSCCTL_PATHALT;
7028                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7029                         udelay(32);
7030                 }
7031                 tmp |= SBI_SSCCTL_DISABLE;
7032                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7033         }
7034
7035         mutex_unlock(&dev_priv->dpio_lock);
7036 }
7037
7038 static void lpt_init_pch_refclk(struct drm_device *dev)
7039 {
7040         struct intel_encoder *encoder;
7041         bool has_vga = false;
7042
7043         for_each_intel_encoder(dev, encoder) {
7044                 switch (encoder->type) {
7045                 case INTEL_OUTPUT_ANALOG:
7046                         has_vga = true;
7047                         break;
7048                 default:
7049                         break;
7050                 }
7051         }
7052
7053         if (has_vga)
7054                 lpt_enable_clkout_dp(dev, true, true);
7055         else
7056                 lpt_disable_clkout_dp(dev);
7057 }
7058
7059 /*
7060  * Initialize reference clocks when the driver loads
7061  */
7062 void intel_init_pch_refclk(struct drm_device *dev)
7063 {
7064         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7065                 ironlake_init_pch_refclk(dev);
7066         else if (HAS_PCH_LPT(dev))
7067                 lpt_init_pch_refclk(dev);
7068 }
7069
7070 static int ironlake_get_refclk(struct drm_crtc *crtc)
7071 {
7072         struct drm_device *dev = crtc->dev;
7073         struct drm_i915_private *dev_priv = dev->dev_private;
7074         struct intel_encoder *encoder;
7075         int num_connectors = 0;
7076         bool is_lvds = false;
7077
7078         for_each_intel_encoder(dev, encoder) {
7079                 if (encoder->new_crtc != to_intel_crtc(crtc))
7080                         continue;
7081
7082                 switch (encoder->type) {
7083                 case INTEL_OUTPUT_LVDS:
7084                         is_lvds = true;
7085                         break;
7086                 default:
7087                         break;
7088                 }
7089                 num_connectors++;
7090         }
7091
7092         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7093                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7094                               dev_priv->vbt.lvds_ssc_freq);
7095                 return dev_priv->vbt.lvds_ssc_freq;
7096         }
7097
7098         return 120000;
7099 }
7100
7101 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7102 {
7103         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7105         int pipe = intel_crtc->pipe;
7106         uint32_t val;
7107
7108         val = 0;
7109
7110         switch (intel_crtc->config.pipe_bpp) {
7111         case 18:
7112                 val |= PIPECONF_6BPC;
7113                 break;
7114         case 24:
7115                 val |= PIPECONF_8BPC;
7116                 break;
7117         case 30:
7118                 val |= PIPECONF_10BPC;
7119                 break;
7120         case 36:
7121                 val |= PIPECONF_12BPC;
7122                 break;
7123         default:
7124                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7125                 BUG();
7126         }
7127
7128         if (intel_crtc->config.dither)
7129                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7130
7131         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7132                 val |= PIPECONF_INTERLACED_ILK;
7133         else
7134                 val |= PIPECONF_PROGRESSIVE;
7135
7136         if (intel_crtc->config.limited_color_range)
7137                 val |= PIPECONF_COLOR_RANGE_SELECT;
7138
7139         I915_WRITE(PIPECONF(pipe), val);
7140         POSTING_READ(PIPECONF(pipe));
7141 }
7142
7143 /*
7144  * Set up the pipe CSC unit.
7145  *
7146  * Currently only full range RGB to limited range RGB conversion
7147  * is supported, but eventually this should handle various
7148  * RGB<->YCbCr scenarios as well.
7149  */
7150 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7151 {
7152         struct drm_device *dev = crtc->dev;
7153         struct drm_i915_private *dev_priv = dev->dev_private;
7154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7155         int pipe = intel_crtc->pipe;
7156         uint16_t coeff = 0x7800; /* 1.0 */
7157
7158         /*
7159          * TODO: Check what kind of values actually come out of the pipe
7160          * with these coeff/postoff values and adjust to get the best
7161          * accuracy. Perhaps we even need to take the bpc value into
7162          * consideration.
7163          */
7164
7165         if (intel_crtc->config.limited_color_range)
7166                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7167
7168         /*
7169          * GY/GU and RY/RU should be the other way around according
7170          * to BSpec, but reality doesn't agree. Just set them up in
7171          * a way that results in the correct picture.
7172          */
7173         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7174         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7175
7176         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7177         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7178
7179         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7180         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7181
7182         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7183         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7184         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7185
7186         if (INTEL_INFO(dev)->gen > 6) {
7187                 uint16_t postoff = 0;
7188
7189                 if (intel_crtc->config.limited_color_range)
7190                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7191
7192                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7193                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7194                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7195
7196                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7197         } else {
7198                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7199
7200                 if (intel_crtc->config.limited_color_range)
7201                         mode |= CSC_BLACK_SCREEN_OFFSET;
7202
7203                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7204         }
7205 }
7206
7207 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7208 {
7209         struct drm_device *dev = crtc->dev;
7210         struct drm_i915_private *dev_priv = dev->dev_private;
7211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7212         enum pipe pipe = intel_crtc->pipe;
7213         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7214         uint32_t val;
7215
7216         val = 0;
7217
7218         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7219                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7220
7221         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7222                 val |= PIPECONF_INTERLACED_ILK;
7223         else
7224                 val |= PIPECONF_PROGRESSIVE;
7225
7226         I915_WRITE(PIPECONF(cpu_transcoder), val);
7227         POSTING_READ(PIPECONF(cpu_transcoder));
7228
7229         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7230         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7231
7232         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7233                 val = 0;
7234
7235                 switch (intel_crtc->config.pipe_bpp) {
7236                 case 18:
7237                         val |= PIPEMISC_DITHER_6_BPC;
7238                         break;
7239                 case 24:
7240                         val |= PIPEMISC_DITHER_8_BPC;
7241                         break;
7242                 case 30:
7243                         val |= PIPEMISC_DITHER_10_BPC;
7244                         break;
7245                 case 36:
7246                         val |= PIPEMISC_DITHER_12_BPC;
7247                         break;
7248                 default:
7249                         /* Case prevented by pipe_config_set_bpp. */
7250                         BUG();
7251                 }
7252
7253                 if (intel_crtc->config.dither)
7254                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7255
7256                 I915_WRITE(PIPEMISC(pipe), val);
7257         }
7258 }
7259
7260 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7261                                     intel_clock_t *clock,
7262                                     bool *has_reduced_clock,
7263                                     intel_clock_t *reduced_clock)
7264 {
7265         struct drm_device *dev = crtc->dev;
7266         struct drm_i915_private *dev_priv = dev->dev_private;
7267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7268         int refclk;
7269         const intel_limit_t *limit;
7270         bool ret, is_lvds = false;
7271
7272         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7273
7274         refclk = ironlake_get_refclk(crtc);
7275
7276         /*
7277          * Returns a set of divisors for the desired target clock with the given
7278          * refclk, or FALSE.  The returned values represent the clock equation:
7279          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7280          */
7281         limit = intel_limit(intel_crtc, refclk);
7282         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7283                                           intel_crtc->new_config->port_clock,
7284                                           refclk, NULL, clock);
7285         if (!ret)
7286                 return false;
7287
7288         if (is_lvds && dev_priv->lvds_downclock_avail) {
7289                 /*
7290                  * Ensure we match the reduced clock's P to the target clock.
7291                  * If the clocks don't match, we can't switch the display clock
7292                  * by using the FP0/FP1. In such case we will disable the LVDS
7293                  * downclock feature.
7294                 */
7295                 *has_reduced_clock =
7296                         dev_priv->display.find_dpll(limit, intel_crtc,
7297                                                     dev_priv->lvds_downclock,
7298                                                     refclk, clock,
7299                                                     reduced_clock);
7300         }
7301
7302         return true;
7303 }
7304
7305 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7306 {
7307         /*
7308          * Account for spread spectrum to avoid
7309          * oversubscribing the link. Max center spread
7310          * is 2.5%; use 5% for safety's sake.
7311          */
7312         u32 bps = target_clock * bpp * 21 / 20;
7313         return DIV_ROUND_UP(bps, link_bw * 8);
7314 }
7315
7316 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7317 {
7318         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7319 }
7320
7321 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7322                                       u32 *fp,
7323                                       intel_clock_t *reduced_clock, u32 *fp2)
7324 {
7325         struct drm_crtc *crtc = &intel_crtc->base;
7326         struct drm_device *dev = crtc->dev;
7327         struct drm_i915_private *dev_priv = dev->dev_private;
7328         struct intel_encoder *intel_encoder;
7329         uint32_t dpll;
7330         int factor, num_connectors = 0;
7331         bool is_lvds = false, is_sdvo = false;
7332
7333         for_each_intel_encoder(dev, intel_encoder) {
7334                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7335                         continue;
7336
7337                 switch (intel_encoder->type) {
7338                 case INTEL_OUTPUT_LVDS:
7339                         is_lvds = true;
7340                         break;
7341                 case INTEL_OUTPUT_SDVO:
7342                 case INTEL_OUTPUT_HDMI:
7343                         is_sdvo = true;
7344                         break;
7345                 default:
7346                         break;
7347                 }
7348
7349                 num_connectors++;
7350         }
7351
7352         /* Enable autotuning of the PLL clock (if permissible) */
7353         factor = 21;
7354         if (is_lvds) {
7355                 if ((intel_panel_use_ssc(dev_priv) &&
7356                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7357                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7358                         factor = 25;
7359         } else if (intel_crtc->new_config->sdvo_tv_clock)
7360                 factor = 20;
7361
7362         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7363                 *fp |= FP_CB_TUNE;
7364
7365         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7366                 *fp2 |= FP_CB_TUNE;
7367
7368         dpll = 0;
7369
7370         if (is_lvds)
7371                 dpll |= DPLLB_MODE_LVDS;
7372         else
7373                 dpll |= DPLLB_MODE_DAC_SERIAL;
7374
7375         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7376                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7377
7378         if (is_sdvo)
7379                 dpll |= DPLL_SDVO_HIGH_SPEED;
7380         if (intel_crtc->new_config->has_dp_encoder)
7381                 dpll |= DPLL_SDVO_HIGH_SPEED;
7382
7383         /* compute bitmask from p1 value */
7384         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7385         /* also FPA1 */
7386         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7387
7388         switch (intel_crtc->new_config->dpll.p2) {
7389         case 5:
7390                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7391                 break;
7392         case 7:
7393                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7394                 break;
7395         case 10:
7396                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7397                 break;
7398         case 14:
7399                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7400                 break;
7401         }
7402
7403         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7404                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7405         else
7406                 dpll |= PLL_REF_INPUT_DREFCLK;
7407
7408         return dpll | DPLL_VCO_ENABLE;
7409 }
7410
7411 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7412 {
7413         struct drm_device *dev = crtc->base.dev;
7414         intel_clock_t clock, reduced_clock;
7415         u32 dpll = 0, fp = 0, fp2 = 0;
7416         bool ok, has_reduced_clock = false;
7417         bool is_lvds = false;
7418         struct intel_shared_dpll *pll;
7419
7420         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7421
7422         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7423              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7424
7425         ok = ironlake_compute_clocks(&crtc->base, &clock,
7426                                      &has_reduced_clock, &reduced_clock);
7427         if (!ok && !crtc->new_config->clock_set) {
7428                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7429                 return -EINVAL;
7430         }
7431         /* Compat-code for transition, will disappear. */
7432         if (!crtc->new_config->clock_set) {
7433                 crtc->new_config->dpll.n = clock.n;
7434                 crtc->new_config->dpll.m1 = clock.m1;
7435                 crtc->new_config->dpll.m2 = clock.m2;
7436                 crtc->new_config->dpll.p1 = clock.p1;
7437                 crtc->new_config->dpll.p2 = clock.p2;
7438         }
7439
7440         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7441         if (crtc->new_config->has_pch_encoder) {
7442                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7443                 if (has_reduced_clock)
7444                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7445
7446                 dpll = ironlake_compute_dpll(crtc,
7447                                              &fp, &reduced_clock,
7448                                              has_reduced_clock ? &fp2 : NULL);
7449
7450                 crtc->new_config->dpll_hw_state.dpll = dpll;
7451                 crtc->new_config->dpll_hw_state.fp0 = fp;
7452                 if (has_reduced_clock)
7453                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7454                 else
7455                         crtc->new_config->dpll_hw_state.fp1 = fp;
7456
7457                 pll = intel_get_shared_dpll(crtc);
7458                 if (pll == NULL) {
7459                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7460                                          pipe_name(crtc->pipe));
7461                         return -EINVAL;
7462                 }
7463         }
7464
7465         if (is_lvds && has_reduced_clock && i915.powersave)
7466                 crtc->lowfreq_avail = true;
7467         else
7468                 crtc->lowfreq_avail = false;
7469
7470         return 0;
7471 }
7472
7473 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7474                                          struct intel_link_m_n *m_n)
7475 {
7476         struct drm_device *dev = crtc->base.dev;
7477         struct drm_i915_private *dev_priv = dev->dev_private;
7478         enum pipe pipe = crtc->pipe;
7479
7480         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7481         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7482         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7483                 & ~TU_SIZE_MASK;
7484         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7485         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7486                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7487 }
7488
7489 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7490                                          enum transcoder transcoder,
7491                                          struct intel_link_m_n *m_n,
7492                                          struct intel_link_m_n *m2_n2)
7493 {
7494         struct drm_device *dev = crtc->base.dev;
7495         struct drm_i915_private *dev_priv = dev->dev_private;
7496         enum pipe pipe = crtc->pipe;
7497
7498         if (INTEL_INFO(dev)->gen >= 5) {
7499                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7500                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7501                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7502                         & ~TU_SIZE_MASK;
7503                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7504                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7505                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7506                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7507                  * gen < 8) and if DRRS is supported (to make sure the
7508                  * registers are not unnecessarily read).
7509                  */
7510                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7511                         crtc->config.has_drrs) {
7512                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7513                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7514                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7515                                         & ~TU_SIZE_MASK;
7516                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7517                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7518                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7519                 }
7520         } else {
7521                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7522                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7523                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7524                         & ~TU_SIZE_MASK;
7525                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7526                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7527                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7528         }
7529 }
7530
7531 void intel_dp_get_m_n(struct intel_crtc *crtc,
7532                       struct intel_crtc_config *pipe_config)
7533 {
7534         if (crtc->config.has_pch_encoder)
7535                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7536         else
7537                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7538                                              &pipe_config->dp_m_n,
7539                                              &pipe_config->dp_m2_n2);
7540 }
7541
7542 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7543                                         struct intel_crtc_config *pipe_config)
7544 {
7545         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7546                                      &pipe_config->fdi_m_n, NULL);
7547 }
7548
7549 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7550                                      struct intel_crtc_config *pipe_config)
7551 {
7552         struct drm_device *dev = crtc->base.dev;
7553         struct drm_i915_private *dev_priv = dev->dev_private;
7554         uint32_t tmp;
7555
7556         tmp = I915_READ(PF_CTL(crtc->pipe));
7557
7558         if (tmp & PF_ENABLE) {
7559                 pipe_config->pch_pfit.enabled = true;
7560                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7561                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7562
7563                 /* We currently do not free assignements of panel fitters on
7564                  * ivb/hsw (since we don't use the higher upscaling modes which
7565                  * differentiates them) so just WARN about this case for now. */
7566                 if (IS_GEN7(dev)) {
7567                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7568                                 PF_PIPE_SEL_IVB(crtc->pipe));
7569                 }
7570         }
7571 }
7572
7573 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7574                                       struct intel_plane_config *plane_config)
7575 {
7576         struct drm_device *dev = crtc->base.dev;
7577         struct drm_i915_private *dev_priv = dev->dev_private;
7578         u32 val, base, offset;
7579         int pipe = crtc->pipe, plane = crtc->plane;
7580         int fourcc, pixel_format;
7581         int aligned_height;
7582
7583         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7584         if (!crtc->base.primary->fb) {
7585                 DRM_DEBUG_KMS("failed to alloc fb\n");
7586                 return;
7587         }
7588
7589         val = I915_READ(DSPCNTR(plane));
7590
7591         if (INTEL_INFO(dev)->gen >= 4)
7592                 if (val & DISPPLANE_TILED)
7593                         plane_config->tiled = true;
7594
7595         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7596         fourcc = intel_format_to_fourcc(pixel_format);
7597         crtc->base.primary->fb->pixel_format = fourcc;
7598         crtc->base.primary->fb->bits_per_pixel =
7599                 drm_format_plane_cpp(fourcc, 0) * 8;
7600
7601         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7602         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7603                 offset = I915_READ(DSPOFFSET(plane));
7604         } else {
7605                 if (plane_config->tiled)
7606                         offset = I915_READ(DSPTILEOFF(plane));
7607                 else
7608                         offset = I915_READ(DSPLINOFF(plane));
7609         }
7610         plane_config->base = base;
7611
7612         val = I915_READ(PIPESRC(pipe));
7613         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7614         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7615
7616         val = I915_READ(DSPSTRIDE(pipe));
7617         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7618
7619         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7620                                             plane_config->tiled);
7621
7622         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7623                                         aligned_height);
7624
7625         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7626                       pipe, plane, crtc->base.primary->fb->width,
7627                       crtc->base.primary->fb->height,
7628                       crtc->base.primary->fb->bits_per_pixel, base,
7629                       crtc->base.primary->fb->pitches[0],
7630                       plane_config->size);
7631 }
7632
7633 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7634                                      struct intel_crtc_config *pipe_config)
7635 {
7636         struct drm_device *dev = crtc->base.dev;
7637         struct drm_i915_private *dev_priv = dev->dev_private;
7638         uint32_t tmp;
7639
7640         if (!intel_display_power_is_enabled(dev_priv,
7641                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7642                 return false;
7643
7644         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7645         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7646
7647         tmp = I915_READ(PIPECONF(crtc->pipe));
7648         if (!(tmp & PIPECONF_ENABLE))
7649                 return false;
7650
7651         switch (tmp & PIPECONF_BPC_MASK) {
7652         case PIPECONF_6BPC:
7653                 pipe_config->pipe_bpp = 18;
7654                 break;
7655         case PIPECONF_8BPC:
7656                 pipe_config->pipe_bpp = 24;
7657                 break;
7658         case PIPECONF_10BPC:
7659                 pipe_config->pipe_bpp = 30;
7660                 break;
7661         case PIPECONF_12BPC:
7662                 pipe_config->pipe_bpp = 36;
7663                 break;
7664         default:
7665                 break;
7666         }
7667
7668         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7669                 pipe_config->limited_color_range = true;
7670
7671         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7672                 struct intel_shared_dpll *pll;
7673
7674                 pipe_config->has_pch_encoder = true;
7675
7676                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7677                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7678                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7679
7680                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7681
7682                 if (HAS_PCH_IBX(dev_priv->dev)) {
7683                         pipe_config->shared_dpll =
7684                                 (enum intel_dpll_id) crtc->pipe;
7685                 } else {
7686                         tmp = I915_READ(PCH_DPLL_SEL);
7687                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7688                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7689                         else
7690                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7691                 }
7692
7693                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7694
7695                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7696                                            &pipe_config->dpll_hw_state));
7697
7698                 tmp = pipe_config->dpll_hw_state.dpll;
7699                 pipe_config->pixel_multiplier =
7700                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7701                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7702
7703                 ironlake_pch_clock_get(crtc, pipe_config);
7704         } else {
7705                 pipe_config->pixel_multiplier = 1;
7706         }
7707
7708         intel_get_pipe_timings(crtc, pipe_config);
7709
7710         ironlake_get_pfit_config(crtc, pipe_config);
7711
7712         return true;
7713 }
7714
7715 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7716 {
7717         struct drm_device *dev = dev_priv->dev;
7718         struct intel_crtc *crtc;
7719
7720         for_each_intel_crtc(dev, crtc)
7721                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7722                      pipe_name(crtc->pipe));
7723
7724         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7725         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7726         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7727         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7728         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7729         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7730              "CPU PWM1 enabled\n");
7731         if (IS_HASWELL(dev))
7732                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7733                      "CPU PWM2 enabled\n");
7734         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7735              "PCH PWM1 enabled\n");
7736         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7737              "Utility pin enabled\n");
7738         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7739
7740         /*
7741          * In theory we can still leave IRQs enabled, as long as only the HPD
7742          * interrupts remain enabled. We used to check for that, but since it's
7743          * gen-specific and since we only disable LCPLL after we fully disable
7744          * the interrupts, the check below should be enough.
7745          */
7746         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7747 }
7748
7749 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7750 {
7751         struct drm_device *dev = dev_priv->dev;
7752
7753         if (IS_HASWELL(dev))
7754                 return I915_READ(D_COMP_HSW);
7755         else
7756                 return I915_READ(D_COMP_BDW);
7757 }
7758
7759 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7760 {
7761         struct drm_device *dev = dev_priv->dev;
7762
7763         if (IS_HASWELL(dev)) {
7764                 mutex_lock(&dev_priv->rps.hw_lock);
7765                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7766                                             val))
7767                         DRM_ERROR("Failed to write to D_COMP\n");
7768                 mutex_unlock(&dev_priv->rps.hw_lock);
7769         } else {
7770                 I915_WRITE(D_COMP_BDW, val);
7771                 POSTING_READ(D_COMP_BDW);
7772         }
7773 }
7774
7775 /*
7776  * This function implements pieces of two sequences from BSpec:
7777  * - Sequence for display software to disable LCPLL
7778  * - Sequence for display software to allow package C8+
7779  * The steps implemented here are just the steps that actually touch the LCPLL
7780  * register. Callers should take care of disabling all the display engine
7781  * functions, doing the mode unset, fixing interrupts, etc.
7782  */
7783 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7784                               bool switch_to_fclk, bool allow_power_down)
7785 {
7786         uint32_t val;
7787
7788         assert_can_disable_lcpll(dev_priv);
7789
7790         val = I915_READ(LCPLL_CTL);
7791
7792         if (switch_to_fclk) {
7793                 val |= LCPLL_CD_SOURCE_FCLK;
7794                 I915_WRITE(LCPLL_CTL, val);
7795
7796                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7797                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7798                         DRM_ERROR("Switching to FCLK failed\n");
7799
7800                 val = I915_READ(LCPLL_CTL);
7801         }
7802
7803         val |= LCPLL_PLL_DISABLE;
7804         I915_WRITE(LCPLL_CTL, val);
7805         POSTING_READ(LCPLL_CTL);
7806
7807         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7808                 DRM_ERROR("LCPLL still locked\n");
7809
7810         val = hsw_read_dcomp(dev_priv);
7811         val |= D_COMP_COMP_DISABLE;
7812         hsw_write_dcomp(dev_priv, val);
7813         ndelay(100);
7814
7815         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7816                      1))
7817                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7818
7819         if (allow_power_down) {
7820                 val = I915_READ(LCPLL_CTL);
7821                 val |= LCPLL_POWER_DOWN_ALLOW;
7822                 I915_WRITE(LCPLL_CTL, val);
7823                 POSTING_READ(LCPLL_CTL);
7824         }
7825 }
7826
7827 /*
7828  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7829  * source.
7830  */
7831 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7832 {
7833         uint32_t val;
7834
7835         val = I915_READ(LCPLL_CTL);
7836
7837         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7838                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7839                 return;
7840
7841         /*
7842          * Make sure we're not on PC8 state before disabling PC8, otherwise
7843          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7844          *
7845          * The other problem is that hsw_restore_lcpll() is called as part of
7846          * the runtime PM resume sequence, so we can't just call
7847          * gen6_gt_force_wake_get() because that function calls
7848          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7849          * while we are on the resume sequence. So to solve this problem we have
7850          * to call special forcewake code that doesn't touch runtime PM and
7851          * doesn't enable the forcewake delayed work.
7852          */
7853         spin_lock_irq(&dev_priv->uncore.lock);
7854         if (dev_priv->uncore.forcewake_count++ == 0)
7855                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7856         spin_unlock_irq(&dev_priv->uncore.lock);
7857
7858         if (val & LCPLL_POWER_DOWN_ALLOW) {
7859                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7860                 I915_WRITE(LCPLL_CTL, val);
7861                 POSTING_READ(LCPLL_CTL);
7862         }
7863
7864         val = hsw_read_dcomp(dev_priv);
7865         val |= D_COMP_COMP_FORCE;
7866         val &= ~D_COMP_COMP_DISABLE;
7867         hsw_write_dcomp(dev_priv, val);
7868
7869         val = I915_READ(LCPLL_CTL);
7870         val &= ~LCPLL_PLL_DISABLE;
7871         I915_WRITE(LCPLL_CTL, val);
7872
7873         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7874                 DRM_ERROR("LCPLL not locked yet\n");
7875
7876         if (val & LCPLL_CD_SOURCE_FCLK) {
7877                 val = I915_READ(LCPLL_CTL);
7878                 val &= ~LCPLL_CD_SOURCE_FCLK;
7879                 I915_WRITE(LCPLL_CTL, val);
7880
7881                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7882                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7883                         DRM_ERROR("Switching back to LCPLL failed\n");
7884         }
7885
7886         /* See the big comment above. */
7887         spin_lock_irq(&dev_priv->uncore.lock);
7888         if (--dev_priv->uncore.forcewake_count == 0)
7889                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7890         spin_unlock_irq(&dev_priv->uncore.lock);
7891 }
7892
7893 /*
7894  * Package states C8 and deeper are really deep PC states that can only be
7895  * reached when all the devices on the system allow it, so even if the graphics
7896  * device allows PC8+, it doesn't mean the system will actually get to these
7897  * states. Our driver only allows PC8+ when going into runtime PM.
7898  *
7899  * The requirements for PC8+ are that all the outputs are disabled, the power
7900  * well is disabled and most interrupts are disabled, and these are also
7901  * requirements for runtime PM. When these conditions are met, we manually do
7902  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7903  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7904  * hang the machine.
7905  *
7906  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7907  * the state of some registers, so when we come back from PC8+ we need to
7908  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7909  * need to take care of the registers kept by RC6. Notice that this happens even
7910  * if we don't put the device in PCI D3 state (which is what currently happens
7911  * because of the runtime PM support).
7912  *
7913  * For more, read "Display Sequences for Package C8" on the hardware
7914  * documentation.
7915  */
7916 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7917 {
7918         struct drm_device *dev = dev_priv->dev;
7919         uint32_t val;
7920
7921         DRM_DEBUG_KMS("Enabling package C8+\n");
7922
7923         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7924                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7925                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7926                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7927         }
7928
7929         lpt_disable_clkout_dp(dev);
7930         hsw_disable_lcpll(dev_priv, true, true);
7931 }
7932
7933 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7934 {
7935         struct drm_device *dev = dev_priv->dev;
7936         uint32_t val;
7937
7938         DRM_DEBUG_KMS("Disabling package C8+\n");
7939
7940         hsw_restore_lcpll(dev_priv);
7941         lpt_init_pch_refclk(dev);
7942
7943         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7944                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7945                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7946                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7947         }
7948
7949         intel_prepare_ddi(dev);
7950 }
7951
7952 static void snb_modeset_global_resources(struct drm_device *dev)
7953 {
7954         modeset_update_crtc_power_domains(dev);
7955 }
7956
7957 static void haswell_modeset_global_resources(struct drm_device *dev)
7958 {
7959         modeset_update_crtc_power_domains(dev);
7960 }
7961
7962 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7963 {
7964         if (!intel_ddi_pll_select(crtc))
7965                 return -EINVAL;
7966
7967         crtc->lowfreq_avail = false;
7968
7969         return 0;
7970 }
7971
7972 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7973                                 enum port port,
7974                                 struct intel_crtc_config *pipe_config)
7975 {
7976         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7977
7978         switch (pipe_config->ddi_pll_sel) {
7979         case PORT_CLK_SEL_WRPLL1:
7980                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7981                 break;
7982         case PORT_CLK_SEL_WRPLL2:
7983                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7984                 break;
7985         }
7986 }
7987
7988 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7989                                        struct intel_crtc_config *pipe_config)
7990 {
7991         struct drm_device *dev = crtc->base.dev;
7992         struct drm_i915_private *dev_priv = dev->dev_private;
7993         struct intel_shared_dpll *pll;
7994         enum port port;
7995         uint32_t tmp;
7996
7997         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7998
7999         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8000
8001         haswell_get_ddi_pll(dev_priv, port, pipe_config);
8002
8003         if (pipe_config->shared_dpll >= 0) {
8004                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8005
8006                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8007                                            &pipe_config->dpll_hw_state));
8008         }
8009
8010         /*
8011          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8012          * DDI E. So just check whether this pipe is wired to DDI E and whether
8013          * the PCH transcoder is on.
8014          */
8015         if (INTEL_INFO(dev)->gen < 9 &&
8016             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8017                 pipe_config->has_pch_encoder = true;
8018
8019                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8020                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8021                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8022
8023                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8024         }
8025 }
8026
8027 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8028                                     struct intel_crtc_config *pipe_config)
8029 {
8030         struct drm_device *dev = crtc->base.dev;
8031         struct drm_i915_private *dev_priv = dev->dev_private;
8032         enum intel_display_power_domain pfit_domain;
8033         uint32_t tmp;
8034
8035         if (!intel_display_power_is_enabled(dev_priv,
8036                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8037                 return false;
8038
8039         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8040         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8041
8042         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8043         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8044                 enum pipe trans_edp_pipe;
8045                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8046                 default:
8047                         WARN(1, "unknown pipe linked to edp transcoder\n");
8048                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8049                 case TRANS_DDI_EDP_INPUT_A_ON:
8050                         trans_edp_pipe = PIPE_A;
8051                         break;
8052                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8053                         trans_edp_pipe = PIPE_B;
8054                         break;
8055                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8056                         trans_edp_pipe = PIPE_C;
8057                         break;
8058                 }
8059
8060                 if (trans_edp_pipe == crtc->pipe)
8061                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8062         }
8063
8064         if (!intel_display_power_is_enabled(dev_priv,
8065                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8066                 return false;
8067
8068         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8069         if (!(tmp & PIPECONF_ENABLE))
8070                 return false;
8071
8072         haswell_get_ddi_port_state(crtc, pipe_config);
8073
8074         intel_get_pipe_timings(crtc, pipe_config);
8075
8076         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8077         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8078                 ironlake_get_pfit_config(crtc, pipe_config);
8079
8080         if (IS_HASWELL(dev))
8081                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8082                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8083
8084         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8085                 pipe_config->pixel_multiplier =
8086                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8087         } else {
8088                 pipe_config->pixel_multiplier = 1;
8089         }
8090
8091         return true;
8092 }
8093
8094 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8095 {
8096         struct drm_device *dev = crtc->dev;
8097         struct drm_i915_private *dev_priv = dev->dev_private;
8098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8099         uint32_t cntl = 0, size = 0;
8100
8101         if (base) {
8102                 unsigned int width = intel_crtc->cursor_width;
8103                 unsigned int height = intel_crtc->cursor_height;
8104                 unsigned int stride = roundup_pow_of_two(width) * 4;
8105
8106                 switch (stride) {
8107                 default:
8108                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8109                                   width, stride);
8110                         stride = 256;
8111                         /* fallthrough */
8112                 case 256:
8113                 case 512:
8114                 case 1024:
8115                 case 2048:
8116                         break;
8117                 }
8118
8119                 cntl |= CURSOR_ENABLE |
8120                         CURSOR_GAMMA_ENABLE |
8121                         CURSOR_FORMAT_ARGB |
8122                         CURSOR_STRIDE(stride);
8123
8124                 size = (height << 12) | width;
8125         }
8126
8127         if (intel_crtc->cursor_cntl != 0 &&
8128             (intel_crtc->cursor_base != base ||
8129              intel_crtc->cursor_size != size ||
8130              intel_crtc->cursor_cntl != cntl)) {
8131                 /* On these chipsets we can only modify the base/size/stride
8132                  * whilst the cursor is disabled.
8133                  */
8134                 I915_WRITE(_CURACNTR, 0);
8135                 POSTING_READ(_CURACNTR);
8136                 intel_crtc->cursor_cntl = 0;
8137         }
8138
8139         if (intel_crtc->cursor_base != base) {
8140                 I915_WRITE(_CURABASE, base);
8141                 intel_crtc->cursor_base = base;
8142         }
8143
8144         if (intel_crtc->cursor_size != size) {
8145                 I915_WRITE(CURSIZE, size);
8146                 intel_crtc->cursor_size = size;
8147         }
8148
8149         if (intel_crtc->cursor_cntl != cntl) {
8150                 I915_WRITE(_CURACNTR, cntl);
8151                 POSTING_READ(_CURACNTR);
8152                 intel_crtc->cursor_cntl = cntl;
8153         }
8154 }
8155
8156 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8157 {
8158         struct drm_device *dev = crtc->dev;
8159         struct drm_i915_private *dev_priv = dev->dev_private;
8160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8161         int pipe = intel_crtc->pipe;
8162         uint32_t cntl;
8163
8164         cntl = 0;
8165         if (base) {
8166                 cntl = MCURSOR_GAMMA_ENABLE;
8167                 switch (intel_crtc->cursor_width) {
8168                         case 64:
8169                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8170                                 break;
8171                         case 128:
8172                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8173                                 break;
8174                         case 256:
8175                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8176                                 break;
8177                         default:
8178                                 WARN_ON(1);
8179                                 return;
8180                 }
8181                 cntl |= pipe << 28; /* Connect to correct pipe */
8182
8183                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8184                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8185         }
8186
8187         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8188                 cntl |= CURSOR_ROTATE_180;
8189
8190         if (intel_crtc->cursor_cntl != cntl) {
8191                 I915_WRITE(CURCNTR(pipe), cntl);
8192                 POSTING_READ(CURCNTR(pipe));
8193                 intel_crtc->cursor_cntl = cntl;
8194         }
8195
8196         /* and commit changes on next vblank */
8197         I915_WRITE(CURBASE(pipe), base);
8198         POSTING_READ(CURBASE(pipe));
8199
8200         intel_crtc->cursor_base = base;
8201 }
8202
8203 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8204 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8205                                      bool on)
8206 {
8207         struct drm_device *dev = crtc->dev;
8208         struct drm_i915_private *dev_priv = dev->dev_private;
8209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8210         int pipe = intel_crtc->pipe;
8211         int x = crtc->cursor_x;
8212         int y = crtc->cursor_y;
8213         u32 base = 0, pos = 0;
8214
8215         if (on)
8216                 base = intel_crtc->cursor_addr;
8217
8218         if (x >= intel_crtc->config.pipe_src_w)
8219                 base = 0;
8220
8221         if (y >= intel_crtc->config.pipe_src_h)
8222                 base = 0;
8223
8224         if (x < 0) {
8225                 if (x + intel_crtc->cursor_width <= 0)
8226                         base = 0;
8227
8228                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8229                 x = -x;
8230         }
8231         pos |= x << CURSOR_X_SHIFT;
8232
8233         if (y < 0) {
8234                 if (y + intel_crtc->cursor_height <= 0)
8235                         base = 0;
8236
8237                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8238                 y = -y;
8239         }
8240         pos |= y << CURSOR_Y_SHIFT;
8241
8242         if (base == 0 && intel_crtc->cursor_base == 0)
8243                 return;
8244
8245         I915_WRITE(CURPOS(pipe), pos);
8246
8247         /* ILK+ do this automagically */
8248         if (HAS_GMCH_DISPLAY(dev) &&
8249                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8250                 base += (intel_crtc->cursor_height *
8251                         intel_crtc->cursor_width - 1) * 4;
8252         }
8253
8254         if (IS_845G(dev) || IS_I865G(dev))
8255                 i845_update_cursor(crtc, base);
8256         else
8257                 i9xx_update_cursor(crtc, base);
8258 }
8259
8260 static bool cursor_size_ok(struct drm_device *dev,
8261                            uint32_t width, uint32_t height)
8262 {
8263         if (width == 0 || height == 0)
8264                 return false;
8265
8266         /*
8267          * 845g/865g are special in that they are only limited by
8268          * the width of their cursors, the height is arbitrary up to
8269          * the precision of the register. Everything else requires
8270          * square cursors, limited to a few power-of-two sizes.
8271          */
8272         if (IS_845G(dev) || IS_I865G(dev)) {
8273                 if ((width & 63) != 0)
8274                         return false;
8275
8276                 if (width > (IS_845G(dev) ? 64 : 512))
8277                         return false;
8278
8279                 if (height > 1023)
8280                         return false;
8281         } else {
8282                 switch (width | height) {
8283                 case 256:
8284                 case 128:
8285                         if (IS_GEN2(dev))
8286                                 return false;
8287                 case 64:
8288                         break;
8289                 default:
8290                         return false;
8291                 }
8292         }
8293
8294         return true;
8295 }
8296
8297 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8298                                      struct drm_i915_gem_object *obj,
8299                                      uint32_t width, uint32_t height)
8300 {
8301         struct drm_device *dev = crtc->dev;
8302         struct drm_i915_private *dev_priv = dev->dev_private;
8303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8304         enum pipe pipe = intel_crtc->pipe;
8305         unsigned old_width;
8306         uint32_t addr;
8307         int ret;
8308
8309         /* if we want to turn off the cursor ignore width and height */
8310         if (!obj) {
8311                 DRM_DEBUG_KMS("cursor off\n");
8312                 addr = 0;
8313                 mutex_lock(&dev->struct_mutex);
8314                 goto finish;
8315         }
8316
8317         /* we only need to pin inside GTT if cursor is non-phy */
8318         mutex_lock(&dev->struct_mutex);
8319         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8320                 unsigned alignment;
8321
8322                 /*
8323                  * Global gtt pte registers are special registers which actually
8324                  * forward writes to a chunk of system memory. Which means that
8325                  * there is no risk that the register values disappear as soon
8326                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8327                  * only the pin/unpin/fence and not more.
8328                  */
8329                 intel_runtime_pm_get(dev_priv);
8330
8331                 /* Note that the w/a also requires 2 PTE of padding following
8332                  * the bo. We currently fill all unused PTE with the shadow
8333                  * page and so we should always have valid PTE following the
8334                  * cursor preventing the VT-d warning.
8335                  */
8336                 alignment = 0;
8337                 if (need_vtd_wa(dev))
8338                         alignment = 64*1024;
8339
8340                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8341                 if (ret) {
8342                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8343                         intel_runtime_pm_put(dev_priv);
8344                         goto fail_locked;
8345                 }
8346
8347                 ret = i915_gem_object_put_fence(obj);
8348                 if (ret) {
8349                         DRM_DEBUG_KMS("failed to release fence for cursor");
8350                         intel_runtime_pm_put(dev_priv);
8351                         goto fail_unpin;
8352                 }
8353
8354                 addr = i915_gem_obj_ggtt_offset(obj);
8355
8356                 intel_runtime_pm_put(dev_priv);
8357         } else {
8358                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8359                 ret = i915_gem_object_attach_phys(obj, align);
8360                 if (ret) {
8361                         DRM_DEBUG_KMS("failed to attach phys object\n");
8362                         goto fail_locked;
8363                 }
8364                 addr = obj->phys_handle->busaddr;
8365         }
8366
8367  finish:
8368         if (intel_crtc->cursor_bo) {
8369                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8370                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8371         }
8372
8373         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8374                           INTEL_FRONTBUFFER_CURSOR(pipe));
8375         mutex_unlock(&dev->struct_mutex);
8376
8377         old_width = intel_crtc->cursor_width;
8378
8379         intel_crtc->cursor_addr = addr;
8380         intel_crtc->cursor_bo = obj;
8381         intel_crtc->cursor_width = width;
8382         intel_crtc->cursor_height = height;
8383
8384         if (intel_crtc->active) {
8385                 if (old_width != width)
8386                         intel_update_watermarks(crtc);
8387                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8388
8389                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8390         }
8391
8392         return 0;
8393 fail_unpin:
8394         i915_gem_object_unpin_from_display_plane(obj);
8395 fail_locked:
8396         mutex_unlock(&dev->struct_mutex);
8397         return ret;
8398 }
8399
8400 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8401                                  u16 *blue, uint32_t start, uint32_t size)
8402 {
8403         int end = (start + size > 256) ? 256 : start + size, i;
8404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8405
8406         for (i = start; i < end; i++) {
8407                 intel_crtc->lut_r[i] = red[i] >> 8;
8408                 intel_crtc->lut_g[i] = green[i] >> 8;
8409                 intel_crtc->lut_b[i] = blue[i] >> 8;
8410         }
8411
8412         intel_crtc_load_lut(crtc);
8413 }
8414
8415 /* VESA 640x480x72Hz mode to set on the pipe */
8416 static struct drm_display_mode load_detect_mode = {
8417         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8418                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8419 };
8420
8421 struct drm_framebuffer *
8422 __intel_framebuffer_create(struct drm_device *dev,
8423                            struct drm_mode_fb_cmd2 *mode_cmd,
8424                            struct drm_i915_gem_object *obj)
8425 {
8426         struct intel_framebuffer *intel_fb;
8427         int ret;
8428
8429         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8430         if (!intel_fb) {
8431                 drm_gem_object_unreference_unlocked(&obj->base);
8432                 return ERR_PTR(-ENOMEM);
8433         }
8434
8435         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8436         if (ret)
8437                 goto err;
8438
8439         return &intel_fb->base;
8440 err:
8441         drm_gem_object_unreference_unlocked(&obj->base);
8442         kfree(intel_fb);
8443
8444         return ERR_PTR(ret);
8445 }
8446
8447 static struct drm_framebuffer *
8448 intel_framebuffer_create(struct drm_device *dev,
8449                          struct drm_mode_fb_cmd2 *mode_cmd,
8450                          struct drm_i915_gem_object *obj)
8451 {
8452         struct drm_framebuffer *fb;
8453         int ret;
8454
8455         ret = i915_mutex_lock_interruptible(dev);
8456         if (ret)
8457                 return ERR_PTR(ret);
8458         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8459         mutex_unlock(&dev->struct_mutex);
8460
8461         return fb;
8462 }
8463
8464 static u32
8465 intel_framebuffer_pitch_for_width(int width, int bpp)
8466 {
8467         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8468         return ALIGN(pitch, 64);
8469 }
8470
8471 static u32
8472 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8473 {
8474         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8475         return PAGE_ALIGN(pitch * mode->vdisplay);
8476 }
8477
8478 static struct drm_framebuffer *
8479 intel_framebuffer_create_for_mode(struct drm_device *dev,
8480                                   struct drm_display_mode *mode,
8481                                   int depth, int bpp)
8482 {
8483         struct drm_i915_gem_object *obj;
8484         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8485
8486         obj = i915_gem_alloc_object(dev,
8487                                     intel_framebuffer_size_for_mode(mode, bpp));
8488         if (obj == NULL)
8489                 return ERR_PTR(-ENOMEM);
8490
8491         mode_cmd.width = mode->hdisplay;
8492         mode_cmd.height = mode->vdisplay;
8493         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8494                                                                 bpp);
8495         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8496
8497         return intel_framebuffer_create(dev, &mode_cmd, obj);
8498 }
8499
8500 static struct drm_framebuffer *
8501 mode_fits_in_fbdev(struct drm_device *dev,
8502                    struct drm_display_mode *mode)
8503 {
8504 #ifdef CONFIG_DRM_I915_FBDEV
8505         struct drm_i915_private *dev_priv = dev->dev_private;
8506         struct drm_i915_gem_object *obj;
8507         struct drm_framebuffer *fb;
8508
8509         if (!dev_priv->fbdev)
8510                 return NULL;
8511
8512         if (!dev_priv->fbdev->fb)
8513                 return NULL;
8514
8515         obj = dev_priv->fbdev->fb->obj;
8516         BUG_ON(!obj);
8517
8518         fb = &dev_priv->fbdev->fb->base;
8519         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8520                                                                fb->bits_per_pixel))
8521                 return NULL;
8522
8523         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8524                 return NULL;
8525
8526         return fb;
8527 #else
8528         return NULL;
8529 #endif
8530 }
8531
8532 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8533                                 struct drm_display_mode *mode,
8534                                 struct intel_load_detect_pipe *old,
8535                                 struct drm_modeset_acquire_ctx *ctx)
8536 {
8537         struct intel_crtc *intel_crtc;
8538         struct intel_encoder *intel_encoder =
8539                 intel_attached_encoder(connector);
8540         struct drm_crtc *possible_crtc;
8541         struct drm_encoder *encoder = &intel_encoder->base;
8542         struct drm_crtc *crtc = NULL;
8543         struct drm_device *dev = encoder->dev;
8544         struct drm_framebuffer *fb;
8545         struct drm_mode_config *config = &dev->mode_config;
8546         int ret, i = -1;
8547
8548         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8549                       connector->base.id, connector->name,
8550                       encoder->base.id, encoder->name);
8551
8552 retry:
8553         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8554         if (ret)
8555                 goto fail_unlock;
8556
8557         /*
8558          * Algorithm gets a little messy:
8559          *
8560          *   - if the connector already has an assigned crtc, use it (but make
8561          *     sure it's on first)
8562          *
8563          *   - try to find the first unused crtc that can drive this connector,
8564          *     and use that if we find one
8565          */
8566
8567         /* See if we already have a CRTC for this connector */
8568         if (encoder->crtc) {
8569                 crtc = encoder->crtc;
8570
8571                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8572                 if (ret)
8573                         goto fail_unlock;
8574
8575                 old->dpms_mode = connector->dpms;
8576                 old->load_detect_temp = false;
8577
8578                 /* Make sure the crtc and connector are running */
8579                 if (connector->dpms != DRM_MODE_DPMS_ON)
8580                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8581
8582                 return true;
8583         }
8584
8585         /* Find an unused one (if possible) */
8586         for_each_crtc(dev, possible_crtc) {
8587                 i++;
8588                 if (!(encoder->possible_crtcs & (1 << i)))
8589                         continue;
8590                 if (possible_crtc->enabled)
8591                         continue;
8592                 /* This can occur when applying the pipe A quirk on resume. */
8593                 if (to_intel_crtc(possible_crtc)->new_enabled)
8594                         continue;
8595
8596                 crtc = possible_crtc;
8597                 break;
8598         }
8599
8600         /*
8601          * If we didn't find an unused CRTC, don't use any.
8602          */
8603         if (!crtc) {
8604                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8605                 goto fail_unlock;
8606         }
8607
8608         ret = drm_modeset_lock(&crtc->mutex, ctx);
8609         if (ret)
8610                 goto fail_unlock;
8611         intel_encoder->new_crtc = to_intel_crtc(crtc);
8612         to_intel_connector(connector)->new_encoder = intel_encoder;
8613
8614         intel_crtc = to_intel_crtc(crtc);
8615         intel_crtc->new_enabled = true;
8616         intel_crtc->new_config = &intel_crtc->config;
8617         old->dpms_mode = connector->dpms;
8618         old->load_detect_temp = true;
8619         old->release_fb = NULL;
8620
8621         if (!mode)
8622                 mode = &load_detect_mode;
8623
8624         /* We need a framebuffer large enough to accommodate all accesses
8625          * that the plane may generate whilst we perform load detection.
8626          * We can not rely on the fbcon either being present (we get called
8627          * during its initialisation to detect all boot displays, or it may
8628          * not even exist) or that it is large enough to satisfy the
8629          * requested mode.
8630          */
8631         fb = mode_fits_in_fbdev(dev, mode);
8632         if (fb == NULL) {
8633                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8634                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8635                 old->release_fb = fb;
8636         } else
8637                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8638         if (IS_ERR(fb)) {
8639                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8640                 goto fail;
8641         }
8642
8643         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8644                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8645                 if (old->release_fb)
8646                         old->release_fb->funcs->destroy(old->release_fb);
8647                 goto fail;
8648         }
8649
8650         /* let the connector get through one full cycle before testing */
8651         intel_wait_for_vblank(dev, intel_crtc->pipe);
8652         return true;
8653
8654  fail:
8655         intel_crtc->new_enabled = crtc->enabled;
8656         if (intel_crtc->new_enabled)
8657                 intel_crtc->new_config = &intel_crtc->config;
8658         else
8659                 intel_crtc->new_config = NULL;
8660 fail_unlock:
8661         if (ret == -EDEADLK) {
8662                 drm_modeset_backoff(ctx);
8663                 goto retry;
8664         }
8665
8666         return false;
8667 }
8668
8669 void intel_release_load_detect_pipe(struct drm_connector *connector,
8670                                     struct intel_load_detect_pipe *old)
8671 {
8672         struct intel_encoder *intel_encoder =
8673                 intel_attached_encoder(connector);
8674         struct drm_encoder *encoder = &intel_encoder->base;
8675         struct drm_crtc *crtc = encoder->crtc;
8676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8677
8678         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8679                       connector->base.id, connector->name,
8680                       encoder->base.id, encoder->name);
8681
8682         if (old->load_detect_temp) {
8683                 to_intel_connector(connector)->new_encoder = NULL;
8684                 intel_encoder->new_crtc = NULL;
8685                 intel_crtc->new_enabled = false;
8686                 intel_crtc->new_config = NULL;
8687                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8688
8689                 if (old->release_fb) {
8690                         drm_framebuffer_unregister_private(old->release_fb);
8691                         drm_framebuffer_unreference(old->release_fb);
8692                 }
8693
8694                 return;
8695         }
8696
8697         /* Switch crtc and encoder back off if necessary */
8698         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8699                 connector->funcs->dpms(connector, old->dpms_mode);
8700 }
8701
8702 static int i9xx_pll_refclk(struct drm_device *dev,
8703                            const struct intel_crtc_config *pipe_config)
8704 {
8705         struct drm_i915_private *dev_priv = dev->dev_private;
8706         u32 dpll = pipe_config->dpll_hw_state.dpll;
8707
8708         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8709                 return dev_priv->vbt.lvds_ssc_freq;
8710         else if (HAS_PCH_SPLIT(dev))
8711                 return 120000;
8712         else if (!IS_GEN2(dev))
8713                 return 96000;
8714         else
8715                 return 48000;
8716 }
8717
8718 /* Returns the clock of the currently programmed mode of the given pipe. */
8719 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8720                                 struct intel_crtc_config *pipe_config)
8721 {
8722         struct drm_device *dev = crtc->base.dev;
8723         struct drm_i915_private *dev_priv = dev->dev_private;
8724         int pipe = pipe_config->cpu_transcoder;
8725         u32 dpll = pipe_config->dpll_hw_state.dpll;
8726         u32 fp;
8727         intel_clock_t clock;
8728         int refclk = i9xx_pll_refclk(dev, pipe_config);
8729
8730         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8731                 fp = pipe_config->dpll_hw_state.fp0;
8732         else
8733                 fp = pipe_config->dpll_hw_state.fp1;
8734
8735         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8736         if (IS_PINEVIEW(dev)) {
8737                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8738                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8739         } else {
8740                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8741                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8742         }
8743
8744         if (!IS_GEN2(dev)) {
8745                 if (IS_PINEVIEW(dev))
8746                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8747                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8748                 else
8749                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8750                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8751
8752                 switch (dpll & DPLL_MODE_MASK) {
8753                 case DPLLB_MODE_DAC_SERIAL:
8754                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8755                                 5 : 10;
8756                         break;
8757                 case DPLLB_MODE_LVDS:
8758                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8759                                 7 : 14;
8760                         break;
8761                 default:
8762                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8763                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8764                         return;
8765                 }
8766
8767                 if (IS_PINEVIEW(dev))
8768                         pineview_clock(refclk, &clock);
8769                 else
8770                         i9xx_clock(refclk, &clock);
8771         } else {
8772                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8773                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8774
8775                 if (is_lvds) {
8776                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8777                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8778
8779                         if (lvds & LVDS_CLKB_POWER_UP)
8780                                 clock.p2 = 7;
8781                         else
8782                                 clock.p2 = 14;
8783                 } else {
8784                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8785                                 clock.p1 = 2;
8786                         else {
8787                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8788                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8789                         }
8790                         if (dpll & PLL_P2_DIVIDE_BY_4)
8791                                 clock.p2 = 4;
8792                         else
8793                                 clock.p2 = 2;
8794                 }
8795
8796                 i9xx_clock(refclk, &clock);
8797         }
8798
8799         /*
8800          * This value includes pixel_multiplier. We will use
8801          * port_clock to compute adjusted_mode.crtc_clock in the
8802          * encoder's get_config() function.
8803          */
8804         pipe_config->port_clock = clock.dot;
8805 }
8806
8807 int intel_dotclock_calculate(int link_freq,
8808                              const struct intel_link_m_n *m_n)
8809 {
8810         /*
8811          * The calculation for the data clock is:
8812          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8813          * But we want to avoid losing precison if possible, so:
8814          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8815          *
8816          * and the link clock is simpler:
8817          * link_clock = (m * link_clock) / n
8818          */
8819
8820         if (!m_n->link_n)
8821                 return 0;
8822
8823         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8824 }
8825
8826 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8827                                    struct intel_crtc_config *pipe_config)
8828 {
8829         struct drm_device *dev = crtc->base.dev;
8830
8831         /* read out port_clock from the DPLL */
8832         i9xx_crtc_clock_get(crtc, pipe_config);
8833
8834         /*
8835          * This value does not include pixel_multiplier.
8836          * We will check that port_clock and adjusted_mode.crtc_clock
8837          * agree once we know their relationship in the encoder's
8838          * get_config() function.
8839          */
8840         pipe_config->adjusted_mode.crtc_clock =
8841                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8842                                          &pipe_config->fdi_m_n);
8843 }
8844
8845 /** Returns the currently programmed mode of the given pipe. */
8846 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8847                                              struct drm_crtc *crtc)
8848 {
8849         struct drm_i915_private *dev_priv = dev->dev_private;
8850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8851         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8852         struct drm_display_mode *mode;
8853         struct intel_crtc_config pipe_config;
8854         int htot = I915_READ(HTOTAL(cpu_transcoder));
8855         int hsync = I915_READ(HSYNC(cpu_transcoder));
8856         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8857         int vsync = I915_READ(VSYNC(cpu_transcoder));
8858         enum pipe pipe = intel_crtc->pipe;
8859
8860         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8861         if (!mode)
8862                 return NULL;
8863
8864         /*
8865          * Construct a pipe_config sufficient for getting the clock info
8866          * back out of crtc_clock_get.
8867          *
8868          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8869          * to use a real value here instead.
8870          */
8871         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8872         pipe_config.pixel_multiplier = 1;
8873         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8874         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8875         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8876         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8877
8878         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8879         mode->hdisplay = (htot & 0xffff) + 1;
8880         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8881         mode->hsync_start = (hsync & 0xffff) + 1;
8882         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8883         mode->vdisplay = (vtot & 0xffff) + 1;
8884         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8885         mode->vsync_start = (vsync & 0xffff) + 1;
8886         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8887
8888         drm_mode_set_name(mode);
8889
8890         return mode;
8891 }
8892
8893 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8894 {
8895         struct drm_device *dev = crtc->dev;
8896         struct drm_i915_private *dev_priv = dev->dev_private;
8897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8898
8899         if (!HAS_GMCH_DISPLAY(dev))
8900                 return;
8901
8902         if (!dev_priv->lvds_downclock_avail)
8903                 return;
8904
8905         /*
8906          * Since this is called by a timer, we should never get here in
8907          * the manual case.
8908          */
8909         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8910                 int pipe = intel_crtc->pipe;
8911                 int dpll_reg = DPLL(pipe);
8912                 int dpll;
8913
8914                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8915
8916                 assert_panel_unlocked(dev_priv, pipe);
8917
8918                 dpll = I915_READ(dpll_reg);
8919                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8920                 I915_WRITE(dpll_reg, dpll);
8921                 intel_wait_for_vblank(dev, pipe);
8922                 dpll = I915_READ(dpll_reg);
8923                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8924                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8925         }
8926
8927 }
8928
8929 void intel_mark_busy(struct drm_device *dev)
8930 {
8931         struct drm_i915_private *dev_priv = dev->dev_private;
8932
8933         if (dev_priv->mm.busy)
8934                 return;
8935
8936         intel_runtime_pm_get(dev_priv);
8937         i915_update_gfx_val(dev_priv);
8938         dev_priv->mm.busy = true;
8939 }
8940
8941 void intel_mark_idle(struct drm_device *dev)
8942 {
8943         struct drm_i915_private *dev_priv = dev->dev_private;
8944         struct drm_crtc *crtc;
8945
8946         if (!dev_priv->mm.busy)
8947                 return;
8948
8949         dev_priv->mm.busy = false;
8950
8951         if (!i915.powersave)
8952                 goto out;
8953
8954         for_each_crtc(dev, crtc) {
8955                 if (!crtc->primary->fb)
8956                         continue;
8957
8958                 intel_decrease_pllclock(crtc);
8959         }
8960
8961         if (INTEL_INFO(dev)->gen >= 6)
8962                 gen6_rps_idle(dev->dev_private);
8963
8964 out:
8965         intel_runtime_pm_put(dev_priv);
8966 }
8967
8968 static void intel_crtc_destroy(struct drm_crtc *crtc)
8969 {
8970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8971         struct drm_device *dev = crtc->dev;
8972         struct intel_unpin_work *work;
8973
8974         spin_lock_irq(&dev->event_lock);
8975         work = intel_crtc->unpin_work;
8976         intel_crtc->unpin_work = NULL;
8977         spin_unlock_irq(&dev->event_lock);
8978
8979         if (work) {
8980                 cancel_work_sync(&work->work);
8981                 kfree(work);
8982         }
8983
8984         drm_crtc_cleanup(crtc);
8985
8986         kfree(intel_crtc);
8987 }
8988
8989 static void intel_unpin_work_fn(struct work_struct *__work)
8990 {
8991         struct intel_unpin_work *work =
8992                 container_of(__work, struct intel_unpin_work, work);
8993         struct drm_device *dev = work->crtc->dev;
8994         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8995
8996         mutex_lock(&dev->struct_mutex);
8997         intel_unpin_fb_obj(work->old_fb_obj);
8998         drm_gem_object_unreference(&work->pending_flip_obj->base);
8999         drm_gem_object_unreference(&work->old_fb_obj->base);
9000
9001         intel_update_fbc(dev);
9002         mutex_unlock(&dev->struct_mutex);
9003
9004         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9005
9006         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9007         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9008
9009         kfree(work);
9010 }
9011
9012 static void do_intel_finish_page_flip(struct drm_device *dev,
9013                                       struct drm_crtc *crtc)
9014 {
9015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9016         struct intel_unpin_work *work;
9017         unsigned long flags;
9018
9019         /* Ignore early vblank irqs */
9020         if (intel_crtc == NULL)
9021                 return;
9022
9023         /*
9024          * This is called both by irq handlers and the reset code (to complete
9025          * lost pageflips) so needs the full irqsave spinlocks.
9026          */
9027         spin_lock_irqsave(&dev->event_lock, flags);
9028         work = intel_crtc->unpin_work;
9029
9030         /* Ensure we don't miss a work->pending update ... */
9031         smp_rmb();
9032
9033         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9034                 spin_unlock_irqrestore(&dev->event_lock, flags);
9035                 return;
9036         }
9037
9038         page_flip_completed(intel_crtc);
9039
9040         spin_unlock_irqrestore(&dev->event_lock, flags);
9041 }
9042
9043 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9044 {
9045         struct drm_i915_private *dev_priv = dev->dev_private;
9046         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9047
9048         do_intel_finish_page_flip(dev, crtc);
9049 }
9050
9051 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9052 {
9053         struct drm_i915_private *dev_priv = dev->dev_private;
9054         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9055
9056         do_intel_finish_page_flip(dev, crtc);
9057 }
9058
9059 /* Is 'a' after or equal to 'b'? */
9060 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9061 {
9062         return !((a - b) & 0x80000000);
9063 }
9064
9065 static bool page_flip_finished(struct intel_crtc *crtc)
9066 {
9067         struct drm_device *dev = crtc->base.dev;
9068         struct drm_i915_private *dev_priv = dev->dev_private;
9069
9070         /*
9071          * The relevant registers doen't exist on pre-ctg.
9072          * As the flip done interrupt doesn't trigger for mmio
9073          * flips on gmch platforms, a flip count check isn't
9074          * really needed there. But since ctg has the registers,
9075          * include it in the check anyway.
9076          */
9077         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9078                 return true;
9079
9080         /*
9081          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9082          * used the same base address. In that case the mmio flip might
9083          * have completed, but the CS hasn't even executed the flip yet.
9084          *
9085          * A flip count check isn't enough as the CS might have updated
9086          * the base address just after start of vblank, but before we
9087          * managed to process the interrupt. This means we'd complete the
9088          * CS flip too soon.
9089          *
9090          * Combining both checks should get us a good enough result. It may
9091          * still happen that the CS flip has been executed, but has not
9092          * yet actually completed. But in case the base address is the same
9093          * anyway, we don't really care.
9094          */
9095         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9096                 crtc->unpin_work->gtt_offset &&
9097                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9098                                     crtc->unpin_work->flip_count);
9099 }
9100
9101 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9102 {
9103         struct drm_i915_private *dev_priv = dev->dev_private;
9104         struct intel_crtc *intel_crtc =
9105                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9106         unsigned long flags;
9107
9108
9109         /*
9110          * This is called both by irq handlers and the reset code (to complete
9111          * lost pageflips) so needs the full irqsave spinlocks.
9112          *
9113          * NB: An MMIO update of the plane base pointer will also
9114          * generate a page-flip completion irq, i.e. every modeset
9115          * is also accompanied by a spurious intel_prepare_page_flip().
9116          */
9117         spin_lock_irqsave(&dev->event_lock, flags);
9118         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9119                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9120         spin_unlock_irqrestore(&dev->event_lock, flags);
9121 }
9122
9123 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9124 {
9125         /* Ensure that the work item is consistent when activating it ... */
9126         smp_wmb();
9127         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9128         /* and that it is marked active as soon as the irq could fire. */
9129         smp_wmb();
9130 }
9131
9132 static int intel_gen2_queue_flip(struct drm_device *dev,
9133                                  struct drm_crtc *crtc,
9134                                  struct drm_framebuffer *fb,
9135                                  struct drm_i915_gem_object *obj,
9136                                  struct intel_engine_cs *ring,
9137                                  uint32_t flags)
9138 {
9139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9140         u32 flip_mask;
9141         int ret;
9142
9143         ret = intel_ring_begin(ring, 6);
9144         if (ret)
9145                 return ret;
9146
9147         /* Can't queue multiple flips, so wait for the previous
9148          * one to finish before executing the next.
9149          */
9150         if (intel_crtc->plane)
9151                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9152         else
9153                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9154         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9155         intel_ring_emit(ring, MI_NOOP);
9156         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9157                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9158         intel_ring_emit(ring, fb->pitches[0]);
9159         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9160         intel_ring_emit(ring, 0); /* aux display base address, unused */
9161
9162         intel_mark_page_flip_active(intel_crtc);
9163         __intel_ring_advance(ring);
9164         return 0;
9165 }
9166
9167 static int intel_gen3_queue_flip(struct drm_device *dev,
9168                                  struct drm_crtc *crtc,
9169                                  struct drm_framebuffer *fb,
9170                                  struct drm_i915_gem_object *obj,
9171                                  struct intel_engine_cs *ring,
9172                                  uint32_t flags)
9173 {
9174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9175         u32 flip_mask;
9176         int ret;
9177
9178         ret = intel_ring_begin(ring, 6);
9179         if (ret)
9180                 return ret;
9181
9182         if (intel_crtc->plane)
9183                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9184         else
9185                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9186         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9187         intel_ring_emit(ring, MI_NOOP);
9188         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9189                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9190         intel_ring_emit(ring, fb->pitches[0]);
9191         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9192         intel_ring_emit(ring, MI_NOOP);
9193
9194         intel_mark_page_flip_active(intel_crtc);
9195         __intel_ring_advance(ring);
9196         return 0;
9197 }
9198
9199 static int intel_gen4_queue_flip(struct drm_device *dev,
9200                                  struct drm_crtc *crtc,
9201                                  struct drm_framebuffer *fb,
9202                                  struct drm_i915_gem_object *obj,
9203                                  struct intel_engine_cs *ring,
9204                                  uint32_t flags)
9205 {
9206         struct drm_i915_private *dev_priv = dev->dev_private;
9207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9208         uint32_t pf, pipesrc;
9209         int ret;
9210
9211         ret = intel_ring_begin(ring, 4);
9212         if (ret)
9213                 return ret;
9214
9215         /* i965+ uses the linear or tiled offsets from the
9216          * Display Registers (which do not change across a page-flip)
9217          * so we need only reprogram the base address.
9218          */
9219         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9220                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9221         intel_ring_emit(ring, fb->pitches[0]);
9222         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9223                         obj->tiling_mode);
9224
9225         /* XXX Enabling the panel-fitter across page-flip is so far
9226          * untested on non-native modes, so ignore it for now.
9227          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9228          */
9229         pf = 0;
9230         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9231         intel_ring_emit(ring, pf | pipesrc);
9232
9233         intel_mark_page_flip_active(intel_crtc);
9234         __intel_ring_advance(ring);
9235         return 0;
9236 }
9237
9238 static int intel_gen6_queue_flip(struct drm_device *dev,
9239                                  struct drm_crtc *crtc,
9240                                  struct drm_framebuffer *fb,
9241                                  struct drm_i915_gem_object *obj,
9242                                  struct intel_engine_cs *ring,
9243                                  uint32_t flags)
9244 {
9245         struct drm_i915_private *dev_priv = dev->dev_private;
9246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9247         uint32_t pf, pipesrc;
9248         int ret;
9249
9250         ret = intel_ring_begin(ring, 4);
9251         if (ret)
9252                 return ret;
9253
9254         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9255                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9256         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9257         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9258
9259         /* Contrary to the suggestions in the documentation,
9260          * "Enable Panel Fitter" does not seem to be required when page
9261          * flipping with a non-native mode, and worse causes a normal
9262          * modeset to fail.
9263          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9264          */
9265         pf = 0;
9266         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9267         intel_ring_emit(ring, pf | pipesrc);
9268
9269         intel_mark_page_flip_active(intel_crtc);
9270         __intel_ring_advance(ring);
9271         return 0;
9272 }
9273
9274 static int intel_gen7_queue_flip(struct drm_device *dev,
9275                                  struct drm_crtc *crtc,
9276                                  struct drm_framebuffer *fb,
9277                                  struct drm_i915_gem_object *obj,
9278                                  struct intel_engine_cs *ring,
9279                                  uint32_t flags)
9280 {
9281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9282         uint32_t plane_bit = 0;
9283         int len, ret;
9284
9285         switch (intel_crtc->plane) {
9286         case PLANE_A:
9287                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9288                 break;
9289         case PLANE_B:
9290                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9291                 break;
9292         case PLANE_C:
9293                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9294                 break;
9295         default:
9296                 WARN_ONCE(1, "unknown plane in flip command\n");
9297                 return -ENODEV;
9298         }
9299
9300         len = 4;
9301         if (ring->id == RCS) {
9302                 len += 6;
9303                 /*
9304                  * On Gen 8, SRM is now taking an extra dword to accommodate
9305                  * 48bits addresses, and we need a NOOP for the batch size to
9306                  * stay even.
9307                  */
9308                 if (IS_GEN8(dev))
9309                         len += 2;
9310         }
9311
9312         /*
9313          * BSpec MI_DISPLAY_FLIP for IVB:
9314          * "The full packet must be contained within the same cache line."
9315          *
9316          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9317          * cacheline, if we ever start emitting more commands before
9318          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9319          * then do the cacheline alignment, and finally emit the
9320          * MI_DISPLAY_FLIP.
9321          */
9322         ret = intel_ring_cacheline_align(ring);
9323         if (ret)
9324                 return ret;
9325
9326         ret = intel_ring_begin(ring, len);
9327         if (ret)
9328                 return ret;
9329
9330         /* Unmask the flip-done completion message. Note that the bspec says that
9331          * we should do this for both the BCS and RCS, and that we must not unmask
9332          * more than one flip event at any time (or ensure that one flip message
9333          * can be sent by waiting for flip-done prior to queueing new flips).
9334          * Experimentation says that BCS works despite DERRMR masking all
9335          * flip-done completion events and that unmasking all planes at once
9336          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9337          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9338          */
9339         if (ring->id == RCS) {
9340                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9341                 intel_ring_emit(ring, DERRMR);
9342                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9343                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9344                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9345                 if (IS_GEN8(dev))
9346                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9347                                               MI_SRM_LRM_GLOBAL_GTT);
9348                 else
9349                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9350                                               MI_SRM_LRM_GLOBAL_GTT);
9351                 intel_ring_emit(ring, DERRMR);
9352                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9353                 if (IS_GEN8(dev)) {
9354                         intel_ring_emit(ring, 0);
9355                         intel_ring_emit(ring, MI_NOOP);
9356                 }
9357         }
9358
9359         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9360         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9361         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9362         intel_ring_emit(ring, (MI_NOOP));
9363
9364         intel_mark_page_flip_active(intel_crtc);
9365         __intel_ring_advance(ring);
9366         return 0;
9367 }
9368
9369 static bool use_mmio_flip(struct intel_engine_cs *ring,
9370                           struct drm_i915_gem_object *obj)
9371 {
9372         /*
9373          * This is not being used for older platforms, because
9374          * non-availability of flip done interrupt forces us to use
9375          * CS flips. Older platforms derive flip done using some clever
9376          * tricks involving the flip_pending status bits and vblank irqs.
9377          * So using MMIO flips there would disrupt this mechanism.
9378          */
9379
9380         if (ring == NULL)
9381                 return true;
9382
9383         if (INTEL_INFO(ring->dev)->gen < 5)
9384                 return false;
9385
9386         if (i915.use_mmio_flip < 0)
9387                 return false;
9388         else if (i915.use_mmio_flip > 0)
9389                 return true;
9390         else if (i915.enable_execlists)
9391                 return true;
9392         else
9393                 return ring != obj->ring;
9394 }
9395
9396 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9397 {
9398         struct drm_device *dev = intel_crtc->base.dev;
9399         struct drm_i915_private *dev_priv = dev->dev_private;
9400         struct intel_framebuffer *intel_fb =
9401                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9402         struct drm_i915_gem_object *obj = intel_fb->obj;
9403         u32 dspcntr;
9404         u32 reg;
9405
9406         intel_mark_page_flip_active(intel_crtc);
9407
9408         reg = DSPCNTR(intel_crtc->plane);
9409         dspcntr = I915_READ(reg);
9410
9411         if (obj->tiling_mode != I915_TILING_NONE)
9412                 dspcntr |= DISPPLANE_TILED;
9413         else
9414                 dspcntr &= ~DISPPLANE_TILED;
9415
9416         I915_WRITE(reg, dspcntr);
9417
9418         I915_WRITE(DSPSURF(intel_crtc->plane),
9419                    intel_crtc->unpin_work->gtt_offset);
9420         POSTING_READ(DSPSURF(intel_crtc->plane));
9421 }
9422
9423 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9424 {
9425         struct intel_engine_cs *ring;
9426         int ret;
9427
9428         lockdep_assert_held(&obj->base.dev->struct_mutex);
9429
9430         if (!obj->last_write_seqno)
9431                 return 0;
9432
9433         ring = obj->ring;
9434
9435         if (i915_seqno_passed(ring->get_seqno(ring, true),
9436                               obj->last_write_seqno))
9437                 return 0;
9438
9439         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9440         if (ret)
9441                 return ret;
9442
9443         if (WARN_ON(!ring->irq_get(ring)))
9444                 return 0;
9445
9446         return 1;
9447 }
9448
9449 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9450 {
9451         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9452         struct intel_crtc *intel_crtc;
9453         unsigned long irq_flags;
9454         u32 seqno;
9455
9456         seqno = ring->get_seqno(ring, false);
9457
9458         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9459         for_each_intel_crtc(ring->dev, intel_crtc) {
9460                 struct intel_mmio_flip *mmio_flip;
9461
9462                 mmio_flip = &intel_crtc->mmio_flip;
9463                 if (mmio_flip->seqno == 0)
9464                         continue;
9465
9466                 if (ring->id != mmio_flip->ring_id)
9467                         continue;
9468
9469                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9470                         intel_do_mmio_flip(intel_crtc);
9471                         mmio_flip->seqno = 0;
9472                         ring->irq_put(ring);
9473                 }
9474         }
9475         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9476 }
9477
9478 static int intel_queue_mmio_flip(struct drm_device *dev,
9479                                  struct drm_crtc *crtc,
9480                                  struct drm_framebuffer *fb,
9481                                  struct drm_i915_gem_object *obj,
9482                                  struct intel_engine_cs *ring,
9483                                  uint32_t flags)
9484 {
9485         struct drm_i915_private *dev_priv = dev->dev_private;
9486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9487         int ret;
9488
9489         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9490                 return -EBUSY;
9491
9492         ret = intel_postpone_flip(obj);
9493         if (ret < 0)
9494                 return ret;
9495         if (ret == 0) {
9496                 intel_do_mmio_flip(intel_crtc);
9497                 return 0;
9498         }
9499
9500         spin_lock_irq(&dev_priv->mmio_flip_lock);
9501         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9502         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9503         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9504
9505         /*
9506          * Double check to catch cases where irq fired before
9507          * mmio flip data was ready
9508          */
9509         intel_notify_mmio_flip(obj->ring);
9510         return 0;
9511 }
9512
9513 static int intel_default_queue_flip(struct drm_device *dev,
9514                                     struct drm_crtc *crtc,
9515                                     struct drm_framebuffer *fb,
9516                                     struct drm_i915_gem_object *obj,
9517                                     struct intel_engine_cs *ring,
9518                                     uint32_t flags)
9519 {
9520         return -ENODEV;
9521 }
9522
9523 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9524                                          struct drm_crtc *crtc)
9525 {
9526         struct drm_i915_private *dev_priv = dev->dev_private;
9527         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9528         struct intel_unpin_work *work = intel_crtc->unpin_work;
9529         u32 addr;
9530
9531         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9532                 return true;
9533
9534         if (!work->enable_stall_check)
9535                 return false;
9536
9537         if (work->flip_ready_vblank == 0) {
9538                 if (work->flip_queued_ring &&
9539                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9540                                        work->flip_queued_seqno))
9541                         return false;
9542
9543                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9544         }
9545
9546         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9547                 return false;
9548
9549         /* Potential stall - if we see that the flip has happened,
9550          * assume a missed interrupt. */
9551         if (INTEL_INFO(dev)->gen >= 4)
9552                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9553         else
9554                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9555
9556         /* There is a potential issue here with a false positive after a flip
9557          * to the same address. We could address this by checking for a
9558          * non-incrementing frame counter.
9559          */
9560         return addr == work->gtt_offset;
9561 }
9562
9563 void intel_check_page_flip(struct drm_device *dev, int pipe)
9564 {
9565         struct drm_i915_private *dev_priv = dev->dev_private;
9566         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9568
9569         WARN_ON(!in_irq());
9570
9571         if (crtc == NULL)
9572                 return;
9573
9574         spin_lock(&dev->event_lock);
9575         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9576                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9577                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9578                 page_flip_completed(intel_crtc);
9579         }
9580         spin_unlock(&dev->event_lock);
9581 }
9582
9583 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9584                                 struct drm_framebuffer *fb,
9585                                 struct drm_pending_vblank_event *event,
9586                                 uint32_t page_flip_flags)
9587 {
9588         struct drm_device *dev = crtc->dev;
9589         struct drm_i915_private *dev_priv = dev->dev_private;
9590         struct drm_framebuffer *old_fb = crtc->primary->fb;
9591         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9593         enum pipe pipe = intel_crtc->pipe;
9594         struct intel_unpin_work *work;
9595         struct intel_engine_cs *ring;
9596         int ret;
9597
9598         /*
9599          * drm_mode_page_flip_ioctl() should already catch this, but double
9600          * check to be safe.  In the future we may enable pageflipping from
9601          * a disabled primary plane.
9602          */
9603         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9604                 return -EBUSY;
9605
9606         /* Can't change pixel format via MI display flips. */
9607         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9608                 return -EINVAL;
9609
9610         /*
9611          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9612          * Note that pitch changes could also affect these register.
9613          */
9614         if (INTEL_INFO(dev)->gen > 3 &&
9615             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9616              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9617                 return -EINVAL;
9618
9619         if (i915_terminally_wedged(&dev_priv->gpu_error))
9620                 goto out_hang;
9621
9622         work = kzalloc(sizeof(*work), GFP_KERNEL);
9623         if (work == NULL)
9624                 return -ENOMEM;
9625
9626         work->event = event;
9627         work->crtc = crtc;
9628         work->old_fb_obj = intel_fb_obj(old_fb);
9629         INIT_WORK(&work->work, intel_unpin_work_fn);
9630
9631         ret = drm_crtc_vblank_get(crtc);
9632         if (ret)
9633                 goto free_work;
9634
9635         /* We borrow the event spin lock for protecting unpin_work */
9636         spin_lock_irq(&dev->event_lock);
9637         if (intel_crtc->unpin_work) {
9638                 /* Before declaring the flip queue wedged, check if
9639                  * the hardware completed the operation behind our backs.
9640                  */
9641                 if (__intel_pageflip_stall_check(dev, crtc)) {
9642                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9643                         page_flip_completed(intel_crtc);
9644                 } else {
9645                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9646                         spin_unlock_irq(&dev->event_lock);
9647
9648                         drm_crtc_vblank_put(crtc);
9649                         kfree(work);
9650                         return -EBUSY;
9651                 }
9652         }
9653         intel_crtc->unpin_work = work;
9654         spin_unlock_irq(&dev->event_lock);
9655
9656         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9657                 flush_workqueue(dev_priv->wq);
9658
9659         ret = i915_mutex_lock_interruptible(dev);
9660         if (ret)
9661                 goto cleanup;
9662
9663         /* Reference the objects for the scheduled work. */
9664         drm_gem_object_reference(&work->old_fb_obj->base);
9665         drm_gem_object_reference(&obj->base);
9666
9667         crtc->primary->fb = fb;
9668
9669         work->pending_flip_obj = obj;
9670
9671         atomic_inc(&intel_crtc->unpin_work_count);
9672         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9673
9674         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9675                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9676
9677         if (IS_VALLEYVIEW(dev)) {
9678                 ring = &dev_priv->ring[BCS];
9679                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9680                         /* vlv: DISPLAY_FLIP fails to change tiling */
9681                         ring = NULL;
9682         } else if (IS_IVYBRIDGE(dev)) {
9683                 ring = &dev_priv->ring[BCS];
9684         } else if (INTEL_INFO(dev)->gen >= 7) {
9685                 ring = obj->ring;
9686                 if (ring == NULL || ring->id != RCS)
9687                         ring = &dev_priv->ring[BCS];
9688         } else {
9689                 ring = &dev_priv->ring[RCS];
9690         }
9691
9692         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9693         if (ret)
9694                 goto cleanup_pending;
9695
9696         work->gtt_offset =
9697                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9698
9699         if (use_mmio_flip(ring, obj)) {
9700                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9701                                             page_flip_flags);
9702                 if (ret)
9703                         goto cleanup_unpin;
9704
9705                 work->flip_queued_seqno = obj->last_write_seqno;
9706                 work->flip_queued_ring = obj->ring;
9707         } else {
9708                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9709                                                    page_flip_flags);
9710                 if (ret)
9711                         goto cleanup_unpin;
9712
9713                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9714                 work->flip_queued_ring = ring;
9715         }
9716
9717         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9718         work->enable_stall_check = true;
9719
9720         i915_gem_track_fb(work->old_fb_obj, obj,
9721                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9722
9723         intel_disable_fbc(dev);
9724         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9725         mutex_unlock(&dev->struct_mutex);
9726
9727         trace_i915_flip_request(intel_crtc->plane, obj);
9728
9729         return 0;
9730
9731 cleanup_unpin:
9732         intel_unpin_fb_obj(obj);
9733 cleanup_pending:
9734         atomic_dec(&intel_crtc->unpin_work_count);
9735         crtc->primary->fb = old_fb;
9736         drm_gem_object_unreference(&work->old_fb_obj->base);
9737         drm_gem_object_unreference(&obj->base);
9738         mutex_unlock(&dev->struct_mutex);
9739
9740 cleanup:
9741         spin_lock_irq(&dev->event_lock);
9742         intel_crtc->unpin_work = NULL;
9743         spin_unlock_irq(&dev->event_lock);
9744
9745         drm_crtc_vblank_put(crtc);
9746 free_work:
9747         kfree(work);
9748
9749         if (ret == -EIO) {
9750 out_hang:
9751                 intel_crtc_wait_for_pending_flips(crtc);
9752                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9753                 if (ret == 0 && event) {
9754                         spin_lock_irq(&dev->event_lock);
9755                         drm_send_vblank_event(dev, pipe, event);
9756                         spin_unlock_irq(&dev->event_lock);
9757                 }
9758         }
9759         return ret;
9760 }
9761
9762 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9763         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9764         .load_lut = intel_crtc_load_lut,
9765 };
9766
9767 /**
9768  * intel_modeset_update_staged_output_state
9769  *
9770  * Updates the staged output configuration state, e.g. after we've read out the
9771  * current hw state.
9772  */
9773 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9774 {
9775         struct intel_crtc *crtc;
9776         struct intel_encoder *encoder;
9777         struct intel_connector *connector;
9778
9779         list_for_each_entry(connector, &dev->mode_config.connector_list,
9780                             base.head) {
9781                 connector->new_encoder =
9782                         to_intel_encoder(connector->base.encoder);
9783         }
9784
9785         for_each_intel_encoder(dev, encoder) {
9786                 encoder->new_crtc =
9787                         to_intel_crtc(encoder->base.crtc);
9788         }
9789
9790         for_each_intel_crtc(dev, crtc) {
9791                 crtc->new_enabled = crtc->base.enabled;
9792
9793                 if (crtc->new_enabled)
9794                         crtc->new_config = &crtc->config;
9795                 else
9796                         crtc->new_config = NULL;
9797         }
9798 }
9799
9800 /**
9801  * intel_modeset_commit_output_state
9802  *
9803  * This function copies the stage display pipe configuration to the real one.
9804  */
9805 static void intel_modeset_commit_output_state(struct drm_device *dev)
9806 {
9807         struct intel_crtc *crtc;
9808         struct intel_encoder *encoder;
9809         struct intel_connector *connector;
9810
9811         list_for_each_entry(connector, &dev->mode_config.connector_list,
9812                             base.head) {
9813                 connector->base.encoder = &connector->new_encoder->base;
9814         }
9815
9816         for_each_intel_encoder(dev, encoder) {
9817                 encoder->base.crtc = &encoder->new_crtc->base;
9818         }
9819
9820         for_each_intel_crtc(dev, crtc) {
9821                 crtc->base.enabled = crtc->new_enabled;
9822         }
9823 }
9824
9825 static void
9826 connected_sink_compute_bpp(struct intel_connector *connector,
9827                            struct intel_crtc_config *pipe_config)
9828 {
9829         int bpp = pipe_config->pipe_bpp;
9830
9831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9832                 connector->base.base.id,
9833                 connector->base.name);
9834
9835         /* Don't use an invalid EDID bpc value */
9836         if (connector->base.display_info.bpc &&
9837             connector->base.display_info.bpc * 3 < bpp) {
9838                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9839                               bpp, connector->base.display_info.bpc*3);
9840                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9841         }
9842
9843         /* Clamp bpp to 8 on screens without EDID 1.4 */
9844         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9845                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9846                               bpp);
9847                 pipe_config->pipe_bpp = 24;
9848         }
9849 }
9850
9851 static int
9852 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9853                           struct drm_framebuffer *fb,
9854                           struct intel_crtc_config *pipe_config)
9855 {
9856         struct drm_device *dev = crtc->base.dev;
9857         struct intel_connector *connector;
9858         int bpp;
9859
9860         switch (fb->pixel_format) {
9861         case DRM_FORMAT_C8:
9862                 bpp = 8*3; /* since we go through a colormap */
9863                 break;
9864         case DRM_FORMAT_XRGB1555:
9865         case DRM_FORMAT_ARGB1555:
9866                 /* checked in intel_framebuffer_init already */
9867                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9868                         return -EINVAL;
9869         case DRM_FORMAT_RGB565:
9870                 bpp = 6*3; /* min is 18bpp */
9871                 break;
9872         case DRM_FORMAT_XBGR8888:
9873         case DRM_FORMAT_ABGR8888:
9874                 /* checked in intel_framebuffer_init already */
9875                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9876                         return -EINVAL;
9877         case DRM_FORMAT_XRGB8888:
9878         case DRM_FORMAT_ARGB8888:
9879                 bpp = 8*3;
9880                 break;
9881         case DRM_FORMAT_XRGB2101010:
9882         case DRM_FORMAT_ARGB2101010:
9883         case DRM_FORMAT_XBGR2101010:
9884         case DRM_FORMAT_ABGR2101010:
9885                 /* checked in intel_framebuffer_init already */
9886                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9887                         return -EINVAL;
9888                 bpp = 10*3;
9889                 break;
9890         /* TODO: gen4+ supports 16 bpc floating point, too. */
9891         default:
9892                 DRM_DEBUG_KMS("unsupported depth\n");
9893                 return -EINVAL;
9894         }
9895
9896         pipe_config->pipe_bpp = bpp;
9897
9898         /* Clamp display bpp to EDID value */
9899         list_for_each_entry(connector, &dev->mode_config.connector_list,
9900                             base.head) {
9901                 if (!connector->new_encoder ||
9902                     connector->new_encoder->new_crtc != crtc)
9903                         continue;
9904
9905                 connected_sink_compute_bpp(connector, pipe_config);
9906         }
9907
9908         return bpp;
9909 }
9910
9911 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9912 {
9913         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9914                         "type: 0x%x flags: 0x%x\n",
9915                 mode->crtc_clock,
9916                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9917                 mode->crtc_hsync_end, mode->crtc_htotal,
9918                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9919                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9920 }
9921
9922 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9923                                    struct intel_crtc_config *pipe_config,
9924                                    const char *context)
9925 {
9926         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9927                       context, pipe_name(crtc->pipe));
9928
9929         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9930         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9931                       pipe_config->pipe_bpp, pipe_config->dither);
9932         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9933                       pipe_config->has_pch_encoder,
9934                       pipe_config->fdi_lanes,
9935                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9936                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9937                       pipe_config->fdi_m_n.tu);
9938         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9939                       pipe_config->has_dp_encoder,
9940                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9941                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9942                       pipe_config->dp_m_n.tu);
9943
9944         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9945                       pipe_config->has_dp_encoder,
9946                       pipe_config->dp_m2_n2.gmch_m,
9947                       pipe_config->dp_m2_n2.gmch_n,
9948                       pipe_config->dp_m2_n2.link_m,
9949                       pipe_config->dp_m2_n2.link_n,
9950                       pipe_config->dp_m2_n2.tu);
9951
9952         DRM_DEBUG_KMS("requested mode:\n");
9953         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9954         DRM_DEBUG_KMS("adjusted mode:\n");
9955         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9956         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9957         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9958         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9959                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9960         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9961                       pipe_config->gmch_pfit.control,
9962                       pipe_config->gmch_pfit.pgm_ratios,
9963                       pipe_config->gmch_pfit.lvds_border_bits);
9964         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9965                       pipe_config->pch_pfit.pos,
9966                       pipe_config->pch_pfit.size,
9967                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9968         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9969         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9970 }
9971
9972 static bool encoders_cloneable(const struct intel_encoder *a,
9973                                const struct intel_encoder *b)
9974 {
9975         /* masks could be asymmetric, so check both ways */
9976         return a == b || (a->cloneable & (1 << b->type) &&
9977                           b->cloneable & (1 << a->type));
9978 }
9979
9980 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9981                                          struct intel_encoder *encoder)
9982 {
9983         struct drm_device *dev = crtc->base.dev;
9984         struct intel_encoder *source_encoder;
9985
9986         for_each_intel_encoder(dev, source_encoder) {
9987                 if (source_encoder->new_crtc != crtc)
9988                         continue;
9989
9990                 if (!encoders_cloneable(encoder, source_encoder))
9991                         return false;
9992         }
9993
9994         return true;
9995 }
9996
9997 static bool check_encoder_cloning(struct intel_crtc *crtc)
9998 {
9999         struct drm_device *dev = crtc->base.dev;
10000         struct intel_encoder *encoder;
10001
10002         for_each_intel_encoder(dev, encoder) {
10003                 if (encoder->new_crtc != crtc)
10004                         continue;
10005
10006                 if (!check_single_encoder_cloning(crtc, encoder))
10007                         return false;
10008         }
10009
10010         return true;
10011 }
10012
10013 static struct intel_crtc_config *
10014 intel_modeset_pipe_config(struct drm_crtc *crtc,
10015                           struct drm_framebuffer *fb,
10016                           struct drm_display_mode *mode)
10017 {
10018         struct drm_device *dev = crtc->dev;
10019         struct intel_encoder *encoder;
10020         struct intel_crtc_config *pipe_config;
10021         int plane_bpp, ret = -EINVAL;
10022         bool retry = true;
10023
10024         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10025                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10026                 return ERR_PTR(-EINVAL);
10027         }
10028
10029         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10030         if (!pipe_config)
10031                 return ERR_PTR(-ENOMEM);
10032
10033         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10034         drm_mode_copy(&pipe_config->requested_mode, mode);
10035
10036         pipe_config->cpu_transcoder =
10037                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10038         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10039
10040         /*
10041          * Sanitize sync polarity flags based on requested ones. If neither
10042          * positive or negative polarity is requested, treat this as meaning
10043          * negative polarity.
10044          */
10045         if (!(pipe_config->adjusted_mode.flags &
10046               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10047                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10048
10049         if (!(pipe_config->adjusted_mode.flags &
10050               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10051                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10052
10053         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10054          * plane pixel format and any sink constraints into account. Returns the
10055          * source plane bpp so that dithering can be selected on mismatches
10056          * after encoders and crtc also have had their say. */
10057         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10058                                               fb, pipe_config);
10059         if (plane_bpp < 0)
10060                 goto fail;
10061
10062         /*
10063          * Determine the real pipe dimensions. Note that stereo modes can
10064          * increase the actual pipe size due to the frame doubling and
10065          * insertion of additional space for blanks between the frame. This
10066          * is stored in the crtc timings. We use the requested mode to do this
10067          * computation to clearly distinguish it from the adjusted mode, which
10068          * can be changed by the connectors in the below retry loop.
10069          */
10070         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10071         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10072         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10073
10074 encoder_retry:
10075         /* Ensure the port clock defaults are reset when retrying. */
10076         pipe_config->port_clock = 0;
10077         pipe_config->pixel_multiplier = 1;
10078
10079         /* Fill in default crtc timings, allow encoders to overwrite them. */
10080         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10081
10082         /* Pass our mode to the connectors and the CRTC to give them a chance to
10083          * adjust it according to limitations or connector properties, and also
10084          * a chance to reject the mode entirely.
10085          */
10086         for_each_intel_encoder(dev, encoder) {
10087
10088                 if (&encoder->new_crtc->base != crtc)
10089                         continue;
10090
10091                 if (!(encoder->compute_config(encoder, pipe_config))) {
10092                         DRM_DEBUG_KMS("Encoder config failure\n");
10093                         goto fail;
10094                 }
10095         }
10096
10097         /* Set default port clock if not overwritten by the encoder. Needs to be
10098          * done afterwards in case the encoder adjusts the mode. */
10099         if (!pipe_config->port_clock)
10100                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10101                         * pipe_config->pixel_multiplier;
10102
10103         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10104         if (ret < 0) {
10105                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10106                 goto fail;
10107         }
10108
10109         if (ret == RETRY) {
10110                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10111                         ret = -EINVAL;
10112                         goto fail;
10113                 }
10114
10115                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10116                 retry = false;
10117                 goto encoder_retry;
10118         }
10119
10120         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10121         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10122                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10123
10124         return pipe_config;
10125 fail:
10126         kfree(pipe_config);
10127         return ERR_PTR(ret);
10128 }
10129
10130 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10131  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10132 static void
10133 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10134                              unsigned *prepare_pipes, unsigned *disable_pipes)
10135 {
10136         struct intel_crtc *intel_crtc;
10137         struct drm_device *dev = crtc->dev;
10138         struct intel_encoder *encoder;
10139         struct intel_connector *connector;
10140         struct drm_crtc *tmp_crtc;
10141
10142         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10143
10144         /* Check which crtcs have changed outputs connected to them, these need
10145          * to be part of the prepare_pipes mask. We don't (yet) support global
10146          * modeset across multiple crtcs, so modeset_pipes will only have one
10147          * bit set at most. */
10148         list_for_each_entry(connector, &dev->mode_config.connector_list,
10149                             base.head) {
10150                 if (connector->base.encoder == &connector->new_encoder->base)
10151                         continue;
10152
10153                 if (connector->base.encoder) {
10154                         tmp_crtc = connector->base.encoder->crtc;
10155
10156                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10157                 }
10158
10159                 if (connector->new_encoder)
10160                         *prepare_pipes |=
10161                                 1 << connector->new_encoder->new_crtc->pipe;
10162         }
10163
10164         for_each_intel_encoder(dev, encoder) {
10165                 if (encoder->base.crtc == &encoder->new_crtc->base)
10166                         continue;
10167
10168                 if (encoder->base.crtc) {
10169                         tmp_crtc = encoder->base.crtc;
10170
10171                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10172                 }
10173
10174                 if (encoder->new_crtc)
10175                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10176         }
10177
10178         /* Check for pipes that will be enabled/disabled ... */
10179         for_each_intel_crtc(dev, intel_crtc) {
10180                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10181                         continue;
10182
10183                 if (!intel_crtc->new_enabled)
10184                         *disable_pipes |= 1 << intel_crtc->pipe;
10185                 else
10186                         *prepare_pipes |= 1 << intel_crtc->pipe;
10187         }
10188
10189
10190         /* set_mode is also used to update properties on life display pipes. */
10191         intel_crtc = to_intel_crtc(crtc);
10192         if (intel_crtc->new_enabled)
10193                 *prepare_pipes |= 1 << intel_crtc->pipe;
10194
10195         /*
10196          * For simplicity do a full modeset on any pipe where the output routing
10197          * changed. We could be more clever, but that would require us to be
10198          * more careful with calling the relevant encoder->mode_set functions.
10199          */
10200         if (*prepare_pipes)
10201                 *modeset_pipes = *prepare_pipes;
10202
10203         /* ... and mask these out. */
10204         *modeset_pipes &= ~(*disable_pipes);
10205         *prepare_pipes &= ~(*disable_pipes);
10206
10207         /*
10208          * HACK: We don't (yet) fully support global modesets. intel_set_config
10209          * obies this rule, but the modeset restore mode of
10210          * intel_modeset_setup_hw_state does not.
10211          */
10212         *modeset_pipes &= 1 << intel_crtc->pipe;
10213         *prepare_pipes &= 1 << intel_crtc->pipe;
10214
10215         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10216                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10217 }
10218
10219 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10220 {
10221         struct drm_encoder *encoder;
10222         struct drm_device *dev = crtc->dev;
10223
10224         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10225                 if (encoder->crtc == crtc)
10226                         return true;
10227
10228         return false;
10229 }
10230
10231 static void
10232 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10233 {
10234         struct drm_i915_private *dev_priv = dev->dev_private;
10235         struct intel_encoder *intel_encoder;
10236         struct intel_crtc *intel_crtc;
10237         struct drm_connector *connector;
10238
10239         intel_shared_dpll_commit(dev_priv);
10240
10241         for_each_intel_encoder(dev, intel_encoder) {
10242                 if (!intel_encoder->base.crtc)
10243                         continue;
10244
10245                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10246
10247                 if (prepare_pipes & (1 << intel_crtc->pipe))
10248                         intel_encoder->connectors_active = false;
10249         }
10250
10251         intel_modeset_commit_output_state(dev);
10252
10253         /* Double check state. */
10254         for_each_intel_crtc(dev, intel_crtc) {
10255                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10256                 WARN_ON(intel_crtc->new_config &&
10257                         intel_crtc->new_config != &intel_crtc->config);
10258                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10259         }
10260
10261         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10262                 if (!connector->encoder || !connector->encoder->crtc)
10263                         continue;
10264
10265                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10266
10267                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10268                         struct drm_property *dpms_property =
10269                                 dev->mode_config.dpms_property;
10270
10271                         connector->dpms = DRM_MODE_DPMS_ON;
10272                         drm_object_property_set_value(&connector->base,
10273                                                          dpms_property,
10274                                                          DRM_MODE_DPMS_ON);
10275
10276                         intel_encoder = to_intel_encoder(connector->encoder);
10277                         intel_encoder->connectors_active = true;
10278                 }
10279         }
10280
10281 }
10282
10283 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10284 {
10285         int diff;
10286
10287         if (clock1 == clock2)
10288                 return true;
10289
10290         if (!clock1 || !clock2)
10291                 return false;
10292
10293         diff = abs(clock1 - clock2);
10294
10295         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10296                 return true;
10297
10298         return false;
10299 }
10300
10301 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10302         list_for_each_entry((intel_crtc), \
10303                             &(dev)->mode_config.crtc_list, \
10304                             base.head) \
10305                 if (mask & (1 <<(intel_crtc)->pipe))
10306
10307 static bool
10308 intel_pipe_config_compare(struct drm_device *dev,
10309                           struct intel_crtc_config *current_config,
10310                           struct intel_crtc_config *pipe_config)
10311 {
10312 #define PIPE_CONF_CHECK_X(name) \
10313         if (current_config->name != pipe_config->name) { \
10314                 DRM_ERROR("mismatch in " #name " " \
10315                           "(expected 0x%08x, found 0x%08x)\n", \
10316                           current_config->name, \
10317                           pipe_config->name); \
10318                 return false; \
10319         }
10320
10321 #define PIPE_CONF_CHECK_I(name) \
10322         if (current_config->name != pipe_config->name) { \
10323                 DRM_ERROR("mismatch in " #name " " \
10324                           "(expected %i, found %i)\n", \
10325                           current_config->name, \
10326                           pipe_config->name); \
10327                 return false; \
10328         }
10329
10330 /* This is required for BDW+ where there is only one set of registers for
10331  * switching between high and low RR.
10332  * This macro can be used whenever a comparison has to be made between one
10333  * hw state and multiple sw state variables.
10334  */
10335 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10336         if ((current_config->name != pipe_config->name) && \
10337                 (current_config->alt_name != pipe_config->name)) { \
10338                         DRM_ERROR("mismatch in " #name " " \
10339                                   "(expected %i or %i, found %i)\n", \
10340                                   current_config->name, \
10341                                   current_config->alt_name, \
10342                                   pipe_config->name); \
10343                         return false; \
10344         }
10345
10346 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10347         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10348                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10349                           "(expected %i, found %i)\n", \
10350                           current_config->name & (mask), \
10351                           pipe_config->name & (mask)); \
10352                 return false; \
10353         }
10354
10355 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10356         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10357                 DRM_ERROR("mismatch in " #name " " \
10358                           "(expected %i, found %i)\n", \
10359                           current_config->name, \
10360                           pipe_config->name); \
10361                 return false; \
10362         }
10363
10364 #define PIPE_CONF_QUIRK(quirk)  \
10365         ((current_config->quirks | pipe_config->quirks) & (quirk))
10366
10367         PIPE_CONF_CHECK_I(cpu_transcoder);
10368
10369         PIPE_CONF_CHECK_I(has_pch_encoder);
10370         PIPE_CONF_CHECK_I(fdi_lanes);
10371         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10372         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10373         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10374         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10375         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10376
10377         PIPE_CONF_CHECK_I(has_dp_encoder);
10378
10379         if (INTEL_INFO(dev)->gen < 8) {
10380                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10381                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10382                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10383                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10384                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10385
10386                 if (current_config->has_drrs) {
10387                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10388                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10389                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10390                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10391                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10392                 }
10393         } else {
10394                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10395                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10396                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10397                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10398                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10399         }
10400
10401         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10402         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10403         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10404         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10405         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10406         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10407
10408         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10409         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10410         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10411         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10412         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10413         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10414
10415         PIPE_CONF_CHECK_I(pixel_multiplier);
10416         PIPE_CONF_CHECK_I(has_hdmi_sink);
10417         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10418             IS_VALLEYVIEW(dev))
10419                 PIPE_CONF_CHECK_I(limited_color_range);
10420
10421         PIPE_CONF_CHECK_I(has_audio);
10422
10423         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10424                               DRM_MODE_FLAG_INTERLACE);
10425
10426         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10427                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10428                                       DRM_MODE_FLAG_PHSYNC);
10429                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10430                                       DRM_MODE_FLAG_NHSYNC);
10431                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10432                                       DRM_MODE_FLAG_PVSYNC);
10433                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10434                                       DRM_MODE_FLAG_NVSYNC);
10435         }
10436
10437         PIPE_CONF_CHECK_I(pipe_src_w);
10438         PIPE_CONF_CHECK_I(pipe_src_h);
10439
10440         /*
10441          * FIXME: BIOS likes to set up a cloned config with lvds+external
10442          * screen. Since we don't yet re-compute the pipe config when moving
10443          * just the lvds port away to another pipe the sw tracking won't match.
10444          *
10445          * Proper atomic modesets with recomputed global state will fix this.
10446          * Until then just don't check gmch state for inherited modes.
10447          */
10448         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10449                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10450                 /* pfit ratios are autocomputed by the hw on gen4+ */
10451                 if (INTEL_INFO(dev)->gen < 4)
10452                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10453                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10454         }
10455
10456         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10457         if (current_config->pch_pfit.enabled) {
10458                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10459                 PIPE_CONF_CHECK_I(pch_pfit.size);
10460         }
10461
10462         /* BDW+ don't expose a synchronous way to read the state */
10463         if (IS_HASWELL(dev))
10464                 PIPE_CONF_CHECK_I(ips_enabled);
10465
10466         PIPE_CONF_CHECK_I(double_wide);
10467
10468         PIPE_CONF_CHECK_X(ddi_pll_sel);
10469
10470         PIPE_CONF_CHECK_I(shared_dpll);
10471         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10472         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10473         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10474         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10475         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10476
10477         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10478                 PIPE_CONF_CHECK_I(pipe_bpp);
10479
10480         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10481         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10482
10483 #undef PIPE_CONF_CHECK_X
10484 #undef PIPE_CONF_CHECK_I
10485 #undef PIPE_CONF_CHECK_I_ALT
10486 #undef PIPE_CONF_CHECK_FLAGS
10487 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10488 #undef PIPE_CONF_QUIRK
10489
10490         return true;
10491 }
10492
10493 static void
10494 check_connector_state(struct drm_device *dev)
10495 {
10496         struct intel_connector *connector;
10497
10498         list_for_each_entry(connector, &dev->mode_config.connector_list,
10499                             base.head) {
10500                 /* This also checks the encoder/connector hw state with the
10501                  * ->get_hw_state callbacks. */
10502                 intel_connector_check_state(connector);
10503
10504                 WARN(&connector->new_encoder->base != connector->base.encoder,
10505                      "connector's staged encoder doesn't match current encoder\n");
10506         }
10507 }
10508
10509 static void
10510 check_encoder_state(struct drm_device *dev)
10511 {
10512         struct intel_encoder *encoder;
10513         struct intel_connector *connector;
10514
10515         for_each_intel_encoder(dev, encoder) {
10516                 bool enabled = false;
10517                 bool active = false;
10518                 enum pipe pipe, tracked_pipe;
10519
10520                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10521                               encoder->base.base.id,
10522                               encoder->base.name);
10523
10524                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10525                      "encoder's stage crtc doesn't match current crtc\n");
10526                 WARN(encoder->connectors_active && !encoder->base.crtc,
10527                      "encoder's active_connectors set, but no crtc\n");
10528
10529                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10530                                     base.head) {
10531                         if (connector->base.encoder != &encoder->base)
10532                                 continue;
10533                         enabled = true;
10534                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10535                                 active = true;
10536                 }
10537                 /*
10538                  * for MST connectors if we unplug the connector is gone
10539                  * away but the encoder is still connected to a crtc
10540                  * until a modeset happens in response to the hotplug.
10541                  */
10542                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10543                         continue;
10544
10545                 WARN(!!encoder->base.crtc != enabled,
10546                      "encoder's enabled state mismatch "
10547                      "(expected %i, found %i)\n",
10548                      !!encoder->base.crtc, enabled);
10549                 WARN(active && !encoder->base.crtc,
10550                      "active encoder with no crtc\n");
10551
10552                 WARN(encoder->connectors_active != active,
10553                      "encoder's computed active state doesn't match tracked active state "
10554                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10555
10556                 active = encoder->get_hw_state(encoder, &pipe);
10557                 WARN(active != encoder->connectors_active,
10558                      "encoder's hw state doesn't match sw tracking "
10559                      "(expected %i, found %i)\n",
10560                      encoder->connectors_active, active);
10561
10562                 if (!encoder->base.crtc)
10563                         continue;
10564
10565                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10566                 WARN(active && pipe != tracked_pipe,
10567                      "active encoder's pipe doesn't match"
10568                      "(expected %i, found %i)\n",
10569                      tracked_pipe, pipe);
10570
10571         }
10572 }
10573
10574 static void
10575 check_crtc_state(struct drm_device *dev)
10576 {
10577         struct drm_i915_private *dev_priv = dev->dev_private;
10578         struct intel_crtc *crtc;
10579         struct intel_encoder *encoder;
10580         struct intel_crtc_config pipe_config;
10581
10582         for_each_intel_crtc(dev, crtc) {
10583                 bool enabled = false;
10584                 bool active = false;
10585
10586                 memset(&pipe_config, 0, sizeof(pipe_config));
10587
10588                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10589                               crtc->base.base.id);
10590
10591                 WARN(crtc->active && !crtc->base.enabled,
10592                      "active crtc, but not enabled in sw tracking\n");
10593
10594                 for_each_intel_encoder(dev, encoder) {
10595                         if (encoder->base.crtc != &crtc->base)
10596                                 continue;
10597                         enabled = true;
10598                         if (encoder->connectors_active)
10599                                 active = true;
10600                 }
10601
10602                 WARN(active != crtc->active,
10603                      "crtc's computed active state doesn't match tracked active state "
10604                      "(expected %i, found %i)\n", active, crtc->active);
10605                 WARN(enabled != crtc->base.enabled,
10606                      "crtc's computed enabled state doesn't match tracked enabled state "
10607                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10608
10609                 active = dev_priv->display.get_pipe_config(crtc,
10610                                                            &pipe_config);
10611
10612                 /* hw state is inconsistent with the pipe quirk */
10613                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10614                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10615                         active = crtc->active;
10616
10617                 for_each_intel_encoder(dev, encoder) {
10618                         enum pipe pipe;
10619                         if (encoder->base.crtc != &crtc->base)
10620                                 continue;
10621                         if (encoder->get_hw_state(encoder, &pipe))
10622                                 encoder->get_config(encoder, &pipe_config);
10623                 }
10624
10625                 WARN(crtc->active != active,
10626                      "crtc active state doesn't match with hw state "
10627                      "(expected %i, found %i)\n", crtc->active, active);
10628
10629                 if (active &&
10630                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10631                         WARN(1, "pipe state doesn't match!\n");
10632                         intel_dump_pipe_config(crtc, &pipe_config,
10633                                                "[hw state]");
10634                         intel_dump_pipe_config(crtc, &crtc->config,
10635                                                "[sw state]");
10636                 }
10637         }
10638 }
10639
10640 static void
10641 check_shared_dpll_state(struct drm_device *dev)
10642 {
10643         struct drm_i915_private *dev_priv = dev->dev_private;
10644         struct intel_crtc *crtc;
10645         struct intel_dpll_hw_state dpll_hw_state;
10646         int i;
10647
10648         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10649                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10650                 int enabled_crtcs = 0, active_crtcs = 0;
10651                 bool active;
10652
10653                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10654
10655                 DRM_DEBUG_KMS("%s\n", pll->name);
10656
10657                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10658
10659                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10660                      "more active pll users than references: %i vs %i\n",
10661                      pll->active, hweight32(pll->config.crtc_mask));
10662                 WARN(pll->active && !pll->on,
10663                      "pll in active use but not on in sw tracking\n");
10664                 WARN(pll->on && !pll->active,
10665                      "pll in on but not on in use in sw tracking\n");
10666                 WARN(pll->on != active,
10667                      "pll on state mismatch (expected %i, found %i)\n",
10668                      pll->on, active);
10669
10670                 for_each_intel_crtc(dev, crtc) {
10671                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10672                                 enabled_crtcs++;
10673                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10674                                 active_crtcs++;
10675                 }
10676                 WARN(pll->active != active_crtcs,
10677                      "pll active crtcs mismatch (expected %i, found %i)\n",
10678                      pll->active, active_crtcs);
10679                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10680                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10681                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10682
10683                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10684                                        sizeof(dpll_hw_state)),
10685                      "pll hw state mismatch\n");
10686         }
10687 }
10688
10689 void
10690 intel_modeset_check_state(struct drm_device *dev)
10691 {
10692         check_connector_state(dev);
10693         check_encoder_state(dev);
10694         check_crtc_state(dev);
10695         check_shared_dpll_state(dev);
10696 }
10697
10698 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10699                                      int dotclock)
10700 {
10701         /*
10702          * FDI already provided one idea for the dotclock.
10703          * Yell if the encoder disagrees.
10704          */
10705         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10706              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10707              pipe_config->adjusted_mode.crtc_clock, dotclock);
10708 }
10709
10710 static void update_scanline_offset(struct intel_crtc *crtc)
10711 {
10712         struct drm_device *dev = crtc->base.dev;
10713
10714         /*
10715          * The scanline counter increments at the leading edge of hsync.
10716          *
10717          * On most platforms it starts counting from vtotal-1 on the
10718          * first active line. That means the scanline counter value is
10719          * always one less than what we would expect. Ie. just after
10720          * start of vblank, which also occurs at start of hsync (on the
10721          * last active line), the scanline counter will read vblank_start-1.
10722          *
10723          * On gen2 the scanline counter starts counting from 1 instead
10724          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10725          * to keep the value positive), instead of adding one.
10726          *
10727          * On HSW+ the behaviour of the scanline counter depends on the output
10728          * type. For DP ports it behaves like most other platforms, but on HDMI
10729          * there's an extra 1 line difference. So we need to add two instead of
10730          * one to the value.
10731          */
10732         if (IS_GEN2(dev)) {
10733                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10734                 int vtotal;
10735
10736                 vtotal = mode->crtc_vtotal;
10737                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10738                         vtotal /= 2;
10739
10740                 crtc->scanline_offset = vtotal - 1;
10741         } else if (HAS_DDI(dev) &&
10742                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10743                 crtc->scanline_offset = 2;
10744         } else
10745                 crtc->scanline_offset = 1;
10746 }
10747
10748 static int __intel_set_mode(struct drm_crtc *crtc,
10749                             struct drm_display_mode *mode,
10750                             int x, int y, struct drm_framebuffer *fb)
10751 {
10752         struct drm_device *dev = crtc->dev;
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754         struct drm_display_mode *saved_mode;
10755         struct intel_crtc_config *pipe_config = NULL;
10756         struct intel_crtc *intel_crtc;
10757         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10758         int ret = 0;
10759
10760         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10761         if (!saved_mode)
10762                 return -ENOMEM;
10763
10764         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10765                                      &prepare_pipes, &disable_pipes);
10766
10767         *saved_mode = crtc->mode;
10768
10769         /* Hack: Because we don't (yet) support global modeset on multiple
10770          * crtcs, we don't keep track of the new mode for more than one crtc.
10771          * Hence simply check whether any bit is set in modeset_pipes in all the
10772          * pieces of code that are not yet converted to deal with mutliple crtcs
10773          * changing their mode at the same time. */
10774         if (modeset_pipes) {
10775                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10776                 if (IS_ERR(pipe_config)) {
10777                         ret = PTR_ERR(pipe_config);
10778                         pipe_config = NULL;
10779
10780                         goto out;
10781                 }
10782                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10783                                        "[modeset]");
10784                 to_intel_crtc(crtc)->new_config = pipe_config;
10785         }
10786
10787         /*
10788          * See if the config requires any additional preparation, e.g.
10789          * to adjust global state with pipes off.  We need to do this
10790          * here so we can get the modeset_pipe updated config for the new
10791          * mode set on this crtc.  For other crtcs we need to use the
10792          * adjusted_mode bits in the crtc directly.
10793          */
10794         if (IS_VALLEYVIEW(dev)) {
10795                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10796
10797                 /* may have added more to prepare_pipes than we should */
10798                 prepare_pipes &= ~disable_pipes;
10799         }
10800
10801         if (dev_priv->display.crtc_compute_clock) {
10802                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10803
10804                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10805                 if (ret)
10806                         goto done;
10807
10808                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10809                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10810                         if (ret) {
10811                                 intel_shared_dpll_abort_config(dev_priv);
10812                                 goto done;
10813                         }
10814                 }
10815         }
10816
10817         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10818                 intel_crtc_disable(&intel_crtc->base);
10819
10820         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10821                 if (intel_crtc->base.enabled)
10822                         dev_priv->display.crtc_disable(&intel_crtc->base);
10823         }
10824
10825         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10826          * to set it here already despite that we pass it down the callchain.
10827          */
10828         if (modeset_pipes) {
10829                 crtc->mode = *mode;
10830                 /* mode_set/enable/disable functions rely on a correct pipe
10831                  * config. */
10832                 to_intel_crtc(crtc)->config = *pipe_config;
10833                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10834
10835                 /*
10836                  * Calculate and store various constants which
10837                  * are later needed by vblank and swap-completion
10838                  * timestamping. They are derived from true hwmode.
10839                  */
10840                 drm_calc_timestamping_constants(crtc,
10841                                                 &pipe_config->adjusted_mode);
10842         }
10843
10844         /* Only after disabling all output pipelines that will be changed can we
10845          * update the the output configuration. */
10846         intel_modeset_update_state(dev, prepare_pipes);
10847
10848         if (dev_priv->display.modeset_global_resources)
10849                 dev_priv->display.modeset_global_resources(dev);
10850
10851         /* Set up the DPLL and any encoders state that needs to adjust or depend
10852          * on the DPLL.
10853          */
10854         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10855                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10856                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10857                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10858
10859                 mutex_lock(&dev->struct_mutex);
10860                 ret = intel_pin_and_fence_fb_obj(dev,
10861                                                  obj,
10862                                                  NULL);
10863                 if (ret != 0) {
10864                         DRM_ERROR("pin & fence failed\n");
10865                         mutex_unlock(&dev->struct_mutex);
10866                         goto done;
10867                 }
10868                 if (old_fb)
10869                         intel_unpin_fb_obj(old_obj);
10870                 i915_gem_track_fb(old_obj, obj,
10871                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10872                 mutex_unlock(&dev->struct_mutex);
10873
10874                 crtc->primary->fb = fb;
10875                 crtc->x = x;
10876                 crtc->y = y;
10877         }
10878
10879         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10880         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10881                 update_scanline_offset(intel_crtc);
10882
10883                 dev_priv->display.crtc_enable(&intel_crtc->base);
10884         }
10885
10886         /* FIXME: add subpixel order */
10887 done:
10888         if (ret && crtc->enabled)
10889                 crtc->mode = *saved_mode;
10890
10891 out:
10892         kfree(pipe_config);
10893         kfree(saved_mode);
10894         return ret;
10895 }
10896
10897 static int intel_set_mode(struct drm_crtc *crtc,
10898                           struct drm_display_mode *mode,
10899                           int x, int y, struct drm_framebuffer *fb)
10900 {
10901         int ret;
10902
10903         ret = __intel_set_mode(crtc, mode, x, y, fb);
10904
10905         if (ret == 0)
10906                 intel_modeset_check_state(crtc->dev);
10907
10908         return ret;
10909 }
10910
10911 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10912 {
10913         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10914 }
10915
10916 #undef for_each_intel_crtc_masked
10917
10918 static void intel_set_config_free(struct intel_set_config *config)
10919 {
10920         if (!config)
10921                 return;
10922
10923         kfree(config->save_connector_encoders);
10924         kfree(config->save_encoder_crtcs);
10925         kfree(config->save_crtc_enabled);
10926         kfree(config);
10927 }
10928
10929 static int intel_set_config_save_state(struct drm_device *dev,
10930                                        struct intel_set_config *config)
10931 {
10932         struct drm_crtc *crtc;
10933         struct drm_encoder *encoder;
10934         struct drm_connector *connector;
10935         int count;
10936
10937         config->save_crtc_enabled =
10938                 kcalloc(dev->mode_config.num_crtc,
10939                         sizeof(bool), GFP_KERNEL);
10940         if (!config->save_crtc_enabled)
10941                 return -ENOMEM;
10942
10943         config->save_encoder_crtcs =
10944                 kcalloc(dev->mode_config.num_encoder,
10945                         sizeof(struct drm_crtc *), GFP_KERNEL);
10946         if (!config->save_encoder_crtcs)
10947                 return -ENOMEM;
10948
10949         config->save_connector_encoders =
10950                 kcalloc(dev->mode_config.num_connector,
10951                         sizeof(struct drm_encoder *), GFP_KERNEL);
10952         if (!config->save_connector_encoders)
10953                 return -ENOMEM;
10954
10955         /* Copy data. Note that driver private data is not affected.
10956          * Should anything bad happen only the expected state is
10957          * restored, not the drivers personal bookkeeping.
10958          */
10959         count = 0;
10960         for_each_crtc(dev, crtc) {
10961                 config->save_crtc_enabled[count++] = crtc->enabled;
10962         }
10963
10964         count = 0;
10965         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10966                 config->save_encoder_crtcs[count++] = encoder->crtc;
10967         }
10968
10969         count = 0;
10970         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10971                 config->save_connector_encoders[count++] = connector->encoder;
10972         }
10973
10974         return 0;
10975 }
10976
10977 static void intel_set_config_restore_state(struct drm_device *dev,
10978                                            struct intel_set_config *config)
10979 {
10980         struct intel_crtc *crtc;
10981         struct intel_encoder *encoder;
10982         struct intel_connector *connector;
10983         int count;
10984
10985         count = 0;
10986         for_each_intel_crtc(dev, crtc) {
10987                 crtc->new_enabled = config->save_crtc_enabled[count++];
10988
10989                 if (crtc->new_enabled)
10990                         crtc->new_config = &crtc->config;
10991                 else
10992                         crtc->new_config = NULL;
10993         }
10994
10995         count = 0;
10996         for_each_intel_encoder(dev, encoder) {
10997                 encoder->new_crtc =
10998                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10999         }
11000
11001         count = 0;
11002         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11003                 connector->new_encoder =
11004                         to_intel_encoder(config->save_connector_encoders[count++]);
11005         }
11006 }
11007
11008 static bool
11009 is_crtc_connector_off(struct drm_mode_set *set)
11010 {
11011         int i;
11012
11013         if (set->num_connectors == 0)
11014                 return false;
11015
11016         if (WARN_ON(set->connectors == NULL))
11017                 return false;
11018
11019         for (i = 0; i < set->num_connectors; i++)
11020                 if (set->connectors[i]->encoder &&
11021                     set->connectors[i]->encoder->crtc == set->crtc &&
11022                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11023                         return true;
11024
11025         return false;
11026 }
11027
11028 static void
11029 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11030                                       struct intel_set_config *config)
11031 {
11032
11033         /* We should be able to check here if the fb has the same properties
11034          * and then just flip_or_move it */
11035         if (is_crtc_connector_off(set)) {
11036                 config->mode_changed = true;
11037         } else if (set->crtc->primary->fb != set->fb) {
11038                 /*
11039                  * If we have no fb, we can only flip as long as the crtc is
11040                  * active, otherwise we need a full mode set.  The crtc may
11041                  * be active if we've only disabled the primary plane, or
11042                  * in fastboot situations.
11043                  */
11044                 if (set->crtc->primary->fb == NULL) {
11045                         struct intel_crtc *intel_crtc =
11046                                 to_intel_crtc(set->crtc);
11047
11048                         if (intel_crtc->active) {
11049                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11050                                 config->fb_changed = true;
11051                         } else {
11052                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11053                                 config->mode_changed = true;
11054                         }
11055                 } else if (set->fb == NULL) {
11056                         config->mode_changed = true;
11057                 } else if (set->fb->pixel_format !=
11058                            set->crtc->primary->fb->pixel_format) {
11059                         config->mode_changed = true;
11060                 } else {
11061                         config->fb_changed = true;
11062                 }
11063         }
11064
11065         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11066                 config->fb_changed = true;
11067
11068         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11069                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11070                 drm_mode_debug_printmodeline(&set->crtc->mode);
11071                 drm_mode_debug_printmodeline(set->mode);
11072                 config->mode_changed = true;
11073         }
11074
11075         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11076                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11077 }
11078
11079 static int
11080 intel_modeset_stage_output_state(struct drm_device *dev,
11081                                  struct drm_mode_set *set,
11082                                  struct intel_set_config *config)
11083 {
11084         struct intel_connector *connector;
11085         struct intel_encoder *encoder;
11086         struct intel_crtc *crtc;
11087         int ro;
11088
11089         /* The upper layers ensure that we either disable a crtc or have a list
11090          * of connectors. For paranoia, double-check this. */
11091         WARN_ON(!set->fb && (set->num_connectors != 0));
11092         WARN_ON(set->fb && (set->num_connectors == 0));
11093
11094         list_for_each_entry(connector, &dev->mode_config.connector_list,
11095                             base.head) {
11096                 /* Otherwise traverse passed in connector list and get encoders
11097                  * for them. */
11098                 for (ro = 0; ro < set->num_connectors; ro++) {
11099                         if (set->connectors[ro] == &connector->base) {
11100                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11101                                 break;
11102                         }
11103                 }
11104
11105                 /* If we disable the crtc, disable all its connectors. Also, if
11106                  * the connector is on the changing crtc but not on the new
11107                  * connector list, disable it. */
11108                 if ((!set->fb || ro == set->num_connectors) &&
11109                     connector->base.encoder &&
11110                     connector->base.encoder->crtc == set->crtc) {
11111                         connector->new_encoder = NULL;
11112
11113                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11114                                 connector->base.base.id,
11115                                 connector->base.name);
11116                 }
11117
11118
11119                 if (&connector->new_encoder->base != connector->base.encoder) {
11120                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11121                         config->mode_changed = true;
11122                 }
11123         }
11124         /* connector->new_encoder is now updated for all connectors. */
11125
11126         /* Update crtc of enabled connectors. */
11127         list_for_each_entry(connector, &dev->mode_config.connector_list,
11128                             base.head) {
11129                 struct drm_crtc *new_crtc;
11130
11131                 if (!connector->new_encoder)
11132                         continue;
11133
11134                 new_crtc = connector->new_encoder->base.crtc;
11135
11136                 for (ro = 0; ro < set->num_connectors; ro++) {
11137                         if (set->connectors[ro] == &connector->base)
11138                                 new_crtc = set->crtc;
11139                 }
11140
11141                 /* Make sure the new CRTC will work with the encoder */
11142                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11143                                          new_crtc)) {
11144                         return -EINVAL;
11145                 }
11146                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11147
11148                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11149                         connector->base.base.id,
11150                         connector->base.name,
11151                         new_crtc->base.id);
11152         }
11153
11154         /* Check for any encoders that needs to be disabled. */
11155         for_each_intel_encoder(dev, encoder) {
11156                 int num_connectors = 0;
11157                 list_for_each_entry(connector,
11158                                     &dev->mode_config.connector_list,
11159                                     base.head) {
11160                         if (connector->new_encoder == encoder) {
11161                                 WARN_ON(!connector->new_encoder->new_crtc);
11162                                 num_connectors++;
11163                         }
11164                 }
11165
11166                 if (num_connectors == 0)
11167                         encoder->new_crtc = NULL;
11168                 else if (num_connectors > 1)
11169                         return -EINVAL;
11170
11171                 /* Only now check for crtc changes so we don't miss encoders
11172                  * that will be disabled. */
11173                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11174                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11175                         config->mode_changed = true;
11176                 }
11177         }
11178         /* Now we've also updated encoder->new_crtc for all encoders. */
11179         list_for_each_entry(connector, &dev->mode_config.connector_list,
11180                             base.head) {
11181                 if (connector->new_encoder)
11182                         if (connector->new_encoder != connector->encoder)
11183                                 connector->encoder = connector->new_encoder;
11184         }
11185         for_each_intel_crtc(dev, crtc) {
11186                 crtc->new_enabled = false;
11187
11188                 for_each_intel_encoder(dev, encoder) {
11189                         if (encoder->new_crtc == crtc) {
11190                                 crtc->new_enabled = true;
11191                                 break;
11192                         }
11193                 }
11194
11195                 if (crtc->new_enabled != crtc->base.enabled) {
11196                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11197                                       crtc->new_enabled ? "en" : "dis");
11198                         config->mode_changed = true;
11199                 }
11200
11201                 if (crtc->new_enabled)
11202                         crtc->new_config = &crtc->config;
11203                 else
11204                         crtc->new_config = NULL;
11205         }
11206
11207         return 0;
11208 }
11209
11210 static void disable_crtc_nofb(struct intel_crtc *crtc)
11211 {
11212         struct drm_device *dev = crtc->base.dev;
11213         struct intel_encoder *encoder;
11214         struct intel_connector *connector;
11215
11216         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11217                       pipe_name(crtc->pipe));
11218
11219         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11220                 if (connector->new_encoder &&
11221                     connector->new_encoder->new_crtc == crtc)
11222                         connector->new_encoder = NULL;
11223         }
11224
11225         for_each_intel_encoder(dev, encoder) {
11226                 if (encoder->new_crtc == crtc)
11227                         encoder->new_crtc = NULL;
11228         }
11229
11230         crtc->new_enabled = false;
11231         crtc->new_config = NULL;
11232 }
11233
11234 static int intel_crtc_set_config(struct drm_mode_set *set)
11235 {
11236         struct drm_device *dev;
11237         struct drm_mode_set save_set;
11238         struct intel_set_config *config;
11239         int ret;
11240
11241         BUG_ON(!set);
11242         BUG_ON(!set->crtc);
11243         BUG_ON(!set->crtc->helper_private);
11244
11245         /* Enforce sane interface api - has been abused by the fb helper. */
11246         BUG_ON(!set->mode && set->fb);
11247         BUG_ON(set->fb && set->num_connectors == 0);
11248
11249         if (set->fb) {
11250                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11251                                 set->crtc->base.id, set->fb->base.id,
11252                                 (int)set->num_connectors, set->x, set->y);
11253         } else {
11254                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11255         }
11256
11257         dev = set->crtc->dev;
11258
11259         ret = -ENOMEM;
11260         config = kzalloc(sizeof(*config), GFP_KERNEL);
11261         if (!config)
11262                 goto out_config;
11263
11264         ret = intel_set_config_save_state(dev, config);
11265         if (ret)
11266                 goto out_config;
11267
11268         save_set.crtc = set->crtc;
11269         save_set.mode = &set->crtc->mode;
11270         save_set.x = set->crtc->x;
11271         save_set.y = set->crtc->y;
11272         save_set.fb = set->crtc->primary->fb;
11273
11274         /* Compute whether we need a full modeset, only an fb base update or no
11275          * change at all. In the future we might also check whether only the
11276          * mode changed, e.g. for LVDS where we only change the panel fitter in
11277          * such cases. */
11278         intel_set_config_compute_mode_changes(set, config);
11279
11280         ret = intel_modeset_stage_output_state(dev, set, config);
11281         if (ret)
11282                 goto fail;
11283
11284         if (config->mode_changed) {
11285                 ret = intel_set_mode(set->crtc, set->mode,
11286                                      set->x, set->y, set->fb);
11287         } else if (config->fb_changed) {
11288                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11289
11290                 intel_crtc_wait_for_pending_flips(set->crtc);
11291
11292                 ret = intel_pipe_set_base(set->crtc,
11293                                           set->x, set->y, set->fb);
11294
11295                 /*
11296                  * We need to make sure the primary plane is re-enabled if it
11297                  * has previously been turned off.
11298                  */
11299                 if (!intel_crtc->primary_enabled && ret == 0) {
11300                         WARN_ON(!intel_crtc->active);
11301                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11302                 }
11303
11304                 /*
11305                  * In the fastboot case this may be our only check of the
11306                  * state after boot.  It would be better to only do it on
11307                  * the first update, but we don't have a nice way of doing that
11308                  * (and really, set_config isn't used much for high freq page
11309                  * flipping, so increasing its cost here shouldn't be a big
11310                  * deal).
11311                  */
11312                 if (i915.fastboot && ret == 0)
11313                         intel_modeset_check_state(set->crtc->dev);
11314         }
11315
11316         if (ret) {
11317                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11318                               set->crtc->base.id, ret);
11319 fail:
11320                 intel_set_config_restore_state(dev, config);
11321
11322                 /*
11323                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11324                  * force the pipe off to avoid oopsing in the modeset code
11325                  * due to fb==NULL. This should only happen during boot since
11326                  * we don't yet reconstruct the FB from the hardware state.
11327                  */
11328                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11329                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11330
11331                 /* Try to restore the config */
11332                 if (config->mode_changed &&
11333                     intel_set_mode(save_set.crtc, save_set.mode,
11334                                    save_set.x, save_set.y, save_set.fb))
11335                         DRM_ERROR("failed to restore config after modeset failure\n");
11336         }
11337
11338 out_config:
11339         intel_set_config_free(config);
11340         return ret;
11341 }
11342
11343 static const struct drm_crtc_funcs intel_crtc_funcs = {
11344         .gamma_set = intel_crtc_gamma_set,
11345         .set_config = intel_crtc_set_config,
11346         .destroy = intel_crtc_destroy,
11347         .page_flip = intel_crtc_page_flip,
11348 };
11349
11350 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11351                                       struct intel_shared_dpll *pll,
11352                                       struct intel_dpll_hw_state *hw_state)
11353 {
11354         uint32_t val;
11355
11356         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11357                 return false;
11358
11359         val = I915_READ(PCH_DPLL(pll->id));
11360         hw_state->dpll = val;
11361         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11362         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11363
11364         return val & DPLL_VCO_ENABLE;
11365 }
11366
11367 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11368                                   struct intel_shared_dpll *pll)
11369 {
11370         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11371         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11372 }
11373
11374 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11375                                 struct intel_shared_dpll *pll)
11376 {
11377         /* PCH refclock must be enabled first */
11378         ibx_assert_pch_refclk_enabled(dev_priv);
11379
11380         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11381
11382         /* Wait for the clocks to stabilize. */
11383         POSTING_READ(PCH_DPLL(pll->id));
11384         udelay(150);
11385
11386         /* The pixel multiplier can only be updated once the
11387          * DPLL is enabled and the clocks are stable.
11388          *
11389          * So write it again.
11390          */
11391         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11392         POSTING_READ(PCH_DPLL(pll->id));
11393         udelay(200);
11394 }
11395
11396 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11397                                  struct intel_shared_dpll *pll)
11398 {
11399         struct drm_device *dev = dev_priv->dev;
11400         struct intel_crtc *crtc;
11401
11402         /* Make sure no transcoder isn't still depending on us. */
11403         for_each_intel_crtc(dev, crtc) {
11404                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11405                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11406         }
11407
11408         I915_WRITE(PCH_DPLL(pll->id), 0);
11409         POSTING_READ(PCH_DPLL(pll->id));
11410         udelay(200);
11411 }
11412
11413 static char *ibx_pch_dpll_names[] = {
11414         "PCH DPLL A",
11415         "PCH DPLL B",
11416 };
11417
11418 static void ibx_pch_dpll_init(struct drm_device *dev)
11419 {
11420         struct drm_i915_private *dev_priv = dev->dev_private;
11421         int i;
11422
11423         dev_priv->num_shared_dpll = 2;
11424
11425         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11426                 dev_priv->shared_dplls[i].id = i;
11427                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11428                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11429                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11430                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11431                 dev_priv->shared_dplls[i].get_hw_state =
11432                         ibx_pch_dpll_get_hw_state;
11433         }
11434 }
11435
11436 static void intel_shared_dpll_init(struct drm_device *dev)
11437 {
11438         struct drm_i915_private *dev_priv = dev->dev_private;
11439
11440         if (HAS_DDI(dev))
11441                 intel_ddi_pll_init(dev);
11442         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11443                 ibx_pch_dpll_init(dev);
11444         else
11445                 dev_priv->num_shared_dpll = 0;
11446
11447         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11448 }
11449
11450 static int
11451 intel_primary_plane_disable(struct drm_plane *plane)
11452 {
11453         struct drm_device *dev = plane->dev;
11454         struct intel_crtc *intel_crtc;
11455
11456         if (!plane->fb)
11457                 return 0;
11458
11459         BUG_ON(!plane->crtc);
11460
11461         intel_crtc = to_intel_crtc(plane->crtc);
11462
11463         /*
11464          * Even though we checked plane->fb above, it's still possible that
11465          * the primary plane has been implicitly disabled because the crtc
11466          * coordinates given weren't visible, or because we detected
11467          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11468          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11469          * In either case, we need to unpin the FB and let the fb pointer get
11470          * updated, but otherwise we don't need to touch the hardware.
11471          */
11472         if (!intel_crtc->primary_enabled)
11473                 goto disable_unpin;
11474
11475         intel_crtc_wait_for_pending_flips(plane->crtc);
11476         intel_disable_primary_hw_plane(plane, plane->crtc);
11477
11478 disable_unpin:
11479         mutex_lock(&dev->struct_mutex);
11480         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11481                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11482         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11483         mutex_unlock(&dev->struct_mutex);
11484         plane->fb = NULL;
11485
11486         return 0;
11487 }
11488
11489 static int
11490 intel_check_primary_plane(struct drm_plane *plane,
11491                           struct intel_plane_state *state)
11492 {
11493         struct drm_crtc *crtc = state->crtc;
11494         struct drm_framebuffer *fb = state->fb;
11495         struct drm_rect *dest = &state->dst;
11496         struct drm_rect *src = &state->src;
11497         const struct drm_rect *clip = &state->clip;
11498
11499         return drm_plane_helper_check_update(plane, crtc, fb,
11500                                              src, dest, clip,
11501                                              DRM_PLANE_HELPER_NO_SCALING,
11502                                              DRM_PLANE_HELPER_NO_SCALING,
11503                                              false, true, &state->visible);
11504 }
11505
11506 static int
11507 intel_prepare_primary_plane(struct drm_plane *plane,
11508                             struct intel_plane_state *state)
11509 {
11510         struct drm_crtc *crtc = state->crtc;
11511         struct drm_framebuffer *fb = state->fb;
11512         struct drm_device *dev = crtc->dev;
11513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11514         enum pipe pipe = intel_crtc->pipe;
11515         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11516         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11517         int ret;
11518
11519         intel_crtc_wait_for_pending_flips(crtc);
11520
11521         if (intel_crtc_has_pending_flip(crtc)) {
11522                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11523                 return -EBUSY;
11524         }
11525
11526         if (old_obj != obj) {
11527                 mutex_lock(&dev->struct_mutex);
11528                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11529                 if (ret == 0)
11530                         i915_gem_track_fb(old_obj, obj,
11531                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11532                 mutex_unlock(&dev->struct_mutex);
11533                 if (ret != 0) {
11534                         DRM_DEBUG_KMS("pin & fence failed\n");
11535                         return ret;
11536                 }
11537         }
11538
11539         return 0;
11540 }
11541
11542 static void
11543 intel_commit_primary_plane(struct drm_plane *plane,
11544                            struct intel_plane_state *state)
11545 {
11546         struct drm_crtc *crtc = state->crtc;
11547         struct drm_framebuffer *fb = state->fb;
11548         struct drm_device *dev = crtc->dev;
11549         struct drm_i915_private *dev_priv = dev->dev_private;
11550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11551         enum pipe pipe = intel_crtc->pipe;
11552         struct drm_framebuffer *old_fb = plane->fb;
11553         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11554         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11555         struct intel_plane *intel_plane = to_intel_plane(plane);
11556         struct drm_rect *src = &state->src;
11557
11558         crtc->primary->fb = fb;
11559         crtc->x = src->x1;
11560         crtc->y = src->y1;
11561
11562         intel_plane->crtc_x = state->orig_dst.x1;
11563         intel_plane->crtc_y = state->orig_dst.y1;
11564         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11565         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11566         intel_plane->src_x = state->orig_src.x1;
11567         intel_plane->src_y = state->orig_src.y1;
11568         intel_plane->src_w = drm_rect_width(&state->orig_src);
11569         intel_plane->src_h = drm_rect_height(&state->orig_src);
11570         intel_plane->obj = obj;
11571
11572         if (intel_crtc->active) {
11573                 /*
11574                  * FBC does not work on some platforms for rotated
11575                  * planes, so disable it when rotation is not 0 and
11576                  * update it when rotation is set back to 0.
11577                  *
11578                  * FIXME: This is redundant with the fbc update done in
11579                  * the primary plane enable function except that that
11580                  * one is done too late. We eventually need to unify
11581                  * this.
11582                  */
11583                 if (intel_crtc->primary_enabled &&
11584                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11585                     dev_priv->fbc.plane == intel_crtc->plane &&
11586                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11587                         intel_disable_fbc(dev);
11588                 }
11589
11590                 if (state->visible) {
11591                         bool was_enabled = intel_crtc->primary_enabled;
11592
11593                         /* FIXME: kill this fastboot hack */
11594                         intel_update_pipe_size(intel_crtc);
11595
11596                         intel_crtc->primary_enabled = true;
11597
11598                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11599                                         crtc->x, crtc->y);
11600
11601                         /*
11602                          * BDW signals flip done immediately if the plane
11603                          * is disabled, even if the plane enable is already
11604                          * armed to occur at the next vblank :(
11605                          */
11606                         if (IS_BROADWELL(dev) && !was_enabled)
11607                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11608                 } else {
11609                         /*
11610                          * If clipping results in a non-visible primary plane,
11611                          * we'll disable the primary plane.  Note that this is
11612                          * a bit different than what happens if userspace
11613                          * explicitly disables the plane by passing fb=0
11614                          * because plane->fb still gets set and pinned.
11615                          */
11616                         intel_disable_primary_hw_plane(plane, crtc);
11617                 }
11618
11619                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11620
11621                 mutex_lock(&dev->struct_mutex);
11622                 intel_update_fbc(dev);
11623                 mutex_unlock(&dev->struct_mutex);
11624         }
11625
11626         if (old_fb && old_fb != fb) {
11627                 if (intel_crtc->active)
11628                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11629
11630                 mutex_lock(&dev->struct_mutex);
11631                 intel_unpin_fb_obj(old_obj);
11632                 mutex_unlock(&dev->struct_mutex);
11633         }
11634 }
11635
11636 static int
11637 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11638                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11639                              unsigned int crtc_w, unsigned int crtc_h,
11640                              uint32_t src_x, uint32_t src_y,
11641                              uint32_t src_w, uint32_t src_h)
11642 {
11643         struct intel_plane_state state;
11644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11645         int ret;
11646
11647         state.crtc = crtc;
11648         state.fb = fb;
11649
11650         /* sample coordinates in 16.16 fixed point */
11651         state.src.x1 = src_x;
11652         state.src.x2 = src_x + src_w;
11653         state.src.y1 = src_y;
11654         state.src.y2 = src_y + src_h;
11655
11656         /* integer pixels */
11657         state.dst.x1 = crtc_x;
11658         state.dst.x2 = crtc_x + crtc_w;
11659         state.dst.y1 = crtc_y;
11660         state.dst.y2 = crtc_y + crtc_h;
11661
11662         state.clip.x1 = 0;
11663         state.clip.y1 = 0;
11664         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11665         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11666
11667         state.orig_src = state.src;
11668         state.orig_dst = state.dst;
11669
11670         ret = intel_check_primary_plane(plane, &state);
11671         if (ret)
11672                 return ret;
11673
11674         ret = intel_prepare_primary_plane(plane, &state);
11675         if (ret)
11676                 return ret;
11677
11678         intel_commit_primary_plane(plane, &state);
11679
11680         return 0;
11681 }
11682
11683 /* Common destruction function for both primary and cursor planes */
11684 static void intel_plane_destroy(struct drm_plane *plane)
11685 {
11686         struct intel_plane *intel_plane = to_intel_plane(plane);
11687         drm_plane_cleanup(plane);
11688         kfree(intel_plane);
11689 }
11690
11691 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11692         .update_plane = intel_primary_plane_setplane,
11693         .disable_plane = intel_primary_plane_disable,
11694         .destroy = intel_plane_destroy,
11695         .set_property = intel_plane_set_property
11696 };
11697
11698 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11699                                                     int pipe)
11700 {
11701         struct intel_plane *primary;
11702         const uint32_t *intel_primary_formats;
11703         int num_formats;
11704
11705         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11706         if (primary == NULL)
11707                 return NULL;
11708
11709         primary->can_scale = false;
11710         primary->max_downscale = 1;
11711         primary->pipe = pipe;
11712         primary->plane = pipe;
11713         primary->rotation = BIT(DRM_ROTATE_0);
11714         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11715                 primary->plane = !pipe;
11716
11717         if (INTEL_INFO(dev)->gen <= 3) {
11718                 intel_primary_formats = intel_primary_formats_gen2;
11719                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11720         } else {
11721                 intel_primary_formats = intel_primary_formats_gen4;
11722                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11723         }
11724
11725         drm_universal_plane_init(dev, &primary->base, 0,
11726                                  &intel_primary_plane_funcs,
11727                                  intel_primary_formats, num_formats,
11728                                  DRM_PLANE_TYPE_PRIMARY);
11729
11730         if (INTEL_INFO(dev)->gen >= 4) {
11731                 if (!dev->mode_config.rotation_property)
11732                         dev->mode_config.rotation_property =
11733                                 drm_mode_create_rotation_property(dev,
11734                                                         BIT(DRM_ROTATE_0) |
11735                                                         BIT(DRM_ROTATE_180));
11736                 if (dev->mode_config.rotation_property)
11737                         drm_object_attach_property(&primary->base.base,
11738                                 dev->mode_config.rotation_property,
11739                                 primary->rotation);
11740         }
11741
11742         return &primary->base;
11743 }
11744
11745 static int
11746 intel_cursor_plane_disable(struct drm_plane *plane)
11747 {
11748         if (!plane->fb)
11749                 return 0;
11750
11751         BUG_ON(!plane->crtc);
11752
11753         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11754 }
11755
11756 static int
11757 intel_check_cursor_plane(struct drm_plane *plane,
11758                          struct intel_plane_state *state)
11759 {
11760         struct drm_crtc *crtc = state->crtc;
11761         struct drm_device *dev = crtc->dev;
11762         struct drm_framebuffer *fb = state->fb;
11763         struct drm_rect *dest = &state->dst;
11764         struct drm_rect *src = &state->src;
11765         const struct drm_rect *clip = &state->clip;
11766         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11767         int crtc_w, crtc_h;
11768         unsigned stride;
11769         int ret;
11770
11771         ret = drm_plane_helper_check_update(plane, crtc, fb,
11772                                             src, dest, clip,
11773                                             DRM_PLANE_HELPER_NO_SCALING,
11774                                             DRM_PLANE_HELPER_NO_SCALING,
11775                                             true, true, &state->visible);
11776         if (ret)
11777                 return ret;
11778
11779
11780         /* if we want to turn off the cursor ignore width and height */
11781         if (!obj)
11782                 return 0;
11783
11784         /* Check for which cursor types we support */
11785         crtc_w = drm_rect_width(&state->orig_dst);
11786         crtc_h = drm_rect_height(&state->orig_dst);
11787         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11788                 DRM_DEBUG("Cursor dimension not supported\n");
11789                 return -EINVAL;
11790         }
11791
11792         stride = roundup_pow_of_two(crtc_w) * 4;
11793         if (obj->base.size < stride * crtc_h) {
11794                 DRM_DEBUG_KMS("buffer is too small\n");
11795                 return -ENOMEM;
11796         }
11797
11798         if (fb == crtc->cursor->fb)
11799                 return 0;
11800
11801         /* we only need to pin inside GTT if cursor is non-phy */
11802         mutex_lock(&dev->struct_mutex);
11803         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11804                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11805                 ret = -EINVAL;
11806         }
11807         mutex_unlock(&dev->struct_mutex);
11808
11809         return ret;
11810 }
11811
11812 static int
11813 intel_commit_cursor_plane(struct drm_plane *plane,
11814                           struct intel_plane_state *state)
11815 {
11816         struct drm_crtc *crtc = state->crtc;
11817         struct drm_framebuffer *fb = state->fb;
11818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11819         struct intel_plane *intel_plane = to_intel_plane(plane);
11820         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11821         struct drm_i915_gem_object *obj = intel_fb->obj;
11822         int crtc_w, crtc_h;
11823
11824         crtc->cursor_x = state->orig_dst.x1;
11825         crtc->cursor_y = state->orig_dst.y1;
11826
11827         intel_plane->crtc_x = state->orig_dst.x1;
11828         intel_plane->crtc_y = state->orig_dst.y1;
11829         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11830         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11831         intel_plane->src_x = state->orig_src.x1;
11832         intel_plane->src_y = state->orig_src.y1;
11833         intel_plane->src_w = drm_rect_width(&state->orig_src);
11834         intel_plane->src_h = drm_rect_height(&state->orig_src);
11835         intel_plane->obj = obj;
11836
11837         if (fb != crtc->cursor->fb) {
11838                 crtc_w = drm_rect_width(&state->orig_dst);
11839                 crtc_h = drm_rect_height(&state->orig_dst);
11840                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11841         } else {
11842                 intel_crtc_update_cursor(crtc, state->visible);
11843
11844                 intel_frontbuffer_flip(crtc->dev,
11845                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11846
11847                 return 0;
11848         }
11849 }
11850
11851 static int
11852 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11853                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11854                           unsigned int crtc_w, unsigned int crtc_h,
11855                           uint32_t src_x, uint32_t src_y,
11856                           uint32_t src_w, uint32_t src_h)
11857 {
11858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11859         struct intel_plane_state state;
11860         int ret;
11861
11862         state.crtc = crtc;
11863         state.fb = fb;
11864
11865         /* sample coordinates in 16.16 fixed point */
11866         state.src.x1 = src_x;
11867         state.src.x2 = src_x + src_w;
11868         state.src.y1 = src_y;
11869         state.src.y2 = src_y + src_h;
11870
11871         /* integer pixels */
11872         state.dst.x1 = crtc_x;
11873         state.dst.x2 = crtc_x + crtc_w;
11874         state.dst.y1 = crtc_y;
11875         state.dst.y2 = crtc_y + crtc_h;
11876
11877         state.clip.x1 = 0;
11878         state.clip.y1 = 0;
11879         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11880         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11881
11882         state.orig_src = state.src;
11883         state.orig_dst = state.dst;
11884
11885         ret = intel_check_cursor_plane(plane, &state);
11886         if (ret)
11887                 return ret;
11888
11889         return intel_commit_cursor_plane(plane, &state);
11890 }
11891
11892 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11893         .update_plane = intel_cursor_plane_update,
11894         .disable_plane = intel_cursor_plane_disable,
11895         .destroy = intel_plane_destroy,
11896         .set_property = intel_plane_set_property,
11897 };
11898
11899 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11900                                                    int pipe)
11901 {
11902         struct intel_plane *cursor;
11903
11904         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11905         if (cursor == NULL)
11906                 return NULL;
11907
11908         cursor->can_scale = false;
11909         cursor->max_downscale = 1;
11910         cursor->pipe = pipe;
11911         cursor->plane = pipe;
11912         cursor->rotation = BIT(DRM_ROTATE_0);
11913
11914         drm_universal_plane_init(dev, &cursor->base, 0,
11915                                  &intel_cursor_plane_funcs,
11916                                  intel_cursor_formats,
11917                                  ARRAY_SIZE(intel_cursor_formats),
11918                                  DRM_PLANE_TYPE_CURSOR);
11919
11920         if (INTEL_INFO(dev)->gen >= 4) {
11921                 if (!dev->mode_config.rotation_property)
11922                         dev->mode_config.rotation_property =
11923                                 drm_mode_create_rotation_property(dev,
11924                                                         BIT(DRM_ROTATE_0) |
11925                                                         BIT(DRM_ROTATE_180));
11926                 if (dev->mode_config.rotation_property)
11927                         drm_object_attach_property(&cursor->base.base,
11928                                 dev->mode_config.rotation_property,
11929                                 cursor->rotation);
11930         }
11931
11932         return &cursor->base;
11933 }
11934
11935 static void intel_crtc_init(struct drm_device *dev, int pipe)
11936 {
11937         struct drm_i915_private *dev_priv = dev->dev_private;
11938         struct intel_crtc *intel_crtc;
11939         struct drm_plane *primary = NULL;
11940         struct drm_plane *cursor = NULL;
11941         int i, ret;
11942
11943         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11944         if (intel_crtc == NULL)
11945                 return;
11946
11947         primary = intel_primary_plane_create(dev, pipe);
11948         if (!primary)
11949                 goto fail;
11950
11951         cursor = intel_cursor_plane_create(dev, pipe);
11952         if (!cursor)
11953                 goto fail;
11954
11955         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11956                                         cursor, &intel_crtc_funcs);
11957         if (ret)
11958                 goto fail;
11959
11960         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11961         for (i = 0; i < 256; i++) {
11962                 intel_crtc->lut_r[i] = i;
11963                 intel_crtc->lut_g[i] = i;
11964                 intel_crtc->lut_b[i] = i;
11965         }
11966
11967         /*
11968          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11969          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11970          */
11971         intel_crtc->pipe = pipe;
11972         intel_crtc->plane = pipe;
11973         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11974                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11975                 intel_crtc->plane = !pipe;
11976         }
11977
11978         intel_crtc->cursor_base = ~0;
11979         intel_crtc->cursor_cntl = ~0;
11980         intel_crtc->cursor_size = ~0;
11981
11982         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11983                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11984         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11985         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11986
11987         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11988
11989         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11990         return;
11991
11992 fail:
11993         if (primary)
11994                 drm_plane_cleanup(primary);
11995         if (cursor)
11996                 drm_plane_cleanup(cursor);
11997         kfree(intel_crtc);
11998 }
11999
12000 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12001 {
12002         struct drm_encoder *encoder = connector->base.encoder;
12003         struct drm_device *dev = connector->base.dev;
12004
12005         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12006
12007         if (!encoder)
12008                 return INVALID_PIPE;
12009
12010         return to_intel_crtc(encoder->crtc)->pipe;
12011 }
12012
12013 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12014                                 struct drm_file *file)
12015 {
12016         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12017         struct drm_crtc *drmmode_crtc;
12018         struct intel_crtc *crtc;
12019
12020         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12021                 return -ENODEV;
12022
12023         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12024
12025         if (!drmmode_crtc) {
12026                 DRM_ERROR("no such CRTC id\n");
12027                 return -ENOENT;
12028         }
12029
12030         crtc = to_intel_crtc(drmmode_crtc);
12031         pipe_from_crtc_id->pipe = crtc->pipe;
12032
12033         return 0;
12034 }
12035
12036 static int intel_encoder_clones(struct intel_encoder *encoder)
12037 {
12038         struct drm_device *dev = encoder->base.dev;
12039         struct intel_encoder *source_encoder;
12040         int index_mask = 0;
12041         int entry = 0;
12042
12043         for_each_intel_encoder(dev, source_encoder) {
12044                 if (encoders_cloneable(encoder, source_encoder))
12045                         index_mask |= (1 << entry);
12046
12047                 entry++;
12048         }
12049
12050         return index_mask;
12051 }
12052
12053 static bool has_edp_a(struct drm_device *dev)
12054 {
12055         struct drm_i915_private *dev_priv = dev->dev_private;
12056
12057         if (!IS_MOBILE(dev))
12058                 return false;
12059
12060         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12061                 return false;
12062
12063         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12064                 return false;
12065
12066         return true;
12067 }
12068
12069 const char *intel_output_name(int output)
12070 {
12071         static const char *names[] = {
12072                 [INTEL_OUTPUT_UNUSED] = "Unused",
12073                 [INTEL_OUTPUT_ANALOG] = "Analog",
12074                 [INTEL_OUTPUT_DVO] = "DVO",
12075                 [INTEL_OUTPUT_SDVO] = "SDVO",
12076                 [INTEL_OUTPUT_LVDS] = "LVDS",
12077                 [INTEL_OUTPUT_TVOUT] = "TV",
12078                 [INTEL_OUTPUT_HDMI] = "HDMI",
12079                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12080                 [INTEL_OUTPUT_EDP] = "eDP",
12081                 [INTEL_OUTPUT_DSI] = "DSI",
12082                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12083         };
12084
12085         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12086                 return "Invalid";
12087
12088         return names[output];
12089 }
12090
12091 static bool intel_crt_present(struct drm_device *dev)
12092 {
12093         struct drm_i915_private *dev_priv = dev->dev_private;
12094
12095         if (INTEL_INFO(dev)->gen >= 9)
12096                 return false;
12097
12098         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12099                 return false;
12100
12101         if (IS_CHERRYVIEW(dev))
12102                 return false;
12103
12104         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12105                 return false;
12106
12107         return true;
12108 }
12109
12110 static void intel_setup_outputs(struct drm_device *dev)
12111 {
12112         struct drm_i915_private *dev_priv = dev->dev_private;
12113         struct intel_encoder *encoder;
12114         bool dpd_is_edp = false;
12115
12116         intel_lvds_init(dev);
12117
12118         if (intel_crt_present(dev))
12119                 intel_crt_init(dev);
12120
12121         if (HAS_DDI(dev)) {
12122                 int found;
12123
12124                 /* Haswell uses DDI functions to detect digital outputs */
12125                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12126                 /* DDI A only supports eDP */
12127                 if (found)
12128                         intel_ddi_init(dev, PORT_A);
12129
12130                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12131                  * register */
12132                 found = I915_READ(SFUSE_STRAP);
12133
12134                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12135                         intel_ddi_init(dev, PORT_B);
12136                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12137                         intel_ddi_init(dev, PORT_C);
12138                 if (found & SFUSE_STRAP_DDID_DETECTED)
12139                         intel_ddi_init(dev, PORT_D);
12140         } else if (HAS_PCH_SPLIT(dev)) {
12141                 int found;
12142                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12143
12144                 if (has_edp_a(dev))
12145                         intel_dp_init(dev, DP_A, PORT_A);
12146
12147                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12148                         /* PCH SDVOB multiplex with HDMIB */
12149                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12150                         if (!found)
12151                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12152                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12153                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12154                 }
12155
12156                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12157                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12158
12159                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12160                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12161
12162                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12163                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12164
12165                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12166                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12167         } else if (IS_VALLEYVIEW(dev)) {
12168                 /*
12169                  * The DP_DETECTED bit is the latched state of the DDC
12170                  * SDA pin at boot. However since eDP doesn't require DDC
12171                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12172                  * eDP ports may have been muxed to an alternate function.
12173                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12174                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12175                  * detect eDP ports.
12176                  */
12177                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12178                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12179                                         PORT_B);
12180                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12181                     intel_dp_is_edp(dev, PORT_B))
12182                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12183
12184                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12185                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12186                                         PORT_C);
12187                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12188                     intel_dp_is_edp(dev, PORT_C))
12189                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12190
12191                 if (IS_CHERRYVIEW(dev)) {
12192                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12193                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12194                                                 PORT_D);
12195                         /* eDP not supported on port D, so don't check VBT */
12196                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12197                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12198                 }
12199
12200                 intel_dsi_init(dev);
12201         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12202                 bool found = false;
12203
12204                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12205                         DRM_DEBUG_KMS("probing SDVOB\n");
12206                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12207                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12208                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12209                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12210                         }
12211
12212                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12213                                 intel_dp_init(dev, DP_B, PORT_B);
12214                 }
12215
12216                 /* Before G4X SDVOC doesn't have its own detect register */
12217
12218                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12219                         DRM_DEBUG_KMS("probing SDVOC\n");
12220                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12221                 }
12222
12223                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12224
12225                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12226                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12227                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12228                         }
12229                         if (SUPPORTS_INTEGRATED_DP(dev))
12230                                 intel_dp_init(dev, DP_C, PORT_C);
12231                 }
12232
12233                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12234                     (I915_READ(DP_D) & DP_DETECTED))
12235                         intel_dp_init(dev, DP_D, PORT_D);
12236         } else if (IS_GEN2(dev))
12237                 intel_dvo_init(dev);
12238
12239         if (SUPPORTS_TV(dev))
12240                 intel_tv_init(dev);
12241
12242         intel_edp_psr_init(dev);
12243
12244         for_each_intel_encoder(dev, encoder) {
12245                 encoder->base.possible_crtcs = encoder->crtc_mask;
12246                 encoder->base.possible_clones =
12247                         intel_encoder_clones(encoder);
12248         }
12249
12250         intel_init_pch_refclk(dev);
12251
12252         drm_helper_move_panel_connectors_to_head(dev);
12253 }
12254
12255 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12256 {
12257         struct drm_device *dev = fb->dev;
12258         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12259
12260         drm_framebuffer_cleanup(fb);
12261         mutex_lock(&dev->struct_mutex);
12262         WARN_ON(!intel_fb->obj->framebuffer_references--);
12263         drm_gem_object_unreference(&intel_fb->obj->base);
12264         mutex_unlock(&dev->struct_mutex);
12265         kfree(intel_fb);
12266 }
12267
12268 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12269                                                 struct drm_file *file,
12270                                                 unsigned int *handle)
12271 {
12272         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12273         struct drm_i915_gem_object *obj = intel_fb->obj;
12274
12275         return drm_gem_handle_create(file, &obj->base, handle);
12276 }
12277
12278 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12279         .destroy = intel_user_framebuffer_destroy,
12280         .create_handle = intel_user_framebuffer_create_handle,
12281 };
12282
12283 static int intel_framebuffer_init(struct drm_device *dev,
12284                                   struct intel_framebuffer *intel_fb,
12285                                   struct drm_mode_fb_cmd2 *mode_cmd,
12286                                   struct drm_i915_gem_object *obj)
12287 {
12288         int aligned_height;
12289         int pitch_limit;
12290         int ret;
12291
12292         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12293
12294         if (obj->tiling_mode == I915_TILING_Y) {
12295                 DRM_DEBUG("hardware does not support tiling Y\n");
12296                 return -EINVAL;
12297         }
12298
12299         if (mode_cmd->pitches[0] & 63) {
12300                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12301                           mode_cmd->pitches[0]);
12302                 return -EINVAL;
12303         }
12304
12305         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12306                 pitch_limit = 32*1024;
12307         } else if (INTEL_INFO(dev)->gen >= 4) {
12308                 if (obj->tiling_mode)
12309                         pitch_limit = 16*1024;
12310                 else
12311                         pitch_limit = 32*1024;
12312         } else if (INTEL_INFO(dev)->gen >= 3) {
12313                 if (obj->tiling_mode)
12314                         pitch_limit = 8*1024;
12315                 else
12316                         pitch_limit = 16*1024;
12317         } else
12318                 /* XXX DSPC is limited to 4k tiled */
12319                 pitch_limit = 8*1024;
12320
12321         if (mode_cmd->pitches[0] > pitch_limit) {
12322                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12323                           obj->tiling_mode ? "tiled" : "linear",
12324                           mode_cmd->pitches[0], pitch_limit);
12325                 return -EINVAL;
12326         }
12327
12328         if (obj->tiling_mode != I915_TILING_NONE &&
12329             mode_cmd->pitches[0] != obj->stride) {
12330                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12331                           mode_cmd->pitches[0], obj->stride);
12332                 return -EINVAL;
12333         }
12334
12335         /* Reject formats not supported by any plane early. */
12336         switch (mode_cmd->pixel_format) {
12337         case DRM_FORMAT_C8:
12338         case DRM_FORMAT_RGB565:
12339         case DRM_FORMAT_XRGB8888:
12340         case DRM_FORMAT_ARGB8888:
12341                 break;
12342         case DRM_FORMAT_XRGB1555:
12343         case DRM_FORMAT_ARGB1555:
12344                 if (INTEL_INFO(dev)->gen > 3) {
12345                         DRM_DEBUG("unsupported pixel format: %s\n",
12346                                   drm_get_format_name(mode_cmd->pixel_format));
12347                         return -EINVAL;
12348                 }
12349                 break;
12350         case DRM_FORMAT_XBGR8888:
12351         case DRM_FORMAT_ABGR8888:
12352         case DRM_FORMAT_XRGB2101010:
12353         case DRM_FORMAT_ARGB2101010:
12354         case DRM_FORMAT_XBGR2101010:
12355         case DRM_FORMAT_ABGR2101010:
12356                 if (INTEL_INFO(dev)->gen < 4) {
12357                         DRM_DEBUG("unsupported pixel format: %s\n",
12358                                   drm_get_format_name(mode_cmd->pixel_format));
12359                         return -EINVAL;
12360                 }
12361                 break;
12362         case DRM_FORMAT_YUYV:
12363         case DRM_FORMAT_UYVY:
12364         case DRM_FORMAT_YVYU:
12365         case DRM_FORMAT_VYUY:
12366                 if (INTEL_INFO(dev)->gen < 5) {
12367                         DRM_DEBUG("unsupported pixel format: %s\n",
12368                                   drm_get_format_name(mode_cmd->pixel_format));
12369                         return -EINVAL;
12370                 }
12371                 break;
12372         default:
12373                 DRM_DEBUG("unsupported pixel format: %s\n",
12374                           drm_get_format_name(mode_cmd->pixel_format));
12375                 return -EINVAL;
12376         }
12377
12378         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12379         if (mode_cmd->offsets[0] != 0)
12380                 return -EINVAL;
12381
12382         aligned_height = intel_align_height(dev, mode_cmd->height,
12383                                             obj->tiling_mode);
12384         /* FIXME drm helper for size checks (especially planar formats)? */
12385         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12386                 return -EINVAL;
12387
12388         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12389         intel_fb->obj = obj;
12390         intel_fb->obj->framebuffer_references++;
12391
12392         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12393         if (ret) {
12394                 DRM_ERROR("framebuffer init failed %d\n", ret);
12395                 return ret;
12396         }
12397
12398         return 0;
12399 }
12400
12401 static struct drm_framebuffer *
12402 intel_user_framebuffer_create(struct drm_device *dev,
12403                               struct drm_file *filp,
12404                               struct drm_mode_fb_cmd2 *mode_cmd)
12405 {
12406         struct drm_i915_gem_object *obj;
12407
12408         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12409                                                 mode_cmd->handles[0]));
12410         if (&obj->base == NULL)
12411                 return ERR_PTR(-ENOENT);
12412
12413         return intel_framebuffer_create(dev, mode_cmd, obj);
12414 }
12415
12416 #ifndef CONFIG_DRM_I915_FBDEV
12417 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12418 {
12419 }
12420 #endif
12421
12422 static const struct drm_mode_config_funcs intel_mode_funcs = {
12423         .fb_create = intel_user_framebuffer_create,
12424         .output_poll_changed = intel_fbdev_output_poll_changed,
12425 };
12426
12427 /* Set up chip specific display functions */
12428 static void intel_init_display(struct drm_device *dev)
12429 {
12430         struct drm_i915_private *dev_priv = dev->dev_private;
12431
12432         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12433                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12434         else if (IS_CHERRYVIEW(dev))
12435                 dev_priv->display.find_dpll = chv_find_best_dpll;
12436         else if (IS_VALLEYVIEW(dev))
12437                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12438         else if (IS_PINEVIEW(dev))
12439                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12440         else
12441                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12442
12443         if (HAS_DDI(dev)) {
12444                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12445                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12446                 dev_priv->display.crtc_compute_clock =
12447                         haswell_crtc_compute_clock;
12448                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12449                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12450                 dev_priv->display.off = ironlake_crtc_off;
12451                 if (INTEL_INFO(dev)->gen >= 9)
12452                         dev_priv->display.update_primary_plane =
12453                                 skylake_update_primary_plane;
12454                 else
12455                         dev_priv->display.update_primary_plane =
12456                                 ironlake_update_primary_plane;
12457         } else if (HAS_PCH_SPLIT(dev)) {
12458                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12459                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12460                 dev_priv->display.crtc_compute_clock =
12461                         ironlake_crtc_compute_clock;
12462                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12463                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12464                 dev_priv->display.off = ironlake_crtc_off;
12465                 dev_priv->display.update_primary_plane =
12466                         ironlake_update_primary_plane;
12467         } else if (IS_VALLEYVIEW(dev)) {
12468                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12469                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12470                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12471                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12472                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12473                 dev_priv->display.off = i9xx_crtc_off;
12474                 dev_priv->display.update_primary_plane =
12475                         i9xx_update_primary_plane;
12476         } else {
12477                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12478                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12479                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12480                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12481                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12482                 dev_priv->display.off = i9xx_crtc_off;
12483                 dev_priv->display.update_primary_plane =
12484                         i9xx_update_primary_plane;
12485         }
12486
12487         /* Returns the core display clock speed */
12488         if (IS_VALLEYVIEW(dev))
12489                 dev_priv->display.get_display_clock_speed =
12490                         valleyview_get_display_clock_speed;
12491         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12492                 dev_priv->display.get_display_clock_speed =
12493                         i945_get_display_clock_speed;
12494         else if (IS_I915G(dev))
12495                 dev_priv->display.get_display_clock_speed =
12496                         i915_get_display_clock_speed;
12497         else if (IS_I945GM(dev) || IS_845G(dev))
12498                 dev_priv->display.get_display_clock_speed =
12499                         i9xx_misc_get_display_clock_speed;
12500         else if (IS_PINEVIEW(dev))
12501                 dev_priv->display.get_display_clock_speed =
12502                         pnv_get_display_clock_speed;
12503         else if (IS_I915GM(dev))
12504                 dev_priv->display.get_display_clock_speed =
12505                         i915gm_get_display_clock_speed;
12506         else if (IS_I865G(dev))
12507                 dev_priv->display.get_display_clock_speed =
12508                         i865_get_display_clock_speed;
12509         else if (IS_I85X(dev))
12510                 dev_priv->display.get_display_clock_speed =
12511                         i855_get_display_clock_speed;
12512         else /* 852, 830 */
12513                 dev_priv->display.get_display_clock_speed =
12514                         i830_get_display_clock_speed;
12515
12516         if (IS_GEN5(dev)) {
12517                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12518         } else if (IS_GEN6(dev)) {
12519                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12520                 dev_priv->display.modeset_global_resources =
12521                         snb_modeset_global_resources;
12522         } else if (IS_IVYBRIDGE(dev)) {
12523                 /* FIXME: detect B0+ stepping and use auto training */
12524                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12525                 dev_priv->display.modeset_global_resources =
12526                         ivb_modeset_global_resources;
12527         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12528                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12529                 dev_priv->display.modeset_global_resources =
12530                         haswell_modeset_global_resources;
12531         } else if (IS_VALLEYVIEW(dev)) {
12532                 dev_priv->display.modeset_global_resources =
12533                         valleyview_modeset_global_resources;
12534         } else if (INTEL_INFO(dev)->gen >= 9) {
12535                 dev_priv->display.modeset_global_resources =
12536                         haswell_modeset_global_resources;
12537         }
12538
12539         /* Default just returns -ENODEV to indicate unsupported */
12540         dev_priv->display.queue_flip = intel_default_queue_flip;
12541
12542         switch (INTEL_INFO(dev)->gen) {
12543         case 2:
12544                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12545                 break;
12546
12547         case 3:
12548                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12549                 break;
12550
12551         case 4:
12552         case 5:
12553                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12554                 break;
12555
12556         case 6:
12557                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12558                 break;
12559         case 7:
12560         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12561                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12562                 break;
12563         }
12564
12565         intel_panel_init_backlight_funcs(dev);
12566
12567         mutex_init(&dev_priv->pps_mutex);
12568 }
12569
12570 /*
12571  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12572  * resume, or other times.  This quirk makes sure that's the case for
12573  * affected systems.
12574  */
12575 static void quirk_pipea_force(struct drm_device *dev)
12576 {
12577         struct drm_i915_private *dev_priv = dev->dev_private;
12578
12579         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12580         DRM_INFO("applying pipe a force quirk\n");
12581 }
12582
12583 static void quirk_pipeb_force(struct drm_device *dev)
12584 {
12585         struct drm_i915_private *dev_priv = dev->dev_private;
12586
12587         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12588         DRM_INFO("applying pipe b force quirk\n");
12589 }
12590
12591 /*
12592  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12593  */
12594 static void quirk_ssc_force_disable(struct drm_device *dev)
12595 {
12596         struct drm_i915_private *dev_priv = dev->dev_private;
12597         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12598         DRM_INFO("applying lvds SSC disable quirk\n");
12599 }
12600
12601 /*
12602  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12603  * brightness value
12604  */
12605 static void quirk_invert_brightness(struct drm_device *dev)
12606 {
12607         struct drm_i915_private *dev_priv = dev->dev_private;
12608         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12609         DRM_INFO("applying inverted panel brightness quirk\n");
12610 }
12611
12612 /* Some VBT's incorrectly indicate no backlight is present */
12613 static void quirk_backlight_present(struct drm_device *dev)
12614 {
12615         struct drm_i915_private *dev_priv = dev->dev_private;
12616         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12617         DRM_INFO("applying backlight present quirk\n");
12618 }
12619
12620 struct intel_quirk {
12621         int device;
12622         int subsystem_vendor;
12623         int subsystem_device;
12624         void (*hook)(struct drm_device *dev);
12625 };
12626
12627 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12628 struct intel_dmi_quirk {
12629         void (*hook)(struct drm_device *dev);
12630         const struct dmi_system_id (*dmi_id_list)[];
12631 };
12632
12633 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12634 {
12635         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12636         return 1;
12637 }
12638
12639 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12640         {
12641                 .dmi_id_list = &(const struct dmi_system_id[]) {
12642                         {
12643                                 .callback = intel_dmi_reverse_brightness,
12644                                 .ident = "NCR Corporation",
12645                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12646                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12647                                 },
12648                         },
12649                         { }  /* terminating entry */
12650                 },
12651                 .hook = quirk_invert_brightness,
12652         },
12653 };
12654
12655 static struct intel_quirk intel_quirks[] = {
12656         /* HP Mini needs pipe A force quirk (LP: #322104) */
12657         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12658
12659         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12660         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12661
12662         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12663         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12664
12665         /* 830 needs to leave pipe A & dpll A up */
12666         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12667
12668         /* 830 needs to leave pipe B & dpll B up */
12669         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12670
12671         /* Lenovo U160 cannot use SSC on LVDS */
12672         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12673
12674         /* Sony Vaio Y cannot use SSC on LVDS */
12675         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12676
12677         /* Acer Aspire 5734Z must invert backlight brightness */
12678         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12679
12680         /* Acer/eMachines G725 */
12681         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12682
12683         /* Acer/eMachines e725 */
12684         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12685
12686         /* Acer/Packard Bell NCL20 */
12687         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12688
12689         /* Acer Aspire 4736Z */
12690         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12691
12692         /* Acer Aspire 5336 */
12693         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12694
12695         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12696         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12697
12698         /* Acer C720 Chromebook (Core i3 4005U) */
12699         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12700
12701         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12702         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12703
12704         /* HP Chromebook 14 (Celeron 2955U) */
12705         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12706 };
12707
12708 static void intel_init_quirks(struct drm_device *dev)
12709 {
12710         struct pci_dev *d = dev->pdev;
12711         int i;
12712
12713         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12714                 struct intel_quirk *q = &intel_quirks[i];
12715
12716                 if (d->device == q->device &&
12717                     (d->subsystem_vendor == q->subsystem_vendor ||
12718                      q->subsystem_vendor == PCI_ANY_ID) &&
12719                     (d->subsystem_device == q->subsystem_device ||
12720                      q->subsystem_device == PCI_ANY_ID))
12721                         q->hook(dev);
12722         }
12723         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12724                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12725                         intel_dmi_quirks[i].hook(dev);
12726         }
12727 }
12728
12729 /* Disable the VGA plane that we never use */
12730 static void i915_disable_vga(struct drm_device *dev)
12731 {
12732         struct drm_i915_private *dev_priv = dev->dev_private;
12733         u8 sr1;
12734         u32 vga_reg = i915_vgacntrl_reg(dev);
12735
12736         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12737         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12738         outb(SR01, VGA_SR_INDEX);
12739         sr1 = inb(VGA_SR_DATA);
12740         outb(sr1 | 1<<5, VGA_SR_DATA);
12741         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12742         udelay(300);
12743
12744         /*
12745          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12746          * from S3 without preserving (some of?) the other bits.
12747          */
12748         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12749         POSTING_READ(vga_reg);
12750 }
12751
12752 void intel_modeset_init_hw(struct drm_device *dev)
12753 {
12754         intel_prepare_ddi(dev);
12755
12756         if (IS_VALLEYVIEW(dev))
12757                 vlv_update_cdclk(dev);
12758
12759         intel_init_clock_gating(dev);
12760
12761         intel_enable_gt_powersave(dev);
12762 }
12763
12764 void intel_modeset_init(struct drm_device *dev)
12765 {
12766         struct drm_i915_private *dev_priv = dev->dev_private;
12767         int sprite, ret;
12768         enum pipe pipe;
12769         struct intel_crtc *crtc;
12770
12771         drm_mode_config_init(dev);
12772
12773         dev->mode_config.min_width = 0;
12774         dev->mode_config.min_height = 0;
12775
12776         dev->mode_config.preferred_depth = 24;
12777         dev->mode_config.prefer_shadow = 1;
12778
12779         dev->mode_config.funcs = &intel_mode_funcs;
12780
12781         intel_init_quirks(dev);
12782
12783         intel_init_pm(dev);
12784
12785         if (INTEL_INFO(dev)->num_pipes == 0)
12786                 return;
12787
12788         intel_init_display(dev);
12789         intel_init_audio(dev);
12790
12791         if (IS_GEN2(dev)) {
12792                 dev->mode_config.max_width = 2048;
12793                 dev->mode_config.max_height = 2048;
12794         } else if (IS_GEN3(dev)) {
12795                 dev->mode_config.max_width = 4096;
12796                 dev->mode_config.max_height = 4096;
12797         } else {
12798                 dev->mode_config.max_width = 8192;
12799                 dev->mode_config.max_height = 8192;
12800         }
12801
12802         if (IS_845G(dev) || IS_I865G(dev)) {
12803                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12804                 dev->mode_config.cursor_height = 1023;
12805         } else if (IS_GEN2(dev)) {
12806                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12807                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12808         } else {
12809                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12810                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12811         }
12812
12813         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12814
12815         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12816                       INTEL_INFO(dev)->num_pipes,
12817                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12818
12819         for_each_pipe(dev_priv, pipe) {
12820                 intel_crtc_init(dev, pipe);
12821                 for_each_sprite(pipe, sprite) {
12822                         ret = intel_plane_init(dev, pipe, sprite);
12823                         if (ret)
12824                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12825                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12826                 }
12827         }
12828
12829         intel_init_dpio(dev);
12830
12831         intel_shared_dpll_init(dev);
12832
12833         /* save the BIOS value before clobbering it */
12834         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12835         /* Just disable it once at startup */
12836         i915_disable_vga(dev);
12837         intel_setup_outputs(dev);
12838
12839         /* Just in case the BIOS is doing something questionable. */
12840         intel_disable_fbc(dev);
12841
12842         drm_modeset_lock_all(dev);
12843         intel_modeset_setup_hw_state(dev, false);
12844         drm_modeset_unlock_all(dev);
12845
12846         for_each_intel_crtc(dev, crtc) {
12847                 if (!crtc->active)
12848                         continue;
12849
12850                 /*
12851                  * Note that reserving the BIOS fb up front prevents us
12852                  * from stuffing other stolen allocations like the ring
12853                  * on top.  This prevents some ugliness at boot time, and
12854                  * can even allow for smooth boot transitions if the BIOS
12855                  * fb is large enough for the active pipe configuration.
12856                  */
12857                 if (dev_priv->display.get_plane_config) {
12858                         dev_priv->display.get_plane_config(crtc,
12859                                                            &crtc->plane_config);
12860                         /*
12861                          * If the fb is shared between multiple heads, we'll
12862                          * just get the first one.
12863                          */
12864                         intel_find_plane_obj(crtc, &crtc->plane_config);
12865                 }
12866         }
12867 }
12868
12869 static void intel_enable_pipe_a(struct drm_device *dev)
12870 {
12871         struct intel_connector *connector;
12872         struct drm_connector *crt = NULL;
12873         struct intel_load_detect_pipe load_detect_temp;
12874         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12875
12876         /* We can't just switch on the pipe A, we need to set things up with a
12877          * proper mode and output configuration. As a gross hack, enable pipe A
12878          * by enabling the load detect pipe once. */
12879         list_for_each_entry(connector,
12880                             &dev->mode_config.connector_list,
12881                             base.head) {
12882                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12883                         crt = &connector->base;
12884                         break;
12885                 }
12886         }
12887
12888         if (!crt)
12889                 return;
12890
12891         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12892                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12893 }
12894
12895 static bool
12896 intel_check_plane_mapping(struct intel_crtc *crtc)
12897 {
12898         struct drm_device *dev = crtc->base.dev;
12899         struct drm_i915_private *dev_priv = dev->dev_private;
12900         u32 reg, val;
12901
12902         if (INTEL_INFO(dev)->num_pipes == 1)
12903                 return true;
12904
12905         reg = DSPCNTR(!crtc->plane);
12906         val = I915_READ(reg);
12907
12908         if ((val & DISPLAY_PLANE_ENABLE) &&
12909             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12910                 return false;
12911
12912         return true;
12913 }
12914
12915 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12916 {
12917         struct drm_device *dev = crtc->base.dev;
12918         struct drm_i915_private *dev_priv = dev->dev_private;
12919         u32 reg;
12920
12921         /* Clear any frame start delays used for debugging left by the BIOS */
12922         reg = PIPECONF(crtc->config.cpu_transcoder);
12923         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12924
12925         /* restore vblank interrupts to correct state */
12926         if (crtc->active) {
12927                 update_scanline_offset(crtc);
12928                 drm_vblank_on(dev, crtc->pipe);
12929         } else
12930                 drm_vblank_off(dev, crtc->pipe);
12931
12932         /* We need to sanitize the plane -> pipe mapping first because this will
12933          * disable the crtc (and hence change the state) if it is wrong. Note
12934          * that gen4+ has a fixed plane -> pipe mapping.  */
12935         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12936                 struct intel_connector *connector;
12937                 bool plane;
12938
12939                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12940                               crtc->base.base.id);
12941
12942                 /* Pipe has the wrong plane attached and the plane is active.
12943                  * Temporarily change the plane mapping and disable everything
12944                  * ...  */
12945                 plane = crtc->plane;
12946                 crtc->plane = !plane;
12947                 crtc->primary_enabled = true;
12948                 dev_priv->display.crtc_disable(&crtc->base);
12949                 crtc->plane = plane;
12950
12951                 /* ... and break all links. */
12952                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12953                                     base.head) {
12954                         if (connector->encoder->base.crtc != &crtc->base)
12955                                 continue;
12956
12957                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12958                         connector->base.encoder = NULL;
12959                 }
12960                 /* multiple connectors may have the same encoder:
12961                  *  handle them and break crtc link separately */
12962                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12963                                     base.head)
12964                         if (connector->encoder->base.crtc == &crtc->base) {
12965                                 connector->encoder->base.crtc = NULL;
12966                                 connector->encoder->connectors_active = false;
12967                         }
12968
12969                 WARN_ON(crtc->active);
12970                 crtc->base.enabled = false;
12971         }
12972
12973         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12974             crtc->pipe == PIPE_A && !crtc->active) {
12975                 /* BIOS forgot to enable pipe A, this mostly happens after
12976                  * resume. Force-enable the pipe to fix this, the update_dpms
12977                  * call below we restore the pipe to the right state, but leave
12978                  * the required bits on. */
12979                 intel_enable_pipe_a(dev);
12980         }
12981
12982         /* Adjust the state of the output pipe according to whether we
12983          * have active connectors/encoders. */
12984         intel_crtc_update_dpms(&crtc->base);
12985
12986         if (crtc->active != crtc->base.enabled) {
12987                 struct intel_encoder *encoder;
12988
12989                 /* This can happen either due to bugs in the get_hw_state
12990                  * functions or because the pipe is force-enabled due to the
12991                  * pipe A quirk. */
12992                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12993                               crtc->base.base.id,
12994                               crtc->base.enabled ? "enabled" : "disabled",
12995                               crtc->active ? "enabled" : "disabled");
12996
12997                 crtc->base.enabled = crtc->active;
12998
12999                 /* Because we only establish the connector -> encoder ->
13000                  * crtc links if something is active, this means the
13001                  * crtc is now deactivated. Break the links. connector
13002                  * -> encoder links are only establish when things are
13003                  *  actually up, hence no need to break them. */
13004                 WARN_ON(crtc->active);
13005
13006                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13007                         WARN_ON(encoder->connectors_active);
13008                         encoder->base.crtc = NULL;
13009                 }
13010         }
13011
13012         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13013                 /*
13014                  * We start out with underrun reporting disabled to avoid races.
13015                  * For correct bookkeeping mark this on active crtcs.
13016                  *
13017                  * Also on gmch platforms we dont have any hardware bits to
13018                  * disable the underrun reporting. Which means we need to start
13019                  * out with underrun reporting disabled also on inactive pipes,
13020                  * since otherwise we'll complain about the garbage we read when
13021                  * e.g. coming up after runtime pm.
13022                  *
13023                  * No protection against concurrent access is required - at
13024                  * worst a fifo underrun happens which also sets this to false.
13025                  */
13026                 crtc->cpu_fifo_underrun_disabled = true;
13027                 crtc->pch_fifo_underrun_disabled = true;
13028         }
13029 }
13030
13031 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13032 {
13033         struct intel_connector *connector;
13034         struct drm_device *dev = encoder->base.dev;
13035
13036         /* We need to check both for a crtc link (meaning that the
13037          * encoder is active and trying to read from a pipe) and the
13038          * pipe itself being active. */
13039         bool has_active_crtc = encoder->base.crtc &&
13040                 to_intel_crtc(encoder->base.crtc)->active;
13041
13042         if (encoder->connectors_active && !has_active_crtc) {
13043                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13044                               encoder->base.base.id,
13045                               encoder->base.name);
13046
13047                 /* Connector is active, but has no active pipe. This is
13048                  * fallout from our resume register restoring. Disable
13049                  * the encoder manually again. */
13050                 if (encoder->base.crtc) {
13051                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13052                                       encoder->base.base.id,
13053                                       encoder->base.name);
13054                         encoder->disable(encoder);
13055                         if (encoder->post_disable)
13056                                 encoder->post_disable(encoder);
13057                 }
13058                 encoder->base.crtc = NULL;
13059                 encoder->connectors_active = false;
13060
13061                 /* Inconsistent output/port/pipe state happens presumably due to
13062                  * a bug in one of the get_hw_state functions. Or someplace else
13063                  * in our code, like the register restore mess on resume. Clamp
13064                  * things to off as a safer default. */
13065                 list_for_each_entry(connector,
13066                                     &dev->mode_config.connector_list,
13067                                     base.head) {
13068                         if (connector->encoder != encoder)
13069                                 continue;
13070                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13071                         connector->base.encoder = NULL;
13072                 }
13073         }
13074         /* Enabled encoders without active connectors will be fixed in
13075          * the crtc fixup. */
13076 }
13077
13078 void i915_redisable_vga_power_on(struct drm_device *dev)
13079 {
13080         struct drm_i915_private *dev_priv = dev->dev_private;
13081         u32 vga_reg = i915_vgacntrl_reg(dev);
13082
13083         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13084                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13085                 i915_disable_vga(dev);
13086         }
13087 }
13088
13089 void i915_redisable_vga(struct drm_device *dev)
13090 {
13091         struct drm_i915_private *dev_priv = dev->dev_private;
13092
13093         /* This function can be called both from intel_modeset_setup_hw_state or
13094          * at a very early point in our resume sequence, where the power well
13095          * structures are not yet restored. Since this function is at a very
13096          * paranoid "someone might have enabled VGA while we were not looking"
13097          * level, just check if the power well is enabled instead of trying to
13098          * follow the "don't touch the power well if we don't need it" policy
13099          * the rest of the driver uses. */
13100         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13101                 return;
13102
13103         i915_redisable_vga_power_on(dev);
13104 }
13105
13106 static bool primary_get_hw_state(struct intel_crtc *crtc)
13107 {
13108         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13109
13110         if (!crtc->active)
13111                 return false;
13112
13113         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13114 }
13115
13116 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13117 {
13118         struct drm_i915_private *dev_priv = dev->dev_private;
13119         enum pipe pipe;
13120         struct intel_crtc *crtc;
13121         struct intel_encoder *encoder;
13122         struct intel_connector *connector;
13123         int i;
13124
13125         for_each_intel_crtc(dev, crtc) {
13126                 memset(&crtc->config, 0, sizeof(crtc->config));
13127
13128                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13129
13130                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13131                                                                  &crtc->config);
13132
13133                 crtc->base.enabled = crtc->active;
13134                 crtc->primary_enabled = primary_get_hw_state(crtc);
13135
13136                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13137                               crtc->base.base.id,
13138                               crtc->active ? "enabled" : "disabled");
13139         }
13140
13141         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13142                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13143
13144                 pll->on = pll->get_hw_state(dev_priv, pll,
13145                                             &pll->config.hw_state);
13146                 pll->active = 0;
13147                 pll->config.crtc_mask = 0;
13148                 for_each_intel_crtc(dev, crtc) {
13149                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13150                                 pll->active++;
13151                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13152                         }
13153                 }
13154
13155                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13156                               pll->name, pll->config.crtc_mask, pll->on);
13157
13158                 if (pll->config.crtc_mask)
13159                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13160         }
13161
13162         for_each_intel_encoder(dev, encoder) {
13163                 pipe = 0;
13164
13165                 if (encoder->get_hw_state(encoder, &pipe)) {
13166                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13167                         encoder->base.crtc = &crtc->base;
13168                         encoder->get_config(encoder, &crtc->config);
13169                 } else {
13170                         encoder->base.crtc = NULL;
13171                 }
13172
13173                 encoder->connectors_active = false;
13174                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13175                               encoder->base.base.id,
13176                               encoder->base.name,
13177                               encoder->base.crtc ? "enabled" : "disabled",
13178                               pipe_name(pipe));
13179         }
13180
13181         list_for_each_entry(connector, &dev->mode_config.connector_list,
13182                             base.head) {
13183                 if (connector->get_hw_state(connector)) {
13184                         connector->base.dpms = DRM_MODE_DPMS_ON;
13185                         connector->encoder->connectors_active = true;
13186                         connector->base.encoder = &connector->encoder->base;
13187                 } else {
13188                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13189                         connector->base.encoder = NULL;
13190                 }
13191                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13192                               connector->base.base.id,
13193                               connector->base.name,
13194                               connector->base.encoder ? "enabled" : "disabled");
13195         }
13196 }
13197
13198 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13199  * and i915 state tracking structures. */
13200 void intel_modeset_setup_hw_state(struct drm_device *dev,
13201                                   bool force_restore)
13202 {
13203         struct drm_i915_private *dev_priv = dev->dev_private;
13204         enum pipe pipe;
13205         struct intel_crtc *crtc;
13206         struct intel_encoder *encoder;
13207         int i;
13208
13209         intel_modeset_readout_hw_state(dev);
13210
13211         /*
13212          * Now that we have the config, copy it to each CRTC struct
13213          * Note that this could go away if we move to using crtc_config
13214          * checking everywhere.
13215          */
13216         for_each_intel_crtc(dev, crtc) {
13217                 if (crtc->active && i915.fastboot) {
13218                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13219                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13220                                       crtc->base.base.id);
13221                         drm_mode_debug_printmodeline(&crtc->base.mode);
13222                 }
13223         }
13224
13225         /* HW state is read out, now we need to sanitize this mess. */
13226         for_each_intel_encoder(dev, encoder) {
13227                 intel_sanitize_encoder(encoder);
13228         }
13229
13230         for_each_pipe(dev_priv, pipe) {
13231                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13232                 intel_sanitize_crtc(crtc);
13233                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13234         }
13235
13236         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13237                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13238
13239                 if (!pll->on || pll->active)
13240                         continue;
13241
13242                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13243
13244                 pll->disable(dev_priv, pll);
13245                 pll->on = false;
13246         }
13247
13248         if (HAS_PCH_SPLIT(dev))
13249                 ilk_wm_get_hw_state(dev);
13250
13251         if (force_restore) {
13252                 i915_redisable_vga(dev);
13253
13254                 /*
13255                  * We need to use raw interfaces for restoring state to avoid
13256                  * checking (bogus) intermediate states.
13257                  */
13258                 for_each_pipe(dev_priv, pipe) {
13259                         struct drm_crtc *crtc =
13260                                 dev_priv->pipe_to_crtc_mapping[pipe];
13261
13262                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13263                                          crtc->primary->fb);
13264                 }
13265         } else {
13266                 intel_modeset_update_staged_output_state(dev);
13267         }
13268
13269         intel_modeset_check_state(dev);
13270 }
13271
13272 void intel_modeset_gem_init(struct drm_device *dev)
13273 {
13274         struct drm_crtc *c;
13275         struct drm_i915_gem_object *obj;
13276
13277         mutex_lock(&dev->struct_mutex);
13278         intel_init_gt_powersave(dev);
13279         mutex_unlock(&dev->struct_mutex);
13280
13281         intel_modeset_init_hw(dev);
13282
13283         intel_setup_overlay(dev);
13284
13285         /*
13286          * Make sure any fbs we allocated at startup are properly
13287          * pinned & fenced.  When we do the allocation it's too early
13288          * for this.
13289          */
13290         mutex_lock(&dev->struct_mutex);
13291         for_each_crtc(dev, c) {
13292                 obj = intel_fb_obj(c->primary->fb);
13293                 if (obj == NULL)
13294                         continue;
13295
13296                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13297                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13298                                   to_intel_crtc(c)->pipe);
13299                         drm_framebuffer_unreference(c->primary->fb);
13300                         c->primary->fb = NULL;
13301                 }
13302         }
13303         mutex_unlock(&dev->struct_mutex);
13304 }
13305
13306 void intel_connector_unregister(struct intel_connector *intel_connector)
13307 {
13308         struct drm_connector *connector = &intel_connector->base;
13309
13310         intel_panel_destroy_backlight(connector);
13311         drm_connector_unregister(connector);
13312 }
13313
13314 void intel_modeset_cleanup(struct drm_device *dev)
13315 {
13316         struct drm_i915_private *dev_priv = dev->dev_private;
13317         struct drm_connector *connector;
13318
13319         /*
13320          * Interrupts and polling as the first thing to avoid creating havoc.
13321          * Too much stuff here (turning of rps, connectors, ...) would
13322          * experience fancy races otherwise.
13323          */
13324         intel_irq_uninstall(dev_priv);
13325
13326         /*
13327          * Due to the hpd irq storm handling the hotplug work can re-arm the
13328          * poll handlers. Hence disable polling after hpd handling is shut down.
13329          */
13330         drm_kms_helper_poll_fini(dev);
13331
13332         mutex_lock(&dev->struct_mutex);
13333
13334         intel_unregister_dsm_handler();
13335
13336         intel_disable_fbc(dev);
13337
13338         intel_disable_gt_powersave(dev);
13339
13340         ironlake_teardown_rc6(dev);
13341
13342         mutex_unlock(&dev->struct_mutex);
13343
13344         /* flush any delayed tasks or pending work */
13345         flush_scheduled_work();
13346
13347         /* destroy the backlight and sysfs files before encoders/connectors */
13348         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13349                 struct intel_connector *intel_connector;
13350
13351                 intel_connector = to_intel_connector(connector);
13352                 intel_connector->unregister(intel_connector);
13353         }
13354
13355         drm_mode_config_cleanup(dev);
13356
13357         intel_cleanup_overlay(dev);
13358
13359         mutex_lock(&dev->struct_mutex);
13360         intel_cleanup_gt_powersave(dev);
13361         mutex_unlock(&dev->struct_mutex);
13362 }
13363
13364 /*
13365  * Return which encoder is currently attached for connector.
13366  */
13367 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13368 {
13369         return &intel_attached_encoder(connector)->base;
13370 }
13371
13372 void intel_connector_attach_encoder(struct intel_connector *connector,
13373                                     struct intel_encoder *encoder)
13374 {
13375         connector->encoder = encoder;
13376         drm_mode_connector_attach_encoder(&connector->base,
13377                                           &encoder->base);
13378 }
13379
13380 /*
13381  * set vga decode state - true == enable VGA decode
13382  */
13383 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13384 {
13385         struct drm_i915_private *dev_priv = dev->dev_private;
13386         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13387         u16 gmch_ctrl;
13388
13389         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13390                 DRM_ERROR("failed to read control word\n");
13391                 return -EIO;
13392         }
13393
13394         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13395                 return 0;
13396
13397         if (state)
13398                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13399         else
13400                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13401
13402         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13403                 DRM_ERROR("failed to write control word\n");
13404                 return -EIO;
13405         }
13406
13407         return 0;
13408 }
13409
13410 struct intel_display_error_state {
13411
13412         u32 power_well_driver;
13413
13414         int num_transcoders;
13415
13416         struct intel_cursor_error_state {
13417                 u32 control;
13418                 u32 position;
13419                 u32 base;
13420                 u32 size;
13421         } cursor[I915_MAX_PIPES];
13422
13423         struct intel_pipe_error_state {
13424                 bool power_domain_on;
13425                 u32 source;
13426                 u32 stat;
13427         } pipe[I915_MAX_PIPES];
13428
13429         struct intel_plane_error_state {
13430                 u32 control;
13431                 u32 stride;
13432                 u32 size;
13433                 u32 pos;
13434                 u32 addr;
13435                 u32 surface;
13436                 u32 tile_offset;
13437         } plane[I915_MAX_PIPES];
13438
13439         struct intel_transcoder_error_state {
13440                 bool power_domain_on;
13441                 enum transcoder cpu_transcoder;
13442
13443                 u32 conf;
13444
13445                 u32 htotal;
13446                 u32 hblank;
13447                 u32 hsync;
13448                 u32 vtotal;
13449                 u32 vblank;
13450                 u32 vsync;
13451         } transcoder[4];
13452 };
13453
13454 struct intel_display_error_state *
13455 intel_display_capture_error_state(struct drm_device *dev)
13456 {
13457         struct drm_i915_private *dev_priv = dev->dev_private;
13458         struct intel_display_error_state *error;
13459         int transcoders[] = {
13460                 TRANSCODER_A,
13461                 TRANSCODER_B,
13462                 TRANSCODER_C,
13463                 TRANSCODER_EDP,
13464         };
13465         int i;
13466
13467         if (INTEL_INFO(dev)->num_pipes == 0)
13468                 return NULL;
13469
13470         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13471         if (error == NULL)
13472                 return NULL;
13473
13474         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13475                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13476
13477         for_each_pipe(dev_priv, i) {
13478                 error->pipe[i].power_domain_on =
13479                         __intel_display_power_is_enabled(dev_priv,
13480                                                          POWER_DOMAIN_PIPE(i));
13481                 if (!error->pipe[i].power_domain_on)
13482                         continue;
13483
13484                 error->cursor[i].control = I915_READ(CURCNTR(i));
13485                 error->cursor[i].position = I915_READ(CURPOS(i));
13486                 error->cursor[i].base = I915_READ(CURBASE(i));
13487
13488                 error->plane[i].control = I915_READ(DSPCNTR(i));
13489                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13490                 if (INTEL_INFO(dev)->gen <= 3) {
13491                         error->plane[i].size = I915_READ(DSPSIZE(i));
13492                         error->plane[i].pos = I915_READ(DSPPOS(i));
13493                 }
13494                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13495                         error->plane[i].addr = I915_READ(DSPADDR(i));
13496                 if (INTEL_INFO(dev)->gen >= 4) {
13497                         error->plane[i].surface = I915_READ(DSPSURF(i));
13498                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13499                 }
13500
13501                 error->pipe[i].source = I915_READ(PIPESRC(i));
13502
13503                 if (HAS_GMCH_DISPLAY(dev))
13504                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13505         }
13506
13507         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13508         if (HAS_DDI(dev_priv->dev))
13509                 error->num_transcoders++; /* Account for eDP. */
13510
13511         for (i = 0; i < error->num_transcoders; i++) {
13512                 enum transcoder cpu_transcoder = transcoders[i];
13513
13514                 error->transcoder[i].power_domain_on =
13515                         __intel_display_power_is_enabled(dev_priv,
13516                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13517                 if (!error->transcoder[i].power_domain_on)
13518                         continue;
13519
13520                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13521
13522                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13523                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13524                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13525                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13526                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13527                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13528                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13529         }
13530
13531         return error;
13532 }
13533
13534 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13535
13536 void
13537 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13538                                 struct drm_device *dev,
13539                                 struct intel_display_error_state *error)
13540 {
13541         struct drm_i915_private *dev_priv = dev->dev_private;
13542         int i;
13543
13544         if (!error)
13545                 return;
13546
13547         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13548         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13549                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13550                            error->power_well_driver);
13551         for_each_pipe(dev_priv, i) {
13552                 err_printf(m, "Pipe [%d]:\n", i);
13553                 err_printf(m, "  Power: %s\n",
13554                            error->pipe[i].power_domain_on ? "on" : "off");
13555                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13556                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13557
13558                 err_printf(m, "Plane [%d]:\n", i);
13559                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13560                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13561                 if (INTEL_INFO(dev)->gen <= 3) {
13562                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13563                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13564                 }
13565                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13566                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13567                 if (INTEL_INFO(dev)->gen >= 4) {
13568                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13569                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13570                 }
13571
13572                 err_printf(m, "Cursor [%d]:\n", i);
13573                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13574                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13575                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13576         }
13577
13578         for (i = 0; i < error->num_transcoders; i++) {
13579                 err_printf(m, "CPU transcoder: %c\n",
13580                            transcoder_name(error->transcoder[i].cpu_transcoder));
13581                 err_printf(m, "  Power: %s\n",
13582                            error->transcoder[i].power_domain_on ? "on" : "off");
13583                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13584                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13585                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13586                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13587                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13588                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13589                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13590         }
13591 }
13592
13593 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13594 {
13595         struct intel_crtc *crtc;
13596
13597         for_each_intel_crtc(dev, crtc) {
13598                 struct intel_unpin_work *work;
13599
13600                 spin_lock_irq(&dev->event_lock);
13601
13602                 work = crtc->unpin_work;
13603
13604                 if (work && work->event &&
13605                     work->event->base.file_priv == file) {
13606                         kfree(work->event);
13607                         work->event = NULL;
13608                 }
13609
13610                 spin_unlock_irq(&dev->event_lock);
13611         }
13612 }