drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & SDVO_ENABLE) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1358                         return false;
1359         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1361                         return false;
1362         } else {
1363                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1364                         return false;
1365         }
1366         return true;
1367 }
1368
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370                               enum pipe pipe, u32 val)
1371 {
1372         if ((val & LVDS_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & ADPA_DAC_ENABLE) == 0)
1389                 return false;
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1392                         return false;
1393         } else {
1394                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1395                         return false;
1396         }
1397         return true;
1398 }
1399
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401                                    enum pipe pipe, int reg, u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, int reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              reg, pipe_name(pipe));
1420
1421         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1435
1436         reg = PCH_ADPA;
1437         val = I915_READ(reg);
1438         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         reg = PCH_LVDS;
1443         val = I915_READ(reg);
1444         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1451 }
1452
1453 static void intel_init_dpio(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!IS_VALLEYVIEW(dev))
1458                 return;
1459
1460         /*
1461          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462          * CHV x1 PHY (DP/HDMI D)
1463          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1464          */
1465         if (IS_CHERRYVIEW(dev)) {
1466                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1468         } else {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1470         }
1471 }
1472
1473 static void intel_reset_dpio(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         if (!IS_VALLEYVIEW(dev))
1478                 return;
1479
1480         /*
1481          * Enable the CRI clock source so we can get at the display and the
1482          * reference clock for VGA hotplug / manual detection.
1483          */
1484         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485                    DPLL_REFA_CLK_ENABLE_VLV |
1486                    DPLL_INTEGRATED_CRI_CLK_VLV);
1487
1488         if (IS_CHERRYVIEW(dev)) {
1489                 enum dpio_phy phy;
1490                 u32 val;
1491
1492                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493                         /* Poll for phypwrgood signal */
1494                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495                                                 PHY_POWERGOOD(phy), 1))
1496                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1497
1498                         /*
1499                          * Deassert common lane reset for PHY.
1500                          *
1501                          * This should only be done on init and resume from S3
1502                          * with both PLLs disabled, or we risk losing DPIO and
1503                          * PLL synchronization.
1504                          */
1505                         val = I915_READ(DISPLAY_PHY_CONTROL);
1506                         I915_WRITE(DISPLAY_PHY_CONTROL,
1507                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1508                 }
1509
1510         } else {
1511                 /*
1512                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1514                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515                  *   b. The other bits such as sfr settings / modesel may all
1516                  *      be set to 0.
1517                  *
1518                  * This should only be done on init and resume from S3 with
1519                  * both PLLs disabled, or we risk losing DPIO and PLL
1520                  * synchronization.
1521                  */
1522                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1523         }
1524 }
1525
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1527 {
1528         struct drm_device *dev = crtc->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         int reg = DPLL(crtc->pipe);
1531         u32 dpll = crtc->config.dpll_hw_state.dpll;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         /* No really, not for ILK+ */
1536         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1537
1538         /* PLL is protected by panel, make sure we can write it */
1539         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540                 assert_panel_unlocked(dev_priv, crtc->pipe);
1541
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150);
1545
1546         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1548
1549         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550         POSTING_READ(DPLL_MD(crtc->pipe));
1551
1552         /* We do this three times for luck */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         int dpll = DPLL(crtc->pipe);
1571         u32 tmp;
1572
1573         assert_pipe_disabled(dev_priv, crtc->pipe);
1574
1575         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1576
1577         mutex_lock(&dev_priv->dpio_lock);
1578
1579         /* Enable back the 10bit clock to display controller */
1580         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581         tmp |= DPIO_DCLKP_EN;
1582         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584         /*
1585          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586          */
1587         udelay(1);
1588
1589         /* Enable PLL */
1590         tmp = I915_READ(dpll);
1591         tmp |= DPLL_VCO_ENABLE;
1592         I915_WRITE(dpll, tmp);
1593
1594         /* Check PLL is locked */
1595         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597
1598         /* Deassert soft data lane reset*/
1599         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1602
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         int dpll = DPLL(pipe);
1696         u32 val;
1697
1698         /* Set PLL en = 0 */
1699         val = I915_READ(dpll);
1700         val &= ~DPLL_VCO_ENABLE;
1701         I915_WRITE(dpll, val);
1702
1703 }
1704
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706                 struct intel_digital_port *dport)
1707 {
1708         u32 port_mask;
1709         int dpll_reg;
1710
1711         switch (dport->port) {
1712         case PORT_B:
1713                 port_mask = DPLL_PORTB_READY_MASK;
1714                 dpll_reg = DPLL(0);
1715                 break;
1716         case PORT_C:
1717                 port_mask = DPLL_PORTC_READY_MASK;
1718                 dpll_reg = DPLL(0);
1719                 break;
1720         case PORT_D:
1721                 port_mask = DPLL_PORTD_READY_MASK;
1722                 dpll_reg = DPIO_PHY_STATUS;
1723                 break;
1724         default:
1725                 BUG();
1726         }
1727
1728         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730                      port_name(dport->port), I915_READ(dpll_reg));
1731 }
1732
1733 /**
1734  * ironlake_enable_shared_dpll - enable PCH PLL
1735  * @dev_priv: i915 private structure
1736  * @pipe: pipe PLL to enable
1737  *
1738  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739  * drives the transcoder clock.
1740  */
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->base.dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1746
1747         /* PCH PLLs only available on ILK, SNB and IVB */
1748         BUG_ON(INTEL_INFO(dev)->gen < 5);
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         if (WARN_ON(pll->refcount == 0))
1753                 return;
1754
1755         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756                       pll->name, pll->active, pll->on,
1757                       crtc->base.base.id);
1758
1759         if (pll->active++) {
1760                 WARN_ON(!pll->on);
1761                 assert_shared_dpll_enabled(dev_priv, pll);
1762                 return;
1763         }
1764         WARN_ON(pll->on);
1765
1766         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767         pll->enable(dev_priv, pll);
1768         pll->on = true;
1769 }
1770
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1772 {
1773         struct drm_device *dev = crtc->base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776
1777         /* PCH only available on ILK+ */
1778         BUG_ON(INTEL_INFO(dev)->gen < 5);
1779         if (WARN_ON(pll == NULL))
1780                return;
1781
1782         if (WARN_ON(pll->refcount == 0))
1783                 return;
1784
1785         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786                       pll->name, pll->active, pll->on,
1787                       crtc->base.base.id);
1788
1789         if (WARN_ON(pll->active == 0)) {
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791                 return;
1792         }
1793
1794         assert_shared_dpll_enabled(dev_priv, pll);
1795         WARN_ON(!pll->on);
1796         if (--pll->active)
1797                 return;
1798
1799         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800         pll->disable(dev_priv, pll);
1801         pll->on = false;
1802 }
1803
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1805                                            enum pipe pipe)
1806 {
1807         struct drm_device *dev = dev_priv->dev;
1808         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         uint32_t reg, val, pipeconf_val;
1811
1812         /* PCH only available on ILK+ */
1813         BUG_ON(INTEL_INFO(dev)->gen < 5);
1814
1815         /* Make sure PCH DPLL is enabled */
1816         assert_shared_dpll_enabled(dev_priv,
1817                                    intel_crtc_to_shared_dpll(intel_crtc));
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, pipe);
1821         assert_fdi_rx_enabled(dev_priv, pipe);
1822
1823         if (HAS_PCH_CPT(dev)) {
1824                 /* Workaround: Set the timing override bit before enabling the
1825                  * pch transcoder. */
1826                 reg = TRANS_CHICKEN2(pipe);
1827                 val = I915_READ(reg);
1828                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829                 I915_WRITE(reg, val);
1830         }
1831
1832         reg = PCH_TRANSCONF(pipe);
1833         val = I915_READ(reg);
1834         pipeconf_val = I915_READ(PIPECONF(pipe));
1835
1836         if (HAS_PCH_IBX(dev_priv->dev)) {
1837                 /*
1838                  * make the BPC in transcoder be consistent with
1839                  * that in pipeconf reg.
1840                  */
1841                 val &= ~PIPECONF_BPC_MASK;
1842                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1843         }
1844
1845         val &= ~TRANS_INTERLACE_MASK;
1846         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847                 if (HAS_PCH_IBX(dev_priv->dev) &&
1848                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849                         val |= TRANS_LEGACY_INTERLACED_ILK;
1850                 else
1851                         val |= TRANS_INTERLACED;
1852         else
1853                 val |= TRANS_PROGRESSIVE;
1854
1855         I915_WRITE(reg, val | TRANS_ENABLE);
1856         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1858 }
1859
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861                                       enum transcoder cpu_transcoder)
1862 {
1863         u32 val, pipeconf_val;
1864
1865         /* PCH only available on ILK+ */
1866         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1867
1868         /* FDI must be feeding us bits for PCH ports */
1869         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1871
1872         /* Workaround: set timing override bit. */
1873         val = I915_READ(_TRANSA_CHICKEN2);
1874         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875         I915_WRITE(_TRANSA_CHICKEN2, val);
1876
1877         val = TRANS_ENABLE;
1878         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1879
1880         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881             PIPECONF_INTERLACED_ILK)
1882                 val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(LPT_TRANSCONF, val);
1887         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("Failed to enable PCH transcoder\n");
1889 }
1890
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                             enum pipe pipe)
1893 {
1894         struct drm_device *dev = dev_priv->dev;
1895         uint32_t reg, val;
1896
1897         /* FDI relies on the transcoder */
1898         assert_fdi_tx_disabled(dev_priv, pipe);
1899         assert_fdi_rx_disabled(dev_priv, pipe);
1900
1901         /* Ports must be off as well */
1902         assert_pch_ports_disabled(dev_priv, pipe);
1903
1904         reg = PCH_TRANSCONF(pipe);
1905         val = I915_READ(reg);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(reg, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1911
1912         if (!HAS_PCH_IBX(dev)) {
1913                 /* Workaround: Clear the timing override chicken bit again. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919 }
1920
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1922 {
1923         u32 val;
1924
1925         val = I915_READ(LPT_TRANSCONF);
1926         val &= ~TRANS_ENABLE;
1927         I915_WRITE(LPT_TRANSCONF, val);
1928         /* wait for PCH transcoder off, transcoder state */
1929         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930                 DRM_ERROR("Failed to disable PCH transcoder\n");
1931
1932         /* Workaround: clear timing override bit. */
1933         val = I915_READ(_TRANSA_CHICKEN2);
1934         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935         I915_WRITE(_TRANSA_CHICKEN2, val);
1936 }
1937
1938 /**
1939  * intel_enable_pipe - enable a pipe, asserting requirements
1940  * @crtc: crtc responsible for the pipe
1941  *
1942  * Enable @crtc's pipe, making sure that various hardware specific requirements
1943  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1944  */
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1946 {
1947         struct drm_device *dev = crtc->base.dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         enum pipe pipe = crtc->pipe;
1950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1951                                                                       pipe);
1952         enum pipe pch_transcoder;
1953         int reg;
1954         u32 val;
1955
1956         assert_planes_disabled(dev_priv, pipe);
1957         assert_cursor_disabled(dev_priv, pipe);
1958         assert_sprites_disabled(dev_priv, pipe);
1959
1960         if (HAS_PCH_LPT(dev_priv->dev))
1961                 pch_transcoder = TRANSCODER_A;
1962         else
1963                 pch_transcoder = pipe;
1964
1965         /*
1966          * A pipe without a PLL won't actually be able to drive bits from
1967          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1968          * need the check.
1969          */
1970         if (!HAS_PCH_SPLIT(dev_priv->dev))
1971                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972                         assert_dsi_pll_enabled(dev_priv);
1973                 else
1974                         assert_pll_enabled(dev_priv, pipe);
1975         else {
1976                 if (crtc->config.has_pch_encoder) {
1977                         /* if driving the PCH, we need FDI enabled */
1978                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979                         assert_fdi_tx_pll_enabled(dev_priv,
1980                                                   (enum pipe) cpu_transcoder);
1981                 }
1982                 /* FIXME: assert CPU port conditions for SNB+ */
1983         }
1984
1985         reg = PIPECONF(cpu_transcoder);
1986         val = I915_READ(reg);
1987         if (val & PIPECONF_ENABLE) {
1988                 WARN_ON(!(pipe == PIPE_A &&
1989                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1990                 return;
1991         }
1992
1993         I915_WRITE(reg, val | PIPECONF_ENABLE);
1994         POSTING_READ(reg);
1995 }
1996
1997 /**
1998  * intel_disable_pipe - disable a pipe, asserting requirements
1999  * @dev_priv: i915 private structure
2000  * @pipe: pipe to disable
2001  *
2002  * Disable @pipe, making sure that various hardware specific requirements
2003  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2004  *
2005  * @pipe should be %PIPE_A or %PIPE_B.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2010                                enum pipe pipe)
2011 {
2012         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013                                                                       pipe);
2014         int reg;
2015         u32 val;
2016
2017         /*
2018          * Make sure planes won't keep trying to pump pixels to us,
2019          * or we might hang the display.
2020          */
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024
2025         /* Don't disable pipe A or pipe A PLLs if needed */
2026         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2027                 return;
2028
2029         reg = PIPECONF(cpu_transcoder);
2030         val = I915_READ(reg);
2031         if ((val & PIPECONF_ENABLE) == 0)
2032                 return;
2033
2034         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2036 }
2037
2038 /*
2039  * Plane regs are double buffered, going from enabled->disabled needs a
2040  * trigger in order to latch.  The display address reg provides this.
2041  */
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2043                                enum plane plane)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2047
2048         I915_WRITE(reg, I915_READ(reg));
2049         POSTING_READ(reg);
2050 }
2051
2052 /**
2053  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054  * @dev_priv: i915 private structure
2055  * @plane: plane to enable
2056  * @pipe: pipe being fed
2057  *
2058  * Enable @plane on @pipe, making sure that @pipe is running first.
2059  */
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061                                           enum plane plane, enum pipe pipe)
2062 {
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2065         int reg;
2066         u32 val;
2067
2068         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069         assert_pipe_enabled(dev_priv, pipe);
2070
2071         if (intel_crtc->primary_enabled)
2072                 return;
2073
2074         intel_crtc->primary_enabled = true;
2075
2076         reg = DSPCNTR(plane);
2077         val = I915_READ(reg);
2078         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2079
2080         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081         intel_flush_primary_plane(dev_priv, plane);
2082         intel_wait_for_vblank(dev_priv->dev, pipe);
2083 }
2084
2085 /**
2086  * intel_disable_primary_hw_plane - disable the primary hardware plane
2087  * @dev_priv: i915 private structure
2088  * @plane: plane to disable
2089  * @pipe: pipe consuming the data
2090  *
2091  * Disable @plane; should be an independent operation.
2092  */
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094                                            enum plane plane, enum pipe pipe)
2095 {
2096         struct intel_crtc *intel_crtc =
2097                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2098         int reg;
2099         u32 val;
2100
2101         if (!intel_crtc->primary_enabled)
2102                 return;
2103
2104         intel_crtc->primary_enabled = false;
2105
2106         reg = DSPCNTR(plane);
2107         val = I915_READ(reg);
2108         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2109
2110         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111         intel_flush_primary_plane(dev_priv, plane);
2112         intel_wait_for_vblank(dev_priv->dev, pipe);
2113 }
2114
2115 static bool need_vtd_wa(struct drm_device *dev)
2116 {
2117 #ifdef CONFIG_INTEL_IOMMU
2118         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2119                 return true;
2120 #endif
2121         return false;
2122 }
2123
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2125 {
2126         int tile_height;
2127
2128         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129         return ALIGN(height, tile_height);
2130 }
2131
2132 int
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134                            struct drm_i915_gem_object *obj,
2135                            struct intel_ring_buffer *pipelined)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 alignment;
2139         int ret;
2140
2141         switch (obj->tiling_mode) {
2142         case I915_TILING_NONE:
2143                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144                         alignment = 128 * 1024;
2145                 else if (INTEL_INFO(dev)->gen >= 4)
2146                         alignment = 4 * 1024;
2147                 else
2148                         alignment = 64 * 1024;
2149                 break;
2150         case I915_TILING_X:
2151                 /* pin() will align the object as required by fence */
2152                 alignment = 0;
2153                 break;
2154         case I915_TILING_Y:
2155                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2156                 return -EINVAL;
2157         default:
2158                 BUG();
2159         }
2160
2161         /* Note that the w/a also requires 64 PTE of padding following the
2162          * bo. We currently fill all unused PTE with the shadow page and so
2163          * we should always have valid PTE following the scanout preventing
2164          * the VT-d warning.
2165          */
2166         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167                 alignment = 256 * 1024;
2168
2169         dev_priv->mm.interruptible = false;
2170         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2171         if (ret)
2172                 goto err_interruptible;
2173
2174         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175          * fence, whereas 965+ only requires a fence if using
2176          * framebuffer compression.  For simplicity, we always install
2177          * a fence as the cost is not that onerous.
2178          */
2179         ret = i915_gem_object_get_fence(obj);
2180         if (ret)
2181                 goto err_unpin;
2182
2183         i915_gem_object_pin_fence(obj);
2184
2185         dev_priv->mm.interruptible = true;
2186         return 0;
2187
2188 err_unpin:
2189         i915_gem_object_unpin_from_display_plane(obj);
2190 err_interruptible:
2191         dev_priv->mm.interruptible = true;
2192         return ret;
2193 }
2194
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2196 {
2197         i915_gem_object_unpin_fence(obj);
2198         i915_gem_object_unpin_from_display_plane(obj);
2199 }
2200
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202  * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204                                              unsigned int tiling_mode,
2205                                              unsigned int cpp,
2206                                              unsigned int pitch)
2207 {
2208         if (tiling_mode != I915_TILING_NONE) {
2209                 unsigned int tile_rows, tiles;
2210
2211                 tile_rows = *y / 8;
2212                 *y %= 8;
2213
2214                 tiles = *x / (512/cpp);
2215                 *x %= 512/cpp;
2216
2217                 return tile_rows * pitch * 8 + tiles * 4096;
2218         } else {
2219                 unsigned int offset;
2220
2221                 offset = *y * pitch + *x * cpp;
2222                 *y = 0;
2223                 *x = (offset & 4095) / cpp;
2224                 return offset & -4096;
2225         }
2226 }
2227
2228 int intel_format_to_fourcc(int format)
2229 {
2230         switch (format) {
2231         case DISPPLANE_8BPP:
2232                 return DRM_FORMAT_C8;
2233         case DISPPLANE_BGRX555:
2234                 return DRM_FORMAT_XRGB1555;
2235         case DISPPLANE_BGRX565:
2236                 return DRM_FORMAT_RGB565;
2237         default:
2238         case DISPPLANE_BGRX888:
2239                 return DRM_FORMAT_XRGB8888;
2240         case DISPPLANE_RGBX888:
2241                 return DRM_FORMAT_XBGR8888;
2242         case DISPPLANE_BGRX101010:
2243                 return DRM_FORMAT_XRGB2101010;
2244         case DISPPLANE_RGBX101010:
2245                 return DRM_FORMAT_XBGR2101010;
2246         }
2247 }
2248
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250                                   struct intel_plane_config *plane_config)
2251 {
2252         struct drm_device *dev = crtc->base.dev;
2253         struct drm_i915_gem_object *obj = NULL;
2254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255         u32 base = plane_config->base;
2256
2257         if (plane_config->size == 0)
2258                 return false;
2259
2260         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261                                                              plane_config->size);
2262         if (!obj)
2263                 return false;
2264
2265         if (plane_config->tiled) {
2266                 obj->tiling_mode = I915_TILING_X;
2267                 obj->stride = crtc->base.primary->fb->pitches[0];
2268         }
2269
2270         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271         mode_cmd.width = crtc->base.primary->fb->width;
2272         mode_cmd.height = crtc->base.primary->fb->height;
2273         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2274
2275         mutex_lock(&dev->struct_mutex);
2276
2277         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2278                                    &mode_cmd, obj)) {
2279                 DRM_DEBUG_KMS("intel fb init failed\n");
2280                 goto out_unref_obj;
2281         }
2282
2283         mutex_unlock(&dev->struct_mutex);
2284
2285         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2286         return true;
2287
2288 out_unref_obj:
2289         drm_gem_object_unreference(&obj->base);
2290         mutex_unlock(&dev->struct_mutex);
2291         return false;
2292 }
2293
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295                                  struct intel_plane_config *plane_config)
2296 {
2297         struct drm_device *dev = intel_crtc->base.dev;
2298         struct drm_crtc *c;
2299         struct intel_crtc *i;
2300         struct intel_framebuffer *fb;
2301
2302         if (!intel_crtc->base.primary->fb)
2303                 return;
2304
2305         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2306                 return;
2307
2308         kfree(intel_crtc->base.primary->fb);
2309         intel_crtc->base.primary->fb = NULL;
2310
2311         /*
2312          * Failed to alloc the obj, check to see if we should share
2313          * an fb with another CRTC instead
2314          */
2315         for_each_crtc(dev, c) {
2316                 i = to_intel_crtc(c);
2317
2318                 if (c == &intel_crtc->base)
2319                         continue;
2320
2321                 if (!i->active || !c->primary->fb)
2322                         continue;
2323
2324                 fb = to_intel_framebuffer(c->primary->fb);
2325                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326                         drm_framebuffer_reference(c->primary->fb);
2327                         intel_crtc->base.primary->fb = c->primary->fb;
2328                         break;
2329                 }
2330         }
2331 }
2332
2333 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2334                                      struct drm_framebuffer *fb,
2335                                      int x, int y)
2336 {
2337         struct drm_device *dev = crtc->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340         struct intel_framebuffer *intel_fb;
2341         struct drm_i915_gem_object *obj;
2342         int plane = intel_crtc->plane;
2343         unsigned long linear_offset;
2344         u32 dspcntr;
2345         u32 reg;
2346
2347         intel_fb = to_intel_framebuffer(fb);
2348         obj = intel_fb->obj;
2349
2350         reg = DSPCNTR(plane);
2351         dspcntr = I915_READ(reg);
2352         /* Mask out pixel format bits in case we change it */
2353         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354         switch (fb->pixel_format) {
2355         case DRM_FORMAT_C8:
2356                 dspcntr |= DISPPLANE_8BPP;
2357                 break;
2358         case DRM_FORMAT_XRGB1555:
2359         case DRM_FORMAT_ARGB1555:
2360                 dspcntr |= DISPPLANE_BGRX555;
2361                 break;
2362         case DRM_FORMAT_RGB565:
2363                 dspcntr |= DISPPLANE_BGRX565;
2364                 break;
2365         case DRM_FORMAT_XRGB8888:
2366         case DRM_FORMAT_ARGB8888:
2367                 dspcntr |= DISPPLANE_BGRX888;
2368                 break;
2369         case DRM_FORMAT_XBGR8888:
2370         case DRM_FORMAT_ABGR8888:
2371                 dspcntr |= DISPPLANE_RGBX888;
2372                 break;
2373         case DRM_FORMAT_XRGB2101010:
2374         case DRM_FORMAT_ARGB2101010:
2375                 dspcntr |= DISPPLANE_BGRX101010;
2376                 break;
2377         case DRM_FORMAT_XBGR2101010:
2378         case DRM_FORMAT_ABGR2101010:
2379                 dspcntr |= DISPPLANE_RGBX101010;
2380                 break;
2381         default:
2382                 BUG();
2383         }
2384
2385         if (INTEL_INFO(dev)->gen >= 4) {
2386                 if (obj->tiling_mode != I915_TILING_NONE)
2387                         dspcntr |= DISPPLANE_TILED;
2388                 else
2389                         dspcntr &= ~DISPPLANE_TILED;
2390         }
2391
2392         if (IS_G4X(dev))
2393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2394
2395         I915_WRITE(reg, dspcntr);
2396
2397         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2398
2399         if (INTEL_INFO(dev)->gen >= 4) {
2400                 intel_crtc->dspaddr_offset =
2401                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402                                                        fb->bits_per_pixel / 8,
2403                                                        fb->pitches[0]);
2404                 linear_offset -= intel_crtc->dspaddr_offset;
2405         } else {
2406                 intel_crtc->dspaddr_offset = linear_offset;
2407         }
2408
2409         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2411                       fb->pitches[0]);
2412         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413         if (INTEL_INFO(dev)->gen >= 4) {
2414                 I915_WRITE(DSPSURF(plane),
2415                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2418         } else
2419                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2420         POSTING_READ(reg);
2421
2422         return 0;
2423 }
2424
2425 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2426                                          struct drm_framebuffer *fb,
2427                                          int x, int y)
2428 {
2429         struct drm_device *dev = crtc->dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432         struct intel_framebuffer *intel_fb;
2433         struct drm_i915_gem_object *obj;
2434         int plane = intel_crtc->plane;
2435         unsigned long linear_offset;
2436         u32 dspcntr;
2437         u32 reg;
2438
2439         intel_fb = to_intel_framebuffer(fb);
2440         obj = intel_fb->obj;
2441
2442         reg = DSPCNTR(plane);
2443         dspcntr = I915_READ(reg);
2444         /* Mask out pixel format bits in case we change it */
2445         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2446         switch (fb->pixel_format) {
2447         case DRM_FORMAT_C8:
2448                 dspcntr |= DISPPLANE_8BPP;
2449                 break;
2450         case DRM_FORMAT_RGB565:
2451                 dspcntr |= DISPPLANE_BGRX565;
2452                 break;
2453         case DRM_FORMAT_XRGB8888:
2454         case DRM_FORMAT_ARGB8888:
2455                 dspcntr |= DISPPLANE_BGRX888;
2456                 break;
2457         case DRM_FORMAT_XBGR8888:
2458         case DRM_FORMAT_ABGR8888:
2459                 dspcntr |= DISPPLANE_RGBX888;
2460                 break;
2461         case DRM_FORMAT_XRGB2101010:
2462         case DRM_FORMAT_ARGB2101010:
2463                 dspcntr |= DISPPLANE_BGRX101010;
2464                 break;
2465         case DRM_FORMAT_XBGR2101010:
2466         case DRM_FORMAT_ABGR2101010:
2467                 dspcntr |= DISPPLANE_RGBX101010;
2468                 break;
2469         default:
2470                 BUG();
2471         }
2472
2473         if (obj->tiling_mode != I915_TILING_NONE)
2474                 dspcntr |= DISPPLANE_TILED;
2475         else
2476                 dspcntr &= ~DISPPLANE_TILED;
2477
2478         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2480         else
2481                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2482
2483         I915_WRITE(reg, dspcntr);
2484
2485         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2486         intel_crtc->dspaddr_offset =
2487                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2488                                                fb->bits_per_pixel / 8,
2489                                                fb->pitches[0]);
2490         linear_offset -= intel_crtc->dspaddr_offset;
2491
2492         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494                       fb->pitches[0]);
2495         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496         I915_WRITE(DSPSURF(plane),
2497                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2498         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2499                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2500         } else {
2501                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2503         }
2504         POSTING_READ(reg);
2505
2506         return 0;
2507 }
2508
2509 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2510 static int
2511 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2512                            int x, int y, enum mode_set_atomic state)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516
2517         if (dev_priv->display.disable_fbc)
2518                 dev_priv->display.disable_fbc(dev);
2519         intel_increase_pllclock(crtc);
2520
2521         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 }
2523
2524 void intel_display_handle_reset(struct drm_device *dev)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         struct drm_crtc *crtc;
2528
2529         /*
2530          * Flips in the rings have been nuked by the reset,
2531          * so complete all pending flips so that user space
2532          * will get its events and not get stuck.
2533          *
2534          * Also update the base address of all primary
2535          * planes to the the last fb to make sure we're
2536          * showing the correct fb after a reset.
2537          *
2538          * Need to make two loops over the crtcs so that we
2539          * don't try to grab a crtc mutex before the
2540          * pending_flip_queue really got woken up.
2541          */
2542
2543         for_each_crtc(dev, crtc) {
2544                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545                 enum plane plane = intel_crtc->plane;
2546
2547                 intel_prepare_page_flip(dev, plane);
2548                 intel_finish_page_flip_plane(dev, plane);
2549         }
2550
2551         for_each_crtc(dev, crtc) {
2552                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2553
2554                 mutex_lock(&crtc->mutex);
2555                 /*
2556                  * FIXME: Once we have proper support for primary planes (and
2557                  * disabling them without disabling the entire crtc) allow again
2558                  * a NULL crtc->primary->fb.
2559                  */
2560                 if (intel_crtc->active && crtc->primary->fb)
2561                         dev_priv->display.update_primary_plane(crtc,
2562                                                                crtc->primary->fb,
2563                                                                crtc->x,
2564                                                                crtc->y);
2565                 mutex_unlock(&crtc->mutex);
2566         }
2567 }
2568
2569 static int
2570 intel_finish_fb(struct drm_framebuffer *old_fb)
2571 {
2572         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2573         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2574         bool was_interruptible = dev_priv->mm.interruptible;
2575         int ret;
2576
2577         /* Big Hammer, we also need to ensure that any pending
2578          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2579          * current scanout is retired before unpinning the old
2580          * framebuffer.
2581          *
2582          * This should only fail upon a hung GPU, in which case we
2583          * can safely continue.
2584          */
2585         dev_priv->mm.interruptible = false;
2586         ret = i915_gem_object_finish_gpu(obj);
2587         dev_priv->mm.interruptible = was_interruptible;
2588
2589         return ret;
2590 }
2591
2592 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         unsigned long flags;
2598         bool pending;
2599
2600         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2601             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2602                 return false;
2603
2604         spin_lock_irqsave(&dev->event_lock, flags);
2605         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2606         spin_unlock_irqrestore(&dev->event_lock, flags);
2607
2608         return pending;
2609 }
2610
2611 static int
2612 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2613                     struct drm_framebuffer *fb)
2614 {
2615         struct drm_device *dev = crtc->dev;
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         struct drm_framebuffer *old_fb;
2619         int ret;
2620
2621         if (intel_crtc_has_pending_flip(crtc)) {
2622                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2623                 return -EBUSY;
2624         }
2625
2626         /* no fb bound */
2627         if (!fb) {
2628                 DRM_ERROR("No FB bound\n");
2629                 return 0;
2630         }
2631
2632         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2633                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2634                           plane_name(intel_crtc->plane),
2635                           INTEL_INFO(dev)->num_pipes);
2636                 return -EINVAL;
2637         }
2638
2639         mutex_lock(&dev->struct_mutex);
2640         ret = intel_pin_and_fence_fb_obj(dev,
2641                                          to_intel_framebuffer(fb)->obj,
2642                                          NULL);
2643         mutex_unlock(&dev->struct_mutex);
2644         if (ret != 0) {
2645                 DRM_ERROR("pin & fence failed\n");
2646                 return ret;
2647         }
2648
2649         /*
2650          * Update pipe size and adjust fitter if needed: the reason for this is
2651          * that in compute_mode_changes we check the native mode (not the pfit
2652          * mode) to see if we can flip rather than do a full mode set. In the
2653          * fastboot case, we'll flip, but if we don't update the pipesrc and
2654          * pfit state, we'll end up with a big fb scanned out into the wrong
2655          * sized surface.
2656          *
2657          * To fix this properly, we need to hoist the checks up into
2658          * compute_mode_changes (or above), check the actual pfit state and
2659          * whether the platform allows pfit disable with pipe active, and only
2660          * then update the pipesrc and pfit state, even on the flip path.
2661          */
2662         if (i915.fastboot) {
2663                 const struct drm_display_mode *adjusted_mode =
2664                         &intel_crtc->config.adjusted_mode;
2665
2666                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2667                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2668                            (adjusted_mode->crtc_vdisplay - 1));
2669                 if (!intel_crtc->config.pch_pfit.enabled &&
2670                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2671                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2672                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2673                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2674                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2675                 }
2676                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2677                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2678         }
2679
2680         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2681         if (ret) {
2682                 mutex_lock(&dev->struct_mutex);
2683                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2684                 mutex_unlock(&dev->struct_mutex);
2685                 DRM_ERROR("failed to update base address\n");
2686                 return ret;
2687         }
2688
2689         old_fb = crtc->primary->fb;
2690         crtc->primary->fb = fb;
2691         crtc->x = x;
2692         crtc->y = y;
2693
2694         if (old_fb) {
2695                 if (intel_crtc->active && old_fb != fb)
2696                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2697                 mutex_lock(&dev->struct_mutex);
2698                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2699                 mutex_unlock(&dev->struct_mutex);
2700         }
2701
2702         mutex_lock(&dev->struct_mutex);
2703         intel_update_fbc(dev);
2704         intel_edp_psr_update(dev);
2705         mutex_unlock(&dev->struct_mutex);
2706
2707         return 0;
2708 }
2709
2710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* enable normal train */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         if (IS_IVYBRIDGE(dev)) {
2722                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2724         } else {
2725                 temp &= ~FDI_LINK_TRAIN_NONE;
2726                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2727         }
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_NONE;
2738         }
2739         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2740
2741         /* wait one idle pattern time */
2742         POSTING_READ(reg);
2743         udelay(1000);
2744
2745         /* IVB wants error correction enabled */
2746         if (IS_IVYBRIDGE(dev))
2747                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2748                            FDI_FE_ERRC_ENABLE);
2749 }
2750
2751 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2752 {
2753         return crtc->base.enabled && crtc->active &&
2754                 crtc->config.has_pch_encoder;
2755 }
2756
2757 static void ivb_modeset_global_resources(struct drm_device *dev)
2758 {
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         struct intel_crtc *pipe_B_crtc =
2761                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2762         struct intel_crtc *pipe_C_crtc =
2763                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2764         uint32_t temp;
2765
2766         /*
2767          * When everything is off disable fdi C so that we could enable fdi B
2768          * with all lanes. Note that we don't care about enabled pipes without
2769          * an enabled pch encoder.
2770          */
2771         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2772             !pipe_has_enabled_pch(pipe_C_crtc)) {
2773                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2774                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2775
2776                 temp = I915_READ(SOUTH_CHICKEN1);
2777                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2778                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2779                 I915_WRITE(SOUTH_CHICKEN1, temp);
2780         }
2781 }
2782
2783 /* The FDI link training functions for ILK/Ibexpeak. */
2784 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp, tries;
2791
2792         /* FDI needs bits from pipe first */
2793         assert_pipe_enabled(dev_priv, pipe);
2794
2795         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2796            for train result */
2797         reg = FDI_RX_IMR(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_RX_SYMBOL_LOCK;
2800         temp &= ~FDI_RX_BIT_LOCK;
2801         I915_WRITE(reg, temp);
2802         I915_READ(reg);
2803         udelay(150);
2804
2805         /* enable CPU FDI TX and PCH FDI RX */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2809         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2810         temp &= ~FDI_LINK_TRAIN_NONE;
2811         temp |= FDI_LINK_TRAIN_PATTERN_1;
2812         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~FDI_LINK_TRAIN_NONE;
2817         temp |= FDI_LINK_TRAIN_PATTERN_1;
2818         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(150);
2822
2823         /* Ironlake workaround, enable clock pointer after FDI enable*/
2824         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2825         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2826                    FDI_RX_PHASE_SYNC_POINTER_EN);
2827
2828         reg = FDI_RX_IIR(pipe);
2829         for (tries = 0; tries < 5; tries++) {
2830                 temp = I915_READ(reg);
2831                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2832
2833                 if ((temp & FDI_RX_BIT_LOCK)) {
2834                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2835                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2836                         break;
2837                 }
2838         }
2839         if (tries == 5)
2840                 DRM_ERROR("FDI train 1 fail!\n");
2841
2842         /* Train 2 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_2;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_2;
2853         I915_WRITE(reg, temp);
2854
2855         POSTING_READ(reg);
2856         udelay(150);
2857
2858         reg = FDI_RX_IIR(pipe);
2859         for (tries = 0; tries < 5; tries++) {
2860                 temp = I915_READ(reg);
2861                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2862
2863                 if (temp & FDI_RX_SYMBOL_LOCK) {
2864                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2865                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2866                         break;
2867                 }
2868         }
2869         if (tries == 5)
2870                 DRM_ERROR("FDI train 2 fail!\n");
2871
2872         DRM_DEBUG_KMS("FDI train done\n");
2873
2874 }
2875
2876 static const int snb_b_fdi_train_param[] = {
2877         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2878         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2879         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2880         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2881 };
2882
2883 /* The FDI link training functions for SNB/Cougarpoint. */
2884 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2885 {
2886         struct drm_device *dev = crtc->dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889         int pipe = intel_crtc->pipe;
2890         u32 reg, temp, i, retry;
2891
2892         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2893            for train result */
2894         reg = FDI_RX_IMR(pipe);
2895         temp = I915_READ(reg);
2896         temp &= ~FDI_RX_SYMBOL_LOCK;
2897         temp &= ~FDI_RX_BIT_LOCK;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(150);
2902
2903         /* enable CPU FDI TX and PCH FDI RX */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2907         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2908         temp &= ~FDI_LINK_TRAIN_NONE;
2909         temp |= FDI_LINK_TRAIN_PATTERN_1;
2910         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2911         /* SNB-B */
2912         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2913         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2914
2915         I915_WRITE(FDI_RX_MISC(pipe),
2916                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2917
2918         reg = FDI_RX_CTL(pipe);
2919         temp = I915_READ(reg);
2920         if (HAS_PCH_CPT(dev)) {
2921                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2922                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2923         } else {
2924                 temp &= ~FDI_LINK_TRAIN_NONE;
2925                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         }
2927         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2928
2929         POSTING_READ(reg);
2930         udelay(150);
2931
2932         for (i = 0; i < 4; i++) {
2933                 reg = FDI_TX_CTL(pipe);
2934                 temp = I915_READ(reg);
2935                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936                 temp |= snb_b_fdi_train_param[i];
2937                 I915_WRITE(reg, temp);
2938
2939                 POSTING_READ(reg);
2940                 udelay(500);
2941
2942                 for (retry = 0; retry < 5; retry++) {
2943                         reg = FDI_RX_IIR(pipe);
2944                         temp = I915_READ(reg);
2945                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2946                         if (temp & FDI_RX_BIT_LOCK) {
2947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2948                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2949                                 break;
2950                         }
2951                         udelay(50);
2952                 }
2953                 if (retry < 5)
2954                         break;
2955         }
2956         if (i == 4)
2957                 DRM_ERROR("FDI train 1 fail!\n");
2958
2959         /* Train 2 */
2960         reg = FDI_TX_CTL(pipe);
2961         temp = I915_READ(reg);
2962         temp &= ~FDI_LINK_TRAIN_NONE;
2963         temp |= FDI_LINK_TRAIN_PATTERN_2;
2964         if (IS_GEN6(dev)) {
2965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966                 /* SNB-B */
2967                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968         }
2969         I915_WRITE(reg, temp);
2970
2971         reg = FDI_RX_CTL(pipe);
2972         temp = I915_READ(reg);
2973         if (HAS_PCH_CPT(dev)) {
2974                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2976         } else {
2977                 temp &= ~FDI_LINK_TRAIN_NONE;
2978                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         }
2980         I915_WRITE(reg, temp);
2981
2982         POSTING_READ(reg);
2983         udelay(150);
2984
2985         for (i = 0; i < 4; i++) {
2986                 reg = FDI_TX_CTL(pipe);
2987                 temp = I915_READ(reg);
2988                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2989                 temp |= snb_b_fdi_train_param[i];
2990                 I915_WRITE(reg, temp);
2991
2992                 POSTING_READ(reg);
2993                 udelay(500);
2994
2995                 for (retry = 0; retry < 5; retry++) {
2996                         reg = FDI_RX_IIR(pipe);
2997                         temp = I915_READ(reg);
2998                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2999                         if (temp & FDI_RX_SYMBOL_LOCK) {
3000                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3001                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3002                                 break;
3003                         }
3004                         udelay(50);
3005                 }
3006                 if (retry < 5)
3007                         break;
3008         }
3009         if (i == 4)
3010                 DRM_ERROR("FDI train 2 fail!\n");
3011
3012         DRM_DEBUG_KMS("FDI train done.\n");
3013 }
3014
3015 /* Manual link training for Ivy Bridge A0 parts */
3016 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3017 {
3018         struct drm_device *dev = crtc->dev;
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021         int pipe = intel_crtc->pipe;
3022         u32 reg, temp, i, j;
3023
3024         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025            for train result */
3026         reg = FDI_RX_IMR(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~FDI_RX_SYMBOL_LOCK;
3029         temp &= ~FDI_RX_BIT_LOCK;
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3036                       I915_READ(FDI_RX_IIR(pipe)));
3037
3038         /* Try each vswing and preemphasis setting twice before moving on */
3039         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3040                 /* disable first in case we need to retry */
3041                 reg = FDI_TX_CTL(pipe);
3042                 temp = I915_READ(reg);
3043                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3044                 temp &= ~FDI_TX_ENABLE;
3045                 I915_WRITE(reg, temp);
3046
3047                 reg = FDI_RX_CTL(pipe);
3048                 temp = I915_READ(reg);
3049                 temp &= ~FDI_LINK_TRAIN_AUTO;
3050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051                 temp &= ~FDI_RX_ENABLE;
3052                 I915_WRITE(reg, temp);
3053
3054                 /* enable CPU FDI TX and PCH FDI RX */
3055                 reg = FDI_TX_CTL(pipe);
3056                 temp = I915_READ(reg);
3057                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3060                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061                 temp |= snb_b_fdi_train_param[j/2];
3062                 temp |= FDI_COMPOSITE_SYNC;
3063                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3064
3065                 I915_WRITE(FDI_RX_MISC(pipe),
3066                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3067
3068                 reg = FDI_RX_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3071                 temp |= FDI_COMPOSITE_SYNC;
3072                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3073
3074                 POSTING_READ(reg);
3075                 udelay(1); /* should be 0.5us */
3076
3077                 for (i = 0; i < 4; i++) {
3078                         reg = FDI_RX_IIR(pipe);
3079                         temp = I915_READ(reg);
3080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                         if (temp & FDI_RX_BIT_LOCK ||
3083                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3084                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3086                                               i);
3087                                 break;
3088                         }
3089                         udelay(1); /* should be 0.5us */
3090                 }
3091                 if (i == 4) {
3092                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3093                         continue;
3094                 }
3095
3096                 /* Train 2 */
3097                 reg = FDI_TX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3100                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3101                 I915_WRITE(reg, temp);
3102
3103                 reg = FDI_RX_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3107                 I915_WRITE(reg, temp);
3108
3109                 POSTING_READ(reg);
3110                 udelay(2); /* should be 1.5us */
3111
3112                 for (i = 0; i < 4; i++) {
3113                         reg = FDI_RX_IIR(pipe);
3114                         temp = I915_READ(reg);
3115                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3116
3117                         if (temp & FDI_RX_SYMBOL_LOCK ||
3118                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3119                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3120                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3121                                               i);
3122                                 goto train_done;
3123                         }
3124                         udelay(2); /* should be 1.5us */
3125                 }
3126                 if (i == 4)
3127                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3128         }
3129
3130 train_done:
3131         DRM_DEBUG_KMS("FDI train done.\n");
3132 }
3133
3134 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3135 {
3136         struct drm_device *dev = intel_crtc->base.dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp;
3140
3141
3142         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3146         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3147         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3148         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(200);
3152
3153         /* Switch from Rawclk to PCDclk */
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp | FDI_PCDCLK);
3156
3157         POSTING_READ(reg);
3158         udelay(200);
3159
3160         /* Enable CPU FDI TX PLL, always on for Ironlake */
3161         reg = FDI_TX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3164                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3165
3166                 POSTING_READ(reg);
3167                 udelay(100);
3168         }
3169 }
3170
3171 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3172 {
3173         struct drm_device *dev = intel_crtc->base.dev;
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         int pipe = intel_crtc->pipe;
3176         u32 reg, temp;
3177
3178         /* Switch from PCDclk to Rawclk */
3179         reg = FDI_RX_CTL(pipe);
3180         temp = I915_READ(reg);
3181         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3182
3183         /* Disable CPU FDI TX PLL */
3184         reg = FDI_TX_CTL(pipe);
3185         temp = I915_READ(reg);
3186         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3187
3188         POSTING_READ(reg);
3189         udelay(100);
3190
3191         reg = FDI_RX_CTL(pipe);
3192         temp = I915_READ(reg);
3193         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3194
3195         /* Wait for the clocks to turn off. */
3196         POSTING_READ(reg);
3197         udelay(100);
3198 }
3199
3200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         u32 reg, temp;
3207
3208         /* disable CPU FDI tx and PCH FDI rx */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3212         POSTING_READ(reg);
3213
3214         reg = FDI_RX_CTL(pipe);
3215         temp = I915_READ(reg);
3216         temp &= ~(0x7 << 16);
3217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3219
3220         POSTING_READ(reg);
3221         udelay(100);
3222
3223         /* Ironlake workaround, disable clock pointer after downing FDI */
3224         if (HAS_PCH_IBX(dev)) {
3225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3226         }
3227
3228         /* still set train pattern 1 */
3229         reg = FDI_TX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         temp &= ~FDI_LINK_TRAIN_NONE;
3232         temp |= FDI_LINK_TRAIN_PATTERN_1;
3233         I915_WRITE(reg, temp);
3234
3235         reg = FDI_RX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (HAS_PCH_CPT(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3239                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3243         }
3244         /* BPC in FDI rx is consistent with that in PIPECONF */
3245         temp &= ~(0x07 << 16);
3246         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3247         I915_WRITE(reg, temp);
3248
3249         POSTING_READ(reg);
3250         udelay(100);
3251 }
3252
3253 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3254 {
3255         struct intel_crtc *crtc;
3256
3257         /* Note that we don't need to be called with mode_config.lock here
3258          * as our list of CRTC objects is static for the lifetime of the
3259          * device and so cannot disappear as we iterate. Similarly, we can
3260          * happily treat the predicates as racy, atomic checks as userspace
3261          * cannot claim and pin a new fb without at least acquring the
3262          * struct_mutex and so serialising with us.
3263          */
3264         for_each_intel_crtc(dev, crtc) {
3265                 if (atomic_read(&crtc->unpin_work_count) == 0)
3266                         continue;
3267
3268                 if (crtc->unpin_work)
3269                         intel_wait_for_vblank(dev, crtc->pipe);
3270
3271                 return true;
3272         }
3273
3274         return false;
3275 }
3276
3277 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282         if (crtc->primary->fb == NULL)
3283                 return;
3284
3285         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3286
3287         wait_event(dev_priv->pending_flip_queue,
3288                    !intel_crtc_has_pending_flip(crtc));
3289
3290         mutex_lock(&dev->struct_mutex);
3291         intel_finish_fb(crtc->primary->fb);
3292         mutex_unlock(&dev->struct_mutex);
3293 }
3294
3295 /* Program iCLKIP clock to the desired frequency */
3296 static void lpt_program_iclkip(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3301         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3302         u32 temp;
3303
3304         mutex_lock(&dev_priv->dpio_lock);
3305
3306         /* It is necessary to ungate the pixclk gate prior to programming
3307          * the divisors, and gate it back when it is done.
3308          */
3309         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3310
3311         /* Disable SSCCTL */
3312         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3313                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3314                                 SBI_SSCCTL_DISABLE,
3315                         SBI_ICLK);
3316
3317         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3318         if (clock == 20000) {
3319                 auxdiv = 1;
3320                 divsel = 0x41;
3321                 phaseinc = 0x20;
3322         } else {
3323                 /* The iCLK virtual clock root frequency is in MHz,
3324                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3325                  * divisors, it is necessary to divide one by another, so we
3326                  * convert the virtual clock precision to KHz here for higher
3327                  * precision.
3328                  */
3329                 u32 iclk_virtual_root_freq = 172800 * 1000;
3330                 u32 iclk_pi_range = 64;
3331                 u32 desired_divisor, msb_divisor_value, pi_value;
3332
3333                 desired_divisor = (iclk_virtual_root_freq / clock);
3334                 msb_divisor_value = desired_divisor / iclk_pi_range;
3335                 pi_value = desired_divisor % iclk_pi_range;
3336
3337                 auxdiv = 0;
3338                 divsel = msb_divisor_value - 2;
3339                 phaseinc = pi_value;
3340         }
3341
3342         /* This should not happen with any sane values */
3343         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3344                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3345         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3346                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3347
3348         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3349                         clock,
3350                         auxdiv,
3351                         divsel,
3352                         phasedir,
3353                         phaseinc);
3354
3355         /* Program SSCDIVINTPHASE6 */
3356         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3357         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3358         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3359         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3360         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3361         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3362         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3363         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3364
3365         /* Program SSCAUXDIV */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3367         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3368         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3369         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3370
3371         /* Enable modulator and associated divider */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3373         temp &= ~SBI_SSCCTL_DISABLE;
3374         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3375
3376         /* Wait for initialization time */
3377         udelay(24);
3378
3379         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3380
3381         mutex_unlock(&dev_priv->dpio_lock);
3382 }
3383
3384 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3385                                                 enum pipe pch_transcoder)
3386 {
3387         struct drm_device *dev = crtc->base.dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3390
3391         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3392                    I915_READ(HTOTAL(cpu_transcoder)));
3393         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3394                    I915_READ(HBLANK(cpu_transcoder)));
3395         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3396                    I915_READ(HSYNC(cpu_transcoder)));
3397
3398         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3399                    I915_READ(VTOTAL(cpu_transcoder)));
3400         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3401                    I915_READ(VBLANK(cpu_transcoder)));
3402         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3403                    I915_READ(VSYNC(cpu_transcoder)));
3404         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3405                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3406 }
3407
3408 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         uint32_t temp;
3412
3413         temp = I915_READ(SOUTH_CHICKEN1);
3414         if (temp & FDI_BC_BIFURCATION_SELECT)
3415                 return;
3416
3417         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3418         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3419
3420         temp |= FDI_BC_BIFURCATION_SELECT;
3421         DRM_DEBUG_KMS("enabling fdi C rx\n");
3422         I915_WRITE(SOUTH_CHICKEN1, temp);
3423         POSTING_READ(SOUTH_CHICKEN1);
3424 }
3425
3426 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3427 {
3428         struct drm_device *dev = intel_crtc->base.dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431         switch (intel_crtc->pipe) {
3432         case PIPE_A:
3433                 break;
3434         case PIPE_B:
3435                 if (intel_crtc->config.fdi_lanes > 2)
3436                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3437                 else
3438                         cpt_enable_fdi_bc_bifurcation(dev);
3439
3440                 break;
3441         case PIPE_C:
3442                 cpt_enable_fdi_bc_bifurcation(dev);
3443
3444                 break;
3445         default:
3446                 BUG();
3447         }
3448 }
3449
3450 /*
3451  * Enable PCH resources required for PCH ports:
3452  *   - PCH PLLs
3453  *   - FDI training & RX/TX
3454  *   - update transcoder timings
3455  *   - DP transcoding bits
3456  *   - transcoder
3457  */
3458 static void ironlake_pch_enable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         int pipe = intel_crtc->pipe;
3464         u32 reg, temp;
3465
3466         assert_pch_transcoder_disabled(dev_priv, pipe);
3467
3468         if (IS_IVYBRIDGE(dev))
3469                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3470
3471         /* Write the TU size bits before fdi link training, so that error
3472          * detection works. */
3473         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3474                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3475
3476         /* For PCH output, training FDI link */
3477         dev_priv->display.fdi_link_train(crtc);
3478
3479         /* We need to program the right clock selection before writing the pixel
3480          * mutliplier into the DPLL. */
3481         if (HAS_PCH_CPT(dev)) {
3482                 u32 sel;
3483
3484                 temp = I915_READ(PCH_DPLL_SEL);
3485                 temp |= TRANS_DPLL_ENABLE(pipe);
3486                 sel = TRANS_DPLLB_SEL(pipe);
3487                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3488                         temp |= sel;
3489                 else
3490                         temp &= ~sel;
3491                 I915_WRITE(PCH_DPLL_SEL, temp);
3492         }
3493
3494         /* XXX: pch pll's can be enabled any time before we enable the PCH
3495          * transcoder, and we actually should do this to not upset any PCH
3496          * transcoder that already use the clock when we share it.
3497          *
3498          * Note that enable_shared_dpll tries to do the right thing, but
3499          * get_shared_dpll unconditionally resets the pll - we need that to have
3500          * the right LVDS enable sequence. */
3501         ironlake_enable_shared_dpll(intel_crtc);
3502
3503         /* set transcoder timing, panel must allow it */
3504         assert_panel_unlocked(dev_priv, pipe);
3505         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3506
3507         intel_fdi_normal_train(crtc);
3508
3509         /* For PCH DP, enable TRANS_DP_CTL */
3510         if (HAS_PCH_CPT(dev) &&
3511             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3512              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3513                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3514                 reg = TRANS_DP_CTL(pipe);
3515                 temp = I915_READ(reg);
3516                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3517                           TRANS_DP_SYNC_MASK |
3518                           TRANS_DP_BPC_MASK);
3519                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3520                          TRANS_DP_ENH_FRAMING);
3521                 temp |= bpc << 9; /* same format but at 11:9 */
3522
3523                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3524                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3525                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3526                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3527
3528                 switch (intel_trans_dp_port_sel(crtc)) {
3529                 case PCH_DP_B:
3530                         temp |= TRANS_DP_PORT_SEL_B;
3531                         break;
3532                 case PCH_DP_C:
3533                         temp |= TRANS_DP_PORT_SEL_C;
3534                         break;
3535                 case PCH_DP_D:
3536                         temp |= TRANS_DP_PORT_SEL_D;
3537                         break;
3538                 default:
3539                         BUG();
3540                 }
3541
3542                 I915_WRITE(reg, temp);
3543         }
3544
3545         ironlake_enable_pch_transcoder(dev_priv, pipe);
3546 }
3547
3548 static void lpt_pch_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3554
3555         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3556
3557         lpt_program_iclkip(crtc);
3558
3559         /* Set transcoder timing. */
3560         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3561
3562         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3563 }
3564
3565 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3566 {
3567         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3568
3569         if (pll == NULL)
3570                 return;
3571
3572         if (pll->refcount == 0) {
3573                 WARN(1, "bad %s refcount\n", pll->name);
3574                 return;
3575         }
3576
3577         if (--pll->refcount == 0) {
3578                 WARN_ON(pll->on);
3579                 WARN_ON(pll->active);
3580         }
3581
3582         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3583 }
3584
3585 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3586 {
3587         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3588         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3589         enum intel_dpll_id i;
3590
3591         if (pll) {
3592                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3593                               crtc->base.base.id, pll->name);
3594                 intel_put_shared_dpll(crtc);
3595         }
3596
3597         if (HAS_PCH_IBX(dev_priv->dev)) {
3598                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3599                 i = (enum intel_dpll_id) crtc->pipe;
3600                 pll = &dev_priv->shared_dplls[i];
3601
3602                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3603                               crtc->base.base.id, pll->name);
3604
3605                 goto found;
3606         }
3607
3608         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3609                 pll = &dev_priv->shared_dplls[i];
3610
3611                 /* Only want to check enabled timings first */
3612                 if (pll->refcount == 0)
3613                         continue;
3614
3615                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3616                            sizeof(pll->hw_state)) == 0) {
3617                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3618                                       crtc->base.base.id,
3619                                       pll->name, pll->refcount, pll->active);
3620
3621                         goto found;
3622                 }
3623         }
3624
3625         /* Ok no matching timings, maybe there's a free one? */
3626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627                 pll = &dev_priv->shared_dplls[i];
3628                 if (pll->refcount == 0) {
3629                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3630                                       crtc->base.base.id, pll->name);
3631                         goto found;
3632                 }
3633         }
3634
3635         return NULL;
3636
3637 found:
3638         crtc->config.shared_dpll = i;
3639         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3640                          pipe_name(crtc->pipe));
3641
3642         if (pll->active == 0) {
3643                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3644                        sizeof(pll->hw_state));
3645
3646                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3647                 WARN_ON(pll->on);
3648                 assert_shared_dpll_disabled(dev_priv, pll);
3649
3650                 pll->mode_set(dev_priv, pll);
3651         }
3652         pll->refcount++;
3653
3654         return pll;
3655 }
3656
3657 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660         int dslreg = PIPEDSL(pipe);
3661         u32 temp;
3662
3663         temp = I915_READ(dslreg);
3664         udelay(500);
3665         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3666                 if (wait_for(I915_READ(dslreg) != temp, 5))
3667                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3668         }
3669 }
3670
3671 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3672 {
3673         struct drm_device *dev = crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         int pipe = crtc->pipe;
3676
3677         if (crtc->config.pch_pfit.enabled) {
3678                 /* Force use of hard-coded filter coefficients
3679                  * as some pre-programmed values are broken,
3680                  * e.g. x201.
3681                  */
3682                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3683                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3684                                                  PF_PIPE_SEL_IVB(pipe));
3685                 else
3686                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3687                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3688                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3689         }
3690 }
3691
3692 static void intel_enable_planes(struct drm_crtc *crtc)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3696         struct drm_plane *plane;
3697         struct intel_plane *intel_plane;
3698
3699         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3700                 intel_plane = to_intel_plane(plane);
3701                 if (intel_plane->pipe == pipe)
3702                         intel_plane_restore(&intel_plane->base);
3703         }
3704 }
3705
3706 static void intel_disable_planes(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3710         struct drm_plane *plane;
3711         struct intel_plane *intel_plane;
3712
3713         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3714                 intel_plane = to_intel_plane(plane);
3715                 if (intel_plane->pipe == pipe)
3716                         intel_plane_disable(&intel_plane->base);
3717         }
3718 }
3719
3720 void hsw_enable_ips(struct intel_crtc *crtc)
3721 {
3722         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3723
3724         if (!crtc->config.ips_enabled)
3725                 return;
3726
3727         /* We can only enable IPS after we enable a plane and wait for a vblank.
3728          * We guarantee that the plane is enabled by calling intel_enable_ips
3729          * only after intel_enable_plane. And intel_enable_plane already waits
3730          * for a vblank, so all we need to do here is to enable the IPS bit. */
3731         assert_plane_enabled(dev_priv, crtc->plane);
3732         if (IS_BROADWELL(crtc->base.dev)) {
3733                 mutex_lock(&dev_priv->rps.hw_lock);
3734                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3735                 mutex_unlock(&dev_priv->rps.hw_lock);
3736                 /* Quoting Art Runyan: "its not safe to expect any particular
3737                  * value in IPS_CTL bit 31 after enabling IPS through the
3738                  * mailbox." Moreover, the mailbox may return a bogus state,
3739                  * so we need to just enable it and continue on.
3740                  */
3741         } else {
3742                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3743                 /* The bit only becomes 1 in the next vblank, so this wait here
3744                  * is essentially intel_wait_for_vblank. If we don't have this
3745                  * and don't wait for vblanks until the end of crtc_enable, then
3746                  * the HW state readout code will complain that the expected
3747                  * IPS_CTL value is not the one we read. */
3748                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3749                         DRM_ERROR("Timed out waiting for IPS enable\n");
3750         }
3751 }
3752
3753 void hsw_disable_ips(struct intel_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757
3758         if (!crtc->config.ips_enabled)
3759                 return;
3760
3761         assert_plane_enabled(dev_priv, crtc->plane);
3762         if (IS_BROADWELL(dev)) {
3763                 mutex_lock(&dev_priv->rps.hw_lock);
3764                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3765                 mutex_unlock(&dev_priv->rps.hw_lock);
3766                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3767                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3768                         DRM_ERROR("Timed out waiting for IPS disable\n");
3769         } else {
3770                 I915_WRITE(IPS_CTL, 0);
3771                 POSTING_READ(IPS_CTL);
3772         }
3773
3774         /* We need to wait for a vblank before we can disable the plane. */
3775         intel_wait_for_vblank(dev, crtc->pipe);
3776 }
3777
3778 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3779 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         enum pipe pipe = intel_crtc->pipe;
3785         int palreg = PALETTE(pipe);
3786         int i;
3787         bool reenable_ips = false;
3788
3789         /* The clocks have to be on to load the palette. */
3790         if (!crtc->enabled || !intel_crtc->active)
3791                 return;
3792
3793         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3794                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3795                         assert_dsi_pll_enabled(dev_priv);
3796                 else
3797                         assert_pll_enabled(dev_priv, pipe);
3798         }
3799
3800         /* use legacy palette for Ironlake */
3801         if (HAS_PCH_SPLIT(dev))
3802                 palreg = LGC_PALETTE(pipe);
3803
3804         /* Workaround : Do not read or write the pipe palette/gamma data while
3805          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3806          */
3807         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3808             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3809              GAMMA_MODE_MODE_SPLIT)) {
3810                 hsw_disable_ips(intel_crtc);
3811                 reenable_ips = true;
3812         }
3813
3814         for (i = 0; i < 256; i++) {
3815                 I915_WRITE(palreg + 4 * i,
3816                            (intel_crtc->lut_r[i] << 16) |
3817                            (intel_crtc->lut_g[i] << 8) |
3818                            intel_crtc->lut_b[i]);
3819         }
3820
3821         if (reenable_ips)
3822                 hsw_enable_ips(intel_crtc);
3823 }
3824
3825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3826 {
3827         if (!enable && intel_crtc->overlay) {
3828                 struct drm_device *dev = intel_crtc->base.dev;
3829                 struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831                 mutex_lock(&dev->struct_mutex);
3832                 dev_priv->mm.interruptible = false;
3833                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3834                 dev_priv->mm.interruptible = true;
3835                 mutex_unlock(&dev->struct_mutex);
3836         }
3837
3838         /* Let userspace switch the overlay on again. In most cases userspace
3839          * has to recompute where to put it anyway.
3840          */
3841 }
3842
3843 /**
3844  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3845  * cursor plane briefly if not already running after enabling the display
3846  * plane.
3847  * This workaround avoids occasional blank screens when self refresh is
3848  * enabled.
3849  */
3850 static void
3851 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3852 {
3853         u32 cntl = I915_READ(CURCNTR(pipe));
3854
3855         if ((cntl & CURSOR_MODE) == 0) {
3856                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3857
3858                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3859                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3860                 intel_wait_for_vblank(dev_priv->dev, pipe);
3861                 I915_WRITE(CURCNTR(pipe), cntl);
3862                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3863                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3864         }
3865 }
3866
3867 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3868 {
3869         struct drm_device *dev = crtc->dev;
3870         struct drm_i915_private *dev_priv = dev->dev_private;
3871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872         int pipe = intel_crtc->pipe;
3873         int plane = intel_crtc->plane;
3874
3875         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3876         intel_enable_planes(crtc);
3877         /* The fixup needs to happen before cursor is enabled */
3878         if (IS_G4X(dev))
3879                 g4x_fixup_plane(dev_priv, pipe);
3880         intel_crtc_update_cursor(crtc, true);
3881         intel_crtc_dpms_overlay(intel_crtc, true);
3882
3883         hsw_enable_ips(intel_crtc);
3884
3885         mutex_lock(&dev->struct_mutex);
3886         intel_update_fbc(dev);
3887         mutex_unlock(&dev->struct_mutex);
3888 }
3889
3890 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3891 {
3892         struct drm_device *dev = crtc->dev;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895         int pipe = intel_crtc->pipe;
3896         int plane = intel_crtc->plane;
3897
3898         intel_crtc_wait_for_pending_flips(crtc);
3899         drm_vblank_off(dev, pipe);
3900
3901         if (dev_priv->fbc.plane == plane)
3902                 intel_disable_fbc(dev);
3903
3904         hsw_disable_ips(intel_crtc);
3905
3906         intel_crtc_dpms_overlay(intel_crtc, false);
3907         intel_crtc_update_cursor(crtc, false);
3908         intel_disable_planes(crtc);
3909         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3910 }
3911
3912 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         struct intel_encoder *encoder;
3918         int pipe = intel_crtc->pipe;
3919
3920         WARN_ON(!crtc->enabled);
3921
3922         if (intel_crtc->active)
3923                 return;
3924
3925         intel_crtc->active = true;
3926
3927         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3928         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->pre_enable)
3932                         encoder->pre_enable(encoder);
3933
3934         if (intel_crtc->config.has_pch_encoder) {
3935                 /* Note: FDI PLL enabling _must_ be done before we enable the
3936                  * cpu pipes, hence this is separate from all the other fdi/pch
3937                  * enabling. */
3938                 ironlake_fdi_pll_enable(intel_crtc);
3939         } else {
3940                 assert_fdi_tx_disabled(dev_priv, pipe);
3941                 assert_fdi_rx_disabled(dev_priv, pipe);
3942         }
3943
3944         ironlake_pfit_enable(intel_crtc);
3945
3946         /*
3947          * On ILK+ LUT must be loaded before the pipe is running but with
3948          * clocks enabled
3949          */
3950         intel_crtc_load_lut(crtc);
3951
3952         intel_update_watermarks(crtc);
3953         intel_enable_pipe(intel_crtc);
3954
3955         if (intel_crtc->config.has_pch_encoder)
3956                 ironlake_pch_enable(crtc);
3957
3958         for_each_encoder_on_crtc(dev, crtc, encoder)
3959                 encoder->enable(encoder);
3960
3961         if (HAS_PCH_CPT(dev))
3962                 cpt_verify_modeset(dev, intel_crtc->pipe);
3963
3964         intel_crtc_enable_planes(crtc);
3965
3966         /*
3967          * There seems to be a race in PCH platform hw (at least on some
3968          * outputs) where an enabled pipe still completes any pageflip right
3969          * away (as if the pipe is off) instead of waiting for vblank. As soon
3970          * as the first vblank happend, everything works as expected. Hence just
3971          * wait for one vblank before returning to avoid strange things
3972          * happening.
3973          */
3974         intel_wait_for_vblank(dev, intel_crtc->pipe);
3975 }
3976
3977 /* IPS only exists on ULT machines and is tied to pipe A. */
3978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3979 {
3980         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3981 }
3982
3983 /*
3984  * This implements the workaround described in the "notes" section of the mode
3985  * set sequence documentation. When going from no pipes or single pipe to
3986  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3987  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3988  */
3989 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3990 {
3991         struct drm_device *dev = crtc->base.dev;
3992         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3993
3994         /* We want to get the other_active_crtc only if there's only 1 other
3995          * active crtc. */
3996         for_each_intel_crtc(dev, crtc_it) {
3997                 if (!crtc_it->active || crtc_it == crtc)
3998                         continue;
3999
4000                 if (other_active_crtc)
4001                         return;
4002
4003                 other_active_crtc = crtc_it;
4004         }
4005         if (!other_active_crtc)
4006                 return;
4007
4008         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4009         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4010 }
4011
4012 static void haswell_crtc_enable(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017         struct intel_encoder *encoder;
4018         int pipe = intel_crtc->pipe;
4019
4020         WARN_ON(!crtc->enabled);
4021
4022         if (intel_crtc->active)
4023                 return;
4024
4025         intel_crtc->active = true;
4026
4027         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028         if (intel_crtc->config.has_pch_encoder)
4029                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4030
4031         if (intel_crtc->config.has_pch_encoder)
4032                 dev_priv->display.fdi_link_train(crtc);
4033
4034         for_each_encoder_on_crtc(dev, crtc, encoder)
4035                 if (encoder->pre_enable)
4036                         encoder->pre_enable(encoder);
4037
4038         intel_ddi_enable_pipe_clock(intel_crtc);
4039
4040         ironlake_pfit_enable(intel_crtc);
4041
4042         /*
4043          * On ILK+ LUT must be loaded before the pipe is running but with
4044          * clocks enabled
4045          */
4046         intel_crtc_load_lut(crtc);
4047
4048         intel_ddi_set_pipe_settings(crtc);
4049         intel_ddi_enable_transcoder_func(crtc);
4050
4051         intel_update_watermarks(crtc);
4052         intel_enable_pipe(intel_crtc);
4053
4054         if (intel_crtc->config.has_pch_encoder)
4055                 lpt_pch_enable(crtc);
4056
4057         for_each_encoder_on_crtc(dev, crtc, encoder) {
4058                 encoder->enable(encoder);
4059                 intel_opregion_notify_encoder(encoder, true);
4060         }
4061
4062         /* If we change the relative order between pipe/planes enabling, we need
4063          * to change the workaround. */
4064         haswell_mode_set_planes_workaround(intel_crtc);
4065         intel_crtc_enable_planes(crtc);
4066 }
4067
4068 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4069 {
4070         struct drm_device *dev = crtc->base.dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072         int pipe = crtc->pipe;
4073
4074         /* To avoid upsetting the power well on haswell only disable the pfit if
4075          * it's in use. The hw state code will make sure we get this right. */
4076         if (crtc->config.pch_pfit.enabled) {
4077                 I915_WRITE(PF_CTL(pipe), 0);
4078                 I915_WRITE(PF_WIN_POS(pipe), 0);
4079                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4080         }
4081 }
4082
4083 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         struct intel_encoder *encoder;
4089         int pipe = intel_crtc->pipe;
4090         u32 reg, temp;
4091
4092         if (!intel_crtc->active)
4093                 return;
4094
4095         intel_crtc_disable_planes(crtc);
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder)
4098                 encoder->disable(encoder);
4099
4100         if (intel_crtc->config.has_pch_encoder)
4101                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4102
4103         intel_disable_pipe(dev_priv, pipe);
4104
4105         ironlake_pfit_disable(intel_crtc);
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder)
4108                 if (encoder->post_disable)
4109                         encoder->post_disable(encoder);
4110
4111         if (intel_crtc->config.has_pch_encoder) {
4112                 ironlake_fdi_disable(crtc);
4113
4114                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4115                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4116
4117                 if (HAS_PCH_CPT(dev)) {
4118                         /* disable TRANS_DP_CTL */
4119                         reg = TRANS_DP_CTL(pipe);
4120                         temp = I915_READ(reg);
4121                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4122                                   TRANS_DP_PORT_SEL_MASK);
4123                         temp |= TRANS_DP_PORT_SEL_NONE;
4124                         I915_WRITE(reg, temp);
4125
4126                         /* disable DPLL_SEL */
4127                         temp = I915_READ(PCH_DPLL_SEL);
4128                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4129                         I915_WRITE(PCH_DPLL_SEL, temp);
4130                 }
4131
4132                 /* disable PCH DPLL */
4133                 intel_disable_shared_dpll(intel_crtc);
4134
4135                 ironlake_fdi_pll_disable(intel_crtc);
4136         }
4137
4138         intel_crtc->active = false;
4139         intel_update_watermarks(crtc);
4140
4141         mutex_lock(&dev->struct_mutex);
4142         intel_update_fbc(dev);
4143         mutex_unlock(&dev->struct_mutex);
4144 }
4145
4146 static void haswell_crtc_disable(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         struct intel_encoder *encoder;
4152         int pipe = intel_crtc->pipe;
4153         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4154
4155         if (!intel_crtc->active)
4156                 return;
4157
4158         intel_crtc_disable_planes(crtc);
4159
4160         for_each_encoder_on_crtc(dev, crtc, encoder) {
4161                 intel_opregion_notify_encoder(encoder, false);
4162                 encoder->disable(encoder);
4163         }
4164
4165         if (intel_crtc->config.has_pch_encoder)
4166                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4167         intel_disable_pipe(dev_priv, pipe);
4168
4169         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4170
4171         ironlake_pfit_disable(intel_crtc);
4172
4173         intel_ddi_disable_pipe_clock(intel_crtc);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->post_disable)
4177                         encoder->post_disable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 lpt_disable_pch_transcoder(dev_priv);
4181                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4182                 intel_ddi_fdi_disable(crtc);
4183         }
4184
4185         intel_crtc->active = false;
4186         intel_update_watermarks(crtc);
4187
4188         mutex_lock(&dev->struct_mutex);
4189         intel_update_fbc(dev);
4190         mutex_unlock(&dev->struct_mutex);
4191 }
4192
4193 static void ironlake_crtc_off(struct drm_crtc *crtc)
4194 {
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         intel_put_shared_dpll(intel_crtc);
4197 }
4198
4199 static void haswell_crtc_off(struct drm_crtc *crtc)
4200 {
4201         intel_ddi_put_crtc_pll(crtc);
4202 }
4203
4204 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->base.dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc_config *pipe_config = &crtc->config;
4209
4210         if (!crtc->config.gmch_pfit.control)
4211                 return;
4212
4213         /*
4214          * The panel fitter should only be adjusted whilst the pipe is disabled,
4215          * according to register description and PRM.
4216          */
4217         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4218         assert_pipe_disabled(dev_priv, crtc->pipe);
4219
4220         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4221         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4222
4223         /* Border color in case we don't scale up to the full screen. Black by
4224          * default, change to something else for debugging. */
4225         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4226 }
4227
4228 #define for_each_power_domain(domain, mask)                             \
4229         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4230                 if ((1 << (domain)) & (mask))
4231
4232 enum intel_display_power_domain
4233 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4234 {
4235         struct drm_device *dev = intel_encoder->base.dev;
4236         struct intel_digital_port *intel_dig_port;
4237
4238         switch (intel_encoder->type) {
4239         case INTEL_OUTPUT_UNKNOWN:
4240                 /* Only DDI platforms should ever use this output type */
4241                 WARN_ON_ONCE(!HAS_DDI(dev));
4242         case INTEL_OUTPUT_DISPLAYPORT:
4243         case INTEL_OUTPUT_HDMI:
4244         case INTEL_OUTPUT_EDP:
4245                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4246                 switch (intel_dig_port->port) {
4247                 case PORT_A:
4248                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4249                 case PORT_B:
4250                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4251                 case PORT_C:
4252                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4253                 case PORT_D:
4254                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4255                 default:
4256                         WARN_ON_ONCE(1);
4257                         return POWER_DOMAIN_PORT_OTHER;
4258                 }
4259         case INTEL_OUTPUT_ANALOG:
4260                 return POWER_DOMAIN_PORT_CRT;
4261         case INTEL_OUTPUT_DSI:
4262                 return POWER_DOMAIN_PORT_DSI;
4263         default:
4264                 return POWER_DOMAIN_PORT_OTHER;
4265         }
4266 }
4267
4268 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct intel_encoder *intel_encoder;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         enum pipe pipe = intel_crtc->pipe;
4274         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4275         unsigned long mask;
4276         enum transcoder transcoder;
4277
4278         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4279
4280         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4281         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4282         if (pfit_enabled)
4283                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4284
4285         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4286                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4287
4288         return mask;
4289 }
4290
4291 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4292                                   bool enable)
4293 {
4294         if (dev_priv->power_domains.init_power_on == enable)
4295                 return;
4296
4297         if (enable)
4298                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4299         else
4300                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4301
4302         dev_priv->power_domains.init_power_on = enable;
4303 }
4304
4305 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4309         struct intel_crtc *crtc;
4310
4311         /*
4312          * First get all needed power domains, then put all unneeded, to avoid
4313          * any unnecessary toggling of the power wells.
4314          */
4315         for_each_intel_crtc(dev, crtc) {
4316                 enum intel_display_power_domain domain;
4317
4318                 if (!crtc->base.enabled)
4319                         continue;
4320
4321                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4322
4323                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4324                         intel_display_power_get(dev_priv, domain);
4325         }
4326
4327         for_each_intel_crtc(dev, crtc) {
4328                 enum intel_display_power_domain domain;
4329
4330                 for_each_power_domain(domain, crtc->enabled_power_domains)
4331                         intel_display_power_put(dev_priv, domain);
4332
4333                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4334         }
4335
4336         intel_display_set_init_power(dev_priv, false);
4337 }
4338
4339 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4340 {
4341         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4342
4343         /* Obtain SKU information */
4344         mutex_lock(&dev_priv->dpio_lock);
4345         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4346                 CCK_FUSE_HPLL_FREQ_MASK;
4347         mutex_unlock(&dev_priv->dpio_lock);
4348
4349         return vco_freq[hpll_freq];
4350 }
4351
4352 /* Adjust CDclk dividers to allow high res or save power if possible */
4353 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         u32 val, cmd;
4357
4358         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4359         dev_priv->vlv_cdclk_freq = cdclk;
4360
4361         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4362                 cmd = 2;
4363         else if (cdclk == 266)
4364                 cmd = 1;
4365         else
4366                 cmd = 0;
4367
4368         mutex_lock(&dev_priv->rps.hw_lock);
4369         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4370         val &= ~DSPFREQGUAR_MASK;
4371         val |= (cmd << DSPFREQGUAR_SHIFT);
4372         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4373         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4374                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4375                      50)) {
4376                 DRM_ERROR("timed out waiting for CDclk change\n");
4377         }
4378         mutex_unlock(&dev_priv->rps.hw_lock);
4379
4380         if (cdclk == 400) {
4381                 u32 divider, vco;
4382
4383                 vco = valleyview_get_vco(dev_priv);
4384                 divider = ((vco << 1) / cdclk) - 1;
4385
4386                 mutex_lock(&dev_priv->dpio_lock);
4387                 /* adjust cdclk divider */
4388                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4389                 val &= ~0xf;
4390                 val |= divider;
4391                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4392                 mutex_unlock(&dev_priv->dpio_lock);
4393         }
4394
4395         mutex_lock(&dev_priv->dpio_lock);
4396         /* adjust self-refresh exit latency value */
4397         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4398         val &= ~0x7f;
4399
4400         /*
4401          * For high bandwidth configs, we set a higher latency in the bunit
4402          * so that the core display fetch happens in time to avoid underruns.
4403          */
4404         if (cdclk == 400)
4405                 val |= 4500 / 250; /* 4.5 usec */
4406         else
4407                 val |= 3000 / 250; /* 3.0 usec */
4408         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4409         mutex_unlock(&dev_priv->dpio_lock);
4410
4411         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4412         intel_i2c_reset(dev);
4413 }
4414
4415 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4416 {
4417         int cur_cdclk, vco;
4418         int divider;
4419
4420         vco = valleyview_get_vco(dev_priv);
4421
4422         mutex_lock(&dev_priv->dpio_lock);
4423         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4424         mutex_unlock(&dev_priv->dpio_lock);
4425
4426         divider &= 0xf;
4427
4428         cur_cdclk = (vco << 1) / (divider + 1);
4429
4430         return cur_cdclk;
4431 }
4432
4433 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4434                                  int max_pixclk)
4435 {
4436         /*
4437          * Really only a few cases to deal with, as only 4 CDclks are supported:
4438          *   200MHz
4439          *   267MHz
4440          *   320MHz
4441          *   400MHz
4442          * So we check to see whether we're above 90% of the lower bin and
4443          * adjust if needed.
4444          */
4445         if (max_pixclk > 288000) {
4446                 return 400;
4447         } else if (max_pixclk > 240000) {
4448                 return 320;
4449         } else
4450                 return 266;
4451         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4452 }
4453
4454 /* compute the max pixel clock for new configuration */
4455 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4456 {
4457         struct drm_device *dev = dev_priv->dev;
4458         struct intel_crtc *intel_crtc;
4459         int max_pixclk = 0;
4460
4461         for_each_intel_crtc(dev, intel_crtc) {
4462                 if (intel_crtc->new_enabled)
4463                         max_pixclk = max(max_pixclk,
4464                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4465         }
4466
4467         return max_pixclk;
4468 }
4469
4470 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4471                                             unsigned *prepare_pipes)
4472 {
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474         struct intel_crtc *intel_crtc;
4475         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4476
4477         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4478             dev_priv->vlv_cdclk_freq)
4479                 return;
4480
4481         /* disable/enable all currently active pipes while we change cdclk */
4482         for_each_intel_crtc(dev, intel_crtc)
4483                 if (intel_crtc->base.enabled)
4484                         *prepare_pipes |= (1 << intel_crtc->pipe);
4485 }
4486
4487 static void valleyview_modeset_global_resources(struct drm_device *dev)
4488 {
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4491         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4492
4493         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4494                 valleyview_set_cdclk(dev, req_cdclk);
4495         modeset_update_crtc_power_domains(dev);
4496 }
4497
4498 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4499 {
4500         struct drm_device *dev = crtc->dev;
4501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4502         struct intel_encoder *encoder;
4503         int pipe = intel_crtc->pipe;
4504         bool is_dsi;
4505
4506         WARN_ON(!crtc->enabled);
4507
4508         if (intel_crtc->active)
4509                 return;
4510
4511         intel_crtc->active = true;
4512
4513         for_each_encoder_on_crtc(dev, crtc, encoder)
4514                 if (encoder->pre_pll_enable)
4515                         encoder->pre_pll_enable(encoder);
4516
4517         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4518
4519         if (!is_dsi) {
4520                 if (IS_CHERRYVIEW(dev))
4521                         chv_enable_pll(intel_crtc);
4522                 else
4523                         vlv_enable_pll(intel_crtc);
4524         }
4525
4526         for_each_encoder_on_crtc(dev, crtc, encoder)
4527                 if (encoder->pre_enable)
4528                         encoder->pre_enable(encoder);
4529
4530         i9xx_pfit_enable(intel_crtc);
4531
4532         intel_crtc_load_lut(crtc);
4533
4534         intel_update_watermarks(crtc);
4535         intel_enable_pipe(intel_crtc);
4536         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4537
4538         for_each_encoder_on_crtc(dev, crtc, encoder)
4539                 encoder->enable(encoder);
4540
4541         intel_crtc_enable_planes(crtc);
4542 }
4543
4544 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4545 {
4546         struct drm_device *dev = crtc->dev;
4547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4548         struct intel_encoder *encoder;
4549         int pipe = intel_crtc->pipe;
4550
4551         WARN_ON(!crtc->enabled);
4552
4553         if (intel_crtc->active)
4554                 return;
4555
4556         intel_crtc->active = true;
4557
4558         for_each_encoder_on_crtc(dev, crtc, encoder)
4559                 if (encoder->pre_enable)
4560                         encoder->pre_enable(encoder);
4561
4562         i9xx_enable_pll(intel_crtc);
4563
4564         i9xx_pfit_enable(intel_crtc);
4565
4566         intel_crtc_load_lut(crtc);
4567
4568         intel_update_watermarks(crtc);
4569         intel_enable_pipe(intel_crtc);
4570         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4571
4572         for_each_encoder_on_crtc(dev, crtc, encoder)
4573                 encoder->enable(encoder);
4574
4575         intel_crtc_enable_planes(crtc);
4576 }
4577
4578 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4579 {
4580         struct drm_device *dev = crtc->base.dev;
4581         struct drm_i915_private *dev_priv = dev->dev_private;
4582
4583         if (!crtc->config.gmch_pfit.control)
4584                 return;
4585
4586         assert_pipe_disabled(dev_priv, crtc->pipe);
4587
4588         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4589                          I915_READ(PFIT_CONTROL));
4590         I915_WRITE(PFIT_CONTROL, 0);
4591 }
4592
4593 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4594 {
4595         struct drm_device *dev = crtc->dev;
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         struct intel_encoder *encoder;
4599         int pipe = intel_crtc->pipe;
4600
4601         if (!intel_crtc->active)
4602                 return;
4603
4604         intel_crtc_disable_planes(crtc);
4605
4606         for_each_encoder_on_crtc(dev, crtc, encoder)
4607                 encoder->disable(encoder);
4608
4609         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4610         intel_disable_pipe(dev_priv, pipe);
4611
4612         i9xx_pfit_disable(intel_crtc);
4613
4614         for_each_encoder_on_crtc(dev, crtc, encoder)
4615                 if (encoder->post_disable)
4616                         encoder->post_disable(encoder);
4617
4618         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4619                 if (IS_CHERRYVIEW(dev))
4620                         chv_disable_pll(dev_priv, pipe);
4621                 else if (IS_VALLEYVIEW(dev))
4622                         vlv_disable_pll(dev_priv, pipe);
4623                 else
4624                         i9xx_disable_pll(dev_priv, pipe);
4625         }
4626
4627         intel_crtc->active = false;
4628         intel_update_watermarks(crtc);
4629
4630         intel_update_fbc(dev);
4631 }
4632
4633 static void i9xx_crtc_off(struct drm_crtc *crtc)
4634 {
4635 }
4636
4637 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4638                                     bool enabled)
4639 {
4640         struct drm_device *dev = crtc->dev;
4641         struct drm_i915_master_private *master_priv;
4642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4643         int pipe = intel_crtc->pipe;
4644
4645         if (!dev->primary->master)
4646                 return;
4647
4648         master_priv = dev->primary->master->driver_priv;
4649         if (!master_priv->sarea_priv)
4650                 return;
4651
4652         switch (pipe) {
4653         case 0:
4654                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4655                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4656                 break;
4657         case 1:
4658                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4659                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4660                 break;
4661         default:
4662                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4663                 break;
4664         }
4665 }
4666
4667 /**
4668  * Sets the power management mode of the pipe and plane.
4669  */
4670 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4671 {
4672         struct drm_device *dev = crtc->dev;
4673         struct drm_i915_private *dev_priv = dev->dev_private;
4674         struct intel_encoder *intel_encoder;
4675         bool enable = false;
4676
4677         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4678                 enable |= intel_encoder->connectors_active;
4679
4680         if (enable)
4681                 dev_priv->display.crtc_enable(crtc);
4682         else
4683                 dev_priv->display.crtc_disable(crtc);
4684
4685         intel_crtc_update_sarea(crtc, enable);
4686 }
4687
4688 static void intel_crtc_disable(struct drm_crtc *crtc)
4689 {
4690         struct drm_device *dev = crtc->dev;
4691         struct drm_connector *connector;
4692         struct drm_i915_private *dev_priv = dev->dev_private;
4693
4694         /* crtc should still be enabled when we disable it. */
4695         WARN_ON(!crtc->enabled);
4696
4697         dev_priv->display.crtc_disable(crtc);
4698         intel_crtc_update_sarea(crtc, false);
4699         dev_priv->display.off(crtc);
4700
4701         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4702         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4703         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4704
4705         if (crtc->primary->fb) {
4706                 mutex_lock(&dev->struct_mutex);
4707                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4708                 mutex_unlock(&dev->struct_mutex);
4709                 crtc->primary->fb = NULL;
4710         }
4711
4712         /* Update computed state. */
4713         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4714                 if (!connector->encoder || !connector->encoder->crtc)
4715                         continue;
4716
4717                 if (connector->encoder->crtc != crtc)
4718                         continue;
4719
4720                 connector->dpms = DRM_MODE_DPMS_OFF;
4721                 to_intel_encoder(connector->encoder)->connectors_active = false;
4722         }
4723 }
4724
4725 void intel_encoder_destroy(struct drm_encoder *encoder)
4726 {
4727         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4728
4729         drm_encoder_cleanup(encoder);
4730         kfree(intel_encoder);
4731 }
4732
4733 /* Simple dpms helper for encoders with just one connector, no cloning and only
4734  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4735  * state of the entire output pipe. */
4736 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4737 {
4738         if (mode == DRM_MODE_DPMS_ON) {
4739                 encoder->connectors_active = true;
4740
4741                 intel_crtc_update_dpms(encoder->base.crtc);
4742         } else {
4743                 encoder->connectors_active = false;
4744
4745                 intel_crtc_update_dpms(encoder->base.crtc);
4746         }
4747 }
4748
4749 /* Cross check the actual hw state with our own modeset state tracking (and it's
4750  * internal consistency). */
4751 static void intel_connector_check_state(struct intel_connector *connector)
4752 {
4753         if (connector->get_hw_state(connector)) {
4754                 struct intel_encoder *encoder = connector->encoder;
4755                 struct drm_crtc *crtc;
4756                 bool encoder_enabled;
4757                 enum pipe pipe;
4758
4759                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4760                               connector->base.base.id,
4761                               drm_get_connector_name(&connector->base));
4762
4763                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4764                      "wrong connector dpms state\n");
4765                 WARN(connector->base.encoder != &encoder->base,
4766                      "active connector not linked to encoder\n");
4767                 WARN(!encoder->connectors_active,
4768                      "encoder->connectors_active not set\n");
4769
4770                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4771                 WARN(!encoder_enabled, "encoder not enabled\n");
4772                 if (WARN_ON(!encoder->base.crtc))
4773                         return;
4774
4775                 crtc = encoder->base.crtc;
4776
4777                 WARN(!crtc->enabled, "crtc not enabled\n");
4778                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4779                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4780                      "encoder active on the wrong pipe\n");
4781         }
4782 }
4783
4784 /* Even simpler default implementation, if there's really no special case to
4785  * consider. */
4786 void intel_connector_dpms(struct drm_connector *connector, int mode)
4787 {
4788         /* All the simple cases only support two dpms states. */
4789         if (mode != DRM_MODE_DPMS_ON)
4790                 mode = DRM_MODE_DPMS_OFF;
4791
4792         if (mode == connector->dpms)
4793                 return;
4794
4795         connector->dpms = mode;
4796
4797         /* Only need to change hw state when actually enabled */
4798         if (connector->encoder)
4799                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4800
4801         intel_modeset_check_state(connector->dev);
4802 }
4803
4804 /* Simple connector->get_hw_state implementation for encoders that support only
4805  * one connector and no cloning and hence the encoder state determines the state
4806  * of the connector. */
4807 bool intel_connector_get_hw_state(struct intel_connector *connector)
4808 {
4809         enum pipe pipe = 0;
4810         struct intel_encoder *encoder = connector->encoder;
4811
4812         return encoder->get_hw_state(encoder, &pipe);
4813 }
4814
4815 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4816                                      struct intel_crtc_config *pipe_config)
4817 {
4818         struct drm_i915_private *dev_priv = dev->dev_private;
4819         struct intel_crtc *pipe_B_crtc =
4820                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4821
4822         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4823                       pipe_name(pipe), pipe_config->fdi_lanes);
4824         if (pipe_config->fdi_lanes > 4) {
4825                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4826                               pipe_name(pipe), pipe_config->fdi_lanes);
4827                 return false;
4828         }
4829
4830         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4831                 if (pipe_config->fdi_lanes > 2) {
4832                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4833                                       pipe_config->fdi_lanes);
4834                         return false;
4835                 } else {
4836                         return true;
4837                 }
4838         }
4839
4840         if (INTEL_INFO(dev)->num_pipes == 2)
4841                 return true;
4842
4843         /* Ivybridge 3 pipe is really complicated */
4844         switch (pipe) {
4845         case PIPE_A:
4846                 return true;
4847         case PIPE_B:
4848                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4849                     pipe_config->fdi_lanes > 2) {
4850                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4851                                       pipe_name(pipe), pipe_config->fdi_lanes);
4852                         return false;
4853                 }
4854                 return true;
4855         case PIPE_C:
4856                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4857                     pipe_B_crtc->config.fdi_lanes <= 2) {
4858                         if (pipe_config->fdi_lanes > 2) {
4859                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4860                                               pipe_name(pipe), pipe_config->fdi_lanes);
4861                                 return false;
4862                         }
4863                 } else {
4864                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4865                         return false;
4866                 }
4867                 return true;
4868         default:
4869                 BUG();
4870         }
4871 }
4872
4873 #define RETRY 1
4874 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4875                                        struct intel_crtc_config *pipe_config)
4876 {
4877         struct drm_device *dev = intel_crtc->base.dev;
4878         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4879         int lane, link_bw, fdi_dotclock;
4880         bool setup_ok, needs_recompute = false;
4881
4882 retry:
4883         /* FDI is a binary signal running at ~2.7GHz, encoding
4884          * each output octet as 10 bits. The actual frequency
4885          * is stored as a divider into a 100MHz clock, and the
4886          * mode pixel clock is stored in units of 1KHz.
4887          * Hence the bw of each lane in terms of the mode signal
4888          * is:
4889          */
4890         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4891
4892         fdi_dotclock = adjusted_mode->crtc_clock;
4893
4894         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4895                                            pipe_config->pipe_bpp);
4896
4897         pipe_config->fdi_lanes = lane;
4898
4899         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4900                                link_bw, &pipe_config->fdi_m_n);
4901
4902         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4903                                             intel_crtc->pipe, pipe_config);
4904         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4905                 pipe_config->pipe_bpp -= 2*3;
4906                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4907                               pipe_config->pipe_bpp);
4908                 needs_recompute = true;
4909                 pipe_config->bw_constrained = true;
4910
4911                 goto retry;
4912         }
4913
4914         if (needs_recompute)
4915                 return RETRY;
4916
4917         return setup_ok ? 0 : -EINVAL;
4918 }
4919
4920 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4921                                    struct intel_crtc_config *pipe_config)
4922 {
4923         pipe_config->ips_enabled = i915.enable_ips &&
4924                                    hsw_crtc_supports_ips(crtc) &&
4925                                    pipe_config->pipe_bpp <= 24;
4926 }
4927
4928 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4929                                      struct intel_crtc_config *pipe_config)
4930 {
4931         struct drm_device *dev = crtc->base.dev;
4932         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4933
4934         /* FIXME should check pixel clock limits on all platforms */
4935         if (INTEL_INFO(dev)->gen < 4) {
4936                 struct drm_i915_private *dev_priv = dev->dev_private;
4937                 int clock_limit =
4938                         dev_priv->display.get_display_clock_speed(dev);
4939
4940                 /*
4941                  * Enable pixel doubling when the dot clock
4942                  * is > 90% of the (display) core speed.
4943                  *
4944                  * GDG double wide on either pipe,
4945                  * otherwise pipe A only.
4946                  */
4947                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4948                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4949                         clock_limit *= 2;
4950                         pipe_config->double_wide = true;
4951                 }
4952
4953                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4954                         return -EINVAL;
4955         }
4956
4957         /*
4958          * Pipe horizontal size must be even in:
4959          * - DVO ganged mode
4960          * - LVDS dual channel mode
4961          * - Double wide pipe
4962          */
4963         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4964              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4965                 pipe_config->pipe_src_w &= ~1;
4966
4967         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4968          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4969          */
4970         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4971                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4972                 return -EINVAL;
4973
4974         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4975                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4976         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4977                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4978                  * for lvds. */
4979                 pipe_config->pipe_bpp = 8*3;
4980         }
4981
4982         if (HAS_IPS(dev))
4983                 hsw_compute_ips_config(crtc, pipe_config);
4984
4985         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4986          * clock survives for now. */
4987         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4988                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4989
4990         if (pipe_config->has_pch_encoder)
4991                 return ironlake_fdi_compute_config(crtc, pipe_config);
4992
4993         return 0;
4994 }
4995
4996 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4997 {
4998         return 400000; /* FIXME */
4999 }
5000
5001 static int i945_get_display_clock_speed(struct drm_device *dev)
5002 {
5003         return 400000;
5004 }
5005
5006 static int i915_get_display_clock_speed(struct drm_device *dev)
5007 {
5008         return 333000;
5009 }
5010
5011 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5012 {
5013         return 200000;
5014 }
5015
5016 static int pnv_get_display_clock_speed(struct drm_device *dev)
5017 {
5018         u16 gcfgc = 0;
5019
5020         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5021
5022         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5023         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5024                 return 267000;
5025         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5026                 return 333000;
5027         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5028                 return 444000;
5029         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5030                 return 200000;
5031         default:
5032                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5033         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5034                 return 133000;
5035         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5036                 return 167000;
5037         }
5038 }
5039
5040 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5041 {
5042         u16 gcfgc = 0;
5043
5044         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5045
5046         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5047                 return 133000;
5048         else {
5049                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5050                 case GC_DISPLAY_CLOCK_333_MHZ:
5051                         return 333000;
5052                 default:
5053                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5054                         return 190000;
5055                 }
5056         }
5057 }
5058
5059 static int i865_get_display_clock_speed(struct drm_device *dev)
5060 {
5061         return 266000;
5062 }
5063
5064 static int i855_get_display_clock_speed(struct drm_device *dev)
5065 {
5066         u16 hpllcc = 0;
5067         /* Assume that the hardware is in the high speed state.  This
5068          * should be the default.
5069          */
5070         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5071         case GC_CLOCK_133_200:
5072         case GC_CLOCK_100_200:
5073                 return 200000;
5074         case GC_CLOCK_166_250:
5075                 return 250000;
5076         case GC_CLOCK_100_133:
5077                 return 133000;
5078         }
5079
5080         /* Shouldn't happen */
5081         return 0;
5082 }
5083
5084 static int i830_get_display_clock_speed(struct drm_device *dev)
5085 {
5086         return 133000;
5087 }
5088
5089 static void
5090 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5091 {
5092         while (*num > DATA_LINK_M_N_MASK ||
5093                *den > DATA_LINK_M_N_MASK) {
5094                 *num >>= 1;
5095                 *den >>= 1;
5096         }
5097 }
5098
5099 static void compute_m_n(unsigned int m, unsigned int n,
5100                         uint32_t *ret_m, uint32_t *ret_n)
5101 {
5102         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5103         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5104         intel_reduce_m_n_ratio(ret_m, ret_n);
5105 }
5106
5107 void
5108 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5109                        int pixel_clock, int link_clock,
5110                        struct intel_link_m_n *m_n)
5111 {
5112         m_n->tu = 64;
5113
5114         compute_m_n(bits_per_pixel * pixel_clock,
5115                     link_clock * nlanes * 8,
5116                     &m_n->gmch_m, &m_n->gmch_n);
5117
5118         compute_m_n(pixel_clock, link_clock,
5119                     &m_n->link_m, &m_n->link_n);
5120 }
5121
5122 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5123 {
5124         if (i915.panel_use_ssc >= 0)
5125                 return i915.panel_use_ssc != 0;
5126         return dev_priv->vbt.lvds_use_ssc
5127                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5128 }
5129
5130 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5131 {
5132         struct drm_device *dev = crtc->dev;
5133         struct drm_i915_private *dev_priv = dev->dev_private;
5134         int refclk;
5135
5136         if (IS_VALLEYVIEW(dev)) {
5137                 refclk = 100000;
5138         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5139             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5140                 refclk = dev_priv->vbt.lvds_ssc_freq;
5141                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5142         } else if (!IS_GEN2(dev)) {
5143                 refclk = 96000;
5144         } else {
5145                 refclk = 48000;
5146         }
5147
5148         return refclk;
5149 }
5150
5151 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5152 {
5153         return (1 << dpll->n) << 16 | dpll->m2;
5154 }
5155
5156 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5157 {
5158         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5159 }
5160
5161 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5162                                      intel_clock_t *reduced_clock)
5163 {
5164         struct drm_device *dev = crtc->base.dev;
5165         struct drm_i915_private *dev_priv = dev->dev_private;
5166         int pipe = crtc->pipe;
5167         u32 fp, fp2 = 0;
5168
5169         if (IS_PINEVIEW(dev)) {
5170                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5171                 if (reduced_clock)
5172                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5173         } else {
5174                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5175                 if (reduced_clock)
5176                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5177         }
5178
5179         I915_WRITE(FP0(pipe), fp);
5180         crtc->config.dpll_hw_state.fp0 = fp;
5181
5182         crtc->lowfreq_avail = false;
5183         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5184             reduced_clock && i915.powersave) {
5185                 I915_WRITE(FP1(pipe), fp2);
5186                 crtc->config.dpll_hw_state.fp1 = fp2;
5187                 crtc->lowfreq_avail = true;
5188         } else {
5189                 I915_WRITE(FP1(pipe), fp);
5190                 crtc->config.dpll_hw_state.fp1 = fp;
5191         }
5192 }
5193
5194 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5195                 pipe)
5196 {
5197         u32 reg_val;
5198
5199         /*
5200          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5201          * and set it to a reasonable value instead.
5202          */
5203         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5204         reg_val &= 0xffffff00;
5205         reg_val |= 0x00000030;
5206         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5207
5208         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5209         reg_val &= 0x8cffffff;
5210         reg_val = 0x8c000000;
5211         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5212
5213         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5214         reg_val &= 0xffffff00;
5215         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5216
5217         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5218         reg_val &= 0x00ffffff;
5219         reg_val |= 0xb0000000;
5220         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5221 }
5222
5223 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5224                                          struct intel_link_m_n *m_n)
5225 {
5226         struct drm_device *dev = crtc->base.dev;
5227         struct drm_i915_private *dev_priv = dev->dev_private;
5228         int pipe = crtc->pipe;
5229
5230         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5231         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5232         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5233         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5234 }
5235
5236 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5237                                          struct intel_link_m_n *m_n)
5238 {
5239         struct drm_device *dev = crtc->base.dev;
5240         struct drm_i915_private *dev_priv = dev->dev_private;
5241         int pipe = crtc->pipe;
5242         enum transcoder transcoder = crtc->config.cpu_transcoder;
5243
5244         if (INTEL_INFO(dev)->gen >= 5) {
5245                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5246                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5247                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5248                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5249         } else {
5250                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5251                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5252                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5253                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5254         }
5255 }
5256
5257 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5258 {
5259         if (crtc->config.has_pch_encoder)
5260                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5261         else
5262                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5263 }
5264
5265 static void vlv_update_pll(struct intel_crtc *crtc)
5266 {
5267         struct drm_device *dev = crtc->base.dev;
5268         struct drm_i915_private *dev_priv = dev->dev_private;
5269         int pipe = crtc->pipe;
5270         u32 dpll, mdiv;
5271         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5272         u32 coreclk, reg_val, dpll_md;
5273
5274         mutex_lock(&dev_priv->dpio_lock);
5275
5276         bestn = crtc->config.dpll.n;
5277         bestm1 = crtc->config.dpll.m1;
5278         bestm2 = crtc->config.dpll.m2;
5279         bestp1 = crtc->config.dpll.p1;
5280         bestp2 = crtc->config.dpll.p2;
5281
5282         /* See eDP HDMI DPIO driver vbios notes doc */
5283
5284         /* PLL B needs special handling */
5285         if (pipe)
5286                 vlv_pllb_recal_opamp(dev_priv, pipe);
5287
5288         /* Set up Tx target for periodic Rcomp update */
5289         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5290
5291         /* Disable target IRef on PLL */
5292         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5293         reg_val &= 0x00ffffff;
5294         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5295
5296         /* Disable fast lock */
5297         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5298
5299         /* Set idtafcrecal before PLL is enabled */
5300         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5301         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5302         mdiv |= ((bestn << DPIO_N_SHIFT));
5303         mdiv |= (1 << DPIO_K_SHIFT);
5304
5305         /*
5306          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5307          * but we don't support that).
5308          * Note: don't use the DAC post divider as it seems unstable.
5309          */
5310         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5311         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5312
5313         mdiv |= DPIO_ENABLE_CALIBRATION;
5314         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5315
5316         /* Set HBR and RBR LPF coefficients */
5317         if (crtc->config.port_clock == 162000 ||
5318             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5319             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5320                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5321                                  0x009f0003);
5322         else
5323                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5324                                  0x00d0000f);
5325
5326         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5327             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5328                 /* Use SSC source */
5329                 if (!pipe)
5330                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5331                                          0x0df40000);
5332                 else
5333                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5334                                          0x0df70000);
5335         } else { /* HDMI or VGA */
5336                 /* Use bend source */
5337                 if (!pipe)
5338                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5339                                          0x0df70000);
5340                 else
5341                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5342                                          0x0df40000);
5343         }
5344
5345         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5346         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5347         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5348             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5349                 coreclk |= 0x01000000;
5350         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5351
5352         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5353
5354         /*
5355          * Enable DPIO clock input. We should never disable the reference
5356          * clock for pipe B, since VGA hotplug / manual detection depends
5357          * on it.
5358          */
5359         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5360                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5361         /* We should never disable this, set it here for state tracking */
5362         if (pipe == PIPE_B)
5363                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5364         dpll |= DPLL_VCO_ENABLE;
5365         crtc->config.dpll_hw_state.dpll = dpll;
5366
5367         dpll_md = (crtc->config.pixel_multiplier - 1)
5368                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5369         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5370
5371         mutex_unlock(&dev_priv->dpio_lock);
5372 }
5373
5374 static void chv_update_pll(struct intel_crtc *crtc)
5375 {
5376         struct drm_device *dev = crtc->base.dev;
5377         struct drm_i915_private *dev_priv = dev->dev_private;
5378         int pipe = crtc->pipe;
5379         int dpll_reg = DPLL(crtc->pipe);
5380         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5381         u32 val, loopfilter, intcoeff;
5382         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5383         int refclk;
5384
5385         mutex_lock(&dev_priv->dpio_lock);
5386
5387         bestn = crtc->config.dpll.n;
5388         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5389         bestm1 = crtc->config.dpll.m1;
5390         bestm2 = crtc->config.dpll.m2 >> 22;
5391         bestp1 = crtc->config.dpll.p1;
5392         bestp2 = crtc->config.dpll.p2;
5393
5394         /*
5395          * Enable Refclk and SSC
5396          */
5397         val = I915_READ(dpll_reg);
5398         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5399         I915_WRITE(dpll_reg, val);
5400
5401         /* Propagate soft reset to data lane reset */
5402         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5403         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5404         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5405
5406         /* Disable 10bit clock to display controller */
5407         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5408         val &= ~DPIO_DCLKP_EN;
5409         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5410
5411         /* p1 and p2 divider */
5412         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5413                         5 << DPIO_CHV_S1_DIV_SHIFT |
5414                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5415                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5416                         1 << DPIO_CHV_K_DIV_SHIFT);
5417
5418         /* Feedback post-divider - m2 */
5419         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5420
5421         /* Feedback refclk divider - n and m1 */
5422         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5423                         DPIO_CHV_M1_DIV_BY_2 |
5424                         1 << DPIO_CHV_N_DIV_SHIFT);
5425
5426         /* M2 fraction division */
5427         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5428
5429         /* M2 fraction division enable */
5430         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5431                        DPIO_CHV_FRAC_DIV_EN |
5432                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5433
5434         /* Loop filter */
5435         refclk = i9xx_get_refclk(&crtc->base, 0);
5436         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5437                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5438         if (refclk == 100000)
5439                 intcoeff = 11;
5440         else if (refclk == 38400)
5441                 intcoeff = 10;
5442         else
5443                 intcoeff = 9;
5444         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5445         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5446
5447         /* AFC Recal */
5448         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5449                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5450                         DPIO_AFC_RECAL);
5451
5452         mutex_unlock(&dev_priv->dpio_lock);
5453 }
5454
5455 static void i9xx_update_pll(struct intel_crtc *crtc,
5456                             intel_clock_t *reduced_clock,
5457                             int num_connectors)
5458 {
5459         struct drm_device *dev = crtc->base.dev;
5460         struct drm_i915_private *dev_priv = dev->dev_private;
5461         u32 dpll;
5462         bool is_sdvo;
5463         struct dpll *clock = &crtc->config.dpll;
5464
5465         i9xx_update_pll_dividers(crtc, reduced_clock);
5466
5467         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5468                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5469
5470         dpll = DPLL_VGA_MODE_DIS;
5471
5472         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5473                 dpll |= DPLLB_MODE_LVDS;
5474         else
5475                 dpll |= DPLLB_MODE_DAC_SERIAL;
5476
5477         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5478                 dpll |= (crtc->config.pixel_multiplier - 1)
5479                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5480         }
5481
5482         if (is_sdvo)
5483                 dpll |= DPLL_SDVO_HIGH_SPEED;
5484
5485         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5486                 dpll |= DPLL_SDVO_HIGH_SPEED;
5487
5488         /* compute bitmask from p1 value */
5489         if (IS_PINEVIEW(dev))
5490                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5491         else {
5492                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5493                 if (IS_G4X(dev) && reduced_clock)
5494                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5495         }
5496         switch (clock->p2) {
5497         case 5:
5498                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5499                 break;
5500         case 7:
5501                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5502                 break;
5503         case 10:
5504                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5505                 break;
5506         case 14:
5507                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5508                 break;
5509         }
5510         if (INTEL_INFO(dev)->gen >= 4)
5511                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5512
5513         if (crtc->config.sdvo_tv_clock)
5514                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5515         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5516                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5517                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5518         else
5519                 dpll |= PLL_REF_INPUT_DREFCLK;
5520
5521         dpll |= DPLL_VCO_ENABLE;
5522         crtc->config.dpll_hw_state.dpll = dpll;
5523
5524         if (INTEL_INFO(dev)->gen >= 4) {
5525                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5526                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5527                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5528         }
5529 }
5530
5531 static void i8xx_update_pll(struct intel_crtc *crtc,
5532                             intel_clock_t *reduced_clock,
5533                             int num_connectors)
5534 {
5535         struct drm_device *dev = crtc->base.dev;
5536         struct drm_i915_private *dev_priv = dev->dev_private;
5537         u32 dpll;
5538         struct dpll *clock = &crtc->config.dpll;
5539
5540         i9xx_update_pll_dividers(crtc, reduced_clock);
5541
5542         dpll = DPLL_VGA_MODE_DIS;
5543
5544         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5545                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5546         } else {
5547                 if (clock->p1 == 2)
5548                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5549                 else
5550                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5551                 if (clock->p2 == 4)
5552                         dpll |= PLL_P2_DIVIDE_BY_4;
5553         }
5554
5555         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5556                 dpll |= DPLL_DVO_2X_MODE;
5557
5558         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5559                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5560                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5561         else
5562                 dpll |= PLL_REF_INPUT_DREFCLK;
5563
5564         dpll |= DPLL_VCO_ENABLE;
5565         crtc->config.dpll_hw_state.dpll = dpll;
5566 }
5567
5568 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5569 {
5570         struct drm_device *dev = intel_crtc->base.dev;
5571         struct drm_i915_private *dev_priv = dev->dev_private;
5572         enum pipe pipe = intel_crtc->pipe;
5573         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5574         struct drm_display_mode *adjusted_mode =
5575                 &intel_crtc->config.adjusted_mode;
5576         uint32_t crtc_vtotal, crtc_vblank_end;
5577         int vsyncshift = 0;
5578
5579         /* We need to be careful not to changed the adjusted mode, for otherwise
5580          * the hw state checker will get angry at the mismatch. */
5581         crtc_vtotal = adjusted_mode->crtc_vtotal;
5582         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5583
5584         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5585                 /* the chip adds 2 halflines automatically */
5586                 crtc_vtotal -= 1;
5587                 crtc_vblank_end -= 1;
5588
5589                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5590                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5591                 else
5592                         vsyncshift = adjusted_mode->crtc_hsync_start -
5593                                 adjusted_mode->crtc_htotal / 2;
5594                 if (vsyncshift < 0)
5595                         vsyncshift += adjusted_mode->crtc_htotal;
5596         }
5597
5598         if (INTEL_INFO(dev)->gen > 3)
5599                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5600
5601         I915_WRITE(HTOTAL(cpu_transcoder),
5602                    (adjusted_mode->crtc_hdisplay - 1) |
5603                    ((adjusted_mode->crtc_htotal - 1) << 16));
5604         I915_WRITE(HBLANK(cpu_transcoder),
5605                    (adjusted_mode->crtc_hblank_start - 1) |
5606                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5607         I915_WRITE(HSYNC(cpu_transcoder),
5608                    (adjusted_mode->crtc_hsync_start - 1) |
5609                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5610
5611         I915_WRITE(VTOTAL(cpu_transcoder),
5612                    (adjusted_mode->crtc_vdisplay - 1) |
5613                    ((crtc_vtotal - 1) << 16));
5614         I915_WRITE(VBLANK(cpu_transcoder),
5615                    (adjusted_mode->crtc_vblank_start - 1) |
5616                    ((crtc_vblank_end - 1) << 16));
5617         I915_WRITE(VSYNC(cpu_transcoder),
5618                    (adjusted_mode->crtc_vsync_start - 1) |
5619                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5620
5621         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5622          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5623          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5624          * bits. */
5625         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5626             (pipe == PIPE_B || pipe == PIPE_C))
5627                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5628
5629         /* pipesrc controls the size that is scaled from, which should
5630          * always be the user's requested size.
5631          */
5632         I915_WRITE(PIPESRC(pipe),
5633                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5634                    (intel_crtc->config.pipe_src_h - 1));
5635 }
5636
5637 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5638                                    struct intel_crtc_config *pipe_config)
5639 {
5640         struct drm_device *dev = crtc->base.dev;
5641         struct drm_i915_private *dev_priv = dev->dev_private;
5642         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5643         uint32_t tmp;
5644
5645         tmp = I915_READ(HTOTAL(cpu_transcoder));
5646         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5647         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5648         tmp = I915_READ(HBLANK(cpu_transcoder));
5649         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5650         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5651         tmp = I915_READ(HSYNC(cpu_transcoder));
5652         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5653         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5654
5655         tmp = I915_READ(VTOTAL(cpu_transcoder));
5656         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5657         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5658         tmp = I915_READ(VBLANK(cpu_transcoder));
5659         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5660         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5661         tmp = I915_READ(VSYNC(cpu_transcoder));
5662         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5663         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5664
5665         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5666                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5667                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5668                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5669         }
5670
5671         tmp = I915_READ(PIPESRC(crtc->pipe));
5672         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5673         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5674
5675         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5676         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5677 }
5678
5679 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5680                                  struct intel_crtc_config *pipe_config)
5681 {
5682         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5683         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5684         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5685         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5686
5687         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5688         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5689         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5690         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5691
5692         mode->flags = pipe_config->adjusted_mode.flags;
5693
5694         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5695         mode->flags |= pipe_config->adjusted_mode.flags;
5696 }
5697
5698 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5699 {
5700         struct drm_device *dev = intel_crtc->base.dev;
5701         struct drm_i915_private *dev_priv = dev->dev_private;
5702         uint32_t pipeconf;
5703
5704         pipeconf = 0;
5705
5706         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5707             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5708                 pipeconf |= PIPECONF_ENABLE;
5709
5710         if (intel_crtc->config.double_wide)
5711                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5712
5713         /* only g4x and later have fancy bpc/dither controls */
5714         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5715                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5716                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5717                         pipeconf |= PIPECONF_DITHER_EN |
5718                                     PIPECONF_DITHER_TYPE_SP;
5719
5720                 switch (intel_crtc->config.pipe_bpp) {
5721                 case 18:
5722                         pipeconf |= PIPECONF_6BPC;
5723                         break;
5724                 case 24:
5725                         pipeconf |= PIPECONF_8BPC;
5726                         break;
5727                 case 30:
5728                         pipeconf |= PIPECONF_10BPC;
5729                         break;
5730                 default:
5731                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5732                         BUG();
5733                 }
5734         }
5735
5736         if (HAS_PIPE_CXSR(dev)) {
5737                 if (intel_crtc->lowfreq_avail) {
5738                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5739                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5740                 } else {
5741                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5742                 }
5743         }
5744
5745         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5746                 if (INTEL_INFO(dev)->gen < 4 ||
5747                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5748                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5749                 else
5750                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5751         } else
5752                 pipeconf |= PIPECONF_PROGRESSIVE;
5753
5754         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5755                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5756
5757         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5758         POSTING_READ(PIPECONF(intel_crtc->pipe));
5759 }
5760
5761 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5762                               int x, int y,
5763                               struct drm_framebuffer *fb)
5764 {
5765         struct drm_device *dev = crtc->dev;
5766         struct drm_i915_private *dev_priv = dev->dev_private;
5767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5768         int pipe = intel_crtc->pipe;
5769         int plane = intel_crtc->plane;
5770         int refclk, num_connectors = 0;
5771         intel_clock_t clock, reduced_clock;
5772         u32 dspcntr;
5773         bool ok, has_reduced_clock = false;
5774         bool is_lvds = false, is_dsi = false;
5775         struct intel_encoder *encoder;
5776         const intel_limit_t *limit;
5777         int ret;
5778
5779         for_each_encoder_on_crtc(dev, crtc, encoder) {
5780                 switch (encoder->type) {
5781                 case INTEL_OUTPUT_LVDS:
5782                         is_lvds = true;
5783                         break;
5784                 case INTEL_OUTPUT_DSI:
5785                         is_dsi = true;
5786                         break;
5787                 }
5788
5789                 num_connectors++;
5790         }
5791
5792         if (is_dsi)
5793                 goto skip_dpll;
5794
5795         if (!intel_crtc->config.clock_set) {
5796                 refclk = i9xx_get_refclk(crtc, num_connectors);
5797
5798                 /*
5799                  * Returns a set of divisors for the desired target clock with
5800                  * the given refclk, or FALSE.  The returned values represent
5801                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5802                  * 2) / p1 / p2.
5803                  */
5804                 limit = intel_limit(crtc, refclk);
5805                 ok = dev_priv->display.find_dpll(limit, crtc,
5806                                                  intel_crtc->config.port_clock,
5807                                                  refclk, NULL, &clock);
5808                 if (!ok) {
5809                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5810                         return -EINVAL;
5811                 }
5812
5813                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5814                         /*
5815                          * Ensure we match the reduced clock's P to the target
5816                          * clock.  If the clocks don't match, we can't switch
5817                          * the display clock by using the FP0/FP1. In such case
5818                          * we will disable the LVDS downclock feature.
5819                          */
5820                         has_reduced_clock =
5821                                 dev_priv->display.find_dpll(limit, crtc,
5822                                                             dev_priv->lvds_downclock,
5823                                                             refclk, &clock,
5824                                                             &reduced_clock);
5825                 }
5826                 /* Compat-code for transition, will disappear. */
5827                 intel_crtc->config.dpll.n = clock.n;
5828                 intel_crtc->config.dpll.m1 = clock.m1;
5829                 intel_crtc->config.dpll.m2 = clock.m2;
5830                 intel_crtc->config.dpll.p1 = clock.p1;
5831                 intel_crtc->config.dpll.p2 = clock.p2;
5832         }
5833
5834         if (IS_GEN2(dev)) {
5835                 i8xx_update_pll(intel_crtc,
5836                                 has_reduced_clock ? &reduced_clock : NULL,
5837                                 num_connectors);
5838         } else if (IS_CHERRYVIEW(dev)) {
5839                 chv_update_pll(intel_crtc);
5840         } else if (IS_VALLEYVIEW(dev)) {
5841                 vlv_update_pll(intel_crtc);
5842         } else {
5843                 i9xx_update_pll(intel_crtc,
5844                                 has_reduced_clock ? &reduced_clock : NULL,
5845                                 num_connectors);
5846         }
5847
5848 skip_dpll:
5849         /* Set up the display plane register */
5850         dspcntr = DISPPLANE_GAMMA_ENABLE;
5851
5852         if (!IS_VALLEYVIEW(dev)) {
5853                 if (pipe == 0)
5854                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5855                 else
5856                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5857         }
5858
5859         if (intel_crtc->config.has_dp_encoder)
5860                 intel_dp_set_m_n(intel_crtc);
5861
5862         intel_set_pipe_timings(intel_crtc);
5863
5864         /* pipesrc and dspsize control the size that is scaled from,
5865          * which should always be the user's requested size.
5866          */
5867         I915_WRITE(DSPSIZE(plane),
5868                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5869                    (intel_crtc->config.pipe_src_w - 1));
5870         I915_WRITE(DSPPOS(plane), 0);
5871
5872         i9xx_set_pipeconf(intel_crtc);
5873
5874         I915_WRITE(DSPCNTR(plane), dspcntr);
5875         POSTING_READ(DSPCNTR(plane));
5876
5877         ret = intel_pipe_set_base(crtc, x, y, fb);
5878
5879         return ret;
5880 }
5881
5882 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5883                                  struct intel_crtc_config *pipe_config)
5884 {
5885         struct drm_device *dev = crtc->base.dev;
5886         struct drm_i915_private *dev_priv = dev->dev_private;
5887         uint32_t tmp;
5888
5889         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5890                 return;
5891
5892         tmp = I915_READ(PFIT_CONTROL);
5893         if (!(tmp & PFIT_ENABLE))
5894                 return;
5895
5896         /* Check whether the pfit is attached to our pipe. */
5897         if (INTEL_INFO(dev)->gen < 4) {
5898                 if (crtc->pipe != PIPE_B)
5899                         return;
5900         } else {
5901                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5902                         return;
5903         }
5904
5905         pipe_config->gmch_pfit.control = tmp;
5906         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5907         if (INTEL_INFO(dev)->gen < 5)
5908                 pipe_config->gmch_pfit.lvds_border_bits =
5909                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5910 }
5911
5912 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5913                                struct intel_crtc_config *pipe_config)
5914 {
5915         struct drm_device *dev = crtc->base.dev;
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917         int pipe = pipe_config->cpu_transcoder;
5918         intel_clock_t clock;
5919         u32 mdiv;
5920         int refclk = 100000;
5921
5922         mutex_lock(&dev_priv->dpio_lock);
5923         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5924         mutex_unlock(&dev_priv->dpio_lock);
5925
5926         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5927         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5928         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5929         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5930         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5931
5932         vlv_clock(refclk, &clock);
5933
5934         /* clock.dot is the fast clock */
5935         pipe_config->port_clock = clock.dot / 5;
5936 }
5937
5938 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5939                                   struct intel_plane_config *plane_config)
5940 {
5941         struct drm_device *dev = crtc->base.dev;
5942         struct drm_i915_private *dev_priv = dev->dev_private;
5943         u32 val, base, offset;
5944         int pipe = crtc->pipe, plane = crtc->plane;
5945         int fourcc, pixel_format;
5946         int aligned_height;
5947
5948         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5949         if (!crtc->base.primary->fb) {
5950                 DRM_DEBUG_KMS("failed to alloc fb\n");
5951                 return;
5952         }
5953
5954         val = I915_READ(DSPCNTR(plane));
5955
5956         if (INTEL_INFO(dev)->gen >= 4)
5957                 if (val & DISPPLANE_TILED)
5958                         plane_config->tiled = true;
5959
5960         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5961         fourcc = intel_format_to_fourcc(pixel_format);
5962         crtc->base.primary->fb->pixel_format = fourcc;
5963         crtc->base.primary->fb->bits_per_pixel =
5964                 drm_format_plane_cpp(fourcc, 0) * 8;
5965
5966         if (INTEL_INFO(dev)->gen >= 4) {
5967                 if (plane_config->tiled)
5968                         offset = I915_READ(DSPTILEOFF(plane));
5969                 else
5970                         offset = I915_READ(DSPLINOFF(plane));
5971                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5972         } else {
5973                 base = I915_READ(DSPADDR(plane));
5974         }
5975         plane_config->base = base;
5976
5977         val = I915_READ(PIPESRC(pipe));
5978         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5979         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5980
5981         val = I915_READ(DSPSTRIDE(pipe));
5982         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5983
5984         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5985                                             plane_config->tiled);
5986
5987         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5988                                    aligned_height, PAGE_SIZE);
5989
5990         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5991                       pipe, plane, crtc->base.primary->fb->width,
5992                       crtc->base.primary->fb->height,
5993                       crtc->base.primary->fb->bits_per_pixel, base,
5994                       crtc->base.primary->fb->pitches[0],
5995                       plane_config->size);
5996
5997 }
5998
5999 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6000                                struct intel_crtc_config *pipe_config)
6001 {
6002         struct drm_device *dev = crtc->base.dev;
6003         struct drm_i915_private *dev_priv = dev->dev_private;
6004         int pipe = pipe_config->cpu_transcoder;
6005         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6006         intel_clock_t clock;
6007         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6008         int refclk = 100000;
6009
6010         mutex_lock(&dev_priv->dpio_lock);
6011         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6012         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6013         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6014         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6015         mutex_unlock(&dev_priv->dpio_lock);
6016
6017         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6018         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6019         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6020         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6021         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6022
6023         chv_clock(refclk, &clock);
6024
6025         /* clock.dot is the fast clock */
6026         pipe_config->port_clock = clock.dot / 5;
6027 }
6028
6029 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6030                                  struct intel_crtc_config *pipe_config)
6031 {
6032         struct drm_device *dev = crtc->base.dev;
6033         struct drm_i915_private *dev_priv = dev->dev_private;
6034         uint32_t tmp;
6035
6036         if (!intel_display_power_enabled(dev_priv,
6037                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6038                 return false;
6039
6040         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6041         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6042
6043         tmp = I915_READ(PIPECONF(crtc->pipe));
6044         if (!(tmp & PIPECONF_ENABLE))
6045                 return false;
6046
6047         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6048                 switch (tmp & PIPECONF_BPC_MASK) {
6049                 case PIPECONF_6BPC:
6050                         pipe_config->pipe_bpp = 18;
6051                         break;
6052                 case PIPECONF_8BPC:
6053                         pipe_config->pipe_bpp = 24;
6054                         break;
6055                 case PIPECONF_10BPC:
6056                         pipe_config->pipe_bpp = 30;
6057                         break;
6058                 default:
6059                         break;
6060                 }
6061         }
6062
6063         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6064                 pipe_config->limited_color_range = true;
6065
6066         if (INTEL_INFO(dev)->gen < 4)
6067                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6068
6069         intel_get_pipe_timings(crtc, pipe_config);
6070
6071         i9xx_get_pfit_config(crtc, pipe_config);
6072
6073         if (INTEL_INFO(dev)->gen >= 4) {
6074                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6075                 pipe_config->pixel_multiplier =
6076                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6077                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6078                 pipe_config->dpll_hw_state.dpll_md = tmp;
6079         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6080                 tmp = I915_READ(DPLL(crtc->pipe));
6081                 pipe_config->pixel_multiplier =
6082                         ((tmp & SDVO_MULTIPLIER_MASK)
6083                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6084         } else {
6085                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6086                  * port and will be fixed up in the encoder->get_config
6087                  * function. */
6088                 pipe_config->pixel_multiplier = 1;
6089         }
6090         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6091         if (!IS_VALLEYVIEW(dev)) {
6092                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6093                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6094         } else {
6095                 /* Mask out read-only status bits. */
6096                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6097                                                      DPLL_PORTC_READY_MASK |
6098                                                      DPLL_PORTB_READY_MASK);
6099         }
6100
6101         if (IS_CHERRYVIEW(dev))
6102                 chv_crtc_clock_get(crtc, pipe_config);
6103         else if (IS_VALLEYVIEW(dev))
6104                 vlv_crtc_clock_get(crtc, pipe_config);
6105         else
6106                 i9xx_crtc_clock_get(crtc, pipe_config);
6107
6108         return true;
6109 }
6110
6111 static void ironlake_init_pch_refclk(struct drm_device *dev)
6112 {
6113         struct drm_i915_private *dev_priv = dev->dev_private;
6114         struct drm_mode_config *mode_config = &dev->mode_config;
6115         struct intel_encoder *encoder;
6116         u32 val, final;
6117         bool has_lvds = false;
6118         bool has_cpu_edp = false;
6119         bool has_panel = false;
6120         bool has_ck505 = false;
6121         bool can_ssc = false;
6122
6123         /* We need to take the global config into account */
6124         list_for_each_entry(encoder, &mode_config->encoder_list,
6125                             base.head) {
6126                 switch (encoder->type) {
6127                 case INTEL_OUTPUT_LVDS:
6128                         has_panel = true;
6129                         has_lvds = true;
6130                         break;
6131                 case INTEL_OUTPUT_EDP:
6132                         has_panel = true;
6133                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6134                                 has_cpu_edp = true;
6135                         break;
6136                 }
6137         }
6138
6139         if (HAS_PCH_IBX(dev)) {
6140                 has_ck505 = dev_priv->vbt.display_clock_mode;
6141                 can_ssc = has_ck505;
6142         } else {
6143                 has_ck505 = false;
6144                 can_ssc = true;
6145         }
6146
6147         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6148                       has_panel, has_lvds, has_ck505);
6149
6150         /* Ironlake: try to setup display ref clock before DPLL
6151          * enabling. This is only under driver's control after
6152          * PCH B stepping, previous chipset stepping should be
6153          * ignoring this setting.
6154          */
6155         val = I915_READ(PCH_DREF_CONTROL);
6156
6157         /* As we must carefully and slowly disable/enable each source in turn,
6158          * compute the final state we want first and check if we need to
6159          * make any changes at all.
6160          */
6161         final = val;
6162         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6163         if (has_ck505)
6164                 final |= DREF_NONSPREAD_CK505_ENABLE;
6165         else
6166                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6167
6168         final &= ~DREF_SSC_SOURCE_MASK;
6169         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6170         final &= ~DREF_SSC1_ENABLE;
6171
6172         if (has_panel) {
6173                 final |= DREF_SSC_SOURCE_ENABLE;
6174
6175                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6176                         final |= DREF_SSC1_ENABLE;
6177
6178                 if (has_cpu_edp) {
6179                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6180                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6181                         else
6182                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6183                 } else
6184                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6185         } else {
6186                 final |= DREF_SSC_SOURCE_DISABLE;
6187                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6188         }
6189
6190         if (final == val)
6191                 return;
6192
6193         /* Always enable nonspread source */
6194         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6195
6196         if (has_ck505)
6197                 val |= DREF_NONSPREAD_CK505_ENABLE;
6198         else
6199                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6200
6201         if (has_panel) {
6202                 val &= ~DREF_SSC_SOURCE_MASK;
6203                 val |= DREF_SSC_SOURCE_ENABLE;
6204
6205                 /* SSC must be turned on before enabling the CPU output  */
6206                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6207                         DRM_DEBUG_KMS("Using SSC on panel\n");
6208                         val |= DREF_SSC1_ENABLE;
6209                 } else
6210                         val &= ~DREF_SSC1_ENABLE;
6211
6212                 /* Get SSC going before enabling the outputs */
6213                 I915_WRITE(PCH_DREF_CONTROL, val);
6214                 POSTING_READ(PCH_DREF_CONTROL);
6215                 udelay(200);
6216
6217                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6218
6219                 /* Enable CPU source on CPU attached eDP */
6220                 if (has_cpu_edp) {
6221                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6222                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6223                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6224                         }
6225                         else
6226                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6227                 } else
6228                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6229
6230                 I915_WRITE(PCH_DREF_CONTROL, val);
6231                 POSTING_READ(PCH_DREF_CONTROL);
6232                 udelay(200);
6233         } else {
6234                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6235
6236                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6237
6238                 /* Turn off CPU output */
6239                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6240
6241                 I915_WRITE(PCH_DREF_CONTROL, val);
6242                 POSTING_READ(PCH_DREF_CONTROL);
6243                 udelay(200);
6244
6245                 /* Turn off the SSC source */
6246                 val &= ~DREF_SSC_SOURCE_MASK;
6247                 val |= DREF_SSC_SOURCE_DISABLE;
6248
6249                 /* Turn off SSC1 */
6250                 val &= ~DREF_SSC1_ENABLE;
6251
6252                 I915_WRITE(PCH_DREF_CONTROL, val);
6253                 POSTING_READ(PCH_DREF_CONTROL);
6254                 udelay(200);
6255         }
6256
6257         BUG_ON(val != final);
6258 }
6259
6260 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6261 {
6262         uint32_t tmp;
6263
6264         tmp = I915_READ(SOUTH_CHICKEN2);
6265         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6266         I915_WRITE(SOUTH_CHICKEN2, tmp);
6267
6268         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6269                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6270                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6271
6272         tmp = I915_READ(SOUTH_CHICKEN2);
6273         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6274         I915_WRITE(SOUTH_CHICKEN2, tmp);
6275
6276         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6277                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6278                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6279 }
6280
6281 /* WaMPhyProgramming:hsw */
6282 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6283 {
6284         uint32_t tmp;
6285
6286         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6287         tmp &= ~(0xFF << 24);
6288         tmp |= (0x12 << 24);
6289         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6290
6291         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6292         tmp |= (1 << 11);
6293         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6294
6295         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6296         tmp |= (1 << 11);
6297         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6298
6299         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6300         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6301         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6302
6303         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6304         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6305         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6306
6307         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6308         tmp &= ~(7 << 13);
6309         tmp |= (5 << 13);
6310         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6311
6312         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6313         tmp &= ~(7 << 13);
6314         tmp |= (5 << 13);
6315         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6316
6317         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6318         tmp &= ~0xFF;
6319         tmp |= 0x1C;
6320         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6321
6322         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6323         tmp &= ~0xFF;
6324         tmp |= 0x1C;
6325         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6326
6327         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6328         tmp &= ~(0xFF << 16);
6329         tmp |= (0x1C << 16);
6330         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6331
6332         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6333         tmp &= ~(0xFF << 16);
6334         tmp |= (0x1C << 16);
6335         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6336
6337         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6338         tmp |= (1 << 27);
6339         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6340
6341         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6342         tmp |= (1 << 27);
6343         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6344
6345         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6346         tmp &= ~(0xF << 28);
6347         tmp |= (4 << 28);
6348         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6349
6350         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6351         tmp &= ~(0xF << 28);
6352         tmp |= (4 << 28);
6353         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6354 }
6355
6356 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6357  * Programming" based on the parameters passed:
6358  * - Sequence to enable CLKOUT_DP
6359  * - Sequence to enable CLKOUT_DP without spread
6360  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6361  */
6362 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6363                                  bool with_fdi)
6364 {
6365         struct drm_i915_private *dev_priv = dev->dev_private;
6366         uint32_t reg, tmp;
6367
6368         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6369                 with_spread = true;
6370         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6371                  with_fdi, "LP PCH doesn't have FDI\n"))
6372                 with_fdi = false;
6373
6374         mutex_lock(&dev_priv->dpio_lock);
6375
6376         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6377         tmp &= ~SBI_SSCCTL_DISABLE;
6378         tmp |= SBI_SSCCTL_PATHALT;
6379         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6380
6381         udelay(24);
6382
6383         if (with_spread) {
6384                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6385                 tmp &= ~SBI_SSCCTL_PATHALT;
6386                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6387
6388                 if (with_fdi) {
6389                         lpt_reset_fdi_mphy(dev_priv);
6390                         lpt_program_fdi_mphy(dev_priv);
6391                 }
6392         }
6393
6394         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6395                SBI_GEN0 : SBI_DBUFF0;
6396         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6397         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6398         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6399
6400         mutex_unlock(&dev_priv->dpio_lock);
6401 }
6402
6403 /* Sequence to disable CLKOUT_DP */
6404 static void lpt_disable_clkout_dp(struct drm_device *dev)
6405 {
6406         struct drm_i915_private *dev_priv = dev->dev_private;
6407         uint32_t reg, tmp;
6408
6409         mutex_lock(&dev_priv->dpio_lock);
6410
6411         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6412                SBI_GEN0 : SBI_DBUFF0;
6413         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6414         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6415         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6416
6417         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6418         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6419                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6420                         tmp |= SBI_SSCCTL_PATHALT;
6421                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6422                         udelay(32);
6423                 }
6424                 tmp |= SBI_SSCCTL_DISABLE;
6425                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6426         }
6427
6428         mutex_unlock(&dev_priv->dpio_lock);
6429 }
6430
6431 static void lpt_init_pch_refclk(struct drm_device *dev)
6432 {
6433         struct drm_mode_config *mode_config = &dev->mode_config;
6434         struct intel_encoder *encoder;
6435         bool has_vga = false;
6436
6437         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6438                 switch (encoder->type) {
6439                 case INTEL_OUTPUT_ANALOG:
6440                         has_vga = true;
6441                         break;
6442                 }
6443         }
6444
6445         if (has_vga)
6446                 lpt_enable_clkout_dp(dev, true, true);
6447         else
6448                 lpt_disable_clkout_dp(dev);
6449 }
6450
6451 /*
6452  * Initialize reference clocks when the driver loads
6453  */
6454 void intel_init_pch_refclk(struct drm_device *dev)
6455 {
6456         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6457                 ironlake_init_pch_refclk(dev);
6458         else if (HAS_PCH_LPT(dev))
6459                 lpt_init_pch_refclk(dev);
6460 }
6461
6462 static int ironlake_get_refclk(struct drm_crtc *crtc)
6463 {
6464         struct drm_device *dev = crtc->dev;
6465         struct drm_i915_private *dev_priv = dev->dev_private;
6466         struct intel_encoder *encoder;
6467         int num_connectors = 0;
6468         bool is_lvds = false;
6469
6470         for_each_encoder_on_crtc(dev, crtc, encoder) {
6471                 switch (encoder->type) {
6472                 case INTEL_OUTPUT_LVDS:
6473                         is_lvds = true;
6474                         break;
6475                 }
6476                 num_connectors++;
6477         }
6478
6479         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6480                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6481                               dev_priv->vbt.lvds_ssc_freq);
6482                 return dev_priv->vbt.lvds_ssc_freq;
6483         }
6484
6485         return 120000;
6486 }
6487
6488 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6489 {
6490         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6492         int pipe = intel_crtc->pipe;
6493         uint32_t val;
6494
6495         val = 0;
6496
6497         switch (intel_crtc->config.pipe_bpp) {
6498         case 18:
6499                 val |= PIPECONF_6BPC;
6500                 break;
6501         case 24:
6502                 val |= PIPECONF_8BPC;
6503                 break;
6504         case 30:
6505                 val |= PIPECONF_10BPC;
6506                 break;
6507         case 36:
6508                 val |= PIPECONF_12BPC;
6509                 break;
6510         default:
6511                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6512                 BUG();
6513         }
6514
6515         if (intel_crtc->config.dither)
6516                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6517
6518         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6519                 val |= PIPECONF_INTERLACED_ILK;
6520         else
6521                 val |= PIPECONF_PROGRESSIVE;
6522
6523         if (intel_crtc->config.limited_color_range)
6524                 val |= PIPECONF_COLOR_RANGE_SELECT;
6525
6526         I915_WRITE(PIPECONF(pipe), val);
6527         POSTING_READ(PIPECONF(pipe));
6528 }
6529
6530 /*
6531  * Set up the pipe CSC unit.
6532  *
6533  * Currently only full range RGB to limited range RGB conversion
6534  * is supported, but eventually this should handle various
6535  * RGB<->YCbCr scenarios as well.
6536  */
6537 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6538 {
6539         struct drm_device *dev = crtc->dev;
6540         struct drm_i915_private *dev_priv = dev->dev_private;
6541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6542         int pipe = intel_crtc->pipe;
6543         uint16_t coeff = 0x7800; /* 1.0 */
6544
6545         /*
6546          * TODO: Check what kind of values actually come out of the pipe
6547          * with these coeff/postoff values and adjust to get the best
6548          * accuracy. Perhaps we even need to take the bpc value into
6549          * consideration.
6550          */
6551
6552         if (intel_crtc->config.limited_color_range)
6553                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6554
6555         /*
6556          * GY/GU and RY/RU should be the other way around according
6557          * to BSpec, but reality doesn't agree. Just set them up in
6558          * a way that results in the correct picture.
6559          */
6560         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6561         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6562
6563         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6564         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6565
6566         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6567         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6568
6569         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6570         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6571         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6572
6573         if (INTEL_INFO(dev)->gen > 6) {
6574                 uint16_t postoff = 0;
6575
6576                 if (intel_crtc->config.limited_color_range)
6577                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6578
6579                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6580                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6581                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6582
6583                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6584         } else {
6585                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6586
6587                 if (intel_crtc->config.limited_color_range)
6588                         mode |= CSC_BLACK_SCREEN_OFFSET;
6589
6590                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6591         }
6592 }
6593
6594 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6595 {
6596         struct drm_device *dev = crtc->dev;
6597         struct drm_i915_private *dev_priv = dev->dev_private;
6598         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6599         enum pipe pipe = intel_crtc->pipe;
6600         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6601         uint32_t val;
6602
6603         val = 0;
6604
6605         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6606                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6607
6608         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6609                 val |= PIPECONF_INTERLACED_ILK;
6610         else
6611                 val |= PIPECONF_PROGRESSIVE;
6612
6613         I915_WRITE(PIPECONF(cpu_transcoder), val);
6614         POSTING_READ(PIPECONF(cpu_transcoder));
6615
6616         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6617         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6618
6619         if (IS_BROADWELL(dev)) {
6620                 val = 0;
6621
6622                 switch (intel_crtc->config.pipe_bpp) {
6623                 case 18:
6624                         val |= PIPEMISC_DITHER_6_BPC;
6625                         break;
6626                 case 24:
6627                         val |= PIPEMISC_DITHER_8_BPC;
6628                         break;
6629                 case 30:
6630                         val |= PIPEMISC_DITHER_10_BPC;
6631                         break;
6632                 case 36:
6633                         val |= PIPEMISC_DITHER_12_BPC;
6634                         break;
6635                 default:
6636                         /* Case prevented by pipe_config_set_bpp. */
6637                         BUG();
6638                 }
6639
6640                 if (intel_crtc->config.dither)
6641                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6642
6643                 I915_WRITE(PIPEMISC(pipe), val);
6644         }
6645 }
6646
6647 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6648                                     intel_clock_t *clock,
6649                                     bool *has_reduced_clock,
6650                                     intel_clock_t *reduced_clock)
6651 {
6652         struct drm_device *dev = crtc->dev;
6653         struct drm_i915_private *dev_priv = dev->dev_private;
6654         struct intel_encoder *intel_encoder;
6655         int refclk;
6656         const intel_limit_t *limit;
6657         bool ret, is_lvds = false;
6658
6659         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6660                 switch (intel_encoder->type) {
6661                 case INTEL_OUTPUT_LVDS:
6662                         is_lvds = true;
6663                         break;
6664                 }
6665         }
6666
6667         refclk = ironlake_get_refclk(crtc);
6668
6669         /*
6670          * Returns a set of divisors for the desired target clock with the given
6671          * refclk, or FALSE.  The returned values represent the clock equation:
6672          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6673          */
6674         limit = intel_limit(crtc, refclk);
6675         ret = dev_priv->display.find_dpll(limit, crtc,
6676                                           to_intel_crtc(crtc)->config.port_clock,
6677                                           refclk, NULL, clock);
6678         if (!ret)
6679                 return false;
6680
6681         if (is_lvds && dev_priv->lvds_downclock_avail) {
6682                 /*
6683                  * Ensure we match the reduced clock's P to the target clock.
6684                  * If the clocks don't match, we can't switch the display clock
6685                  * by using the FP0/FP1. In such case we will disable the LVDS
6686                  * downclock feature.
6687                 */
6688                 *has_reduced_clock =
6689                         dev_priv->display.find_dpll(limit, crtc,
6690                                                     dev_priv->lvds_downclock,
6691                                                     refclk, clock,
6692                                                     reduced_clock);
6693         }
6694
6695         return true;
6696 }
6697
6698 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6699 {
6700         /*
6701          * Account for spread spectrum to avoid
6702          * oversubscribing the link. Max center spread
6703          * is 2.5%; use 5% for safety's sake.
6704          */
6705         u32 bps = target_clock * bpp * 21 / 20;
6706         return DIV_ROUND_UP(bps, link_bw * 8);
6707 }
6708
6709 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6710 {
6711         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6712 }
6713
6714 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6715                                       u32 *fp,
6716                                       intel_clock_t *reduced_clock, u32 *fp2)
6717 {
6718         struct drm_crtc *crtc = &intel_crtc->base;
6719         struct drm_device *dev = crtc->dev;
6720         struct drm_i915_private *dev_priv = dev->dev_private;
6721         struct intel_encoder *intel_encoder;
6722         uint32_t dpll;
6723         int factor, num_connectors = 0;
6724         bool is_lvds = false, is_sdvo = false;
6725
6726         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6727                 switch (intel_encoder->type) {
6728                 case INTEL_OUTPUT_LVDS:
6729                         is_lvds = true;
6730                         break;
6731                 case INTEL_OUTPUT_SDVO:
6732                 case INTEL_OUTPUT_HDMI:
6733                         is_sdvo = true;
6734                         break;
6735                 }
6736
6737                 num_connectors++;
6738         }
6739
6740         /* Enable autotuning of the PLL clock (if permissible) */
6741         factor = 21;
6742         if (is_lvds) {
6743                 if ((intel_panel_use_ssc(dev_priv) &&
6744                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6745                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6746                         factor = 25;
6747         } else if (intel_crtc->config.sdvo_tv_clock)
6748                 factor = 20;
6749
6750         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6751                 *fp |= FP_CB_TUNE;
6752
6753         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6754                 *fp2 |= FP_CB_TUNE;
6755
6756         dpll = 0;
6757
6758         if (is_lvds)
6759                 dpll |= DPLLB_MODE_LVDS;
6760         else
6761                 dpll |= DPLLB_MODE_DAC_SERIAL;
6762
6763         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6764                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6765
6766         if (is_sdvo)
6767                 dpll |= DPLL_SDVO_HIGH_SPEED;
6768         if (intel_crtc->config.has_dp_encoder)
6769                 dpll |= DPLL_SDVO_HIGH_SPEED;
6770
6771         /* compute bitmask from p1 value */
6772         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6773         /* also FPA1 */
6774         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6775
6776         switch (intel_crtc->config.dpll.p2) {
6777         case 5:
6778                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6779                 break;
6780         case 7:
6781                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6782                 break;
6783         case 10:
6784                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6785                 break;
6786         case 14:
6787                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6788                 break;
6789         }
6790
6791         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6792                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6793         else
6794                 dpll |= PLL_REF_INPUT_DREFCLK;
6795
6796         return dpll | DPLL_VCO_ENABLE;
6797 }
6798
6799 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6800                                   int x, int y,
6801                                   struct drm_framebuffer *fb)
6802 {
6803         struct drm_device *dev = crtc->dev;
6804         struct drm_i915_private *dev_priv = dev->dev_private;
6805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6806         int pipe = intel_crtc->pipe;
6807         int plane = intel_crtc->plane;
6808         int num_connectors = 0;
6809         intel_clock_t clock, reduced_clock;
6810         u32 dpll = 0, fp = 0, fp2 = 0;
6811         bool ok, has_reduced_clock = false;
6812         bool is_lvds = false;
6813         struct intel_encoder *encoder;
6814         struct intel_shared_dpll *pll;
6815         int ret;
6816
6817         for_each_encoder_on_crtc(dev, crtc, encoder) {
6818                 switch (encoder->type) {
6819                 case INTEL_OUTPUT_LVDS:
6820                         is_lvds = true;
6821                         break;
6822                 }
6823
6824                 num_connectors++;
6825         }
6826
6827         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6828              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6829
6830         ok = ironlake_compute_clocks(crtc, &clock,
6831                                      &has_reduced_clock, &reduced_clock);
6832         if (!ok && !intel_crtc->config.clock_set) {
6833                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6834                 return -EINVAL;
6835         }
6836         /* Compat-code for transition, will disappear. */
6837         if (!intel_crtc->config.clock_set) {
6838                 intel_crtc->config.dpll.n = clock.n;
6839                 intel_crtc->config.dpll.m1 = clock.m1;
6840                 intel_crtc->config.dpll.m2 = clock.m2;
6841                 intel_crtc->config.dpll.p1 = clock.p1;
6842                 intel_crtc->config.dpll.p2 = clock.p2;
6843         }
6844
6845         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6846         if (intel_crtc->config.has_pch_encoder) {
6847                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6848                 if (has_reduced_clock)
6849                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6850
6851                 dpll = ironlake_compute_dpll(intel_crtc,
6852                                              &fp, &reduced_clock,
6853                                              has_reduced_clock ? &fp2 : NULL);
6854
6855                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6856                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6857                 if (has_reduced_clock)
6858                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6859                 else
6860                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6861
6862                 pll = intel_get_shared_dpll(intel_crtc);
6863                 if (pll == NULL) {
6864                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6865                                          pipe_name(pipe));
6866                         return -EINVAL;
6867                 }
6868         } else
6869                 intel_put_shared_dpll(intel_crtc);
6870
6871         if (intel_crtc->config.has_dp_encoder)
6872                 intel_dp_set_m_n(intel_crtc);
6873
6874         if (is_lvds && has_reduced_clock && i915.powersave)
6875                 intel_crtc->lowfreq_avail = true;
6876         else
6877                 intel_crtc->lowfreq_avail = false;
6878
6879         intel_set_pipe_timings(intel_crtc);
6880
6881         if (intel_crtc->config.has_pch_encoder) {
6882                 intel_cpu_transcoder_set_m_n(intel_crtc,
6883                                              &intel_crtc->config.fdi_m_n);
6884         }
6885
6886         ironlake_set_pipeconf(crtc);
6887
6888         /* Set up the display plane register */
6889         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6890         POSTING_READ(DSPCNTR(plane));
6891
6892         ret = intel_pipe_set_base(crtc, x, y, fb);
6893
6894         return ret;
6895 }
6896
6897 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6898                                          struct intel_link_m_n *m_n)
6899 {
6900         struct drm_device *dev = crtc->base.dev;
6901         struct drm_i915_private *dev_priv = dev->dev_private;
6902         enum pipe pipe = crtc->pipe;
6903
6904         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6905         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6906         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6907                 & ~TU_SIZE_MASK;
6908         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6909         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6910                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6911 }
6912
6913 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6914                                          enum transcoder transcoder,
6915                                          struct intel_link_m_n *m_n)
6916 {
6917         struct drm_device *dev = crtc->base.dev;
6918         struct drm_i915_private *dev_priv = dev->dev_private;
6919         enum pipe pipe = crtc->pipe;
6920
6921         if (INTEL_INFO(dev)->gen >= 5) {
6922                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6923                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6924                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6925                         & ~TU_SIZE_MASK;
6926                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6927                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6928                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6929         } else {
6930                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6931                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6932                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6933                         & ~TU_SIZE_MASK;
6934                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6935                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6936                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6937         }
6938 }
6939
6940 void intel_dp_get_m_n(struct intel_crtc *crtc,
6941                       struct intel_crtc_config *pipe_config)
6942 {
6943         if (crtc->config.has_pch_encoder)
6944                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6945         else
6946                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6947                                              &pipe_config->dp_m_n);
6948 }
6949
6950 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6951                                         struct intel_crtc_config *pipe_config)
6952 {
6953         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6954                                      &pipe_config->fdi_m_n);
6955 }
6956
6957 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6958                                      struct intel_crtc_config *pipe_config)
6959 {
6960         struct drm_device *dev = crtc->base.dev;
6961         struct drm_i915_private *dev_priv = dev->dev_private;
6962         uint32_t tmp;
6963
6964         tmp = I915_READ(PF_CTL(crtc->pipe));
6965
6966         if (tmp & PF_ENABLE) {
6967                 pipe_config->pch_pfit.enabled = true;
6968                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6969                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6970
6971                 /* We currently do not free assignements of panel fitters on
6972                  * ivb/hsw (since we don't use the higher upscaling modes which
6973                  * differentiates them) so just WARN about this case for now. */
6974                 if (IS_GEN7(dev)) {
6975                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6976                                 PF_PIPE_SEL_IVB(crtc->pipe));
6977                 }
6978         }
6979 }
6980
6981 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6982                                       struct intel_plane_config *plane_config)
6983 {
6984         struct drm_device *dev = crtc->base.dev;
6985         struct drm_i915_private *dev_priv = dev->dev_private;
6986         u32 val, base, offset;
6987         int pipe = crtc->pipe, plane = crtc->plane;
6988         int fourcc, pixel_format;
6989         int aligned_height;
6990
6991         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6992         if (!crtc->base.primary->fb) {
6993                 DRM_DEBUG_KMS("failed to alloc fb\n");
6994                 return;
6995         }
6996
6997         val = I915_READ(DSPCNTR(plane));
6998
6999         if (INTEL_INFO(dev)->gen >= 4)
7000                 if (val & DISPPLANE_TILED)
7001                         plane_config->tiled = true;
7002
7003         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7004         fourcc = intel_format_to_fourcc(pixel_format);
7005         crtc->base.primary->fb->pixel_format = fourcc;
7006         crtc->base.primary->fb->bits_per_pixel =
7007                 drm_format_plane_cpp(fourcc, 0) * 8;
7008
7009         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7010         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7011                 offset = I915_READ(DSPOFFSET(plane));
7012         } else {
7013                 if (plane_config->tiled)
7014                         offset = I915_READ(DSPTILEOFF(plane));
7015                 else
7016                         offset = I915_READ(DSPLINOFF(plane));
7017         }
7018         plane_config->base = base;
7019
7020         val = I915_READ(PIPESRC(pipe));
7021         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7022         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7023
7024         val = I915_READ(DSPSTRIDE(pipe));
7025         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7026
7027         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7028                                             plane_config->tiled);
7029
7030         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7031                                    aligned_height, PAGE_SIZE);
7032
7033         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7034                       pipe, plane, crtc->base.primary->fb->width,
7035                       crtc->base.primary->fb->height,
7036                       crtc->base.primary->fb->bits_per_pixel, base,
7037                       crtc->base.primary->fb->pitches[0],
7038                       plane_config->size);
7039 }
7040
7041 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7042                                      struct intel_crtc_config *pipe_config)
7043 {
7044         struct drm_device *dev = crtc->base.dev;
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046         uint32_t tmp;
7047
7048         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7049         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7050
7051         tmp = I915_READ(PIPECONF(crtc->pipe));
7052         if (!(tmp & PIPECONF_ENABLE))
7053                 return false;
7054
7055         switch (tmp & PIPECONF_BPC_MASK) {
7056         case PIPECONF_6BPC:
7057                 pipe_config->pipe_bpp = 18;
7058                 break;
7059         case PIPECONF_8BPC:
7060                 pipe_config->pipe_bpp = 24;
7061                 break;
7062         case PIPECONF_10BPC:
7063                 pipe_config->pipe_bpp = 30;
7064                 break;
7065         case PIPECONF_12BPC:
7066                 pipe_config->pipe_bpp = 36;
7067                 break;
7068         default:
7069                 break;
7070         }
7071
7072         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7073                 pipe_config->limited_color_range = true;
7074
7075         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7076                 struct intel_shared_dpll *pll;
7077
7078                 pipe_config->has_pch_encoder = true;
7079
7080                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7081                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7082                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7083
7084                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7085
7086                 if (HAS_PCH_IBX(dev_priv->dev)) {
7087                         pipe_config->shared_dpll =
7088                                 (enum intel_dpll_id) crtc->pipe;
7089                 } else {
7090                         tmp = I915_READ(PCH_DPLL_SEL);
7091                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7092                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7093                         else
7094                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7095                 }
7096
7097                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7098
7099                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7100                                            &pipe_config->dpll_hw_state));
7101
7102                 tmp = pipe_config->dpll_hw_state.dpll;
7103                 pipe_config->pixel_multiplier =
7104                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7105                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7106
7107                 ironlake_pch_clock_get(crtc, pipe_config);
7108         } else {
7109                 pipe_config->pixel_multiplier = 1;
7110         }
7111
7112         intel_get_pipe_timings(crtc, pipe_config);
7113
7114         ironlake_get_pfit_config(crtc, pipe_config);
7115
7116         return true;
7117 }
7118
7119 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7120 {
7121         struct drm_device *dev = dev_priv->dev;
7122         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7123         struct intel_crtc *crtc;
7124
7125         for_each_intel_crtc(dev, crtc)
7126                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7127                      pipe_name(crtc->pipe));
7128
7129         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7130         WARN(plls->spll_refcount, "SPLL enabled\n");
7131         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7132         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7133         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7134         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7135              "CPU PWM1 enabled\n");
7136         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7137              "CPU PWM2 enabled\n");
7138         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7139              "PCH PWM1 enabled\n");
7140         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7141              "Utility pin enabled\n");
7142         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7143
7144         /*
7145          * In theory we can still leave IRQs enabled, as long as only the HPD
7146          * interrupts remain enabled. We used to check for that, but since it's
7147          * gen-specific and since we only disable LCPLL after we fully disable
7148          * the interrupts, the check below should be enough.
7149          */
7150         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7151 }
7152
7153 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7154 {
7155         struct drm_device *dev = dev_priv->dev;
7156
7157         if (IS_HASWELL(dev)) {
7158                 mutex_lock(&dev_priv->rps.hw_lock);
7159                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7160                                             val))
7161                         DRM_ERROR("Failed to disable D_COMP\n");
7162                 mutex_unlock(&dev_priv->rps.hw_lock);
7163         } else {
7164                 I915_WRITE(D_COMP, val);
7165         }
7166         POSTING_READ(D_COMP);
7167 }
7168
7169 /*
7170  * This function implements pieces of two sequences from BSpec:
7171  * - Sequence for display software to disable LCPLL
7172  * - Sequence for display software to allow package C8+
7173  * The steps implemented here are just the steps that actually touch the LCPLL
7174  * register. Callers should take care of disabling all the display engine
7175  * functions, doing the mode unset, fixing interrupts, etc.
7176  */
7177 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7178                               bool switch_to_fclk, bool allow_power_down)
7179 {
7180         uint32_t val;
7181
7182         assert_can_disable_lcpll(dev_priv);
7183
7184         val = I915_READ(LCPLL_CTL);
7185
7186         if (switch_to_fclk) {
7187                 val |= LCPLL_CD_SOURCE_FCLK;
7188                 I915_WRITE(LCPLL_CTL, val);
7189
7190                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7191                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7192                         DRM_ERROR("Switching to FCLK failed\n");
7193
7194                 val = I915_READ(LCPLL_CTL);
7195         }
7196
7197         val |= LCPLL_PLL_DISABLE;
7198         I915_WRITE(LCPLL_CTL, val);
7199         POSTING_READ(LCPLL_CTL);
7200
7201         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7202                 DRM_ERROR("LCPLL still locked\n");
7203
7204         val = I915_READ(D_COMP);
7205         val |= D_COMP_COMP_DISABLE;
7206         hsw_write_dcomp(dev_priv, val);
7207         ndelay(100);
7208
7209         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7210                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7211
7212         if (allow_power_down) {
7213                 val = I915_READ(LCPLL_CTL);
7214                 val |= LCPLL_POWER_DOWN_ALLOW;
7215                 I915_WRITE(LCPLL_CTL, val);
7216                 POSTING_READ(LCPLL_CTL);
7217         }
7218 }
7219
7220 /*
7221  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7222  * source.
7223  */
7224 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7225 {
7226         uint32_t val;
7227         unsigned long irqflags;
7228
7229         val = I915_READ(LCPLL_CTL);
7230
7231         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7232                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7233                 return;
7234
7235         /*
7236          * Make sure we're not on PC8 state before disabling PC8, otherwise
7237          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7238          *
7239          * The other problem is that hsw_restore_lcpll() is called as part of
7240          * the runtime PM resume sequence, so we can't just call
7241          * gen6_gt_force_wake_get() because that function calls
7242          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7243          * while we are on the resume sequence. So to solve this problem we have
7244          * to call special forcewake code that doesn't touch runtime PM and
7245          * doesn't enable the forcewake delayed work.
7246          */
7247         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7248         if (dev_priv->uncore.forcewake_count++ == 0)
7249                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7250         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7251
7252         if (val & LCPLL_POWER_DOWN_ALLOW) {
7253                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7254                 I915_WRITE(LCPLL_CTL, val);
7255                 POSTING_READ(LCPLL_CTL);
7256         }
7257
7258         val = I915_READ(D_COMP);
7259         val |= D_COMP_COMP_FORCE;
7260         val &= ~D_COMP_COMP_DISABLE;
7261         hsw_write_dcomp(dev_priv, val);
7262
7263         val = I915_READ(LCPLL_CTL);
7264         val &= ~LCPLL_PLL_DISABLE;
7265         I915_WRITE(LCPLL_CTL, val);
7266
7267         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7268                 DRM_ERROR("LCPLL not locked yet\n");
7269
7270         if (val & LCPLL_CD_SOURCE_FCLK) {
7271                 val = I915_READ(LCPLL_CTL);
7272                 val &= ~LCPLL_CD_SOURCE_FCLK;
7273                 I915_WRITE(LCPLL_CTL, val);
7274
7275                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7276                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7277                         DRM_ERROR("Switching back to LCPLL failed\n");
7278         }
7279
7280         /* See the big comment above. */
7281         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7282         if (--dev_priv->uncore.forcewake_count == 0)
7283                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7284         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7285 }
7286
7287 /*
7288  * Package states C8 and deeper are really deep PC states that can only be
7289  * reached when all the devices on the system allow it, so even if the graphics
7290  * device allows PC8+, it doesn't mean the system will actually get to these
7291  * states. Our driver only allows PC8+ when going into runtime PM.
7292  *
7293  * The requirements for PC8+ are that all the outputs are disabled, the power
7294  * well is disabled and most interrupts are disabled, and these are also
7295  * requirements for runtime PM. When these conditions are met, we manually do
7296  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7297  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7298  * hang the machine.
7299  *
7300  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7301  * the state of some registers, so when we come back from PC8+ we need to
7302  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7303  * need to take care of the registers kept by RC6. Notice that this happens even
7304  * if we don't put the device in PCI D3 state (which is what currently happens
7305  * because of the runtime PM support).
7306  *
7307  * For more, read "Display Sequences for Package C8" on the hardware
7308  * documentation.
7309  */
7310 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7311 {
7312         struct drm_device *dev = dev_priv->dev;
7313         uint32_t val;
7314
7315         DRM_DEBUG_KMS("Enabling package C8+\n");
7316
7317         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7318                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7319                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7320                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7321         }
7322
7323         lpt_disable_clkout_dp(dev);
7324         hsw_disable_lcpll(dev_priv, true, true);
7325 }
7326
7327 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7328 {
7329         struct drm_device *dev = dev_priv->dev;
7330         uint32_t val;
7331
7332         DRM_DEBUG_KMS("Disabling package C8+\n");
7333
7334         hsw_restore_lcpll(dev_priv);
7335         lpt_init_pch_refclk(dev);
7336
7337         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7338                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7339                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7340                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7341         }
7342
7343         intel_prepare_ddi(dev);
7344 }
7345
7346 static void snb_modeset_global_resources(struct drm_device *dev)
7347 {
7348         modeset_update_crtc_power_domains(dev);
7349 }
7350
7351 static void haswell_modeset_global_resources(struct drm_device *dev)
7352 {
7353         modeset_update_crtc_power_domains(dev);
7354 }
7355
7356 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7357                                  int x, int y,
7358                                  struct drm_framebuffer *fb)
7359 {
7360         struct drm_device *dev = crtc->dev;
7361         struct drm_i915_private *dev_priv = dev->dev_private;
7362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7363         int plane = intel_crtc->plane;
7364         int ret;
7365
7366         if (!intel_ddi_pll_select(intel_crtc))
7367                 return -EINVAL;
7368         intel_ddi_pll_enable(intel_crtc);
7369
7370         if (intel_crtc->config.has_dp_encoder)
7371                 intel_dp_set_m_n(intel_crtc);
7372
7373         intel_crtc->lowfreq_avail = false;
7374
7375         intel_set_pipe_timings(intel_crtc);
7376
7377         if (intel_crtc->config.has_pch_encoder) {
7378                 intel_cpu_transcoder_set_m_n(intel_crtc,
7379                                              &intel_crtc->config.fdi_m_n);
7380         }
7381
7382         haswell_set_pipeconf(crtc);
7383
7384         intel_set_pipe_csc(crtc);
7385
7386         /* Set up the display plane register */
7387         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7388         POSTING_READ(DSPCNTR(plane));
7389
7390         ret = intel_pipe_set_base(crtc, x, y, fb);
7391
7392         return ret;
7393 }
7394
7395 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7396                                     struct intel_crtc_config *pipe_config)
7397 {
7398         struct drm_device *dev = crtc->base.dev;
7399         struct drm_i915_private *dev_priv = dev->dev_private;
7400         enum intel_display_power_domain pfit_domain;
7401         uint32_t tmp;
7402
7403         if (!intel_display_power_enabled(dev_priv,
7404                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7405                 return false;
7406
7407         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7408         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7409
7410         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7411         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7412                 enum pipe trans_edp_pipe;
7413                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7414                 default:
7415                         WARN(1, "unknown pipe linked to edp transcoder\n");
7416                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7417                 case TRANS_DDI_EDP_INPUT_A_ON:
7418                         trans_edp_pipe = PIPE_A;
7419                         break;
7420                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7421                         trans_edp_pipe = PIPE_B;
7422                         break;
7423                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7424                         trans_edp_pipe = PIPE_C;
7425                         break;
7426                 }
7427
7428                 if (trans_edp_pipe == crtc->pipe)
7429                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7430         }
7431
7432         if (!intel_display_power_enabled(dev_priv,
7433                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7434                 return false;
7435
7436         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7437         if (!(tmp & PIPECONF_ENABLE))
7438                 return false;
7439
7440         /*
7441          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7442          * DDI E. So just check whether this pipe is wired to DDI E and whether
7443          * the PCH transcoder is on.
7444          */
7445         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7446         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7447             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7448                 pipe_config->has_pch_encoder = true;
7449
7450                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7451                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7452                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7453
7454                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7455         }
7456
7457         intel_get_pipe_timings(crtc, pipe_config);
7458
7459         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7460         if (intel_display_power_enabled(dev_priv, pfit_domain))
7461                 ironlake_get_pfit_config(crtc, pipe_config);
7462
7463         if (IS_HASWELL(dev))
7464                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7465                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7466
7467         pipe_config->pixel_multiplier = 1;
7468
7469         return true;
7470 }
7471
7472 static struct {
7473         int clock;
7474         u32 config;
7475 } hdmi_audio_clock[] = {
7476         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7477         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7478         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7479         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7480         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7481         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7482         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7483         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7484         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7485         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7486 };
7487
7488 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7489 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7490 {
7491         int i;
7492
7493         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7494                 if (mode->clock == hdmi_audio_clock[i].clock)
7495                         break;
7496         }
7497
7498         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7499                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7500                 i = 1;
7501         }
7502
7503         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7504                       hdmi_audio_clock[i].clock,
7505                       hdmi_audio_clock[i].config);
7506
7507         return hdmi_audio_clock[i].config;
7508 }
7509
7510 static bool intel_eld_uptodate(struct drm_connector *connector,
7511                                int reg_eldv, uint32_t bits_eldv,
7512                                int reg_elda, uint32_t bits_elda,
7513                                int reg_edid)
7514 {
7515         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7516         uint8_t *eld = connector->eld;
7517         uint32_t i;
7518
7519         i = I915_READ(reg_eldv);
7520         i &= bits_eldv;
7521
7522         if (!eld[0])
7523                 return !i;
7524
7525         if (!i)
7526                 return false;
7527
7528         i = I915_READ(reg_elda);
7529         i &= ~bits_elda;
7530         I915_WRITE(reg_elda, i);
7531
7532         for (i = 0; i < eld[2]; i++)
7533                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7534                         return false;
7535
7536         return true;
7537 }
7538
7539 static void g4x_write_eld(struct drm_connector *connector,
7540                           struct drm_crtc *crtc,
7541                           struct drm_display_mode *mode)
7542 {
7543         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7544         uint8_t *eld = connector->eld;
7545         uint32_t eldv;
7546         uint32_t len;
7547         uint32_t i;
7548
7549         i = I915_READ(G4X_AUD_VID_DID);
7550
7551         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7552                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7553         else
7554                 eldv = G4X_ELDV_DEVCTG;
7555
7556         if (intel_eld_uptodate(connector,
7557                                G4X_AUD_CNTL_ST, eldv,
7558                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7559                                G4X_HDMIW_HDMIEDID))
7560                 return;
7561
7562         i = I915_READ(G4X_AUD_CNTL_ST);
7563         i &= ~(eldv | G4X_ELD_ADDR);
7564         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7565         I915_WRITE(G4X_AUD_CNTL_ST, i);
7566
7567         if (!eld[0])
7568                 return;
7569
7570         len = min_t(uint8_t, eld[2], len);
7571         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7572         for (i = 0; i < len; i++)
7573                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7574
7575         i = I915_READ(G4X_AUD_CNTL_ST);
7576         i |= eldv;
7577         I915_WRITE(G4X_AUD_CNTL_ST, i);
7578 }
7579
7580 static void haswell_write_eld(struct drm_connector *connector,
7581                               struct drm_crtc *crtc,
7582                               struct drm_display_mode *mode)
7583 {
7584         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7585         uint8_t *eld = connector->eld;
7586         uint32_t eldv;
7587         uint32_t i;
7588         int len;
7589         int pipe = to_intel_crtc(crtc)->pipe;
7590         int tmp;
7591
7592         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7593         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7594         int aud_config = HSW_AUD_CFG(pipe);
7595         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7596
7597         /* Audio output enable */
7598         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7599         tmp = I915_READ(aud_cntrl_st2);
7600         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7601         I915_WRITE(aud_cntrl_st2, tmp);
7602         POSTING_READ(aud_cntrl_st2);
7603
7604         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7605
7606         /* Set ELD valid state */
7607         tmp = I915_READ(aud_cntrl_st2);
7608         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7609         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7610         I915_WRITE(aud_cntrl_st2, tmp);
7611         tmp = I915_READ(aud_cntrl_st2);
7612         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7613
7614         /* Enable HDMI mode */
7615         tmp = I915_READ(aud_config);
7616         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7617         /* clear N_programing_enable and N_value_index */
7618         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7619         I915_WRITE(aud_config, tmp);
7620
7621         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7622
7623         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7624
7625         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7626                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7627                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7628                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7629         } else {
7630                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7631         }
7632
7633         if (intel_eld_uptodate(connector,
7634                                aud_cntrl_st2, eldv,
7635                                aud_cntl_st, IBX_ELD_ADDRESS,
7636                                hdmiw_hdmiedid))
7637                 return;
7638
7639         i = I915_READ(aud_cntrl_st2);
7640         i &= ~eldv;
7641         I915_WRITE(aud_cntrl_st2, i);
7642
7643         if (!eld[0])
7644                 return;
7645
7646         i = I915_READ(aud_cntl_st);
7647         i &= ~IBX_ELD_ADDRESS;
7648         I915_WRITE(aud_cntl_st, i);
7649         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7650         DRM_DEBUG_DRIVER("port num:%d\n", i);
7651
7652         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7653         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7654         for (i = 0; i < len; i++)
7655                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7656
7657         i = I915_READ(aud_cntrl_st2);
7658         i |= eldv;
7659         I915_WRITE(aud_cntrl_st2, i);
7660
7661 }
7662
7663 static void ironlake_write_eld(struct drm_connector *connector,
7664                                struct drm_crtc *crtc,
7665                                struct drm_display_mode *mode)
7666 {
7667         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7668         uint8_t *eld = connector->eld;
7669         uint32_t eldv;
7670         uint32_t i;
7671         int len;
7672         int hdmiw_hdmiedid;
7673         int aud_config;
7674         int aud_cntl_st;
7675         int aud_cntrl_st2;
7676         int pipe = to_intel_crtc(crtc)->pipe;
7677
7678         if (HAS_PCH_IBX(connector->dev)) {
7679                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7680                 aud_config = IBX_AUD_CFG(pipe);
7681                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7682                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7683         } else if (IS_VALLEYVIEW(connector->dev)) {
7684                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7685                 aud_config = VLV_AUD_CFG(pipe);
7686                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7687                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7688         } else {
7689                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7690                 aud_config = CPT_AUD_CFG(pipe);
7691                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7692                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7693         }
7694
7695         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7696
7697         if (IS_VALLEYVIEW(connector->dev))  {
7698                 struct intel_encoder *intel_encoder;
7699                 struct intel_digital_port *intel_dig_port;
7700
7701                 intel_encoder = intel_attached_encoder(connector);
7702                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7703                 i = intel_dig_port->port;
7704         } else {
7705                 i = I915_READ(aud_cntl_st);
7706                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7707                 /* DIP_Port_Select, 0x1 = PortB */
7708         }
7709
7710         if (!i) {
7711                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7712                 /* operate blindly on all ports */
7713                 eldv = IBX_ELD_VALIDB;
7714                 eldv |= IBX_ELD_VALIDB << 4;
7715                 eldv |= IBX_ELD_VALIDB << 8;
7716         } else {
7717                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7718                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7719         }
7720
7721         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7722                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7723                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7724                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7725         } else {
7726                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7727         }
7728
7729         if (intel_eld_uptodate(connector,
7730                                aud_cntrl_st2, eldv,
7731                                aud_cntl_st, IBX_ELD_ADDRESS,
7732                                hdmiw_hdmiedid))
7733                 return;
7734
7735         i = I915_READ(aud_cntrl_st2);
7736         i &= ~eldv;
7737         I915_WRITE(aud_cntrl_st2, i);
7738
7739         if (!eld[0])
7740                 return;
7741
7742         i = I915_READ(aud_cntl_st);
7743         i &= ~IBX_ELD_ADDRESS;
7744         I915_WRITE(aud_cntl_st, i);
7745
7746         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7747         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7748         for (i = 0; i < len; i++)
7749                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7750
7751         i = I915_READ(aud_cntrl_st2);
7752         i |= eldv;
7753         I915_WRITE(aud_cntrl_st2, i);
7754 }
7755
7756 void intel_write_eld(struct drm_encoder *encoder,
7757                      struct drm_display_mode *mode)
7758 {
7759         struct drm_crtc *crtc = encoder->crtc;
7760         struct drm_connector *connector;
7761         struct drm_device *dev = encoder->dev;
7762         struct drm_i915_private *dev_priv = dev->dev_private;
7763
7764         connector = drm_select_eld(encoder, mode);
7765         if (!connector)
7766                 return;
7767
7768         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7769                          connector->base.id,
7770                          drm_get_connector_name(connector),
7771                          connector->encoder->base.id,
7772                          drm_get_encoder_name(connector->encoder));
7773
7774         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7775
7776         if (dev_priv->display.write_eld)
7777                 dev_priv->display.write_eld(connector, crtc, mode);
7778 }
7779
7780 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7781 {
7782         struct drm_device *dev = crtc->dev;
7783         struct drm_i915_private *dev_priv = dev->dev_private;
7784         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7785         bool visible = base != 0;
7786         u32 cntl;
7787
7788         if (intel_crtc->cursor_visible == visible)
7789                 return;
7790
7791         cntl = I915_READ(_CURACNTR);
7792         if (visible) {
7793                 /* On these chipsets we can only modify the base whilst
7794                  * the cursor is disabled.
7795                  */
7796                 I915_WRITE(_CURABASE, base);
7797
7798                 cntl &= ~(CURSOR_FORMAT_MASK);
7799                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7800                 cntl |= CURSOR_ENABLE |
7801                         CURSOR_GAMMA_ENABLE |
7802                         CURSOR_FORMAT_ARGB;
7803         } else
7804                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7805         I915_WRITE(_CURACNTR, cntl);
7806
7807         intel_crtc->cursor_visible = visible;
7808 }
7809
7810 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7811 {
7812         struct drm_device *dev = crtc->dev;
7813         struct drm_i915_private *dev_priv = dev->dev_private;
7814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7815         int pipe = intel_crtc->pipe;
7816         bool visible = base != 0;
7817
7818         if (intel_crtc->cursor_visible != visible) {
7819                 int16_t width = intel_crtc->cursor_width;
7820                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7821                 if (base) {
7822                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7823                         cntl |= MCURSOR_GAMMA_ENABLE;
7824
7825                         switch (width) {
7826                         case 64:
7827                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7828                                 break;
7829                         case 128:
7830                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7831                                 break;
7832                         case 256:
7833                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7834                                 break;
7835                         default:
7836                                 WARN_ON(1);
7837                                 return;
7838                         }
7839                         cntl |= pipe << 28; /* Connect to correct pipe */
7840                 } else {
7841                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7842                         cntl |= CURSOR_MODE_DISABLE;
7843                 }
7844                 I915_WRITE(CURCNTR(pipe), cntl);
7845
7846                 intel_crtc->cursor_visible = visible;
7847         }
7848         /* and commit changes on next vblank */
7849         POSTING_READ(CURCNTR(pipe));
7850         I915_WRITE(CURBASE(pipe), base);
7851         POSTING_READ(CURBASE(pipe));
7852 }
7853
7854 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7855 {
7856         struct drm_device *dev = crtc->dev;
7857         struct drm_i915_private *dev_priv = dev->dev_private;
7858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7859         int pipe = intel_crtc->pipe;
7860         bool visible = base != 0;
7861
7862         if (intel_crtc->cursor_visible != visible) {
7863                 int16_t width = intel_crtc->cursor_width;
7864                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7865                 if (base) {
7866                         cntl &= ~CURSOR_MODE;
7867                         cntl |= MCURSOR_GAMMA_ENABLE;
7868                         switch (width) {
7869                         case 64:
7870                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7871                                 break;
7872                         case 128:
7873                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7874                                 break;
7875                         case 256:
7876                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7877                                 break;
7878                         default:
7879                                 WARN_ON(1);
7880                                 return;
7881                         }
7882                 } else {
7883                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7884                         cntl |= CURSOR_MODE_DISABLE;
7885                 }
7886                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7887                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7888                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7889                 }
7890                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7891
7892                 intel_crtc->cursor_visible = visible;
7893         }
7894         /* and commit changes on next vblank */
7895         POSTING_READ(CURCNTR_IVB(pipe));
7896         I915_WRITE(CURBASE_IVB(pipe), base);
7897         POSTING_READ(CURBASE_IVB(pipe));
7898 }
7899
7900 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7901 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7902                                      bool on)
7903 {
7904         struct drm_device *dev = crtc->dev;
7905         struct drm_i915_private *dev_priv = dev->dev_private;
7906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7907         int pipe = intel_crtc->pipe;
7908         int x = intel_crtc->cursor_x;
7909         int y = intel_crtc->cursor_y;
7910         u32 base = 0, pos = 0;
7911         bool visible;
7912
7913         if (on)
7914                 base = intel_crtc->cursor_addr;
7915
7916         if (x >= intel_crtc->config.pipe_src_w)
7917                 base = 0;
7918
7919         if (y >= intel_crtc->config.pipe_src_h)
7920                 base = 0;
7921
7922         if (x < 0) {
7923                 if (x + intel_crtc->cursor_width <= 0)
7924                         base = 0;
7925
7926                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7927                 x = -x;
7928         }
7929         pos |= x << CURSOR_X_SHIFT;
7930
7931         if (y < 0) {
7932                 if (y + intel_crtc->cursor_height <= 0)
7933                         base = 0;
7934
7935                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7936                 y = -y;
7937         }
7938         pos |= y << CURSOR_Y_SHIFT;
7939
7940         visible = base != 0;
7941         if (!visible && !intel_crtc->cursor_visible)
7942                 return;
7943
7944         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7945                 I915_WRITE(CURPOS_IVB(pipe), pos);
7946                 ivb_update_cursor(crtc, base);
7947         } else {
7948                 I915_WRITE(CURPOS(pipe), pos);
7949                 if (IS_845G(dev) || IS_I865G(dev))
7950                         i845_update_cursor(crtc, base);
7951                 else
7952                         i9xx_update_cursor(crtc, base);
7953         }
7954 }
7955
7956 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7957                                  struct drm_file *file,
7958                                  uint32_t handle,
7959                                  uint32_t width, uint32_t height)
7960 {
7961         struct drm_device *dev = crtc->dev;
7962         struct drm_i915_private *dev_priv = dev->dev_private;
7963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7964         struct drm_i915_gem_object *obj;
7965         unsigned old_width;
7966         uint32_t addr;
7967         int ret;
7968
7969         /* if we want to turn off the cursor ignore width and height */
7970         if (!handle) {
7971                 DRM_DEBUG_KMS("cursor off\n");
7972                 addr = 0;
7973                 obj = NULL;
7974                 mutex_lock(&dev->struct_mutex);
7975                 goto finish;
7976         }
7977
7978         /* Check for which cursor types we support */
7979         if (!((width == 64 && height == 64) ||
7980                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7981                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7982                 DRM_DEBUG("Cursor dimension not supported\n");
7983                 return -EINVAL;
7984         }
7985
7986         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7987         if (&obj->base == NULL)
7988                 return -ENOENT;
7989
7990         if (obj->base.size < width * height * 4) {
7991                 DRM_DEBUG_KMS("buffer is to small\n");
7992                 ret = -ENOMEM;
7993                 goto fail;
7994         }
7995
7996         /* we only need to pin inside GTT if cursor is non-phy */
7997         mutex_lock(&dev->struct_mutex);
7998         if (!INTEL_INFO(dev)->cursor_needs_physical) {
7999                 unsigned alignment;
8000
8001                 if (obj->tiling_mode) {
8002                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8003                         ret = -EINVAL;
8004                         goto fail_locked;
8005                 }
8006
8007                 /* Note that the w/a also requires 2 PTE of padding following
8008                  * the bo. We currently fill all unused PTE with the shadow
8009                  * page and so we should always have valid PTE following the
8010                  * cursor preventing the VT-d warning.
8011                  */
8012                 alignment = 0;
8013                 if (need_vtd_wa(dev))
8014                         alignment = 64*1024;
8015
8016                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8017                 if (ret) {
8018                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8019                         goto fail_locked;
8020                 }
8021
8022                 ret = i915_gem_object_put_fence(obj);
8023                 if (ret) {
8024                         DRM_DEBUG_KMS("failed to release fence for cursor");
8025                         goto fail_unpin;
8026                 }
8027
8028                 addr = i915_gem_obj_ggtt_offset(obj);
8029         } else {
8030                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8031                 ret = i915_gem_attach_phys_object(dev, obj,
8032                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8033                                                   align);
8034                 if (ret) {
8035                         DRM_DEBUG_KMS("failed to attach phys object\n");
8036                         goto fail_locked;
8037                 }
8038                 addr = obj->phys_obj->handle->busaddr;
8039         }
8040
8041         if (IS_GEN2(dev))
8042                 I915_WRITE(CURSIZE, (height << 12) | width);
8043
8044  finish:
8045         if (intel_crtc->cursor_bo) {
8046                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8047                         if (intel_crtc->cursor_bo != obj)
8048                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8049                 } else
8050                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8051                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8052         }
8053
8054         mutex_unlock(&dev->struct_mutex);
8055
8056         old_width = intel_crtc->cursor_width;
8057
8058         intel_crtc->cursor_addr = addr;
8059         intel_crtc->cursor_bo = obj;
8060         intel_crtc->cursor_width = width;
8061         intel_crtc->cursor_height = height;
8062
8063         if (intel_crtc->active) {
8064                 if (old_width != width)
8065                         intel_update_watermarks(crtc);
8066                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8067         }
8068
8069         return 0;
8070 fail_unpin:
8071         i915_gem_object_unpin_from_display_plane(obj);
8072 fail_locked:
8073         mutex_unlock(&dev->struct_mutex);
8074 fail:
8075         drm_gem_object_unreference_unlocked(&obj->base);
8076         return ret;
8077 }
8078
8079 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8080 {
8081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8082
8083         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8084         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8085
8086         if (intel_crtc->active)
8087                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8088
8089         return 0;
8090 }
8091
8092 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8093                                  u16 *blue, uint32_t start, uint32_t size)
8094 {
8095         int end = (start + size > 256) ? 256 : start + size, i;
8096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8097
8098         for (i = start; i < end; i++) {
8099                 intel_crtc->lut_r[i] = red[i] >> 8;
8100                 intel_crtc->lut_g[i] = green[i] >> 8;
8101                 intel_crtc->lut_b[i] = blue[i] >> 8;
8102         }
8103
8104         intel_crtc_load_lut(crtc);
8105 }
8106
8107 /* VESA 640x480x72Hz mode to set on the pipe */
8108 static struct drm_display_mode load_detect_mode = {
8109         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8110                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8111 };
8112
8113 struct drm_framebuffer *
8114 __intel_framebuffer_create(struct drm_device *dev,
8115                            struct drm_mode_fb_cmd2 *mode_cmd,
8116                            struct drm_i915_gem_object *obj)
8117 {
8118         struct intel_framebuffer *intel_fb;
8119         int ret;
8120
8121         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8122         if (!intel_fb) {
8123                 drm_gem_object_unreference_unlocked(&obj->base);
8124                 return ERR_PTR(-ENOMEM);
8125         }
8126
8127         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8128         if (ret)
8129                 goto err;
8130
8131         return &intel_fb->base;
8132 err:
8133         drm_gem_object_unreference_unlocked(&obj->base);
8134         kfree(intel_fb);
8135
8136         return ERR_PTR(ret);
8137 }
8138
8139 static struct drm_framebuffer *
8140 intel_framebuffer_create(struct drm_device *dev,
8141                          struct drm_mode_fb_cmd2 *mode_cmd,
8142                          struct drm_i915_gem_object *obj)
8143 {
8144         struct drm_framebuffer *fb;
8145         int ret;
8146
8147         ret = i915_mutex_lock_interruptible(dev);
8148         if (ret)
8149                 return ERR_PTR(ret);
8150         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8151         mutex_unlock(&dev->struct_mutex);
8152
8153         return fb;
8154 }
8155
8156 static u32
8157 intel_framebuffer_pitch_for_width(int width, int bpp)
8158 {
8159         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8160         return ALIGN(pitch, 64);
8161 }
8162
8163 static u32
8164 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8165 {
8166         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8167         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8168 }
8169
8170 static struct drm_framebuffer *
8171 intel_framebuffer_create_for_mode(struct drm_device *dev,
8172                                   struct drm_display_mode *mode,
8173                                   int depth, int bpp)
8174 {
8175         struct drm_i915_gem_object *obj;
8176         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8177
8178         obj = i915_gem_alloc_object(dev,
8179                                     intel_framebuffer_size_for_mode(mode, bpp));
8180         if (obj == NULL)
8181                 return ERR_PTR(-ENOMEM);
8182
8183         mode_cmd.width = mode->hdisplay;
8184         mode_cmd.height = mode->vdisplay;
8185         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8186                                                                 bpp);
8187         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8188
8189         return intel_framebuffer_create(dev, &mode_cmd, obj);
8190 }
8191
8192 static struct drm_framebuffer *
8193 mode_fits_in_fbdev(struct drm_device *dev,
8194                    struct drm_display_mode *mode)
8195 {
8196 #ifdef CONFIG_DRM_I915_FBDEV
8197         struct drm_i915_private *dev_priv = dev->dev_private;
8198         struct drm_i915_gem_object *obj;
8199         struct drm_framebuffer *fb;
8200
8201         if (!dev_priv->fbdev)
8202                 return NULL;
8203
8204         if (!dev_priv->fbdev->fb)
8205                 return NULL;
8206
8207         obj = dev_priv->fbdev->fb->obj;
8208         BUG_ON(!obj);
8209
8210         fb = &dev_priv->fbdev->fb->base;
8211         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8212                                                                fb->bits_per_pixel))
8213                 return NULL;
8214
8215         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8216                 return NULL;
8217
8218         return fb;
8219 #else
8220         return NULL;
8221 #endif
8222 }
8223
8224 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8225                                 struct drm_display_mode *mode,
8226                                 struct intel_load_detect_pipe *old)
8227 {
8228         struct intel_crtc *intel_crtc;
8229         struct intel_encoder *intel_encoder =
8230                 intel_attached_encoder(connector);
8231         struct drm_crtc *possible_crtc;
8232         struct drm_encoder *encoder = &intel_encoder->base;
8233         struct drm_crtc *crtc = NULL;
8234         struct drm_device *dev = encoder->dev;
8235         struct drm_framebuffer *fb;
8236         int i = -1;
8237
8238         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8239                       connector->base.id, drm_get_connector_name(connector),
8240                       encoder->base.id, drm_get_encoder_name(encoder));
8241
8242         /*
8243          * Algorithm gets a little messy:
8244          *
8245          *   - if the connector already has an assigned crtc, use it (but make
8246          *     sure it's on first)
8247          *
8248          *   - try to find the first unused crtc that can drive this connector,
8249          *     and use that if we find one
8250          */
8251
8252         /* See if we already have a CRTC for this connector */
8253         if (encoder->crtc) {
8254                 crtc = encoder->crtc;
8255
8256                 mutex_lock(&crtc->mutex);
8257
8258                 old->dpms_mode = connector->dpms;
8259                 old->load_detect_temp = false;
8260
8261                 /* Make sure the crtc and connector are running */
8262                 if (connector->dpms != DRM_MODE_DPMS_ON)
8263                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8264
8265                 return true;
8266         }
8267
8268         /* Find an unused one (if possible) */
8269         for_each_crtc(dev, possible_crtc) {
8270                 i++;
8271                 if (!(encoder->possible_crtcs & (1 << i)))
8272                         continue;
8273                 if (!possible_crtc->enabled) {
8274                         crtc = possible_crtc;
8275                         break;
8276                 }
8277         }
8278
8279         /*
8280          * If we didn't find an unused CRTC, don't use any.
8281          */
8282         if (!crtc) {
8283                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8284                 return false;
8285         }
8286
8287         mutex_lock(&crtc->mutex);
8288         intel_encoder->new_crtc = to_intel_crtc(crtc);
8289         to_intel_connector(connector)->new_encoder = intel_encoder;
8290
8291         intel_crtc = to_intel_crtc(crtc);
8292         intel_crtc->new_enabled = true;
8293         intel_crtc->new_config = &intel_crtc->config;
8294         old->dpms_mode = connector->dpms;
8295         old->load_detect_temp = true;
8296         old->release_fb = NULL;
8297
8298         if (!mode)
8299                 mode = &load_detect_mode;
8300
8301         /* We need a framebuffer large enough to accommodate all accesses
8302          * that the plane may generate whilst we perform load detection.
8303          * We can not rely on the fbcon either being present (we get called
8304          * during its initialisation to detect all boot displays, or it may
8305          * not even exist) or that it is large enough to satisfy the
8306          * requested mode.
8307          */
8308         fb = mode_fits_in_fbdev(dev, mode);
8309         if (fb == NULL) {
8310                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8311                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8312                 old->release_fb = fb;
8313         } else
8314                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8315         if (IS_ERR(fb)) {
8316                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8317                 goto fail;
8318         }
8319
8320         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8321                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8322                 if (old->release_fb)
8323                         old->release_fb->funcs->destroy(old->release_fb);
8324                 goto fail;
8325         }
8326
8327         /* let the connector get through one full cycle before testing */
8328         intel_wait_for_vblank(dev, intel_crtc->pipe);
8329         return true;
8330
8331  fail:
8332         intel_crtc->new_enabled = crtc->enabled;
8333         if (intel_crtc->new_enabled)
8334                 intel_crtc->new_config = &intel_crtc->config;
8335         else
8336                 intel_crtc->new_config = NULL;
8337         mutex_unlock(&crtc->mutex);
8338         return false;
8339 }
8340
8341 void intel_release_load_detect_pipe(struct drm_connector *connector,
8342                                     struct intel_load_detect_pipe *old)
8343 {
8344         struct intel_encoder *intel_encoder =
8345                 intel_attached_encoder(connector);
8346         struct drm_encoder *encoder = &intel_encoder->base;
8347         struct drm_crtc *crtc = encoder->crtc;
8348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8349
8350         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8351                       connector->base.id, drm_get_connector_name(connector),
8352                       encoder->base.id, drm_get_encoder_name(encoder));
8353
8354         if (old->load_detect_temp) {
8355                 to_intel_connector(connector)->new_encoder = NULL;
8356                 intel_encoder->new_crtc = NULL;
8357                 intel_crtc->new_enabled = false;
8358                 intel_crtc->new_config = NULL;
8359                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8360
8361                 if (old->release_fb) {
8362                         drm_framebuffer_unregister_private(old->release_fb);
8363                         drm_framebuffer_unreference(old->release_fb);
8364                 }
8365
8366                 mutex_unlock(&crtc->mutex);
8367                 return;
8368         }
8369
8370         /* Switch crtc and encoder back off if necessary */
8371         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8372                 connector->funcs->dpms(connector, old->dpms_mode);
8373
8374         mutex_unlock(&crtc->mutex);
8375 }
8376
8377 static int i9xx_pll_refclk(struct drm_device *dev,
8378                            const struct intel_crtc_config *pipe_config)
8379 {
8380         struct drm_i915_private *dev_priv = dev->dev_private;
8381         u32 dpll = pipe_config->dpll_hw_state.dpll;
8382
8383         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8384                 return dev_priv->vbt.lvds_ssc_freq;
8385         else if (HAS_PCH_SPLIT(dev))
8386                 return 120000;
8387         else if (!IS_GEN2(dev))
8388                 return 96000;
8389         else
8390                 return 48000;
8391 }
8392
8393 /* Returns the clock of the currently programmed mode of the given pipe. */
8394 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8395                                 struct intel_crtc_config *pipe_config)
8396 {
8397         struct drm_device *dev = crtc->base.dev;
8398         struct drm_i915_private *dev_priv = dev->dev_private;
8399         int pipe = pipe_config->cpu_transcoder;
8400         u32 dpll = pipe_config->dpll_hw_state.dpll;
8401         u32 fp;
8402         intel_clock_t clock;
8403         int refclk = i9xx_pll_refclk(dev, pipe_config);
8404
8405         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8406                 fp = pipe_config->dpll_hw_state.fp0;
8407         else
8408                 fp = pipe_config->dpll_hw_state.fp1;
8409
8410         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8411         if (IS_PINEVIEW(dev)) {
8412                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8413                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8414         } else {
8415                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8416                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8417         }
8418
8419         if (!IS_GEN2(dev)) {
8420                 if (IS_PINEVIEW(dev))
8421                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8422                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8423                 else
8424                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8425                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8426
8427                 switch (dpll & DPLL_MODE_MASK) {
8428                 case DPLLB_MODE_DAC_SERIAL:
8429                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8430                                 5 : 10;
8431                         break;
8432                 case DPLLB_MODE_LVDS:
8433                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8434                                 7 : 14;
8435                         break;
8436                 default:
8437                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8438                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8439                         return;
8440                 }
8441
8442                 if (IS_PINEVIEW(dev))
8443                         pineview_clock(refclk, &clock);
8444                 else
8445                         i9xx_clock(refclk, &clock);
8446         } else {
8447                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8448                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8449
8450                 if (is_lvds) {
8451                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8452                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8453
8454                         if (lvds & LVDS_CLKB_POWER_UP)
8455                                 clock.p2 = 7;
8456                         else
8457                                 clock.p2 = 14;
8458                 } else {
8459                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8460                                 clock.p1 = 2;
8461                         else {
8462                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8463                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8464                         }
8465                         if (dpll & PLL_P2_DIVIDE_BY_4)
8466                                 clock.p2 = 4;
8467                         else
8468                                 clock.p2 = 2;
8469                 }
8470
8471                 i9xx_clock(refclk, &clock);
8472         }
8473
8474         /*
8475          * This value includes pixel_multiplier. We will use
8476          * port_clock to compute adjusted_mode.crtc_clock in the
8477          * encoder's get_config() function.
8478          */
8479         pipe_config->port_clock = clock.dot;
8480 }
8481
8482 int intel_dotclock_calculate(int link_freq,
8483                              const struct intel_link_m_n *m_n)
8484 {
8485         /*
8486          * The calculation for the data clock is:
8487          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8488          * But we want to avoid losing precison if possible, so:
8489          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8490          *
8491          * and the link clock is simpler:
8492          * link_clock = (m * link_clock) / n
8493          */
8494
8495         if (!m_n->link_n)
8496                 return 0;
8497
8498         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8499 }
8500
8501 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8502                                    struct intel_crtc_config *pipe_config)
8503 {
8504         struct drm_device *dev = crtc->base.dev;
8505
8506         /* read out port_clock from the DPLL */
8507         i9xx_crtc_clock_get(crtc, pipe_config);
8508
8509         /*
8510          * This value does not include pixel_multiplier.
8511          * We will check that port_clock and adjusted_mode.crtc_clock
8512          * agree once we know their relationship in the encoder's
8513          * get_config() function.
8514          */
8515         pipe_config->adjusted_mode.crtc_clock =
8516                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8517                                          &pipe_config->fdi_m_n);
8518 }
8519
8520 /** Returns the currently programmed mode of the given pipe. */
8521 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8522                                              struct drm_crtc *crtc)
8523 {
8524         struct drm_i915_private *dev_priv = dev->dev_private;
8525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8526         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8527         struct drm_display_mode *mode;
8528         struct intel_crtc_config pipe_config;
8529         int htot = I915_READ(HTOTAL(cpu_transcoder));
8530         int hsync = I915_READ(HSYNC(cpu_transcoder));
8531         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8532         int vsync = I915_READ(VSYNC(cpu_transcoder));
8533         enum pipe pipe = intel_crtc->pipe;
8534
8535         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8536         if (!mode)
8537                 return NULL;
8538
8539         /*
8540          * Construct a pipe_config sufficient for getting the clock info
8541          * back out of crtc_clock_get.
8542          *
8543          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8544          * to use a real value here instead.
8545          */
8546         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8547         pipe_config.pixel_multiplier = 1;
8548         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8549         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8550         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8551         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8552
8553         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8554         mode->hdisplay = (htot & 0xffff) + 1;
8555         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8556         mode->hsync_start = (hsync & 0xffff) + 1;
8557         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8558         mode->vdisplay = (vtot & 0xffff) + 1;
8559         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8560         mode->vsync_start = (vsync & 0xffff) + 1;
8561         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8562
8563         drm_mode_set_name(mode);
8564
8565         return mode;
8566 }
8567
8568 static void intel_increase_pllclock(struct drm_crtc *crtc)
8569 {
8570         struct drm_device *dev = crtc->dev;
8571         struct drm_i915_private *dev_priv = dev->dev_private;
8572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8573         int pipe = intel_crtc->pipe;
8574         int dpll_reg = DPLL(pipe);
8575         int dpll;
8576
8577         if (HAS_PCH_SPLIT(dev))
8578                 return;
8579
8580         if (!dev_priv->lvds_downclock_avail)
8581                 return;
8582
8583         dpll = I915_READ(dpll_reg);
8584         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8585                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8586
8587                 assert_panel_unlocked(dev_priv, pipe);
8588
8589                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8590                 I915_WRITE(dpll_reg, dpll);
8591                 intel_wait_for_vblank(dev, pipe);
8592
8593                 dpll = I915_READ(dpll_reg);
8594                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8595                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8596         }
8597 }
8598
8599 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8600 {
8601         struct drm_device *dev = crtc->dev;
8602         struct drm_i915_private *dev_priv = dev->dev_private;
8603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8604
8605         if (HAS_PCH_SPLIT(dev))
8606                 return;
8607
8608         if (!dev_priv->lvds_downclock_avail)
8609                 return;
8610
8611         /*
8612          * Since this is called by a timer, we should never get here in
8613          * the manual case.
8614          */
8615         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8616                 int pipe = intel_crtc->pipe;
8617                 int dpll_reg = DPLL(pipe);
8618                 int dpll;
8619
8620                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8621
8622                 assert_panel_unlocked(dev_priv, pipe);
8623
8624                 dpll = I915_READ(dpll_reg);
8625                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8626                 I915_WRITE(dpll_reg, dpll);
8627                 intel_wait_for_vblank(dev, pipe);
8628                 dpll = I915_READ(dpll_reg);
8629                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8630                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8631         }
8632
8633 }
8634
8635 void intel_mark_busy(struct drm_device *dev)
8636 {
8637         struct drm_i915_private *dev_priv = dev->dev_private;
8638
8639         if (dev_priv->mm.busy)
8640                 return;
8641
8642         intel_runtime_pm_get(dev_priv);
8643         i915_update_gfx_val(dev_priv);
8644         dev_priv->mm.busy = true;
8645 }
8646
8647 void intel_mark_idle(struct drm_device *dev)
8648 {
8649         struct drm_i915_private *dev_priv = dev->dev_private;
8650         struct drm_crtc *crtc;
8651
8652         if (!dev_priv->mm.busy)
8653                 return;
8654
8655         dev_priv->mm.busy = false;
8656
8657         if (!i915.powersave)
8658                 goto out;
8659
8660         for_each_crtc(dev, crtc) {
8661                 if (!crtc->primary->fb)
8662                         continue;
8663
8664                 intel_decrease_pllclock(crtc);
8665         }
8666
8667         if (INTEL_INFO(dev)->gen >= 6)
8668                 gen6_rps_idle(dev->dev_private);
8669
8670 out:
8671         intel_runtime_pm_put(dev_priv);
8672 }
8673
8674 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8675                         struct intel_ring_buffer *ring)
8676 {
8677         struct drm_device *dev = obj->base.dev;
8678         struct drm_crtc *crtc;
8679
8680         if (!i915.powersave)
8681                 return;
8682
8683         for_each_crtc(dev, crtc) {
8684                 if (!crtc->primary->fb)
8685                         continue;
8686
8687                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8688                         continue;
8689
8690                 intel_increase_pllclock(crtc);
8691                 if (ring && intel_fbc_enabled(dev))
8692                         ring->fbc_dirty = true;
8693         }
8694 }
8695
8696 static void intel_crtc_destroy(struct drm_crtc *crtc)
8697 {
8698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8699         struct drm_device *dev = crtc->dev;
8700         struct intel_unpin_work *work;
8701         unsigned long flags;
8702
8703         spin_lock_irqsave(&dev->event_lock, flags);
8704         work = intel_crtc->unpin_work;
8705         intel_crtc->unpin_work = NULL;
8706         spin_unlock_irqrestore(&dev->event_lock, flags);
8707
8708         if (work) {
8709                 cancel_work_sync(&work->work);
8710                 kfree(work);
8711         }
8712
8713         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8714
8715         drm_crtc_cleanup(crtc);
8716
8717         kfree(intel_crtc);
8718 }
8719
8720 static void intel_unpin_work_fn(struct work_struct *__work)
8721 {
8722         struct intel_unpin_work *work =
8723                 container_of(__work, struct intel_unpin_work, work);
8724         struct drm_device *dev = work->crtc->dev;
8725
8726         mutex_lock(&dev->struct_mutex);
8727         intel_unpin_fb_obj(work->old_fb_obj);
8728         drm_gem_object_unreference(&work->pending_flip_obj->base);
8729         drm_gem_object_unreference(&work->old_fb_obj->base);
8730
8731         intel_update_fbc(dev);
8732         mutex_unlock(&dev->struct_mutex);
8733
8734         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8735         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8736
8737         kfree(work);
8738 }
8739
8740 static void do_intel_finish_page_flip(struct drm_device *dev,
8741                                       struct drm_crtc *crtc)
8742 {
8743         struct drm_i915_private *dev_priv = dev->dev_private;
8744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8745         struct intel_unpin_work *work;
8746         unsigned long flags;
8747
8748         /* Ignore early vblank irqs */
8749         if (intel_crtc == NULL)
8750                 return;
8751
8752         spin_lock_irqsave(&dev->event_lock, flags);
8753         work = intel_crtc->unpin_work;
8754
8755         /* Ensure we don't miss a work->pending update ... */
8756         smp_rmb();
8757
8758         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8759                 spin_unlock_irqrestore(&dev->event_lock, flags);
8760                 return;
8761         }
8762
8763         /* and that the unpin work is consistent wrt ->pending. */
8764         smp_rmb();
8765
8766         intel_crtc->unpin_work = NULL;
8767
8768         if (work->event)
8769                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8770
8771         drm_vblank_put(dev, intel_crtc->pipe);
8772
8773         spin_unlock_irqrestore(&dev->event_lock, flags);
8774
8775         wake_up_all(&dev_priv->pending_flip_queue);
8776
8777         queue_work(dev_priv->wq, &work->work);
8778
8779         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8780 }
8781
8782 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8783 {
8784         struct drm_i915_private *dev_priv = dev->dev_private;
8785         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8786
8787         do_intel_finish_page_flip(dev, crtc);
8788 }
8789
8790 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8791 {
8792         struct drm_i915_private *dev_priv = dev->dev_private;
8793         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8794
8795         do_intel_finish_page_flip(dev, crtc);
8796 }
8797
8798 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8799 {
8800         struct drm_i915_private *dev_priv = dev->dev_private;
8801         struct intel_crtc *intel_crtc =
8802                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8803         unsigned long flags;
8804
8805         /* NB: An MMIO update of the plane base pointer will also
8806          * generate a page-flip completion irq, i.e. every modeset
8807          * is also accompanied by a spurious intel_prepare_page_flip().
8808          */
8809         spin_lock_irqsave(&dev->event_lock, flags);
8810         if (intel_crtc->unpin_work)
8811                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8812         spin_unlock_irqrestore(&dev->event_lock, flags);
8813 }
8814
8815 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8816 {
8817         /* Ensure that the work item is consistent when activating it ... */
8818         smp_wmb();
8819         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8820         /* and that it is marked active as soon as the irq could fire. */
8821         smp_wmb();
8822 }
8823
8824 static int intel_gen2_queue_flip(struct drm_device *dev,
8825                                  struct drm_crtc *crtc,
8826                                  struct drm_framebuffer *fb,
8827                                  struct drm_i915_gem_object *obj,
8828                                  uint32_t flags)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8832         u32 flip_mask;
8833         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8834         int ret;
8835
8836         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8837         if (ret)
8838                 goto err;
8839
8840         ret = intel_ring_begin(ring, 6);
8841         if (ret)
8842                 goto err_unpin;
8843
8844         /* Can't queue multiple flips, so wait for the previous
8845          * one to finish before executing the next.
8846          */
8847         if (intel_crtc->plane)
8848                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8849         else
8850                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8851         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8852         intel_ring_emit(ring, MI_NOOP);
8853         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8854                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8855         intel_ring_emit(ring, fb->pitches[0]);
8856         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8857         intel_ring_emit(ring, 0); /* aux display base address, unused */
8858
8859         intel_mark_page_flip_active(intel_crtc);
8860         __intel_ring_advance(ring);
8861         return 0;
8862
8863 err_unpin:
8864         intel_unpin_fb_obj(obj);
8865 err:
8866         return ret;
8867 }
8868
8869 static int intel_gen3_queue_flip(struct drm_device *dev,
8870                                  struct drm_crtc *crtc,
8871                                  struct drm_framebuffer *fb,
8872                                  struct drm_i915_gem_object *obj,
8873                                  uint32_t flags)
8874 {
8875         struct drm_i915_private *dev_priv = dev->dev_private;
8876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8877         u32 flip_mask;
8878         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8879         int ret;
8880
8881         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8882         if (ret)
8883                 goto err;
8884
8885         ret = intel_ring_begin(ring, 6);
8886         if (ret)
8887                 goto err_unpin;
8888
8889         if (intel_crtc->plane)
8890                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8891         else
8892                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8893         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8894         intel_ring_emit(ring, MI_NOOP);
8895         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8896                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8897         intel_ring_emit(ring, fb->pitches[0]);
8898         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8899         intel_ring_emit(ring, MI_NOOP);
8900
8901         intel_mark_page_flip_active(intel_crtc);
8902         __intel_ring_advance(ring);
8903         return 0;
8904
8905 err_unpin:
8906         intel_unpin_fb_obj(obj);
8907 err:
8908         return ret;
8909 }
8910
8911 static int intel_gen4_queue_flip(struct drm_device *dev,
8912                                  struct drm_crtc *crtc,
8913                                  struct drm_framebuffer *fb,
8914                                  struct drm_i915_gem_object *obj,
8915                                  uint32_t flags)
8916 {
8917         struct drm_i915_private *dev_priv = dev->dev_private;
8918         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8919         uint32_t pf, pipesrc;
8920         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8921         int ret;
8922
8923         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8924         if (ret)
8925                 goto err;
8926
8927         ret = intel_ring_begin(ring, 4);
8928         if (ret)
8929                 goto err_unpin;
8930
8931         /* i965+ uses the linear or tiled offsets from the
8932          * Display Registers (which do not change across a page-flip)
8933          * so we need only reprogram the base address.
8934          */
8935         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8936                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8937         intel_ring_emit(ring, fb->pitches[0]);
8938         intel_ring_emit(ring,
8939                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8940                         obj->tiling_mode);
8941
8942         /* XXX Enabling the panel-fitter across page-flip is so far
8943          * untested on non-native modes, so ignore it for now.
8944          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8945          */
8946         pf = 0;
8947         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8948         intel_ring_emit(ring, pf | pipesrc);
8949
8950         intel_mark_page_flip_active(intel_crtc);
8951         __intel_ring_advance(ring);
8952         return 0;
8953
8954 err_unpin:
8955         intel_unpin_fb_obj(obj);
8956 err:
8957         return ret;
8958 }
8959
8960 static int intel_gen6_queue_flip(struct drm_device *dev,
8961                                  struct drm_crtc *crtc,
8962                                  struct drm_framebuffer *fb,
8963                                  struct drm_i915_gem_object *obj,
8964                                  uint32_t flags)
8965 {
8966         struct drm_i915_private *dev_priv = dev->dev_private;
8967         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8968         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8969         uint32_t pf, pipesrc;
8970         int ret;
8971
8972         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8973         if (ret)
8974                 goto err;
8975
8976         ret = intel_ring_begin(ring, 4);
8977         if (ret)
8978                 goto err_unpin;
8979
8980         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8981                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8982         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8983         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8984
8985         /* Contrary to the suggestions in the documentation,
8986          * "Enable Panel Fitter" does not seem to be required when page
8987          * flipping with a non-native mode, and worse causes a normal
8988          * modeset to fail.
8989          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8990          */
8991         pf = 0;
8992         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8993         intel_ring_emit(ring, pf | pipesrc);
8994
8995         intel_mark_page_flip_active(intel_crtc);
8996         __intel_ring_advance(ring);
8997         return 0;
8998
8999 err_unpin:
9000         intel_unpin_fb_obj(obj);
9001 err:
9002         return ret;
9003 }
9004
9005 static int intel_gen7_queue_flip(struct drm_device *dev,
9006                                  struct drm_crtc *crtc,
9007                                  struct drm_framebuffer *fb,
9008                                  struct drm_i915_gem_object *obj,
9009                                  uint32_t flags)
9010 {
9011         struct drm_i915_private *dev_priv = dev->dev_private;
9012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9013         struct intel_ring_buffer *ring;
9014         uint32_t plane_bit = 0;
9015         int len, ret;
9016
9017         ring = obj->ring;
9018         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9019                 ring = &dev_priv->ring[BCS];
9020
9021         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9022         if (ret)
9023                 goto err;
9024
9025         switch(intel_crtc->plane) {
9026         case PLANE_A:
9027                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9028                 break;
9029         case PLANE_B:
9030                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9031                 break;
9032         case PLANE_C:
9033                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9034                 break;
9035         default:
9036                 WARN_ONCE(1, "unknown plane in flip command\n");
9037                 ret = -ENODEV;
9038                 goto err_unpin;
9039         }
9040
9041         len = 4;
9042         if (ring->id == RCS) {
9043                 len += 6;
9044                 /*
9045                  * On Gen 8, SRM is now taking an extra dword to accommodate
9046                  * 48bits addresses, and we need a NOOP for the batch size to
9047                  * stay even.
9048                  */
9049                 if (IS_GEN8(dev))
9050                         len += 2;
9051         }
9052
9053         /*
9054          * BSpec MI_DISPLAY_FLIP for IVB:
9055          * "The full packet must be contained within the same cache line."
9056          *
9057          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9058          * cacheline, if we ever start emitting more commands before
9059          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9060          * then do the cacheline alignment, and finally emit the
9061          * MI_DISPLAY_FLIP.
9062          */
9063         ret = intel_ring_cacheline_align(ring);
9064         if (ret)
9065                 goto err_unpin;
9066
9067         ret = intel_ring_begin(ring, len);
9068         if (ret)
9069                 goto err_unpin;
9070
9071         /* Unmask the flip-done completion message. Note that the bspec says that
9072          * we should do this for both the BCS and RCS, and that we must not unmask
9073          * more than one flip event at any time (or ensure that one flip message
9074          * can be sent by waiting for flip-done prior to queueing new flips).
9075          * Experimentation says that BCS works despite DERRMR masking all
9076          * flip-done completion events and that unmasking all planes at once
9077          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9078          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9079          */
9080         if (ring->id == RCS) {
9081                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9082                 intel_ring_emit(ring, DERRMR);
9083                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9084                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9085                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9086                 if (IS_GEN8(dev))
9087                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9088                                               MI_SRM_LRM_GLOBAL_GTT);
9089                 else
9090                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9091                                               MI_SRM_LRM_GLOBAL_GTT);
9092                 intel_ring_emit(ring, DERRMR);
9093                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9094                 if (IS_GEN8(dev)) {
9095                         intel_ring_emit(ring, 0);
9096                         intel_ring_emit(ring, MI_NOOP);
9097                 }
9098         }
9099
9100         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9101         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9102         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9103         intel_ring_emit(ring, (MI_NOOP));
9104
9105         intel_mark_page_flip_active(intel_crtc);
9106         __intel_ring_advance(ring);
9107         return 0;
9108
9109 err_unpin:
9110         intel_unpin_fb_obj(obj);
9111 err:
9112         return ret;
9113 }
9114
9115 static int intel_default_queue_flip(struct drm_device *dev,
9116                                     struct drm_crtc *crtc,
9117                                     struct drm_framebuffer *fb,
9118                                     struct drm_i915_gem_object *obj,
9119                                     uint32_t flags)
9120 {
9121         return -ENODEV;
9122 }
9123
9124 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9125                                 struct drm_framebuffer *fb,
9126                                 struct drm_pending_vblank_event *event,
9127                                 uint32_t page_flip_flags)
9128 {
9129         struct drm_device *dev = crtc->dev;
9130         struct drm_i915_private *dev_priv = dev->dev_private;
9131         struct drm_framebuffer *old_fb = crtc->primary->fb;
9132         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9134         struct intel_unpin_work *work;
9135         unsigned long flags;
9136         int ret;
9137
9138         /* Can't change pixel format via MI display flips. */
9139         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9140                 return -EINVAL;
9141
9142         /*
9143          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9144          * Note that pitch changes could also affect these register.
9145          */
9146         if (INTEL_INFO(dev)->gen > 3 &&
9147             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9148              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9149                 return -EINVAL;
9150
9151         if (i915_terminally_wedged(&dev_priv->gpu_error))
9152                 goto out_hang;
9153
9154         work = kzalloc(sizeof(*work), GFP_KERNEL);
9155         if (work == NULL)
9156                 return -ENOMEM;
9157
9158         work->event = event;
9159         work->crtc = crtc;
9160         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9161         INIT_WORK(&work->work, intel_unpin_work_fn);
9162
9163         ret = drm_vblank_get(dev, intel_crtc->pipe);
9164         if (ret)
9165                 goto free_work;
9166
9167         /* We borrow the event spin lock for protecting unpin_work */
9168         spin_lock_irqsave(&dev->event_lock, flags);
9169         if (intel_crtc->unpin_work) {
9170                 spin_unlock_irqrestore(&dev->event_lock, flags);
9171                 kfree(work);
9172                 drm_vblank_put(dev, intel_crtc->pipe);
9173
9174                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9175                 return -EBUSY;
9176         }
9177         intel_crtc->unpin_work = work;
9178         spin_unlock_irqrestore(&dev->event_lock, flags);
9179
9180         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9181                 flush_workqueue(dev_priv->wq);
9182
9183         ret = i915_mutex_lock_interruptible(dev);
9184         if (ret)
9185                 goto cleanup;
9186
9187         /* Reference the objects for the scheduled work. */
9188         drm_gem_object_reference(&work->old_fb_obj->base);
9189         drm_gem_object_reference(&obj->base);
9190
9191         crtc->primary->fb = fb;
9192
9193         work->pending_flip_obj = obj;
9194
9195         work->enable_stall_check = true;
9196
9197         atomic_inc(&intel_crtc->unpin_work_count);
9198         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9199
9200         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9201         if (ret)
9202                 goto cleanup_pending;
9203
9204         intel_disable_fbc(dev);
9205         intel_mark_fb_busy(obj, NULL);
9206         mutex_unlock(&dev->struct_mutex);
9207
9208         trace_i915_flip_request(intel_crtc->plane, obj);
9209
9210         return 0;
9211
9212 cleanup_pending:
9213         atomic_dec(&intel_crtc->unpin_work_count);
9214         crtc->primary->fb = old_fb;
9215         drm_gem_object_unreference(&work->old_fb_obj->base);
9216         drm_gem_object_unreference(&obj->base);
9217         mutex_unlock(&dev->struct_mutex);
9218
9219 cleanup:
9220         spin_lock_irqsave(&dev->event_lock, flags);
9221         intel_crtc->unpin_work = NULL;
9222         spin_unlock_irqrestore(&dev->event_lock, flags);
9223
9224         drm_vblank_put(dev, intel_crtc->pipe);
9225 free_work:
9226         kfree(work);
9227
9228         if (ret == -EIO) {
9229 out_hang:
9230                 intel_crtc_wait_for_pending_flips(crtc);
9231                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9232                 if (ret == 0 && event)
9233                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9234         }
9235         return ret;
9236 }
9237
9238 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9239         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9240         .load_lut = intel_crtc_load_lut,
9241 };
9242
9243 /**
9244  * intel_modeset_update_staged_output_state
9245  *
9246  * Updates the staged output configuration state, e.g. after we've read out the
9247  * current hw state.
9248  */
9249 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9250 {
9251         struct intel_crtc *crtc;
9252         struct intel_encoder *encoder;
9253         struct intel_connector *connector;
9254
9255         list_for_each_entry(connector, &dev->mode_config.connector_list,
9256                             base.head) {
9257                 connector->new_encoder =
9258                         to_intel_encoder(connector->base.encoder);
9259         }
9260
9261         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9262                             base.head) {
9263                 encoder->new_crtc =
9264                         to_intel_crtc(encoder->base.crtc);
9265         }
9266
9267         for_each_intel_crtc(dev, crtc) {
9268                 crtc->new_enabled = crtc->base.enabled;
9269
9270                 if (crtc->new_enabled)
9271                         crtc->new_config = &crtc->config;
9272                 else
9273                         crtc->new_config = NULL;
9274         }
9275 }
9276
9277 /**
9278  * intel_modeset_commit_output_state
9279  *
9280  * This function copies the stage display pipe configuration to the real one.
9281  */
9282 static void intel_modeset_commit_output_state(struct drm_device *dev)
9283 {
9284         struct intel_crtc *crtc;
9285         struct intel_encoder *encoder;
9286         struct intel_connector *connector;
9287
9288         list_for_each_entry(connector, &dev->mode_config.connector_list,
9289                             base.head) {
9290                 connector->base.encoder = &connector->new_encoder->base;
9291         }
9292
9293         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9294                             base.head) {
9295                 encoder->base.crtc = &encoder->new_crtc->base;
9296         }
9297
9298         for_each_intel_crtc(dev, crtc) {
9299                 crtc->base.enabled = crtc->new_enabled;
9300         }
9301 }
9302
9303 static void
9304 connected_sink_compute_bpp(struct intel_connector * connector,
9305                            struct intel_crtc_config *pipe_config)
9306 {
9307         int bpp = pipe_config->pipe_bpp;
9308
9309         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9310                 connector->base.base.id,
9311                 drm_get_connector_name(&connector->base));
9312
9313         /* Don't use an invalid EDID bpc value */
9314         if (connector->base.display_info.bpc &&
9315             connector->base.display_info.bpc * 3 < bpp) {
9316                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9317                               bpp, connector->base.display_info.bpc*3);
9318                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9319         }
9320
9321         /* Clamp bpp to 8 on screens without EDID 1.4 */
9322         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9323                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9324                               bpp);
9325                 pipe_config->pipe_bpp = 24;
9326         }
9327 }
9328
9329 static int
9330 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9331                           struct drm_framebuffer *fb,
9332                           struct intel_crtc_config *pipe_config)
9333 {
9334         struct drm_device *dev = crtc->base.dev;
9335         struct intel_connector *connector;
9336         int bpp;
9337
9338         switch (fb->pixel_format) {
9339         case DRM_FORMAT_C8:
9340                 bpp = 8*3; /* since we go through a colormap */
9341                 break;
9342         case DRM_FORMAT_XRGB1555:
9343         case DRM_FORMAT_ARGB1555:
9344                 /* checked in intel_framebuffer_init already */
9345                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9346                         return -EINVAL;
9347         case DRM_FORMAT_RGB565:
9348                 bpp = 6*3; /* min is 18bpp */
9349                 break;
9350         case DRM_FORMAT_XBGR8888:
9351         case DRM_FORMAT_ABGR8888:
9352                 /* checked in intel_framebuffer_init already */
9353                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9354                         return -EINVAL;
9355         case DRM_FORMAT_XRGB8888:
9356         case DRM_FORMAT_ARGB8888:
9357                 bpp = 8*3;
9358                 break;
9359         case DRM_FORMAT_XRGB2101010:
9360         case DRM_FORMAT_ARGB2101010:
9361         case DRM_FORMAT_XBGR2101010:
9362         case DRM_FORMAT_ABGR2101010:
9363                 /* checked in intel_framebuffer_init already */
9364                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9365                         return -EINVAL;
9366                 bpp = 10*3;
9367                 break;
9368         /* TODO: gen4+ supports 16 bpc floating point, too. */
9369         default:
9370                 DRM_DEBUG_KMS("unsupported depth\n");
9371                 return -EINVAL;
9372         }
9373
9374         pipe_config->pipe_bpp = bpp;
9375
9376         /* Clamp display bpp to EDID value */
9377         list_for_each_entry(connector, &dev->mode_config.connector_list,
9378                             base.head) {
9379                 if (!connector->new_encoder ||
9380                     connector->new_encoder->new_crtc != crtc)
9381                         continue;
9382
9383                 connected_sink_compute_bpp(connector, pipe_config);
9384         }
9385
9386         return bpp;
9387 }
9388
9389 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9390 {
9391         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9392                         "type: 0x%x flags: 0x%x\n",
9393                 mode->crtc_clock,
9394                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9395                 mode->crtc_hsync_end, mode->crtc_htotal,
9396                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9397                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9398 }
9399
9400 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9401                                    struct intel_crtc_config *pipe_config,
9402                                    const char *context)
9403 {
9404         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9405                       context, pipe_name(crtc->pipe));
9406
9407         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9408         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9409                       pipe_config->pipe_bpp, pipe_config->dither);
9410         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9411                       pipe_config->has_pch_encoder,
9412                       pipe_config->fdi_lanes,
9413                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9414                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9415                       pipe_config->fdi_m_n.tu);
9416         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9417                       pipe_config->has_dp_encoder,
9418                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9419                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9420                       pipe_config->dp_m_n.tu);
9421         DRM_DEBUG_KMS("requested mode:\n");
9422         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9423         DRM_DEBUG_KMS("adjusted mode:\n");
9424         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9425         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9426         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9427         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9428                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9429         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9430                       pipe_config->gmch_pfit.control,
9431                       pipe_config->gmch_pfit.pgm_ratios,
9432                       pipe_config->gmch_pfit.lvds_border_bits);
9433         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9434                       pipe_config->pch_pfit.pos,
9435                       pipe_config->pch_pfit.size,
9436                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9437         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9438         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9439 }
9440
9441 static bool encoders_cloneable(const struct intel_encoder *a,
9442                                const struct intel_encoder *b)
9443 {
9444         /* masks could be asymmetric, so check both ways */
9445         return a == b || (a->cloneable & (1 << b->type) &&
9446                           b->cloneable & (1 << a->type));
9447 }
9448
9449 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9450                                          struct intel_encoder *encoder)
9451 {
9452         struct drm_device *dev = crtc->base.dev;
9453         struct intel_encoder *source_encoder;
9454
9455         list_for_each_entry(source_encoder,
9456                             &dev->mode_config.encoder_list, base.head) {
9457                 if (source_encoder->new_crtc != crtc)
9458                         continue;
9459
9460                 if (!encoders_cloneable(encoder, source_encoder))
9461                         return false;
9462         }
9463
9464         return true;
9465 }
9466
9467 static bool check_encoder_cloning(struct intel_crtc *crtc)
9468 {
9469         struct drm_device *dev = crtc->base.dev;
9470         struct intel_encoder *encoder;
9471
9472         list_for_each_entry(encoder,
9473                             &dev->mode_config.encoder_list, base.head) {
9474                 if (encoder->new_crtc != crtc)
9475                         continue;
9476
9477                 if (!check_single_encoder_cloning(crtc, encoder))
9478                         return false;
9479         }
9480
9481         return true;
9482 }
9483
9484 static struct intel_crtc_config *
9485 intel_modeset_pipe_config(struct drm_crtc *crtc,
9486                           struct drm_framebuffer *fb,
9487                           struct drm_display_mode *mode)
9488 {
9489         struct drm_device *dev = crtc->dev;
9490         struct intel_encoder *encoder;
9491         struct intel_crtc_config *pipe_config;
9492         int plane_bpp, ret = -EINVAL;
9493         bool retry = true;
9494
9495         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9496                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9497                 return ERR_PTR(-EINVAL);
9498         }
9499
9500         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9501         if (!pipe_config)
9502                 return ERR_PTR(-ENOMEM);
9503
9504         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9505         drm_mode_copy(&pipe_config->requested_mode, mode);
9506
9507         pipe_config->cpu_transcoder =
9508                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9509         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9510
9511         /*
9512          * Sanitize sync polarity flags based on requested ones. If neither
9513          * positive or negative polarity is requested, treat this as meaning
9514          * negative polarity.
9515          */
9516         if (!(pipe_config->adjusted_mode.flags &
9517               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9518                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9519
9520         if (!(pipe_config->adjusted_mode.flags &
9521               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9522                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9523
9524         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9525          * plane pixel format and any sink constraints into account. Returns the
9526          * source plane bpp so that dithering can be selected on mismatches
9527          * after encoders and crtc also have had their say. */
9528         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9529                                               fb, pipe_config);
9530         if (plane_bpp < 0)
9531                 goto fail;
9532
9533         /*
9534          * Determine the real pipe dimensions. Note that stereo modes can
9535          * increase the actual pipe size due to the frame doubling and
9536          * insertion of additional space for blanks between the frame. This
9537          * is stored in the crtc timings. We use the requested mode to do this
9538          * computation to clearly distinguish it from the adjusted mode, which
9539          * can be changed by the connectors in the below retry loop.
9540          */
9541         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9542         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9543         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9544
9545 encoder_retry:
9546         /* Ensure the port clock defaults are reset when retrying. */
9547         pipe_config->port_clock = 0;
9548         pipe_config->pixel_multiplier = 1;
9549
9550         /* Fill in default crtc timings, allow encoders to overwrite them. */
9551         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9552
9553         /* Pass our mode to the connectors and the CRTC to give them a chance to
9554          * adjust it according to limitations or connector properties, and also
9555          * a chance to reject the mode entirely.
9556          */
9557         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9558                             base.head) {
9559
9560                 if (&encoder->new_crtc->base != crtc)
9561                         continue;
9562
9563                 if (!(encoder->compute_config(encoder, pipe_config))) {
9564                         DRM_DEBUG_KMS("Encoder config failure\n");
9565                         goto fail;
9566                 }
9567         }
9568
9569         /* Set default port clock if not overwritten by the encoder. Needs to be
9570          * done afterwards in case the encoder adjusts the mode. */
9571         if (!pipe_config->port_clock)
9572                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9573                         * pipe_config->pixel_multiplier;
9574
9575         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9576         if (ret < 0) {
9577                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9578                 goto fail;
9579         }
9580
9581         if (ret == RETRY) {
9582                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9583                         ret = -EINVAL;
9584                         goto fail;
9585                 }
9586
9587                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9588                 retry = false;
9589                 goto encoder_retry;
9590         }
9591
9592         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9593         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9594                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9595
9596         return pipe_config;
9597 fail:
9598         kfree(pipe_config);
9599         return ERR_PTR(ret);
9600 }
9601
9602 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9603  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9604 static void
9605 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9606                              unsigned *prepare_pipes, unsigned *disable_pipes)
9607 {
9608         struct intel_crtc *intel_crtc;
9609         struct drm_device *dev = crtc->dev;
9610         struct intel_encoder *encoder;
9611         struct intel_connector *connector;
9612         struct drm_crtc *tmp_crtc;
9613
9614         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9615
9616         /* Check which crtcs have changed outputs connected to them, these need
9617          * to be part of the prepare_pipes mask. We don't (yet) support global
9618          * modeset across multiple crtcs, so modeset_pipes will only have one
9619          * bit set at most. */
9620         list_for_each_entry(connector, &dev->mode_config.connector_list,
9621                             base.head) {
9622                 if (connector->base.encoder == &connector->new_encoder->base)
9623                         continue;
9624
9625                 if (connector->base.encoder) {
9626                         tmp_crtc = connector->base.encoder->crtc;
9627
9628                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9629                 }
9630
9631                 if (connector->new_encoder)
9632                         *prepare_pipes |=
9633                                 1 << connector->new_encoder->new_crtc->pipe;
9634         }
9635
9636         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9637                             base.head) {
9638                 if (encoder->base.crtc == &encoder->new_crtc->base)
9639                         continue;
9640
9641                 if (encoder->base.crtc) {
9642                         tmp_crtc = encoder->base.crtc;
9643
9644                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9645                 }
9646
9647                 if (encoder->new_crtc)
9648                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9649         }
9650
9651         /* Check for pipes that will be enabled/disabled ... */
9652         for_each_intel_crtc(dev, intel_crtc) {
9653                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9654                         continue;
9655
9656                 if (!intel_crtc->new_enabled)
9657                         *disable_pipes |= 1 << intel_crtc->pipe;
9658                 else
9659                         *prepare_pipes |= 1 << intel_crtc->pipe;
9660         }
9661
9662
9663         /* set_mode is also used to update properties on life display pipes. */
9664         intel_crtc = to_intel_crtc(crtc);
9665         if (intel_crtc->new_enabled)
9666                 *prepare_pipes |= 1 << intel_crtc->pipe;
9667
9668         /*
9669          * For simplicity do a full modeset on any pipe where the output routing
9670          * changed. We could be more clever, but that would require us to be
9671          * more careful with calling the relevant encoder->mode_set functions.
9672          */
9673         if (*prepare_pipes)
9674                 *modeset_pipes = *prepare_pipes;
9675
9676         /* ... and mask these out. */
9677         *modeset_pipes &= ~(*disable_pipes);
9678         *prepare_pipes &= ~(*disable_pipes);
9679
9680         /*
9681          * HACK: We don't (yet) fully support global modesets. intel_set_config
9682          * obies this rule, but the modeset restore mode of
9683          * intel_modeset_setup_hw_state does not.
9684          */
9685         *modeset_pipes &= 1 << intel_crtc->pipe;
9686         *prepare_pipes &= 1 << intel_crtc->pipe;
9687
9688         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9689                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9690 }
9691
9692 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9693 {
9694         struct drm_encoder *encoder;
9695         struct drm_device *dev = crtc->dev;
9696
9697         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9698                 if (encoder->crtc == crtc)
9699                         return true;
9700
9701         return false;
9702 }
9703
9704 static void
9705 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9706 {
9707         struct intel_encoder *intel_encoder;
9708         struct intel_crtc *intel_crtc;
9709         struct drm_connector *connector;
9710
9711         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9712                             base.head) {
9713                 if (!intel_encoder->base.crtc)
9714                         continue;
9715
9716                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9717
9718                 if (prepare_pipes & (1 << intel_crtc->pipe))
9719                         intel_encoder->connectors_active = false;
9720         }
9721
9722         intel_modeset_commit_output_state(dev);
9723
9724         /* Double check state. */
9725         for_each_intel_crtc(dev, intel_crtc) {
9726                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9727                 WARN_ON(intel_crtc->new_config &&
9728                         intel_crtc->new_config != &intel_crtc->config);
9729                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9730         }
9731
9732         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9733                 if (!connector->encoder || !connector->encoder->crtc)
9734                         continue;
9735
9736                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9737
9738                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9739                         struct drm_property *dpms_property =
9740                                 dev->mode_config.dpms_property;
9741
9742                         connector->dpms = DRM_MODE_DPMS_ON;
9743                         drm_object_property_set_value(&connector->base,
9744                                                          dpms_property,
9745                                                          DRM_MODE_DPMS_ON);
9746
9747                         intel_encoder = to_intel_encoder(connector->encoder);
9748                         intel_encoder->connectors_active = true;
9749                 }
9750         }
9751
9752 }
9753
9754 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9755 {
9756         int diff;
9757
9758         if (clock1 == clock2)
9759                 return true;
9760
9761         if (!clock1 || !clock2)
9762                 return false;
9763
9764         diff = abs(clock1 - clock2);
9765
9766         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9767                 return true;
9768
9769         return false;
9770 }
9771
9772 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9773         list_for_each_entry((intel_crtc), \
9774                             &(dev)->mode_config.crtc_list, \
9775                             base.head) \
9776                 if (mask & (1 <<(intel_crtc)->pipe))
9777
9778 static bool
9779 intel_pipe_config_compare(struct drm_device *dev,
9780                           struct intel_crtc_config *current_config,
9781                           struct intel_crtc_config *pipe_config)
9782 {
9783 #define PIPE_CONF_CHECK_X(name) \
9784         if (current_config->name != pipe_config->name) { \
9785                 DRM_ERROR("mismatch in " #name " " \
9786                           "(expected 0x%08x, found 0x%08x)\n", \
9787                           current_config->name, \
9788                           pipe_config->name); \
9789                 return false; \
9790         }
9791
9792 #define PIPE_CONF_CHECK_I(name) \
9793         if (current_config->name != pipe_config->name) { \
9794                 DRM_ERROR("mismatch in " #name " " \
9795                           "(expected %i, found %i)\n", \
9796                           current_config->name, \
9797                           pipe_config->name); \
9798                 return false; \
9799         }
9800
9801 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9802         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9803                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9804                           "(expected %i, found %i)\n", \
9805                           current_config->name & (mask), \
9806                           pipe_config->name & (mask)); \
9807                 return false; \
9808         }
9809
9810 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9811         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9812                 DRM_ERROR("mismatch in " #name " " \
9813                           "(expected %i, found %i)\n", \
9814                           current_config->name, \
9815                           pipe_config->name); \
9816                 return false; \
9817         }
9818
9819 #define PIPE_CONF_QUIRK(quirk)  \
9820         ((current_config->quirks | pipe_config->quirks) & (quirk))
9821
9822         PIPE_CONF_CHECK_I(cpu_transcoder);
9823
9824         PIPE_CONF_CHECK_I(has_pch_encoder);
9825         PIPE_CONF_CHECK_I(fdi_lanes);
9826         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9827         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9828         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9829         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9830         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9831
9832         PIPE_CONF_CHECK_I(has_dp_encoder);
9833         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9834         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9835         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9836         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9837         PIPE_CONF_CHECK_I(dp_m_n.tu);
9838
9839         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9840         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9841         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9842         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9843         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9844         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9845
9846         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9847         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9848         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9849         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9850         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9851         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9852
9853         PIPE_CONF_CHECK_I(pixel_multiplier);
9854         PIPE_CONF_CHECK_I(has_hdmi_sink);
9855         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9856             IS_VALLEYVIEW(dev))
9857                 PIPE_CONF_CHECK_I(limited_color_range);
9858
9859         PIPE_CONF_CHECK_I(has_audio);
9860
9861         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9862                               DRM_MODE_FLAG_INTERLACE);
9863
9864         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9865                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9866                                       DRM_MODE_FLAG_PHSYNC);
9867                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9868                                       DRM_MODE_FLAG_NHSYNC);
9869                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9870                                       DRM_MODE_FLAG_PVSYNC);
9871                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9872                                       DRM_MODE_FLAG_NVSYNC);
9873         }
9874
9875         PIPE_CONF_CHECK_I(pipe_src_w);
9876         PIPE_CONF_CHECK_I(pipe_src_h);
9877
9878         /*
9879          * FIXME: BIOS likes to set up a cloned config with lvds+external
9880          * screen. Since we don't yet re-compute the pipe config when moving
9881          * just the lvds port away to another pipe the sw tracking won't match.
9882          *
9883          * Proper atomic modesets with recomputed global state will fix this.
9884          * Until then just don't check gmch state for inherited modes.
9885          */
9886         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9887                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9888                 /* pfit ratios are autocomputed by the hw on gen4+ */
9889                 if (INTEL_INFO(dev)->gen < 4)
9890                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9891                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9892         }
9893
9894         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9895         if (current_config->pch_pfit.enabled) {
9896                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9897                 PIPE_CONF_CHECK_I(pch_pfit.size);
9898         }
9899
9900         /* BDW+ don't expose a synchronous way to read the state */
9901         if (IS_HASWELL(dev))
9902                 PIPE_CONF_CHECK_I(ips_enabled);
9903
9904         PIPE_CONF_CHECK_I(double_wide);
9905
9906         PIPE_CONF_CHECK_I(shared_dpll);
9907         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9908         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9909         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9910         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9911
9912         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9913                 PIPE_CONF_CHECK_I(pipe_bpp);
9914
9915         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9916         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9917
9918 #undef PIPE_CONF_CHECK_X
9919 #undef PIPE_CONF_CHECK_I
9920 #undef PIPE_CONF_CHECK_FLAGS
9921 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9922 #undef PIPE_CONF_QUIRK
9923
9924         return true;
9925 }
9926
9927 static void
9928 check_connector_state(struct drm_device *dev)
9929 {
9930         struct intel_connector *connector;
9931
9932         list_for_each_entry(connector, &dev->mode_config.connector_list,
9933                             base.head) {
9934                 /* This also checks the encoder/connector hw state with the
9935                  * ->get_hw_state callbacks. */
9936                 intel_connector_check_state(connector);
9937
9938                 WARN(&connector->new_encoder->base != connector->base.encoder,
9939                      "connector's staged encoder doesn't match current encoder\n");
9940         }
9941 }
9942
9943 static void
9944 check_encoder_state(struct drm_device *dev)
9945 {
9946         struct intel_encoder *encoder;
9947         struct intel_connector *connector;
9948
9949         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9950                             base.head) {
9951                 bool enabled = false;
9952                 bool active = false;
9953                 enum pipe pipe, tracked_pipe;
9954
9955                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9956                               encoder->base.base.id,
9957                               drm_get_encoder_name(&encoder->base));
9958
9959                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9960                      "encoder's stage crtc doesn't match current crtc\n");
9961                 WARN(encoder->connectors_active && !encoder->base.crtc,
9962                      "encoder's active_connectors set, but no crtc\n");
9963
9964                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9965                                     base.head) {
9966                         if (connector->base.encoder != &encoder->base)
9967                                 continue;
9968                         enabled = true;
9969                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9970                                 active = true;
9971                 }
9972                 WARN(!!encoder->base.crtc != enabled,
9973                      "encoder's enabled state mismatch "
9974                      "(expected %i, found %i)\n",
9975                      !!encoder->base.crtc, enabled);
9976                 WARN(active && !encoder->base.crtc,
9977                      "active encoder with no crtc\n");
9978
9979                 WARN(encoder->connectors_active != active,
9980                      "encoder's computed active state doesn't match tracked active state "
9981                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9982
9983                 active = encoder->get_hw_state(encoder, &pipe);
9984                 WARN(active != encoder->connectors_active,
9985                      "encoder's hw state doesn't match sw tracking "
9986                      "(expected %i, found %i)\n",
9987                      encoder->connectors_active, active);
9988
9989                 if (!encoder->base.crtc)
9990                         continue;
9991
9992                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9993                 WARN(active && pipe != tracked_pipe,
9994                      "active encoder's pipe doesn't match"
9995                      "(expected %i, found %i)\n",
9996                      tracked_pipe, pipe);
9997
9998         }
9999 }
10000
10001 static void
10002 check_crtc_state(struct drm_device *dev)
10003 {
10004         struct drm_i915_private *dev_priv = dev->dev_private;
10005         struct intel_crtc *crtc;
10006         struct intel_encoder *encoder;
10007         struct intel_crtc_config pipe_config;
10008
10009         for_each_intel_crtc(dev, crtc) {
10010                 bool enabled = false;
10011                 bool active = false;
10012
10013                 memset(&pipe_config, 0, sizeof(pipe_config));
10014
10015                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10016                               crtc->base.base.id);
10017
10018                 WARN(crtc->active && !crtc->base.enabled,
10019                      "active crtc, but not enabled in sw tracking\n");
10020
10021                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10022                                     base.head) {
10023                         if (encoder->base.crtc != &crtc->base)
10024                                 continue;
10025                         enabled = true;
10026                         if (encoder->connectors_active)
10027                                 active = true;
10028                 }
10029
10030                 WARN(active != crtc->active,
10031                      "crtc's computed active state doesn't match tracked active state "
10032                      "(expected %i, found %i)\n", active, crtc->active);
10033                 WARN(enabled != crtc->base.enabled,
10034                      "crtc's computed enabled state doesn't match tracked enabled state "
10035                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10036
10037                 active = dev_priv->display.get_pipe_config(crtc,
10038                                                            &pipe_config);
10039
10040                 /* hw state is inconsistent with the pipe A quirk */
10041                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10042                         active = crtc->active;
10043
10044                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10045                                     base.head) {
10046                         enum pipe pipe;
10047                         if (encoder->base.crtc != &crtc->base)
10048                                 continue;
10049                         if (encoder->get_hw_state(encoder, &pipe))
10050                                 encoder->get_config(encoder, &pipe_config);
10051                 }
10052
10053                 WARN(crtc->active != active,
10054                      "crtc active state doesn't match with hw state "
10055                      "(expected %i, found %i)\n", crtc->active, active);
10056
10057                 if (active &&
10058                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10059                         WARN(1, "pipe state doesn't match!\n");
10060                         intel_dump_pipe_config(crtc, &pipe_config,
10061                                                "[hw state]");
10062                         intel_dump_pipe_config(crtc, &crtc->config,
10063                                                "[sw state]");
10064                 }
10065         }
10066 }
10067
10068 static void
10069 check_shared_dpll_state(struct drm_device *dev)
10070 {
10071         struct drm_i915_private *dev_priv = dev->dev_private;
10072         struct intel_crtc *crtc;
10073         struct intel_dpll_hw_state dpll_hw_state;
10074         int i;
10075
10076         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10077                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10078                 int enabled_crtcs = 0, active_crtcs = 0;
10079                 bool active;
10080
10081                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10082
10083                 DRM_DEBUG_KMS("%s\n", pll->name);
10084
10085                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10086
10087                 WARN(pll->active > pll->refcount,
10088                      "more active pll users than references: %i vs %i\n",
10089                      pll->active, pll->refcount);
10090                 WARN(pll->active && !pll->on,
10091                      "pll in active use but not on in sw tracking\n");
10092                 WARN(pll->on && !pll->active,
10093                      "pll in on but not on in use in sw tracking\n");
10094                 WARN(pll->on != active,
10095                      "pll on state mismatch (expected %i, found %i)\n",
10096                      pll->on, active);
10097
10098                 for_each_intel_crtc(dev, crtc) {
10099                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10100                                 enabled_crtcs++;
10101                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10102                                 active_crtcs++;
10103                 }
10104                 WARN(pll->active != active_crtcs,
10105                      "pll active crtcs mismatch (expected %i, found %i)\n",
10106                      pll->active, active_crtcs);
10107                 WARN(pll->refcount != enabled_crtcs,
10108                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10109                      pll->refcount, enabled_crtcs);
10110
10111                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10112                                        sizeof(dpll_hw_state)),
10113                      "pll hw state mismatch\n");
10114         }
10115 }
10116
10117 void
10118 intel_modeset_check_state(struct drm_device *dev)
10119 {
10120         check_connector_state(dev);
10121         check_encoder_state(dev);
10122         check_crtc_state(dev);
10123         check_shared_dpll_state(dev);
10124 }
10125
10126 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10127                                      int dotclock)
10128 {
10129         /*
10130          * FDI already provided one idea for the dotclock.
10131          * Yell if the encoder disagrees.
10132          */
10133         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10134              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10135              pipe_config->adjusted_mode.crtc_clock, dotclock);
10136 }
10137
10138 static int __intel_set_mode(struct drm_crtc *crtc,
10139                             struct drm_display_mode *mode,
10140                             int x, int y, struct drm_framebuffer *fb)
10141 {
10142         struct drm_device *dev = crtc->dev;
10143         struct drm_i915_private *dev_priv = dev->dev_private;
10144         struct drm_display_mode *saved_mode;
10145         struct intel_crtc_config *pipe_config = NULL;
10146         struct intel_crtc *intel_crtc;
10147         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10148         int ret = 0;
10149
10150         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10151         if (!saved_mode)
10152                 return -ENOMEM;
10153
10154         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10155                                      &prepare_pipes, &disable_pipes);
10156
10157         *saved_mode = crtc->mode;
10158
10159         /* Hack: Because we don't (yet) support global modeset on multiple
10160          * crtcs, we don't keep track of the new mode for more than one crtc.
10161          * Hence simply check whether any bit is set in modeset_pipes in all the
10162          * pieces of code that are not yet converted to deal with mutliple crtcs
10163          * changing their mode at the same time. */
10164         if (modeset_pipes) {
10165                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10166                 if (IS_ERR(pipe_config)) {
10167                         ret = PTR_ERR(pipe_config);
10168                         pipe_config = NULL;
10169
10170                         goto out;
10171                 }
10172                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10173                                        "[modeset]");
10174                 to_intel_crtc(crtc)->new_config = pipe_config;
10175         }
10176
10177         /*
10178          * See if the config requires any additional preparation, e.g.
10179          * to adjust global state with pipes off.  We need to do this
10180          * here so we can get the modeset_pipe updated config for the new
10181          * mode set on this crtc.  For other crtcs we need to use the
10182          * adjusted_mode bits in the crtc directly.
10183          */
10184         if (IS_VALLEYVIEW(dev)) {
10185                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10186
10187                 /* may have added more to prepare_pipes than we should */
10188                 prepare_pipes &= ~disable_pipes;
10189         }
10190
10191         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10192                 intel_crtc_disable(&intel_crtc->base);
10193
10194         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10195                 if (intel_crtc->base.enabled)
10196                         dev_priv->display.crtc_disable(&intel_crtc->base);
10197         }
10198
10199         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10200          * to set it here already despite that we pass it down the callchain.
10201          */
10202         if (modeset_pipes) {
10203                 crtc->mode = *mode;
10204                 /* mode_set/enable/disable functions rely on a correct pipe
10205                  * config. */
10206                 to_intel_crtc(crtc)->config = *pipe_config;
10207                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10208
10209                 /*
10210                  * Calculate and store various constants which
10211                  * are later needed by vblank and swap-completion
10212                  * timestamping. They are derived from true hwmode.
10213                  */
10214                 drm_calc_timestamping_constants(crtc,
10215                                                 &pipe_config->adjusted_mode);
10216         }
10217
10218         /* Only after disabling all output pipelines that will be changed can we
10219          * update the the output configuration. */
10220         intel_modeset_update_state(dev, prepare_pipes);
10221
10222         if (dev_priv->display.modeset_global_resources)
10223                 dev_priv->display.modeset_global_resources(dev);
10224
10225         /* Set up the DPLL and any encoders state that needs to adjust or depend
10226          * on the DPLL.
10227          */
10228         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10229                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10230                                                       x, y, fb);
10231                 if (ret)
10232                         goto done;
10233         }
10234
10235         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10236         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10237                 dev_priv->display.crtc_enable(&intel_crtc->base);
10238
10239         /* FIXME: add subpixel order */
10240 done:
10241         if (ret && crtc->enabled)
10242                 crtc->mode = *saved_mode;
10243
10244 out:
10245         kfree(pipe_config);
10246         kfree(saved_mode);
10247         return ret;
10248 }
10249
10250 static int intel_set_mode(struct drm_crtc *crtc,
10251                           struct drm_display_mode *mode,
10252                           int x, int y, struct drm_framebuffer *fb)
10253 {
10254         int ret;
10255
10256         ret = __intel_set_mode(crtc, mode, x, y, fb);
10257
10258         if (ret == 0)
10259                 intel_modeset_check_state(crtc->dev);
10260
10261         return ret;
10262 }
10263
10264 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10265 {
10266         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10267 }
10268
10269 #undef for_each_intel_crtc_masked
10270
10271 static void intel_set_config_free(struct intel_set_config *config)
10272 {
10273         if (!config)
10274                 return;
10275
10276         kfree(config->save_connector_encoders);
10277         kfree(config->save_encoder_crtcs);
10278         kfree(config->save_crtc_enabled);
10279         kfree(config);
10280 }
10281
10282 static int intel_set_config_save_state(struct drm_device *dev,
10283                                        struct intel_set_config *config)
10284 {
10285         struct drm_crtc *crtc;
10286         struct drm_encoder *encoder;
10287         struct drm_connector *connector;
10288         int count;
10289
10290         config->save_crtc_enabled =
10291                 kcalloc(dev->mode_config.num_crtc,
10292                         sizeof(bool), GFP_KERNEL);
10293         if (!config->save_crtc_enabled)
10294                 return -ENOMEM;
10295
10296         config->save_encoder_crtcs =
10297                 kcalloc(dev->mode_config.num_encoder,
10298                         sizeof(struct drm_crtc *), GFP_KERNEL);
10299         if (!config->save_encoder_crtcs)
10300                 return -ENOMEM;
10301
10302         config->save_connector_encoders =
10303                 kcalloc(dev->mode_config.num_connector,
10304                         sizeof(struct drm_encoder *), GFP_KERNEL);
10305         if (!config->save_connector_encoders)
10306                 return -ENOMEM;
10307
10308         /* Copy data. Note that driver private data is not affected.
10309          * Should anything bad happen only the expected state is
10310          * restored, not the drivers personal bookkeeping.
10311          */
10312         count = 0;
10313         for_each_crtc(dev, crtc) {
10314                 config->save_crtc_enabled[count++] = crtc->enabled;
10315         }
10316
10317         count = 0;
10318         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10319                 config->save_encoder_crtcs[count++] = encoder->crtc;
10320         }
10321
10322         count = 0;
10323         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10324                 config->save_connector_encoders[count++] = connector->encoder;
10325         }
10326
10327         return 0;
10328 }
10329
10330 static void intel_set_config_restore_state(struct drm_device *dev,
10331                                            struct intel_set_config *config)
10332 {
10333         struct intel_crtc *crtc;
10334         struct intel_encoder *encoder;
10335         struct intel_connector *connector;
10336         int count;
10337
10338         count = 0;
10339         for_each_intel_crtc(dev, crtc) {
10340                 crtc->new_enabled = config->save_crtc_enabled[count++];
10341
10342                 if (crtc->new_enabled)
10343                         crtc->new_config = &crtc->config;
10344                 else
10345                         crtc->new_config = NULL;
10346         }
10347
10348         count = 0;
10349         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10350                 encoder->new_crtc =
10351                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10352         }
10353
10354         count = 0;
10355         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10356                 connector->new_encoder =
10357                         to_intel_encoder(config->save_connector_encoders[count++]);
10358         }
10359 }
10360
10361 static bool
10362 is_crtc_connector_off(struct drm_mode_set *set)
10363 {
10364         int i;
10365
10366         if (set->num_connectors == 0)
10367                 return false;
10368
10369         if (WARN_ON(set->connectors == NULL))
10370                 return false;
10371
10372         for (i = 0; i < set->num_connectors; i++)
10373                 if (set->connectors[i]->encoder &&
10374                     set->connectors[i]->encoder->crtc == set->crtc &&
10375                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10376                         return true;
10377
10378         return false;
10379 }
10380
10381 static void
10382 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10383                                       struct intel_set_config *config)
10384 {
10385
10386         /* We should be able to check here if the fb has the same properties
10387          * and then just flip_or_move it */
10388         if (is_crtc_connector_off(set)) {
10389                 config->mode_changed = true;
10390         } else if (set->crtc->primary->fb != set->fb) {
10391                 /* If we have no fb then treat it as a full mode set */
10392                 if (set->crtc->primary->fb == NULL) {
10393                         struct intel_crtc *intel_crtc =
10394                                 to_intel_crtc(set->crtc);
10395
10396                         if (intel_crtc->active && i915.fastboot) {
10397                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10398                                 config->fb_changed = true;
10399                         } else {
10400                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10401                                 config->mode_changed = true;
10402                         }
10403                 } else if (set->fb == NULL) {
10404                         config->mode_changed = true;
10405                 } else if (set->fb->pixel_format !=
10406                            set->crtc->primary->fb->pixel_format) {
10407                         config->mode_changed = true;
10408                 } else {
10409                         config->fb_changed = true;
10410                 }
10411         }
10412
10413         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10414                 config->fb_changed = true;
10415
10416         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10417                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10418                 drm_mode_debug_printmodeline(&set->crtc->mode);
10419                 drm_mode_debug_printmodeline(set->mode);
10420                 config->mode_changed = true;
10421         }
10422
10423         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10424                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10425 }
10426
10427 static int
10428 intel_modeset_stage_output_state(struct drm_device *dev,
10429                                  struct drm_mode_set *set,
10430                                  struct intel_set_config *config)
10431 {
10432         struct intel_connector *connector;
10433         struct intel_encoder *encoder;
10434         struct intel_crtc *crtc;
10435         int ro;
10436
10437         /* The upper layers ensure that we either disable a crtc or have a list
10438          * of connectors. For paranoia, double-check this. */
10439         WARN_ON(!set->fb && (set->num_connectors != 0));
10440         WARN_ON(set->fb && (set->num_connectors == 0));
10441
10442         list_for_each_entry(connector, &dev->mode_config.connector_list,
10443                             base.head) {
10444                 /* Otherwise traverse passed in connector list and get encoders
10445                  * for them. */
10446                 for (ro = 0; ro < set->num_connectors; ro++) {
10447                         if (set->connectors[ro] == &connector->base) {
10448                                 connector->new_encoder = connector->encoder;
10449                                 break;
10450                         }
10451                 }
10452
10453                 /* If we disable the crtc, disable all its connectors. Also, if
10454                  * the connector is on the changing crtc but not on the new
10455                  * connector list, disable it. */
10456                 if ((!set->fb || ro == set->num_connectors) &&
10457                     connector->base.encoder &&
10458                     connector->base.encoder->crtc == set->crtc) {
10459                         connector->new_encoder = NULL;
10460
10461                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10462                                 connector->base.base.id,
10463                                 drm_get_connector_name(&connector->base));
10464                 }
10465
10466
10467                 if (&connector->new_encoder->base != connector->base.encoder) {
10468                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10469                         config->mode_changed = true;
10470                 }
10471         }
10472         /* connector->new_encoder is now updated for all connectors. */
10473
10474         /* Update crtc of enabled connectors. */
10475         list_for_each_entry(connector, &dev->mode_config.connector_list,
10476                             base.head) {
10477                 struct drm_crtc *new_crtc;
10478
10479                 if (!connector->new_encoder)
10480                         continue;
10481
10482                 new_crtc = connector->new_encoder->base.crtc;
10483
10484                 for (ro = 0; ro < set->num_connectors; ro++) {
10485                         if (set->connectors[ro] == &connector->base)
10486                                 new_crtc = set->crtc;
10487                 }
10488
10489                 /* Make sure the new CRTC will work with the encoder */
10490                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10491                                          new_crtc)) {
10492                         return -EINVAL;
10493                 }
10494                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10495
10496                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10497                         connector->base.base.id,
10498                         drm_get_connector_name(&connector->base),
10499                         new_crtc->base.id);
10500         }
10501
10502         /* Check for any encoders that needs to be disabled. */
10503         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10504                             base.head) {
10505                 int num_connectors = 0;
10506                 list_for_each_entry(connector,
10507                                     &dev->mode_config.connector_list,
10508                                     base.head) {
10509                         if (connector->new_encoder == encoder) {
10510                                 WARN_ON(!connector->new_encoder->new_crtc);
10511                                 num_connectors++;
10512                         }
10513                 }
10514
10515                 if (num_connectors == 0)
10516                         encoder->new_crtc = NULL;
10517                 else if (num_connectors > 1)
10518                         return -EINVAL;
10519
10520                 /* Only now check for crtc changes so we don't miss encoders
10521                  * that will be disabled. */
10522                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10523                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10524                         config->mode_changed = true;
10525                 }
10526         }
10527         /* Now we've also updated encoder->new_crtc for all encoders. */
10528
10529         for_each_intel_crtc(dev, crtc) {
10530                 crtc->new_enabled = false;
10531
10532                 list_for_each_entry(encoder,
10533                                     &dev->mode_config.encoder_list,
10534                                     base.head) {
10535                         if (encoder->new_crtc == crtc) {
10536                                 crtc->new_enabled = true;
10537                                 break;
10538                         }
10539                 }
10540
10541                 if (crtc->new_enabled != crtc->base.enabled) {
10542                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10543                                       crtc->new_enabled ? "en" : "dis");
10544                         config->mode_changed = true;
10545                 }
10546
10547                 if (crtc->new_enabled)
10548                         crtc->new_config = &crtc->config;
10549                 else
10550                         crtc->new_config = NULL;
10551         }
10552
10553         return 0;
10554 }
10555
10556 static void disable_crtc_nofb(struct intel_crtc *crtc)
10557 {
10558         struct drm_device *dev = crtc->base.dev;
10559         struct intel_encoder *encoder;
10560         struct intel_connector *connector;
10561
10562         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10563                       pipe_name(crtc->pipe));
10564
10565         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10566                 if (connector->new_encoder &&
10567                     connector->new_encoder->new_crtc == crtc)
10568                         connector->new_encoder = NULL;
10569         }
10570
10571         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10572                 if (encoder->new_crtc == crtc)
10573                         encoder->new_crtc = NULL;
10574         }
10575
10576         crtc->new_enabled = false;
10577         crtc->new_config = NULL;
10578 }
10579
10580 static int intel_crtc_set_config(struct drm_mode_set *set)
10581 {
10582         struct drm_device *dev;
10583         struct drm_mode_set save_set;
10584         struct intel_set_config *config;
10585         int ret;
10586
10587         BUG_ON(!set);
10588         BUG_ON(!set->crtc);
10589         BUG_ON(!set->crtc->helper_private);
10590
10591         /* Enforce sane interface api - has been abused by the fb helper. */
10592         BUG_ON(!set->mode && set->fb);
10593         BUG_ON(set->fb && set->num_connectors == 0);
10594
10595         if (set->fb) {
10596                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10597                                 set->crtc->base.id, set->fb->base.id,
10598                                 (int)set->num_connectors, set->x, set->y);
10599         } else {
10600                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10601         }
10602
10603         dev = set->crtc->dev;
10604
10605         ret = -ENOMEM;
10606         config = kzalloc(sizeof(*config), GFP_KERNEL);
10607         if (!config)
10608                 goto out_config;
10609
10610         ret = intel_set_config_save_state(dev, config);
10611         if (ret)
10612                 goto out_config;
10613
10614         save_set.crtc = set->crtc;
10615         save_set.mode = &set->crtc->mode;
10616         save_set.x = set->crtc->x;
10617         save_set.y = set->crtc->y;
10618         save_set.fb = set->crtc->primary->fb;
10619
10620         /* Compute whether we need a full modeset, only an fb base update or no
10621          * change at all. In the future we might also check whether only the
10622          * mode changed, e.g. for LVDS where we only change the panel fitter in
10623          * such cases. */
10624         intel_set_config_compute_mode_changes(set, config);
10625
10626         ret = intel_modeset_stage_output_state(dev, set, config);
10627         if (ret)
10628                 goto fail;
10629
10630         if (config->mode_changed) {
10631                 ret = intel_set_mode(set->crtc, set->mode,
10632                                      set->x, set->y, set->fb);
10633         } else if (config->fb_changed) {
10634                 intel_crtc_wait_for_pending_flips(set->crtc);
10635
10636                 ret = intel_pipe_set_base(set->crtc,
10637                                           set->x, set->y, set->fb);
10638                 /*
10639                  * In the fastboot case this may be our only check of the
10640                  * state after boot.  It would be better to only do it on
10641                  * the first update, but we don't have a nice way of doing that
10642                  * (and really, set_config isn't used much for high freq page
10643                  * flipping, so increasing its cost here shouldn't be a big
10644                  * deal).
10645                  */
10646                 if (i915.fastboot && ret == 0)
10647                         intel_modeset_check_state(set->crtc->dev);
10648         }
10649
10650         if (ret) {
10651                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10652                               set->crtc->base.id, ret);
10653 fail:
10654                 intel_set_config_restore_state(dev, config);
10655
10656                 /*
10657                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10658                  * force the pipe off to avoid oopsing in the modeset code
10659                  * due to fb==NULL. This should only happen during boot since
10660                  * we don't yet reconstruct the FB from the hardware state.
10661                  */
10662                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10663                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10664
10665                 /* Try to restore the config */
10666                 if (config->mode_changed &&
10667                     intel_set_mode(save_set.crtc, save_set.mode,
10668                                    save_set.x, save_set.y, save_set.fb))
10669                         DRM_ERROR("failed to restore config after modeset failure\n");
10670         }
10671
10672 out_config:
10673         intel_set_config_free(config);
10674         return ret;
10675 }
10676
10677 static const struct drm_crtc_funcs intel_crtc_funcs = {
10678         .cursor_set = intel_crtc_cursor_set,
10679         .cursor_move = intel_crtc_cursor_move,
10680         .gamma_set = intel_crtc_gamma_set,
10681         .set_config = intel_crtc_set_config,
10682         .destroy = intel_crtc_destroy,
10683         .page_flip = intel_crtc_page_flip,
10684 };
10685
10686 static void intel_cpu_pll_init(struct drm_device *dev)
10687 {
10688         if (HAS_DDI(dev))
10689                 intel_ddi_pll_init(dev);
10690 }
10691
10692 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10693                                       struct intel_shared_dpll *pll,
10694                                       struct intel_dpll_hw_state *hw_state)
10695 {
10696         uint32_t val;
10697
10698         val = I915_READ(PCH_DPLL(pll->id));
10699         hw_state->dpll = val;
10700         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10701         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10702
10703         return val & DPLL_VCO_ENABLE;
10704 }
10705
10706 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10707                                   struct intel_shared_dpll *pll)
10708 {
10709         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10710         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10711 }
10712
10713 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10714                                 struct intel_shared_dpll *pll)
10715 {
10716         /* PCH refclock must be enabled first */
10717         ibx_assert_pch_refclk_enabled(dev_priv);
10718
10719         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10720
10721         /* Wait for the clocks to stabilize. */
10722         POSTING_READ(PCH_DPLL(pll->id));
10723         udelay(150);
10724
10725         /* The pixel multiplier can only be updated once the
10726          * DPLL is enabled and the clocks are stable.
10727          *
10728          * So write it again.
10729          */
10730         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10731         POSTING_READ(PCH_DPLL(pll->id));
10732         udelay(200);
10733 }
10734
10735 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10736                                  struct intel_shared_dpll *pll)
10737 {
10738         struct drm_device *dev = dev_priv->dev;
10739         struct intel_crtc *crtc;
10740
10741         /* Make sure no transcoder isn't still depending on us. */
10742         for_each_intel_crtc(dev, crtc) {
10743                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10744                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10745         }
10746
10747         I915_WRITE(PCH_DPLL(pll->id), 0);
10748         POSTING_READ(PCH_DPLL(pll->id));
10749         udelay(200);
10750 }
10751
10752 static char *ibx_pch_dpll_names[] = {
10753         "PCH DPLL A",
10754         "PCH DPLL B",
10755 };
10756
10757 static void ibx_pch_dpll_init(struct drm_device *dev)
10758 {
10759         struct drm_i915_private *dev_priv = dev->dev_private;
10760         int i;
10761
10762         dev_priv->num_shared_dpll = 2;
10763
10764         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10765                 dev_priv->shared_dplls[i].id = i;
10766                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10767                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10768                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10769                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10770                 dev_priv->shared_dplls[i].get_hw_state =
10771                         ibx_pch_dpll_get_hw_state;
10772         }
10773 }
10774
10775 static void intel_shared_dpll_init(struct drm_device *dev)
10776 {
10777         struct drm_i915_private *dev_priv = dev->dev_private;
10778
10779         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10780                 ibx_pch_dpll_init(dev);
10781         else
10782                 dev_priv->num_shared_dpll = 0;
10783
10784         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10785 }
10786
10787 static void intel_crtc_init(struct drm_device *dev, int pipe)
10788 {
10789         struct drm_i915_private *dev_priv = dev->dev_private;
10790         struct intel_crtc *intel_crtc;
10791         int i;
10792
10793         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10794         if (intel_crtc == NULL)
10795                 return;
10796
10797         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10798
10799         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10800         for (i = 0; i < 256; i++) {
10801                 intel_crtc->lut_r[i] = i;
10802                 intel_crtc->lut_g[i] = i;
10803                 intel_crtc->lut_b[i] = i;
10804         }
10805
10806         /*
10807          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10808          * is hooked to plane B. Hence we want plane A feeding pipe B.
10809          */
10810         intel_crtc->pipe = pipe;
10811         intel_crtc->plane = pipe;
10812         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10813                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10814                 intel_crtc->plane = !pipe;
10815         }
10816
10817         init_waitqueue_head(&intel_crtc->vbl_wait);
10818
10819         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10820                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10821         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10822         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10823
10824         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10825 }
10826
10827 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10828 {
10829         struct drm_encoder *encoder = connector->base.encoder;
10830
10831         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10832
10833         if (!encoder)
10834                 return INVALID_PIPE;
10835
10836         return to_intel_crtc(encoder->crtc)->pipe;
10837 }
10838
10839 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10840                                 struct drm_file *file)
10841 {
10842         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10843         struct drm_mode_object *drmmode_obj;
10844         struct intel_crtc *crtc;
10845
10846         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10847                 return -ENODEV;
10848
10849         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10850                         DRM_MODE_OBJECT_CRTC);
10851
10852         if (!drmmode_obj) {
10853                 DRM_ERROR("no such CRTC id\n");
10854                 return -ENOENT;
10855         }
10856
10857         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10858         pipe_from_crtc_id->pipe = crtc->pipe;
10859
10860         return 0;
10861 }
10862
10863 static int intel_encoder_clones(struct intel_encoder *encoder)
10864 {
10865         struct drm_device *dev = encoder->base.dev;
10866         struct intel_encoder *source_encoder;
10867         int index_mask = 0;
10868         int entry = 0;
10869
10870         list_for_each_entry(source_encoder,
10871                             &dev->mode_config.encoder_list, base.head) {
10872                 if (encoders_cloneable(encoder, source_encoder))
10873                         index_mask |= (1 << entry);
10874
10875                 entry++;
10876         }
10877
10878         return index_mask;
10879 }
10880
10881 static bool has_edp_a(struct drm_device *dev)
10882 {
10883         struct drm_i915_private *dev_priv = dev->dev_private;
10884
10885         if (!IS_MOBILE(dev))
10886                 return false;
10887
10888         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10889                 return false;
10890
10891         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10892                 return false;
10893
10894         return true;
10895 }
10896
10897 const char *intel_output_name(int output)
10898 {
10899         static const char *names[] = {
10900                 [INTEL_OUTPUT_UNUSED] = "Unused",
10901                 [INTEL_OUTPUT_ANALOG] = "Analog",
10902                 [INTEL_OUTPUT_DVO] = "DVO",
10903                 [INTEL_OUTPUT_SDVO] = "SDVO",
10904                 [INTEL_OUTPUT_LVDS] = "LVDS",
10905                 [INTEL_OUTPUT_TVOUT] = "TV",
10906                 [INTEL_OUTPUT_HDMI] = "HDMI",
10907                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10908                 [INTEL_OUTPUT_EDP] = "eDP",
10909                 [INTEL_OUTPUT_DSI] = "DSI",
10910                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10911         };
10912
10913         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10914                 return "Invalid";
10915
10916         return names[output];
10917 }
10918
10919 static void intel_setup_outputs(struct drm_device *dev)
10920 {
10921         struct drm_i915_private *dev_priv = dev->dev_private;
10922         struct intel_encoder *encoder;
10923         bool dpd_is_edp = false;
10924
10925         intel_lvds_init(dev);
10926
10927         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10928                 intel_crt_init(dev);
10929
10930         if (HAS_DDI(dev)) {
10931                 int found;
10932
10933                 /* Haswell uses DDI functions to detect digital outputs */
10934                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10935                 /* DDI A only supports eDP */
10936                 if (found)
10937                         intel_ddi_init(dev, PORT_A);
10938
10939                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10940                  * register */
10941                 found = I915_READ(SFUSE_STRAP);
10942
10943                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10944                         intel_ddi_init(dev, PORT_B);
10945                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10946                         intel_ddi_init(dev, PORT_C);
10947                 if (found & SFUSE_STRAP_DDID_DETECTED)
10948                         intel_ddi_init(dev, PORT_D);
10949         } else if (HAS_PCH_SPLIT(dev)) {
10950                 int found;
10951                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10952
10953                 if (has_edp_a(dev))
10954                         intel_dp_init(dev, DP_A, PORT_A);
10955
10956                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10957                         /* PCH SDVOB multiplex with HDMIB */
10958                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10959                         if (!found)
10960                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10961                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10962                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10963                 }
10964
10965                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10966                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10967
10968                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10969                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10970
10971                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10972                         intel_dp_init(dev, PCH_DP_C, PORT_C);
10973
10974                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10975                         intel_dp_init(dev, PCH_DP_D, PORT_D);
10976         } else if (IS_VALLEYVIEW(dev)) {
10977                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10978                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10979                                         PORT_B);
10980                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10981                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10982                 }
10983
10984                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10985                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10986                                         PORT_C);
10987                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10988                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10989                 }
10990
10991                 intel_dsi_init(dev);
10992         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10993                 bool found = false;
10994
10995                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10996                         DRM_DEBUG_KMS("probing SDVOB\n");
10997                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10998                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10999                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11000                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11001                         }
11002
11003                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11004                                 intel_dp_init(dev, DP_B, PORT_B);
11005                 }
11006
11007                 /* Before G4X SDVOC doesn't have its own detect register */
11008
11009                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11010                         DRM_DEBUG_KMS("probing SDVOC\n");
11011                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11012                 }
11013
11014                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11015
11016                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11017                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11018                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11019                         }
11020                         if (SUPPORTS_INTEGRATED_DP(dev))
11021                                 intel_dp_init(dev, DP_C, PORT_C);
11022                 }
11023
11024                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11025                     (I915_READ(DP_D) & DP_DETECTED))
11026                         intel_dp_init(dev, DP_D, PORT_D);
11027         } else if (IS_GEN2(dev))
11028                 intel_dvo_init(dev);
11029
11030         if (SUPPORTS_TV(dev))
11031                 intel_tv_init(dev);
11032
11033         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11034                 encoder->base.possible_crtcs = encoder->crtc_mask;
11035                 encoder->base.possible_clones =
11036                         intel_encoder_clones(encoder);
11037         }
11038
11039         intel_init_pch_refclk(dev);
11040
11041         drm_helper_move_panel_connectors_to_head(dev);
11042 }
11043
11044 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11045 {
11046         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11047
11048         drm_framebuffer_cleanup(fb);
11049         WARN_ON(!intel_fb->obj->framebuffer_references--);
11050         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11051         kfree(intel_fb);
11052 }
11053
11054 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11055                                                 struct drm_file *file,
11056                                                 unsigned int *handle)
11057 {
11058         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11059         struct drm_i915_gem_object *obj = intel_fb->obj;
11060
11061         return drm_gem_handle_create(file, &obj->base, handle);
11062 }
11063
11064 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11065         .destroy = intel_user_framebuffer_destroy,
11066         .create_handle = intel_user_framebuffer_create_handle,
11067 };
11068
11069 static int intel_framebuffer_init(struct drm_device *dev,
11070                                   struct intel_framebuffer *intel_fb,
11071                                   struct drm_mode_fb_cmd2 *mode_cmd,
11072                                   struct drm_i915_gem_object *obj)
11073 {
11074         int aligned_height;
11075         int pitch_limit;
11076         int ret;
11077
11078         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11079
11080         if (obj->tiling_mode == I915_TILING_Y) {
11081                 DRM_DEBUG("hardware does not support tiling Y\n");
11082                 return -EINVAL;
11083         }
11084
11085         if (mode_cmd->pitches[0] & 63) {
11086                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11087                           mode_cmd->pitches[0]);
11088                 return -EINVAL;
11089         }
11090
11091         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11092                 pitch_limit = 32*1024;
11093         } else if (INTEL_INFO(dev)->gen >= 4) {
11094                 if (obj->tiling_mode)
11095                         pitch_limit = 16*1024;
11096                 else
11097                         pitch_limit = 32*1024;
11098         } else if (INTEL_INFO(dev)->gen >= 3) {
11099                 if (obj->tiling_mode)
11100                         pitch_limit = 8*1024;
11101                 else
11102                         pitch_limit = 16*1024;
11103         } else
11104                 /* XXX DSPC is limited to 4k tiled */
11105                 pitch_limit = 8*1024;
11106
11107         if (mode_cmd->pitches[0] > pitch_limit) {
11108                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11109                           obj->tiling_mode ? "tiled" : "linear",
11110                           mode_cmd->pitches[0], pitch_limit);
11111                 return -EINVAL;
11112         }
11113
11114         if (obj->tiling_mode != I915_TILING_NONE &&
11115             mode_cmd->pitches[0] != obj->stride) {
11116                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11117                           mode_cmd->pitches[0], obj->stride);
11118                 return -EINVAL;
11119         }
11120
11121         /* Reject formats not supported by any plane early. */
11122         switch (mode_cmd->pixel_format) {
11123         case DRM_FORMAT_C8:
11124         case DRM_FORMAT_RGB565:
11125         case DRM_FORMAT_XRGB8888:
11126         case DRM_FORMAT_ARGB8888:
11127                 break;
11128         case DRM_FORMAT_XRGB1555:
11129         case DRM_FORMAT_ARGB1555:
11130                 if (INTEL_INFO(dev)->gen > 3) {
11131                         DRM_DEBUG("unsupported pixel format: %s\n",
11132                                   drm_get_format_name(mode_cmd->pixel_format));
11133                         return -EINVAL;
11134                 }
11135                 break;
11136         case DRM_FORMAT_XBGR8888:
11137         case DRM_FORMAT_ABGR8888:
11138         case DRM_FORMAT_XRGB2101010:
11139         case DRM_FORMAT_ARGB2101010:
11140         case DRM_FORMAT_XBGR2101010:
11141         case DRM_FORMAT_ABGR2101010:
11142                 if (INTEL_INFO(dev)->gen < 4) {
11143                         DRM_DEBUG("unsupported pixel format: %s\n",
11144                                   drm_get_format_name(mode_cmd->pixel_format));
11145                         return -EINVAL;
11146                 }
11147                 break;
11148         case DRM_FORMAT_YUYV:
11149         case DRM_FORMAT_UYVY:
11150         case DRM_FORMAT_YVYU:
11151         case DRM_FORMAT_VYUY:
11152                 if (INTEL_INFO(dev)->gen < 5) {
11153                         DRM_DEBUG("unsupported pixel format: %s\n",
11154                                   drm_get_format_name(mode_cmd->pixel_format));
11155                         return -EINVAL;
11156                 }
11157                 break;
11158         default:
11159                 DRM_DEBUG("unsupported pixel format: %s\n",
11160                           drm_get_format_name(mode_cmd->pixel_format));
11161                 return -EINVAL;
11162         }
11163
11164         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11165         if (mode_cmd->offsets[0] != 0)
11166                 return -EINVAL;
11167
11168         aligned_height = intel_align_height(dev, mode_cmd->height,
11169                                             obj->tiling_mode);
11170         /* FIXME drm helper for size checks (especially planar formats)? */
11171         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11172                 return -EINVAL;
11173
11174         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11175         intel_fb->obj = obj;
11176         intel_fb->obj->framebuffer_references++;
11177
11178         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11179         if (ret) {
11180                 DRM_ERROR("framebuffer init failed %d\n", ret);
11181                 return ret;
11182         }
11183
11184         return 0;
11185 }
11186
11187 static struct drm_framebuffer *
11188 intel_user_framebuffer_create(struct drm_device *dev,
11189                               struct drm_file *filp,
11190                               struct drm_mode_fb_cmd2 *mode_cmd)
11191 {
11192         struct drm_i915_gem_object *obj;
11193
11194         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11195                                                 mode_cmd->handles[0]));
11196         if (&obj->base == NULL)
11197                 return ERR_PTR(-ENOENT);
11198
11199         return intel_framebuffer_create(dev, mode_cmd, obj);
11200 }
11201
11202 #ifndef CONFIG_DRM_I915_FBDEV
11203 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11204 {
11205 }
11206 #endif
11207
11208 static const struct drm_mode_config_funcs intel_mode_funcs = {
11209         .fb_create = intel_user_framebuffer_create,
11210         .output_poll_changed = intel_fbdev_output_poll_changed,
11211 };
11212
11213 /* Set up chip specific display functions */
11214 static void intel_init_display(struct drm_device *dev)
11215 {
11216         struct drm_i915_private *dev_priv = dev->dev_private;
11217
11218         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11219                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11220         else if (IS_CHERRYVIEW(dev))
11221                 dev_priv->display.find_dpll = chv_find_best_dpll;
11222         else if (IS_VALLEYVIEW(dev))
11223                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11224         else if (IS_PINEVIEW(dev))
11225                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11226         else
11227                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11228
11229         if (HAS_DDI(dev)) {
11230                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11231                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11232                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11233                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11234                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11235                 dev_priv->display.off = haswell_crtc_off;
11236                 dev_priv->display.update_primary_plane =
11237                         ironlake_update_primary_plane;
11238         } else if (HAS_PCH_SPLIT(dev)) {
11239                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11240                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11241                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11242                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11243                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11244                 dev_priv->display.off = ironlake_crtc_off;
11245                 dev_priv->display.update_primary_plane =
11246                         ironlake_update_primary_plane;
11247         } else if (IS_VALLEYVIEW(dev)) {
11248                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11249                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11250                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11251                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11252                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11253                 dev_priv->display.off = i9xx_crtc_off;
11254                 dev_priv->display.update_primary_plane =
11255                         i9xx_update_primary_plane;
11256         } else {
11257                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11258                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11259                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11260                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11261                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11262                 dev_priv->display.off = i9xx_crtc_off;
11263                 dev_priv->display.update_primary_plane =
11264                         i9xx_update_primary_plane;
11265         }
11266
11267         /* Returns the core display clock speed */
11268         if (IS_VALLEYVIEW(dev))
11269                 dev_priv->display.get_display_clock_speed =
11270                         valleyview_get_display_clock_speed;
11271         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11272                 dev_priv->display.get_display_clock_speed =
11273                         i945_get_display_clock_speed;
11274         else if (IS_I915G(dev))
11275                 dev_priv->display.get_display_clock_speed =
11276                         i915_get_display_clock_speed;
11277         else if (IS_I945GM(dev) || IS_845G(dev))
11278                 dev_priv->display.get_display_clock_speed =
11279                         i9xx_misc_get_display_clock_speed;
11280         else if (IS_PINEVIEW(dev))
11281                 dev_priv->display.get_display_clock_speed =
11282                         pnv_get_display_clock_speed;
11283         else if (IS_I915GM(dev))
11284                 dev_priv->display.get_display_clock_speed =
11285                         i915gm_get_display_clock_speed;
11286         else if (IS_I865G(dev))
11287                 dev_priv->display.get_display_clock_speed =
11288                         i865_get_display_clock_speed;
11289         else if (IS_I85X(dev))
11290                 dev_priv->display.get_display_clock_speed =
11291                         i855_get_display_clock_speed;
11292         else /* 852, 830 */
11293                 dev_priv->display.get_display_clock_speed =
11294                         i830_get_display_clock_speed;
11295
11296         if (HAS_PCH_SPLIT(dev)) {
11297                 if (IS_GEN5(dev)) {
11298                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11299                         dev_priv->display.write_eld = ironlake_write_eld;
11300                 } else if (IS_GEN6(dev)) {
11301                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11302                         dev_priv->display.write_eld = ironlake_write_eld;
11303                         dev_priv->display.modeset_global_resources =
11304                                 snb_modeset_global_resources;
11305                 } else if (IS_IVYBRIDGE(dev)) {
11306                         /* FIXME: detect B0+ stepping and use auto training */
11307                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11308                         dev_priv->display.write_eld = ironlake_write_eld;
11309                         dev_priv->display.modeset_global_resources =
11310                                 ivb_modeset_global_resources;
11311                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11312                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11313                         dev_priv->display.write_eld = haswell_write_eld;
11314                         dev_priv->display.modeset_global_resources =
11315                                 haswell_modeset_global_resources;
11316                 }
11317         } else if (IS_G4X(dev)) {
11318                 dev_priv->display.write_eld = g4x_write_eld;
11319         } else if (IS_VALLEYVIEW(dev)) {
11320                 dev_priv->display.modeset_global_resources =
11321                         valleyview_modeset_global_resources;
11322                 dev_priv->display.write_eld = ironlake_write_eld;
11323         }
11324
11325         /* Default just returns -ENODEV to indicate unsupported */
11326         dev_priv->display.queue_flip = intel_default_queue_flip;
11327
11328         switch (INTEL_INFO(dev)->gen) {
11329         case 2:
11330                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11331                 break;
11332
11333         case 3:
11334                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11335                 break;
11336
11337         case 4:
11338         case 5:
11339                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11340                 break;
11341
11342         case 6:
11343                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11344                 break;
11345         case 7:
11346         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11347                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11348                 break;
11349         }
11350
11351         intel_panel_init_backlight_funcs(dev);
11352 }
11353
11354 /*
11355  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11356  * resume, or other times.  This quirk makes sure that's the case for
11357  * affected systems.
11358  */
11359 static void quirk_pipea_force(struct drm_device *dev)
11360 {
11361         struct drm_i915_private *dev_priv = dev->dev_private;
11362
11363         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11364         DRM_INFO("applying pipe a force quirk\n");
11365 }
11366
11367 /*
11368  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11369  */
11370 static void quirk_ssc_force_disable(struct drm_device *dev)
11371 {
11372         struct drm_i915_private *dev_priv = dev->dev_private;
11373         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11374         DRM_INFO("applying lvds SSC disable quirk\n");
11375 }
11376
11377 /*
11378  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11379  * brightness value
11380  */
11381 static void quirk_invert_brightness(struct drm_device *dev)
11382 {
11383         struct drm_i915_private *dev_priv = dev->dev_private;
11384         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11385         DRM_INFO("applying inverted panel brightness quirk\n");
11386 }
11387
11388 struct intel_quirk {
11389         int device;
11390         int subsystem_vendor;
11391         int subsystem_device;
11392         void (*hook)(struct drm_device *dev);
11393 };
11394
11395 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11396 struct intel_dmi_quirk {
11397         void (*hook)(struct drm_device *dev);
11398         const struct dmi_system_id (*dmi_id_list)[];
11399 };
11400
11401 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11402 {
11403         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11404         return 1;
11405 }
11406
11407 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11408         {
11409                 .dmi_id_list = &(const struct dmi_system_id[]) {
11410                         {
11411                                 .callback = intel_dmi_reverse_brightness,
11412                                 .ident = "NCR Corporation",
11413                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11414                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11415                                 },
11416                         },
11417                         { }  /* terminating entry */
11418                 },
11419                 .hook = quirk_invert_brightness,
11420         },
11421 };
11422
11423 static struct intel_quirk intel_quirks[] = {
11424         /* HP Mini needs pipe A force quirk (LP: #322104) */
11425         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11426
11427         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11428         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11429
11430         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11431         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11432
11433         /* 830 needs to leave pipe A & dpll A up */
11434         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11435
11436         /* Lenovo U160 cannot use SSC on LVDS */
11437         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11438
11439         /* Sony Vaio Y cannot use SSC on LVDS */
11440         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11441
11442         /* Acer Aspire 5734Z must invert backlight brightness */
11443         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11444
11445         /* Acer/eMachines G725 */
11446         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11447
11448         /* Acer/eMachines e725 */
11449         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11450
11451         /* Acer/Packard Bell NCL20 */
11452         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11453
11454         /* Acer Aspire 4736Z */
11455         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11456
11457         /* Acer Aspire 5336 */
11458         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11459 };
11460
11461 static void intel_init_quirks(struct drm_device *dev)
11462 {
11463         struct pci_dev *d = dev->pdev;
11464         int i;
11465
11466         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11467                 struct intel_quirk *q = &intel_quirks[i];
11468
11469                 if (d->device == q->device &&
11470                     (d->subsystem_vendor == q->subsystem_vendor ||
11471                      q->subsystem_vendor == PCI_ANY_ID) &&
11472                     (d->subsystem_device == q->subsystem_device ||
11473                      q->subsystem_device == PCI_ANY_ID))
11474                         q->hook(dev);
11475         }
11476         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11477                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11478                         intel_dmi_quirks[i].hook(dev);
11479         }
11480 }
11481
11482 /* Disable the VGA plane that we never use */
11483 static void i915_disable_vga(struct drm_device *dev)
11484 {
11485         struct drm_i915_private *dev_priv = dev->dev_private;
11486         u8 sr1;
11487         u32 vga_reg = i915_vgacntrl_reg(dev);
11488
11489         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11490         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11491         outb(SR01, VGA_SR_INDEX);
11492         sr1 = inb(VGA_SR_DATA);
11493         outb(sr1 | 1<<5, VGA_SR_DATA);
11494         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11495         udelay(300);
11496
11497         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11498         POSTING_READ(vga_reg);
11499 }
11500
11501 void intel_modeset_init_hw(struct drm_device *dev)
11502 {
11503         intel_prepare_ddi(dev);
11504
11505         intel_init_clock_gating(dev);
11506
11507         intel_reset_dpio(dev);
11508
11509         intel_enable_gt_powersave(dev);
11510 }
11511
11512 void intel_modeset_suspend_hw(struct drm_device *dev)
11513 {
11514         intel_suspend_hw(dev);
11515 }
11516
11517 void intel_modeset_init(struct drm_device *dev)
11518 {
11519         struct drm_i915_private *dev_priv = dev->dev_private;
11520         int sprite, ret;
11521         enum pipe pipe;
11522         struct intel_crtc *crtc;
11523
11524         drm_mode_config_init(dev);
11525
11526         dev->mode_config.min_width = 0;
11527         dev->mode_config.min_height = 0;
11528
11529         dev->mode_config.preferred_depth = 24;
11530         dev->mode_config.prefer_shadow = 1;
11531
11532         dev->mode_config.funcs = &intel_mode_funcs;
11533
11534         intel_init_quirks(dev);
11535
11536         intel_init_pm(dev);
11537
11538         if (INTEL_INFO(dev)->num_pipes == 0)
11539                 return;
11540
11541         intel_init_display(dev);
11542
11543         if (IS_GEN2(dev)) {
11544                 dev->mode_config.max_width = 2048;
11545                 dev->mode_config.max_height = 2048;
11546         } else if (IS_GEN3(dev)) {
11547                 dev->mode_config.max_width = 4096;
11548                 dev->mode_config.max_height = 4096;
11549         } else {
11550                 dev->mode_config.max_width = 8192;
11551                 dev->mode_config.max_height = 8192;
11552         }
11553
11554         if (IS_GEN2(dev)) {
11555                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11556                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11557         } else {
11558                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11559                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11560         }
11561
11562         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11563
11564         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11565                       INTEL_INFO(dev)->num_pipes,
11566                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11567
11568         for_each_pipe(pipe) {
11569                 intel_crtc_init(dev, pipe);
11570                 for_each_sprite(pipe, sprite) {
11571                         ret = intel_plane_init(dev, pipe, sprite);
11572                         if (ret)
11573                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11574                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11575                 }
11576         }
11577
11578         intel_init_dpio(dev);
11579         intel_reset_dpio(dev);
11580
11581         intel_cpu_pll_init(dev);
11582         intel_shared_dpll_init(dev);
11583
11584         /* Just disable it once at startup */
11585         i915_disable_vga(dev);
11586         intel_setup_outputs(dev);
11587
11588         /* Just in case the BIOS is doing something questionable. */
11589         intel_disable_fbc(dev);
11590
11591         mutex_lock(&dev->mode_config.mutex);
11592         intel_modeset_setup_hw_state(dev, false);
11593         mutex_unlock(&dev->mode_config.mutex);
11594
11595         for_each_intel_crtc(dev, crtc) {
11596                 if (!crtc->active)
11597                         continue;
11598
11599                 /*
11600                  * Note that reserving the BIOS fb up front prevents us
11601                  * from stuffing other stolen allocations like the ring
11602                  * on top.  This prevents some ugliness at boot time, and
11603                  * can even allow for smooth boot transitions if the BIOS
11604                  * fb is large enough for the active pipe configuration.
11605                  */
11606                 if (dev_priv->display.get_plane_config) {
11607                         dev_priv->display.get_plane_config(crtc,
11608                                                            &crtc->plane_config);
11609                         /*
11610                          * If the fb is shared between multiple heads, we'll
11611                          * just get the first one.
11612                          */
11613                         intel_find_plane_obj(crtc, &crtc->plane_config);
11614                 }
11615         }
11616 }
11617
11618 static void
11619 intel_connector_break_all_links(struct intel_connector *connector)
11620 {
11621         connector->base.dpms = DRM_MODE_DPMS_OFF;
11622         connector->base.encoder = NULL;
11623         connector->encoder->connectors_active = false;
11624         connector->encoder->base.crtc = NULL;
11625 }
11626
11627 static void intel_enable_pipe_a(struct drm_device *dev)
11628 {
11629         struct intel_connector *connector;
11630         struct drm_connector *crt = NULL;
11631         struct intel_load_detect_pipe load_detect_temp;
11632
11633         /* We can't just switch on the pipe A, we need to set things up with a
11634          * proper mode and output configuration. As a gross hack, enable pipe A
11635          * by enabling the load detect pipe once. */
11636         list_for_each_entry(connector,
11637                             &dev->mode_config.connector_list,
11638                             base.head) {
11639                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11640                         crt = &connector->base;
11641                         break;
11642                 }
11643         }
11644
11645         if (!crt)
11646                 return;
11647
11648         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11649                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11650
11651
11652 }
11653
11654 static bool
11655 intel_check_plane_mapping(struct intel_crtc *crtc)
11656 {
11657         struct drm_device *dev = crtc->base.dev;
11658         struct drm_i915_private *dev_priv = dev->dev_private;
11659         u32 reg, val;
11660
11661         if (INTEL_INFO(dev)->num_pipes == 1)
11662                 return true;
11663
11664         reg = DSPCNTR(!crtc->plane);
11665         val = I915_READ(reg);
11666
11667         if ((val & DISPLAY_PLANE_ENABLE) &&
11668             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11669                 return false;
11670
11671         return true;
11672 }
11673
11674 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11675 {
11676         struct drm_device *dev = crtc->base.dev;
11677         struct drm_i915_private *dev_priv = dev->dev_private;
11678         u32 reg;
11679
11680         /* Clear any frame start delays used for debugging left by the BIOS */
11681         reg = PIPECONF(crtc->config.cpu_transcoder);
11682         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11683
11684         /* We need to sanitize the plane -> pipe mapping first because this will
11685          * disable the crtc (and hence change the state) if it is wrong. Note
11686          * that gen4+ has a fixed plane -> pipe mapping.  */
11687         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11688                 struct intel_connector *connector;
11689                 bool plane;
11690
11691                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11692                               crtc->base.base.id);
11693
11694                 /* Pipe has the wrong plane attached and the plane is active.
11695                  * Temporarily change the plane mapping and disable everything
11696                  * ...  */
11697                 plane = crtc->plane;
11698                 crtc->plane = !plane;
11699                 dev_priv->display.crtc_disable(&crtc->base);
11700                 crtc->plane = plane;
11701
11702                 /* ... and break all links. */
11703                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11704                                     base.head) {
11705                         if (connector->encoder->base.crtc != &crtc->base)
11706                                 continue;
11707
11708                         intel_connector_break_all_links(connector);
11709                 }
11710
11711                 WARN_ON(crtc->active);
11712                 crtc->base.enabled = false;
11713         }
11714
11715         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11716             crtc->pipe == PIPE_A && !crtc->active) {
11717                 /* BIOS forgot to enable pipe A, this mostly happens after
11718                  * resume. Force-enable the pipe to fix this, the update_dpms
11719                  * call below we restore the pipe to the right state, but leave
11720                  * the required bits on. */
11721                 intel_enable_pipe_a(dev);
11722         }
11723
11724         /* Adjust the state of the output pipe according to whether we
11725          * have active connectors/encoders. */
11726         intel_crtc_update_dpms(&crtc->base);
11727
11728         if (crtc->active != crtc->base.enabled) {
11729                 struct intel_encoder *encoder;
11730
11731                 /* This can happen either due to bugs in the get_hw_state
11732                  * functions or because the pipe is force-enabled due to the
11733                  * pipe A quirk. */
11734                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11735                               crtc->base.base.id,
11736                               crtc->base.enabled ? "enabled" : "disabled",
11737                               crtc->active ? "enabled" : "disabled");
11738
11739                 crtc->base.enabled = crtc->active;
11740
11741                 /* Because we only establish the connector -> encoder ->
11742                  * crtc links if something is active, this means the
11743                  * crtc is now deactivated. Break the links. connector
11744                  * -> encoder links are only establish when things are
11745                  *  actually up, hence no need to break them. */
11746                 WARN_ON(crtc->active);
11747
11748                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11749                         WARN_ON(encoder->connectors_active);
11750                         encoder->base.crtc = NULL;
11751                 }
11752         }
11753         if (crtc->active) {
11754                 /*
11755                  * We start out with underrun reporting disabled to avoid races.
11756                  * For correct bookkeeping mark this on active crtcs.
11757                  *
11758                  * No protection against concurrent access is required - at
11759                  * worst a fifo underrun happens which also sets this to false.
11760                  */
11761                 crtc->cpu_fifo_underrun_disabled = true;
11762                 crtc->pch_fifo_underrun_disabled = true;
11763         }
11764 }
11765
11766 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11767 {
11768         struct intel_connector *connector;
11769         struct drm_device *dev = encoder->base.dev;
11770
11771         /* We need to check both for a crtc link (meaning that the
11772          * encoder is active and trying to read from a pipe) and the
11773          * pipe itself being active. */
11774         bool has_active_crtc = encoder->base.crtc &&
11775                 to_intel_crtc(encoder->base.crtc)->active;
11776
11777         if (encoder->connectors_active && !has_active_crtc) {
11778                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11779                               encoder->base.base.id,
11780                               drm_get_encoder_name(&encoder->base));
11781
11782                 /* Connector is active, but has no active pipe. This is
11783                  * fallout from our resume register restoring. Disable
11784                  * the encoder manually again. */
11785                 if (encoder->base.crtc) {
11786                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11787                                       encoder->base.base.id,
11788                                       drm_get_encoder_name(&encoder->base));
11789                         encoder->disable(encoder);
11790                 }
11791
11792                 /* Inconsistent output/port/pipe state happens presumably due to
11793                  * a bug in one of the get_hw_state functions. Or someplace else
11794                  * in our code, like the register restore mess on resume. Clamp
11795                  * things to off as a safer default. */
11796                 list_for_each_entry(connector,
11797                                     &dev->mode_config.connector_list,
11798                                     base.head) {
11799                         if (connector->encoder != encoder)
11800                                 continue;
11801
11802                         intel_connector_break_all_links(connector);
11803                 }
11804         }
11805         /* Enabled encoders without active connectors will be fixed in
11806          * the crtc fixup. */
11807 }
11808
11809 void i915_redisable_vga_power_on(struct drm_device *dev)
11810 {
11811         struct drm_i915_private *dev_priv = dev->dev_private;
11812         u32 vga_reg = i915_vgacntrl_reg(dev);
11813
11814         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11815                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11816                 i915_disable_vga(dev);
11817         }
11818 }
11819
11820 void i915_redisable_vga(struct drm_device *dev)
11821 {
11822         struct drm_i915_private *dev_priv = dev->dev_private;
11823
11824         /* This function can be called both from intel_modeset_setup_hw_state or
11825          * at a very early point in our resume sequence, where the power well
11826          * structures are not yet restored. Since this function is at a very
11827          * paranoid "someone might have enabled VGA while we were not looking"
11828          * level, just check if the power well is enabled instead of trying to
11829          * follow the "don't touch the power well if we don't need it" policy
11830          * the rest of the driver uses. */
11831         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11832                 return;
11833
11834         i915_redisable_vga_power_on(dev);
11835 }
11836
11837 static bool primary_get_hw_state(struct intel_crtc *crtc)
11838 {
11839         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11840
11841         if (!crtc->active)
11842                 return false;
11843
11844         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11845 }
11846
11847 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11848 {
11849         struct drm_i915_private *dev_priv = dev->dev_private;
11850         enum pipe pipe;
11851         struct intel_crtc *crtc;
11852         struct intel_encoder *encoder;
11853         struct intel_connector *connector;
11854         int i;
11855
11856         for_each_intel_crtc(dev, crtc) {
11857                 memset(&crtc->config, 0, sizeof(crtc->config));
11858
11859                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11860
11861                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11862                                                                  &crtc->config);
11863
11864                 crtc->base.enabled = crtc->active;
11865                 crtc->primary_enabled = primary_get_hw_state(crtc);
11866
11867                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11868                               crtc->base.base.id,
11869                               crtc->active ? "enabled" : "disabled");
11870         }
11871
11872         /* FIXME: Smash this into the new shared dpll infrastructure. */
11873         if (HAS_DDI(dev))
11874                 intel_ddi_setup_hw_pll_state(dev);
11875
11876         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11877                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11878
11879                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11880                 pll->active = 0;
11881                 for_each_intel_crtc(dev, crtc) {
11882                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11883                                 pll->active++;
11884                 }
11885                 pll->refcount = pll->active;
11886
11887                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11888                               pll->name, pll->refcount, pll->on);
11889         }
11890
11891         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11892                             base.head) {
11893                 pipe = 0;
11894
11895                 if (encoder->get_hw_state(encoder, &pipe)) {
11896                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11897                         encoder->base.crtc = &crtc->base;
11898                         encoder->get_config(encoder, &crtc->config);
11899                 } else {
11900                         encoder->base.crtc = NULL;
11901                 }
11902
11903                 encoder->connectors_active = false;
11904                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11905                               encoder->base.base.id,
11906                               drm_get_encoder_name(&encoder->base),
11907                               encoder->base.crtc ? "enabled" : "disabled",
11908                               pipe_name(pipe));
11909         }
11910
11911         list_for_each_entry(connector, &dev->mode_config.connector_list,
11912                             base.head) {
11913                 if (connector->get_hw_state(connector)) {
11914                         connector->base.dpms = DRM_MODE_DPMS_ON;
11915                         connector->encoder->connectors_active = true;
11916                         connector->base.encoder = &connector->encoder->base;
11917                 } else {
11918                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11919                         connector->base.encoder = NULL;
11920                 }
11921                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11922                               connector->base.base.id,
11923                               drm_get_connector_name(&connector->base),
11924                               connector->base.encoder ? "enabled" : "disabled");
11925         }
11926 }
11927
11928 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11929  * and i915 state tracking structures. */
11930 void intel_modeset_setup_hw_state(struct drm_device *dev,
11931                                   bool force_restore)
11932 {
11933         struct drm_i915_private *dev_priv = dev->dev_private;
11934         enum pipe pipe;
11935         struct intel_crtc *crtc;
11936         struct intel_encoder *encoder;
11937         int i;
11938
11939         intel_modeset_readout_hw_state(dev);
11940
11941         /*
11942          * Now that we have the config, copy it to each CRTC struct
11943          * Note that this could go away if we move to using crtc_config
11944          * checking everywhere.
11945          */
11946         for_each_intel_crtc(dev, crtc) {
11947                 if (crtc->active && i915.fastboot) {
11948                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11949                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11950                                       crtc->base.base.id);
11951                         drm_mode_debug_printmodeline(&crtc->base.mode);
11952                 }
11953         }
11954
11955         /* HW state is read out, now we need to sanitize this mess. */
11956         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11957                             base.head) {
11958                 intel_sanitize_encoder(encoder);
11959         }
11960
11961         for_each_pipe(pipe) {
11962                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11963                 intel_sanitize_crtc(crtc);
11964                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11965         }
11966
11967         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11968                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11969
11970                 if (!pll->on || pll->active)
11971                         continue;
11972
11973                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11974
11975                 pll->disable(dev_priv, pll);
11976                 pll->on = false;
11977         }
11978
11979         if (HAS_PCH_SPLIT(dev))
11980                 ilk_wm_get_hw_state(dev);
11981
11982         if (force_restore) {
11983                 i915_redisable_vga(dev);
11984
11985                 /*
11986                  * We need to use raw interfaces for restoring state to avoid
11987                  * checking (bogus) intermediate states.
11988                  */
11989                 for_each_pipe(pipe) {
11990                         struct drm_crtc *crtc =
11991                                 dev_priv->pipe_to_crtc_mapping[pipe];
11992
11993                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11994                                          crtc->primary->fb);
11995                 }
11996         } else {
11997                 intel_modeset_update_staged_output_state(dev);
11998         }
11999
12000         intel_modeset_check_state(dev);
12001 }
12002
12003 void intel_modeset_gem_init(struct drm_device *dev)
12004 {
12005         struct drm_crtc *c;
12006         struct intel_framebuffer *fb;
12007
12008         mutex_lock(&dev->struct_mutex);
12009         intel_init_gt_powersave(dev);
12010         mutex_unlock(&dev->struct_mutex);
12011
12012         intel_modeset_init_hw(dev);
12013
12014         intel_setup_overlay(dev);
12015
12016         /*
12017          * Make sure any fbs we allocated at startup are properly
12018          * pinned & fenced.  When we do the allocation it's too early
12019          * for this.
12020          */
12021         mutex_lock(&dev->struct_mutex);
12022         for_each_crtc(dev, c) {
12023                 if (!c->primary->fb)
12024                         continue;
12025
12026                 fb = to_intel_framebuffer(c->primary->fb);
12027                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12028                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12029                                   to_intel_crtc(c)->pipe);
12030                         drm_framebuffer_unreference(c->primary->fb);
12031                         c->primary->fb = NULL;
12032                 }
12033         }
12034         mutex_unlock(&dev->struct_mutex);
12035 }
12036
12037 void intel_connector_unregister(struct intel_connector *intel_connector)
12038 {
12039         struct drm_connector *connector = &intel_connector->base;
12040
12041         intel_panel_destroy_backlight(connector);
12042         drm_sysfs_connector_remove(connector);
12043 }
12044
12045 void intel_modeset_cleanup(struct drm_device *dev)
12046 {
12047         struct drm_i915_private *dev_priv = dev->dev_private;
12048         struct drm_crtc *crtc;
12049         struct drm_connector *connector;
12050
12051         /*
12052          * Interrupts and polling as the first thing to avoid creating havoc.
12053          * Too much stuff here (turning of rps, connectors, ...) would
12054          * experience fancy races otherwise.
12055          */
12056         drm_irq_uninstall(dev);
12057         cancel_work_sync(&dev_priv->hotplug_work);
12058         /*
12059          * Due to the hpd irq storm handling the hotplug work can re-arm the
12060          * poll handlers. Hence disable polling after hpd handling is shut down.
12061          */
12062         drm_kms_helper_poll_fini(dev);
12063
12064         mutex_lock(&dev->struct_mutex);
12065
12066         intel_unregister_dsm_handler();
12067
12068         for_each_crtc(dev, crtc) {
12069                 /* Skip inactive CRTCs */
12070                 if (!crtc->primary->fb)
12071                         continue;
12072
12073                 intel_increase_pllclock(crtc);
12074         }
12075
12076         intel_disable_fbc(dev);
12077
12078         intel_disable_gt_powersave(dev);
12079
12080         ironlake_teardown_rc6(dev);
12081
12082         mutex_unlock(&dev->struct_mutex);
12083
12084         /* flush any delayed tasks or pending work */
12085         flush_scheduled_work();
12086
12087         /* destroy the backlight and sysfs files before encoders/connectors */
12088         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12089                 struct intel_connector *intel_connector;
12090
12091                 intel_connector = to_intel_connector(connector);
12092                 intel_connector->unregister(intel_connector);
12093         }
12094
12095         drm_mode_config_cleanup(dev);
12096
12097         intel_cleanup_overlay(dev);
12098
12099         mutex_lock(&dev->struct_mutex);
12100         intel_cleanup_gt_powersave(dev);
12101         mutex_unlock(&dev->struct_mutex);
12102 }
12103
12104 /*
12105  * Return which encoder is currently attached for connector.
12106  */
12107 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12108 {
12109         return &intel_attached_encoder(connector)->base;
12110 }
12111
12112 void intel_connector_attach_encoder(struct intel_connector *connector,
12113                                     struct intel_encoder *encoder)
12114 {
12115         connector->encoder = encoder;
12116         drm_mode_connector_attach_encoder(&connector->base,
12117                                           &encoder->base);
12118 }
12119
12120 /*
12121  * set vga decode state - true == enable VGA decode
12122  */
12123 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12124 {
12125         struct drm_i915_private *dev_priv = dev->dev_private;
12126         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12127         u16 gmch_ctrl;
12128
12129         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12130                 DRM_ERROR("failed to read control word\n");
12131                 return -EIO;
12132         }
12133
12134         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12135                 return 0;
12136
12137         if (state)
12138                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12139         else
12140                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12141
12142         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12143                 DRM_ERROR("failed to write control word\n");
12144                 return -EIO;
12145         }
12146
12147         return 0;
12148 }
12149
12150 struct intel_display_error_state {
12151
12152         u32 power_well_driver;
12153
12154         int num_transcoders;
12155
12156         struct intel_cursor_error_state {
12157                 u32 control;
12158                 u32 position;
12159                 u32 base;
12160                 u32 size;
12161         } cursor[I915_MAX_PIPES];
12162
12163         struct intel_pipe_error_state {
12164                 bool power_domain_on;
12165                 u32 source;
12166                 u32 stat;
12167         } pipe[I915_MAX_PIPES];
12168
12169         struct intel_plane_error_state {
12170                 u32 control;
12171                 u32 stride;
12172                 u32 size;
12173                 u32 pos;
12174                 u32 addr;
12175                 u32 surface;
12176                 u32 tile_offset;
12177         } plane[I915_MAX_PIPES];
12178
12179         struct intel_transcoder_error_state {
12180                 bool power_domain_on;
12181                 enum transcoder cpu_transcoder;
12182
12183                 u32 conf;
12184
12185                 u32 htotal;
12186                 u32 hblank;
12187                 u32 hsync;
12188                 u32 vtotal;
12189                 u32 vblank;
12190                 u32 vsync;
12191         } transcoder[4];
12192 };
12193
12194 struct intel_display_error_state *
12195 intel_display_capture_error_state(struct drm_device *dev)
12196 {
12197         struct drm_i915_private *dev_priv = dev->dev_private;
12198         struct intel_display_error_state *error;
12199         int transcoders[] = {
12200                 TRANSCODER_A,
12201                 TRANSCODER_B,
12202                 TRANSCODER_C,
12203                 TRANSCODER_EDP,
12204         };
12205         int i;
12206
12207         if (INTEL_INFO(dev)->num_pipes == 0)
12208                 return NULL;
12209
12210         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12211         if (error == NULL)
12212                 return NULL;
12213
12214         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12215                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12216
12217         for_each_pipe(i) {
12218                 error->pipe[i].power_domain_on =
12219                         intel_display_power_enabled_sw(dev_priv,
12220                                                        POWER_DOMAIN_PIPE(i));
12221                 if (!error->pipe[i].power_domain_on)
12222                         continue;
12223
12224                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12225                         error->cursor[i].control = I915_READ(CURCNTR(i));
12226                         error->cursor[i].position = I915_READ(CURPOS(i));
12227                         error->cursor[i].base = I915_READ(CURBASE(i));
12228                 } else {
12229                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12230                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12231                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12232                 }
12233
12234                 error->plane[i].control = I915_READ(DSPCNTR(i));
12235                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12236                 if (INTEL_INFO(dev)->gen <= 3) {
12237                         error->plane[i].size = I915_READ(DSPSIZE(i));
12238                         error->plane[i].pos = I915_READ(DSPPOS(i));
12239                 }
12240                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12241                         error->plane[i].addr = I915_READ(DSPADDR(i));
12242                 if (INTEL_INFO(dev)->gen >= 4) {
12243                         error->plane[i].surface = I915_READ(DSPSURF(i));
12244                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12245                 }
12246
12247                 error->pipe[i].source = I915_READ(PIPESRC(i));
12248
12249                 if (!HAS_PCH_SPLIT(dev))
12250                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12251         }
12252
12253         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12254         if (HAS_DDI(dev_priv->dev))
12255                 error->num_transcoders++; /* Account for eDP. */
12256
12257         for (i = 0; i < error->num_transcoders; i++) {
12258                 enum transcoder cpu_transcoder = transcoders[i];
12259
12260                 error->transcoder[i].power_domain_on =
12261                         intel_display_power_enabled_sw(dev_priv,
12262                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12263                 if (!error->transcoder[i].power_domain_on)
12264                         continue;
12265
12266                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12267
12268                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12269                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12270                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12271                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12272                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12273                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12274                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12275         }
12276
12277         return error;
12278 }
12279
12280 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12281
12282 void
12283 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12284                                 struct drm_device *dev,
12285                                 struct intel_display_error_state *error)
12286 {
12287         int i;
12288
12289         if (!error)
12290                 return;
12291
12292         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12293         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12294                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12295                            error->power_well_driver);
12296         for_each_pipe(i) {
12297                 err_printf(m, "Pipe [%d]:\n", i);
12298                 err_printf(m, "  Power: %s\n",
12299                            error->pipe[i].power_domain_on ? "on" : "off");
12300                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12301                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12302
12303                 err_printf(m, "Plane [%d]:\n", i);
12304                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12305                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12306                 if (INTEL_INFO(dev)->gen <= 3) {
12307                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12308                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12309                 }
12310                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12311                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12312                 if (INTEL_INFO(dev)->gen >= 4) {
12313                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12314                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12315                 }
12316
12317                 err_printf(m, "Cursor [%d]:\n", i);
12318                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12319                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12320                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12321         }
12322
12323         for (i = 0; i < error->num_transcoders; i++) {
12324                 err_printf(m, "CPU transcoder: %c\n",
12325                            transcoder_name(error->transcoder[i].cpu_transcoder));
12326                 err_printf(m, "  Power: %s\n",
12327                            error->transcoder[i].power_domain_on ? "on" : "off");
12328                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12329                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12330                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12331                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12332                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12333                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12334                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12335         }
12336 }