drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & SDVO_ENABLE) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1358                         return false;
1359         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1361                         return false;
1362         } else {
1363                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1364                         return false;
1365         }
1366         return true;
1367 }
1368
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370                               enum pipe pipe, u32 val)
1371 {
1372         if ((val & LVDS_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & ADPA_DAC_ENABLE) == 0)
1389                 return false;
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1392                         return false;
1393         } else {
1394                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1395                         return false;
1396         }
1397         return true;
1398 }
1399
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401                                    enum pipe pipe, int reg, u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, int reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              reg, pipe_name(pipe));
1420
1421         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1435
1436         reg = PCH_ADPA;
1437         val = I915_READ(reg);
1438         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         reg = PCH_LVDS;
1443         val = I915_READ(reg);
1444         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1451 }
1452
1453 static void intel_init_dpio(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!IS_VALLEYVIEW(dev))
1458                 return;
1459
1460         /*
1461          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462          * CHV x1 PHY (DP/HDMI D)
1463          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1464          */
1465         if (IS_CHERRYVIEW(dev)) {
1466                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1468         } else {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1470         }
1471 }
1472
1473 static void intel_reset_dpio(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         if (!IS_VALLEYVIEW(dev))
1478                 return;
1479
1480         /*
1481          * Enable the CRI clock source so we can get at the display and the
1482          * reference clock for VGA hotplug / manual detection.
1483          */
1484         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485                    DPLL_REFA_CLK_ENABLE_VLV |
1486                    DPLL_INTEGRATED_CRI_CLK_VLV);
1487
1488         if (IS_CHERRYVIEW(dev)) {
1489                 enum dpio_phy phy;
1490                 u32 val;
1491
1492                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493                         /* Poll for phypwrgood signal */
1494                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495                                                 PHY_POWERGOOD(phy), 1))
1496                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1497
1498                         /*
1499                          * Deassert common lane reset for PHY.
1500                          *
1501                          * This should only be done on init and resume from S3
1502                          * with both PLLs disabled, or we risk losing DPIO and
1503                          * PLL synchronization.
1504                          */
1505                         val = I915_READ(DISPLAY_PHY_CONTROL);
1506                         I915_WRITE(DISPLAY_PHY_CONTROL,
1507                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1508                 }
1509
1510         } else {
1511                 /*
1512                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1514                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515                  *   b. The other bits such as sfr settings / modesel may all
1516                  *      be set to 0.
1517                  *
1518                  * This should only be done on init and resume from S3 with
1519                  * both PLLs disabled, or we risk losing DPIO and PLL
1520                  * synchronization.
1521                  */
1522                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1523         }
1524 }
1525
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1527 {
1528         struct drm_device *dev = crtc->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         int reg = DPLL(crtc->pipe);
1531         u32 dpll = crtc->config.dpll_hw_state.dpll;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         /* No really, not for ILK+ */
1536         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1537
1538         /* PLL is protected by panel, make sure we can write it */
1539         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540                 assert_panel_unlocked(dev_priv, crtc->pipe);
1541
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150);
1545
1546         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1548
1549         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550         POSTING_READ(DPLL_MD(crtc->pipe));
1551
1552         /* We do this three times for luck */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         int dpll = DPLL(crtc->pipe);
1571         u32 tmp;
1572
1573         assert_pipe_disabled(dev_priv, crtc->pipe);
1574
1575         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1576
1577         mutex_lock(&dev_priv->dpio_lock);
1578
1579         /* Enable back the 10bit clock to display controller */
1580         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581         tmp |= DPIO_DCLKP_EN;
1582         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584         /*
1585          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586          */
1587         udelay(1);
1588
1589         /* Enable PLL */
1590         tmp = I915_READ(dpll);
1591         tmp |= DPLL_VCO_ENABLE;
1592         I915_WRITE(dpll, tmp);
1593
1594         /* Check PLL is locked */
1595         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597
1598         /* Deassert soft data lane reset*/
1599         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1602
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         int dpll = DPLL(pipe);
1696         u32 val;
1697
1698         /* Set PLL en = 0 */
1699         val = I915_READ(dpll);
1700         val &= ~DPLL_VCO_ENABLE;
1701         I915_WRITE(dpll, val);
1702
1703 }
1704
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706                 struct intel_digital_port *dport)
1707 {
1708         u32 port_mask;
1709         int dpll_reg;
1710
1711         switch (dport->port) {
1712         case PORT_B:
1713                 port_mask = DPLL_PORTB_READY_MASK;
1714                 dpll_reg = DPLL(0);
1715                 break;
1716         case PORT_C:
1717                 port_mask = DPLL_PORTC_READY_MASK;
1718                 dpll_reg = DPLL(0);
1719                 break;
1720         case PORT_D:
1721                 port_mask = DPLL_PORTD_READY_MASK;
1722                 dpll_reg = DPIO_PHY_STATUS;
1723                 break;
1724         default:
1725                 BUG();
1726         }
1727
1728         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730                      port_name(dport->port), I915_READ(dpll_reg));
1731 }
1732
1733 /**
1734  * ironlake_enable_shared_dpll - enable PCH PLL
1735  * @dev_priv: i915 private structure
1736  * @pipe: pipe PLL to enable
1737  *
1738  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739  * drives the transcoder clock.
1740  */
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->base.dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1746
1747         /* PCH PLLs only available on ILK, SNB and IVB */
1748         BUG_ON(INTEL_INFO(dev)->gen < 5);
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         if (WARN_ON(pll->refcount == 0))
1753                 return;
1754
1755         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756                       pll->name, pll->active, pll->on,
1757                       crtc->base.base.id);
1758
1759         if (pll->active++) {
1760                 WARN_ON(!pll->on);
1761                 assert_shared_dpll_enabled(dev_priv, pll);
1762                 return;
1763         }
1764         WARN_ON(pll->on);
1765
1766         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767         pll->enable(dev_priv, pll);
1768         pll->on = true;
1769 }
1770
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1772 {
1773         struct drm_device *dev = crtc->base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776
1777         /* PCH only available on ILK+ */
1778         BUG_ON(INTEL_INFO(dev)->gen < 5);
1779         if (WARN_ON(pll == NULL))
1780                return;
1781
1782         if (WARN_ON(pll->refcount == 0))
1783                 return;
1784
1785         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786                       pll->name, pll->active, pll->on,
1787                       crtc->base.base.id);
1788
1789         if (WARN_ON(pll->active == 0)) {
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791                 return;
1792         }
1793
1794         assert_shared_dpll_enabled(dev_priv, pll);
1795         WARN_ON(!pll->on);
1796         if (--pll->active)
1797                 return;
1798
1799         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800         pll->disable(dev_priv, pll);
1801         pll->on = false;
1802 }
1803
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1805                                            enum pipe pipe)
1806 {
1807         struct drm_device *dev = dev_priv->dev;
1808         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         uint32_t reg, val, pipeconf_val;
1811
1812         /* PCH only available on ILK+ */
1813         BUG_ON(INTEL_INFO(dev)->gen < 5);
1814
1815         /* Make sure PCH DPLL is enabled */
1816         assert_shared_dpll_enabled(dev_priv,
1817                                    intel_crtc_to_shared_dpll(intel_crtc));
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, pipe);
1821         assert_fdi_rx_enabled(dev_priv, pipe);
1822
1823         if (HAS_PCH_CPT(dev)) {
1824                 /* Workaround: Set the timing override bit before enabling the
1825                  * pch transcoder. */
1826                 reg = TRANS_CHICKEN2(pipe);
1827                 val = I915_READ(reg);
1828                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829                 I915_WRITE(reg, val);
1830         }
1831
1832         reg = PCH_TRANSCONF(pipe);
1833         val = I915_READ(reg);
1834         pipeconf_val = I915_READ(PIPECONF(pipe));
1835
1836         if (HAS_PCH_IBX(dev_priv->dev)) {
1837                 /*
1838                  * make the BPC in transcoder be consistent with
1839                  * that in pipeconf reg.
1840                  */
1841                 val &= ~PIPECONF_BPC_MASK;
1842                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1843         }
1844
1845         val &= ~TRANS_INTERLACE_MASK;
1846         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847                 if (HAS_PCH_IBX(dev_priv->dev) &&
1848                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849                         val |= TRANS_LEGACY_INTERLACED_ILK;
1850                 else
1851                         val |= TRANS_INTERLACED;
1852         else
1853                 val |= TRANS_PROGRESSIVE;
1854
1855         I915_WRITE(reg, val | TRANS_ENABLE);
1856         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1858 }
1859
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861                                       enum transcoder cpu_transcoder)
1862 {
1863         u32 val, pipeconf_val;
1864
1865         /* PCH only available on ILK+ */
1866         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1867
1868         /* FDI must be feeding us bits for PCH ports */
1869         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1871
1872         /* Workaround: set timing override bit. */
1873         val = I915_READ(_TRANSA_CHICKEN2);
1874         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875         I915_WRITE(_TRANSA_CHICKEN2, val);
1876
1877         val = TRANS_ENABLE;
1878         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1879
1880         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881             PIPECONF_INTERLACED_ILK)
1882                 val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(LPT_TRANSCONF, val);
1887         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("Failed to enable PCH transcoder\n");
1889 }
1890
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                             enum pipe pipe)
1893 {
1894         struct drm_device *dev = dev_priv->dev;
1895         uint32_t reg, val;
1896
1897         /* FDI relies on the transcoder */
1898         assert_fdi_tx_disabled(dev_priv, pipe);
1899         assert_fdi_rx_disabled(dev_priv, pipe);
1900
1901         /* Ports must be off as well */
1902         assert_pch_ports_disabled(dev_priv, pipe);
1903
1904         reg = PCH_TRANSCONF(pipe);
1905         val = I915_READ(reg);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(reg, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1911
1912         if (!HAS_PCH_IBX(dev)) {
1913                 /* Workaround: Clear the timing override chicken bit again. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919 }
1920
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1922 {
1923         u32 val;
1924
1925         val = I915_READ(LPT_TRANSCONF);
1926         val &= ~TRANS_ENABLE;
1927         I915_WRITE(LPT_TRANSCONF, val);
1928         /* wait for PCH transcoder off, transcoder state */
1929         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930                 DRM_ERROR("Failed to disable PCH transcoder\n");
1931
1932         /* Workaround: clear timing override bit. */
1933         val = I915_READ(_TRANSA_CHICKEN2);
1934         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935         I915_WRITE(_TRANSA_CHICKEN2, val);
1936 }
1937
1938 /**
1939  * intel_enable_pipe - enable a pipe, asserting requirements
1940  * @crtc: crtc responsible for the pipe
1941  *
1942  * Enable @crtc's pipe, making sure that various hardware specific requirements
1943  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1944  */
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1946 {
1947         struct drm_device *dev = crtc->base.dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         enum pipe pipe = crtc->pipe;
1950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1951                                                                       pipe);
1952         enum pipe pch_transcoder;
1953         int reg;
1954         u32 val;
1955
1956         assert_planes_disabled(dev_priv, pipe);
1957         assert_cursor_disabled(dev_priv, pipe);
1958         assert_sprites_disabled(dev_priv, pipe);
1959
1960         if (HAS_PCH_LPT(dev_priv->dev))
1961                 pch_transcoder = TRANSCODER_A;
1962         else
1963                 pch_transcoder = pipe;
1964
1965         /*
1966          * A pipe without a PLL won't actually be able to drive bits from
1967          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1968          * need the check.
1969          */
1970         if (!HAS_PCH_SPLIT(dev_priv->dev))
1971                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972                         assert_dsi_pll_enabled(dev_priv);
1973                 else
1974                         assert_pll_enabled(dev_priv, pipe);
1975         else {
1976                 if (crtc->config.has_pch_encoder) {
1977                         /* if driving the PCH, we need FDI enabled */
1978                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979                         assert_fdi_tx_pll_enabled(dev_priv,
1980                                                   (enum pipe) cpu_transcoder);
1981                 }
1982                 /* FIXME: assert CPU port conditions for SNB+ */
1983         }
1984
1985         reg = PIPECONF(cpu_transcoder);
1986         val = I915_READ(reg);
1987         if (val & PIPECONF_ENABLE) {
1988                 WARN_ON(!(pipe == PIPE_A &&
1989                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1990                 return;
1991         }
1992
1993         I915_WRITE(reg, val | PIPECONF_ENABLE);
1994         POSTING_READ(reg);
1995 }
1996
1997 /**
1998  * intel_disable_pipe - disable a pipe, asserting requirements
1999  * @dev_priv: i915 private structure
2000  * @pipe: pipe to disable
2001  *
2002  * Disable @pipe, making sure that various hardware specific requirements
2003  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2004  *
2005  * @pipe should be %PIPE_A or %PIPE_B.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2010                                enum pipe pipe)
2011 {
2012         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013                                                                       pipe);
2014         int reg;
2015         u32 val;
2016
2017         /*
2018          * Make sure planes won't keep trying to pump pixels to us,
2019          * or we might hang the display.
2020          */
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024
2025         /* Don't disable pipe A or pipe A PLLs if needed */
2026         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2027                 return;
2028
2029         reg = PIPECONF(cpu_transcoder);
2030         val = I915_READ(reg);
2031         if ((val & PIPECONF_ENABLE) == 0)
2032                 return;
2033
2034         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2036 }
2037
2038 /*
2039  * Plane regs are double buffered, going from enabled->disabled needs a
2040  * trigger in order to latch.  The display address reg provides this.
2041  */
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2043                                enum plane plane)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2047
2048         I915_WRITE(reg, I915_READ(reg));
2049         POSTING_READ(reg);
2050 }
2051
2052 /**
2053  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054  * @dev_priv: i915 private structure
2055  * @plane: plane to enable
2056  * @pipe: pipe being fed
2057  *
2058  * Enable @plane on @pipe, making sure that @pipe is running first.
2059  */
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061                                           enum plane plane, enum pipe pipe)
2062 {
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2065         int reg;
2066         u32 val;
2067
2068         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069         assert_pipe_enabled(dev_priv, pipe);
2070
2071         if (intel_crtc->primary_enabled)
2072                 return;
2073
2074         intel_crtc->primary_enabled = true;
2075
2076         reg = DSPCNTR(plane);
2077         val = I915_READ(reg);
2078         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2079
2080         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081         intel_flush_primary_plane(dev_priv, plane);
2082         intel_wait_for_vblank(dev_priv->dev, pipe);
2083 }
2084
2085 /**
2086  * intel_disable_primary_hw_plane - disable the primary hardware plane
2087  * @dev_priv: i915 private structure
2088  * @plane: plane to disable
2089  * @pipe: pipe consuming the data
2090  *
2091  * Disable @plane; should be an independent operation.
2092  */
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094                                            enum plane plane, enum pipe pipe)
2095 {
2096         struct intel_crtc *intel_crtc =
2097                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2098         int reg;
2099         u32 val;
2100
2101         if (!intel_crtc->primary_enabled)
2102                 return;
2103
2104         intel_crtc->primary_enabled = false;
2105
2106         reg = DSPCNTR(plane);
2107         val = I915_READ(reg);
2108         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2109
2110         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111         intel_flush_primary_plane(dev_priv, plane);
2112         intel_wait_for_vblank(dev_priv->dev, pipe);
2113 }
2114
2115 static bool need_vtd_wa(struct drm_device *dev)
2116 {
2117 #ifdef CONFIG_INTEL_IOMMU
2118         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2119                 return true;
2120 #endif
2121         return false;
2122 }
2123
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2125 {
2126         int tile_height;
2127
2128         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129         return ALIGN(height, tile_height);
2130 }
2131
2132 int
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134                            struct drm_i915_gem_object *obj,
2135                            struct intel_ring_buffer *pipelined)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 alignment;
2139         int ret;
2140
2141         switch (obj->tiling_mode) {
2142         case I915_TILING_NONE:
2143                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144                         alignment = 128 * 1024;
2145                 else if (INTEL_INFO(dev)->gen >= 4)
2146                         alignment = 4 * 1024;
2147                 else
2148                         alignment = 64 * 1024;
2149                 break;
2150         case I915_TILING_X:
2151                 /* pin() will align the object as required by fence */
2152                 alignment = 0;
2153                 break;
2154         case I915_TILING_Y:
2155                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2156                 return -EINVAL;
2157         default:
2158                 BUG();
2159         }
2160
2161         /* Note that the w/a also requires 64 PTE of padding following the
2162          * bo. We currently fill all unused PTE with the shadow page and so
2163          * we should always have valid PTE following the scanout preventing
2164          * the VT-d warning.
2165          */
2166         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167                 alignment = 256 * 1024;
2168
2169         dev_priv->mm.interruptible = false;
2170         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2171         if (ret)
2172                 goto err_interruptible;
2173
2174         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175          * fence, whereas 965+ only requires a fence if using
2176          * framebuffer compression.  For simplicity, we always install
2177          * a fence as the cost is not that onerous.
2178          */
2179         ret = i915_gem_object_get_fence(obj);
2180         if (ret)
2181                 goto err_unpin;
2182
2183         i915_gem_object_pin_fence(obj);
2184
2185         dev_priv->mm.interruptible = true;
2186         return 0;
2187
2188 err_unpin:
2189         i915_gem_object_unpin_from_display_plane(obj);
2190 err_interruptible:
2191         dev_priv->mm.interruptible = true;
2192         return ret;
2193 }
2194
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2196 {
2197         i915_gem_object_unpin_fence(obj);
2198         i915_gem_object_unpin_from_display_plane(obj);
2199 }
2200
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202  * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204                                              unsigned int tiling_mode,
2205                                              unsigned int cpp,
2206                                              unsigned int pitch)
2207 {
2208         if (tiling_mode != I915_TILING_NONE) {
2209                 unsigned int tile_rows, tiles;
2210
2211                 tile_rows = *y / 8;
2212                 *y %= 8;
2213
2214                 tiles = *x / (512/cpp);
2215                 *x %= 512/cpp;
2216
2217                 return tile_rows * pitch * 8 + tiles * 4096;
2218         } else {
2219                 unsigned int offset;
2220
2221                 offset = *y * pitch + *x * cpp;
2222                 *y = 0;
2223                 *x = (offset & 4095) / cpp;
2224                 return offset & -4096;
2225         }
2226 }
2227
2228 int intel_format_to_fourcc(int format)
2229 {
2230         switch (format) {
2231         case DISPPLANE_8BPP:
2232                 return DRM_FORMAT_C8;
2233         case DISPPLANE_BGRX555:
2234                 return DRM_FORMAT_XRGB1555;
2235         case DISPPLANE_BGRX565:
2236                 return DRM_FORMAT_RGB565;
2237         default:
2238         case DISPPLANE_BGRX888:
2239                 return DRM_FORMAT_XRGB8888;
2240         case DISPPLANE_RGBX888:
2241                 return DRM_FORMAT_XBGR8888;
2242         case DISPPLANE_BGRX101010:
2243                 return DRM_FORMAT_XRGB2101010;
2244         case DISPPLANE_RGBX101010:
2245                 return DRM_FORMAT_XBGR2101010;
2246         }
2247 }
2248
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250                                   struct intel_plane_config *plane_config)
2251 {
2252         struct drm_device *dev = crtc->base.dev;
2253         struct drm_i915_gem_object *obj = NULL;
2254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255         u32 base = plane_config->base;
2256
2257         if (plane_config->size == 0)
2258                 return false;
2259
2260         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261                                                              plane_config->size);
2262         if (!obj)
2263                 return false;
2264
2265         if (plane_config->tiled) {
2266                 obj->tiling_mode = I915_TILING_X;
2267                 obj->stride = crtc->base.primary->fb->pitches[0];
2268         }
2269
2270         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271         mode_cmd.width = crtc->base.primary->fb->width;
2272         mode_cmd.height = crtc->base.primary->fb->height;
2273         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2274
2275         mutex_lock(&dev->struct_mutex);
2276
2277         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2278                                    &mode_cmd, obj)) {
2279                 DRM_DEBUG_KMS("intel fb init failed\n");
2280                 goto out_unref_obj;
2281         }
2282
2283         mutex_unlock(&dev->struct_mutex);
2284
2285         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2286         return true;
2287
2288 out_unref_obj:
2289         drm_gem_object_unreference(&obj->base);
2290         mutex_unlock(&dev->struct_mutex);
2291         return false;
2292 }
2293
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295                                  struct intel_plane_config *plane_config)
2296 {
2297         struct drm_device *dev = intel_crtc->base.dev;
2298         struct drm_crtc *c;
2299         struct intel_crtc *i;
2300         struct intel_framebuffer *fb;
2301
2302         if (!intel_crtc->base.primary->fb)
2303                 return;
2304
2305         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2306                 return;
2307
2308         kfree(intel_crtc->base.primary->fb);
2309         intel_crtc->base.primary->fb = NULL;
2310
2311         /*
2312          * Failed to alloc the obj, check to see if we should share
2313          * an fb with another CRTC instead
2314          */
2315         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2316                 i = to_intel_crtc(c);
2317
2318                 if (c == &intel_crtc->base)
2319                         continue;
2320
2321                 if (!i->active || !c->primary->fb)
2322                         continue;
2323
2324                 fb = to_intel_framebuffer(c->primary->fb);
2325                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326                         drm_framebuffer_reference(c->primary->fb);
2327                         intel_crtc->base.primary->fb = c->primary->fb;
2328                         break;
2329                 }
2330         }
2331 }
2332
2333 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2334                                      struct drm_framebuffer *fb,
2335                                      int x, int y)
2336 {
2337         struct drm_device *dev = crtc->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340         struct intel_framebuffer *intel_fb;
2341         struct drm_i915_gem_object *obj;
2342         int plane = intel_crtc->plane;
2343         unsigned long linear_offset;
2344         u32 dspcntr;
2345         u32 reg;
2346
2347         intel_fb = to_intel_framebuffer(fb);
2348         obj = intel_fb->obj;
2349
2350         reg = DSPCNTR(plane);
2351         dspcntr = I915_READ(reg);
2352         /* Mask out pixel format bits in case we change it */
2353         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354         switch (fb->pixel_format) {
2355         case DRM_FORMAT_C8:
2356                 dspcntr |= DISPPLANE_8BPP;
2357                 break;
2358         case DRM_FORMAT_XRGB1555:
2359         case DRM_FORMAT_ARGB1555:
2360                 dspcntr |= DISPPLANE_BGRX555;
2361                 break;
2362         case DRM_FORMAT_RGB565:
2363                 dspcntr |= DISPPLANE_BGRX565;
2364                 break;
2365         case DRM_FORMAT_XRGB8888:
2366         case DRM_FORMAT_ARGB8888:
2367                 dspcntr |= DISPPLANE_BGRX888;
2368                 break;
2369         case DRM_FORMAT_XBGR8888:
2370         case DRM_FORMAT_ABGR8888:
2371                 dspcntr |= DISPPLANE_RGBX888;
2372                 break;
2373         case DRM_FORMAT_XRGB2101010:
2374         case DRM_FORMAT_ARGB2101010:
2375                 dspcntr |= DISPPLANE_BGRX101010;
2376                 break;
2377         case DRM_FORMAT_XBGR2101010:
2378         case DRM_FORMAT_ABGR2101010:
2379                 dspcntr |= DISPPLANE_RGBX101010;
2380                 break;
2381         default:
2382                 BUG();
2383         }
2384
2385         if (INTEL_INFO(dev)->gen >= 4) {
2386                 if (obj->tiling_mode != I915_TILING_NONE)
2387                         dspcntr |= DISPPLANE_TILED;
2388                 else
2389                         dspcntr &= ~DISPPLANE_TILED;
2390         }
2391
2392         if (IS_G4X(dev))
2393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2394
2395         I915_WRITE(reg, dspcntr);
2396
2397         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2398
2399         if (INTEL_INFO(dev)->gen >= 4) {
2400                 intel_crtc->dspaddr_offset =
2401                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402                                                        fb->bits_per_pixel / 8,
2403                                                        fb->pitches[0]);
2404                 linear_offset -= intel_crtc->dspaddr_offset;
2405         } else {
2406                 intel_crtc->dspaddr_offset = linear_offset;
2407         }
2408
2409         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2411                       fb->pitches[0]);
2412         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413         if (INTEL_INFO(dev)->gen >= 4) {
2414                 I915_WRITE(DSPSURF(plane),
2415                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2418         } else
2419                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2420         POSTING_READ(reg);
2421
2422         return 0;
2423 }
2424
2425 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2426                                          struct drm_framebuffer *fb,
2427                                          int x, int y)
2428 {
2429         struct drm_device *dev = crtc->dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432         struct intel_framebuffer *intel_fb;
2433         struct drm_i915_gem_object *obj;
2434         int plane = intel_crtc->plane;
2435         unsigned long linear_offset;
2436         u32 dspcntr;
2437         u32 reg;
2438
2439         intel_fb = to_intel_framebuffer(fb);
2440         obj = intel_fb->obj;
2441
2442         reg = DSPCNTR(plane);
2443         dspcntr = I915_READ(reg);
2444         /* Mask out pixel format bits in case we change it */
2445         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2446         switch (fb->pixel_format) {
2447         case DRM_FORMAT_C8:
2448                 dspcntr |= DISPPLANE_8BPP;
2449                 break;
2450         case DRM_FORMAT_RGB565:
2451                 dspcntr |= DISPPLANE_BGRX565;
2452                 break;
2453         case DRM_FORMAT_XRGB8888:
2454         case DRM_FORMAT_ARGB8888:
2455                 dspcntr |= DISPPLANE_BGRX888;
2456                 break;
2457         case DRM_FORMAT_XBGR8888:
2458         case DRM_FORMAT_ABGR8888:
2459                 dspcntr |= DISPPLANE_RGBX888;
2460                 break;
2461         case DRM_FORMAT_XRGB2101010:
2462         case DRM_FORMAT_ARGB2101010:
2463                 dspcntr |= DISPPLANE_BGRX101010;
2464                 break;
2465         case DRM_FORMAT_XBGR2101010:
2466         case DRM_FORMAT_ABGR2101010:
2467                 dspcntr |= DISPPLANE_RGBX101010;
2468                 break;
2469         default:
2470                 BUG();
2471         }
2472
2473         if (obj->tiling_mode != I915_TILING_NONE)
2474                 dspcntr |= DISPPLANE_TILED;
2475         else
2476                 dspcntr &= ~DISPPLANE_TILED;
2477
2478         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2480         else
2481                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2482
2483         I915_WRITE(reg, dspcntr);
2484
2485         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2486         intel_crtc->dspaddr_offset =
2487                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2488                                                fb->bits_per_pixel / 8,
2489                                                fb->pitches[0]);
2490         linear_offset -= intel_crtc->dspaddr_offset;
2491
2492         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494                       fb->pitches[0]);
2495         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496         I915_WRITE(DSPSURF(plane),
2497                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2498         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2499                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2500         } else {
2501                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2503         }
2504         POSTING_READ(reg);
2505
2506         return 0;
2507 }
2508
2509 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2510 static int
2511 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2512                            int x, int y, enum mode_set_atomic state)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516
2517         if (dev_priv->display.disable_fbc)
2518                 dev_priv->display.disable_fbc(dev);
2519         intel_increase_pllclock(crtc);
2520
2521         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 }
2523
2524 void intel_display_handle_reset(struct drm_device *dev)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         struct drm_crtc *crtc;
2528
2529         /*
2530          * Flips in the rings have been nuked by the reset,
2531          * so complete all pending flips so that user space
2532          * will get its events and not get stuck.
2533          *
2534          * Also update the base address of all primary
2535          * planes to the the last fb to make sure we're
2536          * showing the correct fb after a reset.
2537          *
2538          * Need to make two loops over the crtcs so that we
2539          * don't try to grab a crtc mutex before the
2540          * pending_flip_queue really got woken up.
2541          */
2542
2543         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2544                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545                 enum plane plane = intel_crtc->plane;
2546
2547                 intel_prepare_page_flip(dev, plane);
2548                 intel_finish_page_flip_plane(dev, plane);
2549         }
2550
2551         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2552                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2553
2554                 mutex_lock(&crtc->mutex);
2555                 /*
2556                  * FIXME: Once we have proper support for primary planes (and
2557                  * disabling them without disabling the entire crtc) allow again
2558                  * a NULL crtc->primary->fb.
2559                  */
2560                 if (intel_crtc->active && crtc->primary->fb)
2561                         dev_priv->display.update_primary_plane(crtc,
2562                                                                crtc->primary->fb,
2563                                                                crtc->x,
2564                                                                crtc->y);
2565                 mutex_unlock(&crtc->mutex);
2566         }
2567 }
2568
2569 static int
2570 intel_finish_fb(struct drm_framebuffer *old_fb)
2571 {
2572         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2573         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2574         bool was_interruptible = dev_priv->mm.interruptible;
2575         int ret;
2576
2577         /* Big Hammer, we also need to ensure that any pending
2578          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2579          * current scanout is retired before unpinning the old
2580          * framebuffer.
2581          *
2582          * This should only fail upon a hung GPU, in which case we
2583          * can safely continue.
2584          */
2585         dev_priv->mm.interruptible = false;
2586         ret = i915_gem_object_finish_gpu(obj);
2587         dev_priv->mm.interruptible = was_interruptible;
2588
2589         return ret;
2590 }
2591
2592 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         unsigned long flags;
2598         bool pending;
2599
2600         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2601             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2602                 return false;
2603
2604         spin_lock_irqsave(&dev->event_lock, flags);
2605         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2606         spin_unlock_irqrestore(&dev->event_lock, flags);
2607
2608         return pending;
2609 }
2610
2611 static int
2612 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2613                     struct drm_framebuffer *fb)
2614 {
2615         struct drm_device *dev = crtc->dev;
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         struct drm_framebuffer *old_fb;
2619         int ret;
2620
2621         if (intel_crtc_has_pending_flip(crtc)) {
2622                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2623                 return -EBUSY;
2624         }
2625
2626         /* no fb bound */
2627         if (!fb) {
2628                 DRM_ERROR("No FB bound\n");
2629                 return 0;
2630         }
2631
2632         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2633                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2634                           plane_name(intel_crtc->plane),
2635                           INTEL_INFO(dev)->num_pipes);
2636                 return -EINVAL;
2637         }
2638
2639         mutex_lock(&dev->struct_mutex);
2640         ret = intel_pin_and_fence_fb_obj(dev,
2641                                          to_intel_framebuffer(fb)->obj,
2642                                          NULL);
2643         mutex_unlock(&dev->struct_mutex);
2644         if (ret != 0) {
2645                 DRM_ERROR("pin & fence failed\n");
2646                 return ret;
2647         }
2648
2649         /*
2650          * Update pipe size and adjust fitter if needed: the reason for this is
2651          * that in compute_mode_changes we check the native mode (not the pfit
2652          * mode) to see if we can flip rather than do a full mode set. In the
2653          * fastboot case, we'll flip, but if we don't update the pipesrc and
2654          * pfit state, we'll end up with a big fb scanned out into the wrong
2655          * sized surface.
2656          *
2657          * To fix this properly, we need to hoist the checks up into
2658          * compute_mode_changes (or above), check the actual pfit state and
2659          * whether the platform allows pfit disable with pipe active, and only
2660          * then update the pipesrc and pfit state, even on the flip path.
2661          */
2662         if (i915.fastboot) {
2663                 const struct drm_display_mode *adjusted_mode =
2664                         &intel_crtc->config.adjusted_mode;
2665
2666                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2667                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2668                            (adjusted_mode->crtc_vdisplay - 1));
2669                 if (!intel_crtc->config.pch_pfit.enabled &&
2670                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2671                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2672                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2673                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2674                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2675                 }
2676                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2677                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2678         }
2679
2680         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2681         if (ret) {
2682                 mutex_lock(&dev->struct_mutex);
2683                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2684                 mutex_unlock(&dev->struct_mutex);
2685                 DRM_ERROR("failed to update base address\n");
2686                 return ret;
2687         }
2688
2689         old_fb = crtc->primary->fb;
2690         crtc->primary->fb = fb;
2691         crtc->x = x;
2692         crtc->y = y;
2693
2694         if (old_fb) {
2695                 if (intel_crtc->active && old_fb != fb)
2696                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2697                 mutex_lock(&dev->struct_mutex);
2698                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2699                 mutex_unlock(&dev->struct_mutex);
2700         }
2701
2702         mutex_lock(&dev->struct_mutex);
2703         intel_update_fbc(dev);
2704         intel_edp_psr_update(dev);
2705         mutex_unlock(&dev->struct_mutex);
2706
2707         return 0;
2708 }
2709
2710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* enable normal train */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         if (IS_IVYBRIDGE(dev)) {
2722                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2724         } else {
2725                 temp &= ~FDI_LINK_TRAIN_NONE;
2726                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2727         }
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_NONE;
2738         }
2739         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2740
2741         /* wait one idle pattern time */
2742         POSTING_READ(reg);
2743         udelay(1000);
2744
2745         /* IVB wants error correction enabled */
2746         if (IS_IVYBRIDGE(dev))
2747                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2748                            FDI_FE_ERRC_ENABLE);
2749 }
2750
2751 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2752 {
2753         return crtc->base.enabled && crtc->active &&
2754                 crtc->config.has_pch_encoder;
2755 }
2756
2757 static void ivb_modeset_global_resources(struct drm_device *dev)
2758 {
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         struct intel_crtc *pipe_B_crtc =
2761                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2762         struct intel_crtc *pipe_C_crtc =
2763                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2764         uint32_t temp;
2765
2766         /*
2767          * When everything is off disable fdi C so that we could enable fdi B
2768          * with all lanes. Note that we don't care about enabled pipes without
2769          * an enabled pch encoder.
2770          */
2771         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2772             !pipe_has_enabled_pch(pipe_C_crtc)) {
2773                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2774                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2775
2776                 temp = I915_READ(SOUTH_CHICKEN1);
2777                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2778                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2779                 I915_WRITE(SOUTH_CHICKEN1, temp);
2780         }
2781 }
2782
2783 /* The FDI link training functions for ILK/Ibexpeak. */
2784 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp, tries;
2791
2792         /* FDI needs bits from pipe first */
2793         assert_pipe_enabled(dev_priv, pipe);
2794
2795         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2796            for train result */
2797         reg = FDI_RX_IMR(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_RX_SYMBOL_LOCK;
2800         temp &= ~FDI_RX_BIT_LOCK;
2801         I915_WRITE(reg, temp);
2802         I915_READ(reg);
2803         udelay(150);
2804
2805         /* enable CPU FDI TX and PCH FDI RX */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2809         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2810         temp &= ~FDI_LINK_TRAIN_NONE;
2811         temp |= FDI_LINK_TRAIN_PATTERN_1;
2812         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~FDI_LINK_TRAIN_NONE;
2817         temp |= FDI_LINK_TRAIN_PATTERN_1;
2818         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(150);
2822
2823         /* Ironlake workaround, enable clock pointer after FDI enable*/
2824         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2825         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2826                    FDI_RX_PHASE_SYNC_POINTER_EN);
2827
2828         reg = FDI_RX_IIR(pipe);
2829         for (tries = 0; tries < 5; tries++) {
2830                 temp = I915_READ(reg);
2831                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2832
2833                 if ((temp & FDI_RX_BIT_LOCK)) {
2834                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2835                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2836                         break;
2837                 }
2838         }
2839         if (tries == 5)
2840                 DRM_ERROR("FDI train 1 fail!\n");
2841
2842         /* Train 2 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_2;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_2;
2853         I915_WRITE(reg, temp);
2854
2855         POSTING_READ(reg);
2856         udelay(150);
2857
2858         reg = FDI_RX_IIR(pipe);
2859         for (tries = 0; tries < 5; tries++) {
2860                 temp = I915_READ(reg);
2861                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2862
2863                 if (temp & FDI_RX_SYMBOL_LOCK) {
2864                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2865                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2866                         break;
2867                 }
2868         }
2869         if (tries == 5)
2870                 DRM_ERROR("FDI train 2 fail!\n");
2871
2872         DRM_DEBUG_KMS("FDI train done\n");
2873
2874 }
2875
2876 static const int snb_b_fdi_train_param[] = {
2877         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2878         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2879         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2880         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2881 };
2882
2883 /* The FDI link training functions for SNB/Cougarpoint. */
2884 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2885 {
2886         struct drm_device *dev = crtc->dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889         int pipe = intel_crtc->pipe;
2890         u32 reg, temp, i, retry;
2891
2892         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2893            for train result */
2894         reg = FDI_RX_IMR(pipe);
2895         temp = I915_READ(reg);
2896         temp &= ~FDI_RX_SYMBOL_LOCK;
2897         temp &= ~FDI_RX_BIT_LOCK;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(150);
2902
2903         /* enable CPU FDI TX and PCH FDI RX */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2907         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2908         temp &= ~FDI_LINK_TRAIN_NONE;
2909         temp |= FDI_LINK_TRAIN_PATTERN_1;
2910         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2911         /* SNB-B */
2912         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2913         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2914
2915         I915_WRITE(FDI_RX_MISC(pipe),
2916                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2917
2918         reg = FDI_RX_CTL(pipe);
2919         temp = I915_READ(reg);
2920         if (HAS_PCH_CPT(dev)) {
2921                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2922                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2923         } else {
2924                 temp &= ~FDI_LINK_TRAIN_NONE;
2925                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         }
2927         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2928
2929         POSTING_READ(reg);
2930         udelay(150);
2931
2932         for (i = 0; i < 4; i++) {
2933                 reg = FDI_TX_CTL(pipe);
2934                 temp = I915_READ(reg);
2935                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936                 temp |= snb_b_fdi_train_param[i];
2937                 I915_WRITE(reg, temp);
2938
2939                 POSTING_READ(reg);
2940                 udelay(500);
2941
2942                 for (retry = 0; retry < 5; retry++) {
2943                         reg = FDI_RX_IIR(pipe);
2944                         temp = I915_READ(reg);
2945                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2946                         if (temp & FDI_RX_BIT_LOCK) {
2947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2948                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2949                                 break;
2950                         }
2951                         udelay(50);
2952                 }
2953                 if (retry < 5)
2954                         break;
2955         }
2956         if (i == 4)
2957                 DRM_ERROR("FDI train 1 fail!\n");
2958
2959         /* Train 2 */
2960         reg = FDI_TX_CTL(pipe);
2961         temp = I915_READ(reg);
2962         temp &= ~FDI_LINK_TRAIN_NONE;
2963         temp |= FDI_LINK_TRAIN_PATTERN_2;
2964         if (IS_GEN6(dev)) {
2965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966                 /* SNB-B */
2967                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968         }
2969         I915_WRITE(reg, temp);
2970
2971         reg = FDI_RX_CTL(pipe);
2972         temp = I915_READ(reg);
2973         if (HAS_PCH_CPT(dev)) {
2974                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2976         } else {
2977                 temp &= ~FDI_LINK_TRAIN_NONE;
2978                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         }
2980         I915_WRITE(reg, temp);
2981
2982         POSTING_READ(reg);
2983         udelay(150);
2984
2985         for (i = 0; i < 4; i++) {
2986                 reg = FDI_TX_CTL(pipe);
2987                 temp = I915_READ(reg);
2988                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2989                 temp |= snb_b_fdi_train_param[i];
2990                 I915_WRITE(reg, temp);
2991
2992                 POSTING_READ(reg);
2993                 udelay(500);
2994
2995                 for (retry = 0; retry < 5; retry++) {
2996                         reg = FDI_RX_IIR(pipe);
2997                         temp = I915_READ(reg);
2998                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2999                         if (temp & FDI_RX_SYMBOL_LOCK) {
3000                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3001                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3002                                 break;
3003                         }
3004                         udelay(50);
3005                 }
3006                 if (retry < 5)
3007                         break;
3008         }
3009         if (i == 4)
3010                 DRM_ERROR("FDI train 2 fail!\n");
3011
3012         DRM_DEBUG_KMS("FDI train done.\n");
3013 }
3014
3015 /* Manual link training for Ivy Bridge A0 parts */
3016 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3017 {
3018         struct drm_device *dev = crtc->dev;
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021         int pipe = intel_crtc->pipe;
3022         u32 reg, temp, i, j;
3023
3024         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025            for train result */
3026         reg = FDI_RX_IMR(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~FDI_RX_SYMBOL_LOCK;
3029         temp &= ~FDI_RX_BIT_LOCK;
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3036                       I915_READ(FDI_RX_IIR(pipe)));
3037
3038         /* Try each vswing and preemphasis setting twice before moving on */
3039         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3040                 /* disable first in case we need to retry */
3041                 reg = FDI_TX_CTL(pipe);
3042                 temp = I915_READ(reg);
3043                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3044                 temp &= ~FDI_TX_ENABLE;
3045                 I915_WRITE(reg, temp);
3046
3047                 reg = FDI_RX_CTL(pipe);
3048                 temp = I915_READ(reg);
3049                 temp &= ~FDI_LINK_TRAIN_AUTO;
3050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051                 temp &= ~FDI_RX_ENABLE;
3052                 I915_WRITE(reg, temp);
3053
3054                 /* enable CPU FDI TX and PCH FDI RX */
3055                 reg = FDI_TX_CTL(pipe);
3056                 temp = I915_READ(reg);
3057                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3060                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061                 temp |= snb_b_fdi_train_param[j/2];
3062                 temp |= FDI_COMPOSITE_SYNC;
3063                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3064
3065                 I915_WRITE(FDI_RX_MISC(pipe),
3066                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3067
3068                 reg = FDI_RX_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3071                 temp |= FDI_COMPOSITE_SYNC;
3072                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3073
3074                 POSTING_READ(reg);
3075                 udelay(1); /* should be 0.5us */
3076
3077                 for (i = 0; i < 4; i++) {
3078                         reg = FDI_RX_IIR(pipe);
3079                         temp = I915_READ(reg);
3080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                         if (temp & FDI_RX_BIT_LOCK ||
3083                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3084                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3086                                               i);
3087                                 break;
3088                         }
3089                         udelay(1); /* should be 0.5us */
3090                 }
3091                 if (i == 4) {
3092                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3093                         continue;
3094                 }
3095
3096                 /* Train 2 */
3097                 reg = FDI_TX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3100                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3101                 I915_WRITE(reg, temp);
3102
3103                 reg = FDI_RX_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3107                 I915_WRITE(reg, temp);
3108
3109                 POSTING_READ(reg);
3110                 udelay(2); /* should be 1.5us */
3111
3112                 for (i = 0; i < 4; i++) {
3113                         reg = FDI_RX_IIR(pipe);
3114                         temp = I915_READ(reg);
3115                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3116
3117                         if (temp & FDI_RX_SYMBOL_LOCK ||
3118                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3119                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3120                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3121                                               i);
3122                                 goto train_done;
3123                         }
3124                         udelay(2); /* should be 1.5us */
3125                 }
3126                 if (i == 4)
3127                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3128         }
3129
3130 train_done:
3131         DRM_DEBUG_KMS("FDI train done.\n");
3132 }
3133
3134 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3135 {
3136         struct drm_device *dev = intel_crtc->base.dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp;
3140
3141
3142         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3146         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3147         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3148         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(200);
3152
3153         /* Switch from Rawclk to PCDclk */
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp | FDI_PCDCLK);
3156
3157         POSTING_READ(reg);
3158         udelay(200);
3159
3160         /* Enable CPU FDI TX PLL, always on for Ironlake */
3161         reg = FDI_TX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3164                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3165
3166                 POSTING_READ(reg);
3167                 udelay(100);
3168         }
3169 }
3170
3171 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3172 {
3173         struct drm_device *dev = intel_crtc->base.dev;
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         int pipe = intel_crtc->pipe;
3176         u32 reg, temp;
3177
3178         /* Switch from PCDclk to Rawclk */
3179         reg = FDI_RX_CTL(pipe);
3180         temp = I915_READ(reg);
3181         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3182
3183         /* Disable CPU FDI TX PLL */
3184         reg = FDI_TX_CTL(pipe);
3185         temp = I915_READ(reg);
3186         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3187
3188         POSTING_READ(reg);
3189         udelay(100);
3190
3191         reg = FDI_RX_CTL(pipe);
3192         temp = I915_READ(reg);
3193         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3194
3195         /* Wait for the clocks to turn off. */
3196         POSTING_READ(reg);
3197         udelay(100);
3198 }
3199
3200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         u32 reg, temp;
3207
3208         /* disable CPU FDI tx and PCH FDI rx */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3212         POSTING_READ(reg);
3213
3214         reg = FDI_RX_CTL(pipe);
3215         temp = I915_READ(reg);
3216         temp &= ~(0x7 << 16);
3217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3219
3220         POSTING_READ(reg);
3221         udelay(100);
3222
3223         /* Ironlake workaround, disable clock pointer after downing FDI */
3224         if (HAS_PCH_IBX(dev)) {
3225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3226         }
3227
3228         /* still set train pattern 1 */
3229         reg = FDI_TX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         temp &= ~FDI_LINK_TRAIN_NONE;
3232         temp |= FDI_LINK_TRAIN_PATTERN_1;
3233         I915_WRITE(reg, temp);
3234
3235         reg = FDI_RX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (HAS_PCH_CPT(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3239                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3243         }
3244         /* BPC in FDI rx is consistent with that in PIPECONF */
3245         temp &= ~(0x07 << 16);
3246         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3247         I915_WRITE(reg, temp);
3248
3249         POSTING_READ(reg);
3250         udelay(100);
3251 }
3252
3253 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3254 {
3255         struct intel_crtc *crtc;
3256
3257         /* Note that we don't need to be called with mode_config.lock here
3258          * as our list of CRTC objects is static for the lifetime of the
3259          * device and so cannot disappear as we iterate. Similarly, we can
3260          * happily treat the predicates as racy, atomic checks as userspace
3261          * cannot claim and pin a new fb without at least acquring the
3262          * struct_mutex and so serialising with us.
3263          */
3264         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3265                 if (atomic_read(&crtc->unpin_work_count) == 0)
3266                         continue;
3267
3268                 if (crtc->unpin_work)
3269                         intel_wait_for_vblank(dev, crtc->pipe);
3270
3271                 return true;
3272         }
3273
3274         return false;
3275 }
3276
3277 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282         if (crtc->primary->fb == NULL)
3283                 return;
3284
3285         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3286
3287         wait_event(dev_priv->pending_flip_queue,
3288                    !intel_crtc_has_pending_flip(crtc));
3289
3290         mutex_lock(&dev->struct_mutex);
3291         intel_finish_fb(crtc->primary->fb);
3292         mutex_unlock(&dev->struct_mutex);
3293 }
3294
3295 /* Program iCLKIP clock to the desired frequency */
3296 static void lpt_program_iclkip(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3301         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3302         u32 temp;
3303
3304         mutex_lock(&dev_priv->dpio_lock);
3305
3306         /* It is necessary to ungate the pixclk gate prior to programming
3307          * the divisors, and gate it back when it is done.
3308          */
3309         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3310
3311         /* Disable SSCCTL */
3312         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3313                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3314                                 SBI_SSCCTL_DISABLE,
3315                         SBI_ICLK);
3316
3317         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3318         if (clock == 20000) {
3319                 auxdiv = 1;
3320                 divsel = 0x41;
3321                 phaseinc = 0x20;
3322         } else {
3323                 /* The iCLK virtual clock root frequency is in MHz,
3324                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3325                  * divisors, it is necessary to divide one by another, so we
3326                  * convert the virtual clock precision to KHz here for higher
3327                  * precision.
3328                  */
3329                 u32 iclk_virtual_root_freq = 172800 * 1000;
3330                 u32 iclk_pi_range = 64;
3331                 u32 desired_divisor, msb_divisor_value, pi_value;
3332
3333                 desired_divisor = (iclk_virtual_root_freq / clock);
3334                 msb_divisor_value = desired_divisor / iclk_pi_range;
3335                 pi_value = desired_divisor % iclk_pi_range;
3336
3337                 auxdiv = 0;
3338                 divsel = msb_divisor_value - 2;
3339                 phaseinc = pi_value;
3340         }
3341
3342         /* This should not happen with any sane values */
3343         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3344                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3345         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3346                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3347
3348         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3349                         clock,
3350                         auxdiv,
3351                         divsel,
3352                         phasedir,
3353                         phaseinc);
3354
3355         /* Program SSCDIVINTPHASE6 */
3356         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3357         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3358         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3359         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3360         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3361         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3362         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3363         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3364
3365         /* Program SSCAUXDIV */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3367         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3368         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3369         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3370
3371         /* Enable modulator and associated divider */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3373         temp &= ~SBI_SSCCTL_DISABLE;
3374         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3375
3376         /* Wait for initialization time */
3377         udelay(24);
3378
3379         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3380
3381         mutex_unlock(&dev_priv->dpio_lock);
3382 }
3383
3384 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3385                                                 enum pipe pch_transcoder)
3386 {
3387         struct drm_device *dev = crtc->base.dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3390
3391         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3392                    I915_READ(HTOTAL(cpu_transcoder)));
3393         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3394                    I915_READ(HBLANK(cpu_transcoder)));
3395         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3396                    I915_READ(HSYNC(cpu_transcoder)));
3397
3398         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3399                    I915_READ(VTOTAL(cpu_transcoder)));
3400         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3401                    I915_READ(VBLANK(cpu_transcoder)));
3402         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3403                    I915_READ(VSYNC(cpu_transcoder)));
3404         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3405                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3406 }
3407
3408 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         uint32_t temp;
3412
3413         temp = I915_READ(SOUTH_CHICKEN1);
3414         if (temp & FDI_BC_BIFURCATION_SELECT)
3415                 return;
3416
3417         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3418         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3419
3420         temp |= FDI_BC_BIFURCATION_SELECT;
3421         DRM_DEBUG_KMS("enabling fdi C rx\n");
3422         I915_WRITE(SOUTH_CHICKEN1, temp);
3423         POSTING_READ(SOUTH_CHICKEN1);
3424 }
3425
3426 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3427 {
3428         struct drm_device *dev = intel_crtc->base.dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431         switch (intel_crtc->pipe) {
3432         case PIPE_A:
3433                 break;
3434         case PIPE_B:
3435                 if (intel_crtc->config.fdi_lanes > 2)
3436                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3437                 else
3438                         cpt_enable_fdi_bc_bifurcation(dev);
3439
3440                 break;
3441         case PIPE_C:
3442                 cpt_enable_fdi_bc_bifurcation(dev);
3443
3444                 break;
3445         default:
3446                 BUG();
3447         }
3448 }
3449
3450 /*
3451  * Enable PCH resources required for PCH ports:
3452  *   - PCH PLLs
3453  *   - FDI training & RX/TX
3454  *   - update transcoder timings
3455  *   - DP transcoding bits
3456  *   - transcoder
3457  */
3458 static void ironlake_pch_enable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         int pipe = intel_crtc->pipe;
3464         u32 reg, temp;
3465
3466         assert_pch_transcoder_disabled(dev_priv, pipe);
3467
3468         if (IS_IVYBRIDGE(dev))
3469                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3470
3471         /* Write the TU size bits before fdi link training, so that error
3472          * detection works. */
3473         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3474                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3475
3476         /* For PCH output, training FDI link */
3477         dev_priv->display.fdi_link_train(crtc);
3478
3479         /* We need to program the right clock selection before writing the pixel
3480          * mutliplier into the DPLL. */
3481         if (HAS_PCH_CPT(dev)) {
3482                 u32 sel;
3483
3484                 temp = I915_READ(PCH_DPLL_SEL);
3485                 temp |= TRANS_DPLL_ENABLE(pipe);
3486                 sel = TRANS_DPLLB_SEL(pipe);
3487                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3488                         temp |= sel;
3489                 else
3490                         temp &= ~sel;
3491                 I915_WRITE(PCH_DPLL_SEL, temp);
3492         }
3493
3494         /* XXX: pch pll's can be enabled any time before we enable the PCH
3495          * transcoder, and we actually should do this to not upset any PCH
3496          * transcoder that already use the clock when we share it.
3497          *
3498          * Note that enable_shared_dpll tries to do the right thing, but
3499          * get_shared_dpll unconditionally resets the pll - we need that to have
3500          * the right LVDS enable sequence. */
3501         ironlake_enable_shared_dpll(intel_crtc);
3502
3503         /* set transcoder timing, panel must allow it */
3504         assert_panel_unlocked(dev_priv, pipe);
3505         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3506
3507         intel_fdi_normal_train(crtc);
3508
3509         /* For PCH DP, enable TRANS_DP_CTL */
3510         if (HAS_PCH_CPT(dev) &&
3511             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3512              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3513                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3514                 reg = TRANS_DP_CTL(pipe);
3515                 temp = I915_READ(reg);
3516                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3517                           TRANS_DP_SYNC_MASK |
3518                           TRANS_DP_BPC_MASK);
3519                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3520                          TRANS_DP_ENH_FRAMING);
3521                 temp |= bpc << 9; /* same format but at 11:9 */
3522
3523                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3524                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3525                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3526                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3527
3528                 switch (intel_trans_dp_port_sel(crtc)) {
3529                 case PCH_DP_B:
3530                         temp |= TRANS_DP_PORT_SEL_B;
3531                         break;
3532                 case PCH_DP_C:
3533                         temp |= TRANS_DP_PORT_SEL_C;
3534                         break;
3535                 case PCH_DP_D:
3536                         temp |= TRANS_DP_PORT_SEL_D;
3537                         break;
3538                 default:
3539                         BUG();
3540                 }
3541
3542                 I915_WRITE(reg, temp);
3543         }
3544
3545         ironlake_enable_pch_transcoder(dev_priv, pipe);
3546 }
3547
3548 static void lpt_pch_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3554
3555         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3556
3557         lpt_program_iclkip(crtc);
3558
3559         /* Set transcoder timing. */
3560         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3561
3562         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3563 }
3564
3565 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3566 {
3567         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3568
3569         if (pll == NULL)
3570                 return;
3571
3572         if (pll->refcount == 0) {
3573                 WARN(1, "bad %s refcount\n", pll->name);
3574                 return;
3575         }
3576
3577         if (--pll->refcount == 0) {
3578                 WARN_ON(pll->on);
3579                 WARN_ON(pll->active);
3580         }
3581
3582         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3583 }
3584
3585 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3586 {
3587         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3588         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3589         enum intel_dpll_id i;
3590
3591         if (pll) {
3592                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3593                               crtc->base.base.id, pll->name);
3594                 intel_put_shared_dpll(crtc);
3595         }
3596
3597         if (HAS_PCH_IBX(dev_priv->dev)) {
3598                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3599                 i = (enum intel_dpll_id) crtc->pipe;
3600                 pll = &dev_priv->shared_dplls[i];
3601
3602                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3603                               crtc->base.base.id, pll->name);
3604
3605                 goto found;
3606         }
3607
3608         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3609                 pll = &dev_priv->shared_dplls[i];
3610
3611                 /* Only want to check enabled timings first */
3612                 if (pll->refcount == 0)
3613                         continue;
3614
3615                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3616                            sizeof(pll->hw_state)) == 0) {
3617                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3618                                       crtc->base.base.id,
3619                                       pll->name, pll->refcount, pll->active);
3620
3621                         goto found;
3622                 }
3623         }
3624
3625         /* Ok no matching timings, maybe there's a free one? */
3626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627                 pll = &dev_priv->shared_dplls[i];
3628                 if (pll->refcount == 0) {
3629                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3630                                       crtc->base.base.id, pll->name);
3631                         goto found;
3632                 }
3633         }
3634
3635         return NULL;
3636
3637 found:
3638         crtc->config.shared_dpll = i;
3639         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3640                          pipe_name(crtc->pipe));
3641
3642         if (pll->active == 0) {
3643                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3644                        sizeof(pll->hw_state));
3645
3646                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3647                 WARN_ON(pll->on);
3648                 assert_shared_dpll_disabled(dev_priv, pll);
3649
3650                 pll->mode_set(dev_priv, pll);
3651         }
3652         pll->refcount++;
3653
3654         return pll;
3655 }
3656
3657 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660         int dslreg = PIPEDSL(pipe);
3661         u32 temp;
3662
3663         temp = I915_READ(dslreg);
3664         udelay(500);
3665         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3666                 if (wait_for(I915_READ(dslreg) != temp, 5))
3667                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3668         }
3669 }
3670
3671 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3672 {
3673         struct drm_device *dev = crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         int pipe = crtc->pipe;
3676
3677         if (crtc->config.pch_pfit.enabled) {
3678                 /* Force use of hard-coded filter coefficients
3679                  * as some pre-programmed values are broken,
3680                  * e.g. x201.
3681                  */
3682                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3683                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3684                                                  PF_PIPE_SEL_IVB(pipe));
3685                 else
3686                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3687                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3688                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3689         }
3690 }
3691
3692 static void intel_enable_planes(struct drm_crtc *crtc)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3696         struct drm_plane *plane;
3697         struct intel_plane *intel_plane;
3698
3699         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3700                 intel_plane = to_intel_plane(plane);
3701                 if (intel_plane->pipe == pipe)
3702                         intel_plane_restore(&intel_plane->base);
3703         }
3704 }
3705
3706 static void intel_disable_planes(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3710         struct drm_plane *plane;
3711         struct intel_plane *intel_plane;
3712
3713         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3714                 intel_plane = to_intel_plane(plane);
3715                 if (intel_plane->pipe == pipe)
3716                         intel_plane_disable(&intel_plane->base);
3717         }
3718 }
3719
3720 void hsw_enable_ips(struct intel_crtc *crtc)
3721 {
3722         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3723
3724         if (!crtc->config.ips_enabled)
3725                 return;
3726
3727         /* We can only enable IPS after we enable a plane and wait for a vblank.
3728          * We guarantee that the plane is enabled by calling intel_enable_ips
3729          * only after intel_enable_plane. And intel_enable_plane already waits
3730          * for a vblank, so all we need to do here is to enable the IPS bit. */
3731         assert_plane_enabled(dev_priv, crtc->plane);
3732         if (IS_BROADWELL(crtc->base.dev)) {
3733                 mutex_lock(&dev_priv->rps.hw_lock);
3734                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3735                 mutex_unlock(&dev_priv->rps.hw_lock);
3736                 /* Quoting Art Runyan: "its not safe to expect any particular
3737                  * value in IPS_CTL bit 31 after enabling IPS through the
3738                  * mailbox." Moreover, the mailbox may return a bogus state,
3739                  * so we need to just enable it and continue on.
3740                  */
3741         } else {
3742                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3743                 /* The bit only becomes 1 in the next vblank, so this wait here
3744                  * is essentially intel_wait_for_vblank. If we don't have this
3745                  * and don't wait for vblanks until the end of crtc_enable, then
3746                  * the HW state readout code will complain that the expected
3747                  * IPS_CTL value is not the one we read. */
3748                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3749                         DRM_ERROR("Timed out waiting for IPS enable\n");
3750         }
3751 }
3752
3753 void hsw_disable_ips(struct intel_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757
3758         if (!crtc->config.ips_enabled)
3759                 return;
3760
3761         assert_plane_enabled(dev_priv, crtc->plane);
3762         if (IS_BROADWELL(dev)) {
3763                 mutex_lock(&dev_priv->rps.hw_lock);
3764                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3765                 mutex_unlock(&dev_priv->rps.hw_lock);
3766                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3767                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3768                         DRM_ERROR("Timed out waiting for IPS disable\n");
3769         } else {
3770                 I915_WRITE(IPS_CTL, 0);
3771                 POSTING_READ(IPS_CTL);
3772         }
3773
3774         /* We need to wait for a vblank before we can disable the plane. */
3775         intel_wait_for_vblank(dev, crtc->pipe);
3776 }
3777
3778 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3779 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         enum pipe pipe = intel_crtc->pipe;
3785         int palreg = PALETTE(pipe);
3786         int i;
3787         bool reenable_ips = false;
3788
3789         /* The clocks have to be on to load the palette. */
3790         if (!crtc->enabled || !intel_crtc->active)
3791                 return;
3792
3793         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3794                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3795                         assert_dsi_pll_enabled(dev_priv);
3796                 else
3797                         assert_pll_enabled(dev_priv, pipe);
3798         }
3799
3800         /* use legacy palette for Ironlake */
3801         if (HAS_PCH_SPLIT(dev))
3802                 palreg = LGC_PALETTE(pipe);
3803
3804         /* Workaround : Do not read or write the pipe palette/gamma data while
3805          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3806          */
3807         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3808             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3809              GAMMA_MODE_MODE_SPLIT)) {
3810                 hsw_disable_ips(intel_crtc);
3811                 reenable_ips = true;
3812         }
3813
3814         for (i = 0; i < 256; i++) {
3815                 I915_WRITE(palreg + 4 * i,
3816                            (intel_crtc->lut_r[i] << 16) |
3817                            (intel_crtc->lut_g[i] << 8) |
3818                            intel_crtc->lut_b[i]);
3819         }
3820
3821         if (reenable_ips)
3822                 hsw_enable_ips(intel_crtc);
3823 }
3824
3825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3826 {
3827         if (!enable && intel_crtc->overlay) {
3828                 struct drm_device *dev = intel_crtc->base.dev;
3829                 struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831                 mutex_lock(&dev->struct_mutex);
3832                 dev_priv->mm.interruptible = false;
3833                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3834                 dev_priv->mm.interruptible = true;
3835                 mutex_unlock(&dev->struct_mutex);
3836         }
3837
3838         /* Let userspace switch the overlay on again. In most cases userspace
3839          * has to recompute where to put it anyway.
3840          */
3841 }
3842
3843 /**
3844  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3845  * cursor plane briefly if not already running after enabling the display
3846  * plane.
3847  * This workaround avoids occasional blank screens when self refresh is
3848  * enabled.
3849  */
3850 static void
3851 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3852 {
3853         u32 cntl = I915_READ(CURCNTR(pipe));
3854
3855         if ((cntl & CURSOR_MODE) == 0) {
3856                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3857
3858                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3859                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3860                 intel_wait_for_vblank(dev_priv->dev, pipe);
3861                 I915_WRITE(CURCNTR(pipe), cntl);
3862                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3863                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3864         }
3865 }
3866
3867 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3868 {
3869         struct drm_device *dev = crtc->dev;
3870         struct drm_i915_private *dev_priv = dev->dev_private;
3871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872         int pipe = intel_crtc->pipe;
3873         int plane = intel_crtc->plane;
3874
3875         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3876         intel_enable_planes(crtc);
3877         /* The fixup needs to happen before cursor is enabled */
3878         if (IS_G4X(dev))
3879                 g4x_fixup_plane(dev_priv, pipe);
3880         intel_crtc_update_cursor(crtc, true);
3881         intel_crtc_dpms_overlay(intel_crtc, true);
3882
3883         hsw_enable_ips(intel_crtc);
3884
3885         mutex_lock(&dev->struct_mutex);
3886         intel_update_fbc(dev);
3887         mutex_unlock(&dev->struct_mutex);
3888 }
3889
3890 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3891 {
3892         struct drm_device *dev = crtc->dev;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895         int pipe = intel_crtc->pipe;
3896         int plane = intel_crtc->plane;
3897
3898         intel_crtc_wait_for_pending_flips(crtc);
3899         drm_vblank_off(dev, pipe);
3900
3901         if (dev_priv->fbc.plane == plane)
3902                 intel_disable_fbc(dev);
3903
3904         hsw_disable_ips(intel_crtc);
3905
3906         intel_crtc_dpms_overlay(intel_crtc, false);
3907         intel_crtc_update_cursor(crtc, false);
3908         intel_disable_planes(crtc);
3909         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3910 }
3911
3912 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         struct intel_encoder *encoder;
3918         int pipe = intel_crtc->pipe;
3919
3920         WARN_ON(!crtc->enabled);
3921
3922         if (intel_crtc->active)
3923                 return;
3924
3925         intel_crtc->active = true;
3926
3927         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3928         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->pre_enable)
3932                         encoder->pre_enable(encoder);
3933
3934         if (intel_crtc->config.has_pch_encoder) {
3935                 /* Note: FDI PLL enabling _must_ be done before we enable the
3936                  * cpu pipes, hence this is separate from all the other fdi/pch
3937                  * enabling. */
3938                 ironlake_fdi_pll_enable(intel_crtc);
3939         } else {
3940                 assert_fdi_tx_disabled(dev_priv, pipe);
3941                 assert_fdi_rx_disabled(dev_priv, pipe);
3942         }
3943
3944         ironlake_pfit_enable(intel_crtc);
3945
3946         /*
3947          * On ILK+ LUT must be loaded before the pipe is running but with
3948          * clocks enabled
3949          */
3950         intel_crtc_load_lut(crtc);
3951
3952         intel_update_watermarks(crtc);
3953         intel_enable_pipe(intel_crtc);
3954
3955         if (intel_crtc->config.has_pch_encoder)
3956                 ironlake_pch_enable(crtc);
3957
3958         for_each_encoder_on_crtc(dev, crtc, encoder)
3959                 encoder->enable(encoder);
3960
3961         if (HAS_PCH_CPT(dev))
3962                 cpt_verify_modeset(dev, intel_crtc->pipe);
3963
3964         intel_crtc_enable_planes(crtc);
3965
3966         /*
3967          * There seems to be a race in PCH platform hw (at least on some
3968          * outputs) where an enabled pipe still completes any pageflip right
3969          * away (as if the pipe is off) instead of waiting for vblank. As soon
3970          * as the first vblank happend, everything works as expected. Hence just
3971          * wait for one vblank before returning to avoid strange things
3972          * happening.
3973          */
3974         intel_wait_for_vblank(dev, intel_crtc->pipe);
3975 }
3976
3977 /* IPS only exists on ULT machines and is tied to pipe A. */
3978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3979 {
3980         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3981 }
3982
3983 /*
3984  * This implements the workaround described in the "notes" section of the mode
3985  * set sequence documentation. When going from no pipes or single pipe to
3986  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3987  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3988  */
3989 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3990 {
3991         struct drm_device *dev = crtc->base.dev;
3992         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3993
3994         /* We want to get the other_active_crtc only if there's only 1 other
3995          * active crtc. */
3996         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3997                 if (!crtc_it->active || crtc_it == crtc)
3998                         continue;
3999
4000                 if (other_active_crtc)
4001                         return;
4002
4003                 other_active_crtc = crtc_it;
4004         }
4005         if (!other_active_crtc)
4006                 return;
4007
4008         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4009         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4010 }
4011
4012 static void haswell_crtc_enable(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017         struct intel_encoder *encoder;
4018         int pipe = intel_crtc->pipe;
4019
4020         WARN_ON(!crtc->enabled);
4021
4022         if (intel_crtc->active)
4023                 return;
4024
4025         intel_crtc->active = true;
4026
4027         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028         if (intel_crtc->config.has_pch_encoder)
4029                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4030
4031         if (intel_crtc->config.has_pch_encoder)
4032                 dev_priv->display.fdi_link_train(crtc);
4033
4034         for_each_encoder_on_crtc(dev, crtc, encoder)
4035                 if (encoder->pre_enable)
4036                         encoder->pre_enable(encoder);
4037
4038         intel_ddi_enable_pipe_clock(intel_crtc);
4039
4040         ironlake_pfit_enable(intel_crtc);
4041
4042         /*
4043          * On ILK+ LUT must be loaded before the pipe is running but with
4044          * clocks enabled
4045          */
4046         intel_crtc_load_lut(crtc);
4047
4048         intel_ddi_set_pipe_settings(crtc);
4049         intel_ddi_enable_transcoder_func(crtc);
4050
4051         intel_update_watermarks(crtc);
4052         intel_enable_pipe(intel_crtc);
4053
4054         if (intel_crtc->config.has_pch_encoder)
4055                 lpt_pch_enable(crtc);
4056
4057         for_each_encoder_on_crtc(dev, crtc, encoder) {
4058                 encoder->enable(encoder);
4059                 intel_opregion_notify_encoder(encoder, true);
4060         }
4061
4062         /* If we change the relative order between pipe/planes enabling, we need
4063          * to change the workaround. */
4064         haswell_mode_set_planes_workaround(intel_crtc);
4065         intel_crtc_enable_planes(crtc);
4066 }
4067
4068 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4069 {
4070         struct drm_device *dev = crtc->base.dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072         int pipe = crtc->pipe;
4073
4074         /* To avoid upsetting the power well on haswell only disable the pfit if
4075          * it's in use. The hw state code will make sure we get this right. */
4076         if (crtc->config.pch_pfit.enabled) {
4077                 I915_WRITE(PF_CTL(pipe), 0);
4078                 I915_WRITE(PF_WIN_POS(pipe), 0);
4079                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4080         }
4081 }
4082
4083 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         struct intel_encoder *encoder;
4089         int pipe = intel_crtc->pipe;
4090         u32 reg, temp;
4091
4092         if (!intel_crtc->active)
4093                 return;
4094
4095         intel_crtc_disable_planes(crtc);
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder)
4098                 encoder->disable(encoder);
4099
4100         if (intel_crtc->config.has_pch_encoder)
4101                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4102
4103         intel_disable_pipe(dev_priv, pipe);
4104
4105         ironlake_pfit_disable(intel_crtc);
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder)
4108                 if (encoder->post_disable)
4109                         encoder->post_disable(encoder);
4110
4111         if (intel_crtc->config.has_pch_encoder) {
4112                 ironlake_fdi_disable(crtc);
4113
4114                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4115                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4116
4117                 if (HAS_PCH_CPT(dev)) {
4118                         /* disable TRANS_DP_CTL */
4119                         reg = TRANS_DP_CTL(pipe);
4120                         temp = I915_READ(reg);
4121                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4122                                   TRANS_DP_PORT_SEL_MASK);
4123                         temp |= TRANS_DP_PORT_SEL_NONE;
4124                         I915_WRITE(reg, temp);
4125
4126                         /* disable DPLL_SEL */
4127                         temp = I915_READ(PCH_DPLL_SEL);
4128                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4129                         I915_WRITE(PCH_DPLL_SEL, temp);
4130                 }
4131
4132                 /* disable PCH DPLL */
4133                 intel_disable_shared_dpll(intel_crtc);
4134
4135                 ironlake_fdi_pll_disable(intel_crtc);
4136         }
4137
4138         intel_crtc->active = false;
4139         intel_update_watermarks(crtc);
4140
4141         mutex_lock(&dev->struct_mutex);
4142         intel_update_fbc(dev);
4143         mutex_unlock(&dev->struct_mutex);
4144 }
4145
4146 static void haswell_crtc_disable(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         struct intel_encoder *encoder;
4152         int pipe = intel_crtc->pipe;
4153         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4154
4155         if (!intel_crtc->active)
4156                 return;
4157
4158         intel_crtc_disable_planes(crtc);
4159
4160         for_each_encoder_on_crtc(dev, crtc, encoder) {
4161                 intel_opregion_notify_encoder(encoder, false);
4162                 encoder->disable(encoder);
4163         }
4164
4165         if (intel_crtc->config.has_pch_encoder)
4166                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4167         intel_disable_pipe(dev_priv, pipe);
4168
4169         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4170
4171         ironlake_pfit_disable(intel_crtc);
4172
4173         intel_ddi_disable_pipe_clock(intel_crtc);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->post_disable)
4177                         encoder->post_disable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 lpt_disable_pch_transcoder(dev_priv);
4181                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4182                 intel_ddi_fdi_disable(crtc);
4183         }
4184
4185         intel_crtc->active = false;
4186         intel_update_watermarks(crtc);
4187
4188         mutex_lock(&dev->struct_mutex);
4189         intel_update_fbc(dev);
4190         mutex_unlock(&dev->struct_mutex);
4191 }
4192
4193 static void ironlake_crtc_off(struct drm_crtc *crtc)
4194 {
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         intel_put_shared_dpll(intel_crtc);
4197 }
4198
4199 static void haswell_crtc_off(struct drm_crtc *crtc)
4200 {
4201         intel_ddi_put_crtc_pll(crtc);
4202 }
4203
4204 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->base.dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc_config *pipe_config = &crtc->config;
4209
4210         if (!crtc->config.gmch_pfit.control)
4211                 return;
4212
4213         /*
4214          * The panel fitter should only be adjusted whilst the pipe is disabled,
4215          * according to register description and PRM.
4216          */
4217         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4218         assert_pipe_disabled(dev_priv, crtc->pipe);
4219
4220         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4221         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4222
4223         /* Border color in case we don't scale up to the full screen. Black by
4224          * default, change to something else for debugging. */
4225         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4226 }
4227
4228 #define for_each_power_domain(domain, mask)                             \
4229         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4230                 if ((1 << (domain)) & (mask))
4231
4232 enum intel_display_power_domain
4233 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4234 {
4235         struct drm_device *dev = intel_encoder->base.dev;
4236         struct intel_digital_port *intel_dig_port;
4237
4238         switch (intel_encoder->type) {
4239         case INTEL_OUTPUT_UNKNOWN:
4240                 /* Only DDI platforms should ever use this output type */
4241                 WARN_ON_ONCE(!HAS_DDI(dev));
4242         case INTEL_OUTPUT_DISPLAYPORT:
4243         case INTEL_OUTPUT_HDMI:
4244         case INTEL_OUTPUT_EDP:
4245                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4246                 switch (intel_dig_port->port) {
4247                 case PORT_A:
4248                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4249                 case PORT_B:
4250                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4251                 case PORT_C:
4252                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4253                 case PORT_D:
4254                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4255                 default:
4256                         WARN_ON_ONCE(1);
4257                         return POWER_DOMAIN_PORT_OTHER;
4258                 }
4259         case INTEL_OUTPUT_ANALOG:
4260                 return POWER_DOMAIN_PORT_CRT;
4261         case INTEL_OUTPUT_DSI:
4262                 return POWER_DOMAIN_PORT_DSI;
4263         default:
4264                 return POWER_DOMAIN_PORT_OTHER;
4265         }
4266 }
4267
4268 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct intel_encoder *intel_encoder;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         enum pipe pipe = intel_crtc->pipe;
4274         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4275         unsigned long mask;
4276         enum transcoder transcoder;
4277
4278         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4279
4280         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4281         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4282         if (pfit_enabled)
4283                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4284
4285         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4286                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4287
4288         return mask;
4289 }
4290
4291 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4292                                   bool enable)
4293 {
4294         if (dev_priv->power_domains.init_power_on == enable)
4295                 return;
4296
4297         if (enable)
4298                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4299         else
4300                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4301
4302         dev_priv->power_domains.init_power_on = enable;
4303 }
4304
4305 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4309         struct intel_crtc *crtc;
4310
4311         /*
4312          * First get all needed power domains, then put all unneeded, to avoid
4313          * any unnecessary toggling of the power wells.
4314          */
4315         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4316                 enum intel_display_power_domain domain;
4317
4318                 if (!crtc->base.enabled)
4319                         continue;
4320
4321                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4322
4323                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4324                         intel_display_power_get(dev_priv, domain);
4325         }
4326
4327         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4328                 enum intel_display_power_domain domain;
4329
4330                 for_each_power_domain(domain, crtc->enabled_power_domains)
4331                         intel_display_power_put(dev_priv, domain);
4332
4333                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4334         }
4335
4336         intel_display_set_init_power(dev_priv, false);
4337 }
4338
4339 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4340 {
4341         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4342
4343         /* Obtain SKU information */
4344         mutex_lock(&dev_priv->dpio_lock);
4345         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4346                 CCK_FUSE_HPLL_FREQ_MASK;
4347         mutex_unlock(&dev_priv->dpio_lock);
4348
4349         return vco_freq[hpll_freq];
4350 }
4351
4352 /* Adjust CDclk dividers to allow high res or save power if possible */
4353 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         u32 val, cmd;
4357
4358         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4359         dev_priv->vlv_cdclk_freq = cdclk;
4360
4361         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4362                 cmd = 2;
4363         else if (cdclk == 266)
4364                 cmd = 1;
4365         else
4366                 cmd = 0;
4367
4368         mutex_lock(&dev_priv->rps.hw_lock);
4369         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4370         val &= ~DSPFREQGUAR_MASK;
4371         val |= (cmd << DSPFREQGUAR_SHIFT);
4372         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4373         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4374                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4375                      50)) {
4376                 DRM_ERROR("timed out waiting for CDclk change\n");
4377         }
4378         mutex_unlock(&dev_priv->rps.hw_lock);
4379
4380         if (cdclk == 400) {
4381                 u32 divider, vco;
4382
4383                 vco = valleyview_get_vco(dev_priv);
4384                 divider = ((vco << 1) / cdclk) - 1;
4385
4386                 mutex_lock(&dev_priv->dpio_lock);
4387                 /* adjust cdclk divider */
4388                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4389                 val &= ~0xf;
4390                 val |= divider;
4391                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4392                 mutex_unlock(&dev_priv->dpio_lock);
4393         }
4394
4395         mutex_lock(&dev_priv->dpio_lock);
4396         /* adjust self-refresh exit latency value */
4397         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4398         val &= ~0x7f;
4399
4400         /*
4401          * For high bandwidth configs, we set a higher latency in the bunit
4402          * so that the core display fetch happens in time to avoid underruns.
4403          */
4404         if (cdclk == 400)
4405                 val |= 4500 / 250; /* 4.5 usec */
4406         else
4407                 val |= 3000 / 250; /* 3.0 usec */
4408         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4409         mutex_unlock(&dev_priv->dpio_lock);
4410
4411         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4412         intel_i2c_reset(dev);
4413 }
4414
4415 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4416 {
4417         int cur_cdclk, vco;
4418         int divider;
4419
4420         vco = valleyview_get_vco(dev_priv);
4421
4422         mutex_lock(&dev_priv->dpio_lock);
4423         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4424         mutex_unlock(&dev_priv->dpio_lock);
4425
4426         divider &= 0xf;
4427
4428         cur_cdclk = (vco << 1) / (divider + 1);
4429
4430         return cur_cdclk;
4431 }
4432
4433 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4434                                  int max_pixclk)
4435 {
4436         /*
4437          * Really only a few cases to deal with, as only 4 CDclks are supported:
4438          *   200MHz
4439          *   267MHz
4440          *   320MHz
4441          *   400MHz
4442          * So we check to see whether we're above 90% of the lower bin and
4443          * adjust if needed.
4444          */
4445         if (max_pixclk > 288000) {
4446                 return 400;
4447         } else if (max_pixclk > 240000) {
4448                 return 320;
4449         } else
4450                 return 266;
4451         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4452 }
4453
4454 /* compute the max pixel clock for new configuration */
4455 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4456 {
4457         struct drm_device *dev = dev_priv->dev;
4458         struct intel_crtc *intel_crtc;
4459         int max_pixclk = 0;
4460
4461         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4462                             base.head) {
4463                 if (intel_crtc->new_enabled)
4464                         max_pixclk = max(max_pixclk,
4465                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4466         }
4467
4468         return max_pixclk;
4469 }
4470
4471 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4472                                             unsigned *prepare_pipes)
4473 {
4474         struct drm_i915_private *dev_priv = dev->dev_private;
4475         struct intel_crtc *intel_crtc;
4476         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4477
4478         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4479             dev_priv->vlv_cdclk_freq)
4480                 return;
4481
4482         /* disable/enable all currently active pipes while we change cdclk */
4483         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4484                             base.head)
4485                 if (intel_crtc->base.enabled)
4486                         *prepare_pipes |= (1 << intel_crtc->pipe);
4487 }
4488
4489 static void valleyview_modeset_global_resources(struct drm_device *dev)
4490 {
4491         struct drm_i915_private *dev_priv = dev->dev_private;
4492         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4493         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4494
4495         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4496                 valleyview_set_cdclk(dev, req_cdclk);
4497         modeset_update_crtc_power_domains(dev);
4498 }
4499
4500 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4501 {
4502         struct drm_device *dev = crtc->dev;
4503         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4504         struct intel_encoder *encoder;
4505         int pipe = intel_crtc->pipe;
4506         bool is_dsi;
4507
4508         WARN_ON(!crtc->enabled);
4509
4510         if (intel_crtc->active)
4511                 return;
4512
4513         intel_crtc->active = true;
4514
4515         for_each_encoder_on_crtc(dev, crtc, encoder)
4516                 if (encoder->pre_pll_enable)
4517                         encoder->pre_pll_enable(encoder);
4518
4519         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4520
4521         if (!is_dsi) {
4522                 if (IS_CHERRYVIEW(dev))
4523                         chv_enable_pll(intel_crtc);
4524                 else
4525                         vlv_enable_pll(intel_crtc);
4526         }
4527
4528         for_each_encoder_on_crtc(dev, crtc, encoder)
4529                 if (encoder->pre_enable)
4530                         encoder->pre_enable(encoder);
4531
4532         i9xx_pfit_enable(intel_crtc);
4533
4534         intel_crtc_load_lut(crtc);
4535
4536         intel_update_watermarks(crtc);
4537         intel_enable_pipe(intel_crtc);
4538         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4539
4540         for_each_encoder_on_crtc(dev, crtc, encoder)
4541                 encoder->enable(encoder);
4542
4543         intel_crtc_enable_planes(crtc);
4544 }
4545
4546 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4547 {
4548         struct drm_device *dev = crtc->dev;
4549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4550         struct intel_encoder *encoder;
4551         int pipe = intel_crtc->pipe;
4552
4553         WARN_ON(!crtc->enabled);
4554
4555         if (intel_crtc->active)
4556                 return;
4557
4558         intel_crtc->active = true;
4559
4560         for_each_encoder_on_crtc(dev, crtc, encoder)
4561                 if (encoder->pre_enable)
4562                         encoder->pre_enable(encoder);
4563
4564         i9xx_enable_pll(intel_crtc);
4565
4566         i9xx_pfit_enable(intel_crtc);
4567
4568         intel_crtc_load_lut(crtc);
4569
4570         intel_update_watermarks(crtc);
4571         intel_enable_pipe(intel_crtc);
4572         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4573
4574         for_each_encoder_on_crtc(dev, crtc, encoder)
4575                 encoder->enable(encoder);
4576
4577         intel_crtc_enable_planes(crtc);
4578 }
4579
4580 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4581 {
4582         struct drm_device *dev = crtc->base.dev;
4583         struct drm_i915_private *dev_priv = dev->dev_private;
4584
4585         if (!crtc->config.gmch_pfit.control)
4586                 return;
4587
4588         assert_pipe_disabled(dev_priv, crtc->pipe);
4589
4590         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4591                          I915_READ(PFIT_CONTROL));
4592         I915_WRITE(PFIT_CONTROL, 0);
4593 }
4594
4595 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4596 {
4597         struct drm_device *dev = crtc->dev;
4598         struct drm_i915_private *dev_priv = dev->dev_private;
4599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4600         struct intel_encoder *encoder;
4601         int pipe = intel_crtc->pipe;
4602
4603         if (!intel_crtc->active)
4604                 return;
4605
4606         intel_crtc_disable_planes(crtc);
4607
4608         for_each_encoder_on_crtc(dev, crtc, encoder)
4609                 encoder->disable(encoder);
4610
4611         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4612         intel_disable_pipe(dev_priv, pipe);
4613
4614         i9xx_pfit_disable(intel_crtc);
4615
4616         for_each_encoder_on_crtc(dev, crtc, encoder)
4617                 if (encoder->post_disable)
4618                         encoder->post_disable(encoder);
4619
4620         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4621                 if (IS_CHERRYVIEW(dev))
4622                         chv_disable_pll(dev_priv, pipe);
4623                 else if (IS_VALLEYVIEW(dev))
4624                         vlv_disable_pll(dev_priv, pipe);
4625                 else
4626                         i9xx_disable_pll(dev_priv, pipe);
4627         }
4628
4629         intel_crtc->active = false;
4630         intel_update_watermarks(crtc);
4631
4632         intel_update_fbc(dev);
4633 }
4634
4635 static void i9xx_crtc_off(struct drm_crtc *crtc)
4636 {
4637 }
4638
4639 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4640                                     bool enabled)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct drm_i915_master_private *master_priv;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         int pipe = intel_crtc->pipe;
4646
4647         if (!dev->primary->master)
4648                 return;
4649
4650         master_priv = dev->primary->master->driver_priv;
4651         if (!master_priv->sarea_priv)
4652                 return;
4653
4654         switch (pipe) {
4655         case 0:
4656                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4657                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4658                 break;
4659         case 1:
4660                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4661                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4662                 break;
4663         default:
4664                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4665                 break;
4666         }
4667 }
4668
4669 /**
4670  * Sets the power management mode of the pipe and plane.
4671  */
4672 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4673 {
4674         struct drm_device *dev = crtc->dev;
4675         struct drm_i915_private *dev_priv = dev->dev_private;
4676         struct intel_encoder *intel_encoder;
4677         bool enable = false;
4678
4679         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4680                 enable |= intel_encoder->connectors_active;
4681
4682         if (enable)
4683                 dev_priv->display.crtc_enable(crtc);
4684         else
4685                 dev_priv->display.crtc_disable(crtc);
4686
4687         intel_crtc_update_sarea(crtc, enable);
4688 }
4689
4690 static void intel_crtc_disable(struct drm_crtc *crtc)
4691 {
4692         struct drm_device *dev = crtc->dev;
4693         struct drm_connector *connector;
4694         struct drm_i915_private *dev_priv = dev->dev_private;
4695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696
4697         /* crtc should still be enabled when we disable it. */
4698         WARN_ON(!crtc->enabled);
4699
4700         dev_priv->display.crtc_disable(crtc);
4701         intel_crtc->eld_vld = false;
4702         intel_crtc_update_sarea(crtc, false);
4703         dev_priv->display.off(crtc);
4704
4705         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4706         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4707         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4708
4709         if (crtc->primary->fb) {
4710                 mutex_lock(&dev->struct_mutex);
4711                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4712                 mutex_unlock(&dev->struct_mutex);
4713                 crtc->primary->fb = NULL;
4714         }
4715
4716         /* Update computed state. */
4717         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4718                 if (!connector->encoder || !connector->encoder->crtc)
4719                         continue;
4720
4721                 if (connector->encoder->crtc != crtc)
4722                         continue;
4723
4724                 connector->dpms = DRM_MODE_DPMS_OFF;
4725                 to_intel_encoder(connector->encoder)->connectors_active = false;
4726         }
4727 }
4728
4729 void intel_encoder_destroy(struct drm_encoder *encoder)
4730 {
4731         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4732
4733         drm_encoder_cleanup(encoder);
4734         kfree(intel_encoder);
4735 }
4736
4737 /* Simple dpms helper for encoders with just one connector, no cloning and only
4738  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4739  * state of the entire output pipe. */
4740 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4741 {
4742         if (mode == DRM_MODE_DPMS_ON) {
4743                 encoder->connectors_active = true;
4744
4745                 intel_crtc_update_dpms(encoder->base.crtc);
4746         } else {
4747                 encoder->connectors_active = false;
4748
4749                 intel_crtc_update_dpms(encoder->base.crtc);
4750         }
4751 }
4752
4753 /* Cross check the actual hw state with our own modeset state tracking (and it's
4754  * internal consistency). */
4755 static void intel_connector_check_state(struct intel_connector *connector)
4756 {
4757         if (connector->get_hw_state(connector)) {
4758                 struct intel_encoder *encoder = connector->encoder;
4759                 struct drm_crtc *crtc;
4760                 bool encoder_enabled;
4761                 enum pipe pipe;
4762
4763                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4764                               connector->base.base.id,
4765                               drm_get_connector_name(&connector->base));
4766
4767                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4768                      "wrong connector dpms state\n");
4769                 WARN(connector->base.encoder != &encoder->base,
4770                      "active connector not linked to encoder\n");
4771                 WARN(!encoder->connectors_active,
4772                      "encoder->connectors_active not set\n");
4773
4774                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4775                 WARN(!encoder_enabled, "encoder not enabled\n");
4776                 if (WARN_ON(!encoder->base.crtc))
4777                         return;
4778
4779                 crtc = encoder->base.crtc;
4780
4781                 WARN(!crtc->enabled, "crtc not enabled\n");
4782                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4783                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4784                      "encoder active on the wrong pipe\n");
4785         }
4786 }
4787
4788 /* Even simpler default implementation, if there's really no special case to
4789  * consider. */
4790 void intel_connector_dpms(struct drm_connector *connector, int mode)
4791 {
4792         /* All the simple cases only support two dpms states. */
4793         if (mode != DRM_MODE_DPMS_ON)
4794                 mode = DRM_MODE_DPMS_OFF;
4795
4796         if (mode == connector->dpms)
4797                 return;
4798
4799         connector->dpms = mode;
4800
4801         /* Only need to change hw state when actually enabled */
4802         if (connector->encoder)
4803                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4804
4805         intel_modeset_check_state(connector->dev);
4806 }
4807
4808 /* Simple connector->get_hw_state implementation for encoders that support only
4809  * one connector and no cloning and hence the encoder state determines the state
4810  * of the connector. */
4811 bool intel_connector_get_hw_state(struct intel_connector *connector)
4812 {
4813         enum pipe pipe = 0;
4814         struct intel_encoder *encoder = connector->encoder;
4815
4816         return encoder->get_hw_state(encoder, &pipe);
4817 }
4818
4819 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4820                                      struct intel_crtc_config *pipe_config)
4821 {
4822         struct drm_i915_private *dev_priv = dev->dev_private;
4823         struct intel_crtc *pipe_B_crtc =
4824                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4825
4826         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4827                       pipe_name(pipe), pipe_config->fdi_lanes);
4828         if (pipe_config->fdi_lanes > 4) {
4829                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4830                               pipe_name(pipe), pipe_config->fdi_lanes);
4831                 return false;
4832         }
4833
4834         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4835                 if (pipe_config->fdi_lanes > 2) {
4836                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4837                                       pipe_config->fdi_lanes);
4838                         return false;
4839                 } else {
4840                         return true;
4841                 }
4842         }
4843
4844         if (INTEL_INFO(dev)->num_pipes == 2)
4845                 return true;
4846
4847         /* Ivybridge 3 pipe is really complicated */
4848         switch (pipe) {
4849         case PIPE_A:
4850                 return true;
4851         case PIPE_B:
4852                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4853                     pipe_config->fdi_lanes > 2) {
4854                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4855                                       pipe_name(pipe), pipe_config->fdi_lanes);
4856                         return false;
4857                 }
4858                 return true;
4859         case PIPE_C:
4860                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4861                     pipe_B_crtc->config.fdi_lanes <= 2) {
4862                         if (pipe_config->fdi_lanes > 2) {
4863                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4864                                               pipe_name(pipe), pipe_config->fdi_lanes);
4865                                 return false;
4866                         }
4867                 } else {
4868                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4869                         return false;
4870                 }
4871                 return true;
4872         default:
4873                 BUG();
4874         }
4875 }
4876
4877 #define RETRY 1
4878 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4879                                        struct intel_crtc_config *pipe_config)
4880 {
4881         struct drm_device *dev = intel_crtc->base.dev;
4882         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4883         int lane, link_bw, fdi_dotclock;
4884         bool setup_ok, needs_recompute = false;
4885
4886 retry:
4887         /* FDI is a binary signal running at ~2.7GHz, encoding
4888          * each output octet as 10 bits. The actual frequency
4889          * is stored as a divider into a 100MHz clock, and the
4890          * mode pixel clock is stored in units of 1KHz.
4891          * Hence the bw of each lane in terms of the mode signal
4892          * is:
4893          */
4894         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4895
4896         fdi_dotclock = adjusted_mode->crtc_clock;
4897
4898         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4899                                            pipe_config->pipe_bpp);
4900
4901         pipe_config->fdi_lanes = lane;
4902
4903         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4904                                link_bw, &pipe_config->fdi_m_n);
4905
4906         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4907                                             intel_crtc->pipe, pipe_config);
4908         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4909                 pipe_config->pipe_bpp -= 2*3;
4910                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4911                               pipe_config->pipe_bpp);
4912                 needs_recompute = true;
4913                 pipe_config->bw_constrained = true;
4914
4915                 goto retry;
4916         }
4917
4918         if (needs_recompute)
4919                 return RETRY;
4920
4921         return setup_ok ? 0 : -EINVAL;
4922 }
4923
4924 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4925                                    struct intel_crtc_config *pipe_config)
4926 {
4927         pipe_config->ips_enabled = i915.enable_ips &&
4928                                    hsw_crtc_supports_ips(crtc) &&
4929                                    pipe_config->pipe_bpp <= 24;
4930 }
4931
4932 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4933                                      struct intel_crtc_config *pipe_config)
4934 {
4935         struct drm_device *dev = crtc->base.dev;
4936         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4937
4938         /* FIXME should check pixel clock limits on all platforms */
4939         if (INTEL_INFO(dev)->gen < 4) {
4940                 struct drm_i915_private *dev_priv = dev->dev_private;
4941                 int clock_limit =
4942                         dev_priv->display.get_display_clock_speed(dev);
4943
4944                 /*
4945                  * Enable pixel doubling when the dot clock
4946                  * is > 90% of the (display) core speed.
4947                  *
4948                  * GDG double wide on either pipe,
4949                  * otherwise pipe A only.
4950                  */
4951                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4952                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4953                         clock_limit *= 2;
4954                         pipe_config->double_wide = true;
4955                 }
4956
4957                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4958                         return -EINVAL;
4959         }
4960
4961         /*
4962          * Pipe horizontal size must be even in:
4963          * - DVO ganged mode
4964          * - LVDS dual channel mode
4965          * - Double wide pipe
4966          */
4967         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4968              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4969                 pipe_config->pipe_src_w &= ~1;
4970
4971         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4972          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4973          */
4974         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4975                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4976                 return -EINVAL;
4977
4978         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4979                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4980         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4981                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4982                  * for lvds. */
4983                 pipe_config->pipe_bpp = 8*3;
4984         }
4985
4986         if (HAS_IPS(dev))
4987                 hsw_compute_ips_config(crtc, pipe_config);
4988
4989         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4990          * clock survives for now. */
4991         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4992                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4993
4994         if (pipe_config->has_pch_encoder)
4995                 return ironlake_fdi_compute_config(crtc, pipe_config);
4996
4997         return 0;
4998 }
4999
5000 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5001 {
5002         return 400000; /* FIXME */
5003 }
5004
5005 static int i945_get_display_clock_speed(struct drm_device *dev)
5006 {
5007         return 400000;
5008 }
5009
5010 static int i915_get_display_clock_speed(struct drm_device *dev)
5011 {
5012         return 333000;
5013 }
5014
5015 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5016 {
5017         return 200000;
5018 }
5019
5020 static int pnv_get_display_clock_speed(struct drm_device *dev)
5021 {
5022         u16 gcfgc = 0;
5023
5024         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5025
5026         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5027         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5028                 return 267000;
5029         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5030                 return 333000;
5031         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5032                 return 444000;
5033         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5034                 return 200000;
5035         default:
5036                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5037         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5038                 return 133000;
5039         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5040                 return 167000;
5041         }
5042 }
5043
5044 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5045 {
5046         u16 gcfgc = 0;
5047
5048         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5049
5050         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5051                 return 133000;
5052         else {
5053                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5054                 case GC_DISPLAY_CLOCK_333_MHZ:
5055                         return 333000;
5056                 default:
5057                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5058                         return 190000;
5059                 }
5060         }
5061 }
5062
5063 static int i865_get_display_clock_speed(struct drm_device *dev)
5064 {
5065         return 266000;
5066 }
5067
5068 static int i855_get_display_clock_speed(struct drm_device *dev)
5069 {
5070         u16 hpllcc = 0;
5071         /* Assume that the hardware is in the high speed state.  This
5072          * should be the default.
5073          */
5074         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5075         case GC_CLOCK_133_200:
5076         case GC_CLOCK_100_200:
5077                 return 200000;
5078         case GC_CLOCK_166_250:
5079                 return 250000;
5080         case GC_CLOCK_100_133:
5081                 return 133000;
5082         }
5083
5084         /* Shouldn't happen */
5085         return 0;
5086 }
5087
5088 static int i830_get_display_clock_speed(struct drm_device *dev)
5089 {
5090         return 133000;
5091 }
5092
5093 static void
5094 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5095 {
5096         while (*num > DATA_LINK_M_N_MASK ||
5097                *den > DATA_LINK_M_N_MASK) {
5098                 *num >>= 1;
5099                 *den >>= 1;
5100         }
5101 }
5102
5103 static void compute_m_n(unsigned int m, unsigned int n,
5104                         uint32_t *ret_m, uint32_t *ret_n)
5105 {
5106         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5107         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5108         intel_reduce_m_n_ratio(ret_m, ret_n);
5109 }
5110
5111 void
5112 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5113                        int pixel_clock, int link_clock,
5114                        struct intel_link_m_n *m_n)
5115 {
5116         m_n->tu = 64;
5117
5118         compute_m_n(bits_per_pixel * pixel_clock,
5119                     link_clock * nlanes * 8,
5120                     &m_n->gmch_m, &m_n->gmch_n);
5121
5122         compute_m_n(pixel_clock, link_clock,
5123                     &m_n->link_m, &m_n->link_n);
5124 }
5125
5126 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5127 {
5128         if (i915.panel_use_ssc >= 0)
5129                 return i915.panel_use_ssc != 0;
5130         return dev_priv->vbt.lvds_use_ssc
5131                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5132 }
5133
5134 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5135 {
5136         struct drm_device *dev = crtc->dev;
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         int refclk;
5139
5140         if (IS_VALLEYVIEW(dev)) {
5141                 refclk = 100000;
5142         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5143             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5144                 refclk = dev_priv->vbt.lvds_ssc_freq;
5145                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5146         } else if (!IS_GEN2(dev)) {
5147                 refclk = 96000;
5148         } else {
5149                 refclk = 48000;
5150         }
5151
5152         return refclk;
5153 }
5154
5155 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5156 {
5157         return (1 << dpll->n) << 16 | dpll->m2;
5158 }
5159
5160 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5161 {
5162         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5163 }
5164
5165 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5166                                      intel_clock_t *reduced_clock)
5167 {
5168         struct drm_device *dev = crtc->base.dev;
5169         struct drm_i915_private *dev_priv = dev->dev_private;
5170         int pipe = crtc->pipe;
5171         u32 fp, fp2 = 0;
5172
5173         if (IS_PINEVIEW(dev)) {
5174                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5175                 if (reduced_clock)
5176                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5177         } else {
5178                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5179                 if (reduced_clock)
5180                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5181         }
5182
5183         I915_WRITE(FP0(pipe), fp);
5184         crtc->config.dpll_hw_state.fp0 = fp;
5185
5186         crtc->lowfreq_avail = false;
5187         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5188             reduced_clock && i915.powersave) {
5189                 I915_WRITE(FP1(pipe), fp2);
5190                 crtc->config.dpll_hw_state.fp1 = fp2;
5191                 crtc->lowfreq_avail = true;
5192         } else {
5193                 I915_WRITE(FP1(pipe), fp);
5194                 crtc->config.dpll_hw_state.fp1 = fp;
5195         }
5196 }
5197
5198 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5199                 pipe)
5200 {
5201         u32 reg_val;
5202
5203         /*
5204          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5205          * and set it to a reasonable value instead.
5206          */
5207         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5208         reg_val &= 0xffffff00;
5209         reg_val |= 0x00000030;
5210         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5211
5212         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5213         reg_val &= 0x8cffffff;
5214         reg_val = 0x8c000000;
5215         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5216
5217         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5218         reg_val &= 0xffffff00;
5219         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5220
5221         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5222         reg_val &= 0x00ffffff;
5223         reg_val |= 0xb0000000;
5224         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5225 }
5226
5227 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5228                                          struct intel_link_m_n *m_n)
5229 {
5230         struct drm_device *dev = crtc->base.dev;
5231         struct drm_i915_private *dev_priv = dev->dev_private;
5232         int pipe = crtc->pipe;
5233
5234         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5235         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5236         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5237         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5238 }
5239
5240 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5241                                          struct intel_link_m_n *m_n)
5242 {
5243         struct drm_device *dev = crtc->base.dev;
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245         int pipe = crtc->pipe;
5246         enum transcoder transcoder = crtc->config.cpu_transcoder;
5247
5248         if (INTEL_INFO(dev)->gen >= 5) {
5249                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5250                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5251                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5252                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5253         } else {
5254                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5255                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5256                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5257                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5258         }
5259 }
5260
5261 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5262 {
5263         if (crtc->config.has_pch_encoder)
5264                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5265         else
5266                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5267 }
5268
5269 static void vlv_update_pll(struct intel_crtc *crtc)
5270 {
5271         struct drm_device *dev = crtc->base.dev;
5272         struct drm_i915_private *dev_priv = dev->dev_private;
5273         int pipe = crtc->pipe;
5274         u32 dpll, mdiv;
5275         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5276         u32 coreclk, reg_val, dpll_md;
5277
5278         mutex_lock(&dev_priv->dpio_lock);
5279
5280         bestn = crtc->config.dpll.n;
5281         bestm1 = crtc->config.dpll.m1;
5282         bestm2 = crtc->config.dpll.m2;
5283         bestp1 = crtc->config.dpll.p1;
5284         bestp2 = crtc->config.dpll.p2;
5285
5286         /* See eDP HDMI DPIO driver vbios notes doc */
5287
5288         /* PLL B needs special handling */
5289         if (pipe)
5290                 vlv_pllb_recal_opamp(dev_priv, pipe);
5291
5292         /* Set up Tx target for periodic Rcomp update */
5293         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5294
5295         /* Disable target IRef on PLL */
5296         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5297         reg_val &= 0x00ffffff;
5298         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5299
5300         /* Disable fast lock */
5301         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5302
5303         /* Set idtafcrecal before PLL is enabled */
5304         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5305         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5306         mdiv |= ((bestn << DPIO_N_SHIFT));
5307         mdiv |= (1 << DPIO_K_SHIFT);
5308
5309         /*
5310          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5311          * but we don't support that).
5312          * Note: don't use the DAC post divider as it seems unstable.
5313          */
5314         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5315         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5316
5317         mdiv |= DPIO_ENABLE_CALIBRATION;
5318         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5319
5320         /* Set HBR and RBR LPF coefficients */
5321         if (crtc->config.port_clock == 162000 ||
5322             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5323             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5324                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5325                                  0x009f0003);
5326         else
5327                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5328                                  0x00d0000f);
5329
5330         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5331             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5332                 /* Use SSC source */
5333                 if (!pipe)
5334                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5335                                          0x0df40000);
5336                 else
5337                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5338                                          0x0df70000);
5339         } else { /* HDMI or VGA */
5340                 /* Use bend source */
5341                 if (!pipe)
5342                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5343                                          0x0df70000);
5344                 else
5345                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5346                                          0x0df40000);
5347         }
5348
5349         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5350         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5351         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5352             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5353                 coreclk |= 0x01000000;
5354         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5355
5356         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5357
5358         /*
5359          * Enable DPIO clock input. We should never disable the reference
5360          * clock for pipe B, since VGA hotplug / manual detection depends
5361          * on it.
5362          */
5363         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5364                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5365         /* We should never disable this, set it here for state tracking */
5366         if (pipe == PIPE_B)
5367                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5368         dpll |= DPLL_VCO_ENABLE;
5369         crtc->config.dpll_hw_state.dpll = dpll;
5370
5371         dpll_md = (crtc->config.pixel_multiplier - 1)
5372                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5373         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5374
5375         mutex_unlock(&dev_priv->dpio_lock);
5376 }
5377
5378 static void chv_update_pll(struct intel_crtc *crtc)
5379 {
5380         struct drm_device *dev = crtc->base.dev;
5381         struct drm_i915_private *dev_priv = dev->dev_private;
5382         int pipe = crtc->pipe;
5383         int dpll_reg = DPLL(crtc->pipe);
5384         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5385         u32 val, loopfilter, intcoeff;
5386         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5387         int refclk;
5388
5389         mutex_lock(&dev_priv->dpio_lock);
5390
5391         bestn = crtc->config.dpll.n;
5392         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5393         bestm1 = crtc->config.dpll.m1;
5394         bestm2 = crtc->config.dpll.m2 >> 22;
5395         bestp1 = crtc->config.dpll.p1;
5396         bestp2 = crtc->config.dpll.p2;
5397
5398         /*
5399          * Enable Refclk and SSC
5400          */
5401         val = I915_READ(dpll_reg);
5402         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5403         I915_WRITE(dpll_reg, val);
5404
5405         /* Propagate soft reset to data lane reset */
5406         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5407         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5408         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5409
5410         /* Disable 10bit clock to display controller */
5411         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5412         val &= ~DPIO_DCLKP_EN;
5413         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5414
5415         /* p1 and p2 divider */
5416         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5417                         5 << DPIO_CHV_S1_DIV_SHIFT |
5418                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5419                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5420                         1 << DPIO_CHV_K_DIV_SHIFT);
5421
5422         /* Feedback post-divider - m2 */
5423         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5424
5425         /* Feedback refclk divider - n and m1 */
5426         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5427                         DPIO_CHV_M1_DIV_BY_2 |
5428                         1 << DPIO_CHV_N_DIV_SHIFT);
5429
5430         /* M2 fraction division */
5431         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5432
5433         /* M2 fraction division enable */
5434         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5435                        DPIO_CHV_FRAC_DIV_EN |
5436                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5437
5438         /* Loop filter */
5439         refclk = i9xx_get_refclk(&crtc->base, 0);
5440         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5441                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5442         if (refclk == 100000)
5443                 intcoeff = 11;
5444         else if (refclk == 38400)
5445                 intcoeff = 10;
5446         else
5447                 intcoeff = 9;
5448         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5449         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5450
5451         /* AFC Recal */
5452         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5453                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5454                         DPIO_AFC_RECAL);
5455
5456         mutex_unlock(&dev_priv->dpio_lock);
5457 }
5458
5459 static void i9xx_update_pll(struct intel_crtc *crtc,
5460                             intel_clock_t *reduced_clock,
5461                             int num_connectors)
5462 {
5463         struct drm_device *dev = crtc->base.dev;
5464         struct drm_i915_private *dev_priv = dev->dev_private;
5465         u32 dpll;
5466         bool is_sdvo;
5467         struct dpll *clock = &crtc->config.dpll;
5468
5469         i9xx_update_pll_dividers(crtc, reduced_clock);
5470
5471         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5472                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5473
5474         dpll = DPLL_VGA_MODE_DIS;
5475
5476         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5477                 dpll |= DPLLB_MODE_LVDS;
5478         else
5479                 dpll |= DPLLB_MODE_DAC_SERIAL;
5480
5481         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5482                 dpll |= (crtc->config.pixel_multiplier - 1)
5483                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5484         }
5485
5486         if (is_sdvo)
5487                 dpll |= DPLL_SDVO_HIGH_SPEED;
5488
5489         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5490                 dpll |= DPLL_SDVO_HIGH_SPEED;
5491
5492         /* compute bitmask from p1 value */
5493         if (IS_PINEVIEW(dev))
5494                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5495         else {
5496                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5497                 if (IS_G4X(dev) && reduced_clock)
5498                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5499         }
5500         switch (clock->p2) {
5501         case 5:
5502                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5503                 break;
5504         case 7:
5505                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5506                 break;
5507         case 10:
5508                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5509                 break;
5510         case 14:
5511                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5512                 break;
5513         }
5514         if (INTEL_INFO(dev)->gen >= 4)
5515                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5516
5517         if (crtc->config.sdvo_tv_clock)
5518                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5519         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5520                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5521                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5522         else
5523                 dpll |= PLL_REF_INPUT_DREFCLK;
5524
5525         dpll |= DPLL_VCO_ENABLE;
5526         crtc->config.dpll_hw_state.dpll = dpll;
5527
5528         if (INTEL_INFO(dev)->gen >= 4) {
5529                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5530                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5531                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5532         }
5533 }
5534
5535 static void i8xx_update_pll(struct intel_crtc *crtc,
5536                             intel_clock_t *reduced_clock,
5537                             int num_connectors)
5538 {
5539         struct drm_device *dev = crtc->base.dev;
5540         struct drm_i915_private *dev_priv = dev->dev_private;
5541         u32 dpll;
5542         struct dpll *clock = &crtc->config.dpll;
5543
5544         i9xx_update_pll_dividers(crtc, reduced_clock);
5545
5546         dpll = DPLL_VGA_MODE_DIS;
5547
5548         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5549                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5550         } else {
5551                 if (clock->p1 == 2)
5552                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5553                 else
5554                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5555                 if (clock->p2 == 4)
5556                         dpll |= PLL_P2_DIVIDE_BY_4;
5557         }
5558
5559         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5560                 dpll |= DPLL_DVO_2X_MODE;
5561
5562         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5563                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5564                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5565         else
5566                 dpll |= PLL_REF_INPUT_DREFCLK;
5567
5568         dpll |= DPLL_VCO_ENABLE;
5569         crtc->config.dpll_hw_state.dpll = dpll;
5570 }
5571
5572 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5573 {
5574         struct drm_device *dev = intel_crtc->base.dev;
5575         struct drm_i915_private *dev_priv = dev->dev_private;
5576         enum pipe pipe = intel_crtc->pipe;
5577         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5578         struct drm_display_mode *adjusted_mode =
5579                 &intel_crtc->config.adjusted_mode;
5580         uint32_t crtc_vtotal, crtc_vblank_end;
5581         int vsyncshift = 0;
5582
5583         /* We need to be careful not to changed the adjusted mode, for otherwise
5584          * the hw state checker will get angry at the mismatch. */
5585         crtc_vtotal = adjusted_mode->crtc_vtotal;
5586         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5587
5588         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5589                 /* the chip adds 2 halflines automatically */
5590                 crtc_vtotal -= 1;
5591                 crtc_vblank_end -= 1;
5592
5593                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5594                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5595                 else
5596                         vsyncshift = adjusted_mode->crtc_hsync_start -
5597                                 adjusted_mode->crtc_htotal / 2;
5598                 if (vsyncshift < 0)
5599                         vsyncshift += adjusted_mode->crtc_htotal;
5600         }
5601
5602         if (INTEL_INFO(dev)->gen > 3)
5603                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5604
5605         I915_WRITE(HTOTAL(cpu_transcoder),
5606                    (adjusted_mode->crtc_hdisplay - 1) |
5607                    ((adjusted_mode->crtc_htotal - 1) << 16));
5608         I915_WRITE(HBLANK(cpu_transcoder),
5609                    (adjusted_mode->crtc_hblank_start - 1) |
5610                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5611         I915_WRITE(HSYNC(cpu_transcoder),
5612                    (adjusted_mode->crtc_hsync_start - 1) |
5613                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5614
5615         I915_WRITE(VTOTAL(cpu_transcoder),
5616                    (adjusted_mode->crtc_vdisplay - 1) |
5617                    ((crtc_vtotal - 1) << 16));
5618         I915_WRITE(VBLANK(cpu_transcoder),
5619                    (adjusted_mode->crtc_vblank_start - 1) |
5620                    ((crtc_vblank_end - 1) << 16));
5621         I915_WRITE(VSYNC(cpu_transcoder),
5622                    (adjusted_mode->crtc_vsync_start - 1) |
5623                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5624
5625         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5626          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5627          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5628          * bits. */
5629         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5630             (pipe == PIPE_B || pipe == PIPE_C))
5631                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5632
5633         /* pipesrc controls the size that is scaled from, which should
5634          * always be the user's requested size.
5635          */
5636         I915_WRITE(PIPESRC(pipe),
5637                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5638                    (intel_crtc->config.pipe_src_h - 1));
5639 }
5640
5641 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5642                                    struct intel_crtc_config *pipe_config)
5643 {
5644         struct drm_device *dev = crtc->base.dev;
5645         struct drm_i915_private *dev_priv = dev->dev_private;
5646         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5647         uint32_t tmp;
5648
5649         tmp = I915_READ(HTOTAL(cpu_transcoder));
5650         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5651         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5652         tmp = I915_READ(HBLANK(cpu_transcoder));
5653         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5654         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5655         tmp = I915_READ(HSYNC(cpu_transcoder));
5656         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5657         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5658
5659         tmp = I915_READ(VTOTAL(cpu_transcoder));
5660         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5661         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5662         tmp = I915_READ(VBLANK(cpu_transcoder));
5663         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5664         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5665         tmp = I915_READ(VSYNC(cpu_transcoder));
5666         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5667         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5668
5669         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5670                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5671                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5672                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5673         }
5674
5675         tmp = I915_READ(PIPESRC(crtc->pipe));
5676         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5677         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5678
5679         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5680         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5681 }
5682
5683 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5684                                  struct intel_crtc_config *pipe_config)
5685 {
5686         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5687         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5688         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5689         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5690
5691         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5692         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5693         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5694         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5695
5696         mode->flags = pipe_config->adjusted_mode.flags;
5697
5698         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5699         mode->flags |= pipe_config->adjusted_mode.flags;
5700 }
5701
5702 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5703 {
5704         struct drm_device *dev = intel_crtc->base.dev;
5705         struct drm_i915_private *dev_priv = dev->dev_private;
5706         uint32_t pipeconf;
5707
5708         pipeconf = 0;
5709
5710         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5711             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5712                 pipeconf |= PIPECONF_ENABLE;
5713
5714         if (intel_crtc->config.double_wide)
5715                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5716
5717         /* only g4x and later have fancy bpc/dither controls */
5718         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5719                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5720                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5721                         pipeconf |= PIPECONF_DITHER_EN |
5722                                     PIPECONF_DITHER_TYPE_SP;
5723
5724                 switch (intel_crtc->config.pipe_bpp) {
5725                 case 18:
5726                         pipeconf |= PIPECONF_6BPC;
5727                         break;
5728                 case 24:
5729                         pipeconf |= PIPECONF_8BPC;
5730                         break;
5731                 case 30:
5732                         pipeconf |= PIPECONF_10BPC;
5733                         break;
5734                 default:
5735                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5736                         BUG();
5737                 }
5738         }
5739
5740         if (HAS_PIPE_CXSR(dev)) {
5741                 if (intel_crtc->lowfreq_avail) {
5742                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5743                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5744                 } else {
5745                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5746                 }
5747         }
5748
5749         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5750                 if (INTEL_INFO(dev)->gen < 4 ||
5751                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5752                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5753                 else
5754                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5755         } else
5756                 pipeconf |= PIPECONF_PROGRESSIVE;
5757
5758         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5759                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5760
5761         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5762         POSTING_READ(PIPECONF(intel_crtc->pipe));
5763 }
5764
5765 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5766                               int x, int y,
5767                               struct drm_framebuffer *fb)
5768 {
5769         struct drm_device *dev = crtc->dev;
5770         struct drm_i915_private *dev_priv = dev->dev_private;
5771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5772         int pipe = intel_crtc->pipe;
5773         int plane = intel_crtc->plane;
5774         int refclk, num_connectors = 0;
5775         intel_clock_t clock, reduced_clock;
5776         u32 dspcntr;
5777         bool ok, has_reduced_clock = false;
5778         bool is_lvds = false, is_dsi = false;
5779         struct intel_encoder *encoder;
5780         const intel_limit_t *limit;
5781         int ret;
5782
5783         for_each_encoder_on_crtc(dev, crtc, encoder) {
5784                 switch (encoder->type) {
5785                 case INTEL_OUTPUT_LVDS:
5786                         is_lvds = true;
5787                         break;
5788                 case INTEL_OUTPUT_DSI:
5789                         is_dsi = true;
5790                         break;
5791                 }
5792
5793                 num_connectors++;
5794         }
5795
5796         if (is_dsi)
5797                 goto skip_dpll;
5798
5799         if (!intel_crtc->config.clock_set) {
5800                 refclk = i9xx_get_refclk(crtc, num_connectors);
5801
5802                 /*
5803                  * Returns a set of divisors for the desired target clock with
5804                  * the given refclk, or FALSE.  The returned values represent
5805                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5806                  * 2) / p1 / p2.
5807                  */
5808                 limit = intel_limit(crtc, refclk);
5809                 ok = dev_priv->display.find_dpll(limit, crtc,
5810                                                  intel_crtc->config.port_clock,
5811                                                  refclk, NULL, &clock);
5812                 if (!ok) {
5813                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5814                         return -EINVAL;
5815                 }
5816
5817                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5818                         /*
5819                          * Ensure we match the reduced clock's P to the target
5820                          * clock.  If the clocks don't match, we can't switch
5821                          * the display clock by using the FP0/FP1. In such case
5822                          * we will disable the LVDS downclock feature.
5823                          */
5824                         has_reduced_clock =
5825                                 dev_priv->display.find_dpll(limit, crtc,
5826                                                             dev_priv->lvds_downclock,
5827                                                             refclk, &clock,
5828                                                             &reduced_clock);
5829                 }
5830                 /* Compat-code for transition, will disappear. */
5831                 intel_crtc->config.dpll.n = clock.n;
5832                 intel_crtc->config.dpll.m1 = clock.m1;
5833                 intel_crtc->config.dpll.m2 = clock.m2;
5834                 intel_crtc->config.dpll.p1 = clock.p1;
5835                 intel_crtc->config.dpll.p2 = clock.p2;
5836         }
5837
5838         if (IS_GEN2(dev)) {
5839                 i8xx_update_pll(intel_crtc,
5840                                 has_reduced_clock ? &reduced_clock : NULL,
5841                                 num_connectors);
5842         } else if (IS_CHERRYVIEW(dev)) {
5843                 chv_update_pll(intel_crtc);
5844         } else if (IS_VALLEYVIEW(dev)) {
5845                 vlv_update_pll(intel_crtc);
5846         } else {
5847                 i9xx_update_pll(intel_crtc,
5848                                 has_reduced_clock ? &reduced_clock : NULL,
5849                                 num_connectors);
5850         }
5851
5852 skip_dpll:
5853         /* Set up the display plane register */
5854         dspcntr = DISPPLANE_GAMMA_ENABLE;
5855
5856         if (!IS_VALLEYVIEW(dev)) {
5857                 if (pipe == 0)
5858                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5859                 else
5860                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5861         }
5862
5863         if (intel_crtc->config.has_dp_encoder)
5864                 intel_dp_set_m_n(intel_crtc);
5865
5866         intel_set_pipe_timings(intel_crtc);
5867
5868         /* pipesrc and dspsize control the size that is scaled from,
5869          * which should always be the user's requested size.
5870          */
5871         I915_WRITE(DSPSIZE(plane),
5872                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5873                    (intel_crtc->config.pipe_src_w - 1));
5874         I915_WRITE(DSPPOS(plane), 0);
5875
5876         i9xx_set_pipeconf(intel_crtc);
5877
5878         I915_WRITE(DSPCNTR(plane), dspcntr);
5879         POSTING_READ(DSPCNTR(plane));
5880
5881         ret = intel_pipe_set_base(crtc, x, y, fb);
5882
5883         return ret;
5884 }
5885
5886 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5887                                  struct intel_crtc_config *pipe_config)
5888 {
5889         struct drm_device *dev = crtc->base.dev;
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         uint32_t tmp;
5892
5893         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5894                 return;
5895
5896         tmp = I915_READ(PFIT_CONTROL);
5897         if (!(tmp & PFIT_ENABLE))
5898                 return;
5899
5900         /* Check whether the pfit is attached to our pipe. */
5901         if (INTEL_INFO(dev)->gen < 4) {
5902                 if (crtc->pipe != PIPE_B)
5903                         return;
5904         } else {
5905                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5906                         return;
5907         }
5908
5909         pipe_config->gmch_pfit.control = tmp;
5910         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5911         if (INTEL_INFO(dev)->gen < 5)
5912                 pipe_config->gmch_pfit.lvds_border_bits =
5913                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5914 }
5915
5916 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5917                                struct intel_crtc_config *pipe_config)
5918 {
5919         struct drm_device *dev = crtc->base.dev;
5920         struct drm_i915_private *dev_priv = dev->dev_private;
5921         int pipe = pipe_config->cpu_transcoder;
5922         intel_clock_t clock;
5923         u32 mdiv;
5924         int refclk = 100000;
5925
5926         mutex_lock(&dev_priv->dpio_lock);
5927         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5928         mutex_unlock(&dev_priv->dpio_lock);
5929
5930         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5931         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5932         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5933         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5934         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5935
5936         vlv_clock(refclk, &clock);
5937
5938         /* clock.dot is the fast clock */
5939         pipe_config->port_clock = clock.dot / 5;
5940 }
5941
5942 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5943                                   struct intel_plane_config *plane_config)
5944 {
5945         struct drm_device *dev = crtc->base.dev;
5946         struct drm_i915_private *dev_priv = dev->dev_private;
5947         u32 val, base, offset;
5948         int pipe = crtc->pipe, plane = crtc->plane;
5949         int fourcc, pixel_format;
5950         int aligned_height;
5951
5952         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5953         if (!crtc->base.primary->fb) {
5954                 DRM_DEBUG_KMS("failed to alloc fb\n");
5955                 return;
5956         }
5957
5958         val = I915_READ(DSPCNTR(plane));
5959
5960         if (INTEL_INFO(dev)->gen >= 4)
5961                 if (val & DISPPLANE_TILED)
5962                         plane_config->tiled = true;
5963
5964         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5965         fourcc = intel_format_to_fourcc(pixel_format);
5966         crtc->base.primary->fb->pixel_format = fourcc;
5967         crtc->base.primary->fb->bits_per_pixel =
5968                 drm_format_plane_cpp(fourcc, 0) * 8;
5969
5970         if (INTEL_INFO(dev)->gen >= 4) {
5971                 if (plane_config->tiled)
5972                         offset = I915_READ(DSPTILEOFF(plane));
5973                 else
5974                         offset = I915_READ(DSPLINOFF(plane));
5975                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5976         } else {
5977                 base = I915_READ(DSPADDR(plane));
5978         }
5979         plane_config->base = base;
5980
5981         val = I915_READ(PIPESRC(pipe));
5982         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5983         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5984
5985         val = I915_READ(DSPSTRIDE(pipe));
5986         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5987
5988         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5989                                             plane_config->tiled);
5990
5991         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5992                                    aligned_height, PAGE_SIZE);
5993
5994         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5995                       pipe, plane, crtc->base.primary->fb->width,
5996                       crtc->base.primary->fb->height,
5997                       crtc->base.primary->fb->bits_per_pixel, base,
5998                       crtc->base.primary->fb->pitches[0],
5999                       plane_config->size);
6000
6001 }
6002
6003 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6004                                struct intel_crtc_config *pipe_config)
6005 {
6006         struct drm_device *dev = crtc->base.dev;
6007         struct drm_i915_private *dev_priv = dev->dev_private;
6008         int pipe = pipe_config->cpu_transcoder;
6009         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6010         intel_clock_t clock;
6011         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6012         int refclk = 100000;
6013
6014         mutex_lock(&dev_priv->dpio_lock);
6015         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6016         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6017         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6018         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6019         mutex_unlock(&dev_priv->dpio_lock);
6020
6021         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6022         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6023         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6024         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6025         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6026
6027         chv_clock(refclk, &clock);
6028
6029         /* clock.dot is the fast clock */
6030         pipe_config->port_clock = clock.dot / 5;
6031 }
6032
6033 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6034                                  struct intel_crtc_config *pipe_config)
6035 {
6036         struct drm_device *dev = crtc->base.dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         uint32_t tmp;
6039
6040         if (!intel_display_power_enabled(dev_priv,
6041                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6042                 return false;
6043
6044         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6045         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6046
6047         tmp = I915_READ(PIPECONF(crtc->pipe));
6048         if (!(tmp & PIPECONF_ENABLE))
6049                 return false;
6050
6051         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6052                 switch (tmp & PIPECONF_BPC_MASK) {
6053                 case PIPECONF_6BPC:
6054                         pipe_config->pipe_bpp = 18;
6055                         break;
6056                 case PIPECONF_8BPC:
6057                         pipe_config->pipe_bpp = 24;
6058                         break;
6059                 case PIPECONF_10BPC:
6060                         pipe_config->pipe_bpp = 30;
6061                         break;
6062                 default:
6063                         break;
6064                 }
6065         }
6066
6067         if (INTEL_INFO(dev)->gen < 4)
6068                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6069
6070         intel_get_pipe_timings(crtc, pipe_config);
6071
6072         i9xx_get_pfit_config(crtc, pipe_config);
6073
6074         if (INTEL_INFO(dev)->gen >= 4) {
6075                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6076                 pipe_config->pixel_multiplier =
6077                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6078                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6079                 pipe_config->dpll_hw_state.dpll_md = tmp;
6080         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6081                 tmp = I915_READ(DPLL(crtc->pipe));
6082                 pipe_config->pixel_multiplier =
6083                         ((tmp & SDVO_MULTIPLIER_MASK)
6084                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6085         } else {
6086                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6087                  * port and will be fixed up in the encoder->get_config
6088                  * function. */
6089                 pipe_config->pixel_multiplier = 1;
6090         }
6091         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6092         if (!IS_VALLEYVIEW(dev)) {
6093                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6094                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6095         } else {
6096                 /* Mask out read-only status bits. */
6097                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6098                                                      DPLL_PORTC_READY_MASK |
6099                                                      DPLL_PORTB_READY_MASK);
6100         }
6101
6102         if (IS_CHERRYVIEW(dev))
6103                 chv_crtc_clock_get(crtc, pipe_config);
6104         else if (IS_VALLEYVIEW(dev))
6105                 vlv_crtc_clock_get(crtc, pipe_config);
6106         else
6107                 i9xx_crtc_clock_get(crtc, pipe_config);
6108
6109         return true;
6110 }
6111
6112 static void ironlake_init_pch_refclk(struct drm_device *dev)
6113 {
6114         struct drm_i915_private *dev_priv = dev->dev_private;
6115         struct drm_mode_config *mode_config = &dev->mode_config;
6116         struct intel_encoder *encoder;
6117         u32 val, final;
6118         bool has_lvds = false;
6119         bool has_cpu_edp = false;
6120         bool has_panel = false;
6121         bool has_ck505 = false;
6122         bool can_ssc = false;
6123
6124         /* We need to take the global config into account */
6125         list_for_each_entry(encoder, &mode_config->encoder_list,
6126                             base.head) {
6127                 switch (encoder->type) {
6128                 case INTEL_OUTPUT_LVDS:
6129                         has_panel = true;
6130                         has_lvds = true;
6131                         break;
6132                 case INTEL_OUTPUT_EDP:
6133                         has_panel = true;
6134                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6135                                 has_cpu_edp = true;
6136                         break;
6137                 }
6138         }
6139
6140         if (HAS_PCH_IBX(dev)) {
6141                 has_ck505 = dev_priv->vbt.display_clock_mode;
6142                 can_ssc = has_ck505;
6143         } else {
6144                 has_ck505 = false;
6145                 can_ssc = true;
6146         }
6147
6148         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6149                       has_panel, has_lvds, has_ck505);
6150
6151         /* Ironlake: try to setup display ref clock before DPLL
6152          * enabling. This is only under driver's control after
6153          * PCH B stepping, previous chipset stepping should be
6154          * ignoring this setting.
6155          */
6156         val = I915_READ(PCH_DREF_CONTROL);
6157
6158         /* As we must carefully and slowly disable/enable each source in turn,
6159          * compute the final state we want first and check if we need to
6160          * make any changes at all.
6161          */
6162         final = val;
6163         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6164         if (has_ck505)
6165                 final |= DREF_NONSPREAD_CK505_ENABLE;
6166         else
6167                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6168
6169         final &= ~DREF_SSC_SOURCE_MASK;
6170         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6171         final &= ~DREF_SSC1_ENABLE;
6172
6173         if (has_panel) {
6174                 final |= DREF_SSC_SOURCE_ENABLE;
6175
6176                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6177                         final |= DREF_SSC1_ENABLE;
6178
6179                 if (has_cpu_edp) {
6180                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6181                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6182                         else
6183                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6184                 } else
6185                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6186         } else {
6187                 final |= DREF_SSC_SOURCE_DISABLE;
6188                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6189         }
6190
6191         if (final == val)
6192                 return;
6193
6194         /* Always enable nonspread source */
6195         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6196
6197         if (has_ck505)
6198                 val |= DREF_NONSPREAD_CK505_ENABLE;
6199         else
6200                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6201
6202         if (has_panel) {
6203                 val &= ~DREF_SSC_SOURCE_MASK;
6204                 val |= DREF_SSC_SOURCE_ENABLE;
6205
6206                 /* SSC must be turned on before enabling the CPU output  */
6207                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6208                         DRM_DEBUG_KMS("Using SSC on panel\n");
6209                         val |= DREF_SSC1_ENABLE;
6210                 } else
6211                         val &= ~DREF_SSC1_ENABLE;
6212
6213                 /* Get SSC going before enabling the outputs */
6214                 I915_WRITE(PCH_DREF_CONTROL, val);
6215                 POSTING_READ(PCH_DREF_CONTROL);
6216                 udelay(200);
6217
6218                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6219
6220                 /* Enable CPU source on CPU attached eDP */
6221                 if (has_cpu_edp) {
6222                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6223                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6224                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6225                         }
6226                         else
6227                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6228                 } else
6229                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6230
6231                 I915_WRITE(PCH_DREF_CONTROL, val);
6232                 POSTING_READ(PCH_DREF_CONTROL);
6233                 udelay(200);
6234         } else {
6235                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6236
6237                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6238
6239                 /* Turn off CPU output */
6240                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6241
6242                 I915_WRITE(PCH_DREF_CONTROL, val);
6243                 POSTING_READ(PCH_DREF_CONTROL);
6244                 udelay(200);
6245
6246                 /* Turn off the SSC source */
6247                 val &= ~DREF_SSC_SOURCE_MASK;
6248                 val |= DREF_SSC_SOURCE_DISABLE;
6249
6250                 /* Turn off SSC1 */
6251                 val &= ~DREF_SSC1_ENABLE;
6252
6253                 I915_WRITE(PCH_DREF_CONTROL, val);
6254                 POSTING_READ(PCH_DREF_CONTROL);
6255                 udelay(200);
6256         }
6257
6258         BUG_ON(val != final);
6259 }
6260
6261 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6262 {
6263         uint32_t tmp;
6264
6265         tmp = I915_READ(SOUTH_CHICKEN2);
6266         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6267         I915_WRITE(SOUTH_CHICKEN2, tmp);
6268
6269         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6270                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6271                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6272
6273         tmp = I915_READ(SOUTH_CHICKEN2);
6274         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6275         I915_WRITE(SOUTH_CHICKEN2, tmp);
6276
6277         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6278                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6279                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6280 }
6281
6282 /* WaMPhyProgramming:hsw */
6283 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6284 {
6285         uint32_t tmp;
6286
6287         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6288         tmp &= ~(0xFF << 24);
6289         tmp |= (0x12 << 24);
6290         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6291
6292         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6293         tmp |= (1 << 11);
6294         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6295
6296         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6297         tmp |= (1 << 11);
6298         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6299
6300         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6301         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6302         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6303
6304         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6305         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6306         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6307
6308         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6309         tmp &= ~(7 << 13);
6310         tmp |= (5 << 13);
6311         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6312
6313         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6314         tmp &= ~(7 << 13);
6315         tmp |= (5 << 13);
6316         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6317
6318         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6319         tmp &= ~0xFF;
6320         tmp |= 0x1C;
6321         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6322
6323         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6324         tmp &= ~0xFF;
6325         tmp |= 0x1C;
6326         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6327
6328         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6329         tmp &= ~(0xFF << 16);
6330         tmp |= (0x1C << 16);
6331         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6332
6333         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6334         tmp &= ~(0xFF << 16);
6335         tmp |= (0x1C << 16);
6336         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6337
6338         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6339         tmp |= (1 << 27);
6340         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6341
6342         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6343         tmp |= (1 << 27);
6344         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6345
6346         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6347         tmp &= ~(0xF << 28);
6348         tmp |= (4 << 28);
6349         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6350
6351         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6352         tmp &= ~(0xF << 28);
6353         tmp |= (4 << 28);
6354         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6355 }
6356
6357 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6358  * Programming" based on the parameters passed:
6359  * - Sequence to enable CLKOUT_DP
6360  * - Sequence to enable CLKOUT_DP without spread
6361  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6362  */
6363 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6364                                  bool with_fdi)
6365 {
6366         struct drm_i915_private *dev_priv = dev->dev_private;
6367         uint32_t reg, tmp;
6368
6369         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6370                 with_spread = true;
6371         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6372                  with_fdi, "LP PCH doesn't have FDI\n"))
6373                 with_fdi = false;
6374
6375         mutex_lock(&dev_priv->dpio_lock);
6376
6377         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6378         tmp &= ~SBI_SSCCTL_DISABLE;
6379         tmp |= SBI_SSCCTL_PATHALT;
6380         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6381
6382         udelay(24);
6383
6384         if (with_spread) {
6385                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6386                 tmp &= ~SBI_SSCCTL_PATHALT;
6387                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6388
6389                 if (with_fdi) {
6390                         lpt_reset_fdi_mphy(dev_priv);
6391                         lpt_program_fdi_mphy(dev_priv);
6392                 }
6393         }
6394
6395         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6396                SBI_GEN0 : SBI_DBUFF0;
6397         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6398         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6399         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6400
6401         mutex_unlock(&dev_priv->dpio_lock);
6402 }
6403
6404 /* Sequence to disable CLKOUT_DP */
6405 static void lpt_disable_clkout_dp(struct drm_device *dev)
6406 {
6407         struct drm_i915_private *dev_priv = dev->dev_private;
6408         uint32_t reg, tmp;
6409
6410         mutex_lock(&dev_priv->dpio_lock);
6411
6412         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6413                SBI_GEN0 : SBI_DBUFF0;
6414         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6415         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6416         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6417
6418         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6419         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6420                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6421                         tmp |= SBI_SSCCTL_PATHALT;
6422                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6423                         udelay(32);
6424                 }
6425                 tmp |= SBI_SSCCTL_DISABLE;
6426                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6427         }
6428
6429         mutex_unlock(&dev_priv->dpio_lock);
6430 }
6431
6432 static void lpt_init_pch_refclk(struct drm_device *dev)
6433 {
6434         struct drm_mode_config *mode_config = &dev->mode_config;
6435         struct intel_encoder *encoder;
6436         bool has_vga = false;
6437
6438         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6439                 switch (encoder->type) {
6440                 case INTEL_OUTPUT_ANALOG:
6441                         has_vga = true;
6442                         break;
6443                 }
6444         }
6445
6446         if (has_vga)
6447                 lpt_enable_clkout_dp(dev, true, true);
6448         else
6449                 lpt_disable_clkout_dp(dev);
6450 }
6451
6452 /*
6453  * Initialize reference clocks when the driver loads
6454  */
6455 void intel_init_pch_refclk(struct drm_device *dev)
6456 {
6457         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6458                 ironlake_init_pch_refclk(dev);
6459         else if (HAS_PCH_LPT(dev))
6460                 lpt_init_pch_refclk(dev);
6461 }
6462
6463 static int ironlake_get_refclk(struct drm_crtc *crtc)
6464 {
6465         struct drm_device *dev = crtc->dev;
6466         struct drm_i915_private *dev_priv = dev->dev_private;
6467         struct intel_encoder *encoder;
6468         int num_connectors = 0;
6469         bool is_lvds = false;
6470
6471         for_each_encoder_on_crtc(dev, crtc, encoder) {
6472                 switch (encoder->type) {
6473                 case INTEL_OUTPUT_LVDS:
6474                         is_lvds = true;
6475                         break;
6476                 }
6477                 num_connectors++;
6478         }
6479
6480         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6481                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6482                               dev_priv->vbt.lvds_ssc_freq);
6483                 return dev_priv->vbt.lvds_ssc_freq;
6484         }
6485
6486         return 120000;
6487 }
6488
6489 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6490 {
6491         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493         int pipe = intel_crtc->pipe;
6494         uint32_t val;
6495
6496         val = 0;
6497
6498         switch (intel_crtc->config.pipe_bpp) {
6499         case 18:
6500                 val |= PIPECONF_6BPC;
6501                 break;
6502         case 24:
6503                 val |= PIPECONF_8BPC;
6504                 break;
6505         case 30:
6506                 val |= PIPECONF_10BPC;
6507                 break;
6508         case 36:
6509                 val |= PIPECONF_12BPC;
6510                 break;
6511         default:
6512                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6513                 BUG();
6514         }
6515
6516         if (intel_crtc->config.dither)
6517                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6518
6519         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6520                 val |= PIPECONF_INTERLACED_ILK;
6521         else
6522                 val |= PIPECONF_PROGRESSIVE;
6523
6524         if (intel_crtc->config.limited_color_range)
6525                 val |= PIPECONF_COLOR_RANGE_SELECT;
6526
6527         I915_WRITE(PIPECONF(pipe), val);
6528         POSTING_READ(PIPECONF(pipe));
6529 }
6530
6531 /*
6532  * Set up the pipe CSC unit.
6533  *
6534  * Currently only full range RGB to limited range RGB conversion
6535  * is supported, but eventually this should handle various
6536  * RGB<->YCbCr scenarios as well.
6537  */
6538 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6539 {
6540         struct drm_device *dev = crtc->dev;
6541         struct drm_i915_private *dev_priv = dev->dev_private;
6542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6543         int pipe = intel_crtc->pipe;
6544         uint16_t coeff = 0x7800; /* 1.0 */
6545
6546         /*
6547          * TODO: Check what kind of values actually come out of the pipe
6548          * with these coeff/postoff values and adjust to get the best
6549          * accuracy. Perhaps we even need to take the bpc value into
6550          * consideration.
6551          */
6552
6553         if (intel_crtc->config.limited_color_range)
6554                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6555
6556         /*
6557          * GY/GU and RY/RU should be the other way around according
6558          * to BSpec, but reality doesn't agree. Just set them up in
6559          * a way that results in the correct picture.
6560          */
6561         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6562         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6563
6564         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6565         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6566
6567         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6568         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6569
6570         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6571         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6572         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6573
6574         if (INTEL_INFO(dev)->gen > 6) {
6575                 uint16_t postoff = 0;
6576
6577                 if (intel_crtc->config.limited_color_range)
6578                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6579
6580                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6581                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6582                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6583
6584                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6585         } else {
6586                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6587
6588                 if (intel_crtc->config.limited_color_range)
6589                         mode |= CSC_BLACK_SCREEN_OFFSET;
6590
6591                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6592         }
6593 }
6594
6595 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6596 {
6597         struct drm_device *dev = crtc->dev;
6598         struct drm_i915_private *dev_priv = dev->dev_private;
6599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600         enum pipe pipe = intel_crtc->pipe;
6601         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6602         uint32_t val;
6603
6604         val = 0;
6605
6606         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6607                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6608
6609         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6610                 val |= PIPECONF_INTERLACED_ILK;
6611         else
6612                 val |= PIPECONF_PROGRESSIVE;
6613
6614         I915_WRITE(PIPECONF(cpu_transcoder), val);
6615         POSTING_READ(PIPECONF(cpu_transcoder));
6616
6617         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6618         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6619
6620         if (IS_BROADWELL(dev)) {
6621                 val = 0;
6622
6623                 switch (intel_crtc->config.pipe_bpp) {
6624                 case 18:
6625                         val |= PIPEMISC_DITHER_6_BPC;
6626                         break;
6627                 case 24:
6628                         val |= PIPEMISC_DITHER_8_BPC;
6629                         break;
6630                 case 30:
6631                         val |= PIPEMISC_DITHER_10_BPC;
6632                         break;
6633                 case 36:
6634                         val |= PIPEMISC_DITHER_12_BPC;
6635                         break;
6636                 default:
6637                         /* Case prevented by pipe_config_set_bpp. */
6638                         BUG();
6639                 }
6640
6641                 if (intel_crtc->config.dither)
6642                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6643
6644                 I915_WRITE(PIPEMISC(pipe), val);
6645         }
6646 }
6647
6648 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6649                                     intel_clock_t *clock,
6650                                     bool *has_reduced_clock,
6651                                     intel_clock_t *reduced_clock)
6652 {
6653         struct drm_device *dev = crtc->dev;
6654         struct drm_i915_private *dev_priv = dev->dev_private;
6655         struct intel_encoder *intel_encoder;
6656         int refclk;
6657         const intel_limit_t *limit;
6658         bool ret, is_lvds = false;
6659
6660         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6661                 switch (intel_encoder->type) {
6662                 case INTEL_OUTPUT_LVDS:
6663                         is_lvds = true;
6664                         break;
6665                 }
6666         }
6667
6668         refclk = ironlake_get_refclk(crtc);
6669
6670         /*
6671          * Returns a set of divisors for the desired target clock with the given
6672          * refclk, or FALSE.  The returned values represent the clock equation:
6673          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6674          */
6675         limit = intel_limit(crtc, refclk);
6676         ret = dev_priv->display.find_dpll(limit, crtc,
6677                                           to_intel_crtc(crtc)->config.port_clock,
6678                                           refclk, NULL, clock);
6679         if (!ret)
6680                 return false;
6681
6682         if (is_lvds && dev_priv->lvds_downclock_avail) {
6683                 /*
6684                  * Ensure we match the reduced clock's P to the target clock.
6685                  * If the clocks don't match, we can't switch the display clock
6686                  * by using the FP0/FP1. In such case we will disable the LVDS
6687                  * downclock feature.
6688                 */
6689                 *has_reduced_clock =
6690                         dev_priv->display.find_dpll(limit, crtc,
6691                                                     dev_priv->lvds_downclock,
6692                                                     refclk, clock,
6693                                                     reduced_clock);
6694         }
6695
6696         return true;
6697 }
6698
6699 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6700 {
6701         /*
6702          * Account for spread spectrum to avoid
6703          * oversubscribing the link. Max center spread
6704          * is 2.5%; use 5% for safety's sake.
6705          */
6706         u32 bps = target_clock * bpp * 21 / 20;
6707         return DIV_ROUND_UP(bps, link_bw * 8);
6708 }
6709
6710 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6711 {
6712         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6713 }
6714
6715 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6716                                       u32 *fp,
6717                                       intel_clock_t *reduced_clock, u32 *fp2)
6718 {
6719         struct drm_crtc *crtc = &intel_crtc->base;
6720         struct drm_device *dev = crtc->dev;
6721         struct drm_i915_private *dev_priv = dev->dev_private;
6722         struct intel_encoder *intel_encoder;
6723         uint32_t dpll;
6724         int factor, num_connectors = 0;
6725         bool is_lvds = false, is_sdvo = false;
6726
6727         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6728                 switch (intel_encoder->type) {
6729                 case INTEL_OUTPUT_LVDS:
6730                         is_lvds = true;
6731                         break;
6732                 case INTEL_OUTPUT_SDVO:
6733                 case INTEL_OUTPUT_HDMI:
6734                         is_sdvo = true;
6735                         break;
6736                 }
6737
6738                 num_connectors++;
6739         }
6740
6741         /* Enable autotuning of the PLL clock (if permissible) */
6742         factor = 21;
6743         if (is_lvds) {
6744                 if ((intel_panel_use_ssc(dev_priv) &&
6745                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6746                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6747                         factor = 25;
6748         } else if (intel_crtc->config.sdvo_tv_clock)
6749                 factor = 20;
6750
6751         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6752                 *fp |= FP_CB_TUNE;
6753
6754         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6755                 *fp2 |= FP_CB_TUNE;
6756
6757         dpll = 0;
6758
6759         if (is_lvds)
6760                 dpll |= DPLLB_MODE_LVDS;
6761         else
6762                 dpll |= DPLLB_MODE_DAC_SERIAL;
6763
6764         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6765                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6766
6767         if (is_sdvo)
6768                 dpll |= DPLL_SDVO_HIGH_SPEED;
6769         if (intel_crtc->config.has_dp_encoder)
6770                 dpll |= DPLL_SDVO_HIGH_SPEED;
6771
6772         /* compute bitmask from p1 value */
6773         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6774         /* also FPA1 */
6775         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6776
6777         switch (intel_crtc->config.dpll.p2) {
6778         case 5:
6779                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6780                 break;
6781         case 7:
6782                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6783                 break;
6784         case 10:
6785                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6786                 break;
6787         case 14:
6788                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6789                 break;
6790         }
6791
6792         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6793                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6794         else
6795                 dpll |= PLL_REF_INPUT_DREFCLK;
6796
6797         return dpll | DPLL_VCO_ENABLE;
6798 }
6799
6800 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6801                                   int x, int y,
6802                                   struct drm_framebuffer *fb)
6803 {
6804         struct drm_device *dev = crtc->dev;
6805         struct drm_i915_private *dev_priv = dev->dev_private;
6806         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807         int pipe = intel_crtc->pipe;
6808         int plane = intel_crtc->plane;
6809         int num_connectors = 0;
6810         intel_clock_t clock, reduced_clock;
6811         u32 dpll = 0, fp = 0, fp2 = 0;
6812         bool ok, has_reduced_clock = false;
6813         bool is_lvds = false;
6814         struct intel_encoder *encoder;
6815         struct intel_shared_dpll *pll;
6816         int ret;
6817
6818         for_each_encoder_on_crtc(dev, crtc, encoder) {
6819                 switch (encoder->type) {
6820                 case INTEL_OUTPUT_LVDS:
6821                         is_lvds = true;
6822                         break;
6823                 }
6824
6825                 num_connectors++;
6826         }
6827
6828         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6829              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6830
6831         ok = ironlake_compute_clocks(crtc, &clock,
6832                                      &has_reduced_clock, &reduced_clock);
6833         if (!ok && !intel_crtc->config.clock_set) {
6834                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6835                 return -EINVAL;
6836         }
6837         /* Compat-code for transition, will disappear. */
6838         if (!intel_crtc->config.clock_set) {
6839                 intel_crtc->config.dpll.n = clock.n;
6840                 intel_crtc->config.dpll.m1 = clock.m1;
6841                 intel_crtc->config.dpll.m2 = clock.m2;
6842                 intel_crtc->config.dpll.p1 = clock.p1;
6843                 intel_crtc->config.dpll.p2 = clock.p2;
6844         }
6845
6846         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6847         if (intel_crtc->config.has_pch_encoder) {
6848                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6849                 if (has_reduced_clock)
6850                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6851
6852                 dpll = ironlake_compute_dpll(intel_crtc,
6853                                              &fp, &reduced_clock,
6854                                              has_reduced_clock ? &fp2 : NULL);
6855
6856                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6857                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6858                 if (has_reduced_clock)
6859                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6860                 else
6861                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6862
6863                 pll = intel_get_shared_dpll(intel_crtc);
6864                 if (pll == NULL) {
6865                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6866                                          pipe_name(pipe));
6867                         return -EINVAL;
6868                 }
6869         } else
6870                 intel_put_shared_dpll(intel_crtc);
6871
6872         if (intel_crtc->config.has_dp_encoder)
6873                 intel_dp_set_m_n(intel_crtc);
6874
6875         if (is_lvds && has_reduced_clock && i915.powersave)
6876                 intel_crtc->lowfreq_avail = true;
6877         else
6878                 intel_crtc->lowfreq_avail = false;
6879
6880         intel_set_pipe_timings(intel_crtc);
6881
6882         if (intel_crtc->config.has_pch_encoder) {
6883                 intel_cpu_transcoder_set_m_n(intel_crtc,
6884                                              &intel_crtc->config.fdi_m_n);
6885         }
6886
6887         ironlake_set_pipeconf(crtc);
6888
6889         /* Set up the display plane register */
6890         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6891         POSTING_READ(DSPCNTR(plane));
6892
6893         ret = intel_pipe_set_base(crtc, x, y, fb);
6894
6895         return ret;
6896 }
6897
6898 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6899                                          struct intel_link_m_n *m_n)
6900 {
6901         struct drm_device *dev = crtc->base.dev;
6902         struct drm_i915_private *dev_priv = dev->dev_private;
6903         enum pipe pipe = crtc->pipe;
6904
6905         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6906         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6907         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6908                 & ~TU_SIZE_MASK;
6909         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6910         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6911                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6912 }
6913
6914 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6915                                          enum transcoder transcoder,
6916                                          struct intel_link_m_n *m_n)
6917 {
6918         struct drm_device *dev = crtc->base.dev;
6919         struct drm_i915_private *dev_priv = dev->dev_private;
6920         enum pipe pipe = crtc->pipe;
6921
6922         if (INTEL_INFO(dev)->gen >= 5) {
6923                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6924                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6925                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6926                         & ~TU_SIZE_MASK;
6927                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6928                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6929                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6930         } else {
6931                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6932                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6933                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6934                         & ~TU_SIZE_MASK;
6935                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6936                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6937                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6938         }
6939 }
6940
6941 void intel_dp_get_m_n(struct intel_crtc *crtc,
6942                       struct intel_crtc_config *pipe_config)
6943 {
6944         if (crtc->config.has_pch_encoder)
6945                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6946         else
6947                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6948                                              &pipe_config->dp_m_n);
6949 }
6950
6951 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6952                                         struct intel_crtc_config *pipe_config)
6953 {
6954         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6955                                      &pipe_config->fdi_m_n);
6956 }
6957
6958 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6959                                      struct intel_crtc_config *pipe_config)
6960 {
6961         struct drm_device *dev = crtc->base.dev;
6962         struct drm_i915_private *dev_priv = dev->dev_private;
6963         uint32_t tmp;
6964
6965         tmp = I915_READ(PF_CTL(crtc->pipe));
6966
6967         if (tmp & PF_ENABLE) {
6968                 pipe_config->pch_pfit.enabled = true;
6969                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6970                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6971
6972                 /* We currently do not free assignements of panel fitters on
6973                  * ivb/hsw (since we don't use the higher upscaling modes which
6974                  * differentiates them) so just WARN about this case for now. */
6975                 if (IS_GEN7(dev)) {
6976                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6977                                 PF_PIPE_SEL_IVB(crtc->pipe));
6978                 }
6979         }
6980 }
6981
6982 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6983                                       struct intel_plane_config *plane_config)
6984 {
6985         struct drm_device *dev = crtc->base.dev;
6986         struct drm_i915_private *dev_priv = dev->dev_private;
6987         u32 val, base, offset;
6988         int pipe = crtc->pipe, plane = crtc->plane;
6989         int fourcc, pixel_format;
6990         int aligned_height;
6991
6992         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6993         if (!crtc->base.primary->fb) {
6994                 DRM_DEBUG_KMS("failed to alloc fb\n");
6995                 return;
6996         }
6997
6998         val = I915_READ(DSPCNTR(plane));
6999
7000         if (INTEL_INFO(dev)->gen >= 4)
7001                 if (val & DISPPLANE_TILED)
7002                         plane_config->tiled = true;
7003
7004         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7005         fourcc = intel_format_to_fourcc(pixel_format);
7006         crtc->base.primary->fb->pixel_format = fourcc;
7007         crtc->base.primary->fb->bits_per_pixel =
7008                 drm_format_plane_cpp(fourcc, 0) * 8;
7009
7010         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7011         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7012                 offset = I915_READ(DSPOFFSET(plane));
7013         } else {
7014                 if (plane_config->tiled)
7015                         offset = I915_READ(DSPTILEOFF(plane));
7016                 else
7017                         offset = I915_READ(DSPLINOFF(plane));
7018         }
7019         plane_config->base = base;
7020
7021         val = I915_READ(PIPESRC(pipe));
7022         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7023         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7024
7025         val = I915_READ(DSPSTRIDE(pipe));
7026         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7027
7028         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7029                                             plane_config->tiled);
7030
7031         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7032                                    aligned_height, PAGE_SIZE);
7033
7034         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7035                       pipe, plane, crtc->base.primary->fb->width,
7036                       crtc->base.primary->fb->height,
7037                       crtc->base.primary->fb->bits_per_pixel, base,
7038                       crtc->base.primary->fb->pitches[0],
7039                       plane_config->size);
7040 }
7041
7042 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7043                                      struct intel_crtc_config *pipe_config)
7044 {
7045         struct drm_device *dev = crtc->base.dev;
7046         struct drm_i915_private *dev_priv = dev->dev_private;
7047         uint32_t tmp;
7048
7049         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7050         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7051
7052         tmp = I915_READ(PIPECONF(crtc->pipe));
7053         if (!(tmp & PIPECONF_ENABLE))
7054                 return false;
7055
7056         switch (tmp & PIPECONF_BPC_MASK) {
7057         case PIPECONF_6BPC:
7058                 pipe_config->pipe_bpp = 18;
7059                 break;
7060         case PIPECONF_8BPC:
7061                 pipe_config->pipe_bpp = 24;
7062                 break;
7063         case PIPECONF_10BPC:
7064                 pipe_config->pipe_bpp = 30;
7065                 break;
7066         case PIPECONF_12BPC:
7067                 pipe_config->pipe_bpp = 36;
7068                 break;
7069         default:
7070                 break;
7071         }
7072
7073         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7074                 struct intel_shared_dpll *pll;
7075
7076                 pipe_config->has_pch_encoder = true;
7077
7078                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7079                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7080                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7081
7082                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7083
7084                 if (HAS_PCH_IBX(dev_priv->dev)) {
7085                         pipe_config->shared_dpll =
7086                                 (enum intel_dpll_id) crtc->pipe;
7087                 } else {
7088                         tmp = I915_READ(PCH_DPLL_SEL);
7089                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7090                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7091                         else
7092                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7093                 }
7094
7095                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7096
7097                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7098                                            &pipe_config->dpll_hw_state));
7099
7100                 tmp = pipe_config->dpll_hw_state.dpll;
7101                 pipe_config->pixel_multiplier =
7102                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7103                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7104
7105                 ironlake_pch_clock_get(crtc, pipe_config);
7106         } else {
7107                 pipe_config->pixel_multiplier = 1;
7108         }
7109
7110         intel_get_pipe_timings(crtc, pipe_config);
7111
7112         ironlake_get_pfit_config(crtc, pipe_config);
7113
7114         return true;
7115 }
7116
7117 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7118 {
7119         struct drm_device *dev = dev_priv->dev;
7120         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7121         struct intel_crtc *crtc;
7122
7123         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
7124                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7125                      pipe_name(crtc->pipe));
7126
7127         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7128         WARN(plls->spll_refcount, "SPLL enabled\n");
7129         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7130         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7131         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7132         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7133              "CPU PWM1 enabled\n");
7134         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7135              "CPU PWM2 enabled\n");
7136         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7137              "PCH PWM1 enabled\n");
7138         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7139              "Utility pin enabled\n");
7140         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7141
7142         /*
7143          * In theory we can still leave IRQs enabled, as long as only the HPD
7144          * interrupts remain enabled. We used to check for that, but since it's
7145          * gen-specific and since we only disable LCPLL after we fully disable
7146          * the interrupts, the check below should be enough.
7147          */
7148         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7149 }
7150
7151 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7152 {
7153         struct drm_device *dev = dev_priv->dev;
7154
7155         if (IS_HASWELL(dev)) {
7156                 mutex_lock(&dev_priv->rps.hw_lock);
7157                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7158                                             val))
7159                         DRM_ERROR("Failed to disable D_COMP\n");
7160                 mutex_unlock(&dev_priv->rps.hw_lock);
7161         } else {
7162                 I915_WRITE(D_COMP, val);
7163         }
7164         POSTING_READ(D_COMP);
7165 }
7166
7167 /*
7168  * This function implements pieces of two sequences from BSpec:
7169  * - Sequence for display software to disable LCPLL
7170  * - Sequence for display software to allow package C8+
7171  * The steps implemented here are just the steps that actually touch the LCPLL
7172  * register. Callers should take care of disabling all the display engine
7173  * functions, doing the mode unset, fixing interrupts, etc.
7174  */
7175 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7176                               bool switch_to_fclk, bool allow_power_down)
7177 {
7178         uint32_t val;
7179
7180         assert_can_disable_lcpll(dev_priv);
7181
7182         val = I915_READ(LCPLL_CTL);
7183
7184         if (switch_to_fclk) {
7185                 val |= LCPLL_CD_SOURCE_FCLK;
7186                 I915_WRITE(LCPLL_CTL, val);
7187
7188                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7189                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7190                         DRM_ERROR("Switching to FCLK failed\n");
7191
7192                 val = I915_READ(LCPLL_CTL);
7193         }
7194
7195         val |= LCPLL_PLL_DISABLE;
7196         I915_WRITE(LCPLL_CTL, val);
7197         POSTING_READ(LCPLL_CTL);
7198
7199         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7200                 DRM_ERROR("LCPLL still locked\n");
7201
7202         val = I915_READ(D_COMP);
7203         val |= D_COMP_COMP_DISABLE;
7204         hsw_write_dcomp(dev_priv, val);
7205         ndelay(100);
7206
7207         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7208                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7209
7210         if (allow_power_down) {
7211                 val = I915_READ(LCPLL_CTL);
7212                 val |= LCPLL_POWER_DOWN_ALLOW;
7213                 I915_WRITE(LCPLL_CTL, val);
7214                 POSTING_READ(LCPLL_CTL);
7215         }
7216 }
7217
7218 /*
7219  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7220  * source.
7221  */
7222 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7223 {
7224         uint32_t val;
7225         unsigned long irqflags;
7226
7227         val = I915_READ(LCPLL_CTL);
7228
7229         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7230                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7231                 return;
7232
7233         /*
7234          * Make sure we're not on PC8 state before disabling PC8, otherwise
7235          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7236          *
7237          * The other problem is that hsw_restore_lcpll() is called as part of
7238          * the runtime PM resume sequence, so we can't just call
7239          * gen6_gt_force_wake_get() because that function calls
7240          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7241          * while we are on the resume sequence. So to solve this problem we have
7242          * to call special forcewake code that doesn't touch runtime PM and
7243          * doesn't enable the forcewake delayed work.
7244          */
7245         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7246         if (dev_priv->uncore.forcewake_count++ == 0)
7247                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7248         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7249
7250         if (val & LCPLL_POWER_DOWN_ALLOW) {
7251                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7252                 I915_WRITE(LCPLL_CTL, val);
7253                 POSTING_READ(LCPLL_CTL);
7254         }
7255
7256         val = I915_READ(D_COMP);
7257         val |= D_COMP_COMP_FORCE;
7258         val &= ~D_COMP_COMP_DISABLE;
7259         hsw_write_dcomp(dev_priv, val);
7260
7261         val = I915_READ(LCPLL_CTL);
7262         val &= ~LCPLL_PLL_DISABLE;
7263         I915_WRITE(LCPLL_CTL, val);
7264
7265         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7266                 DRM_ERROR("LCPLL not locked yet\n");
7267
7268         if (val & LCPLL_CD_SOURCE_FCLK) {
7269                 val = I915_READ(LCPLL_CTL);
7270                 val &= ~LCPLL_CD_SOURCE_FCLK;
7271                 I915_WRITE(LCPLL_CTL, val);
7272
7273                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7274                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7275                         DRM_ERROR("Switching back to LCPLL failed\n");
7276         }
7277
7278         /* See the big comment above. */
7279         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7280         if (--dev_priv->uncore.forcewake_count == 0)
7281                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7282         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7283 }
7284
7285 /*
7286  * Package states C8 and deeper are really deep PC states that can only be
7287  * reached when all the devices on the system allow it, so even if the graphics
7288  * device allows PC8+, it doesn't mean the system will actually get to these
7289  * states. Our driver only allows PC8+ when going into runtime PM.
7290  *
7291  * The requirements for PC8+ are that all the outputs are disabled, the power
7292  * well is disabled and most interrupts are disabled, and these are also
7293  * requirements for runtime PM. When these conditions are met, we manually do
7294  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7295  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7296  * hang the machine.
7297  *
7298  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7299  * the state of some registers, so when we come back from PC8+ we need to
7300  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7301  * need to take care of the registers kept by RC6. Notice that this happens even
7302  * if we don't put the device in PCI D3 state (which is what currently happens
7303  * because of the runtime PM support).
7304  *
7305  * For more, read "Display Sequences for Package C8" on the hardware
7306  * documentation.
7307  */
7308 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7309 {
7310         struct drm_device *dev = dev_priv->dev;
7311         uint32_t val;
7312
7313         DRM_DEBUG_KMS("Enabling package C8+\n");
7314
7315         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7316                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7317                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7318                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7319         }
7320
7321         lpt_disable_clkout_dp(dev);
7322         hsw_disable_lcpll(dev_priv, true, true);
7323 }
7324
7325 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7326 {
7327         struct drm_device *dev = dev_priv->dev;
7328         uint32_t val;
7329
7330         DRM_DEBUG_KMS("Disabling package C8+\n");
7331
7332         hsw_restore_lcpll(dev_priv);
7333         lpt_init_pch_refclk(dev);
7334
7335         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7336                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7337                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7338                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7339         }
7340
7341         intel_prepare_ddi(dev);
7342 }
7343
7344 static void snb_modeset_global_resources(struct drm_device *dev)
7345 {
7346         modeset_update_crtc_power_domains(dev);
7347 }
7348
7349 static void haswell_modeset_global_resources(struct drm_device *dev)
7350 {
7351         modeset_update_crtc_power_domains(dev);
7352 }
7353
7354 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7355                                  int x, int y,
7356                                  struct drm_framebuffer *fb)
7357 {
7358         struct drm_device *dev = crtc->dev;
7359         struct drm_i915_private *dev_priv = dev->dev_private;
7360         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7361         int plane = intel_crtc->plane;
7362         int ret;
7363
7364         if (!intel_ddi_pll_select(intel_crtc))
7365                 return -EINVAL;
7366         intel_ddi_pll_enable(intel_crtc);
7367
7368         if (intel_crtc->config.has_dp_encoder)
7369                 intel_dp_set_m_n(intel_crtc);
7370
7371         intel_crtc->lowfreq_avail = false;
7372
7373         intel_set_pipe_timings(intel_crtc);
7374
7375         if (intel_crtc->config.has_pch_encoder) {
7376                 intel_cpu_transcoder_set_m_n(intel_crtc,
7377                                              &intel_crtc->config.fdi_m_n);
7378         }
7379
7380         haswell_set_pipeconf(crtc);
7381
7382         intel_set_pipe_csc(crtc);
7383
7384         /* Set up the display plane register */
7385         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7386         POSTING_READ(DSPCNTR(plane));
7387
7388         ret = intel_pipe_set_base(crtc, x, y, fb);
7389
7390         return ret;
7391 }
7392
7393 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7394                                     struct intel_crtc_config *pipe_config)
7395 {
7396         struct drm_device *dev = crtc->base.dev;
7397         struct drm_i915_private *dev_priv = dev->dev_private;
7398         enum intel_display_power_domain pfit_domain;
7399         uint32_t tmp;
7400
7401         if (!intel_display_power_enabled(dev_priv,
7402                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7403                 return false;
7404
7405         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7406         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7407
7408         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7409         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7410                 enum pipe trans_edp_pipe;
7411                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7412                 default:
7413                         WARN(1, "unknown pipe linked to edp transcoder\n");
7414                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7415                 case TRANS_DDI_EDP_INPUT_A_ON:
7416                         trans_edp_pipe = PIPE_A;
7417                         break;
7418                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7419                         trans_edp_pipe = PIPE_B;
7420                         break;
7421                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7422                         trans_edp_pipe = PIPE_C;
7423                         break;
7424                 }
7425
7426                 if (trans_edp_pipe == crtc->pipe)
7427                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7428         }
7429
7430         if (!intel_display_power_enabled(dev_priv,
7431                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7432                 return false;
7433
7434         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7435         if (!(tmp & PIPECONF_ENABLE))
7436                 return false;
7437
7438         /*
7439          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7440          * DDI E. So just check whether this pipe is wired to DDI E and whether
7441          * the PCH transcoder is on.
7442          */
7443         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7444         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7445             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7446                 pipe_config->has_pch_encoder = true;
7447
7448                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7449                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7450                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7451
7452                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7453         }
7454
7455         intel_get_pipe_timings(crtc, pipe_config);
7456
7457         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7458         if (intel_display_power_enabled(dev_priv, pfit_domain))
7459                 ironlake_get_pfit_config(crtc, pipe_config);
7460
7461         if (IS_HASWELL(dev))
7462                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7463                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7464
7465         pipe_config->pixel_multiplier = 1;
7466
7467         return true;
7468 }
7469
7470 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7471                                int x, int y,
7472                                struct drm_framebuffer *fb)
7473 {
7474         struct drm_device *dev = crtc->dev;
7475         struct drm_i915_private *dev_priv = dev->dev_private;
7476         struct intel_encoder *encoder;
7477         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7478         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7479         int pipe = intel_crtc->pipe;
7480         int ret;
7481
7482         drm_vblank_pre_modeset(dev, pipe);
7483
7484         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7485
7486         drm_vblank_post_modeset(dev, pipe);
7487
7488         if (ret != 0)
7489                 return ret;
7490
7491         for_each_encoder_on_crtc(dev, crtc, encoder) {
7492                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7493                         encoder->base.base.id,
7494                         drm_get_encoder_name(&encoder->base),
7495                         mode->base.id, mode->name);
7496
7497                 if (encoder->mode_set)
7498                         encoder->mode_set(encoder);
7499         }
7500
7501         return 0;
7502 }
7503
7504 static struct {
7505         int clock;
7506         u32 config;
7507 } hdmi_audio_clock[] = {
7508         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7509         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7510         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7511         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7512         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7513         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7514         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7515         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7516         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7517         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7518 };
7519
7520 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7521 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7522 {
7523         int i;
7524
7525         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7526                 if (mode->clock == hdmi_audio_clock[i].clock)
7527                         break;
7528         }
7529
7530         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7531                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7532                 i = 1;
7533         }
7534
7535         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7536                       hdmi_audio_clock[i].clock,
7537                       hdmi_audio_clock[i].config);
7538
7539         return hdmi_audio_clock[i].config;
7540 }
7541
7542 static bool intel_eld_uptodate(struct drm_connector *connector,
7543                                int reg_eldv, uint32_t bits_eldv,
7544                                int reg_elda, uint32_t bits_elda,
7545                                int reg_edid)
7546 {
7547         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7548         uint8_t *eld = connector->eld;
7549         uint32_t i;
7550
7551         i = I915_READ(reg_eldv);
7552         i &= bits_eldv;
7553
7554         if (!eld[0])
7555                 return !i;
7556
7557         if (!i)
7558                 return false;
7559
7560         i = I915_READ(reg_elda);
7561         i &= ~bits_elda;
7562         I915_WRITE(reg_elda, i);
7563
7564         for (i = 0; i < eld[2]; i++)
7565                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7566                         return false;
7567
7568         return true;
7569 }
7570
7571 static void g4x_write_eld(struct drm_connector *connector,
7572                           struct drm_crtc *crtc,
7573                           struct drm_display_mode *mode)
7574 {
7575         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7576         uint8_t *eld = connector->eld;
7577         uint32_t eldv;
7578         uint32_t len;
7579         uint32_t i;
7580
7581         i = I915_READ(G4X_AUD_VID_DID);
7582
7583         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7584                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7585         else
7586                 eldv = G4X_ELDV_DEVCTG;
7587
7588         if (intel_eld_uptodate(connector,
7589                                G4X_AUD_CNTL_ST, eldv,
7590                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7591                                G4X_HDMIW_HDMIEDID))
7592                 return;
7593
7594         i = I915_READ(G4X_AUD_CNTL_ST);
7595         i &= ~(eldv | G4X_ELD_ADDR);
7596         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7597         I915_WRITE(G4X_AUD_CNTL_ST, i);
7598
7599         if (!eld[0])
7600                 return;
7601
7602         len = min_t(uint8_t, eld[2], len);
7603         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7604         for (i = 0; i < len; i++)
7605                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7606
7607         i = I915_READ(G4X_AUD_CNTL_ST);
7608         i |= eldv;
7609         I915_WRITE(G4X_AUD_CNTL_ST, i);
7610 }
7611
7612 static void haswell_write_eld(struct drm_connector *connector,
7613                               struct drm_crtc *crtc,
7614                               struct drm_display_mode *mode)
7615 {
7616         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7617         uint8_t *eld = connector->eld;
7618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7619         uint32_t eldv;
7620         uint32_t i;
7621         int len;
7622         int pipe = to_intel_crtc(crtc)->pipe;
7623         int tmp;
7624
7625         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7626         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7627         int aud_config = HSW_AUD_CFG(pipe);
7628         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7629
7630         /* Audio output enable */
7631         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7632         tmp = I915_READ(aud_cntrl_st2);
7633         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7634         I915_WRITE(aud_cntrl_st2, tmp);
7635         POSTING_READ(aud_cntrl_st2);
7636
7637         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7638
7639         /* Set ELD valid state */
7640         tmp = I915_READ(aud_cntrl_st2);
7641         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7642         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7643         I915_WRITE(aud_cntrl_st2, tmp);
7644         tmp = I915_READ(aud_cntrl_st2);
7645         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7646
7647         /* Enable HDMI mode */
7648         tmp = I915_READ(aud_config);
7649         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7650         /* clear N_programing_enable and N_value_index */
7651         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7652         I915_WRITE(aud_config, tmp);
7653
7654         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7655
7656         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7657         intel_crtc->eld_vld = true;
7658
7659         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7660                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7661                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7662                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7663         } else {
7664                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7665         }
7666
7667         if (intel_eld_uptodate(connector,
7668                                aud_cntrl_st2, eldv,
7669                                aud_cntl_st, IBX_ELD_ADDRESS,
7670                                hdmiw_hdmiedid))
7671                 return;
7672
7673         i = I915_READ(aud_cntrl_st2);
7674         i &= ~eldv;
7675         I915_WRITE(aud_cntrl_st2, i);
7676
7677         if (!eld[0])
7678                 return;
7679
7680         i = I915_READ(aud_cntl_st);
7681         i &= ~IBX_ELD_ADDRESS;
7682         I915_WRITE(aud_cntl_st, i);
7683         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7684         DRM_DEBUG_DRIVER("port num:%d\n", i);
7685
7686         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7687         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7688         for (i = 0; i < len; i++)
7689                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7690
7691         i = I915_READ(aud_cntrl_st2);
7692         i |= eldv;
7693         I915_WRITE(aud_cntrl_st2, i);
7694
7695 }
7696
7697 static void ironlake_write_eld(struct drm_connector *connector,
7698                                struct drm_crtc *crtc,
7699                                struct drm_display_mode *mode)
7700 {
7701         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7702         uint8_t *eld = connector->eld;
7703         uint32_t eldv;
7704         uint32_t i;
7705         int len;
7706         int hdmiw_hdmiedid;
7707         int aud_config;
7708         int aud_cntl_st;
7709         int aud_cntrl_st2;
7710         int pipe = to_intel_crtc(crtc)->pipe;
7711
7712         if (HAS_PCH_IBX(connector->dev)) {
7713                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7714                 aud_config = IBX_AUD_CFG(pipe);
7715                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7716                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7717         } else if (IS_VALLEYVIEW(connector->dev)) {
7718                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7719                 aud_config = VLV_AUD_CFG(pipe);
7720                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7721                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7722         } else {
7723                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7724                 aud_config = CPT_AUD_CFG(pipe);
7725                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7726                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7727         }
7728
7729         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7730
7731         if (IS_VALLEYVIEW(connector->dev))  {
7732                 struct intel_encoder *intel_encoder;
7733                 struct intel_digital_port *intel_dig_port;
7734
7735                 intel_encoder = intel_attached_encoder(connector);
7736                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7737                 i = intel_dig_port->port;
7738         } else {
7739                 i = I915_READ(aud_cntl_st);
7740                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7741                 /* DIP_Port_Select, 0x1 = PortB */
7742         }
7743
7744         if (!i) {
7745                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7746                 /* operate blindly on all ports */
7747                 eldv = IBX_ELD_VALIDB;
7748                 eldv |= IBX_ELD_VALIDB << 4;
7749                 eldv |= IBX_ELD_VALIDB << 8;
7750         } else {
7751                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7752                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7753         }
7754
7755         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7756                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7757                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7758                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7759         } else {
7760                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7761         }
7762
7763         if (intel_eld_uptodate(connector,
7764                                aud_cntrl_st2, eldv,
7765                                aud_cntl_st, IBX_ELD_ADDRESS,
7766                                hdmiw_hdmiedid))
7767                 return;
7768
7769         i = I915_READ(aud_cntrl_st2);
7770         i &= ~eldv;
7771         I915_WRITE(aud_cntrl_st2, i);
7772
7773         if (!eld[0])
7774                 return;
7775
7776         i = I915_READ(aud_cntl_st);
7777         i &= ~IBX_ELD_ADDRESS;
7778         I915_WRITE(aud_cntl_st, i);
7779
7780         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7781         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7782         for (i = 0; i < len; i++)
7783                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7784
7785         i = I915_READ(aud_cntrl_st2);
7786         i |= eldv;
7787         I915_WRITE(aud_cntrl_st2, i);
7788 }
7789
7790 void intel_write_eld(struct drm_encoder *encoder,
7791                      struct drm_display_mode *mode)
7792 {
7793         struct drm_crtc *crtc = encoder->crtc;
7794         struct drm_connector *connector;
7795         struct drm_device *dev = encoder->dev;
7796         struct drm_i915_private *dev_priv = dev->dev_private;
7797
7798         connector = drm_select_eld(encoder, mode);
7799         if (!connector)
7800                 return;
7801
7802         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7803                          connector->base.id,
7804                          drm_get_connector_name(connector),
7805                          connector->encoder->base.id,
7806                          drm_get_encoder_name(connector->encoder));
7807
7808         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7809
7810         if (dev_priv->display.write_eld)
7811                 dev_priv->display.write_eld(connector, crtc, mode);
7812 }
7813
7814 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7815 {
7816         struct drm_device *dev = crtc->dev;
7817         struct drm_i915_private *dev_priv = dev->dev_private;
7818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7819         bool visible = base != 0;
7820         u32 cntl;
7821
7822         if (intel_crtc->cursor_visible == visible)
7823                 return;
7824
7825         cntl = I915_READ(_CURACNTR);
7826         if (visible) {
7827                 /* On these chipsets we can only modify the base whilst
7828                  * the cursor is disabled.
7829                  */
7830                 I915_WRITE(_CURABASE, base);
7831
7832                 cntl &= ~(CURSOR_FORMAT_MASK);
7833                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7834                 cntl |= CURSOR_ENABLE |
7835                         CURSOR_GAMMA_ENABLE |
7836                         CURSOR_FORMAT_ARGB;
7837         } else
7838                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7839         I915_WRITE(_CURACNTR, cntl);
7840
7841         intel_crtc->cursor_visible = visible;
7842 }
7843
7844 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7845 {
7846         struct drm_device *dev = crtc->dev;
7847         struct drm_i915_private *dev_priv = dev->dev_private;
7848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7849         int pipe = intel_crtc->pipe;
7850         bool visible = base != 0;
7851
7852         if (intel_crtc->cursor_visible != visible) {
7853                 int16_t width = intel_crtc->cursor_width;
7854                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7855                 if (base) {
7856                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7857                         cntl |= MCURSOR_GAMMA_ENABLE;
7858
7859                         switch (width) {
7860                         case 64:
7861                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7862                                 break;
7863                         case 128:
7864                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7865                                 break;
7866                         case 256:
7867                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7868                                 break;
7869                         default:
7870                                 WARN_ON(1);
7871                                 return;
7872                         }
7873                         cntl |= pipe << 28; /* Connect to correct pipe */
7874                 } else {
7875                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7876                         cntl |= CURSOR_MODE_DISABLE;
7877                 }
7878                 I915_WRITE(CURCNTR(pipe), cntl);
7879
7880                 intel_crtc->cursor_visible = visible;
7881         }
7882         /* and commit changes on next vblank */
7883         POSTING_READ(CURCNTR(pipe));
7884         I915_WRITE(CURBASE(pipe), base);
7885         POSTING_READ(CURBASE(pipe));
7886 }
7887
7888 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7889 {
7890         struct drm_device *dev = crtc->dev;
7891         struct drm_i915_private *dev_priv = dev->dev_private;
7892         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7893         int pipe = intel_crtc->pipe;
7894         bool visible = base != 0;
7895
7896         if (intel_crtc->cursor_visible != visible) {
7897                 int16_t width = intel_crtc->cursor_width;
7898                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7899                 if (base) {
7900                         cntl &= ~CURSOR_MODE;
7901                         cntl |= MCURSOR_GAMMA_ENABLE;
7902                         switch (width) {
7903                         case 64:
7904                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7905                                 break;
7906                         case 128:
7907                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7908                                 break;
7909                         case 256:
7910                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7911                                 break;
7912                         default:
7913                                 WARN_ON(1);
7914                                 return;
7915                         }
7916                 } else {
7917                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7918                         cntl |= CURSOR_MODE_DISABLE;
7919                 }
7920                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7921                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7922                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7923                 }
7924                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7925
7926                 intel_crtc->cursor_visible = visible;
7927         }
7928         /* and commit changes on next vblank */
7929         POSTING_READ(CURCNTR_IVB(pipe));
7930         I915_WRITE(CURBASE_IVB(pipe), base);
7931         POSTING_READ(CURBASE_IVB(pipe));
7932 }
7933
7934 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7935 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7936                                      bool on)
7937 {
7938         struct drm_device *dev = crtc->dev;
7939         struct drm_i915_private *dev_priv = dev->dev_private;
7940         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7941         int pipe = intel_crtc->pipe;
7942         int x = intel_crtc->cursor_x;
7943         int y = intel_crtc->cursor_y;
7944         u32 base = 0, pos = 0;
7945         bool visible;
7946
7947         if (on)
7948                 base = intel_crtc->cursor_addr;
7949
7950         if (x >= intel_crtc->config.pipe_src_w)
7951                 base = 0;
7952
7953         if (y >= intel_crtc->config.pipe_src_h)
7954                 base = 0;
7955
7956         if (x < 0) {
7957                 if (x + intel_crtc->cursor_width <= 0)
7958                         base = 0;
7959
7960                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7961                 x = -x;
7962         }
7963         pos |= x << CURSOR_X_SHIFT;
7964
7965         if (y < 0) {
7966                 if (y + intel_crtc->cursor_height <= 0)
7967                         base = 0;
7968
7969                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7970                 y = -y;
7971         }
7972         pos |= y << CURSOR_Y_SHIFT;
7973
7974         visible = base != 0;
7975         if (!visible && !intel_crtc->cursor_visible)
7976                 return;
7977
7978         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7979                 I915_WRITE(CURPOS_IVB(pipe), pos);
7980                 ivb_update_cursor(crtc, base);
7981         } else {
7982                 I915_WRITE(CURPOS(pipe), pos);
7983                 if (IS_845G(dev) || IS_I865G(dev))
7984                         i845_update_cursor(crtc, base);
7985                 else
7986                         i9xx_update_cursor(crtc, base);
7987         }
7988 }
7989
7990 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7991                                  struct drm_file *file,
7992                                  uint32_t handle,
7993                                  uint32_t width, uint32_t height)
7994 {
7995         struct drm_device *dev = crtc->dev;
7996         struct drm_i915_private *dev_priv = dev->dev_private;
7997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7998         struct drm_i915_gem_object *obj;
7999         unsigned old_width;
8000         uint32_t addr;
8001         int ret;
8002
8003         /* if we want to turn off the cursor ignore width and height */
8004         if (!handle) {
8005                 DRM_DEBUG_KMS("cursor off\n");
8006                 addr = 0;
8007                 obj = NULL;
8008                 mutex_lock(&dev->struct_mutex);
8009                 goto finish;
8010         }
8011
8012         /* Check for which cursor types we support */
8013         if (!((width == 64 && height == 64) ||
8014                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8015                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8016                 DRM_DEBUG("Cursor dimension not supported\n");
8017                 return -EINVAL;
8018         }
8019
8020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8021         if (&obj->base == NULL)
8022                 return -ENOENT;
8023
8024         if (obj->base.size < width * height * 4) {
8025                 DRM_DEBUG_KMS("buffer is to small\n");
8026                 ret = -ENOMEM;
8027                 goto fail;
8028         }
8029
8030         /* we only need to pin inside GTT if cursor is non-phy */
8031         mutex_lock(&dev->struct_mutex);
8032         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8033                 unsigned alignment;
8034
8035                 if (obj->tiling_mode) {
8036                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8037                         ret = -EINVAL;
8038                         goto fail_locked;
8039                 }
8040
8041                 /* Note that the w/a also requires 2 PTE of padding following
8042                  * the bo. We currently fill all unused PTE with the shadow
8043                  * page and so we should always have valid PTE following the
8044                  * cursor preventing the VT-d warning.
8045                  */
8046                 alignment = 0;
8047                 if (need_vtd_wa(dev))
8048                         alignment = 64*1024;
8049
8050                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8051                 if (ret) {
8052                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8053                         goto fail_locked;
8054                 }
8055
8056                 ret = i915_gem_object_put_fence(obj);
8057                 if (ret) {
8058                         DRM_DEBUG_KMS("failed to release fence for cursor");
8059                         goto fail_unpin;
8060                 }
8061
8062                 addr = i915_gem_obj_ggtt_offset(obj);
8063         } else {
8064                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8065                 ret = i915_gem_attach_phys_object(dev, obj,
8066                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8067                                                   align);
8068                 if (ret) {
8069                         DRM_DEBUG_KMS("failed to attach phys object\n");
8070                         goto fail_locked;
8071                 }
8072                 addr = obj->phys_obj->handle->busaddr;
8073         }
8074
8075         if (IS_GEN2(dev))
8076                 I915_WRITE(CURSIZE, (height << 12) | width);
8077
8078  finish:
8079         if (intel_crtc->cursor_bo) {
8080                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8081                         if (intel_crtc->cursor_bo != obj)
8082                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8083                 } else
8084                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8085                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8086         }
8087
8088         mutex_unlock(&dev->struct_mutex);
8089
8090         old_width = intel_crtc->cursor_width;
8091
8092         intel_crtc->cursor_addr = addr;
8093         intel_crtc->cursor_bo = obj;
8094         intel_crtc->cursor_width = width;
8095         intel_crtc->cursor_height = height;
8096
8097         if (intel_crtc->active) {
8098                 if (old_width != width)
8099                         intel_update_watermarks(crtc);
8100                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8101         }
8102
8103         return 0;
8104 fail_unpin:
8105         i915_gem_object_unpin_from_display_plane(obj);
8106 fail_locked:
8107         mutex_unlock(&dev->struct_mutex);
8108 fail:
8109         drm_gem_object_unreference_unlocked(&obj->base);
8110         return ret;
8111 }
8112
8113 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8114 {
8115         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8116
8117         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8118         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8119
8120         if (intel_crtc->active)
8121                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8122
8123         return 0;
8124 }
8125
8126 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8127                                  u16 *blue, uint32_t start, uint32_t size)
8128 {
8129         int end = (start + size > 256) ? 256 : start + size, i;
8130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8131
8132         for (i = start; i < end; i++) {
8133                 intel_crtc->lut_r[i] = red[i] >> 8;
8134                 intel_crtc->lut_g[i] = green[i] >> 8;
8135                 intel_crtc->lut_b[i] = blue[i] >> 8;
8136         }
8137
8138         intel_crtc_load_lut(crtc);
8139 }
8140
8141 /* VESA 640x480x72Hz mode to set on the pipe */
8142 static struct drm_display_mode load_detect_mode = {
8143         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8144                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8145 };
8146
8147 struct drm_framebuffer *
8148 __intel_framebuffer_create(struct drm_device *dev,
8149                            struct drm_mode_fb_cmd2 *mode_cmd,
8150                            struct drm_i915_gem_object *obj)
8151 {
8152         struct intel_framebuffer *intel_fb;
8153         int ret;
8154
8155         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8156         if (!intel_fb) {
8157                 drm_gem_object_unreference_unlocked(&obj->base);
8158                 return ERR_PTR(-ENOMEM);
8159         }
8160
8161         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8162         if (ret)
8163                 goto err;
8164
8165         return &intel_fb->base;
8166 err:
8167         drm_gem_object_unreference_unlocked(&obj->base);
8168         kfree(intel_fb);
8169
8170         return ERR_PTR(ret);
8171 }
8172
8173 static struct drm_framebuffer *
8174 intel_framebuffer_create(struct drm_device *dev,
8175                          struct drm_mode_fb_cmd2 *mode_cmd,
8176                          struct drm_i915_gem_object *obj)
8177 {
8178         struct drm_framebuffer *fb;
8179         int ret;
8180
8181         ret = i915_mutex_lock_interruptible(dev);
8182         if (ret)
8183                 return ERR_PTR(ret);
8184         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8185         mutex_unlock(&dev->struct_mutex);
8186
8187         return fb;
8188 }
8189
8190 static u32
8191 intel_framebuffer_pitch_for_width(int width, int bpp)
8192 {
8193         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8194         return ALIGN(pitch, 64);
8195 }
8196
8197 static u32
8198 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8199 {
8200         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8201         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8202 }
8203
8204 static struct drm_framebuffer *
8205 intel_framebuffer_create_for_mode(struct drm_device *dev,
8206                                   struct drm_display_mode *mode,
8207                                   int depth, int bpp)
8208 {
8209         struct drm_i915_gem_object *obj;
8210         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8211
8212         obj = i915_gem_alloc_object(dev,
8213                                     intel_framebuffer_size_for_mode(mode, bpp));
8214         if (obj == NULL)
8215                 return ERR_PTR(-ENOMEM);
8216
8217         mode_cmd.width = mode->hdisplay;
8218         mode_cmd.height = mode->vdisplay;
8219         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8220                                                                 bpp);
8221         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8222
8223         return intel_framebuffer_create(dev, &mode_cmd, obj);
8224 }
8225
8226 static struct drm_framebuffer *
8227 mode_fits_in_fbdev(struct drm_device *dev,
8228                    struct drm_display_mode *mode)
8229 {
8230 #ifdef CONFIG_DRM_I915_FBDEV
8231         struct drm_i915_private *dev_priv = dev->dev_private;
8232         struct drm_i915_gem_object *obj;
8233         struct drm_framebuffer *fb;
8234
8235         if (!dev_priv->fbdev)
8236                 return NULL;
8237
8238         if (!dev_priv->fbdev->fb)
8239                 return NULL;
8240
8241         obj = dev_priv->fbdev->fb->obj;
8242         BUG_ON(!obj);
8243
8244         fb = &dev_priv->fbdev->fb->base;
8245         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8246                                                                fb->bits_per_pixel))
8247                 return NULL;
8248
8249         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8250                 return NULL;
8251
8252         return fb;
8253 #else
8254         return NULL;
8255 #endif
8256 }
8257
8258 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8259                                 struct drm_display_mode *mode,
8260                                 struct intel_load_detect_pipe *old)
8261 {
8262         struct intel_crtc *intel_crtc;
8263         struct intel_encoder *intel_encoder =
8264                 intel_attached_encoder(connector);
8265         struct drm_crtc *possible_crtc;
8266         struct drm_encoder *encoder = &intel_encoder->base;
8267         struct drm_crtc *crtc = NULL;
8268         struct drm_device *dev = encoder->dev;
8269         struct drm_framebuffer *fb;
8270         int i = -1;
8271
8272         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8273                       connector->base.id, drm_get_connector_name(connector),
8274                       encoder->base.id, drm_get_encoder_name(encoder));
8275
8276         /*
8277          * Algorithm gets a little messy:
8278          *
8279          *   - if the connector already has an assigned crtc, use it (but make
8280          *     sure it's on first)
8281          *
8282          *   - try to find the first unused crtc that can drive this connector,
8283          *     and use that if we find one
8284          */
8285
8286         /* See if we already have a CRTC for this connector */
8287         if (encoder->crtc) {
8288                 crtc = encoder->crtc;
8289
8290                 mutex_lock(&crtc->mutex);
8291
8292                 old->dpms_mode = connector->dpms;
8293                 old->load_detect_temp = false;
8294
8295                 /* Make sure the crtc and connector are running */
8296                 if (connector->dpms != DRM_MODE_DPMS_ON)
8297                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8298
8299                 return true;
8300         }
8301
8302         /* Find an unused one (if possible) */
8303         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8304                 i++;
8305                 if (!(encoder->possible_crtcs & (1 << i)))
8306                         continue;
8307                 if (!possible_crtc->enabled) {
8308                         crtc = possible_crtc;
8309                         break;
8310                 }
8311         }
8312
8313         /*
8314          * If we didn't find an unused CRTC, don't use any.
8315          */
8316         if (!crtc) {
8317                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8318                 return false;
8319         }
8320
8321         mutex_lock(&crtc->mutex);
8322         intel_encoder->new_crtc = to_intel_crtc(crtc);
8323         to_intel_connector(connector)->new_encoder = intel_encoder;
8324
8325         intel_crtc = to_intel_crtc(crtc);
8326         intel_crtc->new_enabled = true;
8327         intel_crtc->new_config = &intel_crtc->config;
8328         old->dpms_mode = connector->dpms;
8329         old->load_detect_temp = true;
8330         old->release_fb = NULL;
8331
8332         if (!mode)
8333                 mode = &load_detect_mode;
8334
8335         /* We need a framebuffer large enough to accommodate all accesses
8336          * that the plane may generate whilst we perform load detection.
8337          * We can not rely on the fbcon either being present (we get called
8338          * during its initialisation to detect all boot displays, or it may
8339          * not even exist) or that it is large enough to satisfy the
8340          * requested mode.
8341          */
8342         fb = mode_fits_in_fbdev(dev, mode);
8343         if (fb == NULL) {
8344                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8345                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8346                 old->release_fb = fb;
8347         } else
8348                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8349         if (IS_ERR(fb)) {
8350                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8351                 goto fail;
8352         }
8353
8354         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8355                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8356                 if (old->release_fb)
8357                         old->release_fb->funcs->destroy(old->release_fb);
8358                 goto fail;
8359         }
8360
8361         /* let the connector get through one full cycle before testing */
8362         intel_wait_for_vblank(dev, intel_crtc->pipe);
8363         return true;
8364
8365  fail:
8366         intel_crtc->new_enabled = crtc->enabled;
8367         if (intel_crtc->new_enabled)
8368                 intel_crtc->new_config = &intel_crtc->config;
8369         else
8370                 intel_crtc->new_config = NULL;
8371         mutex_unlock(&crtc->mutex);
8372         return false;
8373 }
8374
8375 void intel_release_load_detect_pipe(struct drm_connector *connector,
8376                                     struct intel_load_detect_pipe *old)
8377 {
8378         struct intel_encoder *intel_encoder =
8379                 intel_attached_encoder(connector);
8380         struct drm_encoder *encoder = &intel_encoder->base;
8381         struct drm_crtc *crtc = encoder->crtc;
8382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8383
8384         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8385                       connector->base.id, drm_get_connector_name(connector),
8386                       encoder->base.id, drm_get_encoder_name(encoder));
8387
8388         if (old->load_detect_temp) {
8389                 to_intel_connector(connector)->new_encoder = NULL;
8390                 intel_encoder->new_crtc = NULL;
8391                 intel_crtc->new_enabled = false;
8392                 intel_crtc->new_config = NULL;
8393                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8394
8395                 if (old->release_fb) {
8396                         drm_framebuffer_unregister_private(old->release_fb);
8397                         drm_framebuffer_unreference(old->release_fb);
8398                 }
8399
8400                 mutex_unlock(&crtc->mutex);
8401                 return;
8402         }
8403
8404         /* Switch crtc and encoder back off if necessary */
8405         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8406                 connector->funcs->dpms(connector, old->dpms_mode);
8407
8408         mutex_unlock(&crtc->mutex);
8409 }
8410
8411 static int i9xx_pll_refclk(struct drm_device *dev,
8412                            const struct intel_crtc_config *pipe_config)
8413 {
8414         struct drm_i915_private *dev_priv = dev->dev_private;
8415         u32 dpll = pipe_config->dpll_hw_state.dpll;
8416
8417         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8418                 return dev_priv->vbt.lvds_ssc_freq;
8419         else if (HAS_PCH_SPLIT(dev))
8420                 return 120000;
8421         else if (!IS_GEN2(dev))
8422                 return 96000;
8423         else
8424                 return 48000;
8425 }
8426
8427 /* Returns the clock of the currently programmed mode of the given pipe. */
8428 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8429                                 struct intel_crtc_config *pipe_config)
8430 {
8431         struct drm_device *dev = crtc->base.dev;
8432         struct drm_i915_private *dev_priv = dev->dev_private;
8433         int pipe = pipe_config->cpu_transcoder;
8434         u32 dpll = pipe_config->dpll_hw_state.dpll;
8435         u32 fp;
8436         intel_clock_t clock;
8437         int refclk = i9xx_pll_refclk(dev, pipe_config);
8438
8439         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8440                 fp = pipe_config->dpll_hw_state.fp0;
8441         else
8442                 fp = pipe_config->dpll_hw_state.fp1;
8443
8444         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8445         if (IS_PINEVIEW(dev)) {
8446                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8447                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8448         } else {
8449                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8450                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8451         }
8452
8453         if (!IS_GEN2(dev)) {
8454                 if (IS_PINEVIEW(dev))
8455                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8456                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8457                 else
8458                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8459                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8460
8461                 switch (dpll & DPLL_MODE_MASK) {
8462                 case DPLLB_MODE_DAC_SERIAL:
8463                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8464                                 5 : 10;
8465                         break;
8466                 case DPLLB_MODE_LVDS:
8467                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8468                                 7 : 14;
8469                         break;
8470                 default:
8471                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8472                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8473                         return;
8474                 }
8475
8476                 if (IS_PINEVIEW(dev))
8477                         pineview_clock(refclk, &clock);
8478                 else
8479                         i9xx_clock(refclk, &clock);
8480         } else {
8481                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8482                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8483
8484                 if (is_lvds) {
8485                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8486                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8487
8488                         if (lvds & LVDS_CLKB_POWER_UP)
8489                                 clock.p2 = 7;
8490                         else
8491                                 clock.p2 = 14;
8492                 } else {
8493                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8494                                 clock.p1 = 2;
8495                         else {
8496                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8497                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8498                         }
8499                         if (dpll & PLL_P2_DIVIDE_BY_4)
8500                                 clock.p2 = 4;
8501                         else
8502                                 clock.p2 = 2;
8503                 }
8504
8505                 i9xx_clock(refclk, &clock);
8506         }
8507
8508         /*
8509          * This value includes pixel_multiplier. We will use
8510          * port_clock to compute adjusted_mode.crtc_clock in the
8511          * encoder's get_config() function.
8512          */
8513         pipe_config->port_clock = clock.dot;
8514 }
8515
8516 int intel_dotclock_calculate(int link_freq,
8517                              const struct intel_link_m_n *m_n)
8518 {
8519         /*
8520          * The calculation for the data clock is:
8521          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8522          * But we want to avoid losing precison if possible, so:
8523          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8524          *
8525          * and the link clock is simpler:
8526          * link_clock = (m * link_clock) / n
8527          */
8528
8529         if (!m_n->link_n)
8530                 return 0;
8531
8532         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8533 }
8534
8535 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8536                                    struct intel_crtc_config *pipe_config)
8537 {
8538         struct drm_device *dev = crtc->base.dev;
8539
8540         /* read out port_clock from the DPLL */
8541         i9xx_crtc_clock_get(crtc, pipe_config);
8542
8543         /*
8544          * This value does not include pixel_multiplier.
8545          * We will check that port_clock and adjusted_mode.crtc_clock
8546          * agree once we know their relationship in the encoder's
8547          * get_config() function.
8548          */
8549         pipe_config->adjusted_mode.crtc_clock =
8550                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8551                                          &pipe_config->fdi_m_n);
8552 }
8553
8554 /** Returns the currently programmed mode of the given pipe. */
8555 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8556                                              struct drm_crtc *crtc)
8557 {
8558         struct drm_i915_private *dev_priv = dev->dev_private;
8559         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8560         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8561         struct drm_display_mode *mode;
8562         struct intel_crtc_config pipe_config;
8563         int htot = I915_READ(HTOTAL(cpu_transcoder));
8564         int hsync = I915_READ(HSYNC(cpu_transcoder));
8565         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8566         int vsync = I915_READ(VSYNC(cpu_transcoder));
8567         enum pipe pipe = intel_crtc->pipe;
8568
8569         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8570         if (!mode)
8571                 return NULL;
8572
8573         /*
8574          * Construct a pipe_config sufficient for getting the clock info
8575          * back out of crtc_clock_get.
8576          *
8577          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8578          * to use a real value here instead.
8579          */
8580         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8581         pipe_config.pixel_multiplier = 1;
8582         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8583         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8584         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8585         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8586
8587         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8588         mode->hdisplay = (htot & 0xffff) + 1;
8589         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8590         mode->hsync_start = (hsync & 0xffff) + 1;
8591         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8592         mode->vdisplay = (vtot & 0xffff) + 1;
8593         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8594         mode->vsync_start = (vsync & 0xffff) + 1;
8595         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8596
8597         drm_mode_set_name(mode);
8598
8599         return mode;
8600 }
8601
8602 static void intel_increase_pllclock(struct drm_crtc *crtc)
8603 {
8604         struct drm_device *dev = crtc->dev;
8605         struct drm_i915_private *dev_priv = dev->dev_private;
8606         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8607         int pipe = intel_crtc->pipe;
8608         int dpll_reg = DPLL(pipe);
8609         int dpll;
8610
8611         if (HAS_PCH_SPLIT(dev))
8612                 return;
8613
8614         if (!dev_priv->lvds_downclock_avail)
8615                 return;
8616
8617         dpll = I915_READ(dpll_reg);
8618         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8619                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8620
8621                 assert_panel_unlocked(dev_priv, pipe);
8622
8623                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8624                 I915_WRITE(dpll_reg, dpll);
8625                 intel_wait_for_vblank(dev, pipe);
8626
8627                 dpll = I915_READ(dpll_reg);
8628                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8629                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8630         }
8631 }
8632
8633 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8634 {
8635         struct drm_device *dev = crtc->dev;
8636         struct drm_i915_private *dev_priv = dev->dev_private;
8637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8638
8639         if (HAS_PCH_SPLIT(dev))
8640                 return;
8641
8642         if (!dev_priv->lvds_downclock_avail)
8643                 return;
8644
8645         /*
8646          * Since this is called by a timer, we should never get here in
8647          * the manual case.
8648          */
8649         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8650                 int pipe = intel_crtc->pipe;
8651                 int dpll_reg = DPLL(pipe);
8652                 int dpll;
8653
8654                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8655
8656                 assert_panel_unlocked(dev_priv, pipe);
8657
8658                 dpll = I915_READ(dpll_reg);
8659                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8660                 I915_WRITE(dpll_reg, dpll);
8661                 intel_wait_for_vblank(dev, pipe);
8662                 dpll = I915_READ(dpll_reg);
8663                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8664                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8665         }
8666
8667 }
8668
8669 void intel_mark_busy(struct drm_device *dev)
8670 {
8671         struct drm_i915_private *dev_priv = dev->dev_private;
8672
8673         if (dev_priv->mm.busy)
8674                 return;
8675
8676         intel_runtime_pm_get(dev_priv);
8677         i915_update_gfx_val(dev_priv);
8678         dev_priv->mm.busy = true;
8679 }
8680
8681 void intel_mark_idle(struct drm_device *dev)
8682 {
8683         struct drm_i915_private *dev_priv = dev->dev_private;
8684         struct drm_crtc *crtc;
8685
8686         if (!dev_priv->mm.busy)
8687                 return;
8688
8689         dev_priv->mm.busy = false;
8690
8691         if (!i915.powersave)
8692                 goto out;
8693
8694         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8695                 if (!crtc->primary->fb)
8696                         continue;
8697
8698                 intel_decrease_pllclock(crtc);
8699         }
8700
8701         if (INTEL_INFO(dev)->gen >= 6)
8702                 gen6_rps_idle(dev->dev_private);
8703
8704 out:
8705         intel_runtime_pm_put(dev_priv);
8706 }
8707
8708 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8709                         struct intel_ring_buffer *ring)
8710 {
8711         struct drm_device *dev = obj->base.dev;
8712         struct drm_crtc *crtc;
8713
8714         if (!i915.powersave)
8715                 return;
8716
8717         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8718                 if (!crtc->primary->fb)
8719                         continue;
8720
8721                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8722                         continue;
8723
8724                 intel_increase_pllclock(crtc);
8725                 if (ring && intel_fbc_enabled(dev))
8726                         ring->fbc_dirty = true;
8727         }
8728 }
8729
8730 static void intel_crtc_destroy(struct drm_crtc *crtc)
8731 {
8732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8733         struct drm_device *dev = crtc->dev;
8734         struct intel_unpin_work *work;
8735         unsigned long flags;
8736
8737         spin_lock_irqsave(&dev->event_lock, flags);
8738         work = intel_crtc->unpin_work;
8739         intel_crtc->unpin_work = NULL;
8740         spin_unlock_irqrestore(&dev->event_lock, flags);
8741
8742         if (work) {
8743                 cancel_work_sync(&work->work);
8744                 kfree(work);
8745         }
8746
8747         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8748
8749         drm_crtc_cleanup(crtc);
8750
8751         kfree(intel_crtc);
8752 }
8753
8754 static void intel_unpin_work_fn(struct work_struct *__work)
8755 {
8756         struct intel_unpin_work *work =
8757                 container_of(__work, struct intel_unpin_work, work);
8758         struct drm_device *dev = work->crtc->dev;
8759
8760         mutex_lock(&dev->struct_mutex);
8761         intel_unpin_fb_obj(work->old_fb_obj);
8762         drm_gem_object_unreference(&work->pending_flip_obj->base);
8763         drm_gem_object_unreference(&work->old_fb_obj->base);
8764
8765         intel_update_fbc(dev);
8766         mutex_unlock(&dev->struct_mutex);
8767
8768         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8769         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8770
8771         kfree(work);
8772 }
8773
8774 static void do_intel_finish_page_flip(struct drm_device *dev,
8775                                       struct drm_crtc *crtc)
8776 {
8777         struct drm_i915_private *dev_priv = dev->dev_private;
8778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8779         struct intel_unpin_work *work;
8780         unsigned long flags;
8781
8782         /* Ignore early vblank irqs */
8783         if (intel_crtc == NULL)
8784                 return;
8785
8786         spin_lock_irqsave(&dev->event_lock, flags);
8787         work = intel_crtc->unpin_work;
8788
8789         /* Ensure we don't miss a work->pending update ... */
8790         smp_rmb();
8791
8792         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8793                 spin_unlock_irqrestore(&dev->event_lock, flags);
8794                 return;
8795         }
8796
8797         /* and that the unpin work is consistent wrt ->pending. */
8798         smp_rmb();
8799
8800         intel_crtc->unpin_work = NULL;
8801
8802         if (work->event)
8803                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8804
8805         drm_vblank_put(dev, intel_crtc->pipe);
8806
8807         spin_unlock_irqrestore(&dev->event_lock, flags);
8808
8809         wake_up_all(&dev_priv->pending_flip_queue);
8810
8811         queue_work(dev_priv->wq, &work->work);
8812
8813         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8814 }
8815
8816 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8817 {
8818         struct drm_i915_private *dev_priv = dev->dev_private;
8819         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8820
8821         do_intel_finish_page_flip(dev, crtc);
8822 }
8823
8824 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8825 {
8826         struct drm_i915_private *dev_priv = dev->dev_private;
8827         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8828
8829         do_intel_finish_page_flip(dev, crtc);
8830 }
8831
8832 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8833 {
8834         struct drm_i915_private *dev_priv = dev->dev_private;
8835         struct intel_crtc *intel_crtc =
8836                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8837         unsigned long flags;
8838
8839         /* NB: An MMIO update of the plane base pointer will also
8840          * generate a page-flip completion irq, i.e. every modeset
8841          * is also accompanied by a spurious intel_prepare_page_flip().
8842          */
8843         spin_lock_irqsave(&dev->event_lock, flags);
8844         if (intel_crtc->unpin_work)
8845                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8846         spin_unlock_irqrestore(&dev->event_lock, flags);
8847 }
8848
8849 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8850 {
8851         /* Ensure that the work item is consistent when activating it ... */
8852         smp_wmb();
8853         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8854         /* and that it is marked active as soon as the irq could fire. */
8855         smp_wmb();
8856 }
8857
8858 static int intel_gen2_queue_flip(struct drm_device *dev,
8859                                  struct drm_crtc *crtc,
8860                                  struct drm_framebuffer *fb,
8861                                  struct drm_i915_gem_object *obj,
8862                                  uint32_t flags)
8863 {
8864         struct drm_i915_private *dev_priv = dev->dev_private;
8865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8866         u32 flip_mask;
8867         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8868         int ret;
8869
8870         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8871         if (ret)
8872                 goto err;
8873
8874         ret = intel_ring_begin(ring, 6);
8875         if (ret)
8876                 goto err_unpin;
8877
8878         /* Can't queue multiple flips, so wait for the previous
8879          * one to finish before executing the next.
8880          */
8881         if (intel_crtc->plane)
8882                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8883         else
8884                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8885         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8886         intel_ring_emit(ring, MI_NOOP);
8887         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8888                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8889         intel_ring_emit(ring, fb->pitches[0]);
8890         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8891         intel_ring_emit(ring, 0); /* aux display base address, unused */
8892
8893         intel_mark_page_flip_active(intel_crtc);
8894         __intel_ring_advance(ring);
8895         return 0;
8896
8897 err_unpin:
8898         intel_unpin_fb_obj(obj);
8899 err:
8900         return ret;
8901 }
8902
8903 static int intel_gen3_queue_flip(struct drm_device *dev,
8904                                  struct drm_crtc *crtc,
8905                                  struct drm_framebuffer *fb,
8906                                  struct drm_i915_gem_object *obj,
8907                                  uint32_t flags)
8908 {
8909         struct drm_i915_private *dev_priv = dev->dev_private;
8910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8911         u32 flip_mask;
8912         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8913         int ret;
8914
8915         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8916         if (ret)
8917                 goto err;
8918
8919         ret = intel_ring_begin(ring, 6);
8920         if (ret)
8921                 goto err_unpin;
8922
8923         if (intel_crtc->plane)
8924                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8925         else
8926                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8927         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8928         intel_ring_emit(ring, MI_NOOP);
8929         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8930                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8931         intel_ring_emit(ring, fb->pitches[0]);
8932         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8933         intel_ring_emit(ring, MI_NOOP);
8934
8935         intel_mark_page_flip_active(intel_crtc);
8936         __intel_ring_advance(ring);
8937         return 0;
8938
8939 err_unpin:
8940         intel_unpin_fb_obj(obj);
8941 err:
8942         return ret;
8943 }
8944
8945 static int intel_gen4_queue_flip(struct drm_device *dev,
8946                                  struct drm_crtc *crtc,
8947                                  struct drm_framebuffer *fb,
8948                                  struct drm_i915_gem_object *obj,
8949                                  uint32_t flags)
8950 {
8951         struct drm_i915_private *dev_priv = dev->dev_private;
8952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8953         uint32_t pf, pipesrc;
8954         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8955         int ret;
8956
8957         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8958         if (ret)
8959                 goto err;
8960
8961         ret = intel_ring_begin(ring, 4);
8962         if (ret)
8963                 goto err_unpin;
8964
8965         /* i965+ uses the linear or tiled offsets from the
8966          * Display Registers (which do not change across a page-flip)
8967          * so we need only reprogram the base address.
8968          */
8969         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8970                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8971         intel_ring_emit(ring, fb->pitches[0]);
8972         intel_ring_emit(ring,
8973                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8974                         obj->tiling_mode);
8975
8976         /* XXX Enabling the panel-fitter across page-flip is so far
8977          * untested on non-native modes, so ignore it for now.
8978          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8979          */
8980         pf = 0;
8981         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8982         intel_ring_emit(ring, pf | pipesrc);
8983
8984         intel_mark_page_flip_active(intel_crtc);
8985         __intel_ring_advance(ring);
8986         return 0;
8987
8988 err_unpin:
8989         intel_unpin_fb_obj(obj);
8990 err:
8991         return ret;
8992 }
8993
8994 static int intel_gen6_queue_flip(struct drm_device *dev,
8995                                  struct drm_crtc *crtc,
8996                                  struct drm_framebuffer *fb,
8997                                  struct drm_i915_gem_object *obj,
8998                                  uint32_t flags)
8999 {
9000         struct drm_i915_private *dev_priv = dev->dev_private;
9001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9002         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9003         uint32_t pf, pipesrc;
9004         int ret;
9005
9006         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9007         if (ret)
9008                 goto err;
9009
9010         ret = intel_ring_begin(ring, 4);
9011         if (ret)
9012                 goto err_unpin;
9013
9014         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9015                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9016         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9017         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9018
9019         /* Contrary to the suggestions in the documentation,
9020          * "Enable Panel Fitter" does not seem to be required when page
9021          * flipping with a non-native mode, and worse causes a normal
9022          * modeset to fail.
9023          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9024          */
9025         pf = 0;
9026         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9027         intel_ring_emit(ring, pf | pipesrc);
9028
9029         intel_mark_page_flip_active(intel_crtc);
9030         __intel_ring_advance(ring);
9031         return 0;
9032
9033 err_unpin:
9034         intel_unpin_fb_obj(obj);
9035 err:
9036         return ret;
9037 }
9038
9039 static int intel_gen7_queue_flip(struct drm_device *dev,
9040                                  struct drm_crtc *crtc,
9041                                  struct drm_framebuffer *fb,
9042                                  struct drm_i915_gem_object *obj,
9043                                  uint32_t flags)
9044 {
9045         struct drm_i915_private *dev_priv = dev->dev_private;
9046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9047         struct intel_ring_buffer *ring;
9048         uint32_t plane_bit = 0;
9049         int len, ret;
9050
9051         ring = obj->ring;
9052         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9053                 ring = &dev_priv->ring[BCS];
9054
9055         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9056         if (ret)
9057                 goto err;
9058
9059         switch(intel_crtc->plane) {
9060         case PLANE_A:
9061                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9062                 break;
9063         case PLANE_B:
9064                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9065                 break;
9066         case PLANE_C:
9067                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9068                 break;
9069         default:
9070                 WARN_ONCE(1, "unknown plane in flip command\n");
9071                 ret = -ENODEV;
9072                 goto err_unpin;
9073         }
9074
9075         len = 4;
9076         if (ring->id == RCS) {
9077                 len += 6;
9078                 /*
9079                  * On Gen 8, SRM is now taking an extra dword to accommodate
9080                  * 48bits addresses, and we need a NOOP for the batch size to
9081                  * stay even.
9082                  */
9083                 if (IS_GEN8(dev))
9084                         len += 2;
9085         }
9086
9087         /*
9088          * BSpec MI_DISPLAY_FLIP for IVB:
9089          * "The full packet must be contained within the same cache line."
9090          *
9091          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9092          * cacheline, if we ever start emitting more commands before
9093          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9094          * then do the cacheline alignment, and finally emit the
9095          * MI_DISPLAY_FLIP.
9096          */
9097         ret = intel_ring_cacheline_align(ring);
9098         if (ret)
9099                 goto err_unpin;
9100
9101         ret = intel_ring_begin(ring, len);
9102         if (ret)
9103                 goto err_unpin;
9104
9105         /* Unmask the flip-done completion message. Note that the bspec says that
9106          * we should do this for both the BCS and RCS, and that we must not unmask
9107          * more than one flip event at any time (or ensure that one flip message
9108          * can be sent by waiting for flip-done prior to queueing new flips).
9109          * Experimentation says that BCS works despite DERRMR masking all
9110          * flip-done completion events and that unmasking all planes at once
9111          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9112          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9113          */
9114         if (ring->id == RCS) {
9115                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9116                 intel_ring_emit(ring, DERRMR);
9117                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9118                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9119                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9120                 if (IS_GEN8(dev))
9121                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9122                                               MI_SRM_LRM_GLOBAL_GTT);
9123                 else
9124                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9125                                               MI_SRM_LRM_GLOBAL_GTT);
9126                 intel_ring_emit(ring, DERRMR);
9127                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9128                 if (IS_GEN8(dev)) {
9129                         intel_ring_emit(ring, 0);
9130                         intel_ring_emit(ring, MI_NOOP);
9131                 }
9132         }
9133
9134         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9135         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9136         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9137         intel_ring_emit(ring, (MI_NOOP));
9138
9139         intel_mark_page_flip_active(intel_crtc);
9140         __intel_ring_advance(ring);
9141         return 0;
9142
9143 err_unpin:
9144         intel_unpin_fb_obj(obj);
9145 err:
9146         return ret;
9147 }
9148
9149 static int intel_default_queue_flip(struct drm_device *dev,
9150                                     struct drm_crtc *crtc,
9151                                     struct drm_framebuffer *fb,
9152                                     struct drm_i915_gem_object *obj,
9153                                     uint32_t flags)
9154 {
9155         return -ENODEV;
9156 }
9157
9158 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9159                                 struct drm_framebuffer *fb,
9160                                 struct drm_pending_vblank_event *event,
9161                                 uint32_t page_flip_flags)
9162 {
9163         struct drm_device *dev = crtc->dev;
9164         struct drm_i915_private *dev_priv = dev->dev_private;
9165         struct drm_framebuffer *old_fb = crtc->primary->fb;
9166         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9168         struct intel_unpin_work *work;
9169         unsigned long flags;
9170         int ret;
9171
9172         /* Can't change pixel format via MI display flips. */
9173         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9174                 return -EINVAL;
9175
9176         /*
9177          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9178          * Note that pitch changes could also affect these register.
9179          */
9180         if (INTEL_INFO(dev)->gen > 3 &&
9181             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9182              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9183                 return -EINVAL;
9184
9185         if (i915_terminally_wedged(&dev_priv->gpu_error))
9186                 goto out_hang;
9187
9188         work = kzalloc(sizeof(*work), GFP_KERNEL);
9189         if (work == NULL)
9190                 return -ENOMEM;
9191
9192         work->event = event;
9193         work->crtc = crtc;
9194         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9195         INIT_WORK(&work->work, intel_unpin_work_fn);
9196
9197         ret = drm_vblank_get(dev, intel_crtc->pipe);
9198         if (ret)
9199                 goto free_work;
9200
9201         /* We borrow the event spin lock for protecting unpin_work */
9202         spin_lock_irqsave(&dev->event_lock, flags);
9203         if (intel_crtc->unpin_work) {
9204                 spin_unlock_irqrestore(&dev->event_lock, flags);
9205                 kfree(work);
9206                 drm_vblank_put(dev, intel_crtc->pipe);
9207
9208                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9209                 return -EBUSY;
9210         }
9211         intel_crtc->unpin_work = work;
9212         spin_unlock_irqrestore(&dev->event_lock, flags);
9213
9214         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9215                 flush_workqueue(dev_priv->wq);
9216
9217         ret = i915_mutex_lock_interruptible(dev);
9218         if (ret)
9219                 goto cleanup;
9220
9221         /* Reference the objects for the scheduled work. */
9222         drm_gem_object_reference(&work->old_fb_obj->base);
9223         drm_gem_object_reference(&obj->base);
9224
9225         crtc->primary->fb = fb;
9226
9227         work->pending_flip_obj = obj;
9228
9229         work->enable_stall_check = true;
9230
9231         atomic_inc(&intel_crtc->unpin_work_count);
9232         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9233
9234         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9235         if (ret)
9236                 goto cleanup_pending;
9237
9238         intel_disable_fbc(dev);
9239         intel_mark_fb_busy(obj, NULL);
9240         mutex_unlock(&dev->struct_mutex);
9241
9242         trace_i915_flip_request(intel_crtc->plane, obj);
9243
9244         return 0;
9245
9246 cleanup_pending:
9247         atomic_dec(&intel_crtc->unpin_work_count);
9248         crtc->primary->fb = old_fb;
9249         drm_gem_object_unreference(&work->old_fb_obj->base);
9250         drm_gem_object_unreference(&obj->base);
9251         mutex_unlock(&dev->struct_mutex);
9252
9253 cleanup:
9254         spin_lock_irqsave(&dev->event_lock, flags);
9255         intel_crtc->unpin_work = NULL;
9256         spin_unlock_irqrestore(&dev->event_lock, flags);
9257
9258         drm_vblank_put(dev, intel_crtc->pipe);
9259 free_work:
9260         kfree(work);
9261
9262         if (ret == -EIO) {
9263 out_hang:
9264                 intel_crtc_wait_for_pending_flips(crtc);
9265                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9266                 if (ret == 0 && event)
9267                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9268         }
9269         return ret;
9270 }
9271
9272 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9273         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9274         .load_lut = intel_crtc_load_lut,
9275 };
9276
9277 /**
9278  * intel_modeset_update_staged_output_state
9279  *
9280  * Updates the staged output configuration state, e.g. after we've read out the
9281  * current hw state.
9282  */
9283 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9284 {
9285         struct intel_crtc *crtc;
9286         struct intel_encoder *encoder;
9287         struct intel_connector *connector;
9288
9289         list_for_each_entry(connector, &dev->mode_config.connector_list,
9290                             base.head) {
9291                 connector->new_encoder =
9292                         to_intel_encoder(connector->base.encoder);
9293         }
9294
9295         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9296                             base.head) {
9297                 encoder->new_crtc =
9298                         to_intel_crtc(encoder->base.crtc);
9299         }
9300
9301         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9302                             base.head) {
9303                 crtc->new_enabled = crtc->base.enabled;
9304
9305                 if (crtc->new_enabled)
9306                         crtc->new_config = &crtc->config;
9307                 else
9308                         crtc->new_config = NULL;
9309         }
9310 }
9311
9312 /**
9313  * intel_modeset_commit_output_state
9314  *
9315  * This function copies the stage display pipe configuration to the real one.
9316  */
9317 static void intel_modeset_commit_output_state(struct drm_device *dev)
9318 {
9319         struct intel_crtc *crtc;
9320         struct intel_encoder *encoder;
9321         struct intel_connector *connector;
9322
9323         list_for_each_entry(connector, &dev->mode_config.connector_list,
9324                             base.head) {
9325                 connector->base.encoder = &connector->new_encoder->base;
9326         }
9327
9328         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9329                             base.head) {
9330                 encoder->base.crtc = &encoder->new_crtc->base;
9331         }
9332
9333         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9334                             base.head) {
9335                 crtc->base.enabled = crtc->new_enabled;
9336         }
9337 }
9338
9339 static void
9340 connected_sink_compute_bpp(struct intel_connector * connector,
9341                            struct intel_crtc_config *pipe_config)
9342 {
9343         int bpp = pipe_config->pipe_bpp;
9344
9345         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9346                 connector->base.base.id,
9347                 drm_get_connector_name(&connector->base));
9348
9349         /* Don't use an invalid EDID bpc value */
9350         if (connector->base.display_info.bpc &&
9351             connector->base.display_info.bpc * 3 < bpp) {
9352                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9353                               bpp, connector->base.display_info.bpc*3);
9354                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9355         }
9356
9357         /* Clamp bpp to 8 on screens without EDID 1.4 */
9358         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9359                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9360                               bpp);
9361                 pipe_config->pipe_bpp = 24;
9362         }
9363 }
9364
9365 static int
9366 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9367                           struct drm_framebuffer *fb,
9368                           struct intel_crtc_config *pipe_config)
9369 {
9370         struct drm_device *dev = crtc->base.dev;
9371         struct intel_connector *connector;
9372         int bpp;
9373
9374         switch (fb->pixel_format) {
9375         case DRM_FORMAT_C8:
9376                 bpp = 8*3; /* since we go through a colormap */
9377                 break;
9378         case DRM_FORMAT_XRGB1555:
9379         case DRM_FORMAT_ARGB1555:
9380                 /* checked in intel_framebuffer_init already */
9381                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9382                         return -EINVAL;
9383         case DRM_FORMAT_RGB565:
9384                 bpp = 6*3; /* min is 18bpp */
9385                 break;
9386         case DRM_FORMAT_XBGR8888:
9387         case DRM_FORMAT_ABGR8888:
9388                 /* checked in intel_framebuffer_init already */
9389                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9390                         return -EINVAL;
9391         case DRM_FORMAT_XRGB8888:
9392         case DRM_FORMAT_ARGB8888:
9393                 bpp = 8*3;
9394                 break;
9395         case DRM_FORMAT_XRGB2101010:
9396         case DRM_FORMAT_ARGB2101010:
9397         case DRM_FORMAT_XBGR2101010:
9398         case DRM_FORMAT_ABGR2101010:
9399                 /* checked in intel_framebuffer_init already */
9400                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9401                         return -EINVAL;
9402                 bpp = 10*3;
9403                 break;
9404         /* TODO: gen4+ supports 16 bpc floating point, too. */
9405         default:
9406                 DRM_DEBUG_KMS("unsupported depth\n");
9407                 return -EINVAL;
9408         }
9409
9410         pipe_config->pipe_bpp = bpp;
9411
9412         /* Clamp display bpp to EDID value */
9413         list_for_each_entry(connector, &dev->mode_config.connector_list,
9414                             base.head) {
9415                 if (!connector->new_encoder ||
9416                     connector->new_encoder->new_crtc != crtc)
9417                         continue;
9418
9419                 connected_sink_compute_bpp(connector, pipe_config);
9420         }
9421
9422         return bpp;
9423 }
9424
9425 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9426 {
9427         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9428                         "type: 0x%x flags: 0x%x\n",
9429                 mode->crtc_clock,
9430                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9431                 mode->crtc_hsync_end, mode->crtc_htotal,
9432                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9433                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9434 }
9435
9436 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9437                                    struct intel_crtc_config *pipe_config,
9438                                    const char *context)
9439 {
9440         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9441                       context, pipe_name(crtc->pipe));
9442
9443         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9444         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9445                       pipe_config->pipe_bpp, pipe_config->dither);
9446         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9447                       pipe_config->has_pch_encoder,
9448                       pipe_config->fdi_lanes,
9449                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9450                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9451                       pipe_config->fdi_m_n.tu);
9452         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9453                       pipe_config->has_dp_encoder,
9454                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9455                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9456                       pipe_config->dp_m_n.tu);
9457         DRM_DEBUG_KMS("requested mode:\n");
9458         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9459         DRM_DEBUG_KMS("adjusted mode:\n");
9460         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9461         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9462         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9463         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9464                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9465         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9466                       pipe_config->gmch_pfit.control,
9467                       pipe_config->gmch_pfit.pgm_ratios,
9468                       pipe_config->gmch_pfit.lvds_border_bits);
9469         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9470                       pipe_config->pch_pfit.pos,
9471                       pipe_config->pch_pfit.size,
9472                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9473         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9474         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9475 }
9476
9477 static bool encoders_cloneable(const struct intel_encoder *a,
9478                                const struct intel_encoder *b)
9479 {
9480         /* masks could be asymmetric, so check both ways */
9481         return a == b || (a->cloneable & (1 << b->type) &&
9482                           b->cloneable & (1 << a->type));
9483 }
9484
9485 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9486                                          struct intel_encoder *encoder)
9487 {
9488         struct drm_device *dev = crtc->base.dev;
9489         struct intel_encoder *source_encoder;
9490
9491         list_for_each_entry(source_encoder,
9492                             &dev->mode_config.encoder_list, base.head) {
9493                 if (source_encoder->new_crtc != crtc)
9494                         continue;
9495
9496                 if (!encoders_cloneable(encoder, source_encoder))
9497                         return false;
9498         }
9499
9500         return true;
9501 }
9502
9503 static bool check_encoder_cloning(struct intel_crtc *crtc)
9504 {
9505         struct drm_device *dev = crtc->base.dev;
9506         struct intel_encoder *encoder;
9507
9508         list_for_each_entry(encoder,
9509                             &dev->mode_config.encoder_list, base.head) {
9510                 if (encoder->new_crtc != crtc)
9511                         continue;
9512
9513                 if (!check_single_encoder_cloning(crtc, encoder))
9514                         return false;
9515         }
9516
9517         return true;
9518 }
9519
9520 static struct intel_crtc_config *
9521 intel_modeset_pipe_config(struct drm_crtc *crtc,
9522                           struct drm_framebuffer *fb,
9523                           struct drm_display_mode *mode)
9524 {
9525         struct drm_device *dev = crtc->dev;
9526         struct intel_encoder *encoder;
9527         struct intel_crtc_config *pipe_config;
9528         int plane_bpp, ret = -EINVAL;
9529         bool retry = true;
9530
9531         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9532                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9533                 return ERR_PTR(-EINVAL);
9534         }
9535
9536         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9537         if (!pipe_config)
9538                 return ERR_PTR(-ENOMEM);
9539
9540         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9541         drm_mode_copy(&pipe_config->requested_mode, mode);
9542
9543         pipe_config->cpu_transcoder =
9544                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9545         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9546
9547         /*
9548          * Sanitize sync polarity flags based on requested ones. If neither
9549          * positive or negative polarity is requested, treat this as meaning
9550          * negative polarity.
9551          */
9552         if (!(pipe_config->adjusted_mode.flags &
9553               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9554                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9555
9556         if (!(pipe_config->adjusted_mode.flags &
9557               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9558                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9559
9560         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9561          * plane pixel format and any sink constraints into account. Returns the
9562          * source plane bpp so that dithering can be selected on mismatches
9563          * after encoders and crtc also have had their say. */
9564         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9565                                               fb, pipe_config);
9566         if (plane_bpp < 0)
9567                 goto fail;
9568
9569         /*
9570          * Determine the real pipe dimensions. Note that stereo modes can
9571          * increase the actual pipe size due to the frame doubling and
9572          * insertion of additional space for blanks between the frame. This
9573          * is stored in the crtc timings. We use the requested mode to do this
9574          * computation to clearly distinguish it from the adjusted mode, which
9575          * can be changed by the connectors in the below retry loop.
9576          */
9577         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9578         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9579         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9580
9581 encoder_retry:
9582         /* Ensure the port clock defaults are reset when retrying. */
9583         pipe_config->port_clock = 0;
9584         pipe_config->pixel_multiplier = 1;
9585
9586         /* Fill in default crtc timings, allow encoders to overwrite them. */
9587         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9588
9589         /* Pass our mode to the connectors and the CRTC to give them a chance to
9590          * adjust it according to limitations or connector properties, and also
9591          * a chance to reject the mode entirely.
9592          */
9593         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9594                             base.head) {
9595
9596                 if (&encoder->new_crtc->base != crtc)
9597                         continue;
9598
9599                 if (!(encoder->compute_config(encoder, pipe_config))) {
9600                         DRM_DEBUG_KMS("Encoder config failure\n");
9601                         goto fail;
9602                 }
9603         }
9604
9605         /* Set default port clock if not overwritten by the encoder. Needs to be
9606          * done afterwards in case the encoder adjusts the mode. */
9607         if (!pipe_config->port_clock)
9608                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9609                         * pipe_config->pixel_multiplier;
9610
9611         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9612         if (ret < 0) {
9613                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9614                 goto fail;
9615         }
9616
9617         if (ret == RETRY) {
9618                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9619                         ret = -EINVAL;
9620                         goto fail;
9621                 }
9622
9623                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9624                 retry = false;
9625                 goto encoder_retry;
9626         }
9627
9628         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9629         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9630                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9631
9632         return pipe_config;
9633 fail:
9634         kfree(pipe_config);
9635         return ERR_PTR(ret);
9636 }
9637
9638 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9639  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9640 static void
9641 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9642                              unsigned *prepare_pipes, unsigned *disable_pipes)
9643 {
9644         struct intel_crtc *intel_crtc;
9645         struct drm_device *dev = crtc->dev;
9646         struct intel_encoder *encoder;
9647         struct intel_connector *connector;
9648         struct drm_crtc *tmp_crtc;
9649
9650         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9651
9652         /* Check which crtcs have changed outputs connected to them, these need
9653          * to be part of the prepare_pipes mask. We don't (yet) support global
9654          * modeset across multiple crtcs, so modeset_pipes will only have one
9655          * bit set at most. */
9656         list_for_each_entry(connector, &dev->mode_config.connector_list,
9657                             base.head) {
9658                 if (connector->base.encoder == &connector->new_encoder->base)
9659                         continue;
9660
9661                 if (connector->base.encoder) {
9662                         tmp_crtc = connector->base.encoder->crtc;
9663
9664                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9665                 }
9666
9667                 if (connector->new_encoder)
9668                         *prepare_pipes |=
9669                                 1 << connector->new_encoder->new_crtc->pipe;
9670         }
9671
9672         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9673                             base.head) {
9674                 if (encoder->base.crtc == &encoder->new_crtc->base)
9675                         continue;
9676
9677                 if (encoder->base.crtc) {
9678                         tmp_crtc = encoder->base.crtc;
9679
9680                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9681                 }
9682
9683                 if (encoder->new_crtc)
9684                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9685         }
9686
9687         /* Check for pipes that will be enabled/disabled ... */
9688         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9689                             base.head) {
9690                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9691                         continue;
9692
9693                 if (!intel_crtc->new_enabled)
9694                         *disable_pipes |= 1 << intel_crtc->pipe;
9695                 else
9696                         *prepare_pipes |= 1 << intel_crtc->pipe;
9697         }
9698
9699
9700         /* set_mode is also used to update properties on life display pipes. */
9701         intel_crtc = to_intel_crtc(crtc);
9702         if (intel_crtc->new_enabled)
9703                 *prepare_pipes |= 1 << intel_crtc->pipe;
9704
9705         /*
9706          * For simplicity do a full modeset on any pipe where the output routing
9707          * changed. We could be more clever, but that would require us to be
9708          * more careful with calling the relevant encoder->mode_set functions.
9709          */
9710         if (*prepare_pipes)
9711                 *modeset_pipes = *prepare_pipes;
9712
9713         /* ... and mask these out. */
9714         *modeset_pipes &= ~(*disable_pipes);
9715         *prepare_pipes &= ~(*disable_pipes);
9716
9717         /*
9718          * HACK: We don't (yet) fully support global modesets. intel_set_config
9719          * obies this rule, but the modeset restore mode of
9720          * intel_modeset_setup_hw_state does not.
9721          */
9722         *modeset_pipes &= 1 << intel_crtc->pipe;
9723         *prepare_pipes &= 1 << intel_crtc->pipe;
9724
9725         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9726                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9727 }
9728
9729 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9730 {
9731         struct drm_encoder *encoder;
9732         struct drm_device *dev = crtc->dev;
9733
9734         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9735                 if (encoder->crtc == crtc)
9736                         return true;
9737
9738         return false;
9739 }
9740
9741 static void
9742 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9743 {
9744         struct intel_encoder *intel_encoder;
9745         struct intel_crtc *intel_crtc;
9746         struct drm_connector *connector;
9747
9748         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9749                             base.head) {
9750                 if (!intel_encoder->base.crtc)
9751                         continue;
9752
9753                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9754
9755                 if (prepare_pipes & (1 << intel_crtc->pipe))
9756                         intel_encoder->connectors_active = false;
9757         }
9758
9759         intel_modeset_commit_output_state(dev);
9760
9761         /* Double check state. */
9762         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9763                             base.head) {
9764                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9765                 WARN_ON(intel_crtc->new_config &&
9766                         intel_crtc->new_config != &intel_crtc->config);
9767                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9768         }
9769
9770         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9771                 if (!connector->encoder || !connector->encoder->crtc)
9772                         continue;
9773
9774                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9775
9776                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9777                         struct drm_property *dpms_property =
9778                                 dev->mode_config.dpms_property;
9779
9780                         connector->dpms = DRM_MODE_DPMS_ON;
9781                         drm_object_property_set_value(&connector->base,
9782                                                          dpms_property,
9783                                                          DRM_MODE_DPMS_ON);
9784
9785                         intel_encoder = to_intel_encoder(connector->encoder);
9786                         intel_encoder->connectors_active = true;
9787                 }
9788         }
9789
9790 }
9791
9792 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9793 {
9794         int diff;
9795
9796         if (clock1 == clock2)
9797                 return true;
9798
9799         if (!clock1 || !clock2)
9800                 return false;
9801
9802         diff = abs(clock1 - clock2);
9803
9804         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9805                 return true;
9806
9807         return false;
9808 }
9809
9810 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9811         list_for_each_entry((intel_crtc), \
9812                             &(dev)->mode_config.crtc_list, \
9813                             base.head) \
9814                 if (mask & (1 <<(intel_crtc)->pipe))
9815
9816 static bool
9817 intel_pipe_config_compare(struct drm_device *dev,
9818                           struct intel_crtc_config *current_config,
9819                           struct intel_crtc_config *pipe_config)
9820 {
9821 #define PIPE_CONF_CHECK_X(name) \
9822         if (current_config->name != pipe_config->name) { \
9823                 DRM_ERROR("mismatch in " #name " " \
9824                           "(expected 0x%08x, found 0x%08x)\n", \
9825                           current_config->name, \
9826                           pipe_config->name); \
9827                 return false; \
9828         }
9829
9830 #define PIPE_CONF_CHECK_I(name) \
9831         if (current_config->name != pipe_config->name) { \
9832                 DRM_ERROR("mismatch in " #name " " \
9833                           "(expected %i, found %i)\n", \
9834                           current_config->name, \
9835                           pipe_config->name); \
9836                 return false; \
9837         }
9838
9839 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9840         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9841                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9842                           "(expected %i, found %i)\n", \
9843                           current_config->name & (mask), \
9844                           pipe_config->name & (mask)); \
9845                 return false; \
9846         }
9847
9848 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9849         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9850                 DRM_ERROR("mismatch in " #name " " \
9851                           "(expected %i, found %i)\n", \
9852                           current_config->name, \
9853                           pipe_config->name); \
9854                 return false; \
9855         }
9856
9857 #define PIPE_CONF_QUIRK(quirk)  \
9858         ((current_config->quirks | pipe_config->quirks) & (quirk))
9859
9860         PIPE_CONF_CHECK_I(cpu_transcoder);
9861
9862         PIPE_CONF_CHECK_I(has_pch_encoder);
9863         PIPE_CONF_CHECK_I(fdi_lanes);
9864         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9865         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9866         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9867         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9868         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9869
9870         PIPE_CONF_CHECK_I(has_dp_encoder);
9871         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9872         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9873         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9874         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9875         PIPE_CONF_CHECK_I(dp_m_n.tu);
9876
9877         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9878         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9879         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9880         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9881         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9882         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9883
9884         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9885         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9886         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9887         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9888         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9889         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9890
9891         PIPE_CONF_CHECK_I(pixel_multiplier);
9892
9893         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9894                               DRM_MODE_FLAG_INTERLACE);
9895
9896         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9897                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9898                                       DRM_MODE_FLAG_PHSYNC);
9899                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9900                                       DRM_MODE_FLAG_NHSYNC);
9901                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9902                                       DRM_MODE_FLAG_PVSYNC);
9903                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9904                                       DRM_MODE_FLAG_NVSYNC);
9905         }
9906
9907         PIPE_CONF_CHECK_I(pipe_src_w);
9908         PIPE_CONF_CHECK_I(pipe_src_h);
9909
9910         /*
9911          * FIXME: BIOS likes to set up a cloned config with lvds+external
9912          * screen. Since we don't yet re-compute the pipe config when moving
9913          * just the lvds port away to another pipe the sw tracking won't match.
9914          *
9915          * Proper atomic modesets with recomputed global state will fix this.
9916          * Until then just don't check gmch state for inherited modes.
9917          */
9918         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9919                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9920                 /* pfit ratios are autocomputed by the hw on gen4+ */
9921                 if (INTEL_INFO(dev)->gen < 4)
9922                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9923                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9924         }
9925
9926         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9927         if (current_config->pch_pfit.enabled) {
9928                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9929                 PIPE_CONF_CHECK_I(pch_pfit.size);
9930         }
9931
9932         /* BDW+ don't expose a synchronous way to read the state */
9933         if (IS_HASWELL(dev))
9934                 PIPE_CONF_CHECK_I(ips_enabled);
9935
9936         PIPE_CONF_CHECK_I(double_wide);
9937
9938         PIPE_CONF_CHECK_I(shared_dpll);
9939         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9940         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9941         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9942         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9943
9944         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9945                 PIPE_CONF_CHECK_I(pipe_bpp);
9946
9947         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9948         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9949
9950 #undef PIPE_CONF_CHECK_X
9951 #undef PIPE_CONF_CHECK_I
9952 #undef PIPE_CONF_CHECK_FLAGS
9953 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9954 #undef PIPE_CONF_QUIRK
9955
9956         return true;
9957 }
9958
9959 static void
9960 check_connector_state(struct drm_device *dev)
9961 {
9962         struct intel_connector *connector;
9963
9964         list_for_each_entry(connector, &dev->mode_config.connector_list,
9965                             base.head) {
9966                 /* This also checks the encoder/connector hw state with the
9967                  * ->get_hw_state callbacks. */
9968                 intel_connector_check_state(connector);
9969
9970                 WARN(&connector->new_encoder->base != connector->base.encoder,
9971                      "connector's staged encoder doesn't match current encoder\n");
9972         }
9973 }
9974
9975 static void
9976 check_encoder_state(struct drm_device *dev)
9977 {
9978         struct intel_encoder *encoder;
9979         struct intel_connector *connector;
9980
9981         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9982                             base.head) {
9983                 bool enabled = false;
9984                 bool active = false;
9985                 enum pipe pipe, tracked_pipe;
9986
9987                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9988                               encoder->base.base.id,
9989                               drm_get_encoder_name(&encoder->base));
9990
9991                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9992                      "encoder's stage crtc doesn't match current crtc\n");
9993                 WARN(encoder->connectors_active && !encoder->base.crtc,
9994                      "encoder's active_connectors set, but no crtc\n");
9995
9996                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9997                                     base.head) {
9998                         if (connector->base.encoder != &encoder->base)
9999                                 continue;
10000                         enabled = true;
10001                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10002                                 active = true;
10003                 }
10004                 WARN(!!encoder->base.crtc != enabled,
10005                      "encoder's enabled state mismatch "
10006                      "(expected %i, found %i)\n",
10007                      !!encoder->base.crtc, enabled);
10008                 WARN(active && !encoder->base.crtc,
10009                      "active encoder with no crtc\n");
10010
10011                 WARN(encoder->connectors_active != active,
10012                      "encoder's computed active state doesn't match tracked active state "
10013                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10014
10015                 active = encoder->get_hw_state(encoder, &pipe);
10016                 WARN(active != encoder->connectors_active,
10017                      "encoder's hw state doesn't match sw tracking "
10018                      "(expected %i, found %i)\n",
10019                      encoder->connectors_active, active);
10020
10021                 if (!encoder->base.crtc)
10022                         continue;
10023
10024                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10025                 WARN(active && pipe != tracked_pipe,
10026                      "active encoder's pipe doesn't match"
10027                      "(expected %i, found %i)\n",
10028                      tracked_pipe, pipe);
10029
10030         }
10031 }
10032
10033 static void
10034 check_crtc_state(struct drm_device *dev)
10035 {
10036         struct drm_i915_private *dev_priv = dev->dev_private;
10037         struct intel_crtc *crtc;
10038         struct intel_encoder *encoder;
10039         struct intel_crtc_config pipe_config;
10040
10041         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10042                             base.head) {
10043                 bool enabled = false;
10044                 bool active = false;
10045
10046                 memset(&pipe_config, 0, sizeof(pipe_config));
10047
10048                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10049                               crtc->base.base.id);
10050
10051                 WARN(crtc->active && !crtc->base.enabled,
10052                      "active crtc, but not enabled in sw tracking\n");
10053
10054                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10055                                     base.head) {
10056                         if (encoder->base.crtc != &crtc->base)
10057                                 continue;
10058                         enabled = true;
10059                         if (encoder->connectors_active)
10060                                 active = true;
10061                 }
10062
10063                 WARN(active != crtc->active,
10064                      "crtc's computed active state doesn't match tracked active state "
10065                      "(expected %i, found %i)\n", active, crtc->active);
10066                 WARN(enabled != crtc->base.enabled,
10067                      "crtc's computed enabled state doesn't match tracked enabled state "
10068                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10069
10070                 active = dev_priv->display.get_pipe_config(crtc,
10071                                                            &pipe_config);
10072
10073                 /* hw state is inconsistent with the pipe A quirk */
10074                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10075                         active = crtc->active;
10076
10077                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10078                                     base.head) {
10079                         enum pipe pipe;
10080                         if (encoder->base.crtc != &crtc->base)
10081                                 continue;
10082                         if (encoder->get_hw_state(encoder, &pipe))
10083                                 encoder->get_config(encoder, &pipe_config);
10084                 }
10085
10086                 WARN(crtc->active != active,
10087                      "crtc active state doesn't match with hw state "
10088                      "(expected %i, found %i)\n", crtc->active, active);
10089
10090                 if (active &&
10091                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10092                         WARN(1, "pipe state doesn't match!\n");
10093                         intel_dump_pipe_config(crtc, &pipe_config,
10094                                                "[hw state]");
10095                         intel_dump_pipe_config(crtc, &crtc->config,
10096                                                "[sw state]");
10097                 }
10098         }
10099 }
10100
10101 static void
10102 check_shared_dpll_state(struct drm_device *dev)
10103 {
10104         struct drm_i915_private *dev_priv = dev->dev_private;
10105         struct intel_crtc *crtc;
10106         struct intel_dpll_hw_state dpll_hw_state;
10107         int i;
10108
10109         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10110                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10111                 int enabled_crtcs = 0, active_crtcs = 0;
10112                 bool active;
10113
10114                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10115
10116                 DRM_DEBUG_KMS("%s\n", pll->name);
10117
10118                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10119
10120                 WARN(pll->active > pll->refcount,
10121                      "more active pll users than references: %i vs %i\n",
10122                      pll->active, pll->refcount);
10123                 WARN(pll->active && !pll->on,
10124                      "pll in active use but not on in sw tracking\n");
10125                 WARN(pll->on && !pll->active,
10126                      "pll in on but not on in use in sw tracking\n");
10127                 WARN(pll->on != active,
10128                      "pll on state mismatch (expected %i, found %i)\n",
10129                      pll->on, active);
10130
10131                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10132                                     base.head) {
10133                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10134                                 enabled_crtcs++;
10135                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10136                                 active_crtcs++;
10137                 }
10138                 WARN(pll->active != active_crtcs,
10139                      "pll active crtcs mismatch (expected %i, found %i)\n",
10140                      pll->active, active_crtcs);
10141                 WARN(pll->refcount != enabled_crtcs,
10142                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10143                      pll->refcount, enabled_crtcs);
10144
10145                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10146                                        sizeof(dpll_hw_state)),
10147                      "pll hw state mismatch\n");
10148         }
10149 }
10150
10151 void
10152 intel_modeset_check_state(struct drm_device *dev)
10153 {
10154         check_connector_state(dev);
10155         check_encoder_state(dev);
10156         check_crtc_state(dev);
10157         check_shared_dpll_state(dev);
10158 }
10159
10160 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10161                                      int dotclock)
10162 {
10163         /*
10164          * FDI already provided one idea for the dotclock.
10165          * Yell if the encoder disagrees.
10166          */
10167         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10168              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10169              pipe_config->adjusted_mode.crtc_clock, dotclock);
10170 }
10171
10172 static int __intel_set_mode(struct drm_crtc *crtc,
10173                             struct drm_display_mode *mode,
10174                             int x, int y, struct drm_framebuffer *fb)
10175 {
10176         struct drm_device *dev = crtc->dev;
10177         struct drm_i915_private *dev_priv = dev->dev_private;
10178         struct drm_display_mode *saved_mode;
10179         struct intel_crtc_config *pipe_config = NULL;
10180         struct intel_crtc *intel_crtc;
10181         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10182         int ret = 0;
10183
10184         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10185         if (!saved_mode)
10186                 return -ENOMEM;
10187
10188         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10189                                      &prepare_pipes, &disable_pipes);
10190
10191         *saved_mode = crtc->mode;
10192
10193         /* Hack: Because we don't (yet) support global modeset on multiple
10194          * crtcs, we don't keep track of the new mode for more than one crtc.
10195          * Hence simply check whether any bit is set in modeset_pipes in all the
10196          * pieces of code that are not yet converted to deal with mutliple crtcs
10197          * changing their mode at the same time. */
10198         if (modeset_pipes) {
10199                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10200                 if (IS_ERR(pipe_config)) {
10201                         ret = PTR_ERR(pipe_config);
10202                         pipe_config = NULL;
10203
10204                         goto out;
10205                 }
10206                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10207                                        "[modeset]");
10208                 to_intel_crtc(crtc)->new_config = pipe_config;
10209         }
10210
10211         /*
10212          * See if the config requires any additional preparation, e.g.
10213          * to adjust global state with pipes off.  We need to do this
10214          * here so we can get the modeset_pipe updated config for the new
10215          * mode set on this crtc.  For other crtcs we need to use the
10216          * adjusted_mode bits in the crtc directly.
10217          */
10218         if (IS_VALLEYVIEW(dev)) {
10219                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10220
10221                 /* may have added more to prepare_pipes than we should */
10222                 prepare_pipes &= ~disable_pipes;
10223         }
10224
10225         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10226                 intel_crtc_disable(&intel_crtc->base);
10227
10228         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10229                 if (intel_crtc->base.enabled)
10230                         dev_priv->display.crtc_disable(&intel_crtc->base);
10231         }
10232
10233         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10234          * to set it here already despite that we pass it down the callchain.
10235          */
10236         if (modeset_pipes) {
10237                 crtc->mode = *mode;
10238                 /* mode_set/enable/disable functions rely on a correct pipe
10239                  * config. */
10240                 to_intel_crtc(crtc)->config = *pipe_config;
10241                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10242
10243                 /*
10244                  * Calculate and store various constants which
10245                  * are later needed by vblank and swap-completion
10246                  * timestamping. They are derived from true hwmode.
10247                  */
10248                 drm_calc_timestamping_constants(crtc,
10249                                                 &pipe_config->adjusted_mode);
10250         }
10251
10252         /* Only after disabling all output pipelines that will be changed can we
10253          * update the the output configuration. */
10254         intel_modeset_update_state(dev, prepare_pipes);
10255
10256         if (dev_priv->display.modeset_global_resources)
10257                 dev_priv->display.modeset_global_resources(dev);
10258
10259         /* Set up the DPLL and any encoders state that needs to adjust or depend
10260          * on the DPLL.
10261          */
10262         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10263                 ret = intel_crtc_mode_set(&intel_crtc->base,
10264                                           x, y, fb);
10265                 if (ret)
10266                         goto done;
10267         }
10268
10269         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10270         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10271                 dev_priv->display.crtc_enable(&intel_crtc->base);
10272
10273         /* FIXME: add subpixel order */
10274 done:
10275         if (ret && crtc->enabled)
10276                 crtc->mode = *saved_mode;
10277
10278 out:
10279         kfree(pipe_config);
10280         kfree(saved_mode);
10281         return ret;
10282 }
10283
10284 static int intel_set_mode(struct drm_crtc *crtc,
10285                           struct drm_display_mode *mode,
10286                           int x, int y, struct drm_framebuffer *fb)
10287 {
10288         int ret;
10289
10290         ret = __intel_set_mode(crtc, mode, x, y, fb);
10291
10292         if (ret == 0)
10293                 intel_modeset_check_state(crtc->dev);
10294
10295         return ret;
10296 }
10297
10298 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10299 {
10300         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10301 }
10302
10303 #undef for_each_intel_crtc_masked
10304
10305 static void intel_set_config_free(struct intel_set_config *config)
10306 {
10307         if (!config)
10308                 return;
10309
10310         kfree(config->save_connector_encoders);
10311         kfree(config->save_encoder_crtcs);
10312         kfree(config->save_crtc_enabled);
10313         kfree(config);
10314 }
10315
10316 static int intel_set_config_save_state(struct drm_device *dev,
10317                                        struct intel_set_config *config)
10318 {
10319         struct drm_crtc *crtc;
10320         struct drm_encoder *encoder;
10321         struct drm_connector *connector;
10322         int count;
10323
10324         config->save_crtc_enabled =
10325                 kcalloc(dev->mode_config.num_crtc,
10326                         sizeof(bool), GFP_KERNEL);
10327         if (!config->save_crtc_enabled)
10328                 return -ENOMEM;
10329
10330         config->save_encoder_crtcs =
10331                 kcalloc(dev->mode_config.num_encoder,
10332                         sizeof(struct drm_crtc *), GFP_KERNEL);
10333         if (!config->save_encoder_crtcs)
10334                 return -ENOMEM;
10335
10336         config->save_connector_encoders =
10337                 kcalloc(dev->mode_config.num_connector,
10338                         sizeof(struct drm_encoder *), GFP_KERNEL);
10339         if (!config->save_connector_encoders)
10340                 return -ENOMEM;
10341
10342         /* Copy data. Note that driver private data is not affected.
10343          * Should anything bad happen only the expected state is
10344          * restored, not the drivers personal bookkeeping.
10345          */
10346         count = 0;
10347         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10348                 config->save_crtc_enabled[count++] = crtc->enabled;
10349         }
10350
10351         count = 0;
10352         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10353                 config->save_encoder_crtcs[count++] = encoder->crtc;
10354         }
10355
10356         count = 0;
10357         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10358                 config->save_connector_encoders[count++] = connector->encoder;
10359         }
10360
10361         return 0;
10362 }
10363
10364 static void intel_set_config_restore_state(struct drm_device *dev,
10365                                            struct intel_set_config *config)
10366 {
10367         struct intel_crtc *crtc;
10368         struct intel_encoder *encoder;
10369         struct intel_connector *connector;
10370         int count;
10371
10372         count = 0;
10373         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10374                 crtc->new_enabled = config->save_crtc_enabled[count++];
10375
10376                 if (crtc->new_enabled)
10377                         crtc->new_config = &crtc->config;
10378                 else
10379                         crtc->new_config = NULL;
10380         }
10381
10382         count = 0;
10383         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10384                 encoder->new_crtc =
10385                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10386         }
10387
10388         count = 0;
10389         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10390                 connector->new_encoder =
10391                         to_intel_encoder(config->save_connector_encoders[count++]);
10392         }
10393 }
10394
10395 static bool
10396 is_crtc_connector_off(struct drm_mode_set *set)
10397 {
10398         int i;
10399
10400         if (set->num_connectors == 0)
10401                 return false;
10402
10403         if (WARN_ON(set->connectors == NULL))
10404                 return false;
10405
10406         for (i = 0; i < set->num_connectors; i++)
10407                 if (set->connectors[i]->encoder &&
10408                     set->connectors[i]->encoder->crtc == set->crtc &&
10409                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10410                         return true;
10411
10412         return false;
10413 }
10414
10415 static void
10416 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10417                                       struct intel_set_config *config)
10418 {
10419
10420         /* We should be able to check here if the fb has the same properties
10421          * and then just flip_or_move it */
10422         if (is_crtc_connector_off(set)) {
10423                 config->mode_changed = true;
10424         } else if (set->crtc->primary->fb != set->fb) {
10425                 /* If we have no fb then treat it as a full mode set */
10426                 if (set->crtc->primary->fb == NULL) {
10427                         struct intel_crtc *intel_crtc =
10428                                 to_intel_crtc(set->crtc);
10429
10430                         if (intel_crtc->active && i915.fastboot) {
10431                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10432                                 config->fb_changed = true;
10433                         } else {
10434                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10435                                 config->mode_changed = true;
10436                         }
10437                 } else if (set->fb == NULL) {
10438                         config->mode_changed = true;
10439                 } else if (set->fb->pixel_format !=
10440                            set->crtc->primary->fb->pixel_format) {
10441                         config->mode_changed = true;
10442                 } else {
10443                         config->fb_changed = true;
10444                 }
10445         }
10446
10447         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10448                 config->fb_changed = true;
10449
10450         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10451                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10452                 drm_mode_debug_printmodeline(&set->crtc->mode);
10453                 drm_mode_debug_printmodeline(set->mode);
10454                 config->mode_changed = true;
10455         }
10456
10457         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10458                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10459 }
10460
10461 static int
10462 intel_modeset_stage_output_state(struct drm_device *dev,
10463                                  struct drm_mode_set *set,
10464                                  struct intel_set_config *config)
10465 {
10466         struct intel_connector *connector;
10467         struct intel_encoder *encoder;
10468         struct intel_crtc *crtc;
10469         int ro;
10470
10471         /* The upper layers ensure that we either disable a crtc or have a list
10472          * of connectors. For paranoia, double-check this. */
10473         WARN_ON(!set->fb && (set->num_connectors != 0));
10474         WARN_ON(set->fb && (set->num_connectors == 0));
10475
10476         list_for_each_entry(connector, &dev->mode_config.connector_list,
10477                             base.head) {
10478                 /* Otherwise traverse passed in connector list and get encoders
10479                  * for them. */
10480                 for (ro = 0; ro < set->num_connectors; ro++) {
10481                         if (set->connectors[ro] == &connector->base) {
10482                                 connector->new_encoder = connector->encoder;
10483                                 break;
10484                         }
10485                 }
10486
10487                 /* If we disable the crtc, disable all its connectors. Also, if
10488                  * the connector is on the changing crtc but not on the new
10489                  * connector list, disable it. */
10490                 if ((!set->fb || ro == set->num_connectors) &&
10491                     connector->base.encoder &&
10492                     connector->base.encoder->crtc == set->crtc) {
10493                         connector->new_encoder = NULL;
10494
10495                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10496                                 connector->base.base.id,
10497                                 drm_get_connector_name(&connector->base));
10498                 }
10499
10500
10501                 if (&connector->new_encoder->base != connector->base.encoder) {
10502                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10503                         config->mode_changed = true;
10504                 }
10505         }
10506         /* connector->new_encoder is now updated for all connectors. */
10507
10508         /* Update crtc of enabled connectors. */
10509         list_for_each_entry(connector, &dev->mode_config.connector_list,
10510                             base.head) {
10511                 struct drm_crtc *new_crtc;
10512
10513                 if (!connector->new_encoder)
10514                         continue;
10515
10516                 new_crtc = connector->new_encoder->base.crtc;
10517
10518                 for (ro = 0; ro < set->num_connectors; ro++) {
10519                         if (set->connectors[ro] == &connector->base)
10520                                 new_crtc = set->crtc;
10521                 }
10522
10523                 /* Make sure the new CRTC will work with the encoder */
10524                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10525                                          new_crtc)) {
10526                         return -EINVAL;
10527                 }
10528                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10529
10530                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10531                         connector->base.base.id,
10532                         drm_get_connector_name(&connector->base),
10533                         new_crtc->base.id);
10534         }
10535
10536         /* Check for any encoders that needs to be disabled. */
10537         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10538                             base.head) {
10539                 int num_connectors = 0;
10540                 list_for_each_entry(connector,
10541                                     &dev->mode_config.connector_list,
10542                                     base.head) {
10543                         if (connector->new_encoder == encoder) {
10544                                 WARN_ON(!connector->new_encoder->new_crtc);
10545                                 num_connectors++;
10546                         }
10547                 }
10548
10549                 if (num_connectors == 0)
10550                         encoder->new_crtc = NULL;
10551                 else if (num_connectors > 1)
10552                         return -EINVAL;
10553
10554                 /* Only now check for crtc changes so we don't miss encoders
10555                  * that will be disabled. */
10556                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10557                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10558                         config->mode_changed = true;
10559                 }
10560         }
10561         /* Now we've also updated encoder->new_crtc for all encoders. */
10562
10563         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10564                             base.head) {
10565                 crtc->new_enabled = false;
10566
10567                 list_for_each_entry(encoder,
10568                                     &dev->mode_config.encoder_list,
10569                                     base.head) {
10570                         if (encoder->new_crtc == crtc) {
10571                                 crtc->new_enabled = true;
10572                                 break;
10573                         }
10574                 }
10575
10576                 if (crtc->new_enabled != crtc->base.enabled) {
10577                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10578                                       crtc->new_enabled ? "en" : "dis");
10579                         config->mode_changed = true;
10580                 }
10581
10582                 if (crtc->new_enabled)
10583                         crtc->new_config = &crtc->config;
10584                 else
10585                         crtc->new_config = NULL;
10586         }
10587
10588         return 0;
10589 }
10590
10591 static void disable_crtc_nofb(struct intel_crtc *crtc)
10592 {
10593         struct drm_device *dev = crtc->base.dev;
10594         struct intel_encoder *encoder;
10595         struct intel_connector *connector;
10596
10597         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10598                       pipe_name(crtc->pipe));
10599
10600         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10601                 if (connector->new_encoder &&
10602                     connector->new_encoder->new_crtc == crtc)
10603                         connector->new_encoder = NULL;
10604         }
10605
10606         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10607                 if (encoder->new_crtc == crtc)
10608                         encoder->new_crtc = NULL;
10609         }
10610
10611         crtc->new_enabled = false;
10612         crtc->new_config = NULL;
10613 }
10614
10615 static int intel_crtc_set_config(struct drm_mode_set *set)
10616 {
10617         struct drm_device *dev;
10618         struct drm_mode_set save_set;
10619         struct intel_set_config *config;
10620         int ret;
10621
10622         BUG_ON(!set);
10623         BUG_ON(!set->crtc);
10624         BUG_ON(!set->crtc->helper_private);
10625
10626         /* Enforce sane interface api - has been abused by the fb helper. */
10627         BUG_ON(!set->mode && set->fb);
10628         BUG_ON(set->fb && set->num_connectors == 0);
10629
10630         if (set->fb) {
10631                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10632                                 set->crtc->base.id, set->fb->base.id,
10633                                 (int)set->num_connectors, set->x, set->y);
10634         } else {
10635                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10636         }
10637
10638         dev = set->crtc->dev;
10639
10640         ret = -ENOMEM;
10641         config = kzalloc(sizeof(*config), GFP_KERNEL);
10642         if (!config)
10643                 goto out_config;
10644
10645         ret = intel_set_config_save_state(dev, config);
10646         if (ret)
10647                 goto out_config;
10648
10649         save_set.crtc = set->crtc;
10650         save_set.mode = &set->crtc->mode;
10651         save_set.x = set->crtc->x;
10652         save_set.y = set->crtc->y;
10653         save_set.fb = set->crtc->primary->fb;
10654
10655         /* Compute whether we need a full modeset, only an fb base update or no
10656          * change at all. In the future we might also check whether only the
10657          * mode changed, e.g. for LVDS where we only change the panel fitter in
10658          * such cases. */
10659         intel_set_config_compute_mode_changes(set, config);
10660
10661         ret = intel_modeset_stage_output_state(dev, set, config);
10662         if (ret)
10663                 goto fail;
10664
10665         if (config->mode_changed) {
10666                 ret = intel_set_mode(set->crtc, set->mode,
10667                                      set->x, set->y, set->fb);
10668         } else if (config->fb_changed) {
10669                 intel_crtc_wait_for_pending_flips(set->crtc);
10670
10671                 ret = intel_pipe_set_base(set->crtc,
10672                                           set->x, set->y, set->fb);
10673                 /*
10674                  * In the fastboot case this may be our only check of the
10675                  * state after boot.  It would be better to only do it on
10676                  * the first update, but we don't have a nice way of doing that
10677                  * (and really, set_config isn't used much for high freq page
10678                  * flipping, so increasing its cost here shouldn't be a big
10679                  * deal).
10680                  */
10681                 if (i915.fastboot && ret == 0)
10682                         intel_modeset_check_state(set->crtc->dev);
10683         }
10684
10685         if (ret) {
10686                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10687                               set->crtc->base.id, ret);
10688 fail:
10689                 intel_set_config_restore_state(dev, config);
10690
10691                 /*
10692                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10693                  * force the pipe off to avoid oopsing in the modeset code
10694                  * due to fb==NULL. This should only happen during boot since
10695                  * we don't yet reconstruct the FB from the hardware state.
10696                  */
10697                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10698                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10699
10700                 /* Try to restore the config */
10701                 if (config->mode_changed &&
10702                     intel_set_mode(save_set.crtc, save_set.mode,
10703                                    save_set.x, save_set.y, save_set.fb))
10704                         DRM_ERROR("failed to restore config after modeset failure\n");
10705         }
10706
10707 out_config:
10708         intel_set_config_free(config);
10709         return ret;
10710 }
10711
10712 static const struct drm_crtc_funcs intel_crtc_funcs = {
10713         .cursor_set = intel_crtc_cursor_set,
10714         .cursor_move = intel_crtc_cursor_move,
10715         .gamma_set = intel_crtc_gamma_set,
10716         .set_config = intel_crtc_set_config,
10717         .destroy = intel_crtc_destroy,
10718         .page_flip = intel_crtc_page_flip,
10719 };
10720
10721 static void intel_cpu_pll_init(struct drm_device *dev)
10722 {
10723         if (HAS_DDI(dev))
10724                 intel_ddi_pll_init(dev);
10725 }
10726
10727 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10728                                       struct intel_shared_dpll *pll,
10729                                       struct intel_dpll_hw_state *hw_state)
10730 {
10731         uint32_t val;
10732
10733         val = I915_READ(PCH_DPLL(pll->id));
10734         hw_state->dpll = val;
10735         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10736         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10737
10738         return val & DPLL_VCO_ENABLE;
10739 }
10740
10741 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10742                                   struct intel_shared_dpll *pll)
10743 {
10744         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10745         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10746 }
10747
10748 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10749                                 struct intel_shared_dpll *pll)
10750 {
10751         /* PCH refclock must be enabled first */
10752         ibx_assert_pch_refclk_enabled(dev_priv);
10753
10754         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10755
10756         /* Wait for the clocks to stabilize. */
10757         POSTING_READ(PCH_DPLL(pll->id));
10758         udelay(150);
10759
10760         /* The pixel multiplier can only be updated once the
10761          * DPLL is enabled and the clocks are stable.
10762          *
10763          * So write it again.
10764          */
10765         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10766         POSTING_READ(PCH_DPLL(pll->id));
10767         udelay(200);
10768 }
10769
10770 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10771                                  struct intel_shared_dpll *pll)
10772 {
10773         struct drm_device *dev = dev_priv->dev;
10774         struct intel_crtc *crtc;
10775
10776         /* Make sure no transcoder isn't still depending on us. */
10777         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10778                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10779                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10780         }
10781
10782         I915_WRITE(PCH_DPLL(pll->id), 0);
10783         POSTING_READ(PCH_DPLL(pll->id));
10784         udelay(200);
10785 }
10786
10787 static char *ibx_pch_dpll_names[] = {
10788         "PCH DPLL A",
10789         "PCH DPLL B",
10790 };
10791
10792 static void ibx_pch_dpll_init(struct drm_device *dev)
10793 {
10794         struct drm_i915_private *dev_priv = dev->dev_private;
10795         int i;
10796
10797         dev_priv->num_shared_dpll = 2;
10798
10799         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10800                 dev_priv->shared_dplls[i].id = i;
10801                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10802                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10803                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10804                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10805                 dev_priv->shared_dplls[i].get_hw_state =
10806                         ibx_pch_dpll_get_hw_state;
10807         }
10808 }
10809
10810 static void intel_shared_dpll_init(struct drm_device *dev)
10811 {
10812         struct drm_i915_private *dev_priv = dev->dev_private;
10813
10814         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10815                 ibx_pch_dpll_init(dev);
10816         else
10817                 dev_priv->num_shared_dpll = 0;
10818
10819         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10820 }
10821
10822 static void intel_crtc_init(struct drm_device *dev, int pipe)
10823 {
10824         struct drm_i915_private *dev_priv = dev->dev_private;
10825         struct intel_crtc *intel_crtc;
10826         int i;
10827
10828         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10829         if (intel_crtc == NULL)
10830                 return;
10831
10832         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10833
10834         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10835         for (i = 0; i < 256; i++) {
10836                 intel_crtc->lut_r[i] = i;
10837                 intel_crtc->lut_g[i] = i;
10838                 intel_crtc->lut_b[i] = i;
10839         }
10840
10841         /*
10842          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10843          * is hooked to plane B. Hence we want plane A feeding pipe B.
10844          */
10845         intel_crtc->pipe = pipe;
10846         intel_crtc->plane = pipe;
10847         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10848                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10849                 intel_crtc->plane = !pipe;
10850         }
10851
10852         init_waitqueue_head(&intel_crtc->vbl_wait);
10853
10854         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10855                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10856         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10857         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10858
10859         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10860 }
10861
10862 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10863 {
10864         struct drm_encoder *encoder = connector->base.encoder;
10865
10866         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10867
10868         if (!encoder)
10869                 return INVALID_PIPE;
10870
10871         return to_intel_crtc(encoder->crtc)->pipe;
10872 }
10873
10874 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10875                                 struct drm_file *file)
10876 {
10877         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10878         struct drm_mode_object *drmmode_obj;
10879         struct intel_crtc *crtc;
10880
10881         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10882                 return -ENODEV;
10883
10884         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10885                         DRM_MODE_OBJECT_CRTC);
10886
10887         if (!drmmode_obj) {
10888                 DRM_ERROR("no such CRTC id\n");
10889                 return -ENOENT;
10890         }
10891
10892         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10893         pipe_from_crtc_id->pipe = crtc->pipe;
10894
10895         return 0;
10896 }
10897
10898 static int intel_encoder_clones(struct intel_encoder *encoder)
10899 {
10900         struct drm_device *dev = encoder->base.dev;
10901         struct intel_encoder *source_encoder;
10902         int index_mask = 0;
10903         int entry = 0;
10904
10905         list_for_each_entry(source_encoder,
10906                             &dev->mode_config.encoder_list, base.head) {
10907                 if (encoders_cloneable(encoder, source_encoder))
10908                         index_mask |= (1 << entry);
10909
10910                 entry++;
10911         }
10912
10913         return index_mask;
10914 }
10915
10916 static bool has_edp_a(struct drm_device *dev)
10917 {
10918         struct drm_i915_private *dev_priv = dev->dev_private;
10919
10920         if (!IS_MOBILE(dev))
10921                 return false;
10922
10923         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10924                 return false;
10925
10926         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10927                 return false;
10928
10929         return true;
10930 }
10931
10932 const char *intel_output_name(int output)
10933 {
10934         static const char *names[] = {
10935                 [INTEL_OUTPUT_UNUSED] = "Unused",
10936                 [INTEL_OUTPUT_ANALOG] = "Analog",
10937                 [INTEL_OUTPUT_DVO] = "DVO",
10938                 [INTEL_OUTPUT_SDVO] = "SDVO",
10939                 [INTEL_OUTPUT_LVDS] = "LVDS",
10940                 [INTEL_OUTPUT_TVOUT] = "TV",
10941                 [INTEL_OUTPUT_HDMI] = "HDMI",
10942                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10943                 [INTEL_OUTPUT_EDP] = "eDP",
10944                 [INTEL_OUTPUT_DSI] = "DSI",
10945                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10946         };
10947
10948         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10949                 return "Invalid";
10950
10951         return names[output];
10952 }
10953
10954 static void intel_setup_outputs(struct drm_device *dev)
10955 {
10956         struct drm_i915_private *dev_priv = dev->dev_private;
10957         struct intel_encoder *encoder;
10958         bool dpd_is_edp = false;
10959
10960         intel_lvds_init(dev);
10961
10962         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10963                 intel_crt_init(dev);
10964
10965         if (HAS_DDI(dev)) {
10966                 int found;
10967
10968                 /* Haswell uses DDI functions to detect digital outputs */
10969                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10970                 /* DDI A only supports eDP */
10971                 if (found)
10972                         intel_ddi_init(dev, PORT_A);
10973
10974                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10975                  * register */
10976                 found = I915_READ(SFUSE_STRAP);
10977
10978                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10979                         intel_ddi_init(dev, PORT_B);
10980                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10981                         intel_ddi_init(dev, PORT_C);
10982                 if (found & SFUSE_STRAP_DDID_DETECTED)
10983                         intel_ddi_init(dev, PORT_D);
10984         } else if (HAS_PCH_SPLIT(dev)) {
10985                 int found;
10986                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10987
10988                 if (has_edp_a(dev))
10989                         intel_dp_init(dev, DP_A, PORT_A);
10990
10991                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10992                         /* PCH SDVOB multiplex with HDMIB */
10993                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10994                         if (!found)
10995                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10996                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10997                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
10998                 }
10999
11000                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11001                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11002
11003                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11004                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11005
11006                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11007                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11008
11009                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11010                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11011         } else if (IS_VALLEYVIEW(dev)) {
11012                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11013                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11014                                         PORT_B);
11015                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11016                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11017                 }
11018
11019                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11020                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11021                                         PORT_C);
11022                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11023                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11024                 }
11025
11026                 intel_dsi_init(dev);
11027         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11028                 bool found = false;
11029
11030                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11031                         DRM_DEBUG_KMS("probing SDVOB\n");
11032                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11033                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11034                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11035                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11036                         }
11037
11038                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11039                                 intel_dp_init(dev, DP_B, PORT_B);
11040                 }
11041
11042                 /* Before G4X SDVOC doesn't have its own detect register */
11043
11044                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11045                         DRM_DEBUG_KMS("probing SDVOC\n");
11046                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11047                 }
11048
11049                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11050
11051                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11052                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11053                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11054                         }
11055                         if (SUPPORTS_INTEGRATED_DP(dev))
11056                                 intel_dp_init(dev, DP_C, PORT_C);
11057                 }
11058
11059                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11060                     (I915_READ(DP_D) & DP_DETECTED))
11061                         intel_dp_init(dev, DP_D, PORT_D);
11062         } else if (IS_GEN2(dev))
11063                 intel_dvo_init(dev);
11064
11065         if (SUPPORTS_TV(dev))
11066                 intel_tv_init(dev);
11067
11068         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11069                 encoder->base.possible_crtcs = encoder->crtc_mask;
11070                 encoder->base.possible_clones =
11071                         intel_encoder_clones(encoder);
11072         }
11073
11074         intel_init_pch_refclk(dev);
11075
11076         drm_helper_move_panel_connectors_to_head(dev);
11077 }
11078
11079 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11080 {
11081         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11082
11083         drm_framebuffer_cleanup(fb);
11084         WARN_ON(!intel_fb->obj->framebuffer_references--);
11085         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11086         kfree(intel_fb);
11087 }
11088
11089 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11090                                                 struct drm_file *file,
11091                                                 unsigned int *handle)
11092 {
11093         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11094         struct drm_i915_gem_object *obj = intel_fb->obj;
11095
11096         return drm_gem_handle_create(file, &obj->base, handle);
11097 }
11098
11099 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11100         .destroy = intel_user_framebuffer_destroy,
11101         .create_handle = intel_user_framebuffer_create_handle,
11102 };
11103
11104 static int intel_framebuffer_init(struct drm_device *dev,
11105                                   struct intel_framebuffer *intel_fb,
11106                                   struct drm_mode_fb_cmd2 *mode_cmd,
11107                                   struct drm_i915_gem_object *obj)
11108 {
11109         int aligned_height;
11110         int pitch_limit;
11111         int ret;
11112
11113         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11114
11115         if (obj->tiling_mode == I915_TILING_Y) {
11116                 DRM_DEBUG("hardware does not support tiling Y\n");
11117                 return -EINVAL;
11118         }
11119
11120         if (mode_cmd->pitches[0] & 63) {
11121                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11122                           mode_cmd->pitches[0]);
11123                 return -EINVAL;
11124         }
11125
11126         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11127                 pitch_limit = 32*1024;
11128         } else if (INTEL_INFO(dev)->gen >= 4) {
11129                 if (obj->tiling_mode)
11130                         pitch_limit = 16*1024;
11131                 else
11132                         pitch_limit = 32*1024;
11133         } else if (INTEL_INFO(dev)->gen >= 3) {
11134                 if (obj->tiling_mode)
11135                         pitch_limit = 8*1024;
11136                 else
11137                         pitch_limit = 16*1024;
11138         } else
11139                 /* XXX DSPC is limited to 4k tiled */
11140                 pitch_limit = 8*1024;
11141
11142         if (mode_cmd->pitches[0] > pitch_limit) {
11143                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11144                           obj->tiling_mode ? "tiled" : "linear",
11145                           mode_cmd->pitches[0], pitch_limit);
11146                 return -EINVAL;
11147         }
11148
11149         if (obj->tiling_mode != I915_TILING_NONE &&
11150             mode_cmd->pitches[0] != obj->stride) {
11151                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11152                           mode_cmd->pitches[0], obj->stride);
11153                 return -EINVAL;
11154         }
11155
11156         /* Reject formats not supported by any plane early. */
11157         switch (mode_cmd->pixel_format) {
11158         case DRM_FORMAT_C8:
11159         case DRM_FORMAT_RGB565:
11160         case DRM_FORMAT_XRGB8888:
11161         case DRM_FORMAT_ARGB8888:
11162                 break;
11163         case DRM_FORMAT_XRGB1555:
11164         case DRM_FORMAT_ARGB1555:
11165                 if (INTEL_INFO(dev)->gen > 3) {
11166                         DRM_DEBUG("unsupported pixel format: %s\n",
11167                                   drm_get_format_name(mode_cmd->pixel_format));
11168                         return -EINVAL;
11169                 }
11170                 break;
11171         case DRM_FORMAT_XBGR8888:
11172         case DRM_FORMAT_ABGR8888:
11173         case DRM_FORMAT_XRGB2101010:
11174         case DRM_FORMAT_ARGB2101010:
11175         case DRM_FORMAT_XBGR2101010:
11176         case DRM_FORMAT_ABGR2101010:
11177                 if (INTEL_INFO(dev)->gen < 4) {
11178                         DRM_DEBUG("unsupported pixel format: %s\n",
11179                                   drm_get_format_name(mode_cmd->pixel_format));
11180                         return -EINVAL;
11181                 }
11182                 break;
11183         case DRM_FORMAT_YUYV:
11184         case DRM_FORMAT_UYVY:
11185         case DRM_FORMAT_YVYU:
11186         case DRM_FORMAT_VYUY:
11187                 if (INTEL_INFO(dev)->gen < 5) {
11188                         DRM_DEBUG("unsupported pixel format: %s\n",
11189                                   drm_get_format_name(mode_cmd->pixel_format));
11190                         return -EINVAL;
11191                 }
11192                 break;
11193         default:
11194                 DRM_DEBUG("unsupported pixel format: %s\n",
11195                           drm_get_format_name(mode_cmd->pixel_format));
11196                 return -EINVAL;
11197         }
11198
11199         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11200         if (mode_cmd->offsets[0] != 0)
11201                 return -EINVAL;
11202
11203         aligned_height = intel_align_height(dev, mode_cmd->height,
11204                                             obj->tiling_mode);
11205         /* FIXME drm helper for size checks (especially planar formats)? */
11206         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11207                 return -EINVAL;
11208
11209         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11210         intel_fb->obj = obj;
11211         intel_fb->obj->framebuffer_references++;
11212
11213         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11214         if (ret) {
11215                 DRM_ERROR("framebuffer init failed %d\n", ret);
11216                 return ret;
11217         }
11218
11219         return 0;
11220 }
11221
11222 static struct drm_framebuffer *
11223 intel_user_framebuffer_create(struct drm_device *dev,
11224                               struct drm_file *filp,
11225                               struct drm_mode_fb_cmd2 *mode_cmd)
11226 {
11227         struct drm_i915_gem_object *obj;
11228
11229         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11230                                                 mode_cmd->handles[0]));
11231         if (&obj->base == NULL)
11232                 return ERR_PTR(-ENOENT);
11233
11234         return intel_framebuffer_create(dev, mode_cmd, obj);
11235 }
11236
11237 #ifndef CONFIG_DRM_I915_FBDEV
11238 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11239 {
11240 }
11241 #endif
11242
11243 static const struct drm_mode_config_funcs intel_mode_funcs = {
11244         .fb_create = intel_user_framebuffer_create,
11245         .output_poll_changed = intel_fbdev_output_poll_changed,
11246 };
11247
11248 /* Set up chip specific display functions */
11249 static void intel_init_display(struct drm_device *dev)
11250 {
11251         struct drm_i915_private *dev_priv = dev->dev_private;
11252
11253         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11254                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11255         else if (IS_CHERRYVIEW(dev))
11256                 dev_priv->display.find_dpll = chv_find_best_dpll;
11257         else if (IS_VALLEYVIEW(dev))
11258                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11259         else if (IS_PINEVIEW(dev))
11260                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11261         else
11262                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11263
11264         if (HAS_DDI(dev)) {
11265                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11266                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11267                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11268                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11269                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11270                 dev_priv->display.off = haswell_crtc_off;
11271                 dev_priv->display.update_primary_plane =
11272                         ironlake_update_primary_plane;
11273         } else if (HAS_PCH_SPLIT(dev)) {
11274                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11275                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11276                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11277                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11278                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11279                 dev_priv->display.off = ironlake_crtc_off;
11280                 dev_priv->display.update_primary_plane =
11281                         ironlake_update_primary_plane;
11282         } else if (IS_VALLEYVIEW(dev)) {
11283                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11284                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11285                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11286                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11287                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11288                 dev_priv->display.off = i9xx_crtc_off;
11289                 dev_priv->display.update_primary_plane =
11290                         i9xx_update_primary_plane;
11291         } else {
11292                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11293                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11294                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11295                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11296                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11297                 dev_priv->display.off = i9xx_crtc_off;
11298                 dev_priv->display.update_primary_plane =
11299                         i9xx_update_primary_plane;
11300         }
11301
11302         /* Returns the core display clock speed */
11303         if (IS_VALLEYVIEW(dev))
11304                 dev_priv->display.get_display_clock_speed =
11305                         valleyview_get_display_clock_speed;
11306         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11307                 dev_priv->display.get_display_clock_speed =
11308                         i945_get_display_clock_speed;
11309         else if (IS_I915G(dev))
11310                 dev_priv->display.get_display_clock_speed =
11311                         i915_get_display_clock_speed;
11312         else if (IS_I945GM(dev) || IS_845G(dev))
11313                 dev_priv->display.get_display_clock_speed =
11314                         i9xx_misc_get_display_clock_speed;
11315         else if (IS_PINEVIEW(dev))
11316                 dev_priv->display.get_display_clock_speed =
11317                         pnv_get_display_clock_speed;
11318         else if (IS_I915GM(dev))
11319                 dev_priv->display.get_display_clock_speed =
11320                         i915gm_get_display_clock_speed;
11321         else if (IS_I865G(dev))
11322                 dev_priv->display.get_display_clock_speed =
11323                         i865_get_display_clock_speed;
11324         else if (IS_I85X(dev))
11325                 dev_priv->display.get_display_clock_speed =
11326                         i855_get_display_clock_speed;
11327         else /* 852, 830 */
11328                 dev_priv->display.get_display_clock_speed =
11329                         i830_get_display_clock_speed;
11330
11331         if (HAS_PCH_SPLIT(dev)) {
11332                 if (IS_GEN5(dev)) {
11333                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11334                         dev_priv->display.write_eld = ironlake_write_eld;
11335                 } else if (IS_GEN6(dev)) {
11336                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11337                         dev_priv->display.write_eld = ironlake_write_eld;
11338                         dev_priv->display.modeset_global_resources =
11339                                 snb_modeset_global_resources;
11340                 } else if (IS_IVYBRIDGE(dev)) {
11341                         /* FIXME: detect B0+ stepping and use auto training */
11342                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11343                         dev_priv->display.write_eld = ironlake_write_eld;
11344                         dev_priv->display.modeset_global_resources =
11345                                 ivb_modeset_global_resources;
11346                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11347                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11348                         dev_priv->display.write_eld = haswell_write_eld;
11349                         dev_priv->display.modeset_global_resources =
11350                                 haswell_modeset_global_resources;
11351                 }
11352         } else if (IS_G4X(dev)) {
11353                 dev_priv->display.write_eld = g4x_write_eld;
11354         } else if (IS_VALLEYVIEW(dev)) {
11355                 dev_priv->display.modeset_global_resources =
11356                         valleyview_modeset_global_resources;
11357                 dev_priv->display.write_eld = ironlake_write_eld;
11358         }
11359
11360         /* Default just returns -ENODEV to indicate unsupported */
11361         dev_priv->display.queue_flip = intel_default_queue_flip;
11362
11363         switch (INTEL_INFO(dev)->gen) {
11364         case 2:
11365                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11366                 break;
11367
11368         case 3:
11369                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11370                 break;
11371
11372         case 4:
11373         case 5:
11374                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11375                 break;
11376
11377         case 6:
11378                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11379                 break;
11380         case 7:
11381         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11382                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11383                 break;
11384         }
11385
11386         intel_panel_init_backlight_funcs(dev);
11387 }
11388
11389 /*
11390  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11391  * resume, or other times.  This quirk makes sure that's the case for
11392  * affected systems.
11393  */
11394 static void quirk_pipea_force(struct drm_device *dev)
11395 {
11396         struct drm_i915_private *dev_priv = dev->dev_private;
11397
11398         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11399         DRM_INFO("applying pipe a force quirk\n");
11400 }
11401
11402 /*
11403  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11404  */
11405 static void quirk_ssc_force_disable(struct drm_device *dev)
11406 {
11407         struct drm_i915_private *dev_priv = dev->dev_private;
11408         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11409         DRM_INFO("applying lvds SSC disable quirk\n");
11410 }
11411
11412 /*
11413  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11414  * brightness value
11415  */
11416 static void quirk_invert_brightness(struct drm_device *dev)
11417 {
11418         struct drm_i915_private *dev_priv = dev->dev_private;
11419         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11420         DRM_INFO("applying inverted panel brightness quirk\n");
11421 }
11422
11423 struct intel_quirk {
11424         int device;
11425         int subsystem_vendor;
11426         int subsystem_device;
11427         void (*hook)(struct drm_device *dev);
11428 };
11429
11430 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11431 struct intel_dmi_quirk {
11432         void (*hook)(struct drm_device *dev);
11433         const struct dmi_system_id (*dmi_id_list)[];
11434 };
11435
11436 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11437 {
11438         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11439         return 1;
11440 }
11441
11442 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11443         {
11444                 .dmi_id_list = &(const struct dmi_system_id[]) {
11445                         {
11446                                 .callback = intel_dmi_reverse_brightness,
11447                                 .ident = "NCR Corporation",
11448                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11449                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11450                                 },
11451                         },
11452                         { }  /* terminating entry */
11453                 },
11454                 .hook = quirk_invert_brightness,
11455         },
11456 };
11457
11458 static struct intel_quirk intel_quirks[] = {
11459         /* HP Mini needs pipe A force quirk (LP: #322104) */
11460         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11461
11462         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11463         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11464
11465         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11466         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11467
11468         /* 830 needs to leave pipe A & dpll A up */
11469         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11470
11471         /* Lenovo U160 cannot use SSC on LVDS */
11472         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11473
11474         /* Sony Vaio Y cannot use SSC on LVDS */
11475         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11476
11477         /* Acer Aspire 5734Z must invert backlight brightness */
11478         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11479
11480         /* Acer/eMachines G725 */
11481         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11482
11483         /* Acer/eMachines e725 */
11484         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11485
11486         /* Acer/Packard Bell NCL20 */
11487         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11488
11489         /* Acer Aspire 4736Z */
11490         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11491
11492         /* Acer Aspire 5336 */
11493         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11494 };
11495
11496 static void intel_init_quirks(struct drm_device *dev)
11497 {
11498         struct pci_dev *d = dev->pdev;
11499         int i;
11500
11501         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11502                 struct intel_quirk *q = &intel_quirks[i];
11503
11504                 if (d->device == q->device &&
11505                     (d->subsystem_vendor == q->subsystem_vendor ||
11506                      q->subsystem_vendor == PCI_ANY_ID) &&
11507                     (d->subsystem_device == q->subsystem_device ||
11508                      q->subsystem_device == PCI_ANY_ID))
11509                         q->hook(dev);
11510         }
11511         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11512                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11513                         intel_dmi_quirks[i].hook(dev);
11514         }
11515 }
11516
11517 /* Disable the VGA plane that we never use */
11518 static void i915_disable_vga(struct drm_device *dev)
11519 {
11520         struct drm_i915_private *dev_priv = dev->dev_private;
11521         u8 sr1;
11522         u32 vga_reg = i915_vgacntrl_reg(dev);
11523
11524         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11525         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11526         outb(SR01, VGA_SR_INDEX);
11527         sr1 = inb(VGA_SR_DATA);
11528         outb(sr1 | 1<<5, VGA_SR_DATA);
11529         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11530         udelay(300);
11531
11532         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11533         POSTING_READ(vga_reg);
11534 }
11535
11536 void intel_modeset_init_hw(struct drm_device *dev)
11537 {
11538         intel_prepare_ddi(dev);
11539
11540         intel_init_clock_gating(dev);
11541
11542         intel_reset_dpio(dev);
11543
11544         intel_enable_gt_powersave(dev);
11545 }
11546
11547 void intel_modeset_suspend_hw(struct drm_device *dev)
11548 {
11549         intel_suspend_hw(dev);
11550 }
11551
11552 void intel_modeset_init(struct drm_device *dev)
11553 {
11554         struct drm_i915_private *dev_priv = dev->dev_private;
11555         int sprite, ret;
11556         enum pipe pipe;
11557         struct intel_crtc *crtc;
11558
11559         drm_mode_config_init(dev);
11560
11561         dev->mode_config.min_width = 0;
11562         dev->mode_config.min_height = 0;
11563
11564         dev->mode_config.preferred_depth = 24;
11565         dev->mode_config.prefer_shadow = 1;
11566
11567         dev->mode_config.funcs = &intel_mode_funcs;
11568
11569         intel_init_quirks(dev);
11570
11571         intel_init_pm(dev);
11572
11573         if (INTEL_INFO(dev)->num_pipes == 0)
11574                 return;
11575
11576         intel_init_display(dev);
11577
11578         if (IS_GEN2(dev)) {
11579                 dev->mode_config.max_width = 2048;
11580                 dev->mode_config.max_height = 2048;
11581         } else if (IS_GEN3(dev)) {
11582                 dev->mode_config.max_width = 4096;
11583                 dev->mode_config.max_height = 4096;
11584         } else {
11585                 dev->mode_config.max_width = 8192;
11586                 dev->mode_config.max_height = 8192;
11587         }
11588
11589         if (IS_GEN2(dev)) {
11590                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11591                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11592         } else {
11593                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11594                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11595         }
11596
11597         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11598
11599         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11600                       INTEL_INFO(dev)->num_pipes,
11601                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11602
11603         for_each_pipe(pipe) {
11604                 intel_crtc_init(dev, pipe);
11605                 for_each_sprite(pipe, sprite) {
11606                         ret = intel_plane_init(dev, pipe, sprite);
11607                         if (ret)
11608                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11609                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11610                 }
11611         }
11612
11613         intel_init_dpio(dev);
11614         intel_reset_dpio(dev);
11615
11616         intel_cpu_pll_init(dev);
11617         intel_shared_dpll_init(dev);
11618
11619         /* Just disable it once at startup */
11620         i915_disable_vga(dev);
11621         intel_setup_outputs(dev);
11622
11623         /* Just in case the BIOS is doing something questionable. */
11624         intel_disable_fbc(dev);
11625
11626         mutex_lock(&dev->mode_config.mutex);
11627         intel_modeset_setup_hw_state(dev, false);
11628         mutex_unlock(&dev->mode_config.mutex);
11629
11630         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11631                             base.head) {
11632                 if (!crtc->active)
11633                         continue;
11634
11635                 /*
11636                  * Note that reserving the BIOS fb up front prevents us
11637                  * from stuffing other stolen allocations like the ring
11638                  * on top.  This prevents some ugliness at boot time, and
11639                  * can even allow for smooth boot transitions if the BIOS
11640                  * fb is large enough for the active pipe configuration.
11641                  */
11642                 if (dev_priv->display.get_plane_config) {
11643                         dev_priv->display.get_plane_config(crtc,
11644                                                            &crtc->plane_config);
11645                         /*
11646                          * If the fb is shared between multiple heads, we'll
11647                          * just get the first one.
11648                          */
11649                         intel_find_plane_obj(crtc, &crtc->plane_config);
11650                 }
11651         }
11652 }
11653
11654 static void
11655 intel_connector_break_all_links(struct intel_connector *connector)
11656 {
11657         connector->base.dpms = DRM_MODE_DPMS_OFF;
11658         connector->base.encoder = NULL;
11659         connector->encoder->connectors_active = false;
11660         connector->encoder->base.crtc = NULL;
11661 }
11662
11663 static void intel_enable_pipe_a(struct drm_device *dev)
11664 {
11665         struct intel_connector *connector;
11666         struct drm_connector *crt = NULL;
11667         struct intel_load_detect_pipe load_detect_temp;
11668
11669         /* We can't just switch on the pipe A, we need to set things up with a
11670          * proper mode and output configuration. As a gross hack, enable pipe A
11671          * by enabling the load detect pipe once. */
11672         list_for_each_entry(connector,
11673                             &dev->mode_config.connector_list,
11674                             base.head) {
11675                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11676                         crt = &connector->base;
11677                         break;
11678                 }
11679         }
11680
11681         if (!crt)
11682                 return;
11683
11684         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11685                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11686
11687
11688 }
11689
11690 static bool
11691 intel_check_plane_mapping(struct intel_crtc *crtc)
11692 {
11693         struct drm_device *dev = crtc->base.dev;
11694         struct drm_i915_private *dev_priv = dev->dev_private;
11695         u32 reg, val;
11696
11697         if (INTEL_INFO(dev)->num_pipes == 1)
11698                 return true;
11699
11700         reg = DSPCNTR(!crtc->plane);
11701         val = I915_READ(reg);
11702
11703         if ((val & DISPLAY_PLANE_ENABLE) &&
11704             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11705                 return false;
11706
11707         return true;
11708 }
11709
11710 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11711 {
11712         struct drm_device *dev = crtc->base.dev;
11713         struct drm_i915_private *dev_priv = dev->dev_private;
11714         u32 reg;
11715
11716         /* Clear any frame start delays used for debugging left by the BIOS */
11717         reg = PIPECONF(crtc->config.cpu_transcoder);
11718         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11719
11720         /* We need to sanitize the plane -> pipe mapping first because this will
11721          * disable the crtc (and hence change the state) if it is wrong. Note
11722          * that gen4+ has a fixed plane -> pipe mapping.  */
11723         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11724                 struct intel_connector *connector;
11725                 bool plane;
11726
11727                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11728                               crtc->base.base.id);
11729
11730                 /* Pipe has the wrong plane attached and the plane is active.
11731                  * Temporarily change the plane mapping and disable everything
11732                  * ...  */
11733                 plane = crtc->plane;
11734                 crtc->plane = !plane;
11735                 dev_priv->display.crtc_disable(&crtc->base);
11736                 crtc->plane = plane;
11737
11738                 /* ... and break all links. */
11739                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11740                                     base.head) {
11741                         if (connector->encoder->base.crtc != &crtc->base)
11742                                 continue;
11743
11744                         intel_connector_break_all_links(connector);
11745                 }
11746
11747                 WARN_ON(crtc->active);
11748                 crtc->base.enabled = false;
11749         }
11750
11751         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11752             crtc->pipe == PIPE_A && !crtc->active) {
11753                 /* BIOS forgot to enable pipe A, this mostly happens after
11754                  * resume. Force-enable the pipe to fix this, the update_dpms
11755                  * call below we restore the pipe to the right state, but leave
11756                  * the required bits on. */
11757                 intel_enable_pipe_a(dev);
11758         }
11759
11760         /* Adjust the state of the output pipe according to whether we
11761          * have active connectors/encoders. */
11762         intel_crtc_update_dpms(&crtc->base);
11763
11764         if (crtc->active != crtc->base.enabled) {
11765                 struct intel_encoder *encoder;
11766
11767                 /* This can happen either due to bugs in the get_hw_state
11768                  * functions or because the pipe is force-enabled due to the
11769                  * pipe A quirk. */
11770                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11771                               crtc->base.base.id,
11772                               crtc->base.enabled ? "enabled" : "disabled",
11773                               crtc->active ? "enabled" : "disabled");
11774
11775                 crtc->base.enabled = crtc->active;
11776
11777                 /* Because we only establish the connector -> encoder ->
11778                  * crtc links if something is active, this means the
11779                  * crtc is now deactivated. Break the links. connector
11780                  * -> encoder links are only establish when things are
11781                  *  actually up, hence no need to break them. */
11782                 WARN_ON(crtc->active);
11783
11784                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11785                         WARN_ON(encoder->connectors_active);
11786                         encoder->base.crtc = NULL;
11787                 }
11788         }
11789         if (crtc->active) {
11790                 /*
11791                  * We start out with underrun reporting disabled to avoid races.
11792                  * For correct bookkeeping mark this on active crtcs.
11793                  *
11794                  * No protection against concurrent access is required - at
11795                  * worst a fifo underrun happens which also sets this to false.
11796                  */
11797                 crtc->cpu_fifo_underrun_disabled = true;
11798                 crtc->pch_fifo_underrun_disabled = true;
11799         }
11800 }
11801
11802 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11803 {
11804         struct intel_connector *connector;
11805         struct drm_device *dev = encoder->base.dev;
11806
11807         /* We need to check both for a crtc link (meaning that the
11808          * encoder is active and trying to read from a pipe) and the
11809          * pipe itself being active. */
11810         bool has_active_crtc = encoder->base.crtc &&
11811                 to_intel_crtc(encoder->base.crtc)->active;
11812
11813         if (encoder->connectors_active && !has_active_crtc) {
11814                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11815                               encoder->base.base.id,
11816                               drm_get_encoder_name(&encoder->base));
11817
11818                 /* Connector is active, but has no active pipe. This is
11819                  * fallout from our resume register restoring. Disable
11820                  * the encoder manually again. */
11821                 if (encoder->base.crtc) {
11822                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11823                                       encoder->base.base.id,
11824                                       drm_get_encoder_name(&encoder->base));
11825                         encoder->disable(encoder);
11826                 }
11827
11828                 /* Inconsistent output/port/pipe state happens presumably due to
11829                  * a bug in one of the get_hw_state functions. Or someplace else
11830                  * in our code, like the register restore mess on resume. Clamp
11831                  * things to off as a safer default. */
11832                 list_for_each_entry(connector,
11833                                     &dev->mode_config.connector_list,
11834                                     base.head) {
11835                         if (connector->encoder != encoder)
11836                                 continue;
11837
11838                         intel_connector_break_all_links(connector);
11839                 }
11840         }
11841         /* Enabled encoders without active connectors will be fixed in
11842          * the crtc fixup. */
11843 }
11844
11845 void i915_redisable_vga_power_on(struct drm_device *dev)
11846 {
11847         struct drm_i915_private *dev_priv = dev->dev_private;
11848         u32 vga_reg = i915_vgacntrl_reg(dev);
11849
11850         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11851                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11852                 i915_disable_vga(dev);
11853         }
11854 }
11855
11856 void i915_redisable_vga(struct drm_device *dev)
11857 {
11858         struct drm_i915_private *dev_priv = dev->dev_private;
11859
11860         /* This function can be called both from intel_modeset_setup_hw_state or
11861          * at a very early point in our resume sequence, where the power well
11862          * structures are not yet restored. Since this function is at a very
11863          * paranoid "someone might have enabled VGA while we were not looking"
11864          * level, just check if the power well is enabled instead of trying to
11865          * follow the "don't touch the power well if we don't need it" policy
11866          * the rest of the driver uses. */
11867         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11868                 return;
11869
11870         i915_redisable_vga_power_on(dev);
11871 }
11872
11873 static bool primary_get_hw_state(struct intel_crtc *crtc)
11874 {
11875         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11876
11877         if (!crtc->active)
11878                 return false;
11879
11880         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11881 }
11882
11883 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11884 {
11885         struct drm_i915_private *dev_priv = dev->dev_private;
11886         enum pipe pipe;
11887         struct intel_crtc *crtc;
11888         struct intel_encoder *encoder;
11889         struct intel_connector *connector;
11890         int i;
11891
11892         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11893                             base.head) {
11894                 memset(&crtc->config, 0, sizeof(crtc->config));
11895
11896                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11897
11898                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11899                                                                  &crtc->config);
11900
11901                 crtc->base.enabled = crtc->active;
11902                 crtc->primary_enabled = primary_get_hw_state(crtc);
11903
11904                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11905                               crtc->base.base.id,
11906                               crtc->active ? "enabled" : "disabled");
11907         }
11908
11909         /* FIXME: Smash this into the new shared dpll infrastructure. */
11910         if (HAS_DDI(dev))
11911                 intel_ddi_setup_hw_pll_state(dev);
11912
11913         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11914                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11915
11916                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11917                 pll->active = 0;
11918                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11919                                     base.head) {
11920                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11921                                 pll->active++;
11922                 }
11923                 pll->refcount = pll->active;
11924
11925                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11926                               pll->name, pll->refcount, pll->on);
11927         }
11928
11929         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11930                             base.head) {
11931                 pipe = 0;
11932
11933                 if (encoder->get_hw_state(encoder, &pipe)) {
11934                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11935                         encoder->base.crtc = &crtc->base;
11936                         encoder->get_config(encoder, &crtc->config);
11937                 } else {
11938                         encoder->base.crtc = NULL;
11939                 }
11940
11941                 encoder->connectors_active = false;
11942                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11943                               encoder->base.base.id,
11944                               drm_get_encoder_name(&encoder->base),
11945                               encoder->base.crtc ? "enabled" : "disabled",
11946                               pipe_name(pipe));
11947         }
11948
11949         list_for_each_entry(connector, &dev->mode_config.connector_list,
11950                             base.head) {
11951                 if (connector->get_hw_state(connector)) {
11952                         connector->base.dpms = DRM_MODE_DPMS_ON;
11953                         connector->encoder->connectors_active = true;
11954                         connector->base.encoder = &connector->encoder->base;
11955                 } else {
11956                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11957                         connector->base.encoder = NULL;
11958                 }
11959                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11960                               connector->base.base.id,
11961                               drm_get_connector_name(&connector->base),
11962                               connector->base.encoder ? "enabled" : "disabled");
11963         }
11964 }
11965
11966 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11967  * and i915 state tracking structures. */
11968 void intel_modeset_setup_hw_state(struct drm_device *dev,
11969                                   bool force_restore)
11970 {
11971         struct drm_i915_private *dev_priv = dev->dev_private;
11972         enum pipe pipe;
11973         struct intel_crtc *crtc;
11974         struct intel_encoder *encoder;
11975         int i;
11976
11977         intel_modeset_readout_hw_state(dev);
11978
11979         /*
11980          * Now that we have the config, copy it to each CRTC struct
11981          * Note that this could go away if we move to using crtc_config
11982          * checking everywhere.
11983          */
11984         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11985                             base.head) {
11986                 if (crtc->active && i915.fastboot) {
11987                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11988                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11989                                       crtc->base.base.id);
11990                         drm_mode_debug_printmodeline(&crtc->base.mode);
11991                 }
11992         }
11993
11994         /* HW state is read out, now we need to sanitize this mess. */
11995         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11996                             base.head) {
11997                 intel_sanitize_encoder(encoder);
11998         }
11999
12000         for_each_pipe(pipe) {
12001                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12002                 intel_sanitize_crtc(crtc);
12003                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12004         }
12005
12006         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12007                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12008
12009                 if (!pll->on || pll->active)
12010                         continue;
12011
12012                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12013
12014                 pll->disable(dev_priv, pll);
12015                 pll->on = false;
12016         }
12017
12018         if (HAS_PCH_SPLIT(dev))
12019                 ilk_wm_get_hw_state(dev);
12020
12021         if (force_restore) {
12022                 i915_redisable_vga(dev);
12023
12024                 /*
12025                  * We need to use raw interfaces for restoring state to avoid
12026                  * checking (bogus) intermediate states.
12027                  */
12028                 for_each_pipe(pipe) {
12029                         struct drm_crtc *crtc =
12030                                 dev_priv->pipe_to_crtc_mapping[pipe];
12031
12032                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12033                                          crtc->primary->fb);
12034                 }
12035         } else {
12036                 intel_modeset_update_staged_output_state(dev);
12037         }
12038
12039         intel_modeset_check_state(dev);
12040 }
12041
12042 void intel_modeset_gem_init(struct drm_device *dev)
12043 {
12044         struct drm_crtc *c;
12045         struct intel_framebuffer *fb;
12046
12047         mutex_lock(&dev->struct_mutex);
12048         intel_init_gt_powersave(dev);
12049         mutex_unlock(&dev->struct_mutex);
12050
12051         intel_modeset_init_hw(dev);
12052
12053         intel_setup_overlay(dev);
12054
12055         /*
12056          * Make sure any fbs we allocated at startup are properly
12057          * pinned & fenced.  When we do the allocation it's too early
12058          * for this.
12059          */
12060         mutex_lock(&dev->struct_mutex);
12061         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
12062                 if (!c->primary->fb)
12063                         continue;
12064
12065                 fb = to_intel_framebuffer(c->primary->fb);
12066                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12067                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12068                                   to_intel_crtc(c)->pipe);
12069                         drm_framebuffer_unreference(c->primary->fb);
12070                         c->primary->fb = NULL;
12071                 }
12072         }
12073         mutex_unlock(&dev->struct_mutex);
12074 }
12075
12076 void intel_connector_unregister(struct intel_connector *intel_connector)
12077 {
12078         struct drm_connector *connector = &intel_connector->base;
12079
12080         intel_panel_destroy_backlight(connector);
12081         drm_sysfs_connector_remove(connector);
12082 }
12083
12084 void intel_modeset_cleanup(struct drm_device *dev)
12085 {
12086         struct drm_i915_private *dev_priv = dev->dev_private;
12087         struct drm_crtc *crtc;
12088         struct drm_connector *connector;
12089
12090         /*
12091          * Interrupts and polling as the first thing to avoid creating havoc.
12092          * Too much stuff here (turning of rps, connectors, ...) would
12093          * experience fancy races otherwise.
12094          */
12095         drm_irq_uninstall(dev);
12096         cancel_work_sync(&dev_priv->hotplug_work);
12097         /*
12098          * Due to the hpd irq storm handling the hotplug work can re-arm the
12099          * poll handlers. Hence disable polling after hpd handling is shut down.
12100          */
12101         drm_kms_helper_poll_fini(dev);
12102
12103         mutex_lock(&dev->struct_mutex);
12104
12105         intel_unregister_dsm_handler();
12106
12107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
12108                 /* Skip inactive CRTCs */
12109                 if (!crtc->primary->fb)
12110                         continue;
12111
12112                 intel_increase_pllclock(crtc);
12113         }
12114
12115         intel_disable_fbc(dev);
12116
12117         intel_disable_gt_powersave(dev);
12118
12119         ironlake_teardown_rc6(dev);
12120
12121         mutex_unlock(&dev->struct_mutex);
12122
12123         /* flush any delayed tasks or pending work */
12124         flush_scheduled_work();
12125
12126         /* destroy the backlight and sysfs files before encoders/connectors */
12127         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12128                 struct intel_connector *intel_connector;
12129
12130                 intel_connector = to_intel_connector(connector);
12131                 intel_connector->unregister(intel_connector);
12132         }
12133
12134         drm_mode_config_cleanup(dev);
12135
12136         intel_cleanup_overlay(dev);
12137
12138         mutex_lock(&dev->struct_mutex);
12139         intel_cleanup_gt_powersave(dev);
12140         mutex_unlock(&dev->struct_mutex);
12141 }
12142
12143 /*
12144  * Return which encoder is currently attached for connector.
12145  */
12146 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12147 {
12148         return &intel_attached_encoder(connector)->base;
12149 }
12150
12151 void intel_connector_attach_encoder(struct intel_connector *connector,
12152                                     struct intel_encoder *encoder)
12153 {
12154         connector->encoder = encoder;
12155         drm_mode_connector_attach_encoder(&connector->base,
12156                                           &encoder->base);
12157 }
12158
12159 /*
12160  * set vga decode state - true == enable VGA decode
12161  */
12162 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12163 {
12164         struct drm_i915_private *dev_priv = dev->dev_private;
12165         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12166         u16 gmch_ctrl;
12167
12168         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12169                 DRM_ERROR("failed to read control word\n");
12170                 return -EIO;
12171         }
12172
12173         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12174                 return 0;
12175
12176         if (state)
12177                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12178         else
12179                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12180
12181         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12182                 DRM_ERROR("failed to write control word\n");
12183                 return -EIO;
12184         }
12185
12186         return 0;
12187 }
12188
12189 struct intel_display_error_state {
12190
12191         u32 power_well_driver;
12192
12193         int num_transcoders;
12194
12195         struct intel_cursor_error_state {
12196                 u32 control;
12197                 u32 position;
12198                 u32 base;
12199                 u32 size;
12200         } cursor[I915_MAX_PIPES];
12201
12202         struct intel_pipe_error_state {
12203                 bool power_domain_on;
12204                 u32 source;
12205                 u32 stat;
12206         } pipe[I915_MAX_PIPES];
12207
12208         struct intel_plane_error_state {
12209                 u32 control;
12210                 u32 stride;
12211                 u32 size;
12212                 u32 pos;
12213                 u32 addr;
12214                 u32 surface;
12215                 u32 tile_offset;
12216         } plane[I915_MAX_PIPES];
12217
12218         struct intel_transcoder_error_state {
12219                 bool power_domain_on;
12220                 enum transcoder cpu_transcoder;
12221
12222                 u32 conf;
12223
12224                 u32 htotal;
12225                 u32 hblank;
12226                 u32 hsync;
12227                 u32 vtotal;
12228                 u32 vblank;
12229                 u32 vsync;
12230         } transcoder[4];
12231 };
12232
12233 struct intel_display_error_state *
12234 intel_display_capture_error_state(struct drm_device *dev)
12235 {
12236         struct drm_i915_private *dev_priv = dev->dev_private;
12237         struct intel_display_error_state *error;
12238         int transcoders[] = {
12239                 TRANSCODER_A,
12240                 TRANSCODER_B,
12241                 TRANSCODER_C,
12242                 TRANSCODER_EDP,
12243         };
12244         int i;
12245
12246         if (INTEL_INFO(dev)->num_pipes == 0)
12247                 return NULL;
12248
12249         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12250         if (error == NULL)
12251                 return NULL;
12252
12253         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12254                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12255
12256         for_each_pipe(i) {
12257                 error->pipe[i].power_domain_on =
12258                         intel_display_power_enabled_sw(dev_priv,
12259                                                        POWER_DOMAIN_PIPE(i));
12260                 if (!error->pipe[i].power_domain_on)
12261                         continue;
12262
12263                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12264                         error->cursor[i].control = I915_READ(CURCNTR(i));
12265                         error->cursor[i].position = I915_READ(CURPOS(i));
12266                         error->cursor[i].base = I915_READ(CURBASE(i));
12267                 } else {
12268                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12269                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12270                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12271                 }
12272
12273                 error->plane[i].control = I915_READ(DSPCNTR(i));
12274                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12275                 if (INTEL_INFO(dev)->gen <= 3) {
12276                         error->plane[i].size = I915_READ(DSPSIZE(i));
12277                         error->plane[i].pos = I915_READ(DSPPOS(i));
12278                 }
12279                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12280                         error->plane[i].addr = I915_READ(DSPADDR(i));
12281                 if (INTEL_INFO(dev)->gen >= 4) {
12282                         error->plane[i].surface = I915_READ(DSPSURF(i));
12283                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12284                 }
12285
12286                 error->pipe[i].source = I915_READ(PIPESRC(i));
12287
12288                 if (!HAS_PCH_SPLIT(dev))
12289                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12290         }
12291
12292         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12293         if (HAS_DDI(dev_priv->dev))
12294                 error->num_transcoders++; /* Account for eDP. */
12295
12296         for (i = 0; i < error->num_transcoders; i++) {
12297                 enum transcoder cpu_transcoder = transcoders[i];
12298
12299                 error->transcoder[i].power_domain_on =
12300                         intel_display_power_enabled_sw(dev_priv,
12301                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12302                 if (!error->transcoder[i].power_domain_on)
12303                         continue;
12304
12305                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12306
12307                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12308                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12309                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12310                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12311                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12312                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12313                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12314         }
12315
12316         return error;
12317 }
12318
12319 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12320
12321 void
12322 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12323                                 struct drm_device *dev,
12324                                 struct intel_display_error_state *error)
12325 {
12326         int i;
12327
12328         if (!error)
12329                 return;
12330
12331         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12332         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12333                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12334                            error->power_well_driver);
12335         for_each_pipe(i) {
12336                 err_printf(m, "Pipe [%d]:\n", i);
12337                 err_printf(m, "  Power: %s\n",
12338                            error->pipe[i].power_domain_on ? "on" : "off");
12339                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12340                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12341
12342                 err_printf(m, "Plane [%d]:\n", i);
12343                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12344                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12345                 if (INTEL_INFO(dev)->gen <= 3) {
12346                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12347                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12348                 }
12349                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12350                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12351                 if (INTEL_INFO(dev)->gen >= 4) {
12352                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12353                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12354                 }
12355
12356                 err_printf(m, "Cursor [%d]:\n", i);
12357                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12358                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12359                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12360         }
12361
12362         for (i = 0; i < error->num_transcoders; i++) {
12363                 err_printf(m, "CPU transcoder: %c\n",
12364                            transcoder_name(error->transcoder[i].cpu_transcoder));
12365                 err_printf(m, "  Power: %s\n",
12366                            error->transcoder[i].power_domain_on ? "on" : "off");
12367                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12368                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12369                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12370                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12371                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12372                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12373                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12374         }
12375 }