drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_atomic.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_dp_helper.h>
  43 #include <drm/drm_crtc_helper.h>
  44 #include <drm/drm_plane_helper.h>
  45 #include <drm/drm_rect.h>
  46 #include <linux/dma_remapping.h>
  47
  48 /* Primary plane formats for gen <= 3 */
  49 static const uint32_t i8xx_primary_formats[] = {
  50         DRM_FORMAT_C8,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XRGB1555,
  53         DRM_FORMAT_XRGB8888,
  54 };
  55
  56 /* Primary plane formats for gen >= 4 */
  57 static const uint32_t i965_primary_formats[] = {
  58         DRM_FORMAT_C8,
  59         DRM_FORMAT_RGB565,
  60         DRM_FORMAT_XRGB8888,
  61         DRM_FORMAT_XBGR8888,
  62         DRM_FORMAT_XRGB2101010,
  63         DRM_FORMAT_XBGR2101010,
  64 };
  65
  66 static const uint32_t skl_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_ARGB8888,
  72         DRM_FORMAT_ABGR8888,
  73         DRM_FORMAT_XRGB2101010,
  74         DRM_FORMAT_XBGR2101010,
  75 };
  76
  77 /* Cursor formats */
  78 static const uint32_t intel_cursor_formats[] = {
  79         DRM_FORMAT_ARGB8888,
  80 };
  81
  82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  83
  84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  85                                 struct intel_crtc_state *pipe_config);
  86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  87                                    struct intel_crtc_state *pipe_config);
  88
  89 static int intel_framebuffer_init(struct drm_device *dev,
  90                                   struct intel_framebuffer *ifb,
  91                                   struct drm_mode_fb_cmd2 *mode_cmd,
  92                                   struct drm_i915_gem_object *obj);
  93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  96                                          struct intel_link_m_n *m_n,
  97                                          struct intel_link_m_n *m2_n2);
  98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 101 static void vlv_prepare_pll(struct intel_crtc *crtc,
 102                             const struct intel_crtc_state *pipe_config);
 103 static void chv_prepare_pll(struct intel_crtc *crtc,
 104                             const struct intel_crtc_state *pipe_config);
 105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 108         struct intel_crtc_state *crtc_state);
 109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 110                            int num_connectors);
 111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 112
 113 typedef struct {
 114         int     min, max;
 115 } intel_range_t;
 116
 117 typedef struct {
 118         int     dot_limit;
 119         int     p2_slow, p2_fast;
 120 } intel_p2_t;
 121
 122 typedef struct intel_limit intel_limit_t;
 123 struct intel_limit {
 124         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 125         intel_p2_t          p2;
 126 };
 127
 128 int
 129 intel_pch_rawclk(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132
 133         WARN_ON(!HAS_PCH_SPLIT(dev));
 134
 135         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 136 }
 137
 138 static inline u32 /* units of 100MHz */
 139 intel_fdi_link_freq(struct drm_device *dev)
 140 {
 141         if (IS_GEN5(dev)) {
 142                 struct drm_i915_private *dev_priv = dev->dev_private;
 143                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 144         } else
 145                 return 27;
 146 }
 147
 148 static const intel_limit_t intel_limits_i8xx_dac = {
 149         .dot = { .min = 25000, .max = 350000 },
 150         .vco = { .min = 908000, .max = 1512000 },
 151         .n = { .min = 2, .max = 16 },
 152         .m = { .min = 96, .max = 140 },
 153         .m1 = { .min = 18, .max = 26 },
 154         .m2 = { .min = 6, .max = 16 },
 155         .p = { .min = 4, .max = 128 },
 156         .p1 = { .min = 2, .max = 33 },
 157         .p2 = { .dot_limit = 165000,
 158                 .p2_slow = 4, .p2_fast = 2 },
 159 };
 160
 161 static const intel_limit_t intel_limits_i8xx_dvo = {
 162         .dot = { .min = 25000, .max = 350000 },
 163         .vco = { .min = 908000, .max = 1512000 },
 164         .n = { .min = 2, .max = 16 },
 165         .m = { .min = 96, .max = 140 },
 166         .m1 = { .min = 18, .max = 26 },
 167         .m2 = { .min = 6, .max = 16 },
 168         .p = { .min = 4, .max = 128 },
 169         .p1 = { .min = 2, .max = 33 },
 170         .p2 = { .dot_limit = 165000,
 171                 .p2_slow = 4, .p2_fast = 4 },
 172 };
 173
 174 static const intel_limit_t intel_limits_i8xx_lvds = {
 175         .dot = { .min = 25000, .max = 350000 },
 176         .vco = { .min = 908000, .max = 1512000 },
 177         .n = { .min = 2, .max = 16 },
 178         .m = { .min = 96, .max = 140 },
 179         .m1 = { .min = 18, .max = 26 },
 180         .m2 = { .min = 6, .max = 16 },
 181         .p = { .min = 4, .max = 128 },
 182         .p1 = { .min = 1, .max = 6 },
 183         .p2 = { .dot_limit = 165000,
 184                 .p2_slow = 14, .p2_fast = 7 },
 185 };
 186
 187 static const intel_limit_t intel_limits_i9xx_sdvo = {
 188         .dot = { .min = 20000, .max = 400000 },
 189         .vco = { .min = 1400000, .max = 2800000 },
 190         .n = { .min = 1, .max = 6 },
 191         .m = { .min = 70, .max = 120 },
 192         .m1 = { .min = 8, .max = 18 },
 193         .m2 = { .min = 3, .max = 7 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8 },
 196         .p2 = { .dot_limit = 200000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_i9xx_lvds = {
 201         .dot = { .min = 20000, .max = 400000 },
 202         .vco = { .min = 1400000, .max = 2800000 },
 203         .n = { .min = 1, .max = 6 },
 204         .m = { .min = 70, .max = 120 },
 205         .m1 = { .min = 8, .max = 18 },
 206         .m2 = { .min = 3, .max = 7 },
 207         .p = { .min = 7, .max = 98 },
 208         .p1 = { .min = 1, .max = 8 },
 209         .p2 = { .dot_limit = 112000,
 210                 .p2_slow = 14, .p2_fast = 7 },
 211 };
 212
 213
 214 static const intel_limit_t intel_limits_g4x_sdvo = {
 215         .dot = { .min = 25000, .max = 270000 },
 216         .vco = { .min = 1750000, .max = 3500000},
 217         .n = { .min = 1, .max = 4 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 10, .max = 30 },
 222         .p1 = { .min = 1, .max = 3},
 223         .p2 = { .dot_limit = 270000,
 224                 .p2_slow = 10,
 225                 .p2_fast = 10
 226         },
 227 };
 228
 229 static const intel_limit_t intel_limits_g4x_hdmi = {
 230         .dot = { .min = 22000, .max = 400000 },
 231         .vco = { .min = 1750000, .max = 3500000},
 232         .n = { .min = 1, .max = 4 },
 233         .m = { .min = 104, .max = 138 },
 234         .m1 = { .min = 16, .max = 23 },
 235         .m2 = { .min = 5, .max = 11 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8},
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 243         .dot = { .min = 20000, .max = 115000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 14, .p2_fast = 14
 253         },
 254 };
 255
 256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 257         .dot = { .min = 80000, .max = 224000 },
 258         .vco = { .min = 1750000, .max = 3500000 },
 259         .n = { .min = 1, .max = 3 },
 260         .m = { .min = 104, .max = 138 },
 261         .m1 = { .min = 17, .max = 23 },
 262         .m2 = { .min = 5, .max = 11 },
 263         .p = { .min = 14, .max = 42 },
 264         .p1 = { .min = 2, .max = 6 },
 265         .p2 = { .dot_limit = 0,
 266                 .p2_slow = 7, .p2_fast = 7
 267         },
 268 };
 269
 270 static const intel_limit_t intel_limits_pineview_sdvo = {
 271         .dot = { .min = 20000, .max = 400000},
 272         .vco = { .min = 1700000, .max = 3500000 },
 273         /* Pineview's Ncounter is a ring counter */
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         /* Pineview only has one combined m divider, which we treat as m2. */
 277         .m1 = { .min = 0, .max = 0 },
 278         .m2 = { .min = 0, .max = 254 },
 279         .p = { .min = 5, .max = 80 },
 280         .p1 = { .min = 1, .max = 8 },
 281         .p2 = { .dot_limit = 200000,
 282                 .p2_slow = 10, .p2_fast = 5 },
 283 };
 284
 285 static const intel_limit_t intel_limits_pineview_lvds = {
 286         .dot = { .min = 20000, .max = 400000 },
 287         .vco = { .min = 1700000, .max = 3500000 },
 288         .n = { .min = 3, .max = 6 },
 289         .m = { .min = 2, .max = 256 },
 290         .m1 = { .min = 0, .max = 0 },
 291         .m2 = { .min = 0, .max = 254 },
 292         .p = { .min = 7, .max = 112 },
 293         .p1 = { .min = 1, .max = 8 },
 294         .p2 = { .dot_limit = 112000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296 };
 297
 298 /* Ironlake / Sandybridge
 299  *
 300  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 301  * the range value for them is (actual_value - 2).
 302  */
 303 static const intel_limit_t intel_limits_ironlake_dac = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 5 },
 307         .m = { .min = 79, .max = 127 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 5, .max = 80 },
 311         .p1 = { .min = 1, .max = 8 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 10, .p2_fast = 5 },
 314 };
 315
 316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 317         .dot = { .min = 25000, .max = 350000 },
 318         .vco = { .min = 1760000, .max = 3510000 },
 319         .n = { .min = 1, .max = 3 },
 320         .m = { .min = 79, .max = 118 },
 321         .m1 = { .min = 12, .max = 22 },
 322         .m2 = { .min = 5, .max = 9 },
 323         .p = { .min = 28, .max = 112 },
 324         .p1 = { .min = 2, .max = 8 },
 325         .p2 = { .dot_limit = 225000,
 326                 .p2_slow = 14, .p2_fast = 14 },
 327 };
 328
 329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 330         .dot = { .min = 25000, .max = 350000 },
 331         .vco = { .min = 1760000, .max = 3510000 },
 332         .n = { .min = 1, .max = 3 },
 333         .m = { .min = 79, .max = 127 },
 334         .m1 = { .min = 12, .max = 22 },
 335         .m2 = { .min = 5, .max = 9 },
 336         .p = { .min = 14, .max = 56 },
 337         .p1 = { .min = 2, .max = 8 },
 338         .p2 = { .dot_limit = 225000,
 339                 .p2_slow = 7, .p2_fast = 7 },
 340 };
 341
 342 /* LVDS 100mhz refclk limits. */
 343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 344         .dot = { .min = 25000, .max = 350000 },
 345         .vco = { .min = 1760000, .max = 3510000 },
 346         .n = { .min = 1, .max = 2 },
 347         .m = { .min = 79, .max = 126 },
 348         .m1 = { .min = 12, .max = 22 },
 349         .m2 = { .min = 5, .max = 9 },
 350         .p = { .min = 28, .max = 112 },
 351         .p1 = { .min = 2, .max = 8 },
 352         .p2 = { .dot_limit = 225000,
 353                 .p2_slow = 14, .p2_fast = 14 },
 354 };
 355
 356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 357         .dot = { .min = 25000, .max = 350000 },
 358         .vco = { .min = 1760000, .max = 3510000 },
 359         .n = { .min = 1, .max = 3 },
 360         .m = { .min = 79, .max = 126 },
 361         .m1 = { .min = 12, .max = 22 },
 362         .m2 = { .min = 5, .max = 9 },
 363         .p = { .min = 14, .max = 42 },
 364         .p1 = { .min = 2, .max = 6 },
 365         .p2 = { .dot_limit = 225000,
 366                 .p2_slow = 7, .p2_fast = 7 },
 367 };
 368
 369 static const intel_limit_t intel_limits_vlv = {
 370          /*
 371           * These are the data rate limits (measured in fast clocks)
 372           * since those are the strictest limits we have. The fast
 373           * clock and actual rate limits are more relaxed, so checking
 374           * them would make no difference.
 375           */
 376         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m1 = { .min = 2, .max = 3 },
 380         .m2 = { .min = 11, .max = 156 },
 381         .p1 = { .min = 2, .max = 3 },
 382         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 383 };
 384
 385 static const intel_limit_t intel_limits_chv = {
 386         /*
 387          * These are the data rate limits (measured in fast clocks)
 388          * since those are the strictest limits we have.  The fast
 389          * clock and actual rate limits are more relaxed, so checking
 390          * them would make no difference.
 391          */
 392         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 393         .vco = { .min = 4800000, .max = 6480000 },
 394         .n = { .min = 1, .max = 1 },
 395         .m1 = { .min = 2, .max = 2 },
 396         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 397         .p1 = { .min = 2, .max = 4 },
 398         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 399 };
 400
 401 static const intel_limit_t intel_limits_bxt = {
 402         /* FIXME: find real dot limits */
 403         .dot = { .min = 0, .max = INT_MAX },
 404         .vco = { .min = 4800000, .max = 6700000 },
 405         .n = { .min = 1, .max = 1 },
 406         .m1 = { .min = 2, .max = 2 },
 407         /* FIXME: find real m2 limits */
 408         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 409         .p1 = { .min = 2, .max = 4 },
 410         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 411 };
 412
 413 static bool
 414 needs_modeset(struct drm_crtc_state *state)
 415 {
 416         return drm_atomic_crtc_needs_modeset(state);
 417 }
 418
 419 /**
 420  * Returns whether any output on the specified pipe is of the specified type
 421  */
 422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         struct intel_encoder *encoder;
 426
 427         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 428                 if (encoder->type == type)
 429                         return true;
 430
 431         return false;
 432 }
 433
 434 /**
 435  * Returns whether any output on the specified pipe will have the specified
 436  * type after a staged modeset is complete, i.e., the same as
 437  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 438  * encoder->crtc.
 439  */
 440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 441                                       int type)
 442 {
 443         struct drm_atomic_state *state = crtc_state->base.state;
 444         struct drm_connector *connector;
 445         struct drm_connector_state *connector_state;
 446         struct intel_encoder *encoder;
 447         int i, num_connectors = 0;
 448
 449         for_each_connector_in_state(state, connector, connector_state, i) {
 450                 if (connector_state->crtc != crtc_state->base.crtc)
 451                         continue;
 452
 453                 num_connectors++;
 454
 455                 encoder = to_intel_encoder(connector_state->best_encoder);
 456                 if (encoder->type == type)
 457                         return true;
 458         }
 459
 460         WARN_ON(num_connectors == 0);
 461
 462         return false;
 463 }
 464
 465 static const intel_limit_t *
 466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
 467 {
 468         struct drm_device *dev = crtc_state->base.crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 472                 if (intel_is_dual_link_lvds(dev)) {
 473                         if (refclk == 100000)
 474                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 475                         else
 476                                 limit = &intel_limits_ironlake_dual_lvds;
 477                 } else {
 478                         if (refclk == 100000)
 479                                 limit = &intel_limits_ironlake_single_lvds_100m;
 480                         else
 481                                 limit = &intel_limits_ironlake_single_lvds;
 482                 }
 483         } else
 484                 limit = &intel_limits_ironlake_dac;
 485
 486         return limit;
 487 }
 488
 489 static const intel_limit_t *
 490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
 491 {
 492         struct drm_device *dev = crtc_state->base.crtc->dev;
 493         const intel_limit_t *limit;
 494
 495         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 496                 if (intel_is_dual_link_lvds(dev))
 497                         limit = &intel_limits_g4x_dual_channel_lvds;
 498                 else
 499                         limit = &intel_limits_g4x_single_channel_lvds;
 500         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 501                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 502                 limit = &intel_limits_g4x_hdmi;
 503         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 504                 limit = &intel_limits_g4x_sdvo;
 505         } else /* The option is for other outputs */
 506                 limit = &intel_limits_i9xx_sdvo;
 507
 508         return limit;
 509 }
 510
 511 static const intel_limit_t *
 512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
 513 {
 514         struct drm_device *dev = crtc_state->base.crtc->dev;
 515         const intel_limit_t *limit;
 516
 517         if (IS_BROXTON(dev))
 518                 limit = &intel_limits_bxt;
 519         else if (HAS_PCH_SPLIT(dev))
 520                 limit = intel_ironlake_limit(crtc_state, refclk);
 521         else if (IS_G4X(dev)) {
 522                 limit = intel_g4x_limit(crtc_state);
 523         } else if (IS_PINEVIEW(dev)) {
 524                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 525                         limit = &intel_limits_pineview_lvds;
 526                 else
 527                         limit = &intel_limits_pineview_sdvo;
 528         } else if (IS_CHERRYVIEW(dev)) {
 529                 limit = &intel_limits_chv;
 530         } else if (IS_VALLEYVIEW(dev)) {
 531                 limit = &intel_limits_vlv;
 532         } else if (!IS_GEN2(dev)) {
 533                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 534                         limit = &intel_limits_i9xx_lvds;
 535                 else
 536                         limit = &intel_limits_i9xx_sdvo;
 537         } else {
 538                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_i8xx_lvds;
 540                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 541                         limit = &intel_limits_i8xx_dvo;
 542                 else
 543                         limit = &intel_limits_i8xx_dac;
 544         }
 545         return limit;
 546 }
 547
 548 /*
 549  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 550  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 551  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 552  * The helpers' return value is the rate of the clock that is fed to the
 553  * display engine's pipe which can be the above fast dot clock rate or a
 554  * divided-down version of it.
 555  */
 556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
 558 {
 559         clock->m = clock->m2 + 2;
 560         clock->p = clock->p1 * clock->p2;
 561         if (WARN_ON(clock->n == 0 || clock->p == 0))
 562                 return 0;
 563         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 564         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 565
 566         return clock->dot;
 567 }
 568
 569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 570 {
 571         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 572 }
 573
 574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
 575 {
 576         clock->m = i9xx_dpll_compute_m(clock);
 577         clock->p = clock->p1 * clock->p2;
 578         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 579                 return 0;
 580         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 581         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 582
 583         return clock->dot;
 584 }
 585
 586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
 587 {
 588         clock->m = clock->m1 * clock->m2;
 589         clock->p = clock->p1 * clock->p2;
 590         if (WARN_ON(clock->n == 0 || clock->p == 0))
 591                 return 0;
 592         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 593         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 594
 595         return clock->dot / 5;
 596 }
 597
 598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
 599 {
 600         clock->m = clock->m1 * clock->m2;
 601         clock->p = clock->p1 * clock->p2;
 602         if (WARN_ON(clock->n == 0 || clock->p == 0))
 603                 return 0;
 604         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 605                         clock->n << 22);
 606         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 607
 608         return clock->dot / 5;
 609 }
 610
 611 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 612 /**
 613  * Returns whether the given set of divisors are valid for a given refclk with
 614  * the given connectors.
 615  */
 616
 617 static bool intel_PLL_is_valid(struct drm_device *dev,
 618                                const intel_limit_t *limit,
 619                                const intel_clock_t *clock)
 620 {
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 624                 INTELPllInvalid("p1 out of range\n");
 625         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 626                 INTELPllInvalid("m2 out of range\n");
 627         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 628                 INTELPllInvalid("m1 out of range\n");
 629
 630         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 631                 if (clock->m1 <= clock->m2)
 632                         INTELPllInvalid("m1 <= m2\n");
 633
 634         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 635                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 636                         INTELPllInvalid("p out of range\n");
 637                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 638                         INTELPllInvalid("m out of range\n");
 639         }
 640
 641         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 642                 INTELPllInvalid("vco out of range\n");
 643         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 644          * connector, etc., rather than just a single range.
 645          */
 646         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 647                 INTELPllInvalid("dot out of range\n");
 648
 649         return true;
 650 }
 651
 652 static int
 653 i9xx_select_p2_div(const intel_limit_t *limit,
 654                    const struct intel_crtc_state *crtc_state,
 655                    int target)
 656 {
 657         struct drm_device *dev = crtc_state->base.crtc->dev;
 658
 659         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 660                 /*
 661                  * For LVDS just rely on its current settings for dual-channel.
 662                  * We haven't figured out how to reliably set up different
 663                  * single/dual channel state, if we even can.
 664                  */
 665                 if (intel_is_dual_link_lvds(dev))
 666                         return limit->p2.p2_fast;
 667                 else
 668                         return limit->p2.p2_slow;
 669         } else {
 670                 if (target < limit->p2.dot_limit)
 671                         return limit->p2.p2_slow;
 672                 else
 673                         return limit->p2.p2_fast;
 674         }
 675 }
 676
 677 static bool
 678 i9xx_find_best_dpll(const intel_limit_t *limit,
 679                     struct intel_crtc_state *crtc_state,
 680                     int target, int refclk, intel_clock_t *match_clock,
 681                     intel_clock_t *best_clock)
 682 {
 683         struct drm_device *dev = crtc_state->base.crtc->dev;
 684         intel_clock_t clock;
 685         int err = target;
 686
 687         memset(best_clock, 0, sizeof(*best_clock));
 688
 689         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 690
 691         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 692              clock.m1++) {
 693                 for (clock.m2 = limit->m2.min;
 694                      clock.m2 <= limit->m2.max; clock.m2++) {
 695                         if (clock.m2 >= clock.m1)
 696                                 break;
 697                         for (clock.n = limit->n.min;
 698                              clock.n <= limit->n.max; clock.n++) {
 699                                 for (clock.p1 = limit->p1.min;
 700                                         clock.p1 <= limit->p1.max; clock.p1++) {
 701                                         int this_err;
 702
 703                                         i9xx_calc_dpll_params(refclk, &clock);
 704                                         if (!intel_PLL_is_valid(dev, limit,
 705                                                                 &clock))
 706                                                 continue;
 707                                         if (match_clock &&
 708                                             clock.p != match_clock->p)
 709                                                 continue;
 710
 711                                         this_err = abs(clock.dot - target);
 712                                         if (this_err < err) {
 713                                                 *best_clock = clock;
 714                                                 err = this_err;
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720
 721         return (err != target);
 722 }
 723
 724 static bool
 725 pnv_find_best_dpll(const intel_limit_t *limit,
 726                    struct intel_crtc_state *crtc_state,
 727                    int target, int refclk, intel_clock_t *match_clock,
 728                    intel_clock_t *best_clock)
 729 {
 730         struct drm_device *dev = crtc_state->base.crtc->dev;
 731         intel_clock_t clock;
 732         int err = target;
 733
 734         memset(best_clock, 0, sizeof(*best_clock));
 735
 736         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 737
 738         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 739              clock.m1++) {
 740                 for (clock.m2 = limit->m2.min;
 741                      clock.m2 <= limit->m2.max; clock.m2++) {
 742                         for (clock.n = limit->n.min;
 743                              clock.n <= limit->n.max; clock.n++) {
 744                                 for (clock.p1 = limit->p1.min;
 745                                         clock.p1 <= limit->p1.max; clock.p1++) {
 746                                         int this_err;
 747
 748                                         pnv_calc_dpll_params(refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err) {
 758                                                 *best_clock = clock;
 759                                                 err = this_err;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return (err != target);
 767 }
 768
 769 static bool
 770 g4x_find_best_dpll(const intel_limit_t *limit,
 771                    struct intel_crtc_state *crtc_state,
 772                    int target, int refclk, intel_clock_t *match_clock,
 773                    intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc_state->base.crtc->dev;
 776         intel_clock_t clock;
 777         int max_n;
 778         bool found = false;
 779         /* approximately equals target * 0.00585 */
 780         int err_most = (target >> 8) + (target >> 9);
 781
 782         memset(best_clock, 0, sizeof(*best_clock));
 783
 784         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 785
 786         max_n = limit->n.max;
 787         /* based on hardware requirement, prefer smaller n to precision */
 788         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 789                 /* based on hardware requirement, prefere larger m1,m2 */
 790                 for (clock.m1 = limit->m1.max;
 791                      clock.m1 >= limit->m1.min; clock.m1--) {
 792                         for (clock.m2 = limit->m2.max;
 793                              clock.m2 >= limit->m2.min; clock.m2--) {
 794                                 for (clock.p1 = limit->p1.max;
 795                                      clock.p1 >= limit->p1.min; clock.p1--) {
 796                                         int this_err;
 797
 798                                         i9xx_calc_dpll_params(refclk, &clock);
 799                                         if (!intel_PLL_is_valid(dev, limit,
 800                                                                 &clock))
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err_most) {
 805                                                 *best_clock = clock;
 806                                                 err_most = this_err;
 807                                                 max_n = clock.n;
 808                                                 found = true;
 809                                         }
 810                                 }
 811                         }
 812                 }
 813         }
 814         return found;
 815 }
 816
 817 /*
 818  * Check if the calculated PLL configuration is more optimal compared to the
 819  * best configuration and error found so far. Return the calculated error.
 820  */
 821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 822                                const intel_clock_t *calculated_clock,
 823                                const intel_clock_t *best_clock,
 824                                unsigned int best_error_ppm,
 825                                unsigned int *error_ppm)
 826 {
 827         /*
 828          * For CHV ignore the error and consider only the P value.
 829          * Prefer a bigger P value based on HW requirements.
 830          */
 831         if (IS_CHERRYVIEW(dev)) {
 832                 *error_ppm = 0;
 833
 834                 return calculated_clock->p > best_clock->p;
 835         }
 836
 837         if (WARN_ON_ONCE(!target_freq))
 838                 return false;
 839
 840         *error_ppm = div_u64(1000000ULL *
 841                                 abs(target_freq - calculated_clock->dot),
 842                              target_freq);
 843         /*
 844          * Prefer a better P value over a better (smaller) error if the error
 845          * is small. Ensure this preference for future configurations too by
 846          * setting the error to 0.
 847          */
 848         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 849                 *error_ppm = 0;
 850
 851                 return true;
 852         }
 853
 854         return *error_ppm + 10 < best_error_ppm;
 855 }
 856
 857 static bool
 858 vlv_find_best_dpll(const intel_limit_t *limit,
 859                    struct intel_crtc_state *crtc_state,
 860                    int target, int refclk, intel_clock_t *match_clock,
 861                    intel_clock_t *best_clock)
 862 {
 863         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 864         struct drm_device *dev = crtc->base.dev;
 865         intel_clock_t clock;
 866         unsigned int bestppm = 1000000;
 867         /* min update 19.2 MHz */
 868         int max_n = min(limit->n.max, refclk / 19200);
 869         bool found = false;
 870
 871         target *= 5; /* fast clock */
 872
 873         memset(best_clock, 0, sizeof(*best_clock));
 874
 875         /* based on hardware requirement, prefer smaller n to precision */
 876         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 877                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 878                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 879                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 880                                 clock.p = clock.p1 * clock.p2;
 881                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 882                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 883                                         unsigned int ppm;
 884
 885                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 886                                                                      refclk * clock.m1);
 887
 888                                         vlv_calc_dpll_params(refclk, &clock);
 889
 890                                         if (!intel_PLL_is_valid(dev, limit,
 891                                                                 &clock))
 892                                                 continue;
 893
 894                                         if (!vlv_PLL_is_optimal(dev, target,
 895                                                                 &clock,
 896                                                                 best_clock,
 897                                                                 bestppm, &ppm))
 898                                                 continue;
 899
 900                                         *best_clock = clock;
 901                                         bestppm = ppm;
 902                                         found = true;
 903                                 }
 904                         }
 905                 }
 906         }
 907
 908         return found;
 909 }
 910
 911 static bool
 912 chv_find_best_dpll(const intel_limit_t *limit,
 913                    struct intel_crtc_state *crtc_state,
 914                    int target, int refclk, intel_clock_t *match_clock,
 915                    intel_clock_t *best_clock)
 916 {
 917         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 918         struct drm_device *dev = crtc->base.dev;
 919         unsigned int best_error_ppm;
 920         intel_clock_t clock;
 921         uint64_t m2;
 922         int found = false;
 923
 924         memset(best_clock, 0, sizeof(*best_clock));
 925         best_error_ppm = 1000000;
 926
 927         /*
 928          * Based on hardware doc, the n always set to 1, and m1 always
 929          * set to 2.  If requires to support 200Mhz refclk, we need to
 930          * revisit this because n may not 1 anymore.
 931          */
 932         clock.n = 1, clock.m1 = 2;
 933         target *= 5;    /* fast clock */
 934
 935         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 936                 for (clock.p2 = limit->p2.p2_fast;
 937                                 clock.p2 >= limit->p2.p2_slow;
 938                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 939                         unsigned int error_ppm;
 940
 941                         clock.p = clock.p1 * clock.p2;
 942
 943                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 944                                         clock.n) << 22, refclk * clock.m1);
 945
 946                         if (m2 > INT_MAX/clock.m1)
 947                                 continue;
 948
 949                         clock.m2 = m2;
 950
 951                         chv_calc_dpll_params(refclk, &clock);
 952
 953                         if (!intel_PLL_is_valid(dev, limit, &clock))
 954                                 continue;
 955
 956                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 957                                                 best_error_ppm, &error_ppm))
 958                                 continue;
 959
 960                         *best_clock = clock;
 961                         best_error_ppm = error_ppm;
 962                         found = true;
 963                 }
 964         }
 965
 966         return found;
 967 }
 968
 969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 970                         intel_clock_t *best_clock)
 971 {
 972         int refclk = i9xx_get_refclk(crtc_state, 0);
 973
 974         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
 975                                   target_clock, refclk, NULL, best_clock);
 976 }
 977
 978 bool intel_crtc_active(struct drm_crtc *crtc)
 979 {
 980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 981
 982         /* Be paranoid as we can arrive here with only partial
 983          * state retrieved from the hardware during setup.
 984          *
 985          * We can ditch the adjusted_mode.crtc_clock check as soon
 986          * as Haswell has gained clock readout/fastboot support.
 987          *
 988          * We can ditch the crtc->primary->fb check as soon as we can
 989          * properly reconstruct framebuffers.
 990          *
 991          * FIXME: The intel_crtc->active here should be switched to
 992          * crtc->state->active once we have proper CRTC states wired up
 993          * for atomic.
 994          */
 995         return intel_crtc->active && crtc->primary->state->fb &&
 996                 intel_crtc->config->base.adjusted_mode.crtc_clock;
 997 }
 998
 999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000                                              enum pipe pipe)
1001 {
1002         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
1005         return intel_crtc->config->cpu_transcoder;
1006 }
1007
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009 {
1010         struct drm_i915_private *dev_priv = dev->dev_private;
1011         u32 reg = PIPEDSL(pipe);
1012         u32 line1, line2;
1013         u32 line_mask;
1014
1015         if (IS_GEN2(dev))
1016                 line_mask = DSL_LINEMASK_GEN2;
1017         else
1018                 line_mask = DSL_LINEMASK_GEN3;
1019
1020         line1 = I915_READ(reg) & line_mask;
1021         msleep(5);
1022         line2 = I915_READ(reg) & line_mask;
1023
1024         return line1 == line2;
1025 }
1026
1027 /*
1028  * intel_wait_for_pipe_off - wait for pipe to turn off
1029  * @crtc: crtc whose pipe to wait for
1030  *
1031  * After disabling a pipe, we can't wait for vblank in the usual way,
1032  * spinning on the vblank interrupt status bit, since we won't actually
1033  * see an interrupt when the pipe is disabled.
1034  *
1035  * On Gen4 and above:
1036  *   wait for the pipe register state bit to turn off
1037  *
1038  * Otherwise:
1039  *   wait for the display line value to settle (it usually
1040  *   ends up stopping at the start of the next frame).
1041  *
1042  */
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1044 {
1045         struct drm_device *dev = crtc->base.dev;
1046         struct drm_i915_private *dev_priv = dev->dev_private;
1047         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048         enum pipe pipe = crtc->pipe;
1049
1050         if (INTEL_INFO(dev)->gen >= 4) {
1051                 int reg = PIPECONF(cpu_transcoder);
1052
1053                 /* Wait for the Pipe State to go off */
1054                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055                              100))
1056                         WARN(1, "pipe_off wait timed out\n");
1057         } else {
1058                 /* Wait for the display line to settle */
1059                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060                         WARN(1, "pipe_off wait timed out\n");
1061         }
1062 }
1063
1064 /*
1065  * ibx_digital_port_connected - is the specified port connected?
1066  * @dev_priv: i915 private structure
1067  * @port: the port to test
1068  *
1069  * Returns true if @port is connected, false otherwise.
1070  */
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072                                 struct intel_digital_port *port)
1073 {
1074         u32 bit;
1075
1076         if (HAS_PCH_IBX(dev_priv->dev)) {
1077                 switch (port->port) {
1078                 case PORT_B:
1079                         bit = SDE_PORTB_HOTPLUG;
1080                         break;
1081                 case PORT_C:
1082                         bit = SDE_PORTC_HOTPLUG;
1083                         break;
1084                 case PORT_D:
1085                         bit = SDE_PORTD_HOTPLUG;
1086                         break;
1087                 default:
1088                         return true;
1089                 }
1090         } else {
1091                 switch (port->port) {
1092                 case PORT_B:
1093                         bit = SDE_PORTB_HOTPLUG_CPT;
1094                         break;
1095                 case PORT_C:
1096                         bit = SDE_PORTC_HOTPLUG_CPT;
1097                         break;
1098                 case PORT_D:
1099                         bit = SDE_PORTD_HOTPLUG_CPT;
1100                         break;
1101                 default:
1102                         return true;
1103                 }
1104         }
1105
1106         return I915_READ(SDEISR) & bit;
1107 }
1108
1109 static const char *state_string(bool enabled)
1110 {
1111         return enabled ? "on" : "off";
1112 }
1113
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116                 enum pipe pipe, bool state)
1117 {
1118         int reg;
1119         u32 val;
1120         bool cur_state;
1121
1122         reg = DPLL(pipe);
1123         val = I915_READ(reg);
1124         cur_state = !!(val & DPLL_VCO_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "PLL state assertion failure (expected %s, current %s)\n",
1127              state_string(state), state_string(cur_state));
1128 }
1129
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132 {
1133         u32 val;
1134         bool cur_state;
1135
1136         mutex_lock(&dev_priv->sb_lock);
1137         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138         mutex_unlock(&dev_priv->sb_lock);
1139
1140         cur_state = val & DSI_PLL_VCO_EN;
1141         I915_STATE_WARN(cur_state != state,
1142              "DSI PLL state assertion failure (expected %s, current %s)\n",
1143              state_string(state), state_string(cur_state));
1144 }
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150 {
1151         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
1153         if (crtc->config->shared_dpll < 0)
1154                 return NULL;
1155
1156         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1157 }
1158
1159 /* For ILK+ */
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161                         struct intel_shared_dpll *pll,
1162                         bool state)
1163 {
1164         bool cur_state;
1165         struct intel_dpll_hw_state hw_state;
1166
1167         if (WARN (!pll,
1168                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1169                 return;
1170
1171         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172         I915_STATE_WARN(cur_state != state,
1173              "%s assertion failure (expected %s, current %s)\n",
1174              pll->name, state_string(state), state_string(cur_state));
1175 }
1176
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178                           enum pipe pipe, bool state)
1179 {
1180         int reg;
1181         u32 val;
1182         bool cur_state;
1183         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184                                                                       pipe);
1185
1186         if (HAS_DDI(dev_priv->dev)) {
1187                 /* DDI does not have a specific FDI_TX register */
1188                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189                 val = I915_READ(reg);
1190                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1191         } else {
1192                 reg = FDI_TX_CTL(pipe);
1193                 val = I915_READ(reg);
1194                 cur_state = !!(val & FDI_TX_ENABLE);
1195         }
1196         I915_STATE_WARN(cur_state != state,
1197              "FDI TX state assertion failure (expected %s, current %s)\n",
1198              state_string(state), state_string(cur_state));
1199 }
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204                           enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209
1210         reg = FDI_RX_CTL(pipe);
1211         val = I915_READ(reg);
1212         cur_state = !!(val & FDI_RX_ENABLE);
1213         I915_STATE_WARN(cur_state != state,
1214              "FDI RX state assertion failure (expected %s, current %s)\n",
1215              state_string(state), state_string(cur_state));
1216 }
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221                                       enum pipe pipe)
1222 {
1223         int reg;
1224         u32 val;
1225
1226         /* ILK FDI PLL is always enabled */
1227         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1228                 return;
1229
1230         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231         if (HAS_DDI(dev_priv->dev))
1232                 return;
1233
1234         reg = FDI_TX_CTL(pipe);
1235         val = I915_READ(reg);
1236         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1237 }
1238
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240                        enum pipe pipe, bool state)
1241 {
1242         int reg;
1243         u32 val;
1244         bool cur_state;
1245
1246         reg = FDI_RX_CTL(pipe);
1247         val = I915_READ(reg);
1248         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249         I915_STATE_WARN(cur_state != state,
1250              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251              state_string(state), state_string(cur_state));
1252 }
1253
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255                            enum pipe pipe)
1256 {
1257         struct drm_device *dev = dev_priv->dev;
1258         int pp_reg;
1259         u32 val;
1260         enum pipe panel_pipe = PIPE_A;
1261         bool locked = true;
1262
1263         if (WARN_ON(HAS_DDI(dev)))
1264                 return;
1265
1266         if (HAS_PCH_SPLIT(dev)) {
1267                 u32 port_sel;
1268
1269                 pp_reg = PCH_PP_CONTROL;
1270                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274                         panel_pipe = PIPE_B;
1275                 /* XXX: else fix for eDP */
1276         } else if (IS_VALLEYVIEW(dev)) {
1277                 /* presumably write lock depends on pipe, not port select */
1278                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279                 panel_pipe = pipe;
1280         } else {
1281                 pp_reg = PP_CONTROL;
1282                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283                         panel_pipe = PIPE_B;
1284         }
1285
1286         val = I915_READ(pp_reg);
1287         if (!(val & PANEL_POWER_ON) ||
1288             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1289                 locked = false;
1290
1291         I915_STATE_WARN(panel_pipe == pipe && locked,
1292              "panel assertion failure, pipe %c regs locked\n",
1293              pipe_name(pipe));
1294 }
1295
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297                           enum pipe pipe, bool state)
1298 {
1299         struct drm_device *dev = dev_priv->dev;
1300         bool cur_state;
1301
1302         if (IS_845G(dev) || IS_I865G(dev))
1303                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1304         else
1305                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1306
1307         I915_STATE_WARN(cur_state != state,
1308              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309              pipe_name(pipe), state_string(state), state_string(cur_state));
1310 }
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315                  enum pipe pipe, bool state)
1316 {
1317         int reg;
1318         u32 val;
1319         bool cur_state;
1320         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321                                                                       pipe);
1322
1323         /* if we need the pipe quirk it must be always on */
1324         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1326                 state = true;
1327
1328         if (!intel_display_power_is_enabled(dev_priv,
1329                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1330                 cur_state = false;
1331         } else {
1332                 reg = PIPECONF(cpu_transcoder);
1333                 val = I915_READ(reg);
1334                 cur_state = !!(val & PIPECONF_ENABLE);
1335         }
1336
1337         I915_STATE_WARN(cur_state != state,
1338              "pipe %c assertion failure (expected %s, current %s)\n",
1339              pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343                          enum plane plane, bool state)
1344 {
1345         int reg;
1346         u32 val;
1347         bool cur_state;
1348
1349         reg = DSPCNTR(plane);
1350         val = I915_READ(reg);
1351         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352         I915_STATE_WARN(cur_state != state,
1353              "plane %c assertion failure (expected %s, current %s)\n",
1354              plane_name(plane), state_string(state), state_string(cur_state));
1355 }
1356
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361                                    enum pipe pipe)
1362 {
1363         struct drm_device *dev = dev_priv->dev;
1364         int reg, i;
1365         u32 val;
1366         int cur_pipe;
1367
1368         /* Primary planes are fixed to pipes on gen4+ */
1369         if (INTEL_INFO(dev)->gen >= 4) {
1370                 reg = DSPCNTR(pipe);
1371                 val = I915_READ(reg);
1372                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373                      "plane %c assertion failure, should be disabled but not\n",
1374                      plane_name(pipe));
1375                 return;
1376         }
1377
1378         /* Need to check both planes against the pipe */
1379         for_each_pipe(dev_priv, i) {
1380                 reg = DSPCNTR(i);
1381                 val = I915_READ(reg);
1382                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383                         DISPPLANE_SEL_PIPE_SHIFT;
1384                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386                      plane_name(i), pipe_name(pipe));
1387         }
1388 }
1389
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391                                     enum pipe pipe)
1392 {
1393         struct drm_device *dev = dev_priv->dev;
1394         int reg, sprite;
1395         u32 val;
1396
1397         if (INTEL_INFO(dev)->gen >= 9) {
1398                 for_each_sprite(dev_priv, pipe, sprite) {
1399                         val = I915_READ(PLANE_CTL(pipe, sprite));
1400                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402                              sprite, pipe_name(pipe));
1403                 }
1404         } else if (IS_VALLEYVIEW(dev)) {
1405                 for_each_sprite(dev_priv, pipe, sprite) {
1406                         reg = SPCNTR(pipe, sprite);
1407                         val = I915_READ(reg);
1408                         I915_STATE_WARN(val & SP_ENABLE,
1409                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410                              sprite_name(pipe, sprite), pipe_name(pipe));
1411                 }
1412         } else if (INTEL_INFO(dev)->gen >= 7) {
1413                 reg = SPRCTL(pipe);
1414                 val = I915_READ(reg);
1415                 I915_STATE_WARN(val & SPRITE_ENABLE,
1416                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417                      plane_name(pipe), pipe_name(pipe));
1418         } else if (INTEL_INFO(dev)->gen >= 5) {
1419                 reg = DVSCNTR(pipe);
1420                 val = I915_READ(reg);
1421                 I915_STATE_WARN(val & DVS_ENABLE,
1422                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423                      plane_name(pipe), pipe_name(pipe));
1424         }
1425 }
1426
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1428 {
1429         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430                 drm_crtc_vblank_put(crtc);
1431 }
1432
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1434 {
1435         u32 val;
1436         bool enabled;
1437
1438         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1439
1440         val = I915_READ(PCH_DREF_CONTROL);
1441         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442                             DREF_SUPERSPREAD_SOURCE_MASK));
1443         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1444 }
1445
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447                                            enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451         bool enabled;
1452
1453         reg = PCH_TRANSCONF(pipe);
1454         val = I915_READ(reg);
1455         enabled = !!(val & TRANS_ENABLE);
1456         I915_STATE_WARN(enabled,
1457              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458              pipe_name(pipe));
1459 }
1460
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462                             enum pipe pipe, u32 port_sel, u32 val)
1463 {
1464         if ((val & DP_PORT_EN) == 0)
1465                 return false;
1466
1467         if (HAS_PCH_CPT(dev_priv->dev)) {
1468                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471                         return false;
1472         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474                         return false;
1475         } else {
1476                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477                         return false;
1478         }
1479         return true;
1480 }
1481
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483                               enum pipe pipe, u32 val)
1484 {
1485         if ((val & SDVO_ENABLE) == 0)
1486                 return false;
1487
1488         if (HAS_PCH_CPT(dev_priv->dev)) {
1489                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1490                         return false;
1491         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493                         return false;
1494         } else {
1495                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496                         return false;
1497         }
1498         return true;
1499 }
1500
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502                               enum pipe pipe, u32 val)
1503 {
1504         if ((val & LVDS_PORT_EN) == 0)
1505                 return false;
1506
1507         if (HAS_PCH_CPT(dev_priv->dev)) {
1508                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509                         return false;
1510         } else {
1511                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512                         return false;
1513         }
1514         return true;
1515 }
1516
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518                               enum pipe pipe, u32 val)
1519 {
1520         if ((val & ADPA_DAC_ENABLE) == 0)
1521                 return false;
1522         if (HAS_PCH_CPT(dev_priv->dev)) {
1523                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524                         return false;
1525         } else {
1526                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527                         return false;
1528         }
1529         return true;
1530 }
1531
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533                                    enum pipe pipe, int reg, u32 port_sel)
1534 {
1535         u32 val = I915_READ(reg);
1536         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538              reg, pipe_name(pipe));
1539
1540         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541              && (val & DP_PIPEB_SELECT),
1542              "IBX PCH dp port still using transcoder B\n");
1543 }
1544
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546                                      enum pipe pipe, int reg)
1547 {
1548         u32 val = I915_READ(reg);
1549         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551              reg, pipe_name(pipe));
1552
1553         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554              && (val & SDVO_PIPE_B_SELECT),
1555              "IBX PCH hdmi port still using transcoder B\n");
1556 }
1557
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559                                       enum pipe pipe)
1560 {
1561         int reg;
1562         u32 val;
1563
1564         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1567
1568         reg = PCH_ADPA;
1569         val = I915_READ(reg);
1570         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571              "PCH VGA enabled on transcoder %c, should be disabled\n",
1572              pipe_name(pipe));
1573
1574         reg = PCH_LVDS;
1575         val = I915_READ(reg);
1576         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1578              pipe_name(pipe));
1579
1580         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1583 }
1584
1585 static void intel_init_dpio(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589         if (!IS_VALLEYVIEW(dev))
1590                 return;
1591
1592         /*
1593          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594          * CHV x1 PHY (DP/HDMI D)
1595          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596          */
1597         if (IS_CHERRYVIEW(dev)) {
1598                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600         } else {
1601                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602         }
1603 }
1604
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606                            const struct intel_crtc_state *pipe_config)
1607 {
1608         struct drm_device *dev = crtc->base.dev;
1609         struct drm_i915_private *dev_priv = dev->dev_private;
1610         int reg = DPLL(crtc->pipe);
1611         u32 dpll = pipe_config->dpll_hw_state.dpll;
1612
1613         assert_pipe_disabled(dev_priv, crtc->pipe);
1614
1615         /* No really, not for ILK+ */
1616         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618         /* PLL is protected by panel, make sure we can write it */
1619         if (IS_MOBILE(dev_priv->dev))
1620                 assert_panel_unlocked(dev_priv, crtc->pipe);
1621
1622         I915_WRITE(reg, dpll);
1623         POSTING_READ(reg);
1624         udelay(150);
1625
1626         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
1629         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630         POSTING_READ(DPLL_MD(crtc->pipe));
1631
1632         /* We do this three times for luck */
1633         I915_WRITE(reg, dpll);
1634         POSTING_READ(reg);
1635         udelay(150); /* wait for warmup */
1636         I915_WRITE(reg, dpll);
1637         POSTING_READ(reg);
1638         udelay(150); /* wait for warmup */
1639         I915_WRITE(reg, dpll);
1640         POSTING_READ(reg);
1641         udelay(150); /* wait for warmup */
1642 }
1643
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645                            const struct intel_crtc_state *pipe_config)
1646 {
1647         struct drm_device *dev = crtc->base.dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         int pipe = crtc->pipe;
1650         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1651         u32 tmp;
1652
1653         assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
1657         mutex_lock(&dev_priv->sb_lock);
1658
1659         /* Enable back the 10bit clock to display controller */
1660         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661         tmp |= DPIO_DCLKP_EN;
1662         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
1664         mutex_unlock(&dev_priv->sb_lock);
1665
1666         /*
1667          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668          */
1669         udelay(1);
1670
1671         /* Enable PLL */
1672         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1673
1674         /* Check PLL is locked */
1675         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
1678         /* not sure when this should be written */
1679         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680         POSTING_READ(DPLL_MD(pipe));
1681 }
1682
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1684 {
1685         struct intel_crtc *crtc;
1686         int count = 0;
1687
1688         for_each_intel_crtc(dev, crtc)
1689                 count += crtc->base.state->active &&
1690                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1691
1692         return count;
1693 }
1694
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1696 {
1697         struct drm_device *dev = crtc->base.dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699         int reg = DPLL(crtc->pipe);
1700         u32 dpll = crtc->config->dpll_hw_state.dpll;
1701
1702         assert_pipe_disabled(dev_priv, crtc->pipe);
1703
1704         /* No really, not for ILK+ */
1705         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1706
1707         /* PLL is protected by panel, make sure we can write it */
1708         if (IS_MOBILE(dev) && !IS_I830(dev))
1709                 assert_panel_unlocked(dev_priv, crtc->pipe);
1710
1711         /* Enable DVO 2x clock on both PLLs if necessary */
1712         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713                 /*
1714                  * It appears to be important that we don't enable this
1715                  * for the current pipe before otherwise configuring the
1716                  * PLL. No idea how this should be handled if multiple
1717                  * DVO outputs are enabled simultaneosly.
1718                  */
1719                 dpll |= DPLL_DVO_2X_MODE;
1720                 I915_WRITE(DPLL(!crtc->pipe),
1721                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722         }
1723
1724         /* Wait for the clocks to stabilize. */
1725         POSTING_READ(reg);
1726         udelay(150);
1727
1728         if (INTEL_INFO(dev)->gen >= 4) {
1729                 I915_WRITE(DPLL_MD(crtc->pipe),
1730                            crtc->config->dpll_hw_state.dpll_md);
1731         } else {
1732                 /* The pixel multiplier can only be updated once the
1733                  * DPLL is enabled and the clocks are stable.
1734                  *
1735                  * So write it again.
1736                  */
1737                 I915_WRITE(reg, dpll);
1738         }
1739
1740         /* We do this three times for luck */
1741         I915_WRITE(reg, dpll);
1742         POSTING_READ(reg);
1743         udelay(150); /* wait for warmup */
1744         I915_WRITE(reg, dpll);
1745         POSTING_READ(reg);
1746         udelay(150); /* wait for warmup */
1747         I915_WRITE(reg, dpll);
1748         POSTING_READ(reg);
1749         udelay(150); /* wait for warmup */
1750 }
1751
1752 /**
1753  * i9xx_disable_pll - disable a PLL
1754  * @dev_priv: i915 private structure
1755  * @pipe: pipe PLL to disable
1756  *
1757  * Disable the PLL for @pipe, making sure the pipe is off first.
1758  *
1759  * Note!  This is for pre-ILK only.
1760  */
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->base.dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         enum pipe pipe = crtc->pipe;
1766
1767         /* Disable DVO 2x clock on both PLLs if necessary */
1768         if (IS_I830(dev) &&
1769             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770             !intel_num_dvo_pipes(dev)) {
1771                 I915_WRITE(DPLL(PIPE_B),
1772                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773                 I915_WRITE(DPLL(PIPE_A),
1774                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775         }
1776
1777         /* Don't disable pipe or pipe PLLs if needed */
1778         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1780                 return;
1781
1782         /* Make sure the pipe isn't still relying on us */
1783         assert_pipe_disabled(dev_priv, pipe);
1784
1785         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786         POSTING_READ(DPLL(pipe));
1787 }
1788
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790 {
1791         u32 val;
1792
1793         /* Make sure the pipe isn't still relying on us */
1794         assert_pipe_disabled(dev_priv, pipe);
1795
1796         /*
1797          * Leave integrated clock source and reference clock enabled for pipe B.
1798          * The latter is needed for VGA hotplug / manual detection.
1799          */
1800         val = DPLL_VGA_MODE_DIS;
1801         if (pipe == PIPE_B)
1802                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803         I915_WRITE(DPLL(pipe), val);
1804         POSTING_READ(DPLL(pipe));
1805
1806 }
1807
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809 {
1810         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1811         u32 val;
1812
1813         /* Make sure the pipe isn't still relying on us */
1814         assert_pipe_disabled(dev_priv, pipe);
1815
1816         /* Set PLL en = 0 */
1817         val = DPLL_SSC_REF_CLK_CHV |
1818                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1819         if (pipe != PIPE_A)
1820                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821         I915_WRITE(DPLL(pipe), val);
1822         POSTING_READ(DPLL(pipe));
1823
1824         mutex_lock(&dev_priv->sb_lock);
1825
1826         /* Disable 10bit clock to display controller */
1827         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828         val &= ~DPIO_DCLKP_EN;
1829         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
1831         /* disable left/right clock distribution */
1832         if (pipe != PIPE_B) {
1833                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836         } else {
1837                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840         }
1841
1842         mutex_unlock(&dev_priv->sb_lock);
1843 }
1844
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846                          struct intel_digital_port *dport,
1847                          unsigned int expected_mask)
1848 {
1849         u32 port_mask;
1850         int dpll_reg;
1851
1852         switch (dport->port) {
1853         case PORT_B:
1854                 port_mask = DPLL_PORTB_READY_MASK;
1855                 dpll_reg = DPLL(0);
1856                 break;
1857         case PORT_C:
1858                 port_mask = DPLL_PORTC_READY_MASK;
1859                 dpll_reg = DPLL(0);
1860                 expected_mask <<= 4;
1861                 break;
1862         case PORT_D:
1863                 port_mask = DPLL_PORTD_READY_MASK;
1864                 dpll_reg = DPIO_PHY_STATUS;
1865                 break;
1866         default:
1867                 BUG();
1868         }
1869
1870         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1873 }
1874
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876 {
1877         struct drm_device *dev = crtc->base.dev;
1878         struct drm_i915_private *dev_priv = dev->dev_private;
1879         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
1881         if (WARN_ON(pll == NULL))
1882                 return;
1883
1884         WARN_ON(!pll->config.crtc_mask);
1885         if (pll->active == 0) {
1886                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887                 WARN_ON(pll->on);
1888                 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890                 pll->mode_set(dev_priv, pll);
1891         }
1892 }
1893
1894 /**
1895  * intel_enable_shared_dpll - enable PCH PLL
1896  * @dev_priv: i915 private structure
1897  * @pipe: pipe PLL to enable
1898  *
1899  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900  * drives the transcoder clock.
1901  */
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1903 {
1904         struct drm_device *dev = crtc->base.dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1907
1908         if (WARN_ON(pll == NULL))
1909                 return;
1910
1911         if (WARN_ON(pll->config.crtc_mask == 0))
1912                 return;
1913
1914         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915                       pll->name, pll->active, pll->on,
1916                       crtc->base.base.id);
1917
1918         if (pll->active++) {
1919                 WARN_ON(!pll->on);
1920                 assert_shared_dpll_enabled(dev_priv, pll);
1921                 return;
1922         }
1923         WARN_ON(pll->on);
1924
1925         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
1927         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928         pll->enable(dev_priv, pll);
1929         pll->on = true;
1930 }
1931
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1933 {
1934         struct drm_device *dev = crtc->base.dev;
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1937
1938         /* PCH only available on ILK+ */
1939         if (INTEL_INFO(dev)->gen < 5)
1940                 return;
1941
1942         if (pll == NULL)
1943                 return;
1944
1945         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946                 return;
1947
1948         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949                       pll->name, pll->active, pll->on,
1950                       crtc->base.base.id);
1951
1952         if (WARN_ON(pll->active == 0)) {
1953                 assert_shared_dpll_disabled(dev_priv, pll);
1954                 return;
1955         }
1956
1957         assert_shared_dpll_enabled(dev_priv, pll);
1958         WARN_ON(!pll->on);
1959         if (--pll->active)
1960                 return;
1961
1962         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1963         pll->disable(dev_priv, pll);
1964         pll->on = false;
1965
1966         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 }
1968
1969 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970                                            enum pipe pipe)
1971 {
1972         struct drm_device *dev = dev_priv->dev;
1973         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975         uint32_t reg, val, pipeconf_val;
1976
1977         /* PCH only available on ILK+ */
1978         BUG_ON(!HAS_PCH_SPLIT(dev));
1979
1980         /* Make sure PCH DPLL is enabled */
1981         assert_shared_dpll_enabled(dev_priv,
1982                                    intel_crtc_to_shared_dpll(intel_crtc));
1983
1984         /* FDI must be feeding us bits for PCH ports */
1985         assert_fdi_tx_enabled(dev_priv, pipe);
1986         assert_fdi_rx_enabled(dev_priv, pipe);
1987
1988         if (HAS_PCH_CPT(dev)) {
1989                 /* Workaround: Set the timing override bit before enabling the
1990                  * pch transcoder. */
1991                 reg = TRANS_CHICKEN2(pipe);
1992                 val = I915_READ(reg);
1993                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994                 I915_WRITE(reg, val);
1995         }
1996
1997         reg = PCH_TRANSCONF(pipe);
1998         val = I915_READ(reg);
1999         pipeconf_val = I915_READ(PIPECONF(pipe));
2000
2001         if (HAS_PCH_IBX(dev_priv->dev)) {
2002                 /*
2003                  * Make the BPC in transcoder be consistent with
2004                  * that in pipeconf reg. For HDMI we must use 8bpc
2005                  * here for both 8bpc and 12bpc.
2006                  */
2007                 val &= ~PIPECONF_BPC_MASK;
2008                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009                         val |= PIPECONF_8BPC;
2010                 else
2011                         val |= pipeconf_val & PIPECONF_BPC_MASK;
2012         }
2013
2014         val &= ~TRANS_INTERLACE_MASK;
2015         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2016                 if (HAS_PCH_IBX(dev_priv->dev) &&
2017                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2018                         val |= TRANS_LEGACY_INTERLACED_ILK;
2019                 else
2020                         val |= TRANS_INTERLACED;
2021         else
2022                 val |= TRANS_PROGRESSIVE;
2023
2024         I915_WRITE(reg, val | TRANS_ENABLE);
2025         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2026                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 }
2028
2029 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2030                                       enum transcoder cpu_transcoder)
2031 {
2032         u32 val, pipeconf_val;
2033
2034         /* PCH only available on ILK+ */
2035         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2036
2037         /* FDI must be feeding us bits for PCH ports */
2038         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2039         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2040
2041         /* Workaround: set timing override bit. */
2042         val = I915_READ(_TRANSA_CHICKEN2);
2043         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2044         I915_WRITE(_TRANSA_CHICKEN2, val);
2045
2046         val = TRANS_ENABLE;
2047         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2048
2049         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050             PIPECONF_INTERLACED_ILK)
2051                 val |= TRANS_INTERLACED;
2052         else
2053                 val |= TRANS_PROGRESSIVE;
2054
2055         I915_WRITE(LPT_TRANSCONF, val);
2056         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2057                 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 }
2059
2060 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061                                             enum pipe pipe)
2062 {
2063         struct drm_device *dev = dev_priv->dev;
2064         uint32_t reg, val;
2065
2066         /* FDI relies on the transcoder */
2067         assert_fdi_tx_disabled(dev_priv, pipe);
2068         assert_fdi_rx_disabled(dev_priv, pipe);
2069
2070         /* Ports must be off as well */
2071         assert_pch_ports_disabled(dev_priv, pipe);
2072
2073         reg = PCH_TRANSCONF(pipe);
2074         val = I915_READ(reg);
2075         val &= ~TRANS_ENABLE;
2076         I915_WRITE(reg, val);
2077         /* wait for PCH transcoder off, transcoder state */
2078         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2079                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2080
2081         if (!HAS_PCH_IBX(dev)) {
2082                 /* Workaround: Clear the timing override chicken bit again. */
2083                 reg = TRANS_CHICKEN2(pipe);
2084                 val = I915_READ(reg);
2085                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086                 I915_WRITE(reg, val);
2087         }
2088 }
2089
2090 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2091 {
2092         u32 val;
2093
2094         val = I915_READ(LPT_TRANSCONF);
2095         val &= ~TRANS_ENABLE;
2096         I915_WRITE(LPT_TRANSCONF, val);
2097         /* wait for PCH transcoder off, transcoder state */
2098         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2099                 DRM_ERROR("Failed to disable PCH transcoder\n");
2100
2101         /* Workaround: clear timing override bit. */
2102         val = I915_READ(_TRANSA_CHICKEN2);
2103         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2104         I915_WRITE(_TRANSA_CHICKEN2, val);
2105 }
2106
2107 /**
2108  * intel_enable_pipe - enable a pipe, asserting requirements
2109  * @crtc: crtc responsible for the pipe
2110  *
2111  * Enable @crtc's pipe, making sure that various hardware specific requirements
2112  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2113  */
2114 static void intel_enable_pipe(struct intel_crtc *crtc)
2115 {
2116         struct drm_device *dev = crtc->base.dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         enum pipe pipe = crtc->pipe;
2119         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120                                                                       pipe);
2121         enum pipe pch_transcoder;
2122         int reg;
2123         u32 val;
2124
2125         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
2127         assert_planes_disabled(dev_priv, pipe);
2128         assert_cursor_disabled(dev_priv, pipe);
2129         assert_sprites_disabled(dev_priv, pipe);
2130
2131         if (HAS_PCH_LPT(dev_priv->dev))
2132                 pch_transcoder = TRANSCODER_A;
2133         else
2134                 pch_transcoder = pipe;
2135
2136         /*
2137          * A pipe without a PLL won't actually be able to drive bits from
2138          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2139          * need the check.
2140          */
2141         if (HAS_GMCH_DISPLAY(dev_priv->dev))
2142                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2143                         assert_dsi_pll_enabled(dev_priv);
2144                 else
2145                         assert_pll_enabled(dev_priv, pipe);
2146         else {
2147                 if (crtc->config->has_pch_encoder) {
2148                         /* if driving the PCH, we need FDI enabled */
2149                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2150                         assert_fdi_tx_pll_enabled(dev_priv,
2151                                                   (enum pipe) cpu_transcoder);
2152                 }
2153                 /* FIXME: assert CPU port conditions for SNB+ */
2154         }
2155
2156         reg = PIPECONF(cpu_transcoder);
2157         val = I915_READ(reg);
2158         if (val & PIPECONF_ENABLE) {
2159                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2161                 return;
2162         }
2163
2164         I915_WRITE(reg, val | PIPECONF_ENABLE);
2165         POSTING_READ(reg);
2166 }
2167
2168 /**
2169  * intel_disable_pipe - disable a pipe, asserting requirements
2170  * @crtc: crtc whose pipes is to be disabled
2171  *
2172  * Disable the pipe of @crtc, making sure that various hardware
2173  * specific requirements are met, if applicable, e.g. plane
2174  * disabled, panel fitter off, etc.
2175  *
2176  * Will wait until the pipe has shut down before returning.
2177  */
2178 static void intel_disable_pipe(struct intel_crtc *crtc)
2179 {
2180         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2181         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2182         enum pipe pipe = crtc->pipe;
2183         int reg;
2184         u32 val;
2185
2186         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
2188         /*
2189          * Make sure planes won't keep trying to pump pixels to us,
2190          * or we might hang the display.
2191          */
2192         assert_planes_disabled(dev_priv, pipe);
2193         assert_cursor_disabled(dev_priv, pipe);
2194         assert_sprites_disabled(dev_priv, pipe);
2195
2196         reg = PIPECONF(cpu_transcoder);
2197         val = I915_READ(reg);
2198         if ((val & PIPECONF_ENABLE) == 0)
2199                 return;
2200
2201         /*
2202          * Double wide has implications for planes
2203          * so best keep it disabled when not needed.
2204          */
2205         if (crtc->config->double_wide)
2206                 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208         /* Don't disable pipe or pipe PLLs if needed */
2209         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2211                 val &= ~PIPECONF_ENABLE;
2212
2213         I915_WRITE(reg, val);
2214         if ((val & PIPECONF_ENABLE) == 0)
2215                 intel_wait_for_pipe_off(crtc);
2216 }
2217
2218 static bool need_vtd_wa(struct drm_device *dev)
2219 {
2220 #ifdef CONFIG_INTEL_IOMMU
2221         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222                 return true;
2223 #endif
2224         return false;
2225 }
2226
2227 unsigned int
2228 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229                   uint64_t fb_format_modifier)
2230 {
2231         unsigned int tile_height;
2232         uint32_t pixel_bytes;
2233
2234         switch (fb_format_modifier) {
2235         case DRM_FORMAT_MOD_NONE:
2236                 tile_height = 1;
2237                 break;
2238         case I915_FORMAT_MOD_X_TILED:
2239                 tile_height = IS_GEN2(dev) ? 16 : 8;
2240                 break;
2241         case I915_FORMAT_MOD_Y_TILED:
2242                 tile_height = 32;
2243                 break;
2244         case I915_FORMAT_MOD_Yf_TILED:
2245                 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246                 switch (pixel_bytes) {
2247                 default:
2248                 case 1:
2249                         tile_height = 64;
2250                         break;
2251                 case 2:
2252                 case 4:
2253                         tile_height = 32;
2254                         break;
2255                 case 8:
2256                         tile_height = 16;
2257                         break;
2258                 case 16:
2259                         WARN_ONCE(1,
2260                                   "128-bit pixels are not supported for display!");
2261                         tile_height = 16;
2262                         break;
2263                 }
2264                 break;
2265         default:
2266                 MISSING_CASE(fb_format_modifier);
2267                 tile_height = 1;
2268                 break;
2269         }
2270
2271         return tile_height;
2272 }
2273
2274 unsigned int
2275 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276                       uint32_t pixel_format, uint64_t fb_format_modifier)
2277 {
2278         return ALIGN(height, intel_tile_height(dev, pixel_format,
2279                                                fb_format_modifier));
2280 }
2281
2282 static int
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284                         const struct drm_plane_state *plane_state)
2285 {
2286         struct intel_rotation_info *info = &view->rotation_info;
2287         unsigned int tile_height, tile_pitch;
2288
2289         *view = i915_ggtt_view_normal;
2290
2291         if (!plane_state)
2292                 return 0;
2293
2294         if (!intel_rotation_90_or_270(plane_state->rotation))
2295                 return 0;
2296
2297         *view = i915_ggtt_view_rotated;
2298
2299         info->height = fb->height;
2300         info->pixel_format = fb->pixel_format;
2301         info->pitch = fb->pitches[0];
2302         info->fb_modifier = fb->modifier[0];
2303
2304         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305                                         fb->modifier[0]);
2306         tile_pitch = PAGE_SIZE / tile_height;
2307         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
2311         return 0;
2312 }
2313
2314 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315 {
2316         if (INTEL_INFO(dev_priv)->gen >= 9)
2317                 return 256 * 1024;
2318         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319                  IS_VALLEYVIEW(dev_priv))
2320                 return 128 * 1024;
2321         else if (INTEL_INFO(dev_priv)->gen >= 4)
2322                 return 4 * 1024;
2323         else
2324                 return 0;
2325 }
2326
2327 int
2328 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329                            struct drm_framebuffer *fb,
2330                            const struct drm_plane_state *plane_state,
2331                            struct intel_engine_cs *pipelined,
2332                            struct drm_i915_gem_request **pipelined_request)
2333 {
2334         struct drm_device *dev = fb->dev;
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2337         struct i915_ggtt_view view;
2338         u32 alignment;
2339         int ret;
2340
2341         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
2343         switch (fb->modifier[0]) {
2344         case DRM_FORMAT_MOD_NONE:
2345                 alignment = intel_linear_alignment(dev_priv);
2346                 break;
2347         case I915_FORMAT_MOD_X_TILED:
2348                 if (INTEL_INFO(dev)->gen >= 9)
2349                         alignment = 256 * 1024;
2350                 else {
2351                         /* pin() will align the object as required by fence */
2352                         alignment = 0;
2353                 }
2354                 break;
2355         case I915_FORMAT_MOD_Y_TILED:
2356         case I915_FORMAT_MOD_Yf_TILED:
2357                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358                           "Y tiling bo slipped through, driver bug!\n"))
2359                         return -EINVAL;
2360                 alignment = 1 * 1024 * 1024;
2361                 break;
2362         default:
2363                 MISSING_CASE(fb->modifier[0]);
2364                 return -EINVAL;
2365         }
2366
2367         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368         if (ret)
2369                 return ret;
2370
2371         /* Note that the w/a also requires 64 PTE of padding following the
2372          * bo. We currently fill all unused PTE with the shadow page and so
2373          * we should always have valid PTE following the scanout preventing
2374          * the VT-d warning.
2375          */
2376         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377                 alignment = 256 * 1024;
2378
2379         /*
2380          * Global gtt pte registers are special registers which actually forward
2381          * writes to a chunk of system memory. Which means that there is no risk
2382          * that the register values disappear as soon as we call
2383          * intel_runtime_pm_put(), so it is correct to wrap only the
2384          * pin/unpin/fence and not more.
2385          */
2386         intel_runtime_pm_get(dev_priv);
2387
2388         dev_priv->mm.interruptible = false;
2389         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2390                                                    pipelined_request, &view);
2391         if (ret)
2392                 goto err_interruptible;
2393
2394         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395          * fence, whereas 965+ only requires a fence if using
2396          * framebuffer compression.  For simplicity, we always install
2397          * a fence as the cost is not that onerous.
2398          */
2399         ret = i915_gem_object_get_fence(obj);
2400         if (ret == -EDEADLK) {
2401                 /*
2402                  * -EDEADLK means there are no free fences
2403                  * no pending flips.
2404                  *
2405                  * This is propagated to atomic, but it uses
2406                  * -EDEADLK to force a locking recovery, so
2407                  * change the returned error to -EBUSY.
2408                  */
2409                 ret = -EBUSY;
2410                 goto err_unpin;
2411         } else if (ret)
2412                 goto err_unpin;
2413
2414         i915_gem_object_pin_fence(obj);
2415
2416         dev_priv->mm.interruptible = true;
2417         intel_runtime_pm_put(dev_priv);
2418         return 0;
2419
2420 err_unpin:
2421         i915_gem_object_unpin_from_display_plane(obj, &view);
2422 err_interruptible:
2423         dev_priv->mm.interruptible = true;
2424         intel_runtime_pm_put(dev_priv);
2425         return ret;
2426 }
2427
2428 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429                                const struct drm_plane_state *plane_state)
2430 {
2431         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2432         struct i915_ggtt_view view;
2433         int ret;
2434
2435         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
2437         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438         WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
2440         i915_gem_object_unpin_fence(obj);
2441         i915_gem_object_unpin_from_display_plane(obj, &view);
2442 }
2443
2444 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445  * is assumed to be a power-of-two. */
2446 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2447                                              int *x, int *y,
2448                                              unsigned int tiling_mode,
2449                                              unsigned int cpp,
2450                                              unsigned int pitch)
2451 {
2452         if (tiling_mode != I915_TILING_NONE) {
2453                 unsigned int tile_rows, tiles;
2454
2455                 tile_rows = *y / 8;
2456                 *y %= 8;
2457
2458                 tiles = *x / (512/cpp);
2459                 *x %= 512/cpp;
2460
2461                 return tile_rows * pitch * 8 + tiles * 4096;
2462         } else {
2463                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2464                 unsigned int offset;
2465
2466                 offset = *y * pitch + *x * cpp;
2467                 *y = (offset & alignment) / pitch;
2468                 *x = ((offset & alignment) - *y * pitch) / cpp;
2469                 return offset & ~alignment;
2470         }
2471 }
2472
2473 static int i9xx_format_to_fourcc(int format)
2474 {
2475         switch (format) {
2476         case DISPPLANE_8BPP:
2477                 return DRM_FORMAT_C8;
2478         case DISPPLANE_BGRX555:
2479                 return DRM_FORMAT_XRGB1555;
2480         case DISPPLANE_BGRX565:
2481                 return DRM_FORMAT_RGB565;
2482         default:
2483         case DISPPLANE_BGRX888:
2484                 return DRM_FORMAT_XRGB8888;
2485         case DISPPLANE_RGBX888:
2486                 return DRM_FORMAT_XBGR8888;
2487         case DISPPLANE_BGRX101010:
2488                 return DRM_FORMAT_XRGB2101010;
2489         case DISPPLANE_RGBX101010:
2490                 return DRM_FORMAT_XBGR2101010;
2491         }
2492 }
2493
2494 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2495 {
2496         switch (format) {
2497         case PLANE_CTL_FORMAT_RGB_565:
2498                 return DRM_FORMAT_RGB565;
2499         default:
2500         case PLANE_CTL_FORMAT_XRGB_8888:
2501                 if (rgb_order) {
2502                         if (alpha)
2503                                 return DRM_FORMAT_ABGR8888;
2504                         else
2505                                 return DRM_FORMAT_XBGR8888;
2506                 } else {
2507                         if (alpha)
2508                                 return DRM_FORMAT_ARGB8888;
2509                         else
2510                                 return DRM_FORMAT_XRGB8888;
2511                 }
2512         case PLANE_CTL_FORMAT_XRGB_2101010:
2513                 if (rgb_order)
2514                         return DRM_FORMAT_XBGR2101010;
2515                 else
2516                         return DRM_FORMAT_XRGB2101010;
2517         }
2518 }
2519
2520 static bool
2521 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2522                               struct intel_initial_plane_config *plane_config)
2523 {
2524         struct drm_device *dev = crtc->base.dev;
2525         struct drm_i915_gem_object *obj = NULL;
2526         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2527         struct drm_framebuffer *fb = &plane_config->fb->base;
2528         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2529         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2530                                     PAGE_SIZE);
2531
2532         size_aligned -= base_aligned;
2533
2534         if (plane_config->size == 0)
2535                 return false;
2536
2537         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538                                                              base_aligned,
2539                                                              base_aligned,
2540                                                              size_aligned);
2541         if (!obj)
2542                 return false;
2543
2544         obj->tiling_mode = plane_config->tiling;
2545         if (obj->tiling_mode == I915_TILING_X)
2546                 obj->stride = fb->pitches[0];
2547
2548         mode_cmd.pixel_format = fb->pixel_format;
2549         mode_cmd.width = fb->width;
2550         mode_cmd.height = fb->height;
2551         mode_cmd.pitches[0] = fb->pitches[0];
2552         mode_cmd.modifier[0] = fb->modifier[0];
2553         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2554
2555         mutex_lock(&dev->struct_mutex);
2556         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2557                                    &mode_cmd, obj)) {
2558                 DRM_DEBUG_KMS("intel fb init failed\n");
2559                 goto out_unref_obj;
2560         }
2561         mutex_unlock(&dev->struct_mutex);
2562
2563         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2564         return true;
2565
2566 out_unref_obj:
2567         drm_gem_object_unreference(&obj->base);
2568         mutex_unlock(&dev->struct_mutex);
2569         return false;
2570 }
2571
2572 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2573 static void
2574 update_state_fb(struct drm_plane *plane)
2575 {
2576         if (plane->fb == plane->state->fb)
2577                 return;
2578
2579         if (plane->state->fb)
2580                 drm_framebuffer_unreference(plane->state->fb);
2581         plane->state->fb = plane->fb;
2582         if (plane->state->fb)
2583                 drm_framebuffer_reference(plane->state->fb);
2584 }
2585
2586 static void
2587 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588                              struct intel_initial_plane_config *plane_config)
2589 {
2590         struct drm_device *dev = intel_crtc->base.dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         struct drm_crtc *c;
2593         struct intel_crtc *i;
2594         struct drm_i915_gem_object *obj;
2595         struct drm_plane *primary = intel_crtc->base.primary;
2596         struct drm_plane_state *plane_state = primary->state;
2597         struct drm_framebuffer *fb;
2598
2599         if (!plane_config->fb)
2600                 return;
2601
2602         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2603                 fb = &plane_config->fb->base;
2604                 goto valid_fb;
2605         }
2606
2607         kfree(plane_config->fb);
2608
2609         /*
2610          * Failed to alloc the obj, check to see if we should share
2611          * an fb with another CRTC instead
2612          */
2613         for_each_crtc(dev, c) {
2614                 i = to_intel_crtc(c);
2615
2616                 if (c == &intel_crtc->base)
2617                         continue;
2618
2619                 if (!i->active)
2620                         continue;
2621
2622                 fb = c->primary->fb;
2623                 if (!fb)
2624                         continue;
2625
2626                 obj = intel_fb_obj(fb);
2627                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2628                         drm_framebuffer_reference(fb);
2629                         goto valid_fb;
2630                 }
2631         }
2632
2633         return;
2634
2635 valid_fb:
2636         plane_state->src_x = plane_state->src_y = 0;
2637         plane_state->src_w = fb->width << 16;
2638         plane_state->src_h = fb->height << 16;
2639
2640         plane_state->crtc_x = plane_state->src_y = 0;
2641         plane_state->crtc_w = fb->width;
2642         plane_state->crtc_h = fb->height;
2643
2644         obj = intel_fb_obj(fb);
2645         if (obj->tiling_mode != I915_TILING_NONE)
2646                 dev_priv->preserve_bios_swizzle = true;
2647
2648         drm_framebuffer_reference(fb);
2649         primary->fb = primary->state->fb = fb;
2650         primary->crtc = primary->state->crtc = &intel_crtc->base;
2651         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2652         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2653 }
2654
2655 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656                                       struct drm_framebuffer *fb,
2657                                       int x, int y)
2658 {
2659         struct drm_device *dev = crtc->dev;
2660         struct drm_i915_private *dev_priv = dev->dev_private;
2661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2662         struct drm_plane *primary = crtc->primary;
2663         bool visible = to_intel_plane_state(primary->state)->visible;
2664         struct drm_i915_gem_object *obj;
2665         int plane = intel_crtc->plane;
2666         unsigned long linear_offset;
2667         u32 dspcntr;
2668         u32 reg = DSPCNTR(plane);
2669         int pixel_size;
2670
2671         if (!visible || !fb) {
2672                 I915_WRITE(reg, 0);
2673                 if (INTEL_INFO(dev)->gen >= 4)
2674                         I915_WRITE(DSPSURF(plane), 0);
2675                 else
2676                         I915_WRITE(DSPADDR(plane), 0);
2677                 POSTING_READ(reg);
2678                 return;
2679         }
2680
2681         obj = intel_fb_obj(fb);
2682         if (WARN_ON(obj == NULL))
2683                 return;
2684
2685         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
2687         dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
2689         dspcntr |= DISPLAY_PLANE_ENABLE;
2690
2691         if (INTEL_INFO(dev)->gen < 4) {
2692                 if (intel_crtc->pipe == PIPE_B)
2693                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695                 /* pipesrc and dspsize control the size that is scaled from,
2696                  * which should always be the user's requested size.
2697                  */
2698                 I915_WRITE(DSPSIZE(plane),
2699                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700                            (intel_crtc->config->pipe_src_w - 1));
2701                 I915_WRITE(DSPPOS(plane), 0);
2702         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703                 I915_WRITE(PRIMSIZE(plane),
2704                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705                            (intel_crtc->config->pipe_src_w - 1));
2706                 I915_WRITE(PRIMPOS(plane), 0);
2707                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2708         }
2709
2710         switch (fb->pixel_format) {
2711         case DRM_FORMAT_C8:
2712                 dspcntr |= DISPPLANE_8BPP;
2713                 break;
2714         case DRM_FORMAT_XRGB1555:
2715                 dspcntr |= DISPPLANE_BGRX555;
2716                 break;
2717         case DRM_FORMAT_RGB565:
2718                 dspcntr |= DISPPLANE_BGRX565;
2719                 break;
2720         case DRM_FORMAT_XRGB8888:
2721                 dspcntr |= DISPPLANE_BGRX888;
2722                 break;
2723         case DRM_FORMAT_XBGR8888:
2724                 dspcntr |= DISPPLANE_RGBX888;
2725                 break;
2726         case DRM_FORMAT_XRGB2101010:
2727                 dspcntr |= DISPPLANE_BGRX101010;
2728                 break;
2729         case DRM_FORMAT_XBGR2101010:
2730                 dspcntr |= DISPPLANE_RGBX101010;
2731                 break;
2732         default:
2733                 BUG();
2734         }
2735
2736         if (INTEL_INFO(dev)->gen >= 4 &&
2737             obj->tiling_mode != I915_TILING_NONE)
2738                 dspcntr |= DISPPLANE_TILED;
2739
2740         if (IS_G4X(dev))
2741                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
2743         linear_offset = y * fb->pitches[0] + x * pixel_size;
2744
2745         if (INTEL_INFO(dev)->gen >= 4) {
2746                 intel_crtc->dspaddr_offset =
2747                         intel_gen4_compute_page_offset(dev_priv,
2748                                                        &x, &y, obj->tiling_mode,
2749                                                        pixel_size,
2750                                                        fb->pitches[0]);
2751                 linear_offset -= intel_crtc->dspaddr_offset;
2752         } else {
2753                 intel_crtc->dspaddr_offset = linear_offset;
2754         }
2755
2756         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2757                 dspcntr |= DISPPLANE_ROTATE_180;
2758
2759                 x += (intel_crtc->config->pipe_src_w - 1);
2760                 y += (intel_crtc->config->pipe_src_h - 1);
2761
2762                 /* Finding the last pixel of the last line of the display
2763                 data and adding to linear_offset*/
2764                 linear_offset +=
2765                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2767         }
2768
2769         I915_WRITE(reg, dspcntr);
2770
2771         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2772         if (INTEL_INFO(dev)->gen >= 4) {
2773                 I915_WRITE(DSPSURF(plane),
2774                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2775                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2776                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2777         } else
2778                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2779         POSTING_READ(reg);
2780 }
2781
2782 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783                                           struct drm_framebuffer *fb,
2784                                           int x, int y)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         struct drm_plane *primary = crtc->primary;
2790         bool visible = to_intel_plane_state(primary->state)->visible;
2791         struct drm_i915_gem_object *obj;
2792         int plane = intel_crtc->plane;
2793         unsigned long linear_offset;
2794         u32 dspcntr;
2795         u32 reg = DSPCNTR(plane);
2796         int pixel_size;
2797
2798         if (!visible || !fb) {
2799                 I915_WRITE(reg, 0);
2800                 I915_WRITE(DSPSURF(plane), 0);
2801                 POSTING_READ(reg);
2802                 return;
2803         }
2804
2805         obj = intel_fb_obj(fb);
2806         if (WARN_ON(obj == NULL))
2807                 return;
2808
2809         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
2811         dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
2813         dspcntr |= DISPLAY_PLANE_ENABLE;
2814
2815         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2817
2818         switch (fb->pixel_format) {
2819         case DRM_FORMAT_C8:
2820                 dspcntr |= DISPPLANE_8BPP;
2821                 break;
2822         case DRM_FORMAT_RGB565:
2823                 dspcntr |= DISPPLANE_BGRX565;
2824                 break;
2825         case DRM_FORMAT_XRGB8888:
2826                 dspcntr |= DISPPLANE_BGRX888;
2827                 break;
2828         case DRM_FORMAT_XBGR8888:
2829                 dspcntr |= DISPPLANE_RGBX888;
2830                 break;
2831         case DRM_FORMAT_XRGB2101010:
2832                 dspcntr |= DISPPLANE_BGRX101010;
2833                 break;
2834         case DRM_FORMAT_XBGR2101010:
2835                 dspcntr |= DISPPLANE_RGBX101010;
2836                 break;
2837         default:
2838                 BUG();
2839         }
2840
2841         if (obj->tiling_mode != I915_TILING_NONE)
2842                 dspcntr |= DISPPLANE_TILED;
2843
2844         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2845                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2846
2847         linear_offset = y * fb->pitches[0] + x * pixel_size;
2848         intel_crtc->dspaddr_offset =
2849                 intel_gen4_compute_page_offset(dev_priv,
2850                                                &x, &y, obj->tiling_mode,
2851                                                pixel_size,
2852                                                fb->pitches[0]);
2853         linear_offset -= intel_crtc->dspaddr_offset;
2854         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2855                 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2858                         x += (intel_crtc->config->pipe_src_w - 1);
2859                         y += (intel_crtc->config->pipe_src_h - 1);
2860
2861                         /* Finding the last pixel of the last line of the display
2862                         data and adding to linear_offset*/
2863                         linear_offset +=
2864                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2866                 }
2867         }
2868
2869         I915_WRITE(reg, dspcntr);
2870
2871         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2872         I915_WRITE(DSPSURF(plane),
2873                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2874         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2875                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876         } else {
2877                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879         }
2880         POSTING_READ(reg);
2881 }
2882
2883 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884                               uint32_t pixel_format)
2885 {
2886         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888         /*
2889          * The stride is either expressed as a multiple of 64 bytes
2890          * chunks for linear buffers or in number of tiles for tiled
2891          * buffers.
2892          */
2893         switch (fb_modifier) {
2894         case DRM_FORMAT_MOD_NONE:
2895                 return 64;
2896         case I915_FORMAT_MOD_X_TILED:
2897                 if (INTEL_INFO(dev)->gen == 2)
2898                         return 128;
2899                 return 512;
2900         case I915_FORMAT_MOD_Y_TILED:
2901                 /* No need to check for old gens and Y tiling since this is
2902                  * about the display engine and those will be blocked before
2903                  * we get here.
2904                  */
2905                 return 128;
2906         case I915_FORMAT_MOD_Yf_TILED:
2907                 if (bits_per_pixel == 8)
2908                         return 64;
2909                 else
2910                         return 128;
2911         default:
2912                 MISSING_CASE(fb_modifier);
2913                 return 64;
2914         }
2915 }
2916
2917 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2918                                      struct drm_i915_gem_object *obj)
2919 {
2920         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2921
2922         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2923                 view = &i915_ggtt_view_rotated;
2924
2925         return i915_gem_obj_ggtt_offset_view(obj, view);
2926 }
2927
2928 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2929 {
2930         struct drm_device *dev = intel_crtc->base.dev;
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2934         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2935         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2936         DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2937                 intel_crtc->base.base.id, intel_crtc->pipe, id);
2938 }
2939
2940 /*
2941  * This function detaches (aka. unbinds) unused scalers in hardware
2942  */
2943 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2944 {
2945         struct intel_crtc_scaler_state *scaler_state;
2946         int i;
2947
2948         scaler_state = &intel_crtc->config->scaler_state;
2949
2950         /* loop through and disable scalers that aren't in use */
2951         for (i = 0; i < intel_crtc->num_scalers; i++) {
2952                 if (!scaler_state->scalers[i].in_use)
2953                         skl_detach_scaler(intel_crtc, i);
2954         }
2955 }
2956
2957 u32 skl_plane_ctl_format(uint32_t pixel_format)
2958 {
2959         switch (pixel_format) {
2960         case DRM_FORMAT_C8:
2961                 return PLANE_CTL_FORMAT_INDEXED;
2962         case DRM_FORMAT_RGB565:
2963                 return PLANE_CTL_FORMAT_RGB_565;
2964         case DRM_FORMAT_XBGR8888:
2965                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2966         case DRM_FORMAT_XRGB8888:
2967                 return PLANE_CTL_FORMAT_XRGB_8888;
2968         /*
2969          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2970          * to be already pre-multiplied. We need to add a knob (or a different
2971          * DRM_FORMAT) for user-space to configure that.
2972          */
2973         case DRM_FORMAT_ABGR8888:
2974                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2975                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2976         case DRM_FORMAT_ARGB8888:
2977                 return PLANE_CTL_FORMAT_XRGB_8888 |
2978                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979         case DRM_FORMAT_XRGB2101010:
2980                 return PLANE_CTL_FORMAT_XRGB_2101010;
2981         case DRM_FORMAT_XBGR2101010:
2982                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2983         case DRM_FORMAT_YUYV:
2984                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2985         case DRM_FORMAT_YVYU:
2986                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2987         case DRM_FORMAT_UYVY:
2988                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2989         case DRM_FORMAT_VYUY:
2990                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2991         default:
2992                 MISSING_CASE(pixel_format);
2993         }
2994
2995         return 0;
2996 }
2997
2998 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2999 {
3000         switch (fb_modifier) {
3001         case DRM_FORMAT_MOD_NONE:
3002                 break;
3003         case I915_FORMAT_MOD_X_TILED:
3004                 return PLANE_CTL_TILED_X;
3005         case I915_FORMAT_MOD_Y_TILED:
3006                 return PLANE_CTL_TILED_Y;
3007         case I915_FORMAT_MOD_Yf_TILED:
3008                 return PLANE_CTL_TILED_YF;
3009         default:
3010                 MISSING_CASE(fb_modifier);
3011         }
3012
3013         return 0;
3014 }
3015
3016 u32 skl_plane_ctl_rotation(unsigned int rotation)
3017 {
3018         switch (rotation) {
3019         case BIT(DRM_ROTATE_0):
3020                 break;
3021         /*
3022          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3023          * while i915 HW rotation is clockwise, thats why this swapping.
3024          */
3025         case BIT(DRM_ROTATE_90):
3026                 return PLANE_CTL_ROTATE_270;
3027         case BIT(DRM_ROTATE_180):
3028                 return PLANE_CTL_ROTATE_180;
3029         case BIT(DRM_ROTATE_270):
3030                 return PLANE_CTL_ROTATE_90;
3031         default:
3032                 MISSING_CASE(rotation);
3033         }
3034
3035         return 0;
3036 }
3037
3038 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3039                                          struct drm_framebuffer *fb,
3040                                          int x, int y)
3041 {
3042         struct drm_device *dev = crtc->dev;
3043         struct drm_i915_private *dev_priv = dev->dev_private;
3044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3045         struct drm_plane *plane = crtc->primary;
3046         bool visible = to_intel_plane_state(plane->state)->visible;
3047         struct drm_i915_gem_object *obj;
3048         int pipe = intel_crtc->pipe;
3049         u32 plane_ctl, stride_div, stride;
3050         u32 tile_height, plane_offset, plane_size;
3051         unsigned int rotation;
3052         int x_offset, y_offset;
3053         unsigned long surf_addr;
3054         struct intel_crtc_state *crtc_state = intel_crtc->config;
3055         struct intel_plane_state *plane_state;
3056         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3057         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3058         int scaler_id = -1;
3059
3060         plane_state = to_intel_plane_state(plane->state);
3061
3062         if (!visible || !fb) {
3063                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3064                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3065                 POSTING_READ(PLANE_CTL(pipe, 0));
3066                 return;
3067         }
3068
3069         plane_ctl = PLANE_CTL_ENABLE |
3070                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3071                     PLANE_CTL_PIPE_CSC_ENABLE;
3072
3073         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3074         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3075         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3076
3077         rotation = plane->state->rotation;
3078         plane_ctl |= skl_plane_ctl_rotation(rotation);
3079
3080         obj = intel_fb_obj(fb);
3081         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3082                                                fb->pixel_format);
3083         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3084
3085         /*
3086          * FIXME: intel_plane_state->src, dst aren't set when transitional
3087          * update_plane helpers are called from legacy paths.
3088          * Once full atomic crtc is available, below check can be avoided.
3089          */
3090         if (drm_rect_width(&plane_state->src)) {
3091                 scaler_id = plane_state->scaler_id;
3092                 src_x = plane_state->src.x1 >> 16;
3093                 src_y = plane_state->src.y1 >> 16;
3094                 src_w = drm_rect_width(&plane_state->src) >> 16;
3095                 src_h = drm_rect_height(&plane_state->src) >> 16;
3096                 dst_x = plane_state->dst.x1;
3097                 dst_y = plane_state->dst.y1;
3098                 dst_w = drm_rect_width(&plane_state->dst);
3099                 dst_h = drm_rect_height(&plane_state->dst);
3100
3101                 WARN_ON(x != src_x || y != src_y);
3102         } else {
3103                 src_w = intel_crtc->config->pipe_src_w;
3104                 src_h = intel_crtc->config->pipe_src_h;
3105         }
3106
3107         if (intel_rotation_90_or_270(rotation)) {
3108                 /* stride = Surface height in tiles */
3109                 tile_height = intel_tile_height(dev, fb->pixel_format,
3110                                                 fb->modifier[0]);
3111                 stride = DIV_ROUND_UP(fb->height, tile_height);
3112                 x_offset = stride * tile_height - y - src_h;
3113                 y_offset = x;
3114                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3115         } else {
3116                 stride = fb->pitches[0] / stride_div;
3117                 x_offset = x;
3118                 y_offset = y;
3119                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3120         }
3121         plane_offset = y_offset << 16 | x_offset;
3122
3123         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3124         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3125         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3126         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3127
3128         if (scaler_id >= 0) {
3129                 uint32_t ps_ctrl = 0;
3130
3131                 WARN_ON(!dst_w || !dst_h);
3132                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3133                         crtc_state->scaler_state.scalers[scaler_id].mode;
3134                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3135                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3136                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3137                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3138                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3139         } else {
3140                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3141         }
3142
3143         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3144
3145         POSTING_READ(PLANE_SURF(pipe, 0));
3146 }
3147
3148 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3149 static int
3150 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3151                            int x, int y, enum mode_set_atomic state)
3152 {
3153         struct drm_device *dev = crtc->dev;
3154         struct drm_i915_private *dev_priv = dev->dev_private;
3155
3156         if (dev_priv->fbc.disable_fbc)
3157                 dev_priv->fbc.disable_fbc(dev_priv);
3158
3159         dev_priv->display.update_primary_plane(crtc, fb, x, y);
3160
3161         return 0;
3162 }
3163
3164 static void intel_complete_page_flips(struct drm_device *dev)
3165 {
3166         struct drm_crtc *crtc;
3167
3168         for_each_crtc(dev, crtc) {
3169                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170                 enum plane plane = intel_crtc->plane;
3171
3172                 intel_prepare_page_flip(dev, plane);
3173                 intel_finish_page_flip_plane(dev, plane);
3174         }
3175 }
3176
3177 static void intel_update_primary_planes(struct drm_device *dev)
3178 {
3179         struct drm_i915_private *dev_priv = dev->dev_private;
3180         struct drm_crtc *crtc;
3181
3182         for_each_crtc(dev, crtc) {
3183                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184
3185                 drm_modeset_lock(&crtc->mutex, NULL);
3186                 /*
3187                  * FIXME: Once we have proper support for primary planes (and
3188                  * disabling them without disabling the entire crtc) allow again
3189                  * a NULL crtc->primary->fb.
3190                  */
3191                 if (intel_crtc->active && crtc->primary->fb)
3192                         dev_priv->display.update_primary_plane(crtc,
3193                                                                crtc->primary->fb,
3194                                                                crtc->x,
3195                                                                crtc->y);
3196                 drm_modeset_unlock(&crtc->mutex);
3197         }
3198 }
3199
3200 void intel_prepare_reset(struct drm_device *dev)
3201 {
3202         /* no reset support for gen2 */
3203         if (IS_GEN2(dev))
3204                 return;
3205
3206         /* reset doesn't touch the display */
3207         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3208                 return;
3209
3210         drm_modeset_lock_all(dev);
3211         /*
3212          * Disabling the crtcs gracefully seems nicer. Also the
3213          * g33 docs say we should at least disable all the planes.
3214          */
3215         intel_display_suspend(dev);
3216 }
3217
3218 void intel_finish_reset(struct drm_device *dev)
3219 {
3220         struct drm_i915_private *dev_priv = to_i915(dev);
3221
3222         /*
3223          * Flips in the rings will be nuked by the reset,
3224          * so complete all pending flips so that user space
3225          * will get its events and not get stuck.
3226          */
3227         intel_complete_page_flips(dev);
3228
3229         /* no reset support for gen2 */
3230         if (IS_GEN2(dev))
3231                 return;
3232
3233         /* reset doesn't touch the display */
3234         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3235                 /*
3236                  * Flips in the rings have been nuked by the reset,
3237                  * so update the base address of all primary
3238                  * planes to the the last fb to make sure we're
3239                  * showing the correct fb after a reset.
3240                  */
3241                 intel_update_primary_planes(dev);
3242                 return;
3243         }
3244
3245         /*
3246          * The display has been reset as well,
3247          * so need a full re-initialization.
3248          */
3249         intel_runtime_pm_disable_interrupts(dev_priv);
3250         intel_runtime_pm_enable_interrupts(dev_priv);
3251
3252         intel_modeset_init_hw(dev);
3253
3254         spin_lock_irq(&dev_priv->irq_lock);
3255         if (dev_priv->display.hpd_irq_setup)
3256                 dev_priv->display.hpd_irq_setup(dev);
3257         spin_unlock_irq(&dev_priv->irq_lock);
3258
3259         intel_display_resume(dev);
3260
3261         intel_hpd_init(dev_priv);
3262
3263         drm_modeset_unlock_all(dev);
3264 }
3265
3266 static void
3267 intel_finish_fb(struct drm_framebuffer *old_fb)
3268 {
3269         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3270         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3271         bool was_interruptible = dev_priv->mm.interruptible;
3272         int ret;
3273
3274         /* Big Hammer, we also need to ensure that any pending
3275          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3276          * current scanout is retired before unpinning the old
3277          * framebuffer. Note that we rely on userspace rendering
3278          * into the buffer attached to the pipe they are waiting
3279          * on. If not, userspace generates a GPU hang with IPEHR
3280          * point to the MI_WAIT_FOR_EVENT.
3281          *
3282          * This should only fail upon a hung GPU, in which case we
3283          * can safely continue.
3284          */
3285         dev_priv->mm.interruptible = false;
3286         ret = i915_gem_object_wait_rendering(obj, true);
3287         dev_priv->mm.interruptible = was_interruptible;
3288
3289         WARN_ON(ret);
3290 }
3291
3292 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3297         bool pending;
3298
3299         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3300             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3301                 return false;
3302
3303         spin_lock_irq(&dev->event_lock);
3304         pending = to_intel_crtc(crtc)->unpin_work != NULL;
3305         spin_unlock_irq(&dev->event_lock);
3306
3307         return pending;
3308 }
3309
3310 static void intel_update_pipe_size(struct intel_crtc *crtc)
3311 {
3312         struct drm_device *dev = crtc->base.dev;
3313         struct drm_i915_private *dev_priv = dev->dev_private;
3314         const struct drm_display_mode *adjusted_mode;
3315
3316         if (!i915.fastboot)
3317                 return;
3318
3319         /*
3320          * Update pipe size and adjust fitter if needed: the reason for this is
3321          * that in compute_mode_changes we check the native mode (not the pfit
3322          * mode) to see if we can flip rather than do a full mode set. In the
3323          * fastboot case, we'll flip, but if we don't update the pipesrc and
3324          * pfit state, we'll end up with a big fb scanned out into the wrong
3325          * sized surface.
3326          *
3327          * To fix this properly, we need to hoist the checks up into
3328          * compute_mode_changes (or above), check the actual pfit state and
3329          * whether the platform allows pfit disable with pipe active, and only
3330          * then update the pipesrc and pfit state, even on the flip path.
3331          */
3332
3333         adjusted_mode = &crtc->config->base.adjusted_mode;
3334
3335         I915_WRITE(PIPESRC(crtc->pipe),
3336                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3337                    (adjusted_mode->crtc_vdisplay - 1));
3338         if (!crtc->config->pch_pfit.enabled &&
3339             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3340              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3341                 I915_WRITE(PF_CTL(crtc->pipe), 0);
3342                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3343                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3344         }
3345         crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3346         crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3347 }
3348
3349 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3350 {
3351         struct drm_device *dev = crtc->dev;
3352         struct drm_i915_private *dev_priv = dev->dev_private;
3353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354         int pipe = intel_crtc->pipe;
3355         u32 reg, temp;
3356
3357         /* enable normal train */
3358         reg = FDI_TX_CTL(pipe);
3359         temp = I915_READ(reg);
3360         if (IS_IVYBRIDGE(dev)) {
3361                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363         } else {
3364                 temp &= ~FDI_LINK_TRAIN_NONE;
3365                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366         }
3367         I915_WRITE(reg, temp);
3368
3369         reg = FDI_RX_CTL(pipe);
3370         temp = I915_READ(reg);
3371         if (HAS_PCH_CPT(dev)) {
3372                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374         } else {
3375                 temp &= ~FDI_LINK_TRAIN_NONE;
3376                 temp |= FDI_LINK_TRAIN_NONE;
3377         }
3378         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380         /* wait one idle pattern time */
3381         POSTING_READ(reg);
3382         udelay(1000);
3383
3384         /* IVB wants error correction enabled */
3385         if (IS_IVYBRIDGE(dev))
3386                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387                            FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396         int pipe = intel_crtc->pipe;
3397         u32 reg, temp, tries;
3398
3399         /* FDI needs bits from pipe first */
3400         assert_pipe_enabled(dev_priv, pipe);
3401
3402         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403            for train result */
3404         reg = FDI_RX_IMR(pipe);
3405         temp = I915_READ(reg);
3406         temp &= ~FDI_RX_SYMBOL_LOCK;
3407         temp &= ~FDI_RX_BIT_LOCK;
3408         I915_WRITE(reg, temp);
3409         I915_READ(reg);
3410         udelay(150);
3411
3412         /* enable CPU FDI TX and PCH FDI RX */
3413         reg = FDI_TX_CTL(pipe);
3414         temp = I915_READ(reg);
3415         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3416         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3417         temp &= ~FDI_LINK_TRAIN_NONE;
3418         temp |= FDI_LINK_TRAIN_PATTERN_1;
3419         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3420
3421         reg = FDI_RX_CTL(pipe);
3422         temp = I915_READ(reg);
3423         temp &= ~FDI_LINK_TRAIN_NONE;
3424         temp |= FDI_LINK_TRAIN_PATTERN_1;
3425         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427         POSTING_READ(reg);
3428         udelay(150);
3429
3430         /* Ironlake workaround, enable clock pointer after FDI enable*/
3431         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433                    FDI_RX_PHASE_SYNC_POINTER_EN);
3434
3435         reg = FDI_RX_IIR(pipe);
3436         for (tries = 0; tries < 5; tries++) {
3437                 temp = I915_READ(reg);
3438                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440                 if ((temp & FDI_RX_BIT_LOCK)) {
3441                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3442                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3443                         break;
3444                 }
3445         }
3446         if (tries == 5)
3447                 DRM_ERROR("FDI train 1 fail!\n");
3448
3449         /* Train 2 */
3450         reg = FDI_TX_CTL(pipe);
3451         temp = I915_READ(reg);
3452         temp &= ~FDI_LINK_TRAIN_NONE;
3453         temp |= FDI_LINK_TRAIN_PATTERN_2;
3454         I915_WRITE(reg, temp);
3455
3456         reg = FDI_RX_CTL(pipe);
3457         temp = I915_READ(reg);
3458         temp &= ~FDI_LINK_TRAIN_NONE;
3459         temp |= FDI_LINK_TRAIN_PATTERN_2;
3460         I915_WRITE(reg, temp);
3461
3462         POSTING_READ(reg);
3463         udelay(150);
3464
3465         reg = FDI_RX_IIR(pipe);
3466         for (tries = 0; tries < 5; tries++) {
3467                 temp = I915_READ(reg);
3468                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470                 if (temp & FDI_RX_SYMBOL_LOCK) {
3471                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3472                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3473                         break;
3474                 }
3475         }
3476         if (tries == 5)
3477                 DRM_ERROR("FDI train 2 fail!\n");
3478
3479         DRM_DEBUG_KMS("FDI train done\n");
3480
3481 }
3482
3483 static const int snb_b_fdi_train_param[] = {
3484         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488 };
3489
3490 /* The FDI link training functions for SNB/Cougarpoint. */
3491 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492 {
3493         struct drm_device *dev = crtc->dev;
3494         struct drm_i915_private *dev_priv = dev->dev_private;
3495         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496         int pipe = intel_crtc->pipe;
3497         u32 reg, temp, i, retry;
3498
3499         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3500            for train result */
3501         reg = FDI_RX_IMR(pipe);
3502         temp = I915_READ(reg);
3503         temp &= ~FDI_RX_SYMBOL_LOCK;
3504         temp &= ~FDI_RX_BIT_LOCK;
3505         I915_WRITE(reg, temp);
3506
3507         POSTING_READ(reg);
3508         udelay(150);
3509
3510         /* enable CPU FDI TX and PCH FDI RX */
3511         reg = FDI_TX_CTL(pipe);
3512         temp = I915_READ(reg);
3513         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3514         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3515         temp &= ~FDI_LINK_TRAIN_NONE;
3516         temp |= FDI_LINK_TRAIN_PATTERN_1;
3517         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518         /* SNB-B */
3519         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3520         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3521
3522         I915_WRITE(FDI_RX_MISC(pipe),
3523                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3524
3525         reg = FDI_RX_CTL(pipe);
3526         temp = I915_READ(reg);
3527         if (HAS_PCH_CPT(dev)) {
3528                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3529                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3530         } else {
3531                 temp &= ~FDI_LINK_TRAIN_NONE;
3532                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3533         }
3534         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3535
3536         POSTING_READ(reg);
3537         udelay(150);
3538
3539         for (i = 0; i < 4; i++) {
3540                 reg = FDI_TX_CTL(pipe);
3541                 temp = I915_READ(reg);
3542                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3543                 temp |= snb_b_fdi_train_param[i];
3544                 I915_WRITE(reg, temp);
3545
3546                 POSTING_READ(reg);
3547                 udelay(500);
3548
3549                 for (retry = 0; retry < 5; retry++) {
3550                         reg = FDI_RX_IIR(pipe);
3551                         temp = I915_READ(reg);
3552                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3553                         if (temp & FDI_RX_BIT_LOCK) {
3554                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3555                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3556                                 break;
3557                         }
3558                         udelay(50);
3559                 }
3560                 if (retry < 5)
3561                         break;
3562         }
3563         if (i == 4)
3564                 DRM_ERROR("FDI train 1 fail!\n");
3565
3566         /* Train 2 */
3567         reg = FDI_TX_CTL(pipe);
3568         temp = I915_READ(reg);
3569         temp &= ~FDI_LINK_TRAIN_NONE;
3570         temp |= FDI_LINK_TRAIN_PATTERN_2;
3571         if (IS_GEN6(dev)) {
3572                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3573                 /* SNB-B */
3574                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3575         }
3576         I915_WRITE(reg, temp);
3577
3578         reg = FDI_RX_CTL(pipe);
3579         temp = I915_READ(reg);
3580         if (HAS_PCH_CPT(dev)) {
3581                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3582                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3583         } else {
3584                 temp &= ~FDI_LINK_TRAIN_NONE;
3585                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586         }
3587         I915_WRITE(reg, temp);
3588
3589         POSTING_READ(reg);
3590         udelay(150);
3591
3592         for (i = 0; i < 4; i++) {
3593                 reg = FDI_TX_CTL(pipe);
3594                 temp = I915_READ(reg);
3595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3596                 temp |= snb_b_fdi_train_param[i];
3597                 I915_WRITE(reg, temp);
3598
3599                 POSTING_READ(reg);
3600                 udelay(500);
3601
3602                 for (retry = 0; retry < 5; retry++) {
3603                         reg = FDI_RX_IIR(pipe);
3604                         temp = I915_READ(reg);
3605                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3606                         if (temp & FDI_RX_SYMBOL_LOCK) {
3607                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3608                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3609                                 break;
3610                         }
3611                         udelay(50);
3612                 }
3613                 if (retry < 5)
3614                         break;
3615         }
3616         if (i == 4)
3617                 DRM_ERROR("FDI train 2 fail!\n");
3618
3619         DRM_DEBUG_KMS("FDI train done.\n");
3620 }
3621
3622 /* Manual link training for Ivy Bridge A0 parts */
3623 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3624 {
3625         struct drm_device *dev = crtc->dev;
3626         struct drm_i915_private *dev_priv = dev->dev_private;
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628         int pipe = intel_crtc->pipe;
3629         u32 reg, temp, i, j;
3630
3631         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3632            for train result */
3633         reg = FDI_RX_IMR(pipe);
3634         temp = I915_READ(reg);
3635         temp &= ~FDI_RX_SYMBOL_LOCK;
3636         temp &= ~FDI_RX_BIT_LOCK;
3637         I915_WRITE(reg, temp);
3638
3639         POSTING_READ(reg);
3640         udelay(150);
3641
3642         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3643                       I915_READ(FDI_RX_IIR(pipe)));
3644
3645         /* Try each vswing and preemphasis setting twice before moving on */
3646         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3647                 /* disable first in case we need to retry */
3648                 reg = FDI_TX_CTL(pipe);
3649                 temp = I915_READ(reg);
3650                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3651                 temp &= ~FDI_TX_ENABLE;
3652                 I915_WRITE(reg, temp);
3653
3654                 reg = FDI_RX_CTL(pipe);
3655                 temp = I915_READ(reg);
3656                 temp &= ~FDI_LINK_TRAIN_AUTO;
3657                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3658                 temp &= ~FDI_RX_ENABLE;
3659                 I915_WRITE(reg, temp);
3660
3661                 /* enable CPU FDI TX and PCH FDI RX */
3662                 reg = FDI_TX_CTL(pipe);
3663                 temp = I915_READ(reg);
3664                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3665                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3666                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3667                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3668                 temp |= snb_b_fdi_train_param[j/2];
3669                 temp |= FDI_COMPOSITE_SYNC;
3670                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3671
3672                 I915_WRITE(FDI_RX_MISC(pipe),
3673                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3674
3675                 reg = FDI_RX_CTL(pipe);
3676                 temp = I915_READ(reg);
3677                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3678                 temp |= FDI_COMPOSITE_SYNC;
3679                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3680
3681                 POSTING_READ(reg);
3682                 udelay(1); /* should be 0.5us */
3683
3684                 for (i = 0; i < 4; i++) {
3685                         reg = FDI_RX_IIR(pipe);
3686                         temp = I915_READ(reg);
3687                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3688
3689                         if (temp & FDI_RX_BIT_LOCK ||
3690                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3691                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3692                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3693                                               i);
3694                                 break;
3695                         }
3696                         udelay(1); /* should be 0.5us */
3697                 }
3698                 if (i == 4) {
3699                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3700                         continue;
3701                 }
3702
3703                 /* Train 2 */
3704                 reg = FDI_TX_CTL(pipe);
3705                 temp = I915_READ(reg);
3706                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3707                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3708                 I915_WRITE(reg, temp);
3709
3710                 reg = FDI_RX_CTL(pipe);
3711                 temp = I915_READ(reg);
3712                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3713                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3714                 I915_WRITE(reg, temp);
3715
3716                 POSTING_READ(reg);
3717                 udelay(2); /* should be 1.5us */
3718
3719                 for (i = 0; i < 4; i++) {
3720                         reg = FDI_RX_IIR(pipe);
3721                         temp = I915_READ(reg);
3722                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3723
3724                         if (temp & FDI_RX_SYMBOL_LOCK ||
3725                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3726                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3727                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3728                                               i);
3729                                 goto train_done;
3730                         }
3731                         udelay(2); /* should be 1.5us */
3732                 }
3733                 if (i == 4)
3734                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3735         }
3736
3737 train_done:
3738         DRM_DEBUG_KMS("FDI train done.\n");
3739 }
3740
3741 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3742 {
3743         struct drm_device *dev = intel_crtc->base.dev;
3744         struct drm_i915_private *dev_priv = dev->dev_private;
3745         int pipe = intel_crtc->pipe;
3746         u32 reg, temp;
3747
3748
3749         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3750         reg = FDI_RX_CTL(pipe);
3751         temp = I915_READ(reg);
3752         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3753         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3754         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3755         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3756
3757         POSTING_READ(reg);
3758         udelay(200);
3759
3760         /* Switch from Rawclk to PCDclk */
3761         temp = I915_READ(reg);
3762         I915_WRITE(reg, temp | FDI_PCDCLK);
3763
3764         POSTING_READ(reg);
3765         udelay(200);
3766
3767         /* Enable CPU FDI TX PLL, always on for Ironlake */
3768         reg = FDI_TX_CTL(pipe);
3769         temp = I915_READ(reg);
3770         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3771                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3772
3773                 POSTING_READ(reg);
3774                 udelay(100);
3775         }
3776 }
3777
3778 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3779 {
3780         struct drm_device *dev = intel_crtc->base.dev;
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         int pipe = intel_crtc->pipe;
3783         u32 reg, temp;
3784
3785         /* Switch from PCDclk to Rawclk */
3786         reg = FDI_RX_CTL(pipe);
3787         temp = I915_READ(reg);
3788         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3789
3790         /* Disable CPU FDI TX PLL */
3791         reg = FDI_TX_CTL(pipe);
3792         temp = I915_READ(reg);
3793         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3794
3795         POSTING_READ(reg);
3796         udelay(100);
3797
3798         reg = FDI_RX_CTL(pipe);
3799         temp = I915_READ(reg);
3800         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3801
3802         /* Wait for the clocks to turn off. */
3803         POSTING_READ(reg);
3804         udelay(100);
3805 }
3806
3807 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3808 {
3809         struct drm_device *dev = crtc->dev;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812         int pipe = intel_crtc->pipe;
3813         u32 reg, temp;
3814
3815         /* disable CPU FDI tx and PCH FDI rx */
3816         reg = FDI_TX_CTL(pipe);
3817         temp = I915_READ(reg);
3818         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3819         POSTING_READ(reg);
3820
3821         reg = FDI_RX_CTL(pipe);
3822         temp = I915_READ(reg);
3823         temp &= ~(0x7 << 16);
3824         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3825         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3826
3827         POSTING_READ(reg);
3828         udelay(100);
3829
3830         /* Ironlake workaround, disable clock pointer after downing FDI */
3831         if (HAS_PCH_IBX(dev))
3832                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3833
3834         /* still set train pattern 1 */
3835         reg = FDI_TX_CTL(pipe);
3836         temp = I915_READ(reg);
3837         temp &= ~FDI_LINK_TRAIN_NONE;
3838         temp |= FDI_LINK_TRAIN_PATTERN_1;
3839         I915_WRITE(reg, temp);
3840
3841         reg = FDI_RX_CTL(pipe);
3842         temp = I915_READ(reg);
3843         if (HAS_PCH_CPT(dev)) {
3844                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3845                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3846         } else {
3847                 temp &= ~FDI_LINK_TRAIN_NONE;
3848                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3849         }
3850         /* BPC in FDI rx is consistent with that in PIPECONF */
3851         temp &= ~(0x07 << 16);
3852         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3853         I915_WRITE(reg, temp);
3854
3855         POSTING_READ(reg);
3856         udelay(100);
3857 }
3858
3859 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3860 {
3861         struct intel_crtc *crtc;
3862
3863         /* Note that we don't need to be called with mode_config.lock here
3864          * as our list of CRTC objects is static for the lifetime of the
3865          * device and so cannot disappear as we iterate. Similarly, we can
3866          * happily treat the predicates as racy, atomic checks as userspace
3867          * cannot claim and pin a new fb without at least acquring the
3868          * struct_mutex and so serialising with us.
3869          */
3870         for_each_intel_crtc(dev, crtc) {
3871                 if (atomic_read(&crtc->unpin_work_count) == 0)
3872                         continue;
3873
3874                 if (crtc->unpin_work)
3875                         intel_wait_for_vblank(dev, crtc->pipe);
3876
3877                 return true;
3878         }
3879
3880         return false;
3881 }
3882
3883 static void page_flip_completed(struct intel_crtc *intel_crtc)
3884 {
3885         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3886         struct intel_unpin_work *work = intel_crtc->unpin_work;
3887
3888         /* ensure that the unpin work is consistent wrt ->pending. */
3889         smp_rmb();
3890         intel_crtc->unpin_work = NULL;
3891
3892         if (work->event)
3893                 drm_send_vblank_event(intel_crtc->base.dev,
3894                                       intel_crtc->pipe,
3895                                       work->event);
3896
3897         drm_crtc_vblank_put(&intel_crtc->base);
3898
3899         wake_up_all(&dev_priv->pending_flip_queue);
3900         queue_work(dev_priv->wq, &work->work);
3901
3902         trace_i915_flip_complete(intel_crtc->plane,
3903                                  work->pending_flip_obj);
3904 }
3905
3906 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3907 {
3908         struct drm_device *dev = crtc->dev;
3909         struct drm_i915_private *dev_priv = dev->dev_private;
3910
3911         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3912         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3913                                        !intel_crtc_has_pending_flip(crtc),
3914                                        60*HZ) == 0)) {
3915                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916
3917                 spin_lock_irq(&dev->event_lock);
3918                 if (intel_crtc->unpin_work) {
3919                         WARN_ONCE(1, "Removing stuck page flip\n");
3920                         page_flip_completed(intel_crtc);
3921                 }
3922                 spin_unlock_irq(&dev->event_lock);
3923         }
3924
3925         if (crtc->primary->fb) {
3926                 mutex_lock(&dev->struct_mutex);
3927                 intel_finish_fb(crtc->primary->fb);
3928                 mutex_unlock(&dev->struct_mutex);
3929         }
3930 }
3931
3932 /* Program iCLKIP clock to the desired frequency */
3933 static void lpt_program_iclkip(struct drm_crtc *crtc)
3934 {
3935         struct drm_device *dev = crtc->dev;
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3938         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3939         u32 temp;
3940
3941         mutex_lock(&dev_priv->sb_lock);
3942
3943         /* It is necessary to ungate the pixclk gate prior to programming
3944          * the divisors, and gate it back when it is done.
3945          */
3946         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3947
3948         /* Disable SSCCTL */
3949         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3950                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3951                                 SBI_SSCCTL_DISABLE,
3952                         SBI_ICLK);
3953
3954         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3955         if (clock == 20000) {
3956                 auxdiv = 1;
3957                 divsel = 0x41;
3958                 phaseinc = 0x20;
3959         } else {
3960                 /* The iCLK virtual clock root frequency is in MHz,
3961                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3962                  * divisors, it is necessary to divide one by another, so we
3963                  * convert the virtual clock precision to KHz here for higher
3964                  * precision.
3965                  */
3966                 u32 iclk_virtual_root_freq = 172800 * 1000;
3967                 u32 iclk_pi_range = 64;
3968                 u32 desired_divisor, msb_divisor_value, pi_value;
3969
3970                 desired_divisor = (iclk_virtual_root_freq / clock);
3971                 msb_divisor_value = desired_divisor / iclk_pi_range;
3972                 pi_value = desired_divisor % iclk_pi_range;
3973
3974                 auxdiv = 0;
3975                 divsel = msb_divisor_value - 2;
3976                 phaseinc = pi_value;
3977         }
3978
3979         /* This should not happen with any sane values */
3980         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3981                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3982         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3983                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3984
3985         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3986                         clock,
3987                         auxdiv,
3988                         divsel,
3989                         phasedir,
3990                         phaseinc);
3991
3992         /* Program SSCDIVINTPHASE6 */
3993         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3994         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3995         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3996         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3997         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3998         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3999         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4000         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4001
4002         /* Program SSCAUXDIV */
4003         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4004         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4005         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4006         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4007
4008         /* Enable modulator and associated divider */
4009         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4010         temp &= ~SBI_SSCCTL_DISABLE;
4011         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4012
4013         /* Wait for initialization time */
4014         udelay(24);
4015
4016         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4017
4018         mutex_unlock(&dev_priv->sb_lock);
4019 }
4020
4021 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4022                                                 enum pipe pch_transcoder)
4023 {
4024         struct drm_device *dev = crtc->base.dev;
4025         struct drm_i915_private *dev_priv = dev->dev_private;
4026         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4027
4028         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4029                    I915_READ(HTOTAL(cpu_transcoder)));
4030         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4031                    I915_READ(HBLANK(cpu_transcoder)));
4032         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4033                    I915_READ(HSYNC(cpu_transcoder)));
4034
4035         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4036                    I915_READ(VTOTAL(cpu_transcoder)));
4037         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4038                    I915_READ(VBLANK(cpu_transcoder)));
4039         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4040                    I915_READ(VSYNC(cpu_transcoder)));
4041         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4042                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4043 }
4044
4045 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4046 {
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         uint32_t temp;
4049
4050         temp = I915_READ(SOUTH_CHICKEN1);
4051         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4052                 return;
4053
4054         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4055         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4056
4057         temp &= ~FDI_BC_BIFURCATION_SELECT;
4058         if (enable)
4059                 temp |= FDI_BC_BIFURCATION_SELECT;
4060
4061         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4062         I915_WRITE(SOUTH_CHICKEN1, temp);
4063         POSTING_READ(SOUTH_CHICKEN1);
4064 }
4065
4066 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4067 {
4068         struct drm_device *dev = intel_crtc->base.dev;
4069
4070         switch (intel_crtc->pipe) {
4071         case PIPE_A:
4072                 break;
4073         case PIPE_B:
4074                 if (intel_crtc->config->fdi_lanes > 2)
4075                         cpt_set_fdi_bc_bifurcation(dev, false);
4076                 else
4077                         cpt_set_fdi_bc_bifurcation(dev, true);
4078
4079                 break;
4080         case PIPE_C:
4081                 cpt_set_fdi_bc_bifurcation(dev, true);
4082
4083                 break;
4084         default:
4085                 BUG();
4086         }
4087 }
4088
4089 /*
4090  * Enable PCH resources required for PCH ports:
4091  *   - PCH PLLs
4092  *   - FDI training & RX/TX
4093  *   - update transcoder timings
4094  *   - DP transcoding bits
4095  *   - transcoder
4096  */
4097 static void ironlake_pch_enable(struct drm_crtc *crtc)
4098 {
4099         struct drm_device *dev = crtc->dev;
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102         int pipe = intel_crtc->pipe;
4103         u32 reg, temp;
4104
4105         assert_pch_transcoder_disabled(dev_priv, pipe);
4106
4107         if (IS_IVYBRIDGE(dev))
4108                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4109
4110         /* Write the TU size bits before fdi link training, so that error
4111          * detection works. */
4112         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4113                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4114
4115         /* For PCH output, training FDI link */
4116         dev_priv->display.fdi_link_train(crtc);
4117
4118         /* We need to program the right clock selection before writing the pixel
4119          * mutliplier into the DPLL. */
4120         if (HAS_PCH_CPT(dev)) {
4121                 u32 sel;
4122
4123                 temp = I915_READ(PCH_DPLL_SEL);
4124                 temp |= TRANS_DPLL_ENABLE(pipe);
4125                 sel = TRANS_DPLLB_SEL(pipe);
4126                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4127                         temp |= sel;
4128                 else
4129                         temp &= ~sel;
4130                 I915_WRITE(PCH_DPLL_SEL, temp);
4131         }
4132
4133         /* XXX: pch pll's can be enabled any time before we enable the PCH
4134          * transcoder, and we actually should do this to not upset any PCH
4135          * transcoder that already use the clock when we share it.
4136          *
4137          * Note that enable_shared_dpll tries to do the right thing, but
4138          * get_shared_dpll unconditionally resets the pll - we need that to have
4139          * the right LVDS enable sequence. */
4140         intel_enable_shared_dpll(intel_crtc);
4141
4142         /* set transcoder timing, panel must allow it */
4143         assert_panel_unlocked(dev_priv, pipe);
4144         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4145
4146         intel_fdi_normal_train(crtc);
4147
4148         /* For PCH DP, enable TRANS_DP_CTL */
4149         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4150                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4151                 reg = TRANS_DP_CTL(pipe);
4152                 temp = I915_READ(reg);
4153                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4154                           TRANS_DP_SYNC_MASK |
4155                           TRANS_DP_BPC_MASK);
4156                 temp |= TRANS_DP_OUTPUT_ENABLE;
4157                 temp |= bpc << 9; /* same format but at 11:9 */
4158
4159                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4160                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4161                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4162                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4163
4164                 switch (intel_trans_dp_port_sel(crtc)) {
4165                 case PCH_DP_B:
4166                         temp |= TRANS_DP_PORT_SEL_B;
4167                         break;
4168                 case PCH_DP_C:
4169                         temp |= TRANS_DP_PORT_SEL_C;
4170                         break;
4171                 case PCH_DP_D:
4172                         temp |= TRANS_DP_PORT_SEL_D;
4173                         break;
4174                 default:
4175                         BUG();
4176                 }
4177
4178                 I915_WRITE(reg, temp);
4179         }
4180
4181         ironlake_enable_pch_transcoder(dev_priv, pipe);
4182 }
4183
4184 static void lpt_pch_enable(struct drm_crtc *crtc)
4185 {
4186         struct drm_device *dev = crtc->dev;
4187         struct drm_i915_private *dev_priv = dev->dev_private;
4188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4190
4191         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4192
4193         lpt_program_iclkip(crtc);
4194
4195         /* Set transcoder timing. */
4196         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4197
4198         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4199 }
4200
4201 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4202                                                 struct intel_crtc_state *crtc_state)
4203 {
4204         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4205         struct intel_shared_dpll *pll;
4206         struct intel_shared_dpll_config *shared_dpll;
4207         enum intel_dpll_id i;
4208
4209         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4210
4211         if (HAS_PCH_IBX(dev_priv->dev)) {
4212                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4213                 i = (enum intel_dpll_id) crtc->pipe;
4214                 pll = &dev_priv->shared_dplls[i];
4215
4216                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4217                               crtc->base.base.id, pll->name);
4218
4219                 WARN_ON(shared_dpll[i].crtc_mask);
4220
4221                 goto found;
4222         }
4223
4224         if (IS_BROXTON(dev_priv->dev)) {
4225                 /* PLL is attached to port in bxt */
4226                 struct intel_encoder *encoder;
4227                 struct intel_digital_port *intel_dig_port;
4228
4229                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4230                 if (WARN_ON(!encoder))
4231                         return NULL;
4232
4233                 intel_dig_port = enc_to_dig_port(&encoder->base);
4234                 /* 1:1 mapping between ports and PLLs */
4235                 i = (enum intel_dpll_id)intel_dig_port->port;
4236                 pll = &dev_priv->shared_dplls[i];
4237                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4238                         crtc->base.base.id, pll->name);
4239                 WARN_ON(shared_dpll[i].crtc_mask);
4240
4241                 goto found;
4242         }
4243
4244         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245                 pll = &dev_priv->shared_dplls[i];
4246
4247                 /* Only want to check enabled timings first */
4248                 if (shared_dpll[i].crtc_mask == 0)
4249                         continue;
4250
4251                 if (memcmp(&crtc_state->dpll_hw_state,
4252                            &shared_dpll[i].hw_state,
4253                            sizeof(crtc_state->dpll_hw_state)) == 0) {
4254                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4255                                       crtc->base.base.id, pll->name,
4256                                       shared_dpll[i].crtc_mask,
4257                                       pll->active);
4258                         goto found;
4259                 }
4260         }
4261
4262         /* Ok no matching timings, maybe there's a free one? */
4263         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264                 pll = &dev_priv->shared_dplls[i];
4265                 if (shared_dpll[i].crtc_mask == 0) {
4266                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4267                                       crtc->base.base.id, pll->name);
4268                         goto found;
4269                 }
4270         }
4271
4272         return NULL;
4273
4274 found:
4275         if (shared_dpll[i].crtc_mask == 0)
4276                 shared_dpll[i].hw_state =
4277                         crtc_state->dpll_hw_state;
4278
4279         crtc_state->shared_dpll = i;
4280         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4281                          pipe_name(crtc->pipe));
4282
4283         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4284
4285         return pll;
4286 }
4287
4288 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4289 {
4290         struct drm_i915_private *dev_priv = to_i915(state->dev);
4291         struct intel_shared_dpll_config *shared_dpll;
4292         struct intel_shared_dpll *pll;
4293         enum intel_dpll_id i;
4294
4295         if (!to_intel_atomic_state(state)->dpll_set)
4296                 return;
4297
4298         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4299         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4300                 pll = &dev_priv->shared_dplls[i];
4301                 pll->config = shared_dpll[i];
4302         }
4303 }
4304
4305 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         int dslreg = PIPEDSL(pipe);
4309         u32 temp;
4310
4311         temp = I915_READ(dslreg);
4312         udelay(500);
4313         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4314                 if (wait_for(I915_READ(dslreg) != temp, 5))
4315                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4316         }
4317 }
4318
4319 static int
4320 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4321                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4322                   int src_w, int src_h, int dst_w, int dst_h)
4323 {
4324         struct intel_crtc_scaler_state *scaler_state =
4325                 &crtc_state->scaler_state;
4326         struct intel_crtc *intel_crtc =
4327                 to_intel_crtc(crtc_state->base.crtc);
4328         int need_scaling;
4329
4330         need_scaling = intel_rotation_90_or_270(rotation) ?
4331                 (src_h != dst_w || src_w != dst_h):
4332                 (src_w != dst_w || src_h != dst_h);
4333
4334         /*
4335          * if plane is being disabled or scaler is no more required or force detach
4336          *  - free scaler binded to this plane/crtc
4337          *  - in order to do this, update crtc->scaler_usage
4338          *
4339          * Here scaler state in crtc_state is set free so that
4340          * scaler can be assigned to other user. Actual register
4341          * update to free the scaler is done in plane/panel-fit programming.
4342          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4343          */
4344         if (force_detach || !need_scaling) {
4345                 if (*scaler_id >= 0) {
4346                         scaler_state->scaler_users &= ~(1 << scaler_user);
4347                         scaler_state->scalers[*scaler_id].in_use = 0;
4348
4349                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4350                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4351                                 intel_crtc->pipe, scaler_user, *scaler_id,
4352                                 scaler_state->scaler_users);
4353                         *scaler_id = -1;
4354                 }
4355                 return 0;
4356         }
4357
4358         /* range checks */
4359         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4360                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4361
4362                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4363                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4364                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4365                         "size is out of scaler range\n",
4366                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4367                 return -EINVAL;
4368         }
4369
4370         /* mark this plane as a scaler user in crtc_state */
4371         scaler_state->scaler_users |= (1 << scaler_user);
4372         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4373                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4374                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4375                 scaler_state->scaler_users);
4376
4377         return 0;
4378 }
4379
4380 /**
4381  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4382  *
4383  * @state: crtc's scaler state
4384  *
4385  * Return
4386  *     0 - scaler_usage updated successfully
4387  *    error - requested scaling cannot be supported or other error condition
4388  */
4389 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4390 {
4391         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4392         struct drm_display_mode *adjusted_mode =
4393                 &state->base.adjusted_mode;
4394
4395         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4396                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4397
4398         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4399                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4400                 state->pipe_src_w, state->pipe_src_h,
4401                 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4402 }
4403
4404 /**
4405  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4406  *
4407  * @state: crtc's scaler state
4408  * @plane_state: atomic plane state to update
4409  *
4410  * Return
4411  *     0 - scaler_usage updated successfully
4412  *    error - requested scaling cannot be supported or other error condition
4413  */
4414 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4415                                    struct intel_plane_state *plane_state)
4416 {
4417
4418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4419         struct intel_plane *intel_plane =
4420                 to_intel_plane(plane_state->base.plane);
4421         struct drm_framebuffer *fb = plane_state->base.fb;
4422         int ret;
4423
4424         bool force_detach = !fb || !plane_state->visible;
4425
4426         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4427                       intel_plane->base.base.id, intel_crtc->pipe,
4428                       drm_plane_index(&intel_plane->base));
4429
4430         ret = skl_update_scaler(crtc_state, force_detach,
4431                                 drm_plane_index(&intel_plane->base),
4432                                 &plane_state->scaler_id,
4433                                 plane_state->base.rotation,
4434                                 drm_rect_width(&plane_state->src) >> 16,
4435                                 drm_rect_height(&plane_state->src) >> 16,
4436                                 drm_rect_width(&plane_state->dst),
4437                                 drm_rect_height(&plane_state->dst));
4438
4439         if (ret || plane_state->scaler_id < 0)
4440                 return ret;
4441
4442         /* check colorkey */
4443         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4444                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4445                               intel_plane->base.base.id);
4446                 return -EINVAL;
4447         }
4448
4449         /* Check src format */
4450         switch (fb->pixel_format) {
4451         case DRM_FORMAT_RGB565:
4452         case DRM_FORMAT_XBGR8888:
4453         case DRM_FORMAT_XRGB8888:
4454         case DRM_FORMAT_ABGR8888:
4455         case DRM_FORMAT_ARGB8888:
4456         case DRM_FORMAT_XRGB2101010:
4457         case DRM_FORMAT_XBGR2101010:
4458         case DRM_FORMAT_YUYV:
4459         case DRM_FORMAT_YVYU:
4460         case DRM_FORMAT_UYVY:
4461         case DRM_FORMAT_VYUY:
4462                 break;
4463         default:
4464                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4465                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4466                 return -EINVAL;
4467         }
4468
4469         return 0;
4470 }
4471
4472 static void skylake_scaler_disable(struct intel_crtc *crtc)
4473 {
4474         int i;
4475
4476         for (i = 0; i < crtc->num_scalers; i++)
4477                 skl_detach_scaler(crtc, i);
4478 }
4479
4480 static void skylake_pfit_enable(struct intel_crtc *crtc)
4481 {
4482         struct drm_device *dev = crtc->base.dev;
4483         struct drm_i915_private *dev_priv = dev->dev_private;
4484         int pipe = crtc->pipe;
4485         struct intel_crtc_scaler_state *scaler_state =
4486                 &crtc->config->scaler_state;
4487
4488         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4489
4490         if (crtc->config->pch_pfit.enabled) {
4491                 int id;
4492
4493                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4494                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4495                         return;
4496                 }
4497
4498                 id = scaler_state->scaler_id;
4499                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4500                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4501                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4502                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4503
4504                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4505         }
4506 }
4507
4508 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4509 {
4510         struct drm_device *dev = crtc->base.dev;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         int pipe = crtc->pipe;
4513
4514         if (crtc->config->pch_pfit.enabled) {
4515                 /* Force use of hard-coded filter coefficients
4516                  * as some pre-programmed values are broken,
4517                  * e.g. x201.
4518                  */
4519                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4520                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4521                                                  PF_PIPE_SEL_IVB(pipe));
4522                 else
4523                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4524                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4525                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4526         }
4527 }
4528
4529 void hsw_enable_ips(struct intel_crtc *crtc)
4530 {
4531         struct drm_device *dev = crtc->base.dev;
4532         struct drm_i915_private *dev_priv = dev->dev_private;
4533
4534         if (!crtc->config->ips_enabled)
4535                 return;
4536
4537         /* We can only enable IPS after we enable a plane and wait for a vblank */
4538         intel_wait_for_vblank(dev, crtc->pipe);
4539
4540         assert_plane_enabled(dev_priv, crtc->plane);
4541         if (IS_BROADWELL(dev)) {
4542                 mutex_lock(&dev_priv->rps.hw_lock);
4543                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4544                 mutex_unlock(&dev_priv->rps.hw_lock);
4545                 /* Quoting Art Runyan: "its not safe to expect any particular
4546                  * value in IPS_CTL bit 31 after enabling IPS through the
4547                  * mailbox." Moreover, the mailbox may return a bogus state,
4548                  * so we need to just enable it and continue on.
4549                  */
4550         } else {
4551                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4552                 /* The bit only becomes 1 in the next vblank, so this wait here
4553                  * is essentially intel_wait_for_vblank. If we don't have this
4554                  * and don't wait for vblanks until the end of crtc_enable, then
4555                  * the HW state readout code will complain that the expected
4556                  * IPS_CTL value is not the one we read. */
4557                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4558                         DRM_ERROR("Timed out waiting for IPS enable\n");
4559         }
4560 }
4561
4562 void hsw_disable_ips(struct intel_crtc *crtc)
4563 {
4564         struct drm_device *dev = crtc->base.dev;
4565         struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567         if (!crtc->config->ips_enabled)
4568                 return;
4569
4570         assert_plane_enabled(dev_priv, crtc->plane);
4571         if (IS_BROADWELL(dev)) {
4572                 mutex_lock(&dev_priv->rps.hw_lock);
4573                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4574                 mutex_unlock(&dev_priv->rps.hw_lock);
4575                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4576                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4577                         DRM_ERROR("Timed out waiting for IPS disable\n");
4578         } else {
4579                 I915_WRITE(IPS_CTL, 0);
4580                 POSTING_READ(IPS_CTL);
4581         }
4582
4583         /* We need to wait for a vblank before we can disable the plane. */
4584         intel_wait_for_vblank(dev, crtc->pipe);
4585 }
4586
4587 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4588 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4589 {
4590         struct drm_device *dev = crtc->dev;
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593         enum pipe pipe = intel_crtc->pipe;
4594         int palreg = PALETTE(pipe);
4595         int i;
4596         bool reenable_ips = false;
4597
4598         /* The clocks have to be on to load the palette. */
4599         if (!crtc->state->active)
4600                 return;
4601
4602         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4603                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4604                         assert_dsi_pll_enabled(dev_priv);
4605                 else
4606                         assert_pll_enabled(dev_priv, pipe);
4607         }
4608
4609         /* use legacy palette for Ironlake */
4610         if (!HAS_GMCH_DISPLAY(dev))
4611                 palreg = LGC_PALETTE(pipe);
4612
4613         /* Workaround : Do not read or write the pipe palette/gamma data while
4614          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4615          */
4616         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4617             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4618              GAMMA_MODE_MODE_SPLIT)) {
4619                 hsw_disable_ips(intel_crtc);
4620                 reenable_ips = true;
4621         }
4622
4623         for (i = 0; i < 256; i++) {
4624                 I915_WRITE(palreg + 4 * i,
4625                            (intel_crtc->lut_r[i] << 16) |
4626                            (intel_crtc->lut_g[i] << 8) |
4627                            intel_crtc->lut_b[i]);
4628         }
4629
4630         if (reenable_ips)
4631                 hsw_enable_ips(intel_crtc);
4632 }
4633
4634 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4635 {
4636         if (intel_crtc->overlay) {
4637                 struct drm_device *dev = intel_crtc->base.dev;
4638                 struct drm_i915_private *dev_priv = dev->dev_private;
4639
4640                 mutex_lock(&dev->struct_mutex);
4641                 dev_priv->mm.interruptible = false;
4642                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4643                 dev_priv->mm.interruptible = true;
4644                 mutex_unlock(&dev->struct_mutex);
4645         }
4646
4647         /* Let userspace switch the overlay on again. In most cases userspace
4648          * has to recompute where to put it anyway.
4649          */
4650 }
4651
4652 /**
4653  * intel_post_enable_primary - Perform operations after enabling primary plane
4654  * @crtc: the CRTC whose primary plane was just enabled
4655  *
4656  * Performs potentially sleeping operations that must be done after the primary
4657  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4658  * called due to an explicit primary plane update, or due to an implicit
4659  * re-enable that is caused when a sprite plane is updated to no longer
4660  * completely hide the primary plane.
4661  */
4662 static void
4663 intel_post_enable_primary(struct drm_crtc *crtc)
4664 {
4665         struct drm_device *dev = crtc->dev;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668         int pipe = intel_crtc->pipe;
4669
4670         /*
4671          * BDW signals flip done immediately if the plane
4672          * is disabled, even if the plane enable is already
4673          * armed to occur at the next vblank :(
4674          */
4675         if (IS_BROADWELL(dev))
4676                 intel_wait_for_vblank(dev, pipe);
4677
4678         /*
4679          * FIXME IPS should be fine as long as one plane is
4680          * enabled, but in practice it seems to have problems
4681          * when going from primary only to sprite only and vice
4682          * versa.
4683          */
4684         hsw_enable_ips(intel_crtc);
4685
4686         /*
4687          * Gen2 reports pipe underruns whenever all planes are disabled.
4688          * So don't enable underrun reporting before at least some planes
4689          * are enabled.
4690          * FIXME: Need to fix the logic to work when we turn off all planes
4691          * but leave the pipe running.
4692          */
4693         if (IS_GEN2(dev))
4694                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4695
4696         /* Underruns don't raise interrupts, so check manually. */
4697         if (HAS_GMCH_DISPLAY(dev))
4698                 i9xx_check_fifo_underruns(dev_priv);
4699 }
4700
4701 /**
4702  * intel_pre_disable_primary - Perform operations before disabling primary plane
4703  * @crtc: the CRTC whose primary plane is to be disabled
4704  *
4705  * Performs potentially sleeping operations that must be done before the
4706  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
4707  * be called due to an explicit primary plane update, or due to an implicit
4708  * disable that is caused when a sprite plane completely hides the primary
4709  * plane.
4710  */
4711 static void
4712 intel_pre_disable_primary(struct drm_crtc *crtc)
4713 {
4714         struct drm_device *dev = crtc->dev;
4715         struct drm_i915_private *dev_priv = dev->dev_private;
4716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717         int pipe = intel_crtc->pipe;
4718
4719         /*
4720          * Gen2 reports pipe underruns whenever all planes are disabled.
4721          * So diasble underrun reporting before all the planes get disabled.
4722          * FIXME: Need to fix the logic to work when we turn off all planes
4723          * but leave the pipe running.
4724          */
4725         if (IS_GEN2(dev))
4726                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4727
4728         /*
4729          * Vblank time updates from the shadow to live plane control register
4730          * are blocked if the memory self-refresh mode is active at that
4731          * moment. So to make sure the plane gets truly disabled, disable
4732          * first the self-refresh mode. The self-refresh enable bit in turn
4733          * will be checked/applied by the HW only at the next frame start
4734          * event which is after the vblank start event, so we need to have a
4735          * wait-for-vblank between disabling the plane and the pipe.
4736          */
4737         if (HAS_GMCH_DISPLAY(dev)) {
4738                 intel_set_memory_cxsr(dev_priv, false);
4739                 dev_priv->wm.vlv.cxsr = false;
4740                 intel_wait_for_vblank(dev, pipe);
4741         }
4742
4743         /*
4744          * FIXME IPS should be fine as long as one plane is
4745          * enabled, but in practice it seems to have problems
4746          * when going from primary only to sprite only and vice
4747          * versa.
4748          */
4749         hsw_disable_ips(intel_crtc);
4750 }
4751
4752 static void intel_post_plane_update(struct intel_crtc *crtc)
4753 {
4754         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4755         struct drm_device *dev = crtc->base.dev;
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757         struct drm_plane *plane;
4758
4759         if (atomic->wait_vblank)
4760                 intel_wait_for_vblank(dev, crtc->pipe);
4761
4762         intel_frontbuffer_flip(dev, atomic->fb_bits);
4763
4764         if (atomic->disable_cxsr)
4765                 crtc->wm.cxsr_allowed = true;
4766
4767         if (crtc->atomic.update_wm_post)
4768                 intel_update_watermarks(&crtc->base);
4769
4770         if (atomic->update_fbc)
4771                 intel_fbc_update(dev_priv);
4772
4773         if (atomic->post_enable_primary)
4774                 intel_post_enable_primary(&crtc->base);
4775
4776         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4777                 intel_update_sprite_watermarks(plane, &crtc->base,
4778                                                0, 0, 0, false, false);
4779
4780         memset(atomic, 0, sizeof(*atomic));
4781 }
4782
4783 static void intel_pre_plane_update(struct intel_crtc *crtc)
4784 {
4785         struct drm_device *dev = crtc->base.dev;
4786         struct drm_i915_private *dev_priv = dev->dev_private;
4787         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4788         struct drm_plane *p;
4789
4790         /* Track fb's for any planes being disabled */
4791         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4792                 struct intel_plane *plane = to_intel_plane(p);
4793
4794                 mutex_lock(&dev->struct_mutex);
4795                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4796                                   plane->frontbuffer_bit);
4797                 mutex_unlock(&dev->struct_mutex);
4798         }
4799
4800         if (atomic->wait_for_flips)
4801                 intel_crtc_wait_for_pending_flips(&crtc->base);
4802
4803         if (atomic->disable_fbc)
4804                 intel_fbc_disable_crtc(crtc);
4805
4806         if (crtc->atomic.disable_ips)
4807                 hsw_disable_ips(crtc);
4808
4809         if (atomic->pre_disable_primary)
4810                 intel_pre_disable_primary(&crtc->base);
4811
4812         if (atomic->disable_cxsr) {
4813                 crtc->wm.cxsr_allowed = false;
4814                 intel_set_memory_cxsr(dev_priv, false);
4815         }
4816 }
4817
4818 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4819 {
4820         struct drm_device *dev = crtc->dev;
4821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822         struct drm_plane *p;
4823         int pipe = intel_crtc->pipe;
4824
4825         intel_crtc_dpms_overlay_disable(intel_crtc);
4826
4827         drm_for_each_plane_mask(p, dev, plane_mask)
4828                 to_intel_plane(p)->disable_plane(p, crtc);
4829
4830         /*
4831          * FIXME: Once we grow proper nuclear flip support out of this we need
4832          * to compute the mask of flip planes precisely. For the time being
4833          * consider this a flip to a NULL plane.
4834          */
4835         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4836 }
4837
4838 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4839 {
4840         struct drm_device *dev = crtc->dev;
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4843         struct intel_encoder *encoder;
4844         int pipe = intel_crtc->pipe;
4845
4846         if (WARN_ON(intel_crtc->active))
4847                 return;
4848
4849         if (intel_crtc->config->has_pch_encoder)
4850                 intel_prepare_shared_dpll(intel_crtc);
4851
4852         if (intel_crtc->config->has_dp_encoder)
4853                 intel_dp_set_m_n(intel_crtc, M1_N1);
4854
4855         intel_set_pipe_timings(intel_crtc);
4856
4857         if (intel_crtc->config->has_pch_encoder) {
4858                 intel_cpu_transcoder_set_m_n(intel_crtc,
4859                                      &intel_crtc->config->fdi_m_n, NULL);
4860         }
4861
4862         ironlake_set_pipeconf(crtc);
4863
4864         intel_crtc->active = true;
4865
4866         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4867         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4868
4869         for_each_encoder_on_crtc(dev, crtc, encoder)
4870                 if (encoder->pre_enable)
4871                         encoder->pre_enable(encoder);
4872
4873         if (intel_crtc->config->has_pch_encoder) {
4874                 /* Note: FDI PLL enabling _must_ be done before we enable the
4875                  * cpu pipes, hence this is separate from all the other fdi/pch
4876                  * enabling. */
4877                 ironlake_fdi_pll_enable(intel_crtc);
4878         } else {
4879                 assert_fdi_tx_disabled(dev_priv, pipe);
4880                 assert_fdi_rx_disabled(dev_priv, pipe);
4881         }
4882
4883         ironlake_pfit_enable(intel_crtc);
4884
4885         /*
4886          * On ILK+ LUT must be loaded before the pipe is running but with
4887          * clocks enabled
4888          */
4889         intel_crtc_load_lut(crtc);
4890
4891         intel_update_watermarks(crtc);
4892         intel_enable_pipe(intel_crtc);
4893
4894         if (intel_crtc->config->has_pch_encoder)
4895                 ironlake_pch_enable(crtc);
4896
4897         assert_vblank_disabled(crtc);
4898         drm_crtc_vblank_on(crtc);
4899
4900         for_each_encoder_on_crtc(dev, crtc, encoder)
4901                 encoder->enable(encoder);
4902
4903         if (HAS_PCH_CPT(dev))
4904                 cpt_verify_modeset(dev, intel_crtc->pipe);
4905 }
4906
4907 /* IPS only exists on ULT machines and is tied to pipe A. */
4908 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4909 {
4910         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4911 }
4912
4913 static void haswell_crtc_enable(struct drm_crtc *crtc)
4914 {
4915         struct drm_device *dev = crtc->dev;
4916         struct drm_i915_private *dev_priv = dev->dev_private;
4917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918         struct intel_encoder *encoder;
4919         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4920         struct intel_crtc_state *pipe_config =
4921                 to_intel_crtc_state(crtc->state);
4922
4923         if (WARN_ON(intel_crtc->active))
4924                 return;
4925
4926         if (intel_crtc_to_shared_dpll(intel_crtc))
4927                 intel_enable_shared_dpll(intel_crtc);
4928
4929         if (intel_crtc->config->has_dp_encoder)
4930                 intel_dp_set_m_n(intel_crtc, M1_N1);
4931
4932         intel_set_pipe_timings(intel_crtc);
4933
4934         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4935                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4936                            intel_crtc->config->pixel_multiplier - 1);
4937         }
4938
4939         if (intel_crtc->config->has_pch_encoder) {
4940                 intel_cpu_transcoder_set_m_n(intel_crtc,
4941                                      &intel_crtc->config->fdi_m_n, NULL);
4942         }
4943
4944         haswell_set_pipeconf(crtc);
4945
4946         intel_set_pipe_csc(crtc);
4947
4948         intel_crtc->active = true;
4949
4950         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4951         for_each_encoder_on_crtc(dev, crtc, encoder)
4952                 if (encoder->pre_enable)
4953                         encoder->pre_enable(encoder);
4954
4955         if (intel_crtc->config->has_pch_encoder) {
4956                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4957                                                       true);
4958                 dev_priv->display.fdi_link_train(crtc);
4959         }
4960
4961         intel_ddi_enable_pipe_clock(intel_crtc);
4962
4963         if (INTEL_INFO(dev)->gen == 9)
4964                 skylake_pfit_enable(intel_crtc);
4965         else if (INTEL_INFO(dev)->gen < 9)
4966                 ironlake_pfit_enable(intel_crtc);
4967         else
4968                 MISSING_CASE(INTEL_INFO(dev)->gen);
4969
4970         /*
4971          * On ILK+ LUT must be loaded before the pipe is running but with
4972          * clocks enabled
4973          */
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_ddi_set_pipe_settings(crtc);
4977         intel_ddi_enable_transcoder_func(crtc);
4978
4979         intel_update_watermarks(crtc);
4980         intel_enable_pipe(intel_crtc);
4981
4982         if (intel_crtc->config->has_pch_encoder)
4983                 lpt_pch_enable(crtc);
4984
4985         if (intel_crtc->config->dp_encoder_is_mst)
4986                 intel_ddi_set_vc_payload_alloc(crtc, true);
4987
4988         assert_vblank_disabled(crtc);
4989         drm_crtc_vblank_on(crtc);
4990
4991         for_each_encoder_on_crtc(dev, crtc, encoder) {
4992                 encoder->enable(encoder);
4993                 intel_opregion_notify_encoder(encoder, true);
4994         }
4995
4996         /* If we change the relative order between pipe/planes enabling, we need
4997          * to change the workaround. */
4998         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4999         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5000                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5001                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5002         }
5003 }
5004
5005 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5006 {
5007         struct drm_device *dev = crtc->base.dev;
5008         struct drm_i915_private *dev_priv = dev->dev_private;
5009         int pipe = crtc->pipe;
5010
5011         /* To avoid upsetting the power well on haswell only disable the pfit if
5012          * it's in use. The hw state code will make sure we get this right. */
5013         if (crtc->config->pch_pfit.enabled) {
5014                 I915_WRITE(PF_CTL(pipe), 0);
5015                 I915_WRITE(PF_WIN_POS(pipe), 0);
5016                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5017         }
5018 }
5019
5020 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5021 {
5022         struct drm_device *dev = crtc->dev;
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5025         struct intel_encoder *encoder;
5026         int pipe = intel_crtc->pipe;
5027         u32 reg, temp;
5028
5029         for_each_encoder_on_crtc(dev, crtc, encoder)
5030                 encoder->disable(encoder);
5031
5032         drm_crtc_vblank_off(crtc);
5033         assert_vblank_disabled(crtc);
5034
5035         if (intel_crtc->config->has_pch_encoder)
5036                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5037
5038         intel_disable_pipe(intel_crtc);
5039
5040         ironlake_pfit_disable(intel_crtc);
5041
5042         if (intel_crtc->config->has_pch_encoder)
5043                 ironlake_fdi_disable(crtc);
5044
5045         for_each_encoder_on_crtc(dev, crtc, encoder)
5046                 if (encoder->post_disable)
5047                         encoder->post_disable(encoder);
5048
5049         if (intel_crtc->config->has_pch_encoder) {
5050                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5051
5052                 if (HAS_PCH_CPT(dev)) {
5053                         /* disable TRANS_DP_CTL */
5054                         reg = TRANS_DP_CTL(pipe);
5055                         temp = I915_READ(reg);
5056                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057                                   TRANS_DP_PORT_SEL_MASK);
5058                         temp |= TRANS_DP_PORT_SEL_NONE;
5059                         I915_WRITE(reg, temp);
5060
5061                         /* disable DPLL_SEL */
5062                         temp = I915_READ(PCH_DPLL_SEL);
5063                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5064                         I915_WRITE(PCH_DPLL_SEL, temp);
5065                 }
5066
5067                 ironlake_fdi_pll_disable(intel_crtc);
5068         }
5069
5070         intel_crtc->active = false;
5071         intel_update_watermarks(crtc);
5072 }
5073
5074 static void haswell_crtc_disable(struct drm_crtc *crtc)
5075 {
5076         struct drm_device *dev = crtc->dev;
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079         struct intel_encoder *encoder;
5080         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5081
5082         for_each_encoder_on_crtc(dev, crtc, encoder) {
5083                 intel_opregion_notify_encoder(encoder, false);
5084                 encoder->disable(encoder);
5085         }
5086
5087         drm_crtc_vblank_off(crtc);
5088         assert_vblank_disabled(crtc);
5089
5090         if (intel_crtc->config->has_pch_encoder)
5091                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5092                                                       false);
5093         intel_disable_pipe(intel_crtc);
5094
5095         if (intel_crtc->config->dp_encoder_is_mst)
5096                 intel_ddi_set_vc_payload_alloc(crtc, false);
5097
5098         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5099
5100         if (INTEL_INFO(dev)->gen == 9)
5101                 skylake_scaler_disable(intel_crtc);
5102         else if (INTEL_INFO(dev)->gen < 9)
5103                 ironlake_pfit_disable(intel_crtc);
5104         else
5105                 MISSING_CASE(INTEL_INFO(dev)->gen);
5106
5107         intel_ddi_disable_pipe_clock(intel_crtc);
5108
5109         if (intel_crtc->config->has_pch_encoder) {
5110                 lpt_disable_pch_transcoder(dev_priv);
5111                 intel_ddi_fdi_disable(crtc);
5112         }
5113
5114         for_each_encoder_on_crtc(dev, crtc, encoder)
5115                 if (encoder->post_disable)
5116                         encoder->post_disable(encoder);
5117
5118         intel_crtc->active = false;
5119         intel_update_watermarks(crtc);
5120 }
5121
5122 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5123 {
5124         struct drm_device *dev = crtc->base.dev;
5125         struct drm_i915_private *dev_priv = dev->dev_private;
5126         struct intel_crtc_state *pipe_config = crtc->config;
5127
5128         if (!pipe_config->gmch_pfit.control)
5129                 return;
5130
5131         /*
5132          * The panel fitter should only be adjusted whilst the pipe is disabled,
5133          * according to register description and PRM.
5134          */
5135         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5136         assert_pipe_disabled(dev_priv, crtc->pipe);
5137
5138         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5139         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5140
5141         /* Border color in case we don't scale up to the full screen. Black by
5142          * default, change to something else for debugging. */
5143         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5144 }
5145
5146 static enum intel_display_power_domain port_to_power_domain(enum port port)
5147 {
5148         switch (port) {
5149         case PORT_A:
5150         case PORT_E:
5151                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5152         case PORT_B:
5153                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5154         case PORT_C:
5155                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5156         case PORT_D:
5157                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5158         default:
5159                 WARN_ON_ONCE(1);
5160                 return POWER_DOMAIN_PORT_OTHER;
5161         }
5162 }
5163
5164 #define for_each_power_domain(domain, mask)                             \
5165         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
5166                 if ((1 << (domain)) & (mask))
5167
5168 enum intel_display_power_domain
5169 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5170 {
5171         struct drm_device *dev = intel_encoder->base.dev;
5172         struct intel_digital_port *intel_dig_port;
5173
5174         switch (intel_encoder->type) {
5175         case INTEL_OUTPUT_UNKNOWN:
5176                 /* Only DDI platforms should ever use this output type */
5177                 WARN_ON_ONCE(!HAS_DDI(dev));
5178         case INTEL_OUTPUT_DISPLAYPORT:
5179         case INTEL_OUTPUT_HDMI:
5180         case INTEL_OUTPUT_EDP:
5181                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5182                 return port_to_power_domain(intel_dig_port->port);
5183         case INTEL_OUTPUT_DP_MST:
5184                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185                 return port_to_power_domain(intel_dig_port->port);
5186         case INTEL_OUTPUT_ANALOG:
5187                 return POWER_DOMAIN_PORT_CRT;
5188         case INTEL_OUTPUT_DSI:
5189                 return POWER_DOMAIN_PORT_DSI;
5190         default:
5191                 return POWER_DOMAIN_PORT_OTHER;
5192         }
5193 }
5194
5195 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5196 {
5197         struct drm_device *dev = crtc->dev;
5198         struct intel_encoder *intel_encoder;
5199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200         enum pipe pipe = intel_crtc->pipe;
5201         unsigned long mask;
5202         enum transcoder transcoder;
5203
5204         if (!crtc->state->active)
5205                 return 0;
5206
5207         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5208
5209         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5211         if (intel_crtc->config->pch_pfit.enabled ||
5212             intel_crtc->config->pch_pfit.force_thru)
5213                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214
5215         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5216                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5217
5218         return mask;
5219 }
5220
5221 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5222 {
5223         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5225         enum intel_display_power_domain domain;
5226         unsigned long domains, new_domains, old_domains;
5227
5228         old_domains = intel_crtc->enabled_power_domains;
5229         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5230
5231         domains = new_domains & ~old_domains;
5232
5233         for_each_power_domain(domain, domains)
5234                 intel_display_power_get(dev_priv, domain);
5235
5236         return old_domains & ~new_domains;
5237 }
5238
5239 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5240                                       unsigned long domains)
5241 {
5242         enum intel_display_power_domain domain;
5243
5244         for_each_power_domain(domain, domains)
5245                 intel_display_power_put(dev_priv, domain);
5246 }
5247
5248 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5249 {
5250         struct drm_device *dev = state->dev;
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         unsigned long put_domains[I915_MAX_PIPES] = {};
5253         struct drm_crtc_state *crtc_state;
5254         struct drm_crtc *crtc;
5255         int i;
5256
5257         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5258                 if (needs_modeset(crtc->state))
5259                         put_domains[to_intel_crtc(crtc)->pipe] =
5260                                 modeset_get_crtc_power_domains(crtc);
5261         }
5262
5263         if (dev_priv->display.modeset_commit_cdclk) {
5264                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5265
5266                 if (cdclk != dev_priv->cdclk_freq &&
5267                     !WARN_ON(!state->allow_modeset))
5268                         dev_priv->display.modeset_commit_cdclk(state);
5269         }
5270
5271         for (i = 0; i < I915_MAX_PIPES; i++)
5272                 if (put_domains[i])
5273                         modeset_put_power_domains(dev_priv, put_domains[i]);
5274 }
5275
5276 static void intel_update_max_cdclk(struct drm_device *dev)
5277 {
5278         struct drm_i915_private *dev_priv = dev->dev_private;
5279
5280         if (IS_SKYLAKE(dev)) {
5281                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5282
5283                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5284                         dev_priv->max_cdclk_freq = 675000;
5285                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5286                         dev_priv->max_cdclk_freq = 540000;
5287                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5288                         dev_priv->max_cdclk_freq = 450000;
5289                 else
5290                         dev_priv->max_cdclk_freq = 337500;
5291         } else if (IS_BROADWELL(dev))  {
5292                 /*
5293                  * FIXME with extra cooling we can allow
5294                  * 540 MHz for ULX and 675 Mhz for ULT.
5295                  * How can we know if extra cooling is
5296                  * available? PCI ID, VTB, something else?
5297                  */
5298                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5299                         dev_priv->max_cdclk_freq = 450000;
5300                 else if (IS_BDW_ULX(dev))
5301                         dev_priv->max_cdclk_freq = 450000;
5302                 else if (IS_BDW_ULT(dev))
5303                         dev_priv->max_cdclk_freq = 540000;
5304                 else
5305                         dev_priv->max_cdclk_freq = 675000;
5306         } else if (IS_CHERRYVIEW(dev)) {
5307                 dev_priv->max_cdclk_freq = 320000;
5308         } else if (IS_VALLEYVIEW(dev)) {
5309                 dev_priv->max_cdclk_freq = 400000;
5310         } else {
5311                 /* otherwise assume cdclk is fixed */
5312                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5313         }
5314
5315         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5316                          dev_priv->max_cdclk_freq);
5317 }
5318
5319 static void intel_update_cdclk(struct drm_device *dev)
5320 {
5321         struct drm_i915_private *dev_priv = dev->dev_private;
5322
5323         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5324         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5325                          dev_priv->cdclk_freq);
5326
5327         /*
5328          * Program the gmbus_freq based on the cdclk frequency.
5329          * BSpec erroneously claims we should aim for 4MHz, but
5330          * in fact 1MHz is the correct frequency.
5331          */
5332         if (IS_VALLEYVIEW(dev)) {
5333                 /*
5334                  * Program the gmbus_freq based on the cdclk frequency.
5335                  * BSpec erroneously claims we should aim for 4MHz, but
5336                  * in fact 1MHz is the correct frequency.
5337                  */
5338                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5339         }
5340
5341         if (dev_priv->max_cdclk_freq == 0)
5342                 intel_update_max_cdclk(dev);
5343 }
5344
5345 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5346 {
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         uint32_t divider;
5349         uint32_t ratio;
5350         uint32_t current_freq;
5351         int ret;
5352
5353         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5354         switch (frequency) {
5355         case 144000:
5356                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5357                 ratio = BXT_DE_PLL_RATIO(60);
5358                 break;
5359         case 288000:
5360                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5361                 ratio = BXT_DE_PLL_RATIO(60);
5362                 break;
5363         case 384000:
5364                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5365                 ratio = BXT_DE_PLL_RATIO(60);
5366                 break;
5367         case 576000:
5368                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5369                 ratio = BXT_DE_PLL_RATIO(60);
5370                 break;
5371         case 624000:
5372                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373                 ratio = BXT_DE_PLL_RATIO(65);
5374                 break;
5375         case 19200:
5376                 /*
5377                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5378                  * to suppress GCC warning.
5379                  */
5380                 ratio = 0;
5381                 divider = 0;
5382                 break;
5383         default:
5384                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5385
5386                 return;
5387         }
5388
5389         mutex_lock(&dev_priv->rps.hw_lock);
5390         /* Inform power controller of upcoming frequency change */
5391         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5392                                       0x80000000);
5393         mutex_unlock(&dev_priv->rps.hw_lock);
5394
5395         if (ret) {
5396                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5397                           ret, frequency);
5398                 return;
5399         }
5400
5401         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5402         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5403         current_freq = current_freq * 500 + 1000;
5404
5405         /*
5406          * DE PLL has to be disabled when
5407          * - setting to 19.2MHz (bypass, PLL isn't used)
5408          * - before setting to 624MHz (PLL needs toggling)
5409          * - before setting to any frequency from 624MHz (PLL needs toggling)
5410          */
5411         if (frequency == 19200 || frequency == 624000 ||
5412             current_freq == 624000) {
5413                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5414                 /* Timeout 200us */
5415                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5416                              1))
5417                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5418         }
5419
5420         if (frequency != 19200) {
5421                 uint32_t val;
5422
5423                 val = I915_READ(BXT_DE_PLL_CTL);
5424                 val &= ~BXT_DE_PLL_RATIO_MASK;
5425                 val |= ratio;
5426                 I915_WRITE(BXT_DE_PLL_CTL, val);
5427
5428                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5429                 /* Timeout 200us */
5430                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5431                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5432
5433                 val = I915_READ(CDCLK_CTL);
5434                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5435                 val |= divider;
5436                 /*
5437                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5438                  * enable otherwise.
5439                  */
5440                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5441                 if (frequency >= 500000)
5442                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5443
5444                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5445                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5446                 val |= (frequency - 1000) / 500;
5447                 I915_WRITE(CDCLK_CTL, val);
5448         }
5449
5450         mutex_lock(&dev_priv->rps.hw_lock);
5451         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5452                                       DIV_ROUND_UP(frequency, 25000));
5453         mutex_unlock(&dev_priv->rps.hw_lock);
5454
5455         if (ret) {
5456                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5457                           ret, frequency);
5458                 return;
5459         }
5460
5461         intel_update_cdclk(dev);
5462 }
5463
5464 void broxton_init_cdclk(struct drm_device *dev)
5465 {
5466         struct drm_i915_private *dev_priv = dev->dev_private;
5467         uint32_t val;
5468
5469         /*
5470          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5471          * or else the reset will hang because there is no PCH to respond.
5472          * Move the handshake programming to initialization sequence.
5473          * Previously was left up to BIOS.
5474          */
5475         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5476         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5477         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5478
5479         /* Enable PG1 for cdclk */
5480         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5481
5482         /* check if cd clock is enabled */
5483         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5484                 DRM_DEBUG_KMS("Display already initialized\n");
5485                 return;
5486         }
5487
5488         /*
5489          * FIXME:
5490          * - The initial CDCLK needs to be read from VBT.
5491          *   Need to make this change after VBT has changes for BXT.
5492          * - check if setting the max (or any) cdclk freq is really necessary
5493          *   here, it belongs to modeset time
5494          */
5495         broxton_set_cdclk(dev, 624000);
5496
5497         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5498         POSTING_READ(DBUF_CTL);
5499
5500         udelay(10);
5501
5502         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5503                 DRM_ERROR("DBuf power enable timeout!\n");
5504 }
5505
5506 void broxton_uninit_cdclk(struct drm_device *dev)
5507 {
5508         struct drm_i915_private *dev_priv = dev->dev_private;
5509
5510         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5511         POSTING_READ(DBUF_CTL);
5512
5513         udelay(10);
5514
5515         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5516                 DRM_ERROR("DBuf power disable timeout!\n");
5517
5518         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5519         broxton_set_cdclk(dev, 19200);
5520
5521         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5522 }
5523
5524 static const struct skl_cdclk_entry {
5525         unsigned int freq;
5526         unsigned int vco;
5527 } skl_cdclk_frequencies[] = {
5528         { .freq = 308570, .vco = 8640 },
5529         { .freq = 337500, .vco = 8100 },
5530         { .freq = 432000, .vco = 8640 },
5531         { .freq = 450000, .vco = 8100 },
5532         { .freq = 540000, .vco = 8100 },
5533         { .freq = 617140, .vco = 8640 },
5534         { .freq = 675000, .vco = 8100 },
5535 };
5536
5537 static unsigned int skl_cdclk_decimal(unsigned int freq)
5538 {
5539         return (freq - 1000) / 500;
5540 }
5541
5542 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5543 {
5544         unsigned int i;
5545
5546         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5547                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5548
5549                 if (e->freq == freq)
5550                         return e->vco;
5551         }
5552
5553         return 8100;
5554 }
5555
5556 static void
5557 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5558 {
5559         unsigned int min_freq;
5560         u32 val;
5561
5562         /* select the minimum CDCLK before enabling DPLL 0 */
5563         val = I915_READ(CDCLK_CTL);
5564         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5565         val |= CDCLK_FREQ_337_308;
5566
5567         if (required_vco == 8640)
5568                 min_freq = 308570;
5569         else
5570                 min_freq = 337500;
5571
5572         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5573
5574         I915_WRITE(CDCLK_CTL, val);
5575         POSTING_READ(CDCLK_CTL);
5576
5577         /*
5578          * We always enable DPLL0 with the lowest link rate possible, but still
5579          * taking into account the VCO required to operate the eDP panel at the
5580          * desired frequency. The usual DP link rates operate with a VCO of
5581          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5582          * The modeset code is responsible for the selection of the exact link
5583          * rate later on, with the constraint of choosing a frequency that
5584          * works with required_vco.
5585          */
5586         val = I915_READ(DPLL_CTRL1);
5587
5588         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5589                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5590         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5591         if (required_vco == 8640)
5592                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5593                                             SKL_DPLL0);
5594         else
5595                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5596                                             SKL_DPLL0);
5597
5598         I915_WRITE(DPLL_CTRL1, val);
5599         POSTING_READ(DPLL_CTRL1);
5600
5601         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5602
5603         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5604                 DRM_ERROR("DPLL0 not locked\n");
5605 }
5606
5607 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5608 {
5609         int ret;
5610         u32 val;
5611
5612         /* inform PCU we want to change CDCLK */
5613         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5614         mutex_lock(&dev_priv->rps.hw_lock);
5615         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5616         mutex_unlock(&dev_priv->rps.hw_lock);
5617
5618         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5619 }
5620
5621 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5622 {
5623         unsigned int i;
5624
5625         for (i = 0; i < 15; i++) {
5626                 if (skl_cdclk_pcu_ready(dev_priv))
5627                         return true;
5628                 udelay(10);
5629         }
5630
5631         return false;
5632 }
5633
5634 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5635 {
5636         struct drm_device *dev = dev_priv->dev;
5637         u32 freq_select, pcu_ack;
5638
5639         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5640
5641         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5642                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5643                 return;
5644         }
5645
5646         /* set CDCLK_CTL */
5647         switch(freq) {
5648         case 450000:
5649         case 432000:
5650                 freq_select = CDCLK_FREQ_450_432;
5651                 pcu_ack = 1;
5652                 break;
5653         case 540000:
5654                 freq_select = CDCLK_FREQ_540;
5655                 pcu_ack = 2;
5656                 break;
5657         case 308570:
5658         case 337500:
5659         default:
5660                 freq_select = CDCLK_FREQ_337_308;
5661                 pcu_ack = 0;
5662                 break;
5663         case 617140:
5664         case 675000:
5665                 freq_select = CDCLK_FREQ_675_617;
5666                 pcu_ack = 3;
5667                 break;
5668         }
5669
5670         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5671         POSTING_READ(CDCLK_CTL);
5672
5673         /* inform PCU of the change */
5674         mutex_lock(&dev_priv->rps.hw_lock);
5675         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5676         mutex_unlock(&dev_priv->rps.hw_lock);
5677
5678         intel_update_cdclk(dev);
5679 }
5680
5681 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5682 {
5683         /* disable DBUF power */
5684         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5685         POSTING_READ(DBUF_CTL);
5686
5687         udelay(10);
5688
5689         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5690                 DRM_ERROR("DBuf power disable timeout\n");
5691
5692         /* disable DPLL0 */
5693         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5694         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5695                 DRM_ERROR("Couldn't disable DPLL0\n");
5696
5697         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5698 }
5699
5700 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5701 {
5702         u32 val;
5703         unsigned int required_vco;
5704
5705         /* enable PCH reset handshake */
5706         val = I915_READ(HSW_NDE_RSTWRN_OPT);
5707         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5708
5709         /* enable PG1 and Misc I/O */
5710         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5711
5712         /* DPLL0 already enabed !? */
5713         if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5714                 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5715                 return;
5716         }
5717
5718         /* enable DPLL0 */
5719         required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5720         skl_dpll0_enable(dev_priv, required_vco);
5721
5722         /* set CDCLK to the frequency the BIOS chose */
5723         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5724
5725         /* enable DBUF power */
5726         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5727         POSTING_READ(DBUF_CTL);
5728
5729         udelay(10);
5730
5731         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5732                 DRM_ERROR("DBuf power enable timeout\n");
5733 }
5734
5735 /* returns HPLL frequency in kHz */
5736 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5737 {
5738         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5739
5740         /* Obtain SKU information */
5741         mutex_lock(&dev_priv->sb_lock);
5742         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5743                 CCK_FUSE_HPLL_FREQ_MASK;
5744         mutex_unlock(&dev_priv->sb_lock);
5745
5746         return vco_freq[hpll_freq] * 1000;
5747 }
5748
5749 /* Adjust CDclk dividers to allow high res or save power if possible */
5750 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5751 {
5752         struct drm_i915_private *dev_priv = dev->dev_private;
5753         u32 val, cmd;
5754
5755         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5756                                         != dev_priv->cdclk_freq);
5757
5758         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5759                 cmd = 2;
5760         else if (cdclk == 266667)
5761                 cmd = 1;
5762         else
5763                 cmd = 0;
5764
5765         mutex_lock(&dev_priv->rps.hw_lock);
5766         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5767         val &= ~DSPFREQGUAR_MASK;
5768         val |= (cmd << DSPFREQGUAR_SHIFT);
5769         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5770         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5771                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5772                      50)) {
5773                 DRM_ERROR("timed out waiting for CDclk change\n");
5774         }
5775         mutex_unlock(&dev_priv->rps.hw_lock);
5776
5777         mutex_lock(&dev_priv->sb_lock);
5778
5779         if (cdclk == 400000) {
5780                 u32 divider;
5781
5782                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5783
5784                 /* adjust cdclk divider */
5785                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5786                 val &= ~DISPLAY_FREQUENCY_VALUES;
5787                 val |= divider;
5788                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5789
5790                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5791                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5792                              50))
5793                         DRM_ERROR("timed out waiting for CDclk change\n");
5794         }
5795
5796         /* adjust self-refresh exit latency value */
5797         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5798         val &= ~0x7f;
5799
5800         /*
5801          * For high bandwidth configs, we set a higher latency in the bunit
5802          * so that the core display fetch happens in time to avoid underruns.
5803          */
5804         if (cdclk == 400000)
5805                 val |= 4500 / 250; /* 4.5 usec */
5806         else
5807                 val |= 3000 / 250; /* 3.0 usec */
5808         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5809
5810         mutex_unlock(&dev_priv->sb_lock);
5811
5812         intel_update_cdclk(dev);
5813 }
5814
5815 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5816 {
5817         struct drm_i915_private *dev_priv = dev->dev_private;
5818         u32 val, cmd;
5819
5820         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5821                                                 != dev_priv->cdclk_freq);
5822
5823         switch (cdclk) {
5824         case 333333:
5825         case 320000:
5826         case 266667:
5827         case 200000:
5828                 break;
5829         default:
5830                 MISSING_CASE(cdclk);
5831                 return;
5832         }
5833
5834         /*
5835          * Specs are full of misinformation, but testing on actual
5836          * hardware has shown that we just need to write the desired
5837          * CCK divider into the Punit register.
5838          */
5839         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5840
5841         mutex_lock(&dev_priv->rps.hw_lock);
5842         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5843         val &= ~DSPFREQGUAR_MASK_CHV;
5844         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5845         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5846         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5847                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5848                      50)) {
5849                 DRM_ERROR("timed out waiting for CDclk change\n");
5850         }
5851         mutex_unlock(&dev_priv->rps.hw_lock);
5852
5853         intel_update_cdclk(dev);
5854 }
5855
5856 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5857                                  int max_pixclk)
5858 {
5859         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5860         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5861
5862         /*
5863          * Really only a few cases to deal with, as only 4 CDclks are supported:
5864          *   200MHz
5865          *   267MHz
5866          *   320/333MHz (depends on HPLL freq)
5867          *   400MHz (VLV only)
5868          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5869          * of the lower bin and adjust if needed.
5870          *
5871          * We seem to get an unstable or solid color picture at 200MHz.
5872          * Not sure what's wrong. For now use 200MHz only when all pipes
5873          * are off.
5874          */
5875         if (!IS_CHERRYVIEW(dev_priv) &&
5876             max_pixclk > freq_320*limit/100)
5877                 return 400000;
5878         else if (max_pixclk > 266667*limit/100)
5879                 return freq_320;
5880         else if (max_pixclk > 0)
5881                 return 266667;
5882         else
5883                 return 200000;
5884 }
5885
5886 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5887                               int max_pixclk)
5888 {
5889         /*
5890          * FIXME:
5891          * - remove the guardband, it's not needed on BXT
5892          * - set 19.2MHz bypass frequency if there are no active pipes
5893          */
5894         if (max_pixclk > 576000*9/10)
5895                 return 624000;
5896         else if (max_pixclk > 384000*9/10)
5897                 return 576000;
5898         else if (max_pixclk > 288000*9/10)
5899                 return 384000;
5900         else if (max_pixclk > 144000*9/10)
5901                 return 288000;
5902         else
5903                 return 144000;
5904 }
5905
5906 /* Compute the max pixel clock for new configuration. Uses atomic state if
5907  * that's non-NULL, look at current state otherwise. */
5908 static int intel_mode_max_pixclk(struct drm_device *dev,
5909                                  struct drm_atomic_state *state)
5910 {
5911         struct intel_crtc *intel_crtc;
5912         struct intel_crtc_state *crtc_state;
5913         int max_pixclk = 0;
5914
5915         for_each_intel_crtc(dev, intel_crtc) {
5916                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5917                 if (IS_ERR(crtc_state))
5918                         return PTR_ERR(crtc_state);
5919
5920                 if (!crtc_state->base.enable)
5921                         continue;
5922
5923                 max_pixclk = max(max_pixclk,
5924                                  crtc_state->base.adjusted_mode.crtc_clock);
5925         }
5926
5927         return max_pixclk;
5928 }
5929
5930 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5931 {
5932         struct drm_device *dev = state->dev;
5933         struct drm_i915_private *dev_priv = dev->dev_private;
5934         int max_pixclk = intel_mode_max_pixclk(dev, state);
5935
5936         if (max_pixclk < 0)
5937                 return max_pixclk;
5938
5939         to_intel_atomic_state(state)->cdclk =
5940                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5941
5942         return 0;
5943 }
5944
5945 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5946 {
5947         struct drm_device *dev = state->dev;
5948         struct drm_i915_private *dev_priv = dev->dev_private;
5949         int max_pixclk = intel_mode_max_pixclk(dev, state);
5950
5951         if (max_pixclk < 0)
5952                 return max_pixclk;
5953
5954         to_intel_atomic_state(state)->cdclk =
5955                 broxton_calc_cdclk(dev_priv, max_pixclk);
5956
5957         return 0;
5958 }
5959
5960 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5961 {
5962         unsigned int credits, default_credits;
5963
5964         if (IS_CHERRYVIEW(dev_priv))
5965                 default_credits = PFI_CREDIT(12);
5966         else
5967                 default_credits = PFI_CREDIT(8);
5968
5969         if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5970                 /* CHV suggested value is 31 or 63 */
5971                 if (IS_CHERRYVIEW(dev_priv))
5972                         credits = PFI_CREDIT_63;
5973                 else
5974                         credits = PFI_CREDIT(15);
5975         } else {
5976                 credits = default_credits;
5977         }
5978
5979         /*
5980          * WA - write default credits before re-programming
5981          * FIXME: should we also set the resend bit here?
5982          */
5983         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5984                    default_credits);
5985
5986         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5987                    credits | PFI_CREDIT_RESEND);
5988
5989         /*
5990          * FIXME is this guaranteed to clear
5991          * immediately or should we poll for it?
5992          */
5993         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5994 }
5995
5996 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5997 {
5998         struct drm_device *dev = old_state->dev;
5999         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001
6002         /*
6003          * FIXME: We can end up here with all power domains off, yet
6004          * with a CDCLK frequency other than the minimum. To account
6005          * for this take the PIPE-A power domain, which covers the HW
6006          * blocks needed for the following programming. This can be
6007          * removed once it's guaranteed that we get here either with
6008          * the minimum CDCLK set, or the required power domains
6009          * enabled.
6010          */
6011         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6012
6013         if (IS_CHERRYVIEW(dev))
6014                 cherryview_set_cdclk(dev, req_cdclk);
6015         else
6016                 valleyview_set_cdclk(dev, req_cdclk);
6017
6018         vlv_program_pfi_credits(dev_priv);
6019
6020         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6021 }
6022
6023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6024 {
6025         struct drm_device *dev = crtc->dev;
6026         struct drm_i915_private *dev_priv = to_i915(dev);
6027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028         struct intel_encoder *encoder;
6029         int pipe = intel_crtc->pipe;
6030         bool is_dsi;
6031
6032         if (WARN_ON(intel_crtc->active))
6033                 return;
6034
6035         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6036
6037         if (!is_dsi) {
6038                 if (IS_CHERRYVIEW(dev))
6039                         chv_prepare_pll(intel_crtc, intel_crtc->config);
6040                 else
6041                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
6042         }
6043
6044         if (intel_crtc->config->has_dp_encoder)
6045                 intel_dp_set_m_n(intel_crtc, M1_N1);
6046
6047         intel_set_pipe_timings(intel_crtc);
6048
6049         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6050                 struct drm_i915_private *dev_priv = dev->dev_private;
6051
6052                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6053                 I915_WRITE(CHV_CANVAS(pipe), 0);
6054         }
6055
6056         i9xx_set_pipeconf(intel_crtc);
6057
6058         intel_crtc->active = true;
6059
6060         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6061
6062         for_each_encoder_on_crtc(dev, crtc, encoder)
6063                 if (encoder->pre_pll_enable)
6064                         encoder->pre_pll_enable(encoder);
6065
6066         if (!is_dsi) {
6067                 if (IS_CHERRYVIEW(dev))
6068                         chv_enable_pll(intel_crtc, intel_crtc->config);
6069                 else
6070                         vlv_enable_pll(intel_crtc, intel_crtc->config);
6071         }
6072
6073         for_each_encoder_on_crtc(dev, crtc, encoder)
6074                 if (encoder->pre_enable)
6075                         encoder->pre_enable(encoder);
6076
6077         i9xx_pfit_enable(intel_crtc);
6078
6079         intel_crtc_load_lut(crtc);
6080
6081         intel_enable_pipe(intel_crtc);
6082
6083         assert_vblank_disabled(crtc);
6084         drm_crtc_vblank_on(crtc);
6085
6086         for_each_encoder_on_crtc(dev, crtc, encoder)
6087                 encoder->enable(encoder);
6088 }
6089
6090 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6091 {
6092         struct drm_device *dev = crtc->base.dev;
6093         struct drm_i915_private *dev_priv = dev->dev_private;
6094
6095         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6096         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6097 }
6098
6099 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6100 {
6101         struct drm_device *dev = crtc->dev;
6102         struct drm_i915_private *dev_priv = to_i915(dev);
6103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6104         struct intel_encoder *encoder;
6105         int pipe = intel_crtc->pipe;
6106
6107         if (WARN_ON(intel_crtc->active))
6108                 return;
6109
6110         i9xx_set_pll_dividers(intel_crtc);
6111
6112         if (intel_crtc->config->has_dp_encoder)
6113                 intel_dp_set_m_n(intel_crtc, M1_N1);
6114
6115         intel_set_pipe_timings(intel_crtc);
6116
6117         i9xx_set_pipeconf(intel_crtc);
6118
6119         intel_crtc->active = true;
6120
6121         if (!IS_GEN2(dev))
6122                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6123
6124         for_each_encoder_on_crtc(dev, crtc, encoder)
6125                 if (encoder->pre_enable)
6126                         encoder->pre_enable(encoder);
6127
6128         i9xx_enable_pll(intel_crtc);
6129
6130         i9xx_pfit_enable(intel_crtc);
6131
6132         intel_crtc_load_lut(crtc);
6133
6134         intel_update_watermarks(crtc);
6135         intel_enable_pipe(intel_crtc);
6136
6137         assert_vblank_disabled(crtc);
6138         drm_crtc_vblank_on(crtc);
6139
6140         for_each_encoder_on_crtc(dev, crtc, encoder)
6141                 encoder->enable(encoder);
6142 }
6143
6144 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6145 {
6146         struct drm_device *dev = crtc->base.dev;
6147         struct drm_i915_private *dev_priv = dev->dev_private;
6148
6149         if (!crtc->config->gmch_pfit.control)
6150                 return;
6151
6152         assert_pipe_disabled(dev_priv, crtc->pipe);
6153
6154         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6155                          I915_READ(PFIT_CONTROL));
6156         I915_WRITE(PFIT_CONTROL, 0);
6157 }
6158
6159 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6160 {
6161         struct drm_device *dev = crtc->dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164         struct intel_encoder *encoder;
6165         int pipe = intel_crtc->pipe;
6166
6167         /*
6168          * On gen2 planes are double buffered but the pipe isn't, so we must
6169          * wait for planes to fully turn off before disabling the pipe.
6170          * We also need to wait on all gmch platforms because of the
6171          * self-refresh mode constraint explained above.
6172          */
6173         intel_wait_for_vblank(dev, pipe);
6174
6175         for_each_encoder_on_crtc(dev, crtc, encoder)
6176                 encoder->disable(encoder);
6177
6178         drm_crtc_vblank_off(crtc);
6179         assert_vblank_disabled(crtc);
6180
6181         intel_disable_pipe(intel_crtc);
6182
6183         i9xx_pfit_disable(intel_crtc);
6184
6185         for_each_encoder_on_crtc(dev, crtc, encoder)
6186                 if (encoder->post_disable)
6187                         encoder->post_disable(encoder);
6188
6189         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6190                 if (IS_CHERRYVIEW(dev))
6191                         chv_disable_pll(dev_priv, pipe);
6192                 else if (IS_VALLEYVIEW(dev))
6193                         vlv_disable_pll(dev_priv, pipe);
6194                 else
6195                         i9xx_disable_pll(intel_crtc);
6196         }
6197
6198         if (!IS_GEN2(dev))
6199                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6200
6201         intel_crtc->active = false;
6202         intel_update_watermarks(crtc);
6203 }
6204
6205 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6206 {
6207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6209         enum intel_display_power_domain domain;
6210         unsigned long domains;
6211
6212         if (!intel_crtc->active)
6213                 return;
6214
6215         if (to_intel_plane_state(crtc->primary->state)->visible) {
6216                 intel_crtc_wait_for_pending_flips(crtc);
6217                 intel_pre_disable_primary(crtc);
6218         }
6219
6220         intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6221         dev_priv->display.crtc_disable(crtc);
6222         intel_disable_shared_dpll(intel_crtc);
6223
6224         domains = intel_crtc->enabled_power_domains;
6225         for_each_power_domain(domain, domains)
6226                 intel_display_power_put(dev_priv, domain);
6227         intel_crtc->enabled_power_domains = 0;
6228 }
6229
6230 /*
6231  * turn all crtc's off, but do not adjust state
6232  * This has to be paired with a call to intel_modeset_setup_hw_state.
6233  */
6234 int intel_display_suspend(struct drm_device *dev)
6235 {
6236         struct drm_mode_config *config = &dev->mode_config;
6237         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6238         struct drm_atomic_state *state;
6239         struct drm_crtc *crtc;
6240         unsigned crtc_mask = 0;
6241         int ret = 0;
6242
6243         if (WARN_ON(!ctx))
6244                 return 0;
6245
6246         lockdep_assert_held(&ctx->ww_ctx);
6247         state = drm_atomic_state_alloc(dev);
6248         if (WARN_ON(!state))
6249                 return -ENOMEM;
6250
6251         state->acquire_ctx = ctx;
6252         state->allow_modeset = true;
6253
6254         for_each_crtc(dev, crtc) {
6255                 struct drm_crtc_state *crtc_state =
6256                         drm_atomic_get_crtc_state(state, crtc);
6257
6258                 ret = PTR_ERR_OR_ZERO(crtc_state);
6259                 if (ret)
6260                         goto free;
6261
6262                 if (!crtc_state->active)
6263                         continue;
6264
6265                 crtc_state->active = false;
6266                 crtc_mask |= 1 << drm_crtc_index(crtc);
6267         }
6268
6269         if (crtc_mask) {
6270                 ret = drm_atomic_commit(state);
6271
6272                 if (!ret) {
6273                         for_each_crtc(dev, crtc)
6274                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6275                                         crtc->state->active = true;
6276
6277                         return ret;
6278                 }
6279         }
6280
6281 free:
6282         if (ret)
6283                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6284         drm_atomic_state_free(state);
6285         return ret;
6286 }
6287
6288 void intel_encoder_destroy(struct drm_encoder *encoder)
6289 {
6290         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6291
6292         drm_encoder_cleanup(encoder);
6293         kfree(intel_encoder);
6294 }
6295
6296 /* Cross check the actual hw state with our own modeset state tracking (and it's
6297  * internal consistency). */
6298 static void intel_connector_check_state(struct intel_connector *connector)
6299 {
6300         struct drm_crtc *crtc = connector->base.state->crtc;
6301
6302         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6303                       connector->base.base.id,
6304                       connector->base.name);
6305
6306         if (connector->get_hw_state(connector)) {
6307                 struct drm_encoder *encoder = &connector->encoder->base;
6308                 struct drm_connector_state *conn_state = connector->base.state;
6309
6310                 I915_STATE_WARN(!crtc,
6311                          "connector enabled without attached crtc\n");
6312
6313                 if (!crtc)
6314                         return;
6315
6316                 I915_STATE_WARN(!crtc->state->active,
6317                       "connector is active, but attached crtc isn't\n");
6318
6319                 if (!encoder)
6320                         return;
6321
6322                 I915_STATE_WARN(conn_state->best_encoder != encoder,
6323                         "atomic encoder doesn't match attached encoder\n");
6324
6325                 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6326                         "attached encoder crtc differs from connector crtc\n");
6327         } else {
6328                 I915_STATE_WARN(crtc && crtc->state->active,
6329                         "attached crtc is active, but connector isn't\n");
6330                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6331                         "best encoder set without crtc!\n");
6332         }
6333 }
6334
6335 int intel_connector_init(struct intel_connector *connector)
6336 {
6337         struct drm_connector_state *connector_state;
6338
6339         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6340         if (!connector_state)
6341                 return -ENOMEM;
6342
6343         connector->base.state = connector_state;
6344         return 0;
6345 }
6346
6347 struct intel_connector *intel_connector_alloc(void)
6348 {
6349         struct intel_connector *connector;
6350
6351         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6352         if (!connector)
6353                 return NULL;
6354
6355         if (intel_connector_init(connector) < 0) {
6356                 kfree(connector);
6357                 return NULL;
6358         }
6359
6360         return connector;
6361 }
6362
6363 /* Simple connector->get_hw_state implementation for encoders that support only
6364  * one connector and no cloning and hence the encoder state determines the state
6365  * of the connector. */
6366 bool intel_connector_get_hw_state(struct intel_connector *connector)
6367 {
6368         enum pipe pipe = 0;
6369         struct intel_encoder *encoder = connector->encoder;
6370
6371         return encoder->get_hw_state(encoder, &pipe);
6372 }
6373
6374 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6375 {
6376         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6377                 return crtc_state->fdi_lanes;
6378
6379         return 0;
6380 }
6381
6382 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6383                                      struct intel_crtc_state *pipe_config)
6384 {
6385         struct drm_atomic_state *state = pipe_config->base.state;
6386         struct intel_crtc *other_crtc;
6387         struct intel_crtc_state *other_crtc_state;
6388
6389         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6390                       pipe_name(pipe), pipe_config->fdi_lanes);
6391         if (pipe_config->fdi_lanes > 4) {
6392                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6393                               pipe_name(pipe), pipe_config->fdi_lanes);
6394                 return -EINVAL;
6395         }
6396
6397         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6398                 if (pipe_config->fdi_lanes > 2) {
6399                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6400                                       pipe_config->fdi_lanes);
6401                         return -EINVAL;
6402                 } else {
6403                         return 0;
6404                 }
6405         }
6406
6407         if (INTEL_INFO(dev)->num_pipes == 2)
6408                 return 0;
6409
6410         /* Ivybridge 3 pipe is really complicated */
6411         switch (pipe) {
6412         case PIPE_A:
6413                 return 0;
6414         case PIPE_B:
6415                 if (pipe_config->fdi_lanes <= 2)
6416                         return 0;
6417
6418                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6419                 other_crtc_state =
6420                         intel_atomic_get_crtc_state(state, other_crtc);
6421                 if (IS_ERR(other_crtc_state))
6422                         return PTR_ERR(other_crtc_state);
6423
6424                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6425                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6426                                       pipe_name(pipe), pipe_config->fdi_lanes);
6427                         return -EINVAL;
6428                 }
6429                 return 0;
6430         case PIPE_C:
6431                 if (pipe_config->fdi_lanes > 2) {
6432                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6433                                       pipe_name(pipe), pipe_config->fdi_lanes);
6434                         return -EINVAL;
6435                 }
6436
6437                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6438                 other_crtc_state =
6439                         intel_atomic_get_crtc_state(state, other_crtc);
6440                 if (IS_ERR(other_crtc_state))
6441                         return PTR_ERR(other_crtc_state);
6442
6443                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6444                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6445                         return -EINVAL;
6446                 }
6447                 return 0;
6448         default:
6449                 BUG();
6450         }
6451 }
6452
6453 #define RETRY 1
6454 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6455                                        struct intel_crtc_state *pipe_config)
6456 {
6457         struct drm_device *dev = intel_crtc->base.dev;
6458         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6459         int lane, link_bw, fdi_dotclock, ret;
6460         bool needs_recompute = false;
6461
6462 retry:
6463         /* FDI is a binary signal running at ~2.7GHz, encoding
6464          * each output octet as 10 bits. The actual frequency
6465          * is stored as a divider into a 100MHz clock, and the
6466          * mode pixel clock is stored in units of 1KHz.
6467          * Hence the bw of each lane in terms of the mode signal
6468          * is:
6469          */
6470         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6471
6472         fdi_dotclock = adjusted_mode->crtc_clock;
6473
6474         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6475                                            pipe_config->pipe_bpp);
6476
6477         pipe_config->fdi_lanes = lane;
6478
6479         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6480                                link_bw, &pipe_config->fdi_m_n);
6481
6482         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6483                                        intel_crtc->pipe, pipe_config);
6484         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6485                 pipe_config->pipe_bpp -= 2*3;
6486                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6487                               pipe_config->pipe_bpp);
6488                 needs_recompute = true;
6489                 pipe_config->bw_constrained = true;
6490
6491                 goto retry;
6492         }
6493
6494         if (needs_recompute)
6495                 return RETRY;
6496
6497         return ret;
6498 }
6499
6500 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6501                                      struct intel_crtc_state *pipe_config)
6502 {
6503         if (pipe_config->pipe_bpp > 24)
6504                 return false;
6505
6506         /* HSW can handle pixel rate up to cdclk? */
6507         if (IS_HASWELL(dev_priv->dev))
6508                 return true;
6509
6510         /*
6511          * We compare against max which means we must take
6512          * the increased cdclk requirement into account when
6513          * calculating the new cdclk.
6514          *
6515          * Should measure whether using a lower cdclk w/o IPS
6516          */
6517         return ilk_pipe_pixel_rate(pipe_config) <=
6518                 dev_priv->max_cdclk_freq * 95 / 100;
6519 }
6520
6521 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6522                                    struct intel_crtc_state *pipe_config)
6523 {
6524         struct drm_device *dev = crtc->base.dev;
6525         struct drm_i915_private *dev_priv = dev->dev_private;
6526
6527         pipe_config->ips_enabled = i915.enable_ips &&
6528                 hsw_crtc_supports_ips(crtc) &&
6529                 pipe_config_supports_ips(dev_priv, pipe_config);
6530 }
6531
6532 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6533                                      struct intel_crtc_state *pipe_config)
6534 {
6535         struct drm_device *dev = crtc->base.dev;
6536         struct drm_i915_private *dev_priv = dev->dev_private;
6537         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6538
6539         /* FIXME should check pixel clock limits on all platforms */
6540         if (INTEL_INFO(dev)->gen < 4) {
6541                 int clock_limit = dev_priv->max_cdclk_freq;
6542
6543                 /*
6544                  * Enable pixel doubling when the dot clock
6545                  * is > 90% of the (display) core speed.
6546                  *
6547                  * GDG double wide on either pipe,
6548                  * otherwise pipe A only.
6549                  */
6550                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6551                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6552                         clock_limit *= 2;
6553                         pipe_config->double_wide = true;
6554                 }
6555
6556                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6557                         return -EINVAL;
6558         }
6559
6560         /*
6561          * Pipe horizontal size must be even in:
6562          * - DVO ganged mode
6563          * - LVDS dual channel mode
6564          * - Double wide pipe
6565          */
6566         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6567              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6568                 pipe_config->pipe_src_w &= ~1;
6569
6570         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6571          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6572          */
6573         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6574                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6575                 return -EINVAL;
6576
6577         if (HAS_IPS(dev))
6578                 hsw_compute_ips_config(crtc, pipe_config);
6579
6580         if (pipe_config->has_pch_encoder)
6581                 return ironlake_fdi_compute_config(crtc, pipe_config);
6582
6583         return 0;
6584 }
6585
6586 static int skylake_get_display_clock_speed(struct drm_device *dev)
6587 {
6588         struct drm_i915_private *dev_priv = to_i915(dev);
6589         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6590         uint32_t cdctl = I915_READ(CDCLK_CTL);
6591         uint32_t linkrate;
6592
6593         if (!(lcpll1 & LCPLL_PLL_ENABLE))
6594                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6595
6596         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6597                 return 540000;
6598
6599         linkrate = (I915_READ(DPLL_CTRL1) &
6600                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6601
6602         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6603             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6604                 /* vco 8640 */
6605                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6606                 case CDCLK_FREQ_450_432:
6607                         return 432000;
6608                 case CDCLK_FREQ_337_308:
6609                         return 308570;
6610                 case CDCLK_FREQ_675_617:
6611                         return 617140;
6612                 default:
6613                         WARN(1, "Unknown cd freq selection\n");
6614                 }
6615         } else {
6616                 /* vco 8100 */
6617                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6618                 case CDCLK_FREQ_450_432:
6619                         return 450000;
6620                 case CDCLK_FREQ_337_308:
6621                         return 337500;
6622                 case CDCLK_FREQ_675_617:
6623                         return 675000;
6624                 default:
6625                         WARN(1, "Unknown cd freq selection\n");
6626                 }
6627         }
6628
6629         /* error case, do as if DPLL0 isn't enabled */
6630         return 24000;
6631 }
6632
6633 static int broxton_get_display_clock_speed(struct drm_device *dev)
6634 {
6635         struct drm_i915_private *dev_priv = to_i915(dev);
6636         uint32_t cdctl = I915_READ(CDCLK_CTL);
6637         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6638         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6639         int cdclk;
6640
6641         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6642                 return 19200;
6643
6644         cdclk = 19200 * pll_ratio / 2;
6645
6646         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6647         case BXT_CDCLK_CD2X_DIV_SEL_1:
6648                 return cdclk;  /* 576MHz or 624MHz */
6649         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6650                 return cdclk * 2 / 3; /* 384MHz */
6651         case BXT_CDCLK_CD2X_DIV_SEL_2:
6652                 return cdclk / 2; /* 288MHz */
6653         case BXT_CDCLK_CD2X_DIV_SEL_4:
6654                 return cdclk / 4; /* 144MHz */
6655         }
6656
6657         /* error case, do as if DE PLL isn't enabled */
6658         return 19200;
6659 }
6660
6661 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6662 {
6663         struct drm_i915_private *dev_priv = dev->dev_private;
6664         uint32_t lcpll = I915_READ(LCPLL_CTL);
6665         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6666
6667         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6668                 return 800000;
6669         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6670                 return 450000;
6671         else if (freq == LCPLL_CLK_FREQ_450)
6672                 return 450000;
6673         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6674                 return 540000;
6675         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6676                 return 337500;
6677         else
6678                 return 675000;
6679 }
6680
6681 static int haswell_get_display_clock_speed(struct drm_device *dev)
6682 {
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         uint32_t lcpll = I915_READ(LCPLL_CTL);
6685         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6686
6687         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6688                 return 800000;
6689         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6690                 return 450000;
6691         else if (freq == LCPLL_CLK_FREQ_450)
6692                 return 450000;
6693         else if (IS_HSW_ULT(dev))
6694                 return 337500;
6695         else
6696                 return 540000;
6697 }
6698
6699 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6700 {
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         u32 val;
6703         int divider;
6704
6705         if (dev_priv->hpll_freq == 0)
6706                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6707
6708         mutex_lock(&dev_priv->sb_lock);
6709         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6710         mutex_unlock(&dev_priv->sb_lock);
6711
6712         divider = val & DISPLAY_FREQUENCY_VALUES;
6713
6714         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6715              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6716              "cdclk change in progress\n");
6717
6718         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6719 }
6720
6721 static int ilk_get_display_clock_speed(struct drm_device *dev)
6722 {
6723         return 450000;
6724 }
6725
6726 static int i945_get_display_clock_speed(struct drm_device *dev)
6727 {
6728         return 400000;
6729 }
6730
6731 static int i915_get_display_clock_speed(struct drm_device *dev)
6732 {
6733         return 333333;
6734 }
6735
6736 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6737 {
6738         return 200000;
6739 }
6740
6741 static int pnv_get_display_clock_speed(struct drm_device *dev)
6742 {
6743         u16 gcfgc = 0;
6744
6745         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6746
6747         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6748         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6749                 return 266667;
6750         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6751                 return 333333;
6752         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6753                 return 444444;
6754         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6755                 return 200000;
6756         default:
6757                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6758         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6759                 return 133333;
6760         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6761                 return 166667;
6762         }
6763 }
6764
6765 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6766 {
6767         u16 gcfgc = 0;
6768
6769         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6770
6771         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6772                 return 133333;
6773         else {
6774                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6775                 case GC_DISPLAY_CLOCK_333_MHZ:
6776                         return 333333;
6777                 default:
6778                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6779                         return 190000;
6780                 }
6781         }
6782 }
6783
6784 static int i865_get_display_clock_speed(struct drm_device *dev)
6785 {
6786         return 266667;
6787 }
6788
6789 static int i85x_get_display_clock_speed(struct drm_device *dev)
6790 {
6791         u16 hpllcc = 0;
6792
6793         /*
6794          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6795          * encoding is different :(
6796          * FIXME is this the right way to detect 852GM/852GMV?
6797          */
6798         if (dev->pdev->revision == 0x1)
6799                 return 133333;
6800
6801         pci_bus_read_config_word(dev->pdev->bus,
6802                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6803
6804         /* Assume that the hardware is in the high speed state.  This
6805          * should be the default.
6806          */
6807         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6808         case GC_CLOCK_133_200:
6809         case GC_CLOCK_133_200_2:
6810         case GC_CLOCK_100_200:
6811                 return 200000;
6812         case GC_CLOCK_166_250:
6813                 return 250000;
6814         case GC_CLOCK_100_133:
6815                 return 133333;
6816         case GC_CLOCK_133_266:
6817         case GC_CLOCK_133_266_2:
6818         case GC_CLOCK_166_266:
6819                 return 266667;
6820         }
6821
6822         /* Shouldn't happen */
6823         return 0;
6824 }
6825
6826 static int i830_get_display_clock_speed(struct drm_device *dev)
6827 {
6828         return 133333;
6829 }
6830
6831 static unsigned int intel_hpll_vco(struct drm_device *dev)
6832 {
6833         struct drm_i915_private *dev_priv = dev->dev_private;
6834         static const unsigned int blb_vco[8] = {
6835                 [0] = 3200000,
6836                 [1] = 4000000,
6837                 [2] = 5333333,
6838                 [3] = 4800000,
6839                 [4] = 6400000,
6840         };
6841         static const unsigned int pnv_vco[8] = {
6842                 [0] = 3200000,
6843                 [1] = 4000000,
6844                 [2] = 5333333,
6845                 [3] = 4800000,
6846                 [4] = 2666667,
6847         };
6848         static const unsigned int cl_vco[8] = {
6849                 [0] = 3200000,
6850                 [1] = 4000000,
6851                 [2] = 5333333,
6852                 [3] = 6400000,
6853                 [4] = 3333333,
6854                 [5] = 3566667,
6855                 [6] = 4266667,
6856         };
6857         static const unsigned int elk_vco[8] = {
6858                 [0] = 3200000,
6859                 [1] = 4000000,
6860                 [2] = 5333333,
6861                 [3] = 4800000,
6862         };
6863         static const unsigned int ctg_vco[8] = {
6864                 [0] = 3200000,
6865                 [1] = 4000000,
6866                 [2] = 5333333,
6867                 [3] = 6400000,
6868                 [4] = 2666667,
6869                 [5] = 4266667,
6870         };
6871         const unsigned int *vco_table;
6872         unsigned int vco;
6873         uint8_t tmp = 0;
6874
6875         /* FIXME other chipsets? */
6876         if (IS_GM45(dev))
6877                 vco_table = ctg_vco;
6878         else if (IS_G4X(dev))
6879                 vco_table = elk_vco;
6880         else if (IS_CRESTLINE(dev))
6881                 vco_table = cl_vco;
6882         else if (IS_PINEVIEW(dev))
6883                 vco_table = pnv_vco;
6884         else if (IS_G33(dev))
6885                 vco_table = blb_vco;
6886         else
6887                 return 0;
6888
6889         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6890
6891         vco = vco_table[tmp & 0x7];
6892         if (vco == 0)
6893                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6894         else
6895                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6896
6897         return vco;
6898 }
6899
6900 static int gm45_get_display_clock_speed(struct drm_device *dev)
6901 {
6902         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6903         uint16_t tmp = 0;
6904
6905         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6906
6907         cdclk_sel = (tmp >> 12) & 0x1;
6908
6909         switch (vco) {
6910         case 2666667:
6911         case 4000000:
6912         case 5333333:
6913                 return cdclk_sel ? 333333 : 222222;
6914         case 3200000:
6915                 return cdclk_sel ? 320000 : 228571;
6916         default:
6917                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6918                 return 222222;
6919         }
6920 }
6921
6922 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6923 {
6924         static const uint8_t div_3200[] = { 16, 10,  8 };
6925         static const uint8_t div_4000[] = { 20, 12, 10 };
6926         static const uint8_t div_5333[] = { 24, 16, 14 };
6927         const uint8_t *div_table;
6928         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6929         uint16_t tmp = 0;
6930
6931         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6932
6933         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6934
6935         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6936                 goto fail;
6937
6938         switch (vco) {
6939         case 3200000:
6940                 div_table = div_3200;
6941                 break;
6942         case 4000000:
6943                 div_table = div_4000;
6944                 break;
6945         case 5333333:
6946                 div_table = div_5333;
6947                 break;
6948         default:
6949                 goto fail;
6950         }
6951
6952         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6953
6954 fail:
6955         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6956         return 200000;
6957 }
6958
6959 static int g33_get_display_clock_speed(struct drm_device *dev)
6960 {
6961         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6962         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6963         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6964         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6965         const uint8_t *div_table;
6966         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6967         uint16_t tmp = 0;
6968
6969         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6970
6971         cdclk_sel = (tmp >> 4) & 0x7;
6972
6973         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6974                 goto fail;
6975
6976         switch (vco) {
6977         case 3200000:
6978                 div_table = div_3200;
6979                 break;
6980         case 4000000:
6981                 div_table = div_4000;
6982                 break;
6983         case 4800000:
6984                 div_table = div_4800;
6985                 break;
6986         case 5333333:
6987                 div_table = div_5333;
6988                 break;
6989         default:
6990                 goto fail;
6991         }
6992
6993         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6994
6995 fail:
6996         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6997         return 190476;
6998 }
6999
7000 static void
7001 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7002 {
7003         while (*num > DATA_LINK_M_N_MASK ||
7004                *den > DATA_LINK_M_N_MASK) {
7005                 *num >>= 1;
7006                 *den >>= 1;
7007         }
7008 }
7009
7010 static void compute_m_n(unsigned int m, unsigned int n,
7011                         uint32_t *ret_m, uint32_t *ret_n)
7012 {
7013         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7014         *ret_m = div_u64((uint64_t) m * *ret_n, n);
7015         intel_reduce_m_n_ratio(ret_m, ret_n);
7016 }
7017
7018 void
7019 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7020                        int pixel_clock, int link_clock,
7021                        struct intel_link_m_n *m_n)
7022 {
7023         m_n->tu = 64;
7024
7025         compute_m_n(bits_per_pixel * pixel_clock,
7026                     link_clock * nlanes * 8,
7027                     &m_n->gmch_m, &m_n->gmch_n);
7028
7029         compute_m_n(pixel_clock, link_clock,
7030                     &m_n->link_m, &m_n->link_n);
7031 }
7032
7033 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7034 {
7035         if (i915.panel_use_ssc >= 0)
7036                 return i915.panel_use_ssc != 0;
7037         return dev_priv->vbt.lvds_use_ssc
7038                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7039 }
7040
7041 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7042                            int num_connectors)
7043 {
7044         struct drm_device *dev = crtc_state->base.crtc->dev;
7045         struct drm_i915_private *dev_priv = dev->dev_private;
7046         int refclk;
7047
7048         WARN_ON(!crtc_state->base.state);
7049
7050         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7051                 refclk = 100000;
7052         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7053             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7054                 refclk = dev_priv->vbt.lvds_ssc_freq;
7055                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7056         } else if (!IS_GEN2(dev)) {
7057                 refclk = 96000;
7058         } else {
7059                 refclk = 48000;
7060         }
7061
7062         return refclk;
7063 }
7064
7065 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7066 {
7067         return (1 << dpll->n) << 16 | dpll->m2;
7068 }
7069
7070 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7071 {
7072         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7073 }
7074
7075 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7076                                      struct intel_crtc_state *crtc_state,
7077                                      intel_clock_t *reduced_clock)
7078 {
7079         struct drm_device *dev = crtc->base.dev;
7080         u32 fp, fp2 = 0;
7081
7082         if (IS_PINEVIEW(dev)) {
7083                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7084                 if (reduced_clock)
7085                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7086         } else {
7087                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7088                 if (reduced_clock)
7089                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7090         }
7091
7092         crtc_state->dpll_hw_state.fp0 = fp;
7093
7094         crtc->lowfreq_avail = false;
7095         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7096             reduced_clock) {
7097                 crtc_state->dpll_hw_state.fp1 = fp2;
7098                 crtc->lowfreq_avail = true;
7099         } else {
7100                 crtc_state->dpll_hw_state.fp1 = fp;
7101         }
7102 }
7103
7104 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7105                 pipe)
7106 {
7107         u32 reg_val;
7108
7109         /*
7110          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7111          * and set it to a reasonable value instead.
7112          */
7113         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7114         reg_val &= 0xffffff00;
7115         reg_val |= 0x00000030;
7116         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7117
7118         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7119         reg_val &= 0x8cffffff;
7120         reg_val = 0x8c000000;
7121         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7122
7123         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7124         reg_val &= 0xffffff00;
7125         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7126
7127         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7128         reg_val &= 0x00ffffff;
7129         reg_val |= 0xb0000000;
7130         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7131 }
7132
7133 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7134                                          struct intel_link_m_n *m_n)
7135 {
7136         struct drm_device *dev = crtc->base.dev;
7137         struct drm_i915_private *dev_priv = dev->dev_private;
7138         int pipe = crtc->pipe;
7139
7140         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7141         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7142         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7143         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7144 }
7145
7146 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7147                                          struct intel_link_m_n *m_n,
7148                                          struct intel_link_m_n *m2_n2)
7149 {
7150         struct drm_device *dev = crtc->base.dev;
7151         struct drm_i915_private *dev_priv = dev->dev_private;
7152         int pipe = crtc->pipe;
7153         enum transcoder transcoder = crtc->config->cpu_transcoder;
7154
7155         if (INTEL_INFO(dev)->gen >= 5) {
7156                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7157                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7158                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7159                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7160                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7161                  * for gen < 8) and if DRRS is supported (to make sure the
7162                  * registers are not unnecessarily accessed).
7163                  */
7164                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7165                         crtc->config->has_drrs) {
7166                         I915_WRITE(PIPE_DATA_M2(transcoder),
7167                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7168                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7169                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7170                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7171                 }
7172         } else {
7173                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7175                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7176                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7177         }
7178 }
7179
7180 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7181 {
7182         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7183
7184         if (m_n == M1_N1) {
7185                 dp_m_n = &crtc->config->dp_m_n;
7186                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7187         } else if (m_n == M2_N2) {
7188
7189                 /*
7190                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7191                  * needs to be programmed into M1_N1.
7192                  */
7193                 dp_m_n = &crtc->config->dp_m2_n2;
7194         } else {
7195                 DRM_ERROR("Unsupported divider value\n");
7196                 return;
7197         }
7198
7199         if (crtc->config->has_pch_encoder)
7200                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7201         else
7202                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7203 }
7204
7205 static void vlv_compute_dpll(struct intel_crtc *crtc,
7206                              struct intel_crtc_state *pipe_config)
7207 {
7208         u32 dpll, dpll_md;
7209
7210         /*
7211          * Enable DPIO clock input. We should never disable the reference
7212          * clock for pipe B, since VGA hotplug / manual detection depends
7213          * on it.
7214          */
7215         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7216                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7217         /* We should never disable this, set it here for state tracking */
7218         if (crtc->pipe == PIPE_B)
7219                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7220         dpll |= DPLL_VCO_ENABLE;
7221         pipe_config->dpll_hw_state.dpll = dpll;
7222
7223         dpll_md = (pipe_config->pixel_multiplier - 1)
7224                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7225         pipe_config->dpll_hw_state.dpll_md = dpll_md;
7226 }
7227
7228 static void vlv_prepare_pll(struct intel_crtc *crtc,
7229                             const struct intel_crtc_state *pipe_config)
7230 {
7231         struct drm_device *dev = crtc->base.dev;
7232         struct drm_i915_private *dev_priv = dev->dev_private;
7233         int pipe = crtc->pipe;
7234         u32 mdiv;
7235         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7236         u32 coreclk, reg_val;
7237
7238         mutex_lock(&dev_priv->sb_lock);
7239
7240         bestn = pipe_config->dpll.n;
7241         bestm1 = pipe_config->dpll.m1;
7242         bestm2 = pipe_config->dpll.m2;
7243         bestp1 = pipe_config->dpll.p1;
7244         bestp2 = pipe_config->dpll.p2;
7245
7246         /* See eDP HDMI DPIO driver vbios notes doc */
7247
7248         /* PLL B needs special handling */
7249         if (pipe == PIPE_B)
7250                 vlv_pllb_recal_opamp(dev_priv, pipe);
7251
7252         /* Set up Tx target for periodic Rcomp update */
7253         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7254
7255         /* Disable target IRef on PLL */
7256         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7257         reg_val &= 0x00ffffff;
7258         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7259
7260         /* Disable fast lock */
7261         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7262
7263         /* Set idtafcrecal before PLL is enabled */
7264         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7265         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7266         mdiv |= ((bestn << DPIO_N_SHIFT));
7267         mdiv |= (1 << DPIO_K_SHIFT);
7268
7269         /*
7270          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7271          * but we don't support that).
7272          * Note: don't use the DAC post divider as it seems unstable.
7273          */
7274         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7275         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7276
7277         mdiv |= DPIO_ENABLE_CALIBRATION;
7278         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7279
7280         /* Set HBR and RBR LPF coefficients */
7281         if (pipe_config->port_clock == 162000 ||
7282             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7283             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7284                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7285                                  0x009f0003);
7286         else
7287                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7288                                  0x00d0000f);
7289
7290         if (pipe_config->has_dp_encoder) {
7291                 /* Use SSC source */
7292                 if (pipe == PIPE_A)
7293                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7294                                          0x0df40000);
7295                 else
7296                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7297                                          0x0df70000);
7298         } else { /* HDMI or VGA */
7299                 /* Use bend source */
7300                 if (pipe == PIPE_A)
7301                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7302                                          0x0df70000);
7303                 else
7304                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7305                                          0x0df40000);
7306         }
7307
7308         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7309         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7310         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7311             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7312                 coreclk |= 0x01000000;
7313         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7314
7315         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7316         mutex_unlock(&dev_priv->sb_lock);
7317 }
7318
7319 static void chv_compute_dpll(struct intel_crtc *crtc,
7320                              struct intel_crtc_state *pipe_config)
7321 {
7322         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7323                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7324                 DPLL_VCO_ENABLE;
7325         if (crtc->pipe != PIPE_A)
7326                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7327
7328         pipe_config->dpll_hw_state.dpll_md =
7329                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7330 }
7331
7332 static void chv_prepare_pll(struct intel_crtc *crtc,
7333                             const struct intel_crtc_state *pipe_config)
7334 {
7335         struct drm_device *dev = crtc->base.dev;
7336         struct drm_i915_private *dev_priv = dev->dev_private;
7337         int pipe = crtc->pipe;
7338         int dpll_reg = DPLL(crtc->pipe);
7339         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7340         u32 loopfilter, tribuf_calcntr;
7341         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7342         u32 dpio_val;
7343         int vco;
7344
7345         bestn = pipe_config->dpll.n;
7346         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7347         bestm1 = pipe_config->dpll.m1;
7348         bestm2 = pipe_config->dpll.m2 >> 22;
7349         bestp1 = pipe_config->dpll.p1;
7350         bestp2 = pipe_config->dpll.p2;
7351         vco = pipe_config->dpll.vco;
7352         dpio_val = 0;
7353         loopfilter = 0;
7354
7355         /*
7356          * Enable Refclk and SSC
7357          */
7358         I915_WRITE(dpll_reg,
7359                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7360
7361         mutex_lock(&dev_priv->sb_lock);
7362
7363         /* p1 and p2 divider */
7364         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7365                         5 << DPIO_CHV_S1_DIV_SHIFT |
7366                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7367                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7368                         1 << DPIO_CHV_K_DIV_SHIFT);
7369
7370         /* Feedback post-divider - m2 */
7371         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7372
7373         /* Feedback refclk divider - n and m1 */
7374         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7375                         DPIO_CHV_M1_DIV_BY_2 |
7376                         1 << DPIO_CHV_N_DIV_SHIFT);
7377
7378         /* M2 fraction division */
7379         if (bestm2_frac)
7380                 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7381
7382         /* M2 fraction division enable */
7383         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7384         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7385         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7386         if (bestm2_frac)
7387                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7388         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7389
7390         /* Program digital lock detect threshold */
7391         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7392         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7393                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7394         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7395         if (!bestm2_frac)
7396                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7397         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7398
7399         /* Loop filter */
7400         if (vco == 5400000) {
7401                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7402                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7403                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7404                 tribuf_calcntr = 0x9;
7405         } else if (vco <= 6200000) {
7406                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7407                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7408                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409                 tribuf_calcntr = 0x9;
7410         } else if (vco <= 6480000) {
7411                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7412                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7413                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414                 tribuf_calcntr = 0x8;
7415         } else {
7416                 /* Not supported. Apply the same limits as in the max case */
7417                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7418                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7419                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7420                 tribuf_calcntr = 0;
7421         }
7422         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7423
7424         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7425         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7426         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7427         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7428
7429         /* AFC Recal */
7430         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7431                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7432                         DPIO_AFC_RECAL);
7433
7434         mutex_unlock(&dev_priv->sb_lock);
7435 }
7436
7437 /**
7438  * vlv_force_pll_on - forcibly enable just the PLL
7439  * @dev_priv: i915 private structure
7440  * @pipe: pipe PLL to enable
7441  * @dpll: PLL configuration
7442  *
7443  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7444  * in cases where we need the PLL enabled even when @pipe is not going to
7445  * be enabled.
7446  */
7447 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7448                       const struct dpll *dpll)
7449 {
7450         struct intel_crtc *crtc =
7451                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7452         struct intel_crtc_state pipe_config = {
7453                 .base.crtc = &crtc->base,
7454                 .pixel_multiplier = 1,
7455                 .dpll = *dpll,
7456         };
7457
7458         if (IS_CHERRYVIEW(dev)) {
7459                 chv_compute_dpll(crtc, &pipe_config);
7460                 chv_prepare_pll(crtc, &pipe_config);
7461                 chv_enable_pll(crtc, &pipe_config);
7462         } else {
7463                 vlv_compute_dpll(crtc, &pipe_config);
7464                 vlv_prepare_pll(crtc, &pipe_config);
7465                 vlv_enable_pll(crtc, &pipe_config);
7466         }
7467 }
7468
7469 /**
7470  * vlv_force_pll_off - forcibly disable just the PLL
7471  * @dev_priv: i915 private structure
7472  * @pipe: pipe PLL to disable
7473  *
7474  * Disable the PLL for @pipe. To be used in cases where we need
7475  * the PLL enabled even when @pipe is not going to be enabled.
7476  */
7477 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7478 {
7479         if (IS_CHERRYVIEW(dev))
7480                 chv_disable_pll(to_i915(dev), pipe);
7481         else
7482                 vlv_disable_pll(to_i915(dev), pipe);
7483 }
7484
7485 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7486                               struct intel_crtc_state *crtc_state,
7487                               intel_clock_t *reduced_clock,
7488                               int num_connectors)
7489 {
7490         struct drm_device *dev = crtc->base.dev;
7491         struct drm_i915_private *dev_priv = dev->dev_private;
7492         u32 dpll;
7493         bool is_sdvo;
7494         struct dpll *clock = &crtc_state->dpll;
7495
7496         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7497
7498         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7499                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7500
7501         dpll = DPLL_VGA_MODE_DIS;
7502
7503         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7504                 dpll |= DPLLB_MODE_LVDS;
7505         else
7506                 dpll |= DPLLB_MODE_DAC_SERIAL;
7507
7508         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7509                 dpll |= (crtc_state->pixel_multiplier - 1)
7510                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7511         }
7512
7513         if (is_sdvo)
7514                 dpll |= DPLL_SDVO_HIGH_SPEED;
7515
7516         if (crtc_state->has_dp_encoder)
7517                 dpll |= DPLL_SDVO_HIGH_SPEED;
7518
7519         /* compute bitmask from p1 value */
7520         if (IS_PINEVIEW(dev))
7521                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7522         else {
7523                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7524                 if (IS_G4X(dev) && reduced_clock)
7525                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7526         }
7527         switch (clock->p2) {
7528         case 5:
7529                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7530                 break;
7531         case 7:
7532                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7533                 break;
7534         case 10:
7535                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7536                 break;
7537         case 14:
7538                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7539                 break;
7540         }
7541         if (INTEL_INFO(dev)->gen >= 4)
7542                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7543
7544         if (crtc_state->sdvo_tv_clock)
7545                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7546         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7547                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7548                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7549         else
7550                 dpll |= PLL_REF_INPUT_DREFCLK;
7551
7552         dpll |= DPLL_VCO_ENABLE;
7553         crtc_state->dpll_hw_state.dpll = dpll;
7554
7555         if (INTEL_INFO(dev)->gen >= 4) {
7556                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7557                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7558                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7559         }
7560 }
7561
7562 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7563                               struct intel_crtc_state *crtc_state,
7564                               intel_clock_t *reduced_clock,
7565                               int num_connectors)
7566 {
7567         struct drm_device *dev = crtc->base.dev;
7568         struct drm_i915_private *dev_priv = dev->dev_private;
7569         u32 dpll;
7570         struct dpll *clock = &crtc_state->dpll;
7571
7572         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7573
7574         dpll = DPLL_VGA_MODE_DIS;
7575
7576         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7577                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578         } else {
7579                 if (clock->p1 == 2)
7580                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7581                 else
7582                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7583                 if (clock->p2 == 4)
7584                         dpll |= PLL_P2_DIVIDE_BY_4;
7585         }
7586
7587         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7588                 dpll |= DPLL_DVO_2X_MODE;
7589
7590         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7591                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7592                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7593         else
7594                 dpll |= PLL_REF_INPUT_DREFCLK;
7595
7596         dpll |= DPLL_VCO_ENABLE;
7597         crtc_state->dpll_hw_state.dpll = dpll;
7598 }
7599
7600 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7601 {
7602         struct drm_device *dev = intel_crtc->base.dev;
7603         struct drm_i915_private *dev_priv = dev->dev_private;
7604         enum pipe pipe = intel_crtc->pipe;
7605         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7606         struct drm_display_mode *adjusted_mode =
7607                 &intel_crtc->config->base.adjusted_mode;
7608         uint32_t crtc_vtotal, crtc_vblank_end;
7609         int vsyncshift = 0;
7610
7611         /* We need to be careful not to changed the adjusted mode, for otherwise
7612          * the hw state checker will get angry at the mismatch. */
7613         crtc_vtotal = adjusted_mode->crtc_vtotal;
7614         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7615
7616         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7617                 /* the chip adds 2 halflines automatically */
7618                 crtc_vtotal -= 1;
7619                 crtc_vblank_end -= 1;
7620
7621                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7622                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7623                 else
7624                         vsyncshift = adjusted_mode->crtc_hsync_start -
7625                                 adjusted_mode->crtc_htotal / 2;
7626                 if (vsyncshift < 0)
7627                         vsyncshift += adjusted_mode->crtc_htotal;
7628         }
7629
7630         if (INTEL_INFO(dev)->gen > 3)
7631                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7632
7633         I915_WRITE(HTOTAL(cpu_transcoder),
7634                    (adjusted_mode->crtc_hdisplay - 1) |
7635                    ((adjusted_mode->crtc_htotal - 1) << 16));
7636         I915_WRITE(HBLANK(cpu_transcoder),
7637                    (adjusted_mode->crtc_hblank_start - 1) |
7638                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7639         I915_WRITE(HSYNC(cpu_transcoder),
7640                    (adjusted_mode->crtc_hsync_start - 1) |
7641                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7642
7643         I915_WRITE(VTOTAL(cpu_transcoder),
7644                    (adjusted_mode->crtc_vdisplay - 1) |
7645                    ((crtc_vtotal - 1) << 16));
7646         I915_WRITE(VBLANK(cpu_transcoder),
7647                    (adjusted_mode->crtc_vblank_start - 1) |
7648                    ((crtc_vblank_end - 1) << 16));
7649         I915_WRITE(VSYNC(cpu_transcoder),
7650                    (adjusted_mode->crtc_vsync_start - 1) |
7651                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7652
7653         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7654          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7655          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7656          * bits. */
7657         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7658             (pipe == PIPE_B || pipe == PIPE_C))
7659                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7660
7661         /* pipesrc controls the size that is scaled from, which should
7662          * always be the user's requested size.
7663          */
7664         I915_WRITE(PIPESRC(pipe),
7665                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7666                    (intel_crtc->config->pipe_src_h - 1));
7667 }
7668
7669 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7670                                    struct intel_crtc_state *pipe_config)
7671 {
7672         struct drm_device *dev = crtc->base.dev;
7673         struct drm_i915_private *dev_priv = dev->dev_private;
7674         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7675         uint32_t tmp;
7676
7677         tmp = I915_READ(HTOTAL(cpu_transcoder));
7678         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7679         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7680         tmp = I915_READ(HBLANK(cpu_transcoder));
7681         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7682         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7683         tmp = I915_READ(HSYNC(cpu_transcoder));
7684         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7685         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7686
7687         tmp = I915_READ(VTOTAL(cpu_transcoder));
7688         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7689         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7690         tmp = I915_READ(VBLANK(cpu_transcoder));
7691         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7692         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7693         tmp = I915_READ(VSYNC(cpu_transcoder));
7694         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7695         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7696
7697         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7698                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7699                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7700                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7701         }
7702
7703         tmp = I915_READ(PIPESRC(crtc->pipe));
7704         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7705         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7706
7707         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7708         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7709 }
7710
7711 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7712                                  struct intel_crtc_state *pipe_config)
7713 {
7714         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7715         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7716         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7717         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7718
7719         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7720         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7721         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7722         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7723
7724         mode->flags = pipe_config->base.adjusted_mode.flags;
7725         mode->type = DRM_MODE_TYPE_DRIVER;
7726
7727         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7728         mode->flags |= pipe_config->base.adjusted_mode.flags;
7729
7730         mode->hsync = drm_mode_hsync(mode);
7731         mode->vrefresh = drm_mode_vrefresh(mode);
7732         drm_mode_set_name(mode);
7733 }
7734
7735 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7736 {
7737         struct drm_device *dev = intel_crtc->base.dev;
7738         struct drm_i915_private *dev_priv = dev->dev_private;
7739         uint32_t pipeconf;
7740
7741         pipeconf = 0;
7742
7743         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7744             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7745                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7746
7747         if (intel_crtc->config->double_wide)
7748                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7749
7750         /* only g4x and later have fancy bpc/dither controls */
7751         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7752                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7753                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7754                         pipeconf |= PIPECONF_DITHER_EN |
7755                                     PIPECONF_DITHER_TYPE_SP;
7756
7757                 switch (intel_crtc->config->pipe_bpp) {
7758                 case 18:
7759                         pipeconf |= PIPECONF_6BPC;
7760                         break;
7761                 case 24:
7762                         pipeconf |= PIPECONF_8BPC;
7763                         break;
7764                 case 30:
7765                         pipeconf |= PIPECONF_10BPC;
7766                         break;
7767                 default:
7768                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7769                         BUG();
7770                 }
7771         }
7772
7773         if (HAS_PIPE_CXSR(dev)) {
7774                 if (intel_crtc->lowfreq_avail) {
7775                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7776                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7777                 } else {
7778                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7779                 }
7780         }
7781
7782         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7783                 if (INTEL_INFO(dev)->gen < 4 ||
7784                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7785                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7786                 else
7787                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7788         } else
7789                 pipeconf |= PIPECONF_PROGRESSIVE;
7790
7791         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7792                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7793
7794         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7795         POSTING_READ(PIPECONF(intel_crtc->pipe));
7796 }
7797
7798 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7799                                    struct intel_crtc_state *crtc_state)
7800 {
7801         struct drm_device *dev = crtc->base.dev;
7802         struct drm_i915_private *dev_priv = dev->dev_private;
7803         int refclk, num_connectors = 0;
7804         intel_clock_t clock;
7805         bool ok;
7806         bool is_dsi = false;
7807         struct intel_encoder *encoder;
7808         const intel_limit_t *limit;
7809         struct drm_atomic_state *state = crtc_state->base.state;
7810         struct drm_connector *connector;
7811         struct drm_connector_state *connector_state;
7812         int i;
7813
7814         memset(&crtc_state->dpll_hw_state, 0,
7815                sizeof(crtc_state->dpll_hw_state));
7816
7817         for_each_connector_in_state(state, connector, connector_state, i) {
7818                 if (connector_state->crtc != &crtc->base)
7819                         continue;
7820
7821                 encoder = to_intel_encoder(connector_state->best_encoder);
7822
7823                 switch (encoder->type) {
7824                 case INTEL_OUTPUT_DSI:
7825                         is_dsi = true;
7826                         break;
7827                 default:
7828                         break;
7829                 }
7830
7831                 num_connectors++;
7832         }
7833
7834         if (is_dsi)
7835                 return 0;
7836
7837         if (!crtc_state->clock_set) {
7838                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7839
7840                 /*
7841                  * Returns a set of divisors for the desired target clock with
7842                  * the given refclk, or FALSE.  The returned values represent
7843                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7844                  * 2) / p1 / p2.
7845                  */
7846                 limit = intel_limit(crtc_state, refclk);
7847                 ok = dev_priv->display.find_dpll(limit, crtc_state,
7848                                                  crtc_state->port_clock,
7849                                                  refclk, NULL, &clock);
7850                 if (!ok) {
7851                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
7852                         return -EINVAL;
7853                 }
7854
7855                 /* Compat-code for transition, will disappear. */
7856                 crtc_state->dpll.n = clock.n;
7857                 crtc_state->dpll.m1 = clock.m1;
7858                 crtc_state->dpll.m2 = clock.m2;
7859                 crtc_state->dpll.p1 = clock.p1;
7860                 crtc_state->dpll.p2 = clock.p2;
7861         }
7862
7863         if (IS_GEN2(dev)) {
7864                 i8xx_compute_dpll(crtc, crtc_state, NULL,
7865                                   num_connectors);
7866         } else if (IS_CHERRYVIEW(dev)) {
7867                 chv_compute_dpll(crtc, crtc_state);
7868         } else if (IS_VALLEYVIEW(dev)) {
7869                 vlv_compute_dpll(crtc, crtc_state);
7870         } else {
7871                 i9xx_compute_dpll(crtc, crtc_state, NULL,
7872                                   num_connectors);
7873         }
7874
7875         return 0;
7876 }
7877
7878 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7879                                  struct intel_crtc_state *pipe_config)
7880 {
7881         struct drm_device *dev = crtc->base.dev;
7882         struct drm_i915_private *dev_priv = dev->dev_private;
7883         uint32_t tmp;
7884
7885         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7886                 return;
7887
7888         tmp = I915_READ(PFIT_CONTROL);
7889         if (!(tmp & PFIT_ENABLE))
7890                 return;
7891
7892         /* Check whether the pfit is attached to our pipe. */
7893         if (INTEL_INFO(dev)->gen < 4) {
7894                 if (crtc->pipe != PIPE_B)
7895                         return;
7896         } else {
7897                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7898                         return;
7899         }
7900
7901         pipe_config->gmch_pfit.control = tmp;
7902         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7903         if (INTEL_INFO(dev)->gen < 5)
7904                 pipe_config->gmch_pfit.lvds_border_bits =
7905                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7906 }
7907
7908 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7909                                struct intel_crtc_state *pipe_config)
7910 {
7911         struct drm_device *dev = crtc->base.dev;
7912         struct drm_i915_private *dev_priv = dev->dev_private;
7913         int pipe = pipe_config->cpu_transcoder;
7914         intel_clock_t clock;
7915         u32 mdiv;
7916         int refclk = 100000;
7917
7918         /* In case of MIPI DPLL will not even be used */
7919         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7920                 return;
7921
7922         mutex_lock(&dev_priv->sb_lock);
7923         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7924         mutex_unlock(&dev_priv->sb_lock);
7925
7926         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7927         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7928         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7929         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7930         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7931
7932         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7933 }
7934
7935 static void
7936 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7937                               struct intel_initial_plane_config *plane_config)
7938 {
7939         struct drm_device *dev = crtc->base.dev;
7940         struct drm_i915_private *dev_priv = dev->dev_private;
7941         u32 val, base, offset;
7942         int pipe = crtc->pipe, plane = crtc->plane;
7943         int fourcc, pixel_format;
7944         unsigned int aligned_height;
7945         struct drm_framebuffer *fb;
7946         struct intel_framebuffer *intel_fb;
7947
7948         val = I915_READ(DSPCNTR(plane));
7949         if (!(val & DISPLAY_PLANE_ENABLE))
7950                 return;
7951
7952         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7953         if (!intel_fb) {
7954                 DRM_DEBUG_KMS("failed to alloc fb\n");
7955                 return;
7956         }
7957
7958         fb = &intel_fb->base;
7959
7960         if (INTEL_INFO(dev)->gen >= 4) {
7961                 if (val & DISPPLANE_TILED) {
7962                         plane_config->tiling = I915_TILING_X;
7963                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7964                 }
7965         }
7966
7967         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7968         fourcc = i9xx_format_to_fourcc(pixel_format);
7969         fb->pixel_format = fourcc;
7970         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7971
7972         if (INTEL_INFO(dev)->gen >= 4) {
7973                 if (plane_config->tiling)
7974                         offset = I915_READ(DSPTILEOFF(plane));
7975                 else
7976                         offset = I915_READ(DSPLINOFF(plane));
7977                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7978         } else {
7979                 base = I915_READ(DSPADDR(plane));
7980         }
7981         plane_config->base = base;
7982
7983         val = I915_READ(PIPESRC(pipe));
7984         fb->width = ((val >> 16) & 0xfff) + 1;
7985         fb->height = ((val >> 0) & 0xfff) + 1;
7986
7987         val = I915_READ(DSPSTRIDE(pipe));
7988         fb->pitches[0] = val & 0xffffffc0;
7989
7990         aligned_height = intel_fb_align_height(dev, fb->height,
7991                                                fb->pixel_format,
7992                                                fb->modifier[0]);
7993
7994         plane_config->size = fb->pitches[0] * aligned_height;
7995
7996         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7997                       pipe_name(pipe), plane, fb->width, fb->height,
7998                       fb->bits_per_pixel, base, fb->pitches[0],
7999                       plane_config->size);
8000
8001         plane_config->fb = intel_fb;
8002 }
8003
8004 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8005                                struct intel_crtc_state *pipe_config)
8006 {
8007         struct drm_device *dev = crtc->base.dev;
8008         struct drm_i915_private *dev_priv = dev->dev_private;
8009         int pipe = pipe_config->cpu_transcoder;
8010         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8011         intel_clock_t clock;
8012         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8013         int refclk = 100000;
8014
8015         mutex_lock(&dev_priv->sb_lock);
8016         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8017         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8018         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8019         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8020         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8021         mutex_unlock(&dev_priv->sb_lock);
8022
8023         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8024         clock.m2 = (pll_dw0 & 0xff) << 22;
8025         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8026                 clock.m2 |= pll_dw2 & 0x3fffff;
8027         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8028         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8029         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8030
8031         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8032 }
8033
8034 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8035                                  struct intel_crtc_state *pipe_config)
8036 {
8037         struct drm_device *dev = crtc->base.dev;
8038         struct drm_i915_private *dev_priv = dev->dev_private;
8039         uint32_t tmp;
8040
8041         if (!intel_display_power_is_enabled(dev_priv,
8042                                             POWER_DOMAIN_PIPE(crtc->pipe)))
8043                 return false;
8044
8045         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8046         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8047
8048         tmp = I915_READ(PIPECONF(crtc->pipe));
8049         if (!(tmp & PIPECONF_ENABLE))
8050                 return false;
8051
8052         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8053                 switch (tmp & PIPECONF_BPC_MASK) {
8054                 case PIPECONF_6BPC:
8055                         pipe_config->pipe_bpp = 18;
8056                         break;
8057                 case PIPECONF_8BPC:
8058                         pipe_config->pipe_bpp = 24;
8059                         break;
8060                 case PIPECONF_10BPC:
8061                         pipe_config->pipe_bpp = 30;
8062                         break;
8063                 default:
8064                         break;
8065                 }
8066         }
8067
8068         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8069                 pipe_config->limited_color_range = true;
8070
8071         if (INTEL_INFO(dev)->gen < 4)
8072                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8073
8074         intel_get_pipe_timings(crtc, pipe_config);
8075
8076         i9xx_get_pfit_config(crtc, pipe_config);
8077
8078         if (INTEL_INFO(dev)->gen >= 4) {
8079                 tmp = I915_READ(DPLL_MD(crtc->pipe));
8080                 pipe_config->pixel_multiplier =
8081                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8082                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8083                 pipe_config->dpll_hw_state.dpll_md = tmp;
8084         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8085                 tmp = I915_READ(DPLL(crtc->pipe));
8086                 pipe_config->pixel_multiplier =
8087                         ((tmp & SDVO_MULTIPLIER_MASK)
8088                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8089         } else {
8090                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8091                  * port and will be fixed up in the encoder->get_config
8092                  * function. */
8093                 pipe_config->pixel_multiplier = 1;
8094         }
8095         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8096         if (!IS_VALLEYVIEW(dev)) {
8097                 /*
8098                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8099                  * on 830. Filter it out here so that we don't
8100                  * report errors due to that.
8101                  */
8102                 if (IS_I830(dev))
8103                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8104
8105                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8106                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8107         } else {
8108                 /* Mask out read-only status bits. */
8109                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8110                                                      DPLL_PORTC_READY_MASK |
8111                                                      DPLL_PORTB_READY_MASK);
8112         }
8113
8114         if (IS_CHERRYVIEW(dev))
8115                 chv_crtc_clock_get(crtc, pipe_config);
8116         else if (IS_VALLEYVIEW(dev))
8117                 vlv_crtc_clock_get(crtc, pipe_config);
8118         else
8119                 i9xx_crtc_clock_get(crtc, pipe_config);
8120
8121         return true;
8122 }
8123
8124 static void ironlake_init_pch_refclk(struct drm_device *dev)
8125 {
8126         struct drm_i915_private *dev_priv = dev->dev_private;
8127         struct intel_encoder *encoder;
8128         u32 val, final;
8129         bool has_lvds = false;
8130         bool has_cpu_edp = false;
8131         bool has_panel = false;
8132         bool has_ck505 = false;
8133         bool can_ssc = false;
8134
8135         /* We need to take the global config into account */
8136         for_each_intel_encoder(dev, encoder) {
8137                 switch (encoder->type) {
8138                 case INTEL_OUTPUT_LVDS:
8139                         has_panel = true;
8140                         has_lvds = true;
8141                         break;
8142                 case INTEL_OUTPUT_EDP:
8143                         has_panel = true;
8144                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8145                                 has_cpu_edp = true;
8146                         break;
8147                 default:
8148                         break;
8149                 }
8150         }
8151
8152         if (HAS_PCH_IBX(dev)) {
8153                 has_ck505 = dev_priv->vbt.display_clock_mode;
8154                 can_ssc = has_ck505;
8155         } else {
8156                 has_ck505 = false;
8157                 can_ssc = true;
8158         }
8159
8160         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8161                       has_panel, has_lvds, has_ck505);
8162
8163         /* Ironlake: try to setup display ref clock before DPLL
8164          * enabling. This is only under driver's control after
8165          * PCH B stepping, previous chipset stepping should be
8166          * ignoring this setting.
8167          */
8168         val = I915_READ(PCH_DREF_CONTROL);
8169
8170         /* As we must carefully and slowly disable/enable each source in turn,
8171          * compute the final state we want first and check if we need to
8172          * make any changes at all.
8173          */
8174         final = val;
8175         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8176         if (has_ck505)
8177                 final |= DREF_NONSPREAD_CK505_ENABLE;
8178         else
8179                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8180
8181         final &= ~DREF_SSC_SOURCE_MASK;
8182         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8183         final &= ~DREF_SSC1_ENABLE;
8184
8185         if (has_panel) {
8186                 final |= DREF_SSC_SOURCE_ENABLE;
8187
8188                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8189                         final |= DREF_SSC1_ENABLE;
8190
8191                 if (has_cpu_edp) {
8192                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8193                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8194                         else
8195                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8196                 } else
8197                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8198         } else {
8199                 final |= DREF_SSC_SOURCE_DISABLE;
8200                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8201         }
8202
8203         if (final == val)
8204                 return;
8205
8206         /* Always enable nonspread source */
8207         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8208
8209         if (has_ck505)
8210                 val |= DREF_NONSPREAD_CK505_ENABLE;
8211         else
8212                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8213
8214         if (has_panel) {
8215                 val &= ~DREF_SSC_SOURCE_MASK;
8216                 val |= DREF_SSC_SOURCE_ENABLE;
8217
8218                 /* SSC must be turned on before enabling the CPU output  */
8219                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8220                         DRM_DEBUG_KMS("Using SSC on panel\n");
8221                         val |= DREF_SSC1_ENABLE;
8222                 } else
8223                         val &= ~DREF_SSC1_ENABLE;
8224
8225                 /* Get SSC going before enabling the outputs */
8226                 I915_WRITE(PCH_DREF_CONTROL, val);
8227                 POSTING_READ(PCH_DREF_CONTROL);
8228                 udelay(200);
8229
8230                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8231
8232                 /* Enable CPU source on CPU attached eDP */
8233                 if (has_cpu_edp) {
8234                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8235                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8236                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8237                         } else
8238                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8239                 } else
8240                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8241
8242                 I915_WRITE(PCH_DREF_CONTROL, val);
8243                 POSTING_READ(PCH_DREF_CONTROL);
8244                 udelay(200);
8245         } else {
8246                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8247
8248                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8249
8250                 /* Turn off CPU output */
8251                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8252
8253                 I915_WRITE(PCH_DREF_CONTROL, val);
8254                 POSTING_READ(PCH_DREF_CONTROL);
8255                 udelay(200);
8256
8257                 /* Turn off the SSC source */
8258                 val &= ~DREF_SSC_SOURCE_MASK;
8259                 val |= DREF_SSC_SOURCE_DISABLE;
8260
8261                 /* Turn off SSC1 */
8262                 val &= ~DREF_SSC1_ENABLE;
8263
8264                 I915_WRITE(PCH_DREF_CONTROL, val);
8265                 POSTING_READ(PCH_DREF_CONTROL);
8266                 udelay(200);
8267         }
8268
8269         BUG_ON(val != final);
8270 }
8271
8272 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8273 {
8274         uint32_t tmp;
8275
8276         tmp = I915_READ(SOUTH_CHICKEN2);
8277         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8278         I915_WRITE(SOUTH_CHICKEN2, tmp);
8279
8280         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8281                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8282                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8283
8284         tmp = I915_READ(SOUTH_CHICKEN2);
8285         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8286         I915_WRITE(SOUTH_CHICKEN2, tmp);
8287
8288         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8289                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8290                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8291 }
8292
8293 /* WaMPhyProgramming:hsw */
8294 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8295 {
8296         uint32_t tmp;
8297
8298         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8299         tmp &= ~(0xFF << 24);
8300         tmp |= (0x12 << 24);
8301         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8302
8303         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8304         tmp |= (1 << 11);
8305         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8306
8307         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8308         tmp |= (1 << 11);
8309         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8310
8311         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8312         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8313         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8314
8315         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8316         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8317         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8318
8319         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8320         tmp &= ~(7 << 13);
8321         tmp |= (5 << 13);
8322         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8323
8324         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8325         tmp &= ~(7 << 13);
8326         tmp |= (5 << 13);
8327         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8328
8329         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8330         tmp &= ~0xFF;
8331         tmp |= 0x1C;
8332         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8333
8334         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8335         tmp &= ~0xFF;
8336         tmp |= 0x1C;
8337         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8338
8339         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8340         tmp &= ~(0xFF << 16);
8341         tmp |= (0x1C << 16);
8342         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8343
8344         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8345         tmp &= ~(0xFF << 16);
8346         tmp |= (0x1C << 16);
8347         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8348
8349         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8350         tmp |= (1 << 27);
8351         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8352
8353         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8354         tmp |= (1 << 27);
8355         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8356
8357         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8358         tmp &= ~(0xF << 28);
8359         tmp |= (4 << 28);
8360         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8361
8362         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8363         tmp &= ~(0xF << 28);
8364         tmp |= (4 << 28);
8365         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8366 }
8367
8368 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8369  * Programming" based on the parameters passed:
8370  * - Sequence to enable CLKOUT_DP
8371  * - Sequence to enable CLKOUT_DP without spread
8372  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8373  */
8374 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8375                                  bool with_fdi)
8376 {
8377         struct drm_i915_private *dev_priv = dev->dev_private;
8378         uint32_t reg, tmp;
8379
8380         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8381                 with_spread = true;
8382         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8383                  with_fdi, "LP PCH doesn't have FDI\n"))
8384                 with_fdi = false;
8385
8386         mutex_lock(&dev_priv->sb_lock);
8387
8388         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8389         tmp &= ~SBI_SSCCTL_DISABLE;
8390         tmp |= SBI_SSCCTL_PATHALT;
8391         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8392
8393         udelay(24);
8394
8395         if (with_spread) {
8396                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8397                 tmp &= ~SBI_SSCCTL_PATHALT;
8398                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8399
8400                 if (with_fdi) {
8401                         lpt_reset_fdi_mphy(dev_priv);
8402                         lpt_program_fdi_mphy(dev_priv);
8403                 }
8404         }
8405
8406         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8407                SBI_GEN0 : SBI_DBUFF0;
8408         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8409         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8410         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8411
8412         mutex_unlock(&dev_priv->sb_lock);
8413 }
8414
8415 /* Sequence to disable CLKOUT_DP */
8416 static void lpt_disable_clkout_dp(struct drm_device *dev)
8417 {
8418         struct drm_i915_private *dev_priv = dev->dev_private;
8419         uint32_t reg, tmp;
8420
8421         mutex_lock(&dev_priv->sb_lock);
8422
8423         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8424                SBI_GEN0 : SBI_DBUFF0;
8425         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8426         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8427         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8428
8429         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8431                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8432                         tmp |= SBI_SSCCTL_PATHALT;
8433                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8434                         udelay(32);
8435                 }
8436                 tmp |= SBI_SSCCTL_DISABLE;
8437                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438         }
8439
8440         mutex_unlock(&dev_priv->sb_lock);
8441 }
8442
8443 static void lpt_init_pch_refclk(struct drm_device *dev)
8444 {
8445         struct intel_encoder *encoder;
8446         bool has_vga = false;
8447
8448         for_each_intel_encoder(dev, encoder) {
8449                 switch (encoder->type) {
8450                 case INTEL_OUTPUT_ANALOG:
8451                         has_vga = true;
8452                         break;
8453                 default:
8454                         break;
8455                 }
8456         }
8457
8458         if (has_vga)
8459                 lpt_enable_clkout_dp(dev, true, true);
8460         else
8461                 lpt_disable_clkout_dp(dev);
8462 }
8463
8464 /*
8465  * Initialize reference clocks when the driver loads
8466  */
8467 void intel_init_pch_refclk(struct drm_device *dev)
8468 {
8469         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8470                 ironlake_init_pch_refclk(dev);
8471         else if (HAS_PCH_LPT(dev))
8472                 lpt_init_pch_refclk(dev);
8473 }
8474
8475 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8476 {
8477         struct drm_device *dev = crtc_state->base.crtc->dev;
8478         struct drm_i915_private *dev_priv = dev->dev_private;
8479         struct drm_atomic_state *state = crtc_state->base.state;
8480         struct drm_connector *connector;
8481         struct drm_connector_state *connector_state;
8482         struct intel_encoder *encoder;
8483         int num_connectors = 0, i;
8484         bool is_lvds = false;
8485
8486         for_each_connector_in_state(state, connector, connector_state, i) {
8487                 if (connector_state->crtc != crtc_state->base.crtc)
8488                         continue;
8489
8490                 encoder = to_intel_encoder(connector_state->best_encoder);
8491
8492                 switch (encoder->type) {
8493                 case INTEL_OUTPUT_LVDS:
8494                         is_lvds = true;
8495                         break;
8496                 default:
8497                         break;
8498                 }
8499                 num_connectors++;
8500         }
8501
8502         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8503                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8504                               dev_priv->vbt.lvds_ssc_freq);
8505                 return dev_priv->vbt.lvds_ssc_freq;
8506         }
8507
8508         return 120000;
8509 }
8510
8511 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8512 {
8513         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8515         int pipe = intel_crtc->pipe;
8516         uint32_t val;
8517
8518         val = 0;
8519
8520         switch (intel_crtc->config->pipe_bpp) {
8521         case 18:
8522                 val |= PIPECONF_6BPC;
8523                 break;
8524         case 24:
8525                 val |= PIPECONF_8BPC;
8526                 break;
8527         case 30:
8528                 val |= PIPECONF_10BPC;
8529                 break;
8530         case 36:
8531                 val |= PIPECONF_12BPC;
8532                 break;
8533         default:
8534                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8535                 BUG();
8536         }
8537
8538         if (intel_crtc->config->dither)
8539                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8540
8541         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8542                 val |= PIPECONF_INTERLACED_ILK;
8543         else
8544                 val |= PIPECONF_PROGRESSIVE;
8545
8546         if (intel_crtc->config->limited_color_range)
8547                 val |= PIPECONF_COLOR_RANGE_SELECT;
8548
8549         I915_WRITE(PIPECONF(pipe), val);
8550         POSTING_READ(PIPECONF(pipe));
8551 }
8552
8553 /*
8554  * Set up the pipe CSC unit.
8555  *
8556  * Currently only full range RGB to limited range RGB conversion
8557  * is supported, but eventually this should handle various
8558  * RGB<->YCbCr scenarios as well.
8559  */
8560 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8561 {
8562         struct drm_device *dev = crtc->dev;
8563         struct drm_i915_private *dev_priv = dev->dev_private;
8564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565         int pipe = intel_crtc->pipe;
8566         uint16_t coeff = 0x7800; /* 1.0 */
8567
8568         /*
8569          * TODO: Check what kind of values actually come out of the pipe
8570          * with these coeff/postoff values and adjust to get the best
8571          * accuracy. Perhaps we even need to take the bpc value into
8572          * consideration.
8573          */
8574
8575         if (intel_crtc->config->limited_color_range)
8576                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8577
8578         /*
8579          * GY/GU and RY/RU should be the other way around according
8580          * to BSpec, but reality doesn't agree. Just set them up in
8581          * a way that results in the correct picture.
8582          */
8583         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8584         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8585
8586         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8587         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8588
8589         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8590         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8591
8592         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8593         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8594         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8595
8596         if (INTEL_INFO(dev)->gen > 6) {
8597                 uint16_t postoff = 0;
8598
8599                 if (intel_crtc->config->limited_color_range)
8600                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
8601
8602                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8603                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8604                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8605
8606                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8607         } else {
8608                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8609
8610                 if (intel_crtc->config->limited_color_range)
8611                         mode |= CSC_BLACK_SCREEN_OFFSET;
8612
8613                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8614         }
8615 }
8616
8617 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8618 {
8619         struct drm_device *dev = crtc->dev;
8620         struct drm_i915_private *dev_priv = dev->dev_private;
8621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8622         enum pipe pipe = intel_crtc->pipe;
8623         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8624         uint32_t val;
8625
8626         val = 0;
8627
8628         if (IS_HASWELL(dev) && intel_crtc->config->dither)
8629                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8630
8631         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8632                 val |= PIPECONF_INTERLACED_ILK;
8633         else
8634                 val |= PIPECONF_PROGRESSIVE;
8635
8636         I915_WRITE(PIPECONF(cpu_transcoder), val);
8637         POSTING_READ(PIPECONF(cpu_transcoder));
8638
8639         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8640         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8641
8642         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8643                 val = 0;
8644
8645                 switch (intel_crtc->config->pipe_bpp) {
8646                 case 18:
8647                         val |= PIPEMISC_DITHER_6_BPC;
8648                         break;
8649                 case 24:
8650                         val |= PIPEMISC_DITHER_8_BPC;
8651                         break;
8652                 case 30:
8653                         val |= PIPEMISC_DITHER_10_BPC;
8654                         break;
8655                 case 36:
8656                         val |= PIPEMISC_DITHER_12_BPC;
8657                         break;
8658                 default:
8659                         /* Case prevented by pipe_config_set_bpp. */
8660                         BUG();
8661                 }
8662
8663                 if (intel_crtc->config->dither)
8664                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8665
8666                 I915_WRITE(PIPEMISC(pipe), val);
8667         }
8668 }
8669
8670 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8671                                     struct intel_crtc_state *crtc_state,
8672                                     intel_clock_t *clock,
8673                                     bool *has_reduced_clock,
8674                                     intel_clock_t *reduced_clock)
8675 {
8676         struct drm_device *dev = crtc->dev;
8677         struct drm_i915_private *dev_priv = dev->dev_private;
8678         int refclk;
8679         const intel_limit_t *limit;
8680         bool ret;
8681
8682         refclk = ironlake_get_refclk(crtc_state);
8683
8684         /*
8685          * Returns a set of divisors for the desired target clock with the given
8686          * refclk, or FALSE.  The returned values represent the clock equation:
8687          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8688          */
8689         limit = intel_limit(crtc_state, refclk);
8690         ret = dev_priv->display.find_dpll(limit, crtc_state,
8691                                           crtc_state->port_clock,
8692                                           refclk, NULL, clock);
8693         if (!ret)
8694                 return false;
8695
8696         return true;
8697 }
8698
8699 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8700 {
8701         /*
8702          * Account for spread spectrum to avoid
8703          * oversubscribing the link. Max center spread
8704          * is 2.5%; use 5% for safety's sake.
8705          */
8706         u32 bps = target_clock * bpp * 21 / 20;
8707         return DIV_ROUND_UP(bps, link_bw * 8);
8708 }
8709
8710 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8711 {
8712         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8713 }
8714
8715 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8716                                       struct intel_crtc_state *crtc_state,
8717                                       u32 *fp,
8718                                       intel_clock_t *reduced_clock, u32 *fp2)
8719 {
8720         struct drm_crtc *crtc = &intel_crtc->base;
8721         struct drm_device *dev = crtc->dev;
8722         struct drm_i915_private *dev_priv = dev->dev_private;
8723         struct drm_atomic_state *state = crtc_state->base.state;
8724         struct drm_connector *connector;
8725         struct drm_connector_state *connector_state;
8726         struct intel_encoder *encoder;
8727         uint32_t dpll;
8728         int factor, num_connectors = 0, i;
8729         bool is_lvds = false, is_sdvo = false;
8730
8731         for_each_connector_in_state(state, connector, connector_state, i) {
8732                 if (connector_state->crtc != crtc_state->base.crtc)
8733                         continue;
8734
8735                 encoder = to_intel_encoder(connector_state->best_encoder);
8736
8737                 switch (encoder->type) {
8738                 case INTEL_OUTPUT_LVDS:
8739                         is_lvds = true;
8740                         break;
8741                 case INTEL_OUTPUT_SDVO:
8742                 case INTEL_OUTPUT_HDMI:
8743                         is_sdvo = true;
8744                         break;
8745                 default:
8746                         break;
8747                 }
8748
8749                 num_connectors++;
8750         }
8751
8752         /* Enable autotuning of the PLL clock (if permissible) */
8753         factor = 21;
8754         if (is_lvds) {
8755                 if ((intel_panel_use_ssc(dev_priv) &&
8756                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8757                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8758                         factor = 25;
8759         } else if (crtc_state->sdvo_tv_clock)
8760                 factor = 20;
8761
8762         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8763                 *fp |= FP_CB_TUNE;
8764
8765         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8766                 *fp2 |= FP_CB_TUNE;
8767
8768         dpll = 0;
8769
8770         if (is_lvds)
8771                 dpll |= DPLLB_MODE_LVDS;
8772         else
8773                 dpll |= DPLLB_MODE_DAC_SERIAL;
8774
8775         dpll |= (crtc_state->pixel_multiplier - 1)
8776                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8777
8778         if (is_sdvo)
8779                 dpll |= DPLL_SDVO_HIGH_SPEED;
8780         if (crtc_state->has_dp_encoder)
8781                 dpll |= DPLL_SDVO_HIGH_SPEED;
8782
8783         /* compute bitmask from p1 value */
8784         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8785         /* also FPA1 */
8786         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8787
8788         switch (crtc_state->dpll.p2) {
8789         case 5:
8790                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8791                 break;
8792         case 7:
8793                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8794                 break;
8795         case 10:
8796                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8797                 break;
8798         case 14:
8799                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8800                 break;
8801         }
8802
8803         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8804                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8805         else
8806                 dpll |= PLL_REF_INPUT_DREFCLK;
8807
8808         return dpll | DPLL_VCO_ENABLE;
8809 }
8810
8811 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8812                                        struct intel_crtc_state *crtc_state)
8813 {
8814         struct drm_device *dev = crtc->base.dev;
8815         intel_clock_t clock, reduced_clock;
8816         u32 dpll = 0, fp = 0, fp2 = 0;
8817         bool ok, has_reduced_clock = false;
8818         bool is_lvds = false;
8819         struct intel_shared_dpll *pll;
8820
8821         memset(&crtc_state->dpll_hw_state, 0,
8822                sizeof(crtc_state->dpll_hw_state));
8823
8824         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8825
8826         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8827              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8828
8829         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8830                                      &has_reduced_clock, &reduced_clock);
8831         if (!ok && !crtc_state->clock_set) {
8832                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8833                 return -EINVAL;
8834         }
8835         /* Compat-code for transition, will disappear. */
8836         if (!crtc_state->clock_set) {
8837                 crtc_state->dpll.n = clock.n;
8838                 crtc_state->dpll.m1 = clock.m1;
8839                 crtc_state->dpll.m2 = clock.m2;
8840                 crtc_state->dpll.p1 = clock.p1;
8841                 crtc_state->dpll.p2 = clock.p2;
8842         }
8843
8844         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8845         if (crtc_state->has_pch_encoder) {
8846                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8847                 if (has_reduced_clock)
8848                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8849
8850                 dpll = ironlake_compute_dpll(crtc, crtc_state,
8851                                              &fp, &reduced_clock,
8852                                              has_reduced_clock ? &fp2 : NULL);
8853
8854                 crtc_state->dpll_hw_state.dpll = dpll;
8855                 crtc_state->dpll_hw_state.fp0 = fp;
8856                 if (has_reduced_clock)
8857                         crtc_state->dpll_hw_state.fp1 = fp2;
8858                 else
8859                         crtc_state->dpll_hw_state.fp1 = fp;
8860
8861                 pll = intel_get_shared_dpll(crtc, crtc_state);
8862                 if (pll == NULL) {
8863                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8864                                          pipe_name(crtc->pipe));
8865                         return -EINVAL;
8866                 }
8867         }
8868
8869         if (is_lvds && has_reduced_clock)
8870                 crtc->lowfreq_avail = true;
8871         else
8872                 crtc->lowfreq_avail = false;
8873
8874         return 0;
8875 }
8876
8877 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8878                                          struct intel_link_m_n *m_n)
8879 {
8880         struct drm_device *dev = crtc->base.dev;
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882         enum pipe pipe = crtc->pipe;
8883
8884         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8885         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8886         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8887                 & ~TU_SIZE_MASK;
8888         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8889         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8890                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8891 }
8892
8893 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8894                                          enum transcoder transcoder,
8895                                          struct intel_link_m_n *m_n,
8896                                          struct intel_link_m_n *m2_n2)
8897 {
8898         struct drm_device *dev = crtc->base.dev;
8899         struct drm_i915_private *dev_priv = dev->dev_private;
8900         enum pipe pipe = crtc->pipe;
8901
8902         if (INTEL_INFO(dev)->gen >= 5) {
8903                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8904                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8905                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8906                         & ~TU_SIZE_MASK;
8907                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8908                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8909                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8910                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8911                  * gen < 8) and if DRRS is supported (to make sure the
8912                  * registers are not unnecessarily read).
8913                  */
8914                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8915                         crtc->config->has_drrs) {
8916                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8917                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8918                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8919                                         & ~TU_SIZE_MASK;
8920                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8921                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8922                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923                 }
8924         } else {
8925                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8926                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8927                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8928                         & ~TU_SIZE_MASK;
8929                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8930                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8931                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932         }
8933 }
8934
8935 void intel_dp_get_m_n(struct intel_crtc *crtc,
8936                       struct intel_crtc_state *pipe_config)
8937 {
8938         if (pipe_config->has_pch_encoder)
8939                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8940         else
8941                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8942                                              &pipe_config->dp_m_n,
8943                                              &pipe_config->dp_m2_n2);
8944 }
8945
8946 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8947                                         struct intel_crtc_state *pipe_config)
8948 {
8949         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8950                                      &pipe_config->fdi_m_n, NULL);
8951 }
8952
8953 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8954                                     struct intel_crtc_state *pipe_config)
8955 {
8956         struct drm_device *dev = crtc->base.dev;
8957         struct drm_i915_private *dev_priv = dev->dev_private;
8958         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8959         uint32_t ps_ctrl = 0;
8960         int id = -1;
8961         int i;
8962
8963         /* find scaler attached to this pipe */
8964         for (i = 0; i < crtc->num_scalers; i++) {
8965                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8966                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8967                         id = i;
8968                         pipe_config->pch_pfit.enabled = true;
8969                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8970                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8971                         break;
8972                 }
8973         }
8974
8975         scaler_state->scaler_id = id;
8976         if (id >= 0) {
8977                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8978         } else {
8979                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8980         }
8981 }
8982
8983 static void
8984 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8985                                  struct intel_initial_plane_config *plane_config)
8986 {
8987         struct drm_device *dev = crtc->base.dev;
8988         struct drm_i915_private *dev_priv = dev->dev_private;
8989         u32 val, base, offset, stride_mult, tiling;
8990         int pipe = crtc->pipe;
8991         int fourcc, pixel_format;
8992         unsigned int aligned_height;
8993         struct drm_framebuffer *fb;
8994         struct intel_framebuffer *intel_fb;
8995
8996         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8997         if (!intel_fb) {
8998                 DRM_DEBUG_KMS("failed to alloc fb\n");
8999                 return;
9000         }
9001
9002         fb = &intel_fb->base;
9003
9004         val = I915_READ(PLANE_CTL(pipe, 0));
9005         if (!(val & PLANE_CTL_ENABLE))
9006                 goto error;
9007
9008         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9009         fourcc = skl_format_to_fourcc(pixel_format,
9010                                       val & PLANE_CTL_ORDER_RGBX,
9011                                       val & PLANE_CTL_ALPHA_MASK);
9012         fb->pixel_format = fourcc;
9013         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9014
9015         tiling = val & PLANE_CTL_TILED_MASK;
9016         switch (tiling) {
9017         case PLANE_CTL_TILED_LINEAR:
9018                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9019                 break;
9020         case PLANE_CTL_TILED_X:
9021                 plane_config->tiling = I915_TILING_X;
9022                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9023                 break;
9024         case PLANE_CTL_TILED_Y:
9025                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9026                 break;
9027         case PLANE_CTL_TILED_YF:
9028                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9029                 break;
9030         default:
9031                 MISSING_CASE(tiling);
9032                 goto error;
9033         }
9034
9035         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9036         plane_config->base = base;
9037
9038         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9039
9040         val = I915_READ(PLANE_SIZE(pipe, 0));
9041         fb->height = ((val >> 16) & 0xfff) + 1;
9042         fb->width = ((val >> 0) & 0x1fff) + 1;
9043
9044         val = I915_READ(PLANE_STRIDE(pipe, 0));
9045         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9046                                                 fb->pixel_format);
9047         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9048
9049         aligned_height = intel_fb_align_height(dev, fb->height,
9050                                                fb->pixel_format,
9051                                                fb->modifier[0]);
9052
9053         plane_config->size = fb->pitches[0] * aligned_height;
9054
9055         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9056                       pipe_name(pipe), fb->width, fb->height,
9057                       fb->bits_per_pixel, base, fb->pitches[0],
9058                       plane_config->size);
9059
9060         plane_config->fb = intel_fb;
9061         return;
9062
9063 error:
9064         kfree(fb);
9065 }
9066
9067 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9068                                      struct intel_crtc_state *pipe_config)
9069 {
9070         struct drm_device *dev = crtc->base.dev;
9071         struct drm_i915_private *dev_priv = dev->dev_private;
9072         uint32_t tmp;
9073
9074         tmp = I915_READ(PF_CTL(crtc->pipe));
9075
9076         if (tmp & PF_ENABLE) {
9077                 pipe_config->pch_pfit.enabled = true;
9078                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9079                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9080
9081                 /* We currently do not free assignements of panel fitters on
9082                  * ivb/hsw (since we don't use the higher upscaling modes which
9083                  * differentiates them) so just WARN about this case for now. */
9084                 if (IS_GEN7(dev)) {
9085                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9086                                 PF_PIPE_SEL_IVB(crtc->pipe));
9087                 }
9088         }
9089 }
9090
9091 static void
9092 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9093                                   struct intel_initial_plane_config *plane_config)
9094 {
9095         struct drm_device *dev = crtc->base.dev;
9096         struct drm_i915_private *dev_priv = dev->dev_private;
9097         u32 val, base, offset;
9098         int pipe = crtc->pipe;
9099         int fourcc, pixel_format;
9100         unsigned int aligned_height;
9101         struct drm_framebuffer *fb;
9102         struct intel_framebuffer *intel_fb;
9103
9104         val = I915_READ(DSPCNTR(pipe));
9105         if (!(val & DISPLAY_PLANE_ENABLE))
9106                 return;
9107
9108         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9109         if (!intel_fb) {
9110                 DRM_DEBUG_KMS("failed to alloc fb\n");
9111                 return;
9112         }
9113
9114         fb = &intel_fb->base;
9115
9116         if (INTEL_INFO(dev)->gen >= 4) {
9117                 if (val & DISPPLANE_TILED) {
9118                         plane_config->tiling = I915_TILING_X;
9119                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9120                 }
9121         }
9122
9123         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9124         fourcc = i9xx_format_to_fourcc(pixel_format);
9125         fb->pixel_format = fourcc;
9126         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9127
9128         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9129         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9130                 offset = I915_READ(DSPOFFSET(pipe));
9131         } else {
9132                 if (plane_config->tiling)
9133                         offset = I915_READ(DSPTILEOFF(pipe));
9134                 else
9135                         offset = I915_READ(DSPLINOFF(pipe));
9136         }
9137         plane_config->base = base;
9138
9139         val = I915_READ(PIPESRC(pipe));
9140         fb->width = ((val >> 16) & 0xfff) + 1;
9141         fb->height = ((val >> 0) & 0xfff) + 1;
9142
9143         val = I915_READ(DSPSTRIDE(pipe));
9144         fb->pitches[0] = val & 0xffffffc0;
9145
9146         aligned_height = intel_fb_align_height(dev, fb->height,
9147                                                fb->pixel_format,
9148                                                fb->modifier[0]);
9149
9150         plane_config->size = fb->pitches[0] * aligned_height;
9151
9152         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153                       pipe_name(pipe), fb->width, fb->height,
9154                       fb->bits_per_pixel, base, fb->pitches[0],
9155                       plane_config->size);
9156
9157         plane_config->fb = intel_fb;
9158 }
9159
9160 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9161                                      struct intel_crtc_state *pipe_config)
9162 {
9163         struct drm_device *dev = crtc->base.dev;
9164         struct drm_i915_private *dev_priv = dev->dev_private;
9165         uint32_t tmp;
9166
9167         if (!intel_display_power_is_enabled(dev_priv,
9168                                             POWER_DOMAIN_PIPE(crtc->pipe)))
9169                 return false;
9170
9171         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9172         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9173
9174         tmp = I915_READ(PIPECONF(crtc->pipe));
9175         if (!(tmp & PIPECONF_ENABLE))
9176                 return false;
9177
9178         switch (tmp & PIPECONF_BPC_MASK) {
9179         case PIPECONF_6BPC:
9180                 pipe_config->pipe_bpp = 18;
9181                 break;
9182         case PIPECONF_8BPC:
9183                 pipe_config->pipe_bpp = 24;
9184                 break;
9185         case PIPECONF_10BPC:
9186                 pipe_config->pipe_bpp = 30;
9187                 break;
9188         case PIPECONF_12BPC:
9189                 pipe_config->pipe_bpp = 36;
9190                 break;
9191         default:
9192                 break;
9193         }
9194
9195         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9196                 pipe_config->limited_color_range = true;
9197
9198         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9199                 struct intel_shared_dpll *pll;
9200
9201                 pipe_config->has_pch_encoder = true;
9202
9203                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9204                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9205                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9206
9207                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9208
9209                 if (HAS_PCH_IBX(dev_priv->dev)) {
9210                         pipe_config->shared_dpll =
9211                                 (enum intel_dpll_id) crtc->pipe;
9212                 } else {
9213                         tmp = I915_READ(PCH_DPLL_SEL);
9214                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9215                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9216                         else
9217                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9218                 }
9219
9220                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9221
9222                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9223                                            &pipe_config->dpll_hw_state));
9224
9225                 tmp = pipe_config->dpll_hw_state.dpll;
9226                 pipe_config->pixel_multiplier =
9227                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9228                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9229
9230                 ironlake_pch_clock_get(crtc, pipe_config);
9231         } else {
9232                 pipe_config->pixel_multiplier = 1;
9233         }
9234
9235         intel_get_pipe_timings(crtc, pipe_config);
9236
9237         ironlake_get_pfit_config(crtc, pipe_config);
9238
9239         return true;
9240 }
9241
9242 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9243 {
9244         struct drm_device *dev = dev_priv->dev;
9245         struct intel_crtc *crtc;
9246
9247         for_each_intel_crtc(dev, crtc)
9248                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9249                      pipe_name(crtc->pipe));
9250
9251         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9252         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9253         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9254         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9255         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9256         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9257              "CPU PWM1 enabled\n");
9258         if (IS_HASWELL(dev))
9259                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9260                      "CPU PWM2 enabled\n");
9261         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9262              "PCH PWM1 enabled\n");
9263         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9264              "Utility pin enabled\n");
9265         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9266
9267         /*
9268          * In theory we can still leave IRQs enabled, as long as only the HPD
9269          * interrupts remain enabled. We used to check for that, but since it's
9270          * gen-specific and since we only disable LCPLL after we fully disable
9271          * the interrupts, the check below should be enough.
9272          */
9273         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9274 }
9275
9276 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9277 {
9278         struct drm_device *dev = dev_priv->dev;
9279
9280         if (IS_HASWELL(dev))
9281                 return I915_READ(D_COMP_HSW);
9282         else
9283                 return I915_READ(D_COMP_BDW);
9284 }
9285
9286 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9287 {
9288         struct drm_device *dev = dev_priv->dev;
9289
9290         if (IS_HASWELL(dev)) {
9291                 mutex_lock(&dev_priv->rps.hw_lock);
9292                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9293                                             val))
9294                         DRM_ERROR("Failed to write to D_COMP\n");
9295                 mutex_unlock(&dev_priv->rps.hw_lock);
9296         } else {
9297                 I915_WRITE(D_COMP_BDW, val);
9298                 POSTING_READ(D_COMP_BDW);
9299         }
9300 }
9301
9302 /*
9303  * This function implements pieces of two sequences from BSpec:
9304  * - Sequence for display software to disable LCPLL
9305  * - Sequence for display software to allow package C8+
9306  * The steps implemented here are just the steps that actually touch the LCPLL
9307  * register. Callers should take care of disabling all the display engine
9308  * functions, doing the mode unset, fixing interrupts, etc.
9309  */
9310 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9311                               bool switch_to_fclk, bool allow_power_down)
9312 {
9313         uint32_t val;
9314
9315         assert_can_disable_lcpll(dev_priv);
9316
9317         val = I915_READ(LCPLL_CTL);
9318
9319         if (switch_to_fclk) {
9320                 val |= LCPLL_CD_SOURCE_FCLK;
9321                 I915_WRITE(LCPLL_CTL, val);
9322
9323                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9324                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9325                         DRM_ERROR("Switching to FCLK failed\n");
9326
9327                 val = I915_READ(LCPLL_CTL);
9328         }
9329
9330         val |= LCPLL_PLL_DISABLE;
9331         I915_WRITE(LCPLL_CTL, val);
9332         POSTING_READ(LCPLL_CTL);
9333
9334         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9335                 DRM_ERROR("LCPLL still locked\n");
9336
9337         val = hsw_read_dcomp(dev_priv);
9338         val |= D_COMP_COMP_DISABLE;
9339         hsw_write_dcomp(dev_priv, val);
9340         ndelay(100);
9341
9342         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9343                      1))
9344                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9345
9346         if (allow_power_down) {
9347                 val = I915_READ(LCPLL_CTL);
9348                 val |= LCPLL_POWER_DOWN_ALLOW;
9349                 I915_WRITE(LCPLL_CTL, val);
9350                 POSTING_READ(LCPLL_CTL);
9351         }
9352 }
9353
9354 /*
9355  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9356  * source.
9357  */
9358 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9359 {
9360         uint32_t val;
9361
9362         val = I915_READ(LCPLL_CTL);
9363
9364         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9365                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9366                 return;
9367
9368         /*
9369          * Make sure we're not on PC8 state before disabling PC8, otherwise
9370          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9371          */
9372         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9373
9374         if (val & LCPLL_POWER_DOWN_ALLOW) {
9375                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9376                 I915_WRITE(LCPLL_CTL, val);
9377                 POSTING_READ(LCPLL_CTL);
9378         }
9379
9380         val = hsw_read_dcomp(dev_priv);
9381         val |= D_COMP_COMP_FORCE;
9382         val &= ~D_COMP_COMP_DISABLE;
9383         hsw_write_dcomp(dev_priv, val);
9384
9385         val = I915_READ(LCPLL_CTL);
9386         val &= ~LCPLL_PLL_DISABLE;
9387         I915_WRITE(LCPLL_CTL, val);
9388
9389         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9390                 DRM_ERROR("LCPLL not locked yet\n");
9391
9392         if (val & LCPLL_CD_SOURCE_FCLK) {
9393                 val = I915_READ(LCPLL_CTL);
9394                 val &= ~LCPLL_CD_SOURCE_FCLK;
9395                 I915_WRITE(LCPLL_CTL, val);
9396
9397                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9398                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9399                         DRM_ERROR("Switching back to LCPLL failed\n");
9400         }
9401
9402         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9403         intel_update_cdclk(dev_priv->dev);
9404 }
9405
9406 /*
9407  * Package states C8 and deeper are really deep PC states that can only be
9408  * reached when all the devices on the system allow it, so even if the graphics
9409  * device allows PC8+, it doesn't mean the system will actually get to these
9410  * states. Our driver only allows PC8+ when going into runtime PM.
9411  *
9412  * The requirements for PC8+ are that all the outputs are disabled, the power
9413  * well is disabled and most interrupts are disabled, and these are also
9414  * requirements for runtime PM. When these conditions are met, we manually do
9415  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9416  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9417  * hang the machine.
9418  *
9419  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9420  * the state of some registers, so when we come back from PC8+ we need to
9421  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9422  * need to take care of the registers kept by RC6. Notice that this happens even
9423  * if we don't put the device in PCI D3 state (which is what currently happens
9424  * because of the runtime PM support).
9425  *
9426  * For more, read "Display Sequences for Package C8" on the hardware
9427  * documentation.
9428  */
9429 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9430 {
9431         struct drm_device *dev = dev_priv->dev;
9432         uint32_t val;
9433
9434         DRM_DEBUG_KMS("Enabling package C8+\n");
9435
9436         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9437                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9439                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9440         }
9441
9442         lpt_disable_clkout_dp(dev);
9443         hsw_disable_lcpll(dev_priv, true, true);
9444 }
9445
9446 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9447 {
9448         struct drm_device *dev = dev_priv->dev;
9449         uint32_t val;
9450
9451         DRM_DEBUG_KMS("Disabling package C8+\n");
9452
9453         hsw_restore_lcpll(dev_priv);
9454         lpt_init_pch_refclk(dev);
9455
9456         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9457                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9458                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9459                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9460         }
9461
9462         intel_prepare_ddi(dev);
9463 }
9464
9465 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9466 {
9467         struct drm_device *dev = old_state->dev;
9468         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9469
9470         broxton_set_cdclk(dev, req_cdclk);
9471 }
9472
9473 /* compute the max rate for new configuration */
9474 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9475 {
9476         struct intel_crtc *intel_crtc;
9477         struct intel_crtc_state *crtc_state;
9478         int max_pixel_rate = 0;
9479
9480         for_each_intel_crtc(state->dev, intel_crtc) {
9481                 int pixel_rate;
9482
9483                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9484                 if (IS_ERR(crtc_state))
9485                         return PTR_ERR(crtc_state);
9486
9487                 if (!crtc_state->base.enable)
9488                         continue;
9489
9490                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9491
9492                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9493                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9494                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9495
9496                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9497         }
9498
9499         return max_pixel_rate;
9500 }
9501
9502 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9503 {
9504         struct drm_i915_private *dev_priv = dev->dev_private;
9505         uint32_t val, data;
9506         int ret;
9507
9508         if (WARN((I915_READ(LCPLL_CTL) &
9509                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9510                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9511                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9512                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9513                  "trying to change cdclk frequency with cdclk not enabled\n"))
9514                 return;
9515
9516         mutex_lock(&dev_priv->rps.hw_lock);
9517         ret = sandybridge_pcode_write(dev_priv,
9518                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9519         mutex_unlock(&dev_priv->rps.hw_lock);
9520         if (ret) {
9521                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9522                 return;
9523         }
9524
9525         val = I915_READ(LCPLL_CTL);
9526         val |= LCPLL_CD_SOURCE_FCLK;
9527         I915_WRITE(LCPLL_CTL, val);
9528
9529         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9530                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
9531                 DRM_ERROR("Switching to FCLK failed\n");
9532
9533         val = I915_READ(LCPLL_CTL);
9534         val &= ~LCPLL_CLK_FREQ_MASK;
9535
9536         switch (cdclk) {
9537         case 450000:
9538                 val |= LCPLL_CLK_FREQ_450;
9539                 data = 0;
9540                 break;
9541         case 540000:
9542                 val |= LCPLL_CLK_FREQ_54O_BDW;
9543                 data = 1;
9544                 break;
9545         case 337500:
9546                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9547                 data = 2;
9548                 break;
9549         case 675000:
9550                 val |= LCPLL_CLK_FREQ_675_BDW;
9551                 data = 3;
9552                 break;
9553         default:
9554                 WARN(1, "invalid cdclk frequency\n");
9555                 return;
9556         }
9557
9558         I915_WRITE(LCPLL_CTL, val);
9559
9560         val = I915_READ(LCPLL_CTL);
9561         val &= ~LCPLL_CD_SOURCE_FCLK;
9562         I915_WRITE(LCPLL_CTL, val);
9563
9564         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9565                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566                 DRM_ERROR("Switching back to LCPLL failed\n");
9567
9568         mutex_lock(&dev_priv->rps.hw_lock);
9569         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9570         mutex_unlock(&dev_priv->rps.hw_lock);
9571
9572         intel_update_cdclk(dev);
9573
9574         WARN(cdclk != dev_priv->cdclk_freq,
9575              "cdclk requested %d kHz but got %d kHz\n",
9576              cdclk, dev_priv->cdclk_freq);
9577 }
9578
9579 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9580 {
9581         struct drm_i915_private *dev_priv = to_i915(state->dev);
9582         int max_pixclk = ilk_max_pixel_rate(state);
9583         int cdclk;
9584
9585         /*
9586          * FIXME should also account for plane ratio
9587          * once 64bpp pixel formats are supported.
9588          */
9589         if (max_pixclk > 540000)
9590                 cdclk = 675000;
9591         else if (max_pixclk > 450000)
9592                 cdclk = 540000;
9593         else if (max_pixclk > 337500)
9594                 cdclk = 450000;
9595         else
9596                 cdclk = 337500;
9597
9598         /*
9599          * FIXME move the cdclk caclulation to
9600          * compute_config() so we can fail gracegully.
9601          */
9602         if (cdclk > dev_priv->max_cdclk_freq) {
9603                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9604                           cdclk, dev_priv->max_cdclk_freq);
9605                 cdclk = dev_priv->max_cdclk_freq;
9606         }
9607
9608         to_intel_atomic_state(state)->cdclk = cdclk;
9609
9610         return 0;
9611 }
9612
9613 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9614 {
9615         struct drm_device *dev = old_state->dev;
9616         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9617
9618         broadwell_set_cdclk(dev, req_cdclk);
9619 }
9620
9621 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9622                                       struct intel_crtc_state *crtc_state)
9623 {
9624         if (!intel_ddi_pll_select(crtc, crtc_state))
9625                 return -EINVAL;
9626
9627         crtc->lowfreq_avail = false;
9628
9629         return 0;
9630 }
9631
9632 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9633                                 enum port port,
9634                                 struct intel_crtc_state *pipe_config)
9635 {
9636         switch (port) {
9637         case PORT_A:
9638                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9639                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9640                 break;
9641         case PORT_B:
9642                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9643                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9644                 break;
9645         case PORT_C:
9646                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9647                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9648                 break;
9649         default:
9650                 DRM_ERROR("Incorrect port type\n");
9651         }
9652 }
9653
9654 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655                                 enum port port,
9656                                 struct intel_crtc_state *pipe_config)
9657 {
9658         u32 temp, dpll_ctl1;
9659
9660         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9661         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9662
9663         switch (pipe_config->ddi_pll_sel) {
9664         case SKL_DPLL0:
9665                 /*
9666                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9667                  * of the shared DPLL framework and thus needs to be read out
9668                  * separately
9669                  */
9670                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9671                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9672                 break;
9673         case SKL_DPLL1:
9674                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9675                 break;
9676         case SKL_DPLL2:
9677                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9678                 break;
9679         case SKL_DPLL3:
9680                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9681                 break;
9682         }
9683 }
9684
9685 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9686                                 enum port port,
9687                                 struct intel_crtc_state *pipe_config)
9688 {
9689         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9690
9691         switch (pipe_config->ddi_pll_sel) {
9692         case PORT_CLK_SEL_WRPLL1:
9693                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9694                 break;
9695         case PORT_CLK_SEL_WRPLL2:
9696                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9697                 break;
9698         }
9699 }
9700
9701 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9702                                        struct intel_crtc_state *pipe_config)
9703 {
9704         struct drm_device *dev = crtc->base.dev;
9705         struct drm_i915_private *dev_priv = dev->dev_private;
9706         struct intel_shared_dpll *pll;
9707         enum port port;
9708         uint32_t tmp;
9709
9710         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9711
9712         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9713
9714         if (IS_SKYLAKE(dev))
9715                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9716         else if (IS_BROXTON(dev))
9717                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9718         else
9719                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9720
9721         if (pipe_config->shared_dpll >= 0) {
9722                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9723
9724                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9725                                            &pipe_config->dpll_hw_state));
9726         }
9727
9728         /*
9729          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9730          * DDI E. So just check whether this pipe is wired to DDI E and whether
9731          * the PCH transcoder is on.
9732          */
9733         if (INTEL_INFO(dev)->gen < 9 &&
9734             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9735                 pipe_config->has_pch_encoder = true;
9736
9737                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9738                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9739                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9740
9741                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9742         }
9743 }
9744
9745 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9746                                     struct intel_crtc_state *pipe_config)
9747 {
9748         struct drm_device *dev = crtc->base.dev;
9749         struct drm_i915_private *dev_priv = dev->dev_private;
9750         enum intel_display_power_domain pfit_domain;
9751         uint32_t tmp;
9752
9753         if (!intel_display_power_is_enabled(dev_priv,
9754                                          POWER_DOMAIN_PIPE(crtc->pipe)))
9755                 return false;
9756
9757         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9758         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9759
9760         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9761         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9762                 enum pipe trans_edp_pipe;
9763                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9764                 default:
9765                         WARN(1, "unknown pipe linked to edp transcoder\n");
9766                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9767                 case TRANS_DDI_EDP_INPUT_A_ON:
9768                         trans_edp_pipe = PIPE_A;
9769                         break;
9770                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9771                         trans_edp_pipe = PIPE_B;
9772                         break;
9773                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9774                         trans_edp_pipe = PIPE_C;
9775                         break;
9776                 }
9777
9778                 if (trans_edp_pipe == crtc->pipe)
9779                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9780         }
9781
9782         if (!intel_display_power_is_enabled(dev_priv,
9783                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9784                 return false;
9785
9786         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9787         if (!(tmp & PIPECONF_ENABLE))
9788                 return false;
9789
9790         haswell_get_ddi_port_state(crtc, pipe_config);
9791
9792         intel_get_pipe_timings(crtc, pipe_config);
9793
9794         if (INTEL_INFO(dev)->gen >= 9) {
9795                 skl_init_scalers(dev, crtc, pipe_config);
9796         }
9797
9798         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9799
9800         if (INTEL_INFO(dev)->gen >= 9) {
9801                 pipe_config->scaler_state.scaler_id = -1;
9802                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9803         }
9804
9805         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9806                 if (INTEL_INFO(dev)->gen == 9)
9807                         skylake_get_pfit_config(crtc, pipe_config);
9808                 else if (INTEL_INFO(dev)->gen < 9)
9809                         ironlake_get_pfit_config(crtc, pipe_config);
9810                 else
9811                         MISSING_CASE(INTEL_INFO(dev)->gen);
9812         }
9813
9814         if (IS_HASWELL(dev))
9815                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9816                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9817
9818         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9819                 pipe_config->pixel_multiplier =
9820                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9821         } else {
9822                 pipe_config->pixel_multiplier = 1;
9823         }
9824
9825         return true;
9826 }
9827
9828 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9829 {
9830         struct drm_device *dev = crtc->dev;
9831         struct drm_i915_private *dev_priv = dev->dev_private;
9832         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9833         uint32_t cntl = 0, size = 0;
9834
9835         if (base) {
9836                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9837                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9838                 unsigned int stride = roundup_pow_of_two(width) * 4;
9839
9840                 switch (stride) {
9841                 default:
9842                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9843                                   width, stride);
9844                         stride = 256;
9845                         /* fallthrough */
9846                 case 256:
9847                 case 512:
9848                 case 1024:
9849                 case 2048:
9850                         break;
9851                 }
9852
9853                 cntl |= CURSOR_ENABLE |
9854                         CURSOR_GAMMA_ENABLE |
9855                         CURSOR_FORMAT_ARGB |
9856                         CURSOR_STRIDE(stride);
9857
9858                 size = (height << 12) | width;
9859         }
9860
9861         if (intel_crtc->cursor_cntl != 0 &&
9862             (intel_crtc->cursor_base != base ||
9863              intel_crtc->cursor_size != size ||
9864              intel_crtc->cursor_cntl != cntl)) {
9865                 /* On these chipsets we can only modify the base/size/stride
9866                  * whilst the cursor is disabled.
9867                  */
9868                 I915_WRITE(_CURACNTR, 0);
9869                 POSTING_READ(_CURACNTR);
9870                 intel_crtc->cursor_cntl = 0;
9871         }
9872
9873         if (intel_crtc->cursor_base != base) {
9874                 I915_WRITE(_CURABASE, base);
9875                 intel_crtc->cursor_base = base;
9876         }
9877
9878         if (intel_crtc->cursor_size != size) {
9879                 I915_WRITE(CURSIZE, size);
9880                 intel_crtc->cursor_size = size;
9881         }
9882
9883         if (intel_crtc->cursor_cntl != cntl) {
9884                 I915_WRITE(_CURACNTR, cntl);
9885                 POSTING_READ(_CURACNTR);
9886                 intel_crtc->cursor_cntl = cntl;
9887         }
9888 }
9889
9890 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9891 {
9892         struct drm_device *dev = crtc->dev;
9893         struct drm_i915_private *dev_priv = dev->dev_private;
9894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9895         int pipe = intel_crtc->pipe;
9896         uint32_t cntl;
9897
9898         cntl = 0;
9899         if (base) {
9900                 cntl = MCURSOR_GAMMA_ENABLE;
9901                 switch (intel_crtc->base.cursor->state->crtc_w) {
9902                         case 64:
9903                                 cntl |= CURSOR_MODE_64_ARGB_AX;
9904                                 break;
9905                         case 128:
9906                                 cntl |= CURSOR_MODE_128_ARGB_AX;
9907                                 break;
9908                         case 256:
9909                                 cntl |= CURSOR_MODE_256_ARGB_AX;
9910                                 break;
9911                         default:
9912                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9913                                 return;
9914                 }
9915                 cntl |= pipe << 28; /* Connect to correct pipe */
9916
9917                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9918                         cntl |= CURSOR_PIPE_CSC_ENABLE;
9919         }
9920
9921         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9922                 cntl |= CURSOR_ROTATE_180;
9923
9924         if (intel_crtc->cursor_cntl != cntl) {
9925                 I915_WRITE(CURCNTR(pipe), cntl);
9926                 POSTING_READ(CURCNTR(pipe));
9927                 intel_crtc->cursor_cntl = cntl;
9928         }
9929
9930         /* and commit changes on next vblank */
9931         I915_WRITE(CURBASE(pipe), base);
9932         POSTING_READ(CURBASE(pipe));
9933
9934         intel_crtc->cursor_base = base;
9935 }
9936
9937 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9938 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9939                                      bool on)
9940 {
9941         struct drm_device *dev = crtc->dev;
9942         struct drm_i915_private *dev_priv = dev->dev_private;
9943         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944         int pipe = intel_crtc->pipe;
9945         int x = crtc->cursor_x;
9946         int y = crtc->cursor_y;
9947         u32 base = 0, pos = 0;
9948
9949         if (on)
9950                 base = intel_crtc->cursor_addr;
9951
9952         if (x >= intel_crtc->config->pipe_src_w)
9953                 base = 0;
9954
9955         if (y >= intel_crtc->config->pipe_src_h)
9956                 base = 0;
9957
9958         if (x < 0) {
9959                 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9960                         base = 0;
9961
9962                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9963                 x = -x;
9964         }
9965         pos |= x << CURSOR_X_SHIFT;
9966
9967         if (y < 0) {
9968                 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9969                         base = 0;
9970
9971                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9972                 y = -y;
9973         }
9974         pos |= y << CURSOR_Y_SHIFT;
9975
9976         if (base == 0 && intel_crtc->cursor_base == 0)
9977                 return;
9978
9979         I915_WRITE(CURPOS(pipe), pos);
9980
9981         /* ILK+ do this automagically */
9982         if (HAS_GMCH_DISPLAY(dev) &&
9983             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9984                 base += (intel_crtc->base.cursor->state->crtc_h *
9985                         intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9986         }
9987
9988         if (IS_845G(dev) || IS_I865G(dev))
9989                 i845_update_cursor(crtc, base);
9990         else
9991                 i9xx_update_cursor(crtc, base);
9992 }
9993
9994 static bool cursor_size_ok(struct drm_device *dev,
9995                            uint32_t width, uint32_t height)
9996 {
9997         if (width == 0 || height == 0)
9998                 return false;
9999
10000         /*
10001          * 845g/865g are special in that they are only limited by
10002          * the width of their cursors, the height is arbitrary up to
10003          * the precision of the register. Everything else requires
10004          * square cursors, limited to a few power-of-two sizes.
10005          */
10006         if (IS_845G(dev) || IS_I865G(dev)) {
10007                 if ((width & 63) != 0)
10008                         return false;
10009
10010                 if (width > (IS_845G(dev) ? 64 : 512))
10011                         return false;
10012
10013                 if (height > 1023)
10014                         return false;
10015         } else {
10016                 switch (width | height) {
10017                 case 256:
10018                 case 128:
10019                         if (IS_GEN2(dev))
10020                                 return false;
10021                 case 64:
10022                         break;
10023                 default:
10024                         return false;
10025                 }
10026         }
10027
10028         return true;
10029 }
10030
10031 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10032                                  u16 *blue, uint32_t start, uint32_t size)
10033 {
10034         int end = (start + size > 256) ? 256 : start + size, i;
10035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10036
10037         for (i = start; i < end; i++) {
10038                 intel_crtc->lut_r[i] = red[i] >> 8;
10039                 intel_crtc->lut_g[i] = green[i] >> 8;
10040                 intel_crtc->lut_b[i] = blue[i] >> 8;
10041         }
10042
10043         intel_crtc_load_lut(crtc);
10044 }
10045
10046 /* VESA 640x480x72Hz mode to set on the pipe */
10047 static struct drm_display_mode load_detect_mode = {
10048         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10049                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10050 };
10051
10052 struct drm_framebuffer *
10053 __intel_framebuffer_create(struct drm_device *dev,
10054                            struct drm_mode_fb_cmd2 *mode_cmd,
10055                            struct drm_i915_gem_object *obj)
10056 {
10057         struct intel_framebuffer *intel_fb;
10058         int ret;
10059
10060         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10061         if (!intel_fb) {
10062                 drm_gem_object_unreference(&obj->base);
10063                 return ERR_PTR(-ENOMEM);
10064         }
10065
10066         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10067         if (ret)
10068                 goto err;
10069
10070         return &intel_fb->base;
10071 err:
10072         drm_gem_object_unreference(&obj->base);
10073         kfree(intel_fb);
10074
10075         return ERR_PTR(ret);
10076 }
10077
10078 static struct drm_framebuffer *
10079 intel_framebuffer_create(struct drm_device *dev,
10080                          struct drm_mode_fb_cmd2 *mode_cmd,
10081                          struct drm_i915_gem_object *obj)
10082 {
10083         struct drm_framebuffer *fb;
10084         int ret;
10085
10086         ret = i915_mutex_lock_interruptible(dev);
10087         if (ret)
10088                 return ERR_PTR(ret);
10089         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10090         mutex_unlock(&dev->struct_mutex);
10091
10092         return fb;
10093 }
10094
10095 static u32
10096 intel_framebuffer_pitch_for_width(int width, int bpp)
10097 {
10098         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10099         return ALIGN(pitch, 64);
10100 }
10101
10102 static u32
10103 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10104 {
10105         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10106         return PAGE_ALIGN(pitch * mode->vdisplay);
10107 }
10108
10109 static struct drm_framebuffer *
10110 intel_framebuffer_create_for_mode(struct drm_device *dev,
10111                                   struct drm_display_mode *mode,
10112                                   int depth, int bpp)
10113 {
10114         struct drm_i915_gem_object *obj;
10115         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10116
10117         obj = i915_gem_alloc_object(dev,
10118                                     intel_framebuffer_size_for_mode(mode, bpp));
10119         if (obj == NULL)
10120                 return ERR_PTR(-ENOMEM);
10121
10122         mode_cmd.width = mode->hdisplay;
10123         mode_cmd.height = mode->vdisplay;
10124         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10125                                                                 bpp);
10126         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10127
10128         return intel_framebuffer_create(dev, &mode_cmd, obj);
10129 }
10130
10131 static struct drm_framebuffer *
10132 mode_fits_in_fbdev(struct drm_device *dev,
10133                    struct drm_display_mode *mode)
10134 {
10135 #ifdef CONFIG_DRM_I915_FBDEV
10136         struct drm_i915_private *dev_priv = dev->dev_private;
10137         struct drm_i915_gem_object *obj;
10138         struct drm_framebuffer *fb;
10139
10140         if (!dev_priv->fbdev)
10141                 return NULL;
10142
10143         if (!dev_priv->fbdev->fb)
10144                 return NULL;
10145
10146         obj = dev_priv->fbdev->fb->obj;
10147         BUG_ON(!obj);
10148
10149         fb = &dev_priv->fbdev->fb->base;
10150         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10151                                                                fb->bits_per_pixel))
10152                 return NULL;
10153
10154         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10155                 return NULL;
10156
10157         return fb;
10158 #else
10159         return NULL;
10160 #endif
10161 }
10162
10163 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10164                                            struct drm_crtc *crtc,
10165                                            struct drm_display_mode *mode,
10166                                            struct drm_framebuffer *fb,
10167                                            int x, int y)
10168 {
10169         struct drm_plane_state *plane_state;
10170         int hdisplay, vdisplay;
10171         int ret;
10172
10173         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10174         if (IS_ERR(plane_state))
10175                 return PTR_ERR(plane_state);
10176
10177         if (mode)
10178                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10179         else
10180                 hdisplay = vdisplay = 0;
10181
10182         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10183         if (ret)
10184                 return ret;
10185         drm_atomic_set_fb_for_plane(plane_state, fb);
10186         plane_state->crtc_x = 0;
10187         plane_state->crtc_y = 0;
10188         plane_state->crtc_w = hdisplay;
10189         plane_state->crtc_h = vdisplay;
10190         plane_state->src_x = x << 16;
10191         plane_state->src_y = y << 16;
10192         plane_state->src_w = hdisplay << 16;
10193         plane_state->src_h = vdisplay << 16;
10194
10195         return 0;
10196 }
10197
10198 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10199                                 struct drm_display_mode *mode,
10200                                 struct intel_load_detect_pipe *old,
10201                                 struct drm_modeset_acquire_ctx *ctx)
10202 {
10203         struct intel_crtc *intel_crtc;
10204         struct intel_encoder *intel_encoder =
10205                 intel_attached_encoder(connector);
10206         struct drm_crtc *possible_crtc;
10207         struct drm_encoder *encoder = &intel_encoder->base;
10208         struct drm_crtc *crtc = NULL;
10209         struct drm_device *dev = encoder->dev;
10210         struct drm_framebuffer *fb;
10211         struct drm_mode_config *config = &dev->mode_config;
10212         struct drm_atomic_state *state = NULL;
10213         struct drm_connector_state *connector_state;
10214         struct intel_crtc_state *crtc_state;
10215         int ret, i = -1;
10216
10217         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10218                       connector->base.id, connector->name,
10219                       encoder->base.id, encoder->name);
10220
10221 retry:
10222         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10223         if (ret)
10224                 goto fail;
10225
10226         /*
10227          * Algorithm gets a little messy:
10228          *
10229          *   - if the connector already has an assigned crtc, use it (but make
10230          *     sure it's on first)
10231          *
10232          *   - try to find the first unused crtc that can drive this connector,
10233          *     and use that if we find one
10234          */
10235
10236         /* See if we already have a CRTC for this connector */
10237         if (encoder->crtc) {
10238                 crtc = encoder->crtc;
10239
10240                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10241                 if (ret)
10242                         goto fail;
10243                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10244                 if (ret)
10245                         goto fail;
10246
10247                 old->dpms_mode = connector->dpms;
10248                 old->load_detect_temp = false;
10249
10250                 /* Make sure the crtc and connector are running */
10251                 if (connector->dpms != DRM_MODE_DPMS_ON)
10252                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10253
10254                 return true;
10255         }
10256
10257         /* Find an unused one (if possible) */
10258         for_each_crtc(dev, possible_crtc) {
10259                 i++;
10260                 if (!(encoder->possible_crtcs & (1 << i)))
10261                         continue;
10262                 if (possible_crtc->state->enable)
10263                         continue;
10264
10265                 crtc = possible_crtc;
10266                 break;
10267         }
10268
10269         /*
10270          * If we didn't find an unused CRTC, don't use any.
10271          */
10272         if (!crtc) {
10273                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10274                 goto fail;
10275         }
10276
10277         ret = drm_modeset_lock(&crtc->mutex, ctx);
10278         if (ret)
10279                 goto fail;
10280         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10281         if (ret)
10282                 goto fail;
10283
10284         intel_crtc = to_intel_crtc(crtc);
10285         old->dpms_mode = connector->dpms;
10286         old->load_detect_temp = true;
10287         old->release_fb = NULL;
10288
10289         state = drm_atomic_state_alloc(dev);
10290         if (!state)
10291                 return false;
10292
10293         state->acquire_ctx = ctx;
10294
10295         connector_state = drm_atomic_get_connector_state(state, connector);
10296         if (IS_ERR(connector_state)) {
10297                 ret = PTR_ERR(connector_state);
10298                 goto fail;
10299         }
10300
10301         connector_state->crtc = crtc;
10302         connector_state->best_encoder = &intel_encoder->base;
10303
10304         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10305         if (IS_ERR(crtc_state)) {
10306                 ret = PTR_ERR(crtc_state);
10307                 goto fail;
10308         }
10309
10310         crtc_state->base.active = crtc_state->base.enable = true;
10311
10312         if (!mode)
10313                 mode = &load_detect_mode;
10314
10315         /* We need a framebuffer large enough to accommodate all accesses
10316          * that the plane may generate whilst we perform load detection.
10317          * We can not rely on the fbcon either being present (we get called
10318          * during its initialisation to detect all boot displays, or it may
10319          * not even exist) or that it is large enough to satisfy the
10320          * requested mode.
10321          */
10322         fb = mode_fits_in_fbdev(dev, mode);
10323         if (fb == NULL) {
10324                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10325                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10326                 old->release_fb = fb;
10327         } else
10328                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10329         if (IS_ERR(fb)) {
10330                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10331                 goto fail;
10332         }
10333
10334         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10335         if (ret)
10336                 goto fail;
10337
10338         drm_mode_copy(&crtc_state->base.mode, mode);
10339
10340         if (drm_atomic_commit(state)) {
10341                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10342                 if (old->release_fb)
10343                         old->release_fb->funcs->destroy(old->release_fb);
10344                 goto fail;
10345         }
10346         crtc->primary->crtc = crtc;
10347
10348         /* let the connector get through one full cycle before testing */
10349         intel_wait_for_vblank(dev, intel_crtc->pipe);
10350         return true;
10351
10352 fail:
10353         drm_atomic_state_free(state);
10354         state = NULL;
10355
10356         if (ret == -EDEADLK) {
10357                 drm_modeset_backoff(ctx);
10358                 goto retry;
10359         }
10360
10361         return false;
10362 }
10363
10364 void intel_release_load_detect_pipe(struct drm_connector *connector,
10365                                     struct intel_load_detect_pipe *old,
10366                                     struct drm_modeset_acquire_ctx *ctx)
10367 {
10368         struct drm_device *dev = connector->dev;
10369         struct intel_encoder *intel_encoder =
10370                 intel_attached_encoder(connector);
10371         struct drm_encoder *encoder = &intel_encoder->base;
10372         struct drm_crtc *crtc = encoder->crtc;
10373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10374         struct drm_atomic_state *state;
10375         struct drm_connector_state *connector_state;
10376         struct intel_crtc_state *crtc_state;
10377         int ret;
10378
10379         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10380                       connector->base.id, connector->name,
10381                       encoder->base.id, encoder->name);
10382
10383         if (old->load_detect_temp) {
10384                 state = drm_atomic_state_alloc(dev);
10385                 if (!state)
10386                         goto fail;
10387
10388                 state->acquire_ctx = ctx;
10389
10390                 connector_state = drm_atomic_get_connector_state(state, connector);
10391                 if (IS_ERR(connector_state))
10392                         goto fail;
10393
10394                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10395                 if (IS_ERR(crtc_state))
10396                         goto fail;
10397
10398                 connector_state->best_encoder = NULL;
10399                 connector_state->crtc = NULL;
10400
10401                 crtc_state->base.enable = crtc_state->base.active = false;
10402
10403                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10404                                                       0, 0);
10405                 if (ret)
10406                         goto fail;
10407
10408                 ret = drm_atomic_commit(state);
10409                 if (ret)
10410                         goto fail;
10411
10412                 if (old->release_fb) {
10413                         drm_framebuffer_unregister_private(old->release_fb);
10414                         drm_framebuffer_unreference(old->release_fb);
10415                 }
10416
10417                 return;
10418         }
10419
10420         /* Switch crtc and encoder back off if necessary */
10421         if (old->dpms_mode != DRM_MODE_DPMS_ON)
10422                 connector->funcs->dpms(connector, old->dpms_mode);
10423
10424         return;
10425 fail:
10426         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10427         drm_atomic_state_free(state);
10428 }
10429
10430 static int i9xx_pll_refclk(struct drm_device *dev,
10431                            const struct intel_crtc_state *pipe_config)
10432 {
10433         struct drm_i915_private *dev_priv = dev->dev_private;
10434         u32 dpll = pipe_config->dpll_hw_state.dpll;
10435
10436         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10437                 return dev_priv->vbt.lvds_ssc_freq;
10438         else if (HAS_PCH_SPLIT(dev))
10439                 return 120000;
10440         else if (!IS_GEN2(dev))
10441                 return 96000;
10442         else
10443                 return 48000;
10444 }
10445
10446 /* Returns the clock of the currently programmed mode of the given pipe. */
10447 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10448                                 struct intel_crtc_state *pipe_config)
10449 {
10450         struct drm_device *dev = crtc->base.dev;
10451         struct drm_i915_private *dev_priv = dev->dev_private;
10452         int pipe = pipe_config->cpu_transcoder;
10453         u32 dpll = pipe_config->dpll_hw_state.dpll;
10454         u32 fp;
10455         intel_clock_t clock;
10456         int port_clock;
10457         int refclk = i9xx_pll_refclk(dev, pipe_config);
10458
10459         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10460                 fp = pipe_config->dpll_hw_state.fp0;
10461         else
10462                 fp = pipe_config->dpll_hw_state.fp1;
10463
10464         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10465         if (IS_PINEVIEW(dev)) {
10466                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10467                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10468         } else {
10469                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10470                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471         }
10472
10473         if (!IS_GEN2(dev)) {
10474                 if (IS_PINEVIEW(dev))
10475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10476                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10477                 else
10478                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10479                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10480
10481                 switch (dpll & DPLL_MODE_MASK) {
10482                 case DPLLB_MODE_DAC_SERIAL:
10483                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10484                                 5 : 10;
10485                         break;
10486                 case DPLLB_MODE_LVDS:
10487                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10488                                 7 : 14;
10489                         break;
10490                 default:
10491                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10492                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10493                         return;
10494                 }
10495
10496                 if (IS_PINEVIEW(dev))
10497                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10498                 else
10499                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10500         } else {
10501                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10502                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10503
10504                 if (is_lvds) {
10505                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10506                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10507
10508                         if (lvds & LVDS_CLKB_POWER_UP)
10509                                 clock.p2 = 7;
10510                         else
10511                                 clock.p2 = 14;
10512                 } else {
10513                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10514                                 clock.p1 = 2;
10515                         else {
10516                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10517                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10518                         }
10519                         if (dpll & PLL_P2_DIVIDE_BY_4)
10520                                 clock.p2 = 4;
10521                         else
10522                                 clock.p2 = 2;
10523                 }
10524
10525                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10526         }
10527
10528         /*
10529          * This value includes pixel_multiplier. We will use
10530          * port_clock to compute adjusted_mode.crtc_clock in the
10531          * encoder's get_config() function.
10532          */
10533         pipe_config->port_clock = port_clock;
10534 }
10535
10536 int intel_dotclock_calculate(int link_freq,
10537                              const struct intel_link_m_n *m_n)
10538 {
10539         /*
10540          * The calculation for the data clock is:
10541          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10542          * But we want to avoid losing precison if possible, so:
10543          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10544          *
10545          * and the link clock is simpler:
10546          * link_clock = (m * link_clock) / n
10547          */
10548
10549         if (!m_n->link_n)
10550                 return 0;
10551
10552         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10553 }
10554
10555 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10556                                    struct intel_crtc_state *pipe_config)
10557 {
10558         struct drm_device *dev = crtc->base.dev;
10559
10560         /* read out port_clock from the DPLL */
10561         i9xx_crtc_clock_get(crtc, pipe_config);
10562
10563         /*
10564          * This value does not include pixel_multiplier.
10565          * We will check that port_clock and adjusted_mode.crtc_clock
10566          * agree once we know their relationship in the encoder's
10567          * get_config() function.
10568          */
10569         pipe_config->base.adjusted_mode.crtc_clock =
10570                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10571                                          &pipe_config->fdi_m_n);
10572 }
10573
10574 /** Returns the currently programmed mode of the given pipe. */
10575 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10576                                              struct drm_crtc *crtc)
10577 {
10578         struct drm_i915_private *dev_priv = dev->dev_private;
10579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10580         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10581         struct drm_display_mode *mode;
10582         struct intel_crtc_state pipe_config;
10583         int htot = I915_READ(HTOTAL(cpu_transcoder));
10584         int hsync = I915_READ(HSYNC(cpu_transcoder));
10585         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10586         int vsync = I915_READ(VSYNC(cpu_transcoder));
10587         enum pipe pipe = intel_crtc->pipe;
10588
10589         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10590         if (!mode)
10591                 return NULL;
10592
10593         /*
10594          * Construct a pipe_config sufficient for getting the clock info
10595          * back out of crtc_clock_get.
10596          *
10597          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10598          * to use a real value here instead.
10599          */
10600         pipe_config.cpu_transcoder = (enum transcoder) pipe;
10601         pipe_config.pixel_multiplier = 1;
10602         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10603         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10604         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10605         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10606
10607         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10608         mode->hdisplay = (htot & 0xffff) + 1;
10609         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10610         mode->hsync_start = (hsync & 0xffff) + 1;
10611         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10612         mode->vdisplay = (vtot & 0xffff) + 1;
10613         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10614         mode->vsync_start = (vsync & 0xffff) + 1;
10615         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10616
10617         drm_mode_set_name(mode);
10618
10619         return mode;
10620 }
10621
10622 void intel_mark_busy(struct drm_device *dev)
10623 {
10624         struct drm_i915_private *dev_priv = dev->dev_private;
10625
10626         if (dev_priv->mm.busy)
10627                 return;
10628
10629         intel_runtime_pm_get(dev_priv);
10630         i915_update_gfx_val(dev_priv);
10631         if (INTEL_INFO(dev)->gen >= 6)
10632                 gen6_rps_busy(dev_priv);
10633         dev_priv->mm.busy = true;
10634 }
10635
10636 void intel_mark_idle(struct drm_device *dev)
10637 {
10638         struct drm_i915_private *dev_priv = dev->dev_private;
10639
10640         if (!dev_priv->mm.busy)
10641                 return;
10642
10643         dev_priv->mm.busy = false;
10644
10645         if (INTEL_INFO(dev)->gen >= 6)
10646                 gen6_rps_idle(dev->dev_private);
10647
10648         intel_runtime_pm_put(dev_priv);
10649 }
10650
10651 static void intel_crtc_destroy(struct drm_crtc *crtc)
10652 {
10653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10654         struct drm_device *dev = crtc->dev;
10655         struct intel_unpin_work *work;
10656
10657         spin_lock_irq(&dev->event_lock);
10658         work = intel_crtc->unpin_work;
10659         intel_crtc->unpin_work = NULL;
10660         spin_unlock_irq(&dev->event_lock);
10661
10662         if (work) {
10663                 cancel_work_sync(&work->work);
10664                 kfree(work);
10665         }
10666
10667         drm_crtc_cleanup(crtc);
10668
10669         kfree(intel_crtc);
10670 }
10671
10672 static void intel_unpin_work_fn(struct work_struct *__work)
10673 {
10674         struct intel_unpin_work *work =
10675                 container_of(__work, struct intel_unpin_work, work);
10676         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10677         struct drm_device *dev = crtc->base.dev;
10678         struct drm_plane *primary = crtc->base.primary;
10679
10680         mutex_lock(&dev->struct_mutex);
10681         intel_unpin_fb_obj(work->old_fb, primary->state);
10682         drm_gem_object_unreference(&work->pending_flip_obj->base);
10683
10684         if (work->flip_queued_req)
10685                 i915_gem_request_assign(&work->flip_queued_req, NULL);
10686         mutex_unlock(&dev->struct_mutex);
10687
10688         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10689         drm_framebuffer_unreference(work->old_fb);
10690
10691         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10692         atomic_dec(&crtc->unpin_work_count);
10693
10694         kfree(work);
10695 }
10696
10697 static void do_intel_finish_page_flip(struct drm_device *dev,
10698                                       struct drm_crtc *crtc)
10699 {
10700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10701         struct intel_unpin_work *work;
10702         unsigned long flags;
10703
10704         /* Ignore early vblank irqs */
10705         if (intel_crtc == NULL)
10706                 return;
10707
10708         /*
10709          * This is called both by irq handlers and the reset code (to complete
10710          * lost pageflips) so needs the full irqsave spinlocks.
10711          */
10712         spin_lock_irqsave(&dev->event_lock, flags);
10713         work = intel_crtc->unpin_work;
10714
10715         /* Ensure we don't miss a work->pending update ... */
10716         smp_rmb();
10717
10718         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10719                 spin_unlock_irqrestore(&dev->event_lock, flags);
10720                 return;
10721         }
10722
10723         page_flip_completed(intel_crtc);
10724
10725         spin_unlock_irqrestore(&dev->event_lock, flags);
10726 }
10727
10728 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10729 {
10730         struct drm_i915_private *dev_priv = dev->dev_private;
10731         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10732
10733         do_intel_finish_page_flip(dev, crtc);
10734 }
10735
10736 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10737 {
10738         struct drm_i915_private *dev_priv = dev->dev_private;
10739         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10740
10741         do_intel_finish_page_flip(dev, crtc);
10742 }
10743
10744 /* Is 'a' after or equal to 'b'? */
10745 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10746 {
10747         return !((a - b) & 0x80000000);
10748 }
10749
10750 static bool page_flip_finished(struct intel_crtc *crtc)
10751 {
10752         struct drm_device *dev = crtc->base.dev;
10753         struct drm_i915_private *dev_priv = dev->dev_private;
10754
10755         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10756             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10757                 return true;
10758
10759         /*
10760          * The relevant registers doen't exist on pre-ctg.
10761          * As the flip done interrupt doesn't trigger for mmio
10762          * flips on gmch platforms, a flip count check isn't
10763          * really needed there. But since ctg has the registers,
10764          * include it in the check anyway.
10765          */
10766         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10767                 return true;
10768
10769         /*
10770          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10771          * used the same base address. In that case the mmio flip might
10772          * have completed, but the CS hasn't even executed the flip yet.
10773          *
10774          * A flip count check isn't enough as the CS might have updated
10775          * the base address just after start of vblank, but before we
10776          * managed to process the interrupt. This means we'd complete the
10777          * CS flip too soon.
10778          *
10779          * Combining both checks should get us a good enough result. It may
10780          * still happen that the CS flip has been executed, but has not
10781          * yet actually completed. But in case the base address is the same
10782          * anyway, we don't really care.
10783          */
10784         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10785                 crtc->unpin_work->gtt_offset &&
10786                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10787                                     crtc->unpin_work->flip_count);
10788 }
10789
10790 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10791 {
10792         struct drm_i915_private *dev_priv = dev->dev_private;
10793         struct intel_crtc *intel_crtc =
10794                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10795         unsigned long flags;
10796
10797
10798         /*
10799          * This is called both by irq handlers and the reset code (to complete
10800          * lost pageflips) so needs the full irqsave spinlocks.
10801          *
10802          * NB: An MMIO update of the plane base pointer will also
10803          * generate a page-flip completion irq, i.e. every modeset
10804          * is also accompanied by a spurious intel_prepare_page_flip().
10805          */
10806         spin_lock_irqsave(&dev->event_lock, flags);
10807         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10808                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10809         spin_unlock_irqrestore(&dev->event_lock, flags);
10810 }
10811
10812 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10813 {
10814         /* Ensure that the work item is consistent when activating it ... */
10815         smp_wmb();
10816         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10817         /* and that it is marked active as soon as the irq could fire. */
10818         smp_wmb();
10819 }
10820
10821 static int intel_gen2_queue_flip(struct drm_device *dev,
10822                                  struct drm_crtc *crtc,
10823                                  struct drm_framebuffer *fb,
10824                                  struct drm_i915_gem_object *obj,
10825                                  struct drm_i915_gem_request *req,
10826                                  uint32_t flags)
10827 {
10828         struct intel_engine_cs *ring = req->ring;
10829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10830         u32 flip_mask;
10831         int ret;
10832
10833         ret = intel_ring_begin(req, 6);
10834         if (ret)
10835                 return ret;
10836
10837         /* Can't queue multiple flips, so wait for the previous
10838          * one to finish before executing the next.
10839          */
10840         if (intel_crtc->plane)
10841                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10842         else
10843                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10844         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10845         intel_ring_emit(ring, MI_NOOP);
10846         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10847                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10848         intel_ring_emit(ring, fb->pitches[0]);
10849         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10850         intel_ring_emit(ring, 0); /* aux display base address, unused */
10851
10852         intel_mark_page_flip_active(intel_crtc);
10853         return 0;
10854 }
10855
10856 static int intel_gen3_queue_flip(struct drm_device *dev,
10857                                  struct drm_crtc *crtc,
10858                                  struct drm_framebuffer *fb,
10859                                  struct drm_i915_gem_object *obj,
10860                                  struct drm_i915_gem_request *req,
10861                                  uint32_t flags)
10862 {
10863         struct intel_engine_cs *ring = req->ring;
10864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10865         u32 flip_mask;
10866         int ret;
10867
10868         ret = intel_ring_begin(req, 6);
10869         if (ret)
10870                 return ret;
10871
10872         if (intel_crtc->plane)
10873                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10874         else
10875                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10876         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10877         intel_ring_emit(ring, MI_NOOP);
10878         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10879                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10880         intel_ring_emit(ring, fb->pitches[0]);
10881         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10882         intel_ring_emit(ring, MI_NOOP);
10883
10884         intel_mark_page_flip_active(intel_crtc);
10885         return 0;
10886 }
10887
10888 static int intel_gen4_queue_flip(struct drm_device *dev,
10889                                  struct drm_crtc *crtc,
10890                                  struct drm_framebuffer *fb,
10891                                  struct drm_i915_gem_object *obj,
10892                                  struct drm_i915_gem_request *req,
10893                                  uint32_t flags)
10894 {
10895         struct intel_engine_cs *ring = req->ring;
10896         struct drm_i915_private *dev_priv = dev->dev_private;
10897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10898         uint32_t pf, pipesrc;
10899         int ret;
10900
10901         ret = intel_ring_begin(req, 4);
10902         if (ret)
10903                 return ret;
10904
10905         /* i965+ uses the linear or tiled offsets from the
10906          * Display Registers (which do not change across a page-flip)
10907          * so we need only reprogram the base address.
10908          */
10909         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10910                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10911         intel_ring_emit(ring, fb->pitches[0]);
10912         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10913                         obj->tiling_mode);
10914
10915         /* XXX Enabling the panel-fitter across page-flip is so far
10916          * untested on non-native modes, so ignore it for now.
10917          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10918          */
10919         pf = 0;
10920         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10921         intel_ring_emit(ring, pf | pipesrc);
10922
10923         intel_mark_page_flip_active(intel_crtc);
10924         return 0;
10925 }
10926
10927 static int intel_gen6_queue_flip(struct drm_device *dev,
10928                                  struct drm_crtc *crtc,
10929                                  struct drm_framebuffer *fb,
10930                                  struct drm_i915_gem_object *obj,
10931                                  struct drm_i915_gem_request *req,
10932                                  uint32_t flags)
10933 {
10934         struct intel_engine_cs *ring = req->ring;
10935         struct drm_i915_private *dev_priv = dev->dev_private;
10936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10937         uint32_t pf, pipesrc;
10938         int ret;
10939
10940         ret = intel_ring_begin(req, 4);
10941         if (ret)
10942                 return ret;
10943
10944         intel_ring_emit(ring, MI_DISPLAY_FLIP |
10945                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10946         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10947         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10948
10949         /* Contrary to the suggestions in the documentation,
10950          * "Enable Panel Fitter" does not seem to be required when page
10951          * flipping with a non-native mode, and worse causes a normal
10952          * modeset to fail.
10953          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10954          */
10955         pf = 0;
10956         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10957         intel_ring_emit(ring, pf | pipesrc);
10958
10959         intel_mark_page_flip_active(intel_crtc);
10960         return 0;
10961 }
10962
10963 static int intel_gen7_queue_flip(struct drm_device *dev,
10964                                  struct drm_crtc *crtc,
10965                                  struct drm_framebuffer *fb,
10966                                  struct drm_i915_gem_object *obj,
10967                                  struct drm_i915_gem_request *req,
10968                                  uint32_t flags)
10969 {
10970         struct intel_engine_cs *ring = req->ring;
10971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10972         uint32_t plane_bit = 0;
10973         int len, ret;
10974
10975         switch (intel_crtc->plane) {
10976         case PLANE_A:
10977                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10978                 break;
10979         case PLANE_B:
10980                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10981                 break;
10982         case PLANE_C:
10983                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10984                 break;
10985         default:
10986                 WARN_ONCE(1, "unknown plane in flip command\n");
10987                 return -ENODEV;
10988         }
10989
10990         len = 4;
10991         if (ring->id == RCS) {
10992                 len += 6;
10993                 /*
10994                  * On Gen 8, SRM is now taking an extra dword to accommodate
10995                  * 48bits addresses, and we need a NOOP for the batch size to
10996                  * stay even.
10997                  */
10998                 if (IS_GEN8(dev))
10999                         len += 2;
11000         }
11001
11002         /*
11003          * BSpec MI_DISPLAY_FLIP for IVB:
11004          * "The full packet must be contained within the same cache line."
11005          *
11006          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11007          * cacheline, if we ever start emitting more commands before
11008          * the MI_DISPLAY_FLIP we may need to first emit everything else,
11009          * then do the cacheline alignment, and finally emit the
11010          * MI_DISPLAY_FLIP.
11011          */
11012         ret = intel_ring_cacheline_align(req);
11013         if (ret)
11014                 return ret;
11015
11016         ret = intel_ring_begin(req, len);
11017         if (ret)
11018                 return ret;
11019
11020         /* Unmask the flip-done completion message. Note that the bspec says that
11021          * we should do this for both the BCS and RCS, and that we must not unmask
11022          * more than one flip event at any time (or ensure that one flip message
11023          * can be sent by waiting for flip-done prior to queueing new flips).
11024          * Experimentation says that BCS works despite DERRMR masking all
11025          * flip-done completion events and that unmasking all planes at once
11026          * for the RCS also doesn't appear to drop events. Setting the DERRMR
11027          * to zero does lead to lockups within MI_DISPLAY_FLIP.
11028          */
11029         if (ring->id == RCS) {
11030                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11031                 intel_ring_emit(ring, DERRMR);
11032                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11033                                         DERRMR_PIPEB_PRI_FLIP_DONE |
11034                                         DERRMR_PIPEC_PRI_FLIP_DONE));
11035                 if (IS_GEN8(dev))
11036                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11037                                               MI_SRM_LRM_GLOBAL_GTT);
11038                 else
11039                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11040                                               MI_SRM_LRM_GLOBAL_GTT);
11041                 intel_ring_emit(ring, DERRMR);
11042                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11043                 if (IS_GEN8(dev)) {
11044                         intel_ring_emit(ring, 0);
11045                         intel_ring_emit(ring, MI_NOOP);
11046                 }
11047         }
11048
11049         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11050         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11051         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11052         intel_ring_emit(ring, (MI_NOOP));
11053
11054         intel_mark_page_flip_active(intel_crtc);
11055         return 0;
11056 }
11057
11058 static bool use_mmio_flip(struct intel_engine_cs *ring,
11059                           struct drm_i915_gem_object *obj)
11060 {
11061         /*
11062          * This is not being used for older platforms, because
11063          * non-availability of flip done interrupt forces us to use
11064          * CS flips. Older platforms derive flip done using some clever
11065          * tricks involving the flip_pending status bits and vblank irqs.
11066          * So using MMIO flips there would disrupt this mechanism.
11067          */
11068
11069         if (ring == NULL)
11070                 return true;
11071
11072         if (INTEL_INFO(ring->dev)->gen < 5)
11073                 return false;
11074
11075         if (i915.use_mmio_flip < 0)
11076                 return false;
11077         else if (i915.use_mmio_flip > 0)
11078                 return true;
11079         else if (i915.enable_execlists)
11080                 return true;
11081         else
11082                 return ring != i915_gem_request_get_ring(obj->last_write_req);
11083 }
11084
11085 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11086 {
11087         struct drm_device *dev = intel_crtc->base.dev;
11088         struct drm_i915_private *dev_priv = dev->dev_private;
11089         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11090         const enum pipe pipe = intel_crtc->pipe;
11091         u32 ctl, stride;
11092
11093         ctl = I915_READ(PLANE_CTL(pipe, 0));
11094         ctl &= ~PLANE_CTL_TILED_MASK;
11095         switch (fb->modifier[0]) {
11096         case DRM_FORMAT_MOD_NONE:
11097                 break;
11098         case I915_FORMAT_MOD_X_TILED:
11099                 ctl |= PLANE_CTL_TILED_X;
11100                 break;
11101         case I915_FORMAT_MOD_Y_TILED:
11102                 ctl |= PLANE_CTL_TILED_Y;
11103                 break;
11104         case I915_FORMAT_MOD_Yf_TILED:
11105                 ctl |= PLANE_CTL_TILED_YF;
11106                 break;
11107         default:
11108                 MISSING_CASE(fb->modifier[0]);
11109         }
11110
11111         /*
11112          * The stride is either expressed as a multiple of 64 bytes chunks for
11113          * linear buffers or in number of tiles for tiled buffers.
11114          */
11115         stride = fb->pitches[0] /
11116                  intel_fb_stride_alignment(dev, fb->modifier[0],
11117                                            fb->pixel_format);
11118
11119         /*
11120          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11121          * PLANE_SURF updates, the update is then guaranteed to be atomic.
11122          */
11123         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11124         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11125
11126         I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11127         POSTING_READ(PLANE_SURF(pipe, 0));
11128 }
11129
11130 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11131 {
11132         struct drm_device *dev = intel_crtc->base.dev;
11133         struct drm_i915_private *dev_priv = dev->dev_private;
11134         struct intel_framebuffer *intel_fb =
11135                 to_intel_framebuffer(intel_crtc->base.primary->fb);
11136         struct drm_i915_gem_object *obj = intel_fb->obj;
11137         u32 dspcntr;
11138         u32 reg;
11139
11140         reg = DSPCNTR(intel_crtc->plane);
11141         dspcntr = I915_READ(reg);
11142
11143         if (obj->tiling_mode != I915_TILING_NONE)
11144                 dspcntr |= DISPPLANE_TILED;
11145         else
11146                 dspcntr &= ~DISPPLANE_TILED;
11147
11148         I915_WRITE(reg, dspcntr);
11149
11150         I915_WRITE(DSPSURF(intel_crtc->plane),
11151                    intel_crtc->unpin_work->gtt_offset);
11152         POSTING_READ(DSPSURF(intel_crtc->plane));
11153
11154 }
11155
11156 /*
11157  * XXX: This is the temporary way to update the plane registers until we get
11158  * around to using the usual plane update functions for MMIO flips
11159  */
11160 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11161 {
11162         struct drm_device *dev = intel_crtc->base.dev;
11163         u32 start_vbl_count;
11164
11165         intel_mark_page_flip_active(intel_crtc);
11166
11167         intel_pipe_update_start(intel_crtc, &start_vbl_count);
11168
11169         if (INTEL_INFO(dev)->gen >= 9)
11170                 skl_do_mmio_flip(intel_crtc);
11171         else
11172                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11173                 ilk_do_mmio_flip(intel_crtc);
11174
11175         intel_pipe_update_end(intel_crtc, start_vbl_count);
11176 }
11177
11178 static void intel_mmio_flip_work_func(struct work_struct *work)
11179 {
11180         struct intel_mmio_flip *mmio_flip =
11181                 container_of(work, struct intel_mmio_flip, work);
11182
11183         if (mmio_flip->req)
11184                 WARN_ON(__i915_wait_request(mmio_flip->req,
11185                                             mmio_flip->crtc->reset_counter,
11186                                             false, NULL,
11187                                             &mmio_flip->i915->rps.mmioflips));
11188
11189         intel_do_mmio_flip(mmio_flip->crtc);
11190
11191         i915_gem_request_unreference__unlocked(mmio_flip->req);
11192         kfree(mmio_flip);
11193 }
11194
11195 static int intel_queue_mmio_flip(struct drm_device *dev,
11196                                  struct drm_crtc *crtc,
11197                                  struct drm_framebuffer *fb,
11198                                  struct drm_i915_gem_object *obj,
11199                                  struct intel_engine_cs *ring,
11200                                  uint32_t flags)
11201 {
11202         struct intel_mmio_flip *mmio_flip;
11203
11204         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11205         if (mmio_flip == NULL)
11206                 return -ENOMEM;
11207
11208         mmio_flip->i915 = to_i915(dev);
11209         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11210         mmio_flip->crtc = to_intel_crtc(crtc);
11211
11212         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11213         schedule_work(&mmio_flip->work);
11214
11215         return 0;
11216 }
11217
11218 static int intel_default_queue_flip(struct drm_device *dev,
11219                                     struct drm_crtc *crtc,
11220                                     struct drm_framebuffer *fb,
11221                                     struct drm_i915_gem_object *obj,
11222                                     struct drm_i915_gem_request *req,
11223                                     uint32_t flags)
11224 {
11225         return -ENODEV;
11226 }
11227
11228 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11229                                          struct drm_crtc *crtc)
11230 {
11231         struct drm_i915_private *dev_priv = dev->dev_private;
11232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11233         struct intel_unpin_work *work = intel_crtc->unpin_work;
11234         u32 addr;
11235
11236         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11237                 return true;
11238
11239         if (!work->enable_stall_check)
11240                 return false;
11241
11242         if (work->flip_ready_vblank == 0) {
11243                 if (work->flip_queued_req &&
11244                     !i915_gem_request_completed(work->flip_queued_req, true))
11245                         return false;
11246
11247                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11248         }
11249
11250         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11251                 return false;
11252
11253         /* Potential stall - if we see that the flip has happened,
11254          * assume a missed interrupt. */
11255         if (INTEL_INFO(dev)->gen >= 4)
11256                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11257         else
11258                 addr = I915_READ(DSPADDR(intel_crtc->plane));
11259
11260         /* There is a potential issue here with a false positive after a flip
11261          * to the same address. We could address this by checking for a
11262          * non-incrementing frame counter.
11263          */
11264         return addr == work->gtt_offset;
11265 }
11266
11267 void intel_check_page_flip(struct drm_device *dev, int pipe)
11268 {
11269         struct drm_i915_private *dev_priv = dev->dev_private;
11270         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11272         struct intel_unpin_work *work;
11273
11274         WARN_ON(!in_interrupt());
11275
11276         if (crtc == NULL)
11277                 return;
11278
11279         spin_lock(&dev->event_lock);
11280         work = intel_crtc->unpin_work;
11281         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11282                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11283                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11284                 page_flip_completed(intel_crtc);
11285                 work = NULL;
11286         }
11287         if (work != NULL &&
11288             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11289                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11290         spin_unlock(&dev->event_lock);
11291 }
11292
11293 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11294                                 struct drm_framebuffer *fb,
11295                                 struct drm_pending_vblank_event *event,
11296                                 uint32_t page_flip_flags)
11297 {
11298         struct drm_device *dev = crtc->dev;
11299         struct drm_i915_private *dev_priv = dev->dev_private;
11300         struct drm_framebuffer *old_fb = crtc->primary->fb;
11301         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11303         struct drm_plane *primary = crtc->primary;
11304         enum pipe pipe = intel_crtc->pipe;
11305         struct intel_unpin_work *work;
11306         struct intel_engine_cs *ring;
11307         bool mmio_flip;
11308         struct drm_i915_gem_request *request = NULL;
11309         int ret;
11310
11311         /*
11312          * drm_mode_page_flip_ioctl() should already catch this, but double
11313          * check to be safe.  In the future we may enable pageflipping from
11314          * a disabled primary plane.
11315          */
11316         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11317                 return -EBUSY;
11318
11319         /* Can't change pixel format via MI display flips. */
11320         if (fb->pixel_format != crtc->primary->fb->pixel_format)
11321                 return -EINVAL;
11322
11323         /*
11324          * TILEOFF/LINOFF registers can't be changed via MI display flips.
11325          * Note that pitch changes could also affect these register.
11326          */
11327         if (INTEL_INFO(dev)->gen > 3 &&
11328             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11329              fb->pitches[0] != crtc->primary->fb->pitches[0]))
11330                 return -EINVAL;
11331
11332         if (i915_terminally_wedged(&dev_priv->gpu_error))
11333                 goto out_hang;
11334
11335         work = kzalloc(sizeof(*work), GFP_KERNEL);
11336         if (work == NULL)
11337                 return -ENOMEM;
11338
11339         work->event = event;
11340         work->crtc = crtc;
11341         work->old_fb = old_fb;
11342         INIT_WORK(&work->work, intel_unpin_work_fn);
11343
11344         ret = drm_crtc_vblank_get(crtc);
11345         if (ret)
11346                 goto free_work;
11347
11348         /* We borrow the event spin lock for protecting unpin_work */
11349         spin_lock_irq(&dev->event_lock);
11350         if (intel_crtc->unpin_work) {
11351                 /* Before declaring the flip queue wedged, check if
11352                  * the hardware completed the operation behind our backs.
11353                  */
11354                 if (__intel_pageflip_stall_check(dev, crtc)) {
11355                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11356                         page_flip_completed(intel_crtc);
11357                 } else {
11358                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11359                         spin_unlock_irq(&dev->event_lock);
11360
11361                         drm_crtc_vblank_put(crtc);
11362                         kfree(work);
11363                         return -EBUSY;
11364                 }
11365         }
11366         intel_crtc->unpin_work = work;
11367         spin_unlock_irq(&dev->event_lock);
11368
11369         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11370                 flush_workqueue(dev_priv->wq);
11371
11372         /* Reference the objects for the scheduled work. */
11373         drm_framebuffer_reference(work->old_fb);
11374         drm_gem_object_reference(&obj->base);
11375
11376         crtc->primary->fb = fb;
11377         update_state_fb(crtc->primary);
11378
11379         work->pending_flip_obj = obj;
11380
11381         ret = i915_mutex_lock_interruptible(dev);
11382         if (ret)
11383                 goto cleanup;
11384
11385         atomic_inc(&intel_crtc->unpin_work_count);
11386         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11387
11388         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11389                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11390
11391         if (IS_VALLEYVIEW(dev)) {
11392                 ring = &dev_priv->ring[BCS];
11393                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11394                         /* vlv: DISPLAY_FLIP fails to change tiling */
11395                         ring = NULL;
11396         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11397                 ring = &dev_priv->ring[BCS];
11398         } else if (INTEL_INFO(dev)->gen >= 7) {
11399                 ring = i915_gem_request_get_ring(obj->last_write_req);
11400                 if (ring == NULL || ring->id != RCS)
11401                         ring = &dev_priv->ring[BCS];
11402         } else {
11403                 ring = &dev_priv->ring[RCS];
11404         }
11405
11406         mmio_flip = use_mmio_flip(ring, obj);
11407
11408         /* When using CS flips, we want to emit semaphores between rings.
11409          * However, when using mmio flips we will create a task to do the
11410          * synchronisation, so all we want here is to pin the framebuffer
11411          * into the display plane and skip any waits.
11412          */
11413         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11414                                          crtc->primary->state,
11415                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11416         if (ret)
11417                 goto cleanup_pending;
11418
11419         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11420                                                   + intel_crtc->dspaddr_offset;
11421
11422         if (mmio_flip) {
11423                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11424                                             page_flip_flags);
11425                 if (ret)
11426                         goto cleanup_unpin;
11427
11428                 i915_gem_request_assign(&work->flip_queued_req,
11429                                         obj->last_write_req);
11430         } else {
11431                 if (!request) {
11432                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11433                         if (ret)
11434                                 goto cleanup_unpin;
11435                 }
11436
11437                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11438                                                    page_flip_flags);
11439                 if (ret)
11440                         goto cleanup_unpin;
11441
11442                 i915_gem_request_assign(&work->flip_queued_req, request);
11443         }
11444
11445         if (request)
11446                 i915_add_request_no_flush(request);
11447
11448         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11449         work->enable_stall_check = true;
11450
11451         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11452                           to_intel_plane(primary)->frontbuffer_bit);
11453         mutex_unlock(&dev->struct_mutex);
11454
11455         intel_fbc_disable_crtc(intel_crtc);
11456         intel_frontbuffer_flip_prepare(dev,
11457                                        to_intel_plane(primary)->frontbuffer_bit);
11458
11459         trace_i915_flip_request(intel_crtc->plane, obj);
11460
11461         return 0;
11462
11463 cleanup_unpin:
11464         intel_unpin_fb_obj(fb, crtc->primary->state);
11465 cleanup_pending:
11466         if (request)
11467                 i915_gem_request_cancel(request);
11468         atomic_dec(&intel_crtc->unpin_work_count);
11469         mutex_unlock(&dev->struct_mutex);
11470 cleanup:
11471         crtc->primary->fb = old_fb;
11472         update_state_fb(crtc->primary);
11473
11474         drm_gem_object_unreference_unlocked(&obj->base);
11475         drm_framebuffer_unreference(work->old_fb);
11476
11477         spin_lock_irq(&dev->event_lock);
11478         intel_crtc->unpin_work = NULL;
11479         spin_unlock_irq(&dev->event_lock);
11480
11481         drm_crtc_vblank_put(crtc);
11482 free_work:
11483         kfree(work);
11484
11485         if (ret == -EIO) {
11486                 struct drm_atomic_state *state;
11487                 struct drm_plane_state *plane_state;
11488
11489 out_hang:
11490                 state = drm_atomic_state_alloc(dev);
11491                 if (!state)
11492                         return -ENOMEM;
11493                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11494
11495 retry:
11496                 plane_state = drm_atomic_get_plane_state(state, primary);
11497                 ret = PTR_ERR_OR_ZERO(plane_state);
11498                 if (!ret) {
11499                         drm_atomic_set_fb_for_plane(plane_state, fb);
11500
11501                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11502                         if (!ret)
11503                                 ret = drm_atomic_commit(state);
11504                 }
11505
11506                 if (ret == -EDEADLK) {
11507                         drm_modeset_backoff(state->acquire_ctx);
11508                         drm_atomic_state_clear(state);
11509                         goto retry;
11510                 }
11511
11512                 if (ret)
11513                         drm_atomic_state_free(state);
11514
11515                 if (ret == 0 && event) {
11516                         spin_lock_irq(&dev->event_lock);
11517                         drm_send_vblank_event(dev, pipe, event);
11518                         spin_unlock_irq(&dev->event_lock);
11519                 }
11520         }
11521         return ret;
11522 }
11523
11524
11525 /**
11526  * intel_wm_need_update - Check whether watermarks need updating
11527  * @plane: drm plane
11528  * @state: new plane state
11529  *
11530  * Check current plane state versus the new one to determine whether
11531  * watermarks need to be recalculated.
11532  *
11533  * Returns true or false.
11534  */
11535 static bool intel_wm_need_update(struct drm_plane *plane,
11536                                  struct drm_plane_state *state)
11537 {
11538         /* Update watermarks on tiling changes. */
11539         if (!plane->state->fb || !state->fb ||
11540             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11541             plane->state->rotation != state->rotation)
11542                 return true;
11543
11544         if (plane->state->crtc_w != state->crtc_w)
11545                 return true;
11546
11547         return false;
11548 }
11549
11550 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11551                                     struct drm_plane_state *plane_state)
11552 {
11553         struct drm_crtc *crtc = crtc_state->crtc;
11554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11555         struct drm_plane *plane = plane_state->plane;
11556         struct drm_device *dev = crtc->dev;
11557         struct drm_i915_private *dev_priv = dev->dev_private;
11558         struct intel_plane_state *old_plane_state =
11559                 to_intel_plane_state(plane->state);
11560         int idx = intel_crtc->base.base.id, ret;
11561         int i = drm_plane_index(plane);
11562         bool mode_changed = needs_modeset(crtc_state);
11563         bool was_crtc_enabled = crtc->state->active;
11564         bool is_crtc_enabled = crtc_state->active;
11565
11566         bool turn_off, turn_on, visible, was_visible;
11567         struct drm_framebuffer *fb = plane_state->fb;
11568
11569         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11570             plane->type != DRM_PLANE_TYPE_CURSOR) {
11571                 ret = skl_update_scaler_plane(
11572                         to_intel_crtc_state(crtc_state),
11573                         to_intel_plane_state(plane_state));
11574                 if (ret)
11575                         return ret;
11576         }
11577
11578         /*
11579          * Disabling a plane is always okay; we just need to update
11580          * fb tracking in a special way since cleanup_fb() won't
11581          * get called by the plane helpers.
11582          */
11583         if (old_plane_state->base.fb && !fb)
11584                 intel_crtc->atomic.disabled_planes |= 1 << i;
11585
11586         was_visible = old_plane_state->visible;
11587         visible = to_intel_plane_state(plane_state)->visible;
11588
11589         if (!was_crtc_enabled && WARN_ON(was_visible))
11590                 was_visible = false;
11591
11592         if (!is_crtc_enabled && WARN_ON(visible))
11593                 visible = false;
11594
11595         if (!was_visible && !visible)
11596                 return 0;
11597
11598         turn_off = was_visible && (!visible || mode_changed);
11599         turn_on = visible && (!was_visible || mode_changed);
11600
11601         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11602                          plane->base.id, fb ? fb->base.id : -1);
11603
11604         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11605                          plane->base.id, was_visible, visible,
11606                          turn_off, turn_on, mode_changed);
11607
11608         if (turn_on) {
11609                 intel_crtc->atomic.update_wm_pre = true;
11610                 /* must disable cxsr around plane enable/disable */
11611                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11612                         intel_crtc->atomic.disable_cxsr = true;
11613                         /* to potentially re-enable cxsr */
11614                         intel_crtc->atomic.wait_vblank = true;
11615                         intel_crtc->atomic.update_wm_post = true;
11616                 }
11617         } else if (turn_off) {
11618                 intel_crtc->atomic.update_wm_post = true;
11619                 /* must disable cxsr around plane enable/disable */
11620                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11621                         if (is_crtc_enabled)
11622                                 intel_crtc->atomic.wait_vblank = true;
11623                         intel_crtc->atomic.disable_cxsr = true;
11624                 }
11625         } else if (intel_wm_need_update(plane, plane_state)) {
11626                 intel_crtc->atomic.update_wm_pre = true;
11627         }
11628
11629         if (visible)
11630                 intel_crtc->atomic.fb_bits |=
11631                         to_intel_plane(plane)->frontbuffer_bit;
11632
11633         switch (plane->type) {
11634         case DRM_PLANE_TYPE_PRIMARY:
11635                 intel_crtc->atomic.wait_for_flips = true;
11636                 intel_crtc->atomic.pre_disable_primary = turn_off;
11637                 intel_crtc->atomic.post_enable_primary = turn_on;
11638
11639                 if (turn_off) {
11640                         /*
11641                          * FIXME: Actually if we will still have any other
11642                          * plane enabled on the pipe we could let IPS enabled
11643                          * still, but for now lets consider that when we make
11644                          * primary invisible by setting DSPCNTR to 0 on
11645                          * update_primary_plane function IPS needs to be
11646                          * disable.
11647                          */
11648                         intel_crtc->atomic.disable_ips = true;
11649
11650                         intel_crtc->atomic.disable_fbc = true;
11651                 }
11652
11653                 /*
11654                  * FBC does not work on some platforms for rotated
11655                  * planes, so disable it when rotation is not 0 and
11656                  * update it when rotation is set back to 0.
11657                  *
11658                  * FIXME: This is redundant with the fbc update done in
11659                  * the primary plane enable function except that that
11660                  * one is done too late. We eventually need to unify
11661                  * this.
11662                  */
11663
11664                 if (visible &&
11665                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11666                     dev_priv->fbc.crtc == intel_crtc &&
11667                     plane_state->rotation != BIT(DRM_ROTATE_0))
11668                         intel_crtc->atomic.disable_fbc = true;
11669
11670                 /*
11671                  * BDW signals flip done immediately if the plane
11672                  * is disabled, even if the plane enable is already
11673                  * armed to occur at the next vblank :(
11674                  */
11675                 if (turn_on && IS_BROADWELL(dev))
11676                         intel_crtc->atomic.wait_vblank = true;
11677
11678                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11679                 break;
11680         case DRM_PLANE_TYPE_CURSOR:
11681                 break;
11682         case DRM_PLANE_TYPE_OVERLAY:
11683                 if (turn_off && !mode_changed) {
11684                         intel_crtc->atomic.wait_vblank = true;
11685                         intel_crtc->atomic.update_sprite_watermarks |=
11686                                 1 << i;
11687                 }
11688         }
11689         return 0;
11690 }
11691
11692 static bool encoders_cloneable(const struct intel_encoder *a,
11693                                const struct intel_encoder *b)
11694 {
11695         /* masks could be asymmetric, so check both ways */
11696         return a == b || (a->cloneable & (1 << b->type) &&
11697                           b->cloneable & (1 << a->type));
11698 }
11699
11700 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11701                                          struct intel_crtc *crtc,
11702                                          struct intel_encoder *encoder)
11703 {
11704         struct intel_encoder *source_encoder;
11705         struct drm_connector *connector;
11706         struct drm_connector_state *connector_state;
11707         int i;
11708
11709         for_each_connector_in_state(state, connector, connector_state, i) {
11710                 if (connector_state->crtc != &crtc->base)
11711                         continue;
11712
11713                 source_encoder =
11714                         to_intel_encoder(connector_state->best_encoder);
11715                 if (!encoders_cloneable(encoder, source_encoder))
11716                         return false;
11717         }
11718
11719         return true;
11720 }
11721
11722 static bool check_encoder_cloning(struct drm_atomic_state *state,
11723                                   struct intel_crtc *crtc)
11724 {
11725         struct intel_encoder *encoder;
11726         struct drm_connector *connector;
11727         struct drm_connector_state *connector_state;
11728         int i;
11729
11730         for_each_connector_in_state(state, connector, connector_state, i) {
11731                 if (connector_state->crtc != &crtc->base)
11732                         continue;
11733
11734                 encoder = to_intel_encoder(connector_state->best_encoder);
11735                 if (!check_single_encoder_cloning(state, crtc, encoder))
11736                         return false;
11737         }
11738
11739         return true;
11740 }
11741
11742 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11743                                    struct drm_crtc_state *crtc_state)
11744 {
11745         struct drm_device *dev = crtc->dev;
11746         struct drm_i915_private *dev_priv = dev->dev_private;
11747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11748         struct intel_crtc_state *pipe_config =
11749                 to_intel_crtc_state(crtc_state);
11750         struct drm_atomic_state *state = crtc_state->state;
11751         int ret;
11752         bool mode_changed = needs_modeset(crtc_state);
11753
11754         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11755                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11756                 return -EINVAL;
11757         }
11758
11759         if (mode_changed && !crtc_state->active)
11760                 intel_crtc->atomic.update_wm_post = true;
11761
11762         if (mode_changed && crtc_state->enable &&
11763             dev_priv->display.crtc_compute_clock &&
11764             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11765                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11766                                                            pipe_config);
11767                 if (ret)
11768                         return ret;
11769         }
11770
11771         ret = 0;
11772         if (INTEL_INFO(dev)->gen >= 9) {
11773                 if (mode_changed)
11774                         ret = skl_update_scaler_crtc(pipe_config);
11775
11776                 if (!ret)
11777                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11778                                                          pipe_config);
11779         }
11780
11781         return ret;
11782 }
11783
11784 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11785         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11786         .load_lut = intel_crtc_load_lut,
11787         .atomic_begin = intel_begin_crtc_commit,
11788         .atomic_flush = intel_finish_crtc_commit,
11789         .atomic_check = intel_crtc_atomic_check,
11790 };
11791
11792 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11793 {
11794         struct intel_connector *connector;
11795
11796         for_each_intel_connector(dev, connector) {
11797                 if (connector->base.encoder) {
11798                         connector->base.state->best_encoder =
11799                                 connector->base.encoder;
11800                         connector->base.state->crtc =
11801                                 connector->base.encoder->crtc;
11802                 } else {
11803                         connector->base.state->best_encoder = NULL;
11804                         connector->base.state->crtc = NULL;
11805                 }
11806         }
11807 }
11808
11809 static void
11810 connected_sink_compute_bpp(struct intel_connector *connector,
11811                            struct intel_crtc_state *pipe_config)
11812 {
11813         int bpp = pipe_config->pipe_bpp;
11814
11815         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11816                 connector->base.base.id,
11817                 connector->base.name);
11818
11819         /* Don't use an invalid EDID bpc value */
11820         if (connector->base.display_info.bpc &&
11821             connector->base.display_info.bpc * 3 < bpp) {
11822                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11823                               bpp, connector->base.display_info.bpc*3);
11824                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11825         }
11826
11827         /* Clamp bpp to 8 on screens without EDID 1.4 */
11828         if (connector->base.display_info.bpc == 0 && bpp > 24) {
11829                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11830                               bpp);
11831                 pipe_config->pipe_bpp = 24;
11832         }
11833 }
11834
11835 static int
11836 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11837                           struct intel_crtc_state *pipe_config)
11838 {
11839         struct drm_device *dev = crtc->base.dev;
11840         struct drm_atomic_state *state;
11841         struct drm_connector *connector;
11842         struct drm_connector_state *connector_state;
11843         int bpp, i;
11844
11845         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11846                 bpp = 10*3;
11847         else if (INTEL_INFO(dev)->gen >= 5)
11848                 bpp = 12*3;
11849         else
11850                 bpp = 8*3;
11851
11852
11853         pipe_config->pipe_bpp = bpp;
11854
11855         state = pipe_config->base.state;
11856
11857         /* Clamp display bpp to EDID value */
11858         for_each_connector_in_state(state, connector, connector_state, i) {
11859                 if (connector_state->crtc != &crtc->base)
11860                         continue;
11861
11862                 connected_sink_compute_bpp(to_intel_connector(connector),
11863                                            pipe_config);
11864         }
11865
11866         return bpp;
11867 }
11868
11869 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11870 {
11871         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11872                         "type: 0x%x flags: 0x%x\n",
11873                 mode->crtc_clock,
11874                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11875                 mode->crtc_hsync_end, mode->crtc_htotal,
11876                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11877                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11878 }
11879
11880 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11881                                    struct intel_crtc_state *pipe_config,
11882                                    const char *context)
11883 {
11884         struct drm_device *dev = crtc->base.dev;
11885         struct drm_plane *plane;
11886         struct intel_plane *intel_plane;
11887         struct intel_plane_state *state;
11888         struct drm_framebuffer *fb;
11889
11890         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11891                       context, pipe_config, pipe_name(crtc->pipe));
11892
11893         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11894         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11895                       pipe_config->pipe_bpp, pipe_config->dither);
11896         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11897                       pipe_config->has_pch_encoder,
11898                       pipe_config->fdi_lanes,
11899                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11900                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11901                       pipe_config->fdi_m_n.tu);
11902         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11903                       pipe_config->has_dp_encoder,
11904                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11905                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11906                       pipe_config->dp_m_n.tu);
11907
11908         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11909                       pipe_config->has_dp_encoder,
11910                       pipe_config->dp_m2_n2.gmch_m,
11911                       pipe_config->dp_m2_n2.gmch_n,
11912                       pipe_config->dp_m2_n2.link_m,
11913                       pipe_config->dp_m2_n2.link_n,
11914                       pipe_config->dp_m2_n2.tu);
11915
11916         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11917                       pipe_config->has_audio,
11918                       pipe_config->has_infoframe);
11919
11920         DRM_DEBUG_KMS("requested mode:\n");
11921         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11922         DRM_DEBUG_KMS("adjusted mode:\n");
11923         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11924         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11925         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11926         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11927                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11928         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11929                       crtc->num_scalers,
11930                       pipe_config->scaler_state.scaler_users,
11931                       pipe_config->scaler_state.scaler_id);
11932         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11933                       pipe_config->gmch_pfit.control,
11934                       pipe_config->gmch_pfit.pgm_ratios,
11935                       pipe_config->gmch_pfit.lvds_border_bits);
11936         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11937                       pipe_config->pch_pfit.pos,
11938                       pipe_config->pch_pfit.size,
11939                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11940         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11941         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11942
11943         if (IS_BROXTON(dev)) {
11944                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11945                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11946                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11947                               pipe_config->ddi_pll_sel,
11948                               pipe_config->dpll_hw_state.ebb0,
11949                               pipe_config->dpll_hw_state.ebb4,
11950                               pipe_config->dpll_hw_state.pll0,
11951                               pipe_config->dpll_hw_state.pll1,
11952                               pipe_config->dpll_hw_state.pll2,
11953                               pipe_config->dpll_hw_state.pll3,
11954                               pipe_config->dpll_hw_state.pll6,
11955                               pipe_config->dpll_hw_state.pll8,
11956                               pipe_config->dpll_hw_state.pll9,
11957                               pipe_config->dpll_hw_state.pll10,
11958                               pipe_config->dpll_hw_state.pcsdw12);
11959         } else if (IS_SKYLAKE(dev)) {
11960                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11961                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11962                               pipe_config->ddi_pll_sel,
11963                               pipe_config->dpll_hw_state.ctrl1,
11964                               pipe_config->dpll_hw_state.cfgcr1,
11965                               pipe_config->dpll_hw_state.cfgcr2);
11966         } else if (HAS_DDI(dev)) {
11967                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11968                               pipe_config->ddi_pll_sel,
11969                               pipe_config->dpll_hw_state.wrpll);
11970         } else {
11971                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11972                               "fp0: 0x%x, fp1: 0x%x\n",
11973                               pipe_config->dpll_hw_state.dpll,
11974                               pipe_config->dpll_hw_state.dpll_md,
11975                               pipe_config->dpll_hw_state.fp0,
11976                               pipe_config->dpll_hw_state.fp1);
11977         }
11978
11979         DRM_DEBUG_KMS("planes on this crtc\n");
11980         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11981                 intel_plane = to_intel_plane(plane);
11982                 if (intel_plane->pipe != crtc->pipe)
11983                         continue;
11984
11985                 state = to_intel_plane_state(plane->state);
11986                 fb = state->base.fb;
11987                 if (!fb) {
11988                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11989                                 "disabled, scaler_id = %d\n",
11990                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11991                                 plane->base.id, intel_plane->pipe,
11992                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11993                                 drm_plane_index(plane), state->scaler_id);
11994                         continue;
11995                 }
11996
11997                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11998                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11999                         plane->base.id, intel_plane->pipe,
12000                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12001                         drm_plane_index(plane));
12002                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12003                         fb->base.id, fb->width, fb->height, fb->pixel_format);
12004                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12005                         state->scaler_id,
12006                         state->src.x1 >> 16, state->src.y1 >> 16,
12007                         drm_rect_width(&state->src) >> 16,
12008                         drm_rect_height(&state->src) >> 16,
12009                         state->dst.x1, state->dst.y1,
12010                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12011         }
12012 }
12013
12014 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12015 {
12016         struct drm_device *dev = state->dev;
12017         struct intel_encoder *encoder;
12018         struct drm_connector *connector;
12019         struct drm_connector_state *connector_state;
12020         unsigned int used_ports = 0;
12021         int i;
12022
12023         /*
12024          * Walk the connector list instead of the encoder
12025          * list to detect the problem on ddi platforms
12026          * where there's just one encoder per digital port.
12027          */
12028         for_each_connector_in_state(state, connector, connector_state, i) {
12029                 if (!connector_state->best_encoder)
12030                         continue;
12031
12032                 encoder = to_intel_encoder(connector_state->best_encoder);
12033
12034                 WARN_ON(!connector_state->crtc);
12035
12036                 switch (encoder->type) {
12037                         unsigned int port_mask;
12038                 case INTEL_OUTPUT_UNKNOWN:
12039                         if (WARN_ON(!HAS_DDI(dev)))
12040                                 break;
12041                 case INTEL_OUTPUT_DISPLAYPORT:
12042                 case INTEL_OUTPUT_HDMI:
12043                 case INTEL_OUTPUT_EDP:
12044                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12045
12046                         /* the same port mustn't appear more than once */
12047                         if (used_ports & port_mask)
12048                                 return false;
12049
12050                         used_ports |= port_mask;
12051                 default:
12052                         break;
12053                 }
12054         }
12055
12056         return true;
12057 }
12058
12059 static void
12060 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12061 {
12062         struct drm_crtc_state tmp_state;
12063         struct intel_crtc_scaler_state scaler_state;
12064         struct intel_dpll_hw_state dpll_hw_state;
12065         enum intel_dpll_id shared_dpll;
12066         uint32_t ddi_pll_sel;
12067         bool force_thru;
12068
12069         /* FIXME: before the switch to atomic started, a new pipe_config was
12070          * kzalloc'd. Code that depends on any field being zero should be
12071          * fixed, so that the crtc_state can be safely duplicated. For now,
12072          * only fields that are know to not cause problems are preserved. */
12073
12074         tmp_state = crtc_state->base;
12075         scaler_state = crtc_state->scaler_state;
12076         shared_dpll = crtc_state->shared_dpll;
12077         dpll_hw_state = crtc_state->dpll_hw_state;
12078         ddi_pll_sel = crtc_state->ddi_pll_sel;
12079         force_thru = crtc_state->pch_pfit.force_thru;
12080
12081         memset(crtc_state, 0, sizeof *crtc_state);
12082
12083         crtc_state->base = tmp_state;
12084         crtc_state->scaler_state = scaler_state;
12085         crtc_state->shared_dpll = shared_dpll;
12086         crtc_state->dpll_hw_state = dpll_hw_state;
12087         crtc_state->ddi_pll_sel = ddi_pll_sel;
12088         crtc_state->pch_pfit.force_thru = force_thru;
12089 }
12090
12091 static int
12092 intel_modeset_pipe_config(struct drm_crtc *crtc,
12093                           struct intel_crtc_state *pipe_config)
12094 {
12095         struct drm_atomic_state *state = pipe_config->base.state;
12096         struct intel_encoder *encoder;
12097         struct drm_connector *connector;
12098         struct drm_connector_state *connector_state;
12099         int base_bpp, ret = -EINVAL;
12100         int i;
12101         bool retry = true;
12102
12103         clear_intel_crtc_state(pipe_config);
12104
12105         pipe_config->cpu_transcoder =
12106                 (enum transcoder) to_intel_crtc(crtc)->pipe;
12107
12108         /*
12109          * Sanitize sync polarity flags based on requested ones. If neither
12110          * positive or negative polarity is requested, treat this as meaning
12111          * negative polarity.
12112          */
12113         if (!(pipe_config->base.adjusted_mode.flags &
12114               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12115                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12116
12117         if (!(pipe_config->base.adjusted_mode.flags &
12118               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12119                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12120
12121         /* Compute a starting value for pipe_config->pipe_bpp taking the source
12122          * plane pixel format and any sink constraints into account. Returns the
12123          * source plane bpp so that dithering can be selected on mismatches
12124          * after encoders and crtc also have had their say. */
12125         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12126                                              pipe_config);
12127         if (base_bpp < 0)
12128                 goto fail;
12129
12130         /*
12131          * Determine the real pipe dimensions. Note that stereo modes can
12132          * increase the actual pipe size due to the frame doubling and
12133          * insertion of additional space for blanks between the frame. This
12134          * is stored in the crtc timings. We use the requested mode to do this
12135          * computation to clearly distinguish it from the adjusted mode, which
12136          * can be changed by the connectors in the below retry loop.
12137          */
12138         drm_crtc_get_hv_timing(&pipe_config->base.mode,
12139                                &pipe_config->pipe_src_w,
12140                                &pipe_config->pipe_src_h);
12141
12142 encoder_retry:
12143         /* Ensure the port clock defaults are reset when retrying. */
12144         pipe_config->port_clock = 0;
12145         pipe_config->pixel_multiplier = 1;
12146
12147         /* Fill in default crtc timings, allow encoders to overwrite them. */
12148         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12149                               CRTC_STEREO_DOUBLE);
12150
12151         /* Pass our mode to the connectors and the CRTC to give them a chance to
12152          * adjust it according to limitations or connector properties, and also
12153          * a chance to reject the mode entirely.
12154          */
12155         for_each_connector_in_state(state, connector, connector_state, i) {
12156                 if (connector_state->crtc != crtc)
12157                         continue;
12158
12159                 encoder = to_intel_encoder(connector_state->best_encoder);
12160
12161                 if (!(encoder->compute_config(encoder, pipe_config))) {
12162                         DRM_DEBUG_KMS("Encoder config failure\n");
12163                         goto fail;
12164                 }
12165         }
12166
12167         /* Set default port clock if not overwritten by the encoder. Needs to be
12168          * done afterwards in case the encoder adjusts the mode. */
12169         if (!pipe_config->port_clock)
12170                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12171                         * pipe_config->pixel_multiplier;
12172
12173         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12174         if (ret < 0) {
12175                 DRM_DEBUG_KMS("CRTC fixup failed\n");
12176                 goto fail;
12177         }
12178
12179         if (ret == RETRY) {
12180                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12181                         ret = -EINVAL;
12182                         goto fail;
12183                 }
12184
12185                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12186                 retry = false;
12187                 goto encoder_retry;
12188         }
12189
12190         pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12191         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12192                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12193
12194 fail:
12195         return ret;
12196 }
12197
12198 static void
12199 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12200 {
12201         struct drm_crtc *crtc;
12202         struct drm_crtc_state *crtc_state;
12203         int i;
12204
12205         /* Double check state. */
12206         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12207                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12208
12209                 /* Update hwmode for vblank functions */
12210                 if (crtc->state->active)
12211                         crtc->hwmode = crtc->state->adjusted_mode;
12212                 else
12213                         crtc->hwmode.crtc_clock = 0;
12214         }
12215 }
12216
12217 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12218 {
12219         int diff;
12220
12221         if (clock1 == clock2)
12222                 return true;
12223
12224         if (!clock1 || !clock2)
12225                 return false;
12226
12227         diff = abs(clock1 - clock2);
12228
12229         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12230                 return true;
12231
12232         return false;
12233 }
12234
12235 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12236         list_for_each_entry((intel_crtc), \
12237                             &(dev)->mode_config.crtc_list, \
12238                             base.head) \
12239                 if (mask & (1 <<(intel_crtc)->pipe))
12240
12241
12242 static bool
12243 intel_compare_m_n(unsigned int m, unsigned int n,
12244                   unsigned int m2, unsigned int n2,
12245                   bool exact)
12246 {
12247         if (m == m2 && n == n2)
12248                 return true;
12249
12250         if (exact || !m || !n || !m2 || !n2)
12251                 return false;
12252
12253         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12254
12255         if (m > m2) {
12256                 while (m > m2) {
12257                         m2 <<= 1;
12258                         n2 <<= 1;
12259                 }
12260         } else if (m < m2) {
12261                 while (m < m2) {
12262                         m <<= 1;
12263                         n <<= 1;
12264                 }
12265         }
12266
12267         return m == m2 && n == n2;
12268 }
12269
12270 static bool
12271 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12272                        struct intel_link_m_n *m2_n2,
12273                        bool adjust)
12274 {
12275         if (m_n->tu == m2_n2->tu &&
12276             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12277                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12278             intel_compare_m_n(m_n->link_m, m_n->link_n,
12279                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
12280                 if (adjust)
12281                         *m2_n2 = *m_n;
12282
12283                 return true;
12284         }
12285
12286         return false;
12287 }
12288
12289 static bool
12290 intel_pipe_config_compare(struct drm_device *dev,
12291                           struct intel_crtc_state *current_config,
12292                           struct intel_crtc_state *pipe_config,
12293                           bool adjust)
12294 {
12295         bool ret = true;
12296
12297 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12298         do { \
12299                 if (!adjust) \
12300                         DRM_ERROR(fmt, ##__VA_ARGS__); \
12301                 else \
12302                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12303         } while (0)
12304
12305 #define PIPE_CONF_CHECK_X(name) \
12306         if (current_config->name != pipe_config->name) { \
12307                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12308                           "(expected 0x%08x, found 0x%08x)\n", \
12309                           current_config->name, \
12310                           pipe_config->name); \
12311                 ret = false; \
12312         }
12313
12314 #define PIPE_CONF_CHECK_I(name) \
12315         if (current_config->name != pipe_config->name) { \
12316                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12317                           "(expected %i, found %i)\n", \
12318                           current_config->name, \
12319                           pipe_config->name); \
12320                 ret = false; \
12321         }
12322
12323 #define PIPE_CONF_CHECK_M_N(name) \
12324         if (!intel_compare_link_m_n(&current_config->name, \
12325                                     &pipe_config->name,\
12326                                     adjust)) { \
12327                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12328                           "(expected tu %i gmch %i/%i link %i/%i, " \
12329                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12330                           current_config->name.tu, \
12331                           current_config->name.gmch_m, \
12332                           current_config->name.gmch_n, \
12333                           current_config->name.link_m, \
12334                           current_config->name.link_n, \
12335                           pipe_config->name.tu, \
12336                           pipe_config->name.gmch_m, \
12337                           pipe_config->name.gmch_n, \
12338                           pipe_config->name.link_m, \
12339                           pipe_config->name.link_n); \
12340                 ret = false; \
12341         }
12342
12343 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12344         if (!intel_compare_link_m_n(&current_config->name, \
12345                                     &pipe_config->name, adjust) && \
12346             !intel_compare_link_m_n(&current_config->alt_name, \
12347                                     &pipe_config->name, adjust)) { \
12348                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12349                           "(expected tu %i gmch %i/%i link %i/%i, " \
12350                           "or tu %i gmch %i/%i link %i/%i, " \
12351                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12352                           current_config->name.tu, \
12353                           current_config->name.gmch_m, \
12354                           current_config->name.gmch_n, \
12355                           current_config->name.link_m, \
12356                           current_config->name.link_n, \
12357                           current_config->alt_name.tu, \
12358                           current_config->alt_name.gmch_m, \
12359                           current_config->alt_name.gmch_n, \
12360                           current_config->alt_name.link_m, \
12361                           current_config->alt_name.link_n, \
12362                           pipe_config->name.tu, \
12363                           pipe_config->name.gmch_m, \
12364                           pipe_config->name.gmch_n, \
12365                           pipe_config->name.link_m, \
12366                           pipe_config->name.link_n); \
12367                 ret = false; \
12368         }
12369
12370 /* This is required for BDW+ where there is only one set of registers for
12371  * switching between high and low RR.
12372  * This macro can be used whenever a comparison has to be made between one
12373  * hw state and multiple sw state variables.
12374  */
12375 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12376         if ((current_config->name != pipe_config->name) && \
12377                 (current_config->alt_name != pipe_config->name)) { \
12378                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12379                                   "(expected %i or %i, found %i)\n", \
12380                                   current_config->name, \
12381                                   current_config->alt_name, \
12382                                   pipe_config->name); \
12383                         ret = false; \
12384         }
12385
12386 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12387         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12388                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12389                           "(expected %i, found %i)\n", \
12390                           current_config->name & (mask), \
12391                           pipe_config->name & (mask)); \
12392                 ret = false; \
12393         }
12394
12395 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12396         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12397                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12398                           "(expected %i, found %i)\n", \
12399                           current_config->name, \
12400                           pipe_config->name); \
12401                 ret = false; \
12402         }
12403
12404 #define PIPE_CONF_QUIRK(quirk)  \
12405         ((current_config->quirks | pipe_config->quirks) & (quirk))
12406
12407         PIPE_CONF_CHECK_I(cpu_transcoder);
12408
12409         PIPE_CONF_CHECK_I(has_pch_encoder);
12410         PIPE_CONF_CHECK_I(fdi_lanes);
12411         PIPE_CONF_CHECK_M_N(fdi_m_n);
12412
12413         PIPE_CONF_CHECK_I(has_dp_encoder);
12414
12415         if (INTEL_INFO(dev)->gen < 8) {
12416                 PIPE_CONF_CHECK_M_N(dp_m_n);
12417
12418                 PIPE_CONF_CHECK_I(has_drrs);
12419                 if (current_config->has_drrs)
12420                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12421         } else
12422                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12423
12424         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12425         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12426         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12427         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12428         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12429         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12430
12431         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12432         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12433         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12434         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12435         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12436         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12437
12438         PIPE_CONF_CHECK_I(pixel_multiplier);
12439         PIPE_CONF_CHECK_I(has_hdmi_sink);
12440         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12441             IS_VALLEYVIEW(dev))
12442                 PIPE_CONF_CHECK_I(limited_color_range);
12443         PIPE_CONF_CHECK_I(has_infoframe);
12444
12445         PIPE_CONF_CHECK_I(has_audio);
12446
12447         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12448                               DRM_MODE_FLAG_INTERLACE);
12449
12450         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12451                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12452                                       DRM_MODE_FLAG_PHSYNC);
12453                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12454                                       DRM_MODE_FLAG_NHSYNC);
12455                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12456                                       DRM_MODE_FLAG_PVSYNC);
12457                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12458                                       DRM_MODE_FLAG_NVSYNC);
12459         }
12460
12461         PIPE_CONF_CHECK_I(pipe_src_w);
12462         PIPE_CONF_CHECK_I(pipe_src_h);
12463
12464         PIPE_CONF_CHECK_I(gmch_pfit.control);
12465         /* pfit ratios are autocomputed by the hw on gen4+ */
12466         if (INTEL_INFO(dev)->gen < 4)
12467                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12468         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12469
12470         PIPE_CONF_CHECK_I(pch_pfit.enabled);
12471         if (current_config->pch_pfit.enabled) {
12472                 PIPE_CONF_CHECK_I(pch_pfit.pos);
12473                 PIPE_CONF_CHECK_I(pch_pfit.size);
12474         }
12475
12476         PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12477
12478         /* BDW+ don't expose a synchronous way to read the state */
12479         if (IS_HASWELL(dev))
12480                 PIPE_CONF_CHECK_I(ips_enabled);
12481
12482         PIPE_CONF_CHECK_I(double_wide);
12483
12484         PIPE_CONF_CHECK_X(ddi_pll_sel);
12485
12486         PIPE_CONF_CHECK_I(shared_dpll);
12487         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12488         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12489         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12490         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12491         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12492         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12493         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12494         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12495
12496         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12497                 PIPE_CONF_CHECK_I(pipe_bpp);
12498
12499         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12500         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12501
12502 #undef PIPE_CONF_CHECK_X
12503 #undef PIPE_CONF_CHECK_I
12504 #undef PIPE_CONF_CHECK_I_ALT
12505 #undef PIPE_CONF_CHECK_FLAGS
12506 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12507 #undef PIPE_CONF_QUIRK
12508 #undef INTEL_ERR_OR_DBG_KMS
12509
12510         return ret;
12511 }
12512
12513 static void check_wm_state(struct drm_device *dev)
12514 {
12515         struct drm_i915_private *dev_priv = dev->dev_private;
12516         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12517         struct intel_crtc *intel_crtc;
12518         int plane;
12519
12520         if (INTEL_INFO(dev)->gen < 9)
12521                 return;
12522
12523         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12524         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12525
12526         for_each_intel_crtc(dev, intel_crtc) {
12527                 struct skl_ddb_entry *hw_entry, *sw_entry;
12528                 const enum pipe pipe = intel_crtc->pipe;
12529
12530                 if (!intel_crtc->active)
12531                         continue;
12532
12533                 /* planes */
12534                 for_each_plane(dev_priv, pipe, plane) {
12535                         hw_entry = &hw_ddb.plane[pipe][plane];
12536                         sw_entry = &sw_ddb->plane[pipe][plane];
12537
12538                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
12539                                 continue;
12540
12541                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12542                                   "(expected (%u,%u), found (%u,%u))\n",
12543                                   pipe_name(pipe), plane + 1,
12544                                   sw_entry->start, sw_entry->end,
12545                                   hw_entry->start, hw_entry->end);
12546                 }
12547
12548                 /* cursor */
12549                 hw_entry = &hw_ddb.cursor[pipe];
12550                 sw_entry = &sw_ddb->cursor[pipe];
12551
12552                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12553                         continue;
12554
12555                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12556                           "(expected (%u,%u), found (%u,%u))\n",
12557                           pipe_name(pipe),
12558                           sw_entry->start, sw_entry->end,
12559                           hw_entry->start, hw_entry->end);
12560         }
12561 }
12562
12563 static void
12564 check_connector_state(struct drm_device *dev,
12565                       struct drm_atomic_state *old_state)
12566 {
12567         struct drm_connector_state *old_conn_state;
12568         struct drm_connector *connector;
12569         int i;
12570
12571         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12572                 struct drm_encoder *encoder = connector->encoder;
12573                 struct drm_connector_state *state = connector->state;
12574
12575                 /* This also checks the encoder/connector hw state with the
12576                  * ->get_hw_state callbacks. */
12577                 intel_connector_check_state(to_intel_connector(connector));
12578
12579                 I915_STATE_WARN(state->best_encoder != encoder,
12580                      "connector's atomic encoder doesn't match legacy encoder\n");
12581         }
12582 }
12583
12584 static void
12585 check_encoder_state(struct drm_device *dev)
12586 {
12587         struct intel_encoder *encoder;
12588         struct intel_connector *connector;
12589
12590         for_each_intel_encoder(dev, encoder) {
12591                 bool enabled = false;
12592                 enum pipe pipe;
12593
12594                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12595                               encoder->base.base.id,
12596                               encoder->base.name);
12597
12598                 for_each_intel_connector(dev, connector) {
12599                         if (connector->base.state->best_encoder != &encoder->base)
12600                                 continue;
12601                         enabled = true;
12602
12603                         I915_STATE_WARN(connector->base.state->crtc !=
12604                                         encoder->base.crtc,
12605                              "connector's crtc doesn't match encoder crtc\n");
12606                 }
12607
12608                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12609                      "encoder's enabled state mismatch "
12610                      "(expected %i, found %i)\n",
12611                      !!encoder->base.crtc, enabled);
12612
12613                 if (!encoder->base.crtc) {
12614                         bool active;
12615
12616                         active = encoder->get_hw_state(encoder, &pipe);
12617                         I915_STATE_WARN(active,
12618                              "encoder detached but still enabled on pipe %c.\n",
12619                              pipe_name(pipe));
12620                 }
12621         }
12622 }
12623
12624 static void
12625 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12626 {
12627         struct drm_i915_private *dev_priv = dev->dev_private;
12628         struct intel_encoder *encoder;
12629         struct drm_crtc_state *old_crtc_state;
12630         struct drm_crtc *crtc;
12631         int i;
12632
12633         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12634                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12635                 struct intel_crtc_state *pipe_config, *sw_config;
12636                 bool active;
12637
12638                 if (!needs_modeset(crtc->state))
12639                         continue;
12640
12641                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12642                 pipe_config = to_intel_crtc_state(old_crtc_state);
12643                 memset(pipe_config, 0, sizeof(*pipe_config));
12644                 pipe_config->base.crtc = crtc;
12645                 pipe_config->base.state = old_state;
12646
12647                 DRM_DEBUG_KMS("[CRTC:%d]\n",
12648                               crtc->base.id);
12649
12650                 active = dev_priv->display.get_pipe_config(intel_crtc,
12651                                                            pipe_config);
12652
12653                 /* hw state is inconsistent with the pipe quirk */
12654                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12655                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12656                         active = crtc->state->active;
12657
12658                 I915_STATE_WARN(crtc->state->active != active,
12659                      "crtc active state doesn't match with hw state "
12660                      "(expected %i, found %i)\n", crtc->state->active, active);
12661
12662                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12663                      "transitional active state does not match atomic hw state "
12664                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12665
12666                 for_each_encoder_on_crtc(dev, crtc, encoder) {
12667                         enum pipe pipe;
12668
12669                         active = encoder->get_hw_state(encoder, &pipe);
12670                         I915_STATE_WARN(active != crtc->state->active,
12671                                 "[ENCODER:%i] active %i with crtc active %i\n",
12672                                 encoder->base.base.id, active, crtc->state->active);
12673
12674                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12675                                         "Encoder connected to wrong pipe %c\n",
12676                                         pipe_name(pipe));
12677
12678                         if (active)
12679                                 encoder->get_config(encoder, pipe_config);
12680                 }
12681
12682                 if (!crtc->state->active)
12683                         continue;
12684
12685                 sw_config = to_intel_crtc_state(crtc->state);
12686                 if (!intel_pipe_config_compare(dev, sw_config,
12687                                                pipe_config, false)) {
12688                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
12689                         intel_dump_pipe_config(intel_crtc, pipe_config,
12690                                                "[hw state]");
12691                         intel_dump_pipe_config(intel_crtc, sw_config,
12692                                                "[sw state]");
12693                 }
12694         }
12695 }
12696
12697 static void
12698 check_shared_dpll_state(struct drm_device *dev)
12699 {
12700         struct drm_i915_private *dev_priv = dev->dev_private;
12701         struct intel_crtc *crtc;
12702         struct intel_dpll_hw_state dpll_hw_state;
12703         int i;
12704
12705         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12706                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12707                 int enabled_crtcs = 0, active_crtcs = 0;
12708                 bool active;
12709
12710                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12711
12712                 DRM_DEBUG_KMS("%s\n", pll->name);
12713
12714                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12715
12716                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12717                      "more active pll users than references: %i vs %i\n",
12718                      pll->active, hweight32(pll->config.crtc_mask));
12719                 I915_STATE_WARN(pll->active && !pll->on,
12720                      "pll in active use but not on in sw tracking\n");
12721                 I915_STATE_WARN(pll->on && !pll->active,
12722                      "pll in on but not on in use in sw tracking\n");
12723                 I915_STATE_WARN(pll->on != active,
12724                      "pll on state mismatch (expected %i, found %i)\n",
12725                      pll->on, active);
12726
12727                 for_each_intel_crtc(dev, crtc) {
12728                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12729                                 enabled_crtcs++;
12730                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12731                                 active_crtcs++;
12732                 }
12733                 I915_STATE_WARN(pll->active != active_crtcs,
12734                      "pll active crtcs mismatch (expected %i, found %i)\n",
12735                      pll->active, active_crtcs);
12736                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12737                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
12738                      hweight32(pll->config.crtc_mask), enabled_crtcs);
12739
12740                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12741                                        sizeof(dpll_hw_state)),
12742                      "pll hw state mismatch\n");
12743         }
12744 }
12745
12746 static void
12747 intel_modeset_check_state(struct drm_device *dev,
12748                           struct drm_atomic_state *old_state)
12749 {
12750         check_wm_state(dev);
12751         check_connector_state(dev, old_state);
12752         check_encoder_state(dev);
12753         check_crtc_state(dev, old_state);
12754         check_shared_dpll_state(dev);
12755 }
12756
12757 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12758                                      int dotclock)
12759 {
12760         /*
12761          * FDI already provided one idea for the dotclock.
12762          * Yell if the encoder disagrees.
12763          */
12764         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12765              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12766              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12767 }
12768
12769 static void update_scanline_offset(struct intel_crtc *crtc)
12770 {
12771         struct drm_device *dev = crtc->base.dev;
12772
12773         /*
12774          * The scanline counter increments at the leading edge of hsync.
12775          *
12776          * On most platforms it starts counting from vtotal-1 on the
12777          * first active line. That means the scanline counter value is
12778          * always one less than what we would expect. Ie. just after
12779          * start of vblank, which also occurs at start of hsync (on the
12780          * last active line), the scanline counter will read vblank_start-1.
12781          *
12782          * On gen2 the scanline counter starts counting from 1 instead
12783          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12784          * to keep the value positive), instead of adding one.
12785          *
12786          * On HSW+ the behaviour of the scanline counter depends on the output
12787          * type. For DP ports it behaves like most other platforms, but on HDMI
12788          * there's an extra 1 line difference. So we need to add two instead of
12789          * one to the value.
12790          */
12791         if (IS_GEN2(dev)) {
12792                 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12793                 int vtotal;
12794
12795                 vtotal = mode->crtc_vtotal;
12796                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12797                         vtotal /= 2;
12798
12799                 crtc->scanline_offset = vtotal - 1;
12800         } else if (HAS_DDI(dev) &&
12801                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12802                 crtc->scanline_offset = 2;
12803         } else
12804                 crtc->scanline_offset = 1;
12805 }
12806
12807 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12808 {
12809         struct drm_device *dev = state->dev;
12810         struct drm_i915_private *dev_priv = to_i915(dev);
12811         struct intel_shared_dpll_config *shared_dpll = NULL;
12812         struct intel_crtc *intel_crtc;
12813         struct intel_crtc_state *intel_crtc_state;
12814         struct drm_crtc *crtc;
12815         struct drm_crtc_state *crtc_state;
12816         int i;
12817
12818         if (!dev_priv->display.crtc_compute_clock)
12819                 return;
12820
12821         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12822                 int dpll;
12823
12824                 intel_crtc = to_intel_crtc(crtc);
12825                 intel_crtc_state = to_intel_crtc_state(crtc_state);
12826                 dpll = intel_crtc_state->shared_dpll;
12827
12828                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12829                         continue;
12830
12831                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12832
12833                 if (!shared_dpll)
12834                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12835
12836                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12837         }
12838 }
12839
12840 /*
12841  * This implements the workaround described in the "notes" section of the mode
12842  * set sequence documentation. When going from no pipes or single pipe to
12843  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12844  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12845  */
12846 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12847 {
12848         struct drm_crtc_state *crtc_state;
12849         struct intel_crtc *intel_crtc;
12850         struct drm_crtc *crtc;
12851         struct intel_crtc_state *first_crtc_state = NULL;
12852         struct intel_crtc_state *other_crtc_state = NULL;
12853         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12854         int i;
12855
12856         /* look at all crtc's that are going to be enabled in during modeset */
12857         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12858                 intel_crtc = to_intel_crtc(crtc);
12859
12860                 if (!crtc_state->active || !needs_modeset(crtc_state))
12861                         continue;
12862
12863                 if (first_crtc_state) {
12864                         other_crtc_state = to_intel_crtc_state(crtc_state);
12865                         break;
12866                 } else {
12867                         first_crtc_state = to_intel_crtc_state(crtc_state);
12868                         first_pipe = intel_crtc->pipe;
12869                 }
12870         }
12871
12872         /* No workaround needed? */
12873         if (!first_crtc_state)
12874                 return 0;
12875
12876         /* w/a possibly needed, check how many crtc's are already enabled. */
12877         for_each_intel_crtc(state->dev, intel_crtc) {
12878                 struct intel_crtc_state *pipe_config;
12879
12880                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12881                 if (IS_ERR(pipe_config))
12882                         return PTR_ERR(pipe_config);
12883
12884                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12885
12886                 if (!pipe_config->base.active ||
12887                     needs_modeset(&pipe_config->base))
12888                         continue;
12889
12890                 /* 2 or more enabled crtcs means no need for w/a */
12891                 if (enabled_pipe != INVALID_PIPE)
12892                         return 0;
12893
12894                 enabled_pipe = intel_crtc->pipe;
12895         }
12896
12897         if (enabled_pipe != INVALID_PIPE)
12898                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12899         else if (other_crtc_state)
12900                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12901
12902         return 0;
12903 }
12904
12905 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12906 {
12907         struct drm_crtc *crtc;
12908         struct drm_crtc_state *crtc_state;
12909         int ret = 0;
12910
12911         /* add all active pipes to the state */
12912         for_each_crtc(state->dev, crtc) {
12913                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12914                 if (IS_ERR(crtc_state))
12915                         return PTR_ERR(crtc_state);
12916
12917                 if (!crtc_state->active || needs_modeset(crtc_state))
12918                         continue;
12919
12920                 crtc_state->mode_changed = true;
12921
12922                 ret = drm_atomic_add_affected_connectors(state, crtc);
12923                 if (ret)
12924                         break;
12925
12926                 ret = drm_atomic_add_affected_planes(state, crtc);
12927                 if (ret)
12928                         break;
12929         }
12930
12931         return ret;
12932 }
12933
12934
12935 static int intel_modeset_checks(struct drm_atomic_state *state)
12936 {
12937         struct drm_device *dev = state->dev;
12938         struct drm_i915_private *dev_priv = dev->dev_private;
12939         int ret;
12940
12941         if (!check_digital_port_conflicts(state)) {
12942                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12943                 return -EINVAL;
12944         }
12945
12946         /*
12947          * See if the config requires any additional preparation, e.g.
12948          * to adjust global state with pipes off.  We need to do this
12949          * here so we can get the modeset_pipe updated config for the new
12950          * mode set on this crtc.  For other crtcs we need to use the
12951          * adjusted_mode bits in the crtc directly.
12952          */
12953         if (dev_priv->display.modeset_calc_cdclk) {
12954                 unsigned int cdclk;
12955
12956                 ret = dev_priv->display.modeset_calc_cdclk(state);
12957
12958                 cdclk = to_intel_atomic_state(state)->cdclk;
12959                 if (!ret && cdclk != dev_priv->cdclk_freq)
12960                         ret = intel_modeset_all_pipes(state);
12961
12962                 if (ret < 0)
12963                         return ret;
12964         } else
12965                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12966
12967         intel_modeset_clear_plls(state);
12968
12969         if (IS_HASWELL(dev))
12970                 return haswell_mode_set_planes_workaround(state);
12971
12972         return 0;
12973 }
12974
12975 /**
12976  * intel_atomic_check - validate state object
12977  * @dev: drm device
12978  * @state: state to validate
12979  */
12980 static int intel_atomic_check(struct drm_device *dev,
12981                               struct drm_atomic_state *state)
12982 {
12983         struct drm_crtc *crtc;
12984         struct drm_crtc_state *crtc_state;
12985         int ret, i;
12986         bool any_ms = false;
12987
12988         ret = drm_atomic_helper_check_modeset(dev, state);
12989         if (ret)
12990                 return ret;
12991
12992         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12993                 struct intel_crtc_state *pipe_config =
12994                         to_intel_crtc_state(crtc_state);
12995
12996                 /* Catch I915_MODE_FLAG_INHERITED */
12997                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12998                         crtc_state->mode_changed = true;
12999
13000                 if (!crtc_state->enable) {
13001                         if (needs_modeset(crtc_state))
13002                                 any_ms = true;
13003                         continue;
13004                 }
13005
13006                 if (!needs_modeset(crtc_state))
13007                         continue;
13008
13009                 /* FIXME: For only active_changed we shouldn't need to do any
13010                  * state recomputation at all. */
13011
13012                 ret = drm_atomic_add_affected_connectors(state, crtc);
13013                 if (ret)
13014                         return ret;
13015
13016                 ret = intel_modeset_pipe_config(crtc, pipe_config);
13017                 if (ret)
13018                         return ret;
13019
13020                 if (i915.fastboot &&
13021                     intel_pipe_config_compare(state->dev,
13022                                         to_intel_crtc_state(crtc->state),
13023                                         pipe_config, true)) {
13024                         crtc_state->mode_changed = false;
13025                 }
13026
13027                 if (needs_modeset(crtc_state)) {
13028                         any_ms = true;
13029
13030                         ret = drm_atomic_add_affected_planes(state, crtc);
13031                         if (ret)
13032                                 return ret;
13033                 }
13034
13035                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13036                                        needs_modeset(crtc_state) ?
13037                                        "[modeset]" : "[fastset]");
13038         }
13039
13040         if (any_ms) {
13041                 ret = intel_modeset_checks(state);
13042
13043                 if (ret)
13044                         return ret;
13045         } else
13046                 to_intel_atomic_state(state)->cdclk =
13047                         to_i915(state->dev)->cdclk_freq;
13048
13049         return drm_atomic_helper_check_planes(state->dev, state);
13050 }
13051
13052 /**
13053  * intel_atomic_commit - commit validated state object
13054  * @dev: DRM device
13055  * @state: the top-level driver state object
13056  * @async: asynchronous commit
13057  *
13058  * This function commits a top-level state object that has been validated
13059  * with drm_atomic_helper_check().
13060  *
13061  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13062  * we can only handle plane-related operations and do not yet support
13063  * asynchronous commit.
13064  *
13065  * RETURNS
13066  * Zero for success or -errno.
13067  */
13068 static int intel_atomic_commit(struct drm_device *dev,
13069                                struct drm_atomic_state *state,
13070                                bool async)
13071 {
13072         struct drm_i915_private *dev_priv = dev->dev_private;
13073         struct drm_crtc *crtc;
13074         struct drm_crtc_state *crtc_state;
13075         int ret = 0;
13076         int i;
13077         bool any_ms = false;
13078
13079         if (async) {
13080                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13081                 return -EINVAL;
13082         }
13083
13084         ret = drm_atomic_helper_prepare_planes(dev, state);
13085         if (ret)
13086                 return ret;
13087
13088         drm_atomic_helper_swap_state(dev, state);
13089
13090         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13091                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13092
13093                 if (!needs_modeset(crtc->state))
13094                         continue;
13095
13096                 any_ms = true;
13097                 intel_pre_plane_update(intel_crtc);
13098
13099                 if (crtc_state->active) {
13100                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13101                         dev_priv->display.crtc_disable(crtc);
13102                         intel_crtc->active = false;
13103                         intel_disable_shared_dpll(intel_crtc);
13104                 }
13105         }
13106
13107         /* Only after disabling all output pipelines that will be changed can we
13108          * update the the output configuration. */
13109         intel_modeset_update_crtc_state(state);
13110
13111         if (any_ms) {
13112                 intel_shared_dpll_commit(state);
13113
13114                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13115                 modeset_update_crtc_power_domains(state);
13116         }
13117
13118         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13119         for_each_crtc_in_state(state, crtc, crtc_state, i) {
13120                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13121                 bool modeset = needs_modeset(crtc->state);
13122
13123                 if (modeset && crtc->state->active) {
13124                         update_scanline_offset(to_intel_crtc(crtc));
13125                         dev_priv->display.crtc_enable(crtc);
13126                 }
13127
13128                 if (!modeset)
13129                         intel_pre_plane_update(intel_crtc);
13130
13131                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13132                 intel_post_plane_update(intel_crtc);
13133         }
13134
13135         /* FIXME: add subpixel order */
13136
13137         drm_atomic_helper_wait_for_vblanks(dev, state);
13138         drm_atomic_helper_cleanup_planes(dev, state);
13139
13140         if (any_ms)
13141                 intel_modeset_check_state(dev, state);
13142
13143         drm_atomic_state_free(state);
13144
13145         return 0;
13146 }
13147
13148 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13149 {
13150         struct drm_device *dev = crtc->dev;
13151         struct drm_atomic_state *state;
13152         struct drm_crtc_state *crtc_state;
13153         int ret;
13154
13155         state = drm_atomic_state_alloc(dev);
13156         if (!state) {
13157                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13158                               crtc->base.id);
13159                 return;
13160         }
13161
13162         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13163
13164 retry:
13165         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13166         ret = PTR_ERR_OR_ZERO(crtc_state);
13167         if (!ret) {
13168                 if (!crtc_state->active)
13169                         goto out;
13170
13171                 crtc_state->mode_changed = true;
13172                 ret = drm_atomic_commit(state);
13173         }
13174
13175         if (ret == -EDEADLK) {
13176                 drm_atomic_state_clear(state);
13177                 drm_modeset_backoff(state->acquire_ctx);
13178                 goto retry;
13179         }
13180
13181         if (ret)
13182 out:
13183                 drm_atomic_state_free(state);
13184 }
13185
13186 #undef for_each_intel_crtc_masked
13187
13188 static const struct drm_crtc_funcs intel_crtc_funcs = {
13189         .gamma_set = intel_crtc_gamma_set,
13190         .set_config = drm_atomic_helper_set_config,
13191         .destroy = intel_crtc_destroy,
13192         .page_flip = intel_crtc_page_flip,
13193         .atomic_duplicate_state = intel_crtc_duplicate_state,
13194         .atomic_destroy_state = intel_crtc_destroy_state,
13195 };
13196
13197 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13198                                       struct intel_shared_dpll *pll,
13199                                       struct intel_dpll_hw_state *hw_state)
13200 {
13201         uint32_t val;
13202
13203         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13204                 return false;
13205
13206         val = I915_READ(PCH_DPLL(pll->id));
13207         hw_state->dpll = val;
13208         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13209         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13210
13211         return val & DPLL_VCO_ENABLE;
13212 }
13213
13214 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13215                                   struct intel_shared_dpll *pll)
13216 {
13217         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13218         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13219 }
13220
13221 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13222                                 struct intel_shared_dpll *pll)
13223 {
13224         /* PCH refclock must be enabled first */
13225         ibx_assert_pch_refclk_enabled(dev_priv);
13226
13227         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13228
13229         /* Wait for the clocks to stabilize. */
13230         POSTING_READ(PCH_DPLL(pll->id));
13231         udelay(150);
13232
13233         /* The pixel multiplier can only be updated once the
13234          * DPLL is enabled and the clocks are stable.
13235          *
13236          * So write it again.
13237          */
13238         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13239         POSTING_READ(PCH_DPLL(pll->id));
13240         udelay(200);
13241 }
13242
13243 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13244                                  struct intel_shared_dpll *pll)
13245 {
13246         struct drm_device *dev = dev_priv->dev;
13247         struct intel_crtc *crtc;
13248
13249         /* Make sure no transcoder isn't still depending on us. */
13250         for_each_intel_crtc(dev, crtc) {
13251                 if (intel_crtc_to_shared_dpll(crtc) == pll)
13252                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13253         }
13254
13255         I915_WRITE(PCH_DPLL(pll->id), 0);
13256         POSTING_READ(PCH_DPLL(pll->id));
13257         udelay(200);
13258 }
13259
13260 static char *ibx_pch_dpll_names[] = {
13261         "PCH DPLL A",
13262         "PCH DPLL B",
13263 };
13264
13265 static void ibx_pch_dpll_init(struct drm_device *dev)
13266 {
13267         struct drm_i915_private *dev_priv = dev->dev_private;
13268         int i;
13269
13270         dev_priv->num_shared_dpll = 2;
13271
13272         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13273                 dev_priv->shared_dplls[i].id = i;
13274                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13275                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13276                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13277                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13278                 dev_priv->shared_dplls[i].get_hw_state =
13279                         ibx_pch_dpll_get_hw_state;
13280         }
13281 }
13282
13283 static void intel_shared_dpll_init(struct drm_device *dev)
13284 {
13285         struct drm_i915_private *dev_priv = dev->dev_private;
13286
13287         intel_update_cdclk(dev);
13288
13289         if (HAS_DDI(dev))
13290                 intel_ddi_pll_init(dev);
13291         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13292                 ibx_pch_dpll_init(dev);
13293         else
13294                 dev_priv->num_shared_dpll = 0;
13295
13296         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13297 }
13298
13299 /**
13300  * intel_prepare_plane_fb - Prepare fb for usage on plane
13301  * @plane: drm plane to prepare for
13302  * @fb: framebuffer to prepare for presentation
13303  *
13304  * Prepares a framebuffer for usage on a display plane.  Generally this
13305  * involves pinning the underlying object and updating the frontbuffer tracking
13306  * bits.  Some older platforms need special physical address handling for
13307  * cursor planes.
13308  *
13309  * Returns 0 on success, negative error code on failure.
13310  */
13311 int
13312 intel_prepare_plane_fb(struct drm_plane *plane,
13313                        struct drm_framebuffer *fb,
13314                        const struct drm_plane_state *new_state)
13315 {
13316         struct drm_device *dev = plane->dev;
13317         struct intel_plane *intel_plane = to_intel_plane(plane);
13318         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13319         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13320         int ret = 0;
13321
13322         if (!obj)
13323                 return 0;
13324
13325         mutex_lock(&dev->struct_mutex);
13326
13327         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13328             INTEL_INFO(dev)->cursor_needs_physical) {
13329                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13330                 ret = i915_gem_object_attach_phys(obj, align);
13331                 if (ret)
13332                         DRM_DEBUG_KMS("failed to attach phys object\n");
13333         } else {
13334                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13335         }
13336
13337         if (ret == 0)
13338                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13339
13340         mutex_unlock(&dev->struct_mutex);
13341
13342         return ret;
13343 }
13344
13345 /**
13346  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13347  * @plane: drm plane to clean up for
13348  * @fb: old framebuffer that was on plane
13349  *
13350  * Cleans up a framebuffer that has just been removed from a plane.
13351  */
13352 void
13353 intel_cleanup_plane_fb(struct drm_plane *plane,
13354                        struct drm_framebuffer *fb,
13355                        const struct drm_plane_state *old_state)
13356 {
13357         struct drm_device *dev = plane->dev;
13358         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13359
13360         if (WARN_ON(!obj))
13361                 return;
13362
13363         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13364             !INTEL_INFO(dev)->cursor_needs_physical) {
13365                 mutex_lock(&dev->struct_mutex);
13366                 intel_unpin_fb_obj(fb, old_state);
13367                 mutex_unlock(&dev->struct_mutex);
13368         }
13369 }
13370
13371 int
13372 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13373 {
13374         int max_scale;
13375         struct drm_device *dev;
13376         struct drm_i915_private *dev_priv;
13377         int crtc_clock, cdclk;
13378
13379         if (!intel_crtc || !crtc_state)
13380                 return DRM_PLANE_HELPER_NO_SCALING;
13381
13382         dev = intel_crtc->base.dev;
13383         dev_priv = dev->dev_private;
13384         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13385         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13386
13387         if (!crtc_clock || !cdclk)
13388                 return DRM_PLANE_HELPER_NO_SCALING;
13389
13390         /*
13391          * skl max scale is lower of:
13392          *    close to 3 but not 3, -1 is for that purpose
13393          *            or
13394          *    cdclk/crtc_clock
13395          */
13396         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13397
13398         return max_scale;
13399 }
13400
13401 static int
13402 intel_check_primary_plane(struct drm_plane *plane,
13403                           struct intel_crtc_state *crtc_state,
13404                           struct intel_plane_state *state)
13405 {
13406         struct drm_crtc *crtc = state->base.crtc;
13407         struct drm_framebuffer *fb = state->base.fb;
13408         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13409         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13410         bool can_position = false;
13411
13412         /* use scaler when colorkey is not required */
13413         if (INTEL_INFO(plane->dev)->gen >= 9 &&
13414             state->ckey.flags == I915_SET_COLORKEY_NONE) {
13415                 min_scale = 1;
13416                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13417                 can_position = true;
13418         }
13419
13420         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13421                                              &state->dst, &state->clip,
13422                                              min_scale, max_scale,
13423                                              can_position, true,
13424                                              &state->visible);
13425 }
13426
13427 static void
13428 intel_commit_primary_plane(struct drm_plane *plane,
13429                            struct intel_plane_state *state)
13430 {
13431         struct drm_crtc *crtc = state->base.crtc;
13432         struct drm_framebuffer *fb = state->base.fb;
13433         struct drm_device *dev = plane->dev;
13434         struct drm_i915_private *dev_priv = dev->dev_private;
13435         struct intel_crtc *intel_crtc;
13436         struct drm_rect *src = &state->src;
13437
13438         crtc = crtc ? crtc : plane->crtc;
13439         intel_crtc = to_intel_crtc(crtc);
13440
13441         plane->fb = fb;
13442         crtc->x = src->x1 >> 16;
13443         crtc->y = src->y1 >> 16;
13444
13445         if (!crtc->state->active)
13446                 return;
13447
13448         if (state->visible)
13449                 /* FIXME: kill this fastboot hack */
13450                 intel_update_pipe_size(intel_crtc);
13451
13452         dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13453 }
13454
13455 static void
13456 intel_disable_primary_plane(struct drm_plane *plane,
13457                             struct drm_crtc *crtc)
13458 {
13459         struct drm_device *dev = plane->dev;
13460         struct drm_i915_private *dev_priv = dev->dev_private;
13461
13462         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13463 }
13464
13465 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13466                                     struct drm_crtc_state *old_crtc_state)
13467 {
13468         struct drm_device *dev = crtc->dev;
13469         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13470
13471         if (intel_crtc->atomic.update_wm_pre)
13472                 intel_update_watermarks(crtc);
13473
13474         /* Perform vblank evasion around commit operation */
13475         if (crtc->state->active)
13476                 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13477
13478         if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13479                 skl_detach_scalers(intel_crtc);
13480 }
13481
13482 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13483                                      struct drm_crtc_state *old_crtc_state)
13484 {
13485         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13486
13487         if (crtc->state->active)
13488                 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13489 }
13490
13491 /**
13492  * intel_plane_destroy - destroy a plane
13493  * @plane: plane to destroy
13494  *
13495  * Common destruction function for all types of planes (primary, cursor,
13496  * sprite).
13497  */
13498 void intel_plane_destroy(struct drm_plane *plane)
13499 {
13500         struct intel_plane *intel_plane = to_intel_plane(plane);
13501         drm_plane_cleanup(plane);
13502         kfree(intel_plane);
13503 }
13504
13505 const struct drm_plane_funcs intel_plane_funcs = {
13506         .update_plane = drm_atomic_helper_update_plane,
13507         .disable_plane = drm_atomic_helper_disable_plane,
13508         .destroy = intel_plane_destroy,
13509         .set_property = drm_atomic_helper_plane_set_property,
13510         .atomic_get_property = intel_plane_atomic_get_property,
13511         .atomic_set_property = intel_plane_atomic_set_property,
13512         .atomic_duplicate_state = intel_plane_duplicate_state,
13513         .atomic_destroy_state = intel_plane_destroy_state,
13514
13515 };
13516
13517 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13518                                                     int pipe)
13519 {
13520         struct intel_plane *primary;
13521         struct intel_plane_state *state;
13522         const uint32_t *intel_primary_formats;
13523         int num_formats;
13524
13525         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13526         if (primary == NULL)
13527                 return NULL;
13528
13529         state = intel_create_plane_state(&primary->base);
13530         if (!state) {
13531                 kfree(primary);
13532                 return NULL;
13533         }
13534         primary->base.state = &state->base;
13535
13536         primary->can_scale = false;
13537         primary->max_downscale = 1;
13538         if (INTEL_INFO(dev)->gen >= 9) {
13539                 primary->can_scale = true;
13540                 state->scaler_id = -1;
13541         }
13542         primary->pipe = pipe;
13543         primary->plane = pipe;
13544         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13545         primary->check_plane = intel_check_primary_plane;
13546         primary->commit_plane = intel_commit_primary_plane;
13547         primary->disable_plane = intel_disable_primary_plane;
13548         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13549                 primary->plane = !pipe;
13550
13551         if (INTEL_INFO(dev)->gen >= 9) {
13552                 intel_primary_formats = skl_primary_formats;
13553                 num_formats = ARRAY_SIZE(skl_primary_formats);
13554         } else if (INTEL_INFO(dev)->gen >= 4) {
13555                 intel_primary_formats = i965_primary_formats;
13556                 num_formats = ARRAY_SIZE(i965_primary_formats);
13557         } else {
13558                 intel_primary_formats = i8xx_primary_formats;
13559                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13560         }
13561
13562         drm_universal_plane_init(dev, &primary->base, 0,
13563                                  &intel_plane_funcs,
13564                                  intel_primary_formats, num_formats,
13565                                  DRM_PLANE_TYPE_PRIMARY);
13566
13567         if (INTEL_INFO(dev)->gen >= 4)
13568                 intel_create_rotation_property(dev, primary);
13569
13570         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13571
13572         return &primary->base;
13573 }
13574
13575 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13576 {
13577         if (!dev->mode_config.rotation_property) {
13578                 unsigned long flags = BIT(DRM_ROTATE_0) |
13579                         BIT(DRM_ROTATE_180);
13580
13581                 if (INTEL_INFO(dev)->gen >= 9)
13582                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13583
13584                 dev->mode_config.rotation_property =
13585                         drm_mode_create_rotation_property(dev, flags);
13586         }
13587         if (dev->mode_config.rotation_property)
13588                 drm_object_attach_property(&plane->base.base,
13589                                 dev->mode_config.rotation_property,
13590                                 plane->base.state->rotation);
13591 }
13592
13593 static int
13594 intel_check_cursor_plane(struct drm_plane *plane,
13595                          struct intel_crtc_state *crtc_state,
13596                          struct intel_plane_state *state)
13597 {
13598         struct drm_crtc *crtc = crtc_state->base.crtc;
13599         struct drm_framebuffer *fb = state->base.fb;
13600         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13601         unsigned stride;
13602         int ret;
13603
13604         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13605                                             &state->dst, &state->clip,
13606                                             DRM_PLANE_HELPER_NO_SCALING,
13607                                             DRM_PLANE_HELPER_NO_SCALING,
13608                                             true, true, &state->visible);
13609         if (ret)
13610                 return ret;
13611
13612         /* if we want to turn off the cursor ignore width and height */
13613         if (!obj)
13614                 return 0;
13615
13616         /* Check for which cursor types we support */
13617         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13618                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13619                           state->base.crtc_w, state->base.crtc_h);
13620                 return -EINVAL;
13621         }
13622
13623         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13624         if (obj->base.size < stride * state->base.crtc_h) {
13625                 DRM_DEBUG_KMS("buffer is too small\n");
13626                 return -ENOMEM;
13627         }
13628
13629         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13630                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13631                 return -EINVAL;
13632         }
13633
13634         return 0;
13635 }
13636
13637 static void
13638 intel_disable_cursor_plane(struct drm_plane *plane,
13639                            struct drm_crtc *crtc)
13640 {
13641         intel_crtc_update_cursor(crtc, false);
13642 }
13643
13644 static void
13645 intel_commit_cursor_plane(struct drm_plane *plane,
13646                           struct intel_plane_state *state)
13647 {
13648         struct drm_crtc *crtc = state->base.crtc;
13649         struct drm_device *dev = plane->dev;
13650         struct intel_crtc *intel_crtc;
13651         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13652         uint32_t addr;
13653
13654         crtc = crtc ? crtc : plane->crtc;
13655         intel_crtc = to_intel_crtc(crtc);
13656
13657         plane->fb = state->base.fb;
13658         crtc->cursor_x = state->base.crtc_x;
13659         crtc->cursor_y = state->base.crtc_y;
13660
13661         if (intel_crtc->cursor_bo == obj)
13662                 goto update;
13663
13664         if (!obj)
13665                 addr = 0;
13666         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13667                 addr = i915_gem_obj_ggtt_offset(obj);
13668         else
13669                 addr = obj->phys_handle->busaddr;
13670
13671         intel_crtc->cursor_addr = addr;
13672         intel_crtc->cursor_bo = obj;
13673
13674 update:
13675         if (crtc->state->active)
13676                 intel_crtc_update_cursor(crtc, state->visible);
13677 }
13678
13679 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13680                                                    int pipe)
13681 {
13682         struct intel_plane *cursor;
13683         struct intel_plane_state *state;
13684
13685         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13686         if (cursor == NULL)
13687                 return NULL;
13688
13689         state = intel_create_plane_state(&cursor->base);
13690         if (!state) {
13691                 kfree(cursor);
13692                 return NULL;
13693         }
13694         cursor->base.state = &state->base;
13695
13696         cursor->can_scale = false;
13697         cursor->max_downscale = 1;
13698         cursor->pipe = pipe;
13699         cursor->plane = pipe;
13700         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13701         cursor->check_plane = intel_check_cursor_plane;
13702         cursor->commit_plane = intel_commit_cursor_plane;
13703         cursor->disable_plane = intel_disable_cursor_plane;
13704
13705         drm_universal_plane_init(dev, &cursor->base, 0,
13706                                  &intel_plane_funcs,
13707                                  intel_cursor_formats,
13708                                  ARRAY_SIZE(intel_cursor_formats),
13709                                  DRM_PLANE_TYPE_CURSOR);
13710
13711         if (INTEL_INFO(dev)->gen >= 4) {
13712                 if (!dev->mode_config.rotation_property)
13713                         dev->mode_config.rotation_property =
13714                                 drm_mode_create_rotation_property(dev,
13715                                                         BIT(DRM_ROTATE_0) |
13716                                                         BIT(DRM_ROTATE_180));
13717                 if (dev->mode_config.rotation_property)
13718                         drm_object_attach_property(&cursor->base.base,
13719                                 dev->mode_config.rotation_property,
13720                                 state->base.rotation);
13721         }
13722
13723         if (INTEL_INFO(dev)->gen >=9)
13724                 state->scaler_id = -1;
13725
13726         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13727
13728         return &cursor->base;
13729 }
13730
13731 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13732         struct intel_crtc_state *crtc_state)
13733 {
13734         int i;
13735         struct intel_scaler *intel_scaler;
13736         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13737
13738         for (i = 0; i < intel_crtc->num_scalers; i++) {
13739                 intel_scaler = &scaler_state->scalers[i];
13740                 intel_scaler->in_use = 0;
13741                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13742         }
13743
13744         scaler_state->scaler_id = -1;
13745 }
13746
13747 static void intel_crtc_init(struct drm_device *dev, int pipe)
13748 {
13749         struct drm_i915_private *dev_priv = dev->dev_private;
13750         struct intel_crtc *intel_crtc;
13751         struct intel_crtc_state *crtc_state = NULL;
13752         struct drm_plane *primary = NULL;
13753         struct drm_plane *cursor = NULL;
13754         int i, ret;
13755
13756         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13757         if (intel_crtc == NULL)
13758                 return;
13759
13760         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13761         if (!crtc_state)
13762                 goto fail;
13763         intel_crtc->config = crtc_state;
13764         intel_crtc->base.state = &crtc_state->base;
13765         crtc_state->base.crtc = &intel_crtc->base;
13766
13767         /* initialize shared scalers */
13768         if (INTEL_INFO(dev)->gen >= 9) {
13769                 if (pipe == PIPE_C)
13770                         intel_crtc->num_scalers = 1;
13771                 else
13772                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13773
13774                 skl_init_scalers(dev, intel_crtc, crtc_state);
13775         }
13776
13777         primary = intel_primary_plane_create(dev, pipe);
13778         if (!primary)
13779                 goto fail;
13780
13781         cursor = intel_cursor_plane_create(dev, pipe);
13782         if (!cursor)
13783                 goto fail;
13784
13785         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13786                                         cursor, &intel_crtc_funcs);
13787         if (ret)
13788                 goto fail;
13789
13790         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13791         for (i = 0; i < 256; i++) {
13792                 intel_crtc->lut_r[i] = i;
13793                 intel_crtc->lut_g[i] = i;
13794                 intel_crtc->lut_b[i] = i;
13795         }
13796
13797         /*
13798          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13799          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13800          */
13801         intel_crtc->pipe = pipe;
13802         intel_crtc->plane = pipe;
13803         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13804                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13805                 intel_crtc->plane = !pipe;
13806         }
13807
13808         intel_crtc->cursor_base = ~0;
13809         intel_crtc->cursor_cntl = ~0;
13810         intel_crtc->cursor_size = ~0;
13811
13812         intel_crtc->wm.cxsr_allowed = true;
13813
13814         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13815                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13816         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13817         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13818
13819         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13820
13821         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13822         return;
13823
13824 fail:
13825         if (primary)
13826                 drm_plane_cleanup(primary);
13827         if (cursor)
13828                 drm_plane_cleanup(cursor);
13829         kfree(crtc_state);
13830         kfree(intel_crtc);
13831 }
13832
13833 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13834 {
13835         struct drm_encoder *encoder = connector->base.encoder;
13836         struct drm_device *dev = connector->base.dev;
13837
13838         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13839
13840         if (!encoder || WARN_ON(!encoder->crtc))
13841                 return INVALID_PIPE;
13842
13843         return to_intel_crtc(encoder->crtc)->pipe;
13844 }
13845
13846 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13847                                 struct drm_file *file)
13848 {
13849         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13850         struct drm_crtc *drmmode_crtc;
13851         struct intel_crtc *crtc;
13852
13853         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13854
13855         if (!drmmode_crtc) {
13856                 DRM_ERROR("no such CRTC id\n");
13857                 return -ENOENT;
13858         }
13859
13860         crtc = to_intel_crtc(drmmode_crtc);
13861         pipe_from_crtc_id->pipe = crtc->pipe;
13862
13863         return 0;
13864 }
13865
13866 static int intel_encoder_clones(struct intel_encoder *encoder)
13867 {
13868         struct drm_device *dev = encoder->base.dev;
13869         struct intel_encoder *source_encoder;
13870         int index_mask = 0;
13871         int entry = 0;
13872
13873         for_each_intel_encoder(dev, source_encoder) {
13874                 if (encoders_cloneable(encoder, source_encoder))
13875                         index_mask |= (1 << entry);
13876
13877                 entry++;
13878         }
13879
13880         return index_mask;
13881 }
13882
13883 static bool has_edp_a(struct drm_device *dev)
13884 {
13885         struct drm_i915_private *dev_priv = dev->dev_private;
13886
13887         if (!IS_MOBILE(dev))
13888                 return false;
13889
13890         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13891                 return false;
13892
13893         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13894                 return false;
13895
13896         return true;
13897 }
13898
13899 static bool intel_crt_present(struct drm_device *dev)
13900 {
13901         struct drm_i915_private *dev_priv = dev->dev_private;
13902
13903         if (INTEL_INFO(dev)->gen >= 9)
13904                 return false;
13905
13906         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13907                 return false;
13908
13909         if (IS_CHERRYVIEW(dev))
13910                 return false;
13911
13912         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13913                 return false;
13914
13915         return true;
13916 }
13917
13918 static void intel_setup_outputs(struct drm_device *dev)
13919 {
13920         struct drm_i915_private *dev_priv = dev->dev_private;
13921         struct intel_encoder *encoder;
13922         bool dpd_is_edp = false;
13923
13924         intel_lvds_init(dev);
13925
13926         if (intel_crt_present(dev))
13927                 intel_crt_init(dev);
13928
13929         if (IS_BROXTON(dev)) {
13930                 /*
13931                  * FIXME: Broxton doesn't support port detection via the
13932                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13933                  * detect the ports.
13934                  */
13935                 intel_ddi_init(dev, PORT_A);
13936                 intel_ddi_init(dev, PORT_B);
13937                 intel_ddi_init(dev, PORT_C);
13938         } else if (HAS_DDI(dev)) {
13939                 int found;
13940
13941                 /*
13942                  * Haswell uses DDI functions to detect digital outputs.
13943                  * On SKL pre-D0 the strap isn't connected, so we assume
13944                  * it's there.
13945                  */
13946                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13947                 /* WaIgnoreDDIAStrap: skl */
13948                 if (found || IS_SKYLAKE(dev))
13949                         intel_ddi_init(dev, PORT_A);
13950
13951                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13952                  * register */
13953                 found = I915_READ(SFUSE_STRAP);
13954
13955                 if (found & SFUSE_STRAP_DDIB_DETECTED)
13956                         intel_ddi_init(dev, PORT_B);
13957                 if (found & SFUSE_STRAP_DDIC_DETECTED)
13958                         intel_ddi_init(dev, PORT_C);
13959                 if (found & SFUSE_STRAP_DDID_DETECTED)
13960                         intel_ddi_init(dev, PORT_D);
13961         } else if (HAS_PCH_SPLIT(dev)) {
13962                 int found;
13963                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13964
13965                 if (has_edp_a(dev))
13966                         intel_dp_init(dev, DP_A, PORT_A);
13967
13968                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13969                         /* PCH SDVOB multiplex with HDMIB */
13970                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
13971                         if (!found)
13972                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13973                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13974                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
13975                 }
13976
13977                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13978                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13979
13980                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13981                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13982
13983                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13984                         intel_dp_init(dev, PCH_DP_C, PORT_C);
13985
13986                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13987                         intel_dp_init(dev, PCH_DP_D, PORT_D);
13988         } else if (IS_VALLEYVIEW(dev)) {
13989                 /*
13990                  * The DP_DETECTED bit is the latched state of the DDC
13991                  * SDA pin at boot. However since eDP doesn't require DDC
13992                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
13993                  * eDP ports may have been muxed to an alternate function.
13994                  * Thus we can't rely on the DP_DETECTED bit alone to detect
13995                  * eDP ports. Consult the VBT as well as DP_DETECTED to
13996                  * detect eDP ports.
13997                  */
13998                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13999                     !intel_dp_is_edp(dev, PORT_B))
14000                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14001                                         PORT_B);
14002                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14003                     intel_dp_is_edp(dev, PORT_B))
14004                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14005
14006                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14007                     !intel_dp_is_edp(dev, PORT_C))
14008                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14009                                         PORT_C);
14010                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14011                     intel_dp_is_edp(dev, PORT_C))
14012                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14013
14014                 if (IS_CHERRYVIEW(dev)) {
14015                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14016                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14017                                                 PORT_D);
14018                         /* eDP not supported on port D, so don't check VBT */
14019                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14020                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14021                 }
14022
14023                 intel_dsi_init(dev);
14024         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14025                 bool found = false;
14026
14027                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14028                         DRM_DEBUG_KMS("probing SDVOB\n");
14029                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14030                         if (!found && IS_G4X(dev)) {
14031                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14032                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14033                         }
14034
14035                         if (!found && IS_G4X(dev))
14036                                 intel_dp_init(dev, DP_B, PORT_B);
14037                 }
14038
14039                 /* Before G4X SDVOC doesn't have its own detect register */
14040
14041                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14042                         DRM_DEBUG_KMS("probing SDVOC\n");
14043                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14044                 }
14045
14046                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14047
14048                         if (IS_G4X(dev)) {
14049                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14050                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14051                         }
14052                         if (IS_G4X(dev))
14053                                 intel_dp_init(dev, DP_C, PORT_C);
14054                 }
14055
14056                 if (IS_G4X(dev) &&
14057                     (I915_READ(DP_D) & DP_DETECTED))
14058                         intel_dp_init(dev, DP_D, PORT_D);
14059         } else if (IS_GEN2(dev))
14060                 intel_dvo_init(dev);
14061
14062         if (SUPPORTS_TV(dev))
14063                 intel_tv_init(dev);
14064
14065         intel_psr_init(dev);
14066
14067         for_each_intel_encoder(dev, encoder) {
14068                 encoder->base.possible_crtcs = encoder->crtc_mask;
14069                 encoder->base.possible_clones =
14070                         intel_encoder_clones(encoder);
14071         }
14072
14073         intel_init_pch_refclk(dev);
14074
14075         drm_helper_move_panel_connectors_to_head(dev);
14076 }
14077
14078 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14079 {
14080         struct drm_device *dev = fb->dev;
14081         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14082
14083         drm_framebuffer_cleanup(fb);
14084         mutex_lock(&dev->struct_mutex);
14085         WARN_ON(!intel_fb->obj->framebuffer_references--);
14086         drm_gem_object_unreference(&intel_fb->obj->base);
14087         mutex_unlock(&dev->struct_mutex);
14088         kfree(intel_fb);
14089 }
14090
14091 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14092                                                 struct drm_file *file,
14093                                                 unsigned int *handle)
14094 {
14095         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14096         struct drm_i915_gem_object *obj = intel_fb->obj;
14097
14098         return drm_gem_handle_create(file, &obj->base, handle);
14099 }
14100
14101 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14102                                         struct drm_file *file,
14103                                         unsigned flags, unsigned color,
14104                                         struct drm_clip_rect *clips,
14105                                         unsigned num_clips)
14106 {
14107         struct drm_device *dev = fb->dev;
14108         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14109         struct drm_i915_gem_object *obj = intel_fb->obj;
14110
14111         mutex_lock(&dev->struct_mutex);
14112         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14113         mutex_unlock(&dev->struct_mutex);
14114
14115         return 0;
14116 }
14117
14118 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14119         .destroy = intel_user_framebuffer_destroy,
14120         .create_handle = intel_user_framebuffer_create_handle,
14121         .dirty = intel_user_framebuffer_dirty,
14122 };
14123
14124 static
14125 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14126                          uint32_t pixel_format)
14127 {
14128         u32 gen = INTEL_INFO(dev)->gen;
14129
14130         if (gen >= 9) {
14131                 /* "The stride in bytes must not exceed the of the size of 8K
14132                  *  pixels and 32K bytes."
14133                  */
14134                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14135         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14136                 return 32*1024;
14137         } else if (gen >= 4) {
14138                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14139                         return 16*1024;
14140                 else
14141                         return 32*1024;
14142         } else if (gen >= 3) {
14143                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14144                         return 8*1024;
14145                 else
14146                         return 16*1024;
14147         } else {
14148                 /* XXX DSPC is limited to 4k tiled */
14149                 return 8*1024;
14150         }
14151 }
14152
14153 static int intel_framebuffer_init(struct drm_device *dev,
14154                                   struct intel_framebuffer *intel_fb,
14155                                   struct drm_mode_fb_cmd2 *mode_cmd,
14156                                   struct drm_i915_gem_object *obj)
14157 {
14158         unsigned int aligned_height;
14159         int ret;
14160         u32 pitch_limit, stride_alignment;
14161
14162         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14163
14164         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14165                 /* Enforce that fb modifier and tiling mode match, but only for
14166                  * X-tiled. This is needed for FBC. */
14167                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14168                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14169                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14170                         return -EINVAL;
14171                 }
14172         } else {
14173                 if (obj->tiling_mode == I915_TILING_X)
14174                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14175                 else if (obj->tiling_mode == I915_TILING_Y) {
14176                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14177                         return -EINVAL;
14178                 }
14179         }
14180
14181         /* Passed in modifier sanity checking. */
14182         switch (mode_cmd->modifier[0]) {
14183         case I915_FORMAT_MOD_Y_TILED:
14184         case I915_FORMAT_MOD_Yf_TILED:
14185                 if (INTEL_INFO(dev)->gen < 9) {
14186                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14187                                   mode_cmd->modifier[0]);
14188                         return -EINVAL;
14189                 }
14190         case DRM_FORMAT_MOD_NONE:
14191         case I915_FORMAT_MOD_X_TILED:
14192                 break;
14193         default:
14194                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14195                           mode_cmd->modifier[0]);
14196                 return -EINVAL;
14197         }
14198
14199         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14200                                                      mode_cmd->pixel_format);
14201         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14202                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14203                           mode_cmd->pitches[0], stride_alignment);
14204                 return -EINVAL;
14205         }
14206
14207         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14208                                            mode_cmd->pixel_format);
14209         if (mode_cmd->pitches[0] > pitch_limit) {
14210                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14211                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14212                           "tiled" : "linear",
14213                           mode_cmd->pitches[0], pitch_limit);
14214                 return -EINVAL;
14215         }
14216
14217         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14218             mode_cmd->pitches[0] != obj->stride) {
14219                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14220                           mode_cmd->pitches[0], obj->stride);
14221                 return -EINVAL;
14222         }
14223
14224         /* Reject formats not supported by any plane early. */
14225         switch (mode_cmd->pixel_format) {
14226         case DRM_FORMAT_C8:
14227         case DRM_FORMAT_RGB565:
14228         case DRM_FORMAT_XRGB8888:
14229         case DRM_FORMAT_ARGB8888:
14230                 break;
14231         case DRM_FORMAT_XRGB1555:
14232                 if (INTEL_INFO(dev)->gen > 3) {
14233                         DRM_DEBUG("unsupported pixel format: %s\n",
14234                                   drm_get_format_name(mode_cmd->pixel_format));
14235                         return -EINVAL;
14236                 }
14237                 break;
14238         case DRM_FORMAT_ABGR8888:
14239                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14240                         DRM_DEBUG("unsupported pixel format: %s\n",
14241                                   drm_get_format_name(mode_cmd->pixel_format));
14242                         return -EINVAL;
14243                 }
14244                 break;
14245         case DRM_FORMAT_XBGR8888:
14246         case DRM_FORMAT_XRGB2101010:
14247         case DRM_FORMAT_XBGR2101010:
14248                 if (INTEL_INFO(dev)->gen < 4) {
14249                         DRM_DEBUG("unsupported pixel format: %s\n",
14250                                   drm_get_format_name(mode_cmd->pixel_format));
14251                         return -EINVAL;
14252                 }
14253                 break;
14254         case DRM_FORMAT_ABGR2101010:
14255                 if (!IS_VALLEYVIEW(dev)) {
14256                         DRM_DEBUG("unsupported pixel format: %s\n",
14257                                   drm_get_format_name(mode_cmd->pixel_format));
14258                         return -EINVAL;
14259                 }
14260                 break;
14261         case DRM_FORMAT_YUYV:
14262         case DRM_FORMAT_UYVY:
14263         case DRM_FORMAT_YVYU:
14264         case DRM_FORMAT_VYUY:
14265                 if (INTEL_INFO(dev)->gen < 5) {
14266                         DRM_DEBUG("unsupported pixel format: %s\n",
14267                                   drm_get_format_name(mode_cmd->pixel_format));
14268                         return -EINVAL;
14269                 }
14270                 break;
14271         default:
14272                 DRM_DEBUG("unsupported pixel format: %s\n",
14273                           drm_get_format_name(mode_cmd->pixel_format));
14274                 return -EINVAL;
14275         }
14276
14277         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14278         if (mode_cmd->offsets[0] != 0)
14279                 return -EINVAL;
14280
14281         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14282                                                mode_cmd->pixel_format,
14283                                                mode_cmd->modifier[0]);
14284         /* FIXME drm helper for size checks (especially planar formats)? */
14285         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14286                 return -EINVAL;
14287
14288         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14289         intel_fb->obj = obj;
14290         intel_fb->obj->framebuffer_references++;
14291
14292         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14293         if (ret) {
14294                 DRM_ERROR("framebuffer init failed %d\n", ret);
14295                 return ret;
14296         }
14297
14298         return 0;
14299 }
14300
14301 static struct drm_framebuffer *
14302 intel_user_framebuffer_create(struct drm_device *dev,
14303                               struct drm_file *filp,
14304                               struct drm_mode_fb_cmd2 *mode_cmd)
14305 {
14306         struct drm_i915_gem_object *obj;
14307
14308         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14309                                                 mode_cmd->handles[0]));
14310         if (&obj->base == NULL)
14311                 return ERR_PTR(-ENOENT);
14312
14313         return intel_framebuffer_create(dev, mode_cmd, obj);
14314 }
14315
14316 #ifndef CONFIG_DRM_I915_FBDEV
14317 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14318 {
14319 }
14320 #endif
14321
14322 static const struct drm_mode_config_funcs intel_mode_funcs = {
14323         .fb_create = intel_user_framebuffer_create,
14324         .output_poll_changed = intel_fbdev_output_poll_changed,
14325         .atomic_check = intel_atomic_check,
14326         .atomic_commit = intel_atomic_commit,
14327         .atomic_state_alloc = intel_atomic_state_alloc,
14328         .atomic_state_clear = intel_atomic_state_clear,
14329 };
14330
14331 /* Set up chip specific display functions */
14332 static void intel_init_display(struct drm_device *dev)
14333 {
14334         struct drm_i915_private *dev_priv = dev->dev_private;
14335
14336         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14337                 dev_priv->display.find_dpll = g4x_find_best_dpll;
14338         else if (IS_CHERRYVIEW(dev))
14339                 dev_priv->display.find_dpll = chv_find_best_dpll;
14340         else if (IS_VALLEYVIEW(dev))
14341                 dev_priv->display.find_dpll = vlv_find_best_dpll;
14342         else if (IS_PINEVIEW(dev))
14343                 dev_priv->display.find_dpll = pnv_find_best_dpll;
14344         else
14345                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14346
14347         if (INTEL_INFO(dev)->gen >= 9) {
14348                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14349                 dev_priv->display.get_initial_plane_config =
14350                         skylake_get_initial_plane_config;
14351                 dev_priv->display.crtc_compute_clock =
14352                         haswell_crtc_compute_clock;
14353                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14354                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14355                 dev_priv->display.update_primary_plane =
14356                         skylake_update_primary_plane;
14357         } else if (HAS_DDI(dev)) {
14358                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14359                 dev_priv->display.get_initial_plane_config =
14360                         ironlake_get_initial_plane_config;
14361                 dev_priv->display.crtc_compute_clock =
14362                         haswell_crtc_compute_clock;
14363                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14364                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14365                 dev_priv->display.update_primary_plane =
14366                         ironlake_update_primary_plane;
14367         } else if (HAS_PCH_SPLIT(dev)) {
14368                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14369                 dev_priv->display.get_initial_plane_config =
14370                         ironlake_get_initial_plane_config;
14371                 dev_priv->display.crtc_compute_clock =
14372                         ironlake_crtc_compute_clock;
14373                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14374                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14375                 dev_priv->display.update_primary_plane =
14376                         ironlake_update_primary_plane;
14377         } else if (IS_VALLEYVIEW(dev)) {
14378                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14379                 dev_priv->display.get_initial_plane_config =
14380                         i9xx_get_initial_plane_config;
14381                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14382                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14383                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14384                 dev_priv->display.update_primary_plane =
14385                         i9xx_update_primary_plane;
14386         } else {
14387                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14388                 dev_priv->display.get_initial_plane_config =
14389                         i9xx_get_initial_plane_config;
14390                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14391                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14392                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14393                 dev_priv->display.update_primary_plane =
14394                         i9xx_update_primary_plane;
14395         }
14396
14397         /* Returns the core display clock speed */
14398         if (IS_SKYLAKE(dev))
14399                 dev_priv->display.get_display_clock_speed =
14400                         skylake_get_display_clock_speed;
14401         else if (IS_BROXTON(dev))
14402                 dev_priv->display.get_display_clock_speed =
14403                         broxton_get_display_clock_speed;
14404         else if (IS_BROADWELL(dev))
14405                 dev_priv->display.get_display_clock_speed =
14406                         broadwell_get_display_clock_speed;
14407         else if (IS_HASWELL(dev))
14408                 dev_priv->display.get_display_clock_speed =
14409                         haswell_get_display_clock_speed;
14410         else if (IS_VALLEYVIEW(dev))
14411                 dev_priv->display.get_display_clock_speed =
14412                         valleyview_get_display_clock_speed;
14413         else if (IS_GEN5(dev))
14414                 dev_priv->display.get_display_clock_speed =
14415                         ilk_get_display_clock_speed;
14416         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14417                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14418                 dev_priv->display.get_display_clock_speed =
14419                         i945_get_display_clock_speed;
14420         else if (IS_GM45(dev))
14421                 dev_priv->display.get_display_clock_speed =
14422                         gm45_get_display_clock_speed;
14423         else if (IS_CRESTLINE(dev))
14424                 dev_priv->display.get_display_clock_speed =
14425                         i965gm_get_display_clock_speed;
14426         else if (IS_PINEVIEW(dev))
14427                 dev_priv->display.get_display_clock_speed =
14428                         pnv_get_display_clock_speed;
14429         else if (IS_G33(dev) || IS_G4X(dev))
14430                 dev_priv->display.get_display_clock_speed =
14431                         g33_get_display_clock_speed;
14432         else if (IS_I915G(dev))
14433                 dev_priv->display.get_display_clock_speed =
14434                         i915_get_display_clock_speed;
14435         else if (IS_I945GM(dev) || IS_845G(dev))
14436                 dev_priv->display.get_display_clock_speed =
14437                         i9xx_misc_get_display_clock_speed;
14438         else if (IS_PINEVIEW(dev))
14439                 dev_priv->display.get_display_clock_speed =
14440                         pnv_get_display_clock_speed;
14441         else if (IS_I915GM(dev))
14442                 dev_priv->display.get_display_clock_speed =
14443                         i915gm_get_display_clock_speed;
14444         else if (IS_I865G(dev))
14445                 dev_priv->display.get_display_clock_speed =
14446                         i865_get_display_clock_speed;
14447         else if (IS_I85X(dev))
14448                 dev_priv->display.get_display_clock_speed =
14449                         i85x_get_display_clock_speed;
14450         else { /* 830 */
14451                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14452                 dev_priv->display.get_display_clock_speed =
14453                         i830_get_display_clock_speed;
14454         }
14455
14456         if (IS_GEN5(dev)) {
14457                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14458         } else if (IS_GEN6(dev)) {
14459                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14460         } else if (IS_IVYBRIDGE(dev)) {
14461                 /* FIXME: detect B0+ stepping and use auto training */
14462                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14463         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14464                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14465                 if (IS_BROADWELL(dev)) {
14466                         dev_priv->display.modeset_commit_cdclk =
14467                                 broadwell_modeset_commit_cdclk;
14468                         dev_priv->display.modeset_calc_cdclk =
14469                                 broadwell_modeset_calc_cdclk;
14470                 }
14471         } else if (IS_VALLEYVIEW(dev)) {
14472                 dev_priv->display.modeset_commit_cdclk =
14473                         valleyview_modeset_commit_cdclk;
14474                 dev_priv->display.modeset_calc_cdclk =
14475                         valleyview_modeset_calc_cdclk;
14476         } else if (IS_BROXTON(dev)) {
14477                 dev_priv->display.modeset_commit_cdclk =
14478                         broxton_modeset_commit_cdclk;
14479                 dev_priv->display.modeset_calc_cdclk =
14480                         broxton_modeset_calc_cdclk;
14481         }
14482
14483         switch (INTEL_INFO(dev)->gen) {
14484         case 2:
14485                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14486                 break;
14487
14488         case 3:
14489                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14490                 break;
14491
14492         case 4:
14493         case 5:
14494                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14495                 break;
14496
14497         case 6:
14498                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14499                 break;
14500         case 7:
14501         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14502                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14503                 break;
14504         case 9:
14505                 /* Drop through - unsupported since execlist only. */
14506         default:
14507                 /* Default just returns -ENODEV to indicate unsupported */
14508                 dev_priv->display.queue_flip = intel_default_queue_flip;
14509         }
14510
14511         intel_panel_init_backlight_funcs(dev);
14512
14513         mutex_init(&dev_priv->pps_mutex);
14514 }
14515
14516 /*
14517  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14518  * resume, or other times.  This quirk makes sure that's the case for
14519  * affected systems.
14520  */
14521 static void quirk_pipea_force(struct drm_device *dev)
14522 {
14523         struct drm_i915_private *dev_priv = dev->dev_private;
14524
14525         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14526         DRM_INFO("applying pipe a force quirk\n");
14527 }
14528
14529 static void quirk_pipeb_force(struct drm_device *dev)
14530 {
14531         struct drm_i915_private *dev_priv = dev->dev_private;
14532
14533         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14534         DRM_INFO("applying pipe b force quirk\n");
14535 }
14536
14537 /*
14538  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14539  */
14540 static void quirk_ssc_force_disable(struct drm_device *dev)
14541 {
14542         struct drm_i915_private *dev_priv = dev->dev_private;
14543         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14544         DRM_INFO("applying lvds SSC disable quirk\n");
14545 }
14546
14547 /*
14548  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14549  * brightness value
14550  */
14551 static void quirk_invert_brightness(struct drm_device *dev)
14552 {
14553         struct drm_i915_private *dev_priv = dev->dev_private;
14554         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14555         DRM_INFO("applying inverted panel brightness quirk\n");
14556 }
14557
14558 /* Some VBT's incorrectly indicate no backlight is present */
14559 static void quirk_backlight_present(struct drm_device *dev)
14560 {
14561         struct drm_i915_private *dev_priv = dev->dev_private;
14562         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14563         DRM_INFO("applying backlight present quirk\n");
14564 }
14565
14566 struct intel_quirk {
14567         int device;
14568         int subsystem_vendor;
14569         int subsystem_device;
14570         void (*hook)(struct drm_device *dev);
14571 };
14572
14573 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14574 struct intel_dmi_quirk {
14575         void (*hook)(struct drm_device *dev);
14576         const struct dmi_system_id (*dmi_id_list)[];
14577 };
14578
14579 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14580 {
14581         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14582         return 1;
14583 }
14584
14585 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14586         {
14587                 .dmi_id_list = &(const struct dmi_system_id[]) {
14588                         {
14589                                 .callback = intel_dmi_reverse_brightness,
14590                                 .ident = "NCR Corporation",
14591                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14592                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14593                                 },
14594                         },
14595                         { }  /* terminating entry */
14596                 },
14597                 .hook = quirk_invert_brightness,
14598         },
14599 };
14600
14601 static struct intel_quirk intel_quirks[] = {
14602         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14603         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14604
14605         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14606         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14607
14608         /* 830 needs to leave pipe A & dpll A up */
14609         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14610
14611         /* 830 needs to leave pipe B & dpll B up */
14612         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14613
14614         /* Lenovo U160 cannot use SSC on LVDS */
14615         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14616
14617         /* Sony Vaio Y cannot use SSC on LVDS */
14618         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14619
14620         /* Acer Aspire 5734Z must invert backlight brightness */
14621         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14622
14623         /* Acer/eMachines G725 */
14624         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14625
14626         /* Acer/eMachines e725 */
14627         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14628
14629         /* Acer/Packard Bell NCL20 */
14630         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14631
14632         /* Acer Aspire 4736Z */
14633         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14634
14635         /* Acer Aspire 5336 */
14636         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14637
14638         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14639         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14640
14641         /* Acer C720 Chromebook (Core i3 4005U) */
14642         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14643
14644         /* Apple Macbook 2,1 (Core 2 T7400) */
14645         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14646
14647         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14648         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14649
14650         /* HP Chromebook 14 (Celeron 2955U) */
14651         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14652
14653         /* Dell Chromebook 11 */
14654         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14655 };
14656
14657 static void intel_init_quirks(struct drm_device *dev)
14658 {
14659         struct pci_dev *d = dev->pdev;
14660         int i;
14661
14662         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14663                 struct intel_quirk *q = &intel_quirks[i];
14664
14665                 if (d->device == q->device &&
14666                     (d->subsystem_vendor == q->subsystem_vendor ||
14667                      q->subsystem_vendor == PCI_ANY_ID) &&
14668                     (d->subsystem_device == q->subsystem_device ||
14669                      q->subsystem_device == PCI_ANY_ID))
14670                         q->hook(dev);
14671         }
14672         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14673                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14674                         intel_dmi_quirks[i].hook(dev);
14675         }
14676 }
14677
14678 /* Disable the VGA plane that we never use */
14679 static void i915_disable_vga(struct drm_device *dev)
14680 {
14681         struct drm_i915_private *dev_priv = dev->dev_private;
14682         u8 sr1;
14683         u32 vga_reg = i915_vgacntrl_reg(dev);
14684
14685         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14686         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14687         outb(SR01, VGA_SR_INDEX);
14688         sr1 = inb(VGA_SR_DATA);
14689         outb(sr1 | 1<<5, VGA_SR_DATA);
14690         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14691         udelay(300);
14692
14693         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14694         POSTING_READ(vga_reg);
14695 }
14696
14697 void intel_modeset_init_hw(struct drm_device *dev)
14698 {
14699         intel_update_cdclk(dev);
14700         intel_prepare_ddi(dev);
14701         intel_init_clock_gating(dev);
14702         intel_enable_gt_powersave(dev);
14703 }
14704
14705 void intel_modeset_init(struct drm_device *dev)
14706 {
14707         struct drm_i915_private *dev_priv = dev->dev_private;
14708         int sprite, ret;
14709         enum pipe pipe;
14710         struct intel_crtc *crtc;
14711
14712         drm_mode_config_init(dev);
14713
14714         dev->mode_config.min_width = 0;
14715         dev->mode_config.min_height = 0;
14716
14717         dev->mode_config.preferred_depth = 24;
14718         dev->mode_config.prefer_shadow = 1;
14719
14720         dev->mode_config.allow_fb_modifiers = true;
14721
14722         dev->mode_config.funcs = &intel_mode_funcs;
14723
14724         intel_init_quirks(dev);
14725
14726         intel_init_pm(dev);
14727
14728         if (INTEL_INFO(dev)->num_pipes == 0)
14729                 return;
14730
14731         intel_init_display(dev);
14732         intel_init_audio(dev);
14733
14734         if (IS_GEN2(dev)) {
14735                 dev->mode_config.max_width = 2048;
14736                 dev->mode_config.max_height = 2048;
14737         } else if (IS_GEN3(dev)) {
14738                 dev->mode_config.max_width = 4096;
14739                 dev->mode_config.max_height = 4096;
14740         } else {
14741                 dev->mode_config.max_width = 8192;
14742                 dev->mode_config.max_height = 8192;
14743         }
14744
14745         if (IS_845G(dev) || IS_I865G(dev)) {
14746                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14747                 dev->mode_config.cursor_height = 1023;
14748         } else if (IS_GEN2(dev)) {
14749                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14750                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14751         } else {
14752                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14753                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14754         }
14755
14756         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14757
14758         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14759                       INTEL_INFO(dev)->num_pipes,
14760                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14761
14762         for_each_pipe(dev_priv, pipe) {
14763                 intel_crtc_init(dev, pipe);
14764                 for_each_sprite(dev_priv, pipe, sprite) {
14765                         ret = intel_plane_init(dev, pipe, sprite);
14766                         if (ret)
14767                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14768                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14769                 }
14770         }
14771
14772         intel_init_dpio(dev);
14773
14774         intel_shared_dpll_init(dev);
14775
14776         /* Just disable it once at startup */
14777         i915_disable_vga(dev);
14778         intel_setup_outputs(dev);
14779
14780         /* Just in case the BIOS is doing something questionable. */
14781         intel_fbc_disable(dev_priv);
14782
14783         drm_modeset_lock_all(dev);
14784         intel_modeset_setup_hw_state(dev);
14785         drm_modeset_unlock_all(dev);
14786
14787         for_each_intel_crtc(dev, crtc) {
14788                 struct intel_initial_plane_config plane_config = {};
14789
14790                 if (!crtc->active)
14791                         continue;
14792
14793                 /*
14794                  * Note that reserving the BIOS fb up front prevents us
14795                  * from stuffing other stolen allocations like the ring
14796                  * on top.  This prevents some ugliness at boot time, and
14797                  * can even allow for smooth boot transitions if the BIOS
14798                  * fb is large enough for the active pipe configuration.
14799                  */
14800                 dev_priv->display.get_initial_plane_config(crtc,
14801                                                            &plane_config);
14802
14803                 /*
14804                  * If the fb is shared between multiple heads, we'll
14805                  * just get the first one.
14806                  */
14807                 intel_find_initial_plane_obj(crtc, &plane_config);
14808         }
14809 }
14810
14811 static void intel_enable_pipe_a(struct drm_device *dev)
14812 {
14813         struct intel_connector *connector;
14814         struct drm_connector *crt = NULL;
14815         struct intel_load_detect_pipe load_detect_temp;
14816         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14817
14818         /* We can't just switch on the pipe A, we need to set things up with a
14819          * proper mode and output configuration. As a gross hack, enable pipe A
14820          * by enabling the load detect pipe once. */
14821         for_each_intel_connector(dev, connector) {
14822                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14823                         crt = &connector->base;
14824                         break;
14825                 }
14826         }
14827
14828         if (!crt)
14829                 return;
14830
14831         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14832                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14833 }
14834
14835 static bool
14836 intel_check_plane_mapping(struct intel_crtc *crtc)
14837 {
14838         struct drm_device *dev = crtc->base.dev;
14839         struct drm_i915_private *dev_priv = dev->dev_private;
14840         u32 reg, val;
14841
14842         if (INTEL_INFO(dev)->num_pipes == 1)
14843                 return true;
14844
14845         reg = DSPCNTR(!crtc->plane);
14846         val = I915_READ(reg);
14847
14848         if ((val & DISPLAY_PLANE_ENABLE) &&
14849             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14850                 return false;
14851
14852         return true;
14853 }
14854
14855 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14856 {
14857         struct drm_device *dev = crtc->base.dev;
14858         struct drm_i915_private *dev_priv = dev->dev_private;
14859         struct intel_encoder *encoder;
14860         u32 reg;
14861         bool enable;
14862
14863         /* Clear any frame start delays used for debugging left by the BIOS */
14864         reg = PIPECONF(crtc->config->cpu_transcoder);
14865         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14866
14867         /* restore vblank interrupts to correct state */
14868         drm_crtc_vblank_reset(&crtc->base);
14869         if (crtc->active) {
14870                 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
14871                 update_scanline_offset(crtc);
14872                 drm_crtc_vblank_on(&crtc->base);
14873         }
14874
14875         /* We need to sanitize the plane -> pipe mapping first because this will
14876          * disable the crtc (and hence change the state) if it is wrong. Note
14877          * that gen4+ has a fixed plane -> pipe mapping.  */
14878         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14879                 bool plane;
14880
14881                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14882                               crtc->base.base.id);
14883
14884                 /* Pipe has the wrong plane attached and the plane is active.
14885                  * Temporarily change the plane mapping and disable everything
14886                  * ...  */
14887                 plane = crtc->plane;
14888                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14889                 crtc->plane = !plane;
14890                 intel_crtc_disable_noatomic(&crtc->base);
14891                 crtc->plane = plane;
14892         }
14893
14894         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14895             crtc->pipe == PIPE_A && !crtc->active) {
14896                 /* BIOS forgot to enable pipe A, this mostly happens after
14897                  * resume. Force-enable the pipe to fix this, the update_dpms
14898                  * call below we restore the pipe to the right state, but leave
14899                  * the required bits on. */
14900                 intel_enable_pipe_a(dev);
14901         }
14902
14903         /* Adjust the state of the output pipe according to whether we
14904          * have active connectors/encoders. */
14905         enable = false;
14906         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14907                 enable = true;
14908                 break;
14909         }
14910
14911         if (!enable)
14912                 intel_crtc_disable_noatomic(&crtc->base);
14913
14914         if (crtc->active != crtc->base.state->active) {
14915
14916                 /* This can happen either due to bugs in the get_hw_state
14917                  * functions or because of calls to intel_crtc_disable_noatomic,
14918                  * or because the pipe is force-enabled due to the
14919                  * pipe A quirk. */
14920                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14921                               crtc->base.base.id,
14922                               crtc->base.state->enable ? "enabled" : "disabled",
14923                               crtc->active ? "enabled" : "disabled");
14924
14925                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
14926                 crtc->base.state->active = crtc->active;
14927                 crtc->base.enabled = crtc->active;
14928
14929                 /* Because we only establish the connector -> encoder ->
14930                  * crtc links if something is active, this means the
14931                  * crtc is now deactivated. Break the links. connector
14932                  * -> encoder links are only establish when things are
14933                  *  actually up, hence no need to break them. */
14934                 WARN_ON(crtc->active);
14935
14936                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14937                         encoder->base.crtc = NULL;
14938         }
14939
14940         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14941                 /*
14942                  * We start out with underrun reporting disabled to avoid races.
14943                  * For correct bookkeeping mark this on active crtcs.
14944                  *
14945                  * Also on gmch platforms we dont have any hardware bits to
14946                  * disable the underrun reporting. Which means we need to start
14947                  * out with underrun reporting disabled also on inactive pipes,
14948                  * since otherwise we'll complain about the garbage we read when
14949                  * e.g. coming up after runtime pm.
14950                  *
14951                  * No protection against concurrent access is required - at
14952                  * worst a fifo underrun happens which also sets this to false.
14953                  */
14954                 crtc->cpu_fifo_underrun_disabled = true;
14955                 crtc->pch_fifo_underrun_disabled = true;
14956         }
14957 }
14958
14959 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14960 {
14961         struct intel_connector *connector;
14962         struct drm_device *dev = encoder->base.dev;
14963         bool active = false;
14964
14965         /* We need to check both for a crtc link (meaning that the
14966          * encoder is active and trying to read from a pipe) and the
14967          * pipe itself being active. */
14968         bool has_active_crtc = encoder->base.crtc &&
14969                 to_intel_crtc(encoder->base.crtc)->active;
14970
14971         for_each_intel_connector(dev, connector) {
14972                 if (connector->base.encoder != &encoder->base)
14973                         continue;
14974
14975                 active = true;
14976                 break;
14977         }
14978
14979         if (active && !has_active_crtc) {
14980                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14981                               encoder->base.base.id,
14982                               encoder->base.name);
14983
14984                 /* Connector is active, but has no active pipe. This is
14985                  * fallout from our resume register restoring. Disable
14986                  * the encoder manually again. */
14987                 if (encoder->base.crtc) {
14988                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14989                                       encoder->base.base.id,
14990                                       encoder->base.name);
14991                         encoder->disable(encoder);
14992                         if (encoder->post_disable)
14993                                 encoder->post_disable(encoder);
14994                 }
14995                 encoder->base.crtc = NULL;
14996
14997                 /* Inconsistent output/port/pipe state happens presumably due to
14998                  * a bug in one of the get_hw_state functions. Or someplace else
14999                  * in our code, like the register restore mess on resume. Clamp
15000                  * things to off as a safer default. */
15001                 for_each_intel_connector(dev, connector) {
15002                         if (connector->encoder != encoder)
15003                                 continue;
15004                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15005                         connector->base.encoder = NULL;
15006                 }
15007         }
15008         /* Enabled encoders without active connectors will be fixed in
15009          * the crtc fixup. */
15010 }
15011
15012 void i915_redisable_vga_power_on(struct drm_device *dev)
15013 {
15014         struct drm_i915_private *dev_priv = dev->dev_private;
15015         u32 vga_reg = i915_vgacntrl_reg(dev);
15016
15017         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15018                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15019                 i915_disable_vga(dev);
15020         }
15021 }
15022
15023 void i915_redisable_vga(struct drm_device *dev)
15024 {
15025         struct drm_i915_private *dev_priv = dev->dev_private;
15026
15027         /* This function can be called both from intel_modeset_setup_hw_state or
15028          * at a very early point in our resume sequence, where the power well
15029          * structures are not yet restored. Since this function is at a very
15030          * paranoid "someone might have enabled VGA while we were not looking"
15031          * level, just check if the power well is enabled instead of trying to
15032          * follow the "don't touch the power well if we don't need it" policy
15033          * the rest of the driver uses. */
15034         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15035                 return;
15036
15037         i915_redisable_vga_power_on(dev);
15038 }
15039
15040 static bool primary_get_hw_state(struct intel_crtc *crtc)
15041 {
15042         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15043
15044         return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15045 }
15046
15047 static void readout_plane_state(struct intel_crtc *crtc,
15048                                 struct intel_crtc_state *crtc_state)
15049 {
15050         struct intel_plane *p;
15051         struct intel_plane_state *plane_state;
15052         bool active = crtc_state->base.active;
15053
15054         for_each_intel_plane(crtc->base.dev, p) {
15055                 if (crtc->pipe != p->pipe)
15056                         continue;
15057
15058                 plane_state = to_intel_plane_state(p->base.state);
15059
15060                 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15061                         plane_state->visible = primary_get_hw_state(crtc);
15062                 else {
15063                         if (active)
15064                                 p->disable_plane(&p->base, &crtc->base);
15065
15066                         plane_state->visible = false;
15067                 }
15068         }
15069 }
15070
15071 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15072 {
15073         struct drm_i915_private *dev_priv = dev->dev_private;
15074         enum pipe pipe;
15075         struct intel_crtc *crtc;
15076         struct intel_encoder *encoder;
15077         struct intel_connector *connector;
15078         int i;
15079
15080         for_each_intel_crtc(dev, crtc) {
15081                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15082                 memset(crtc->config, 0, sizeof(*crtc->config));
15083                 crtc->config->base.crtc = &crtc->base;
15084
15085                 crtc->active = dev_priv->display.get_pipe_config(crtc,
15086                                                                  crtc->config);
15087
15088                 crtc->base.state->active = crtc->active;
15089                 crtc->base.enabled = crtc->active;
15090
15091                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15092                 if (crtc->base.state->active) {
15093                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15094                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15095                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15096
15097                         /*
15098                          * The initial mode needs to be set in order to keep
15099                          * the atomic core happy. It wants a valid mode if the
15100                          * crtc's enabled, so we do the above call.
15101                          *
15102                          * At this point some state updated by the connectors
15103                          * in their ->detect() callback has not run yet, so
15104                          * no recalculation can be done yet.
15105                          *
15106                          * Even if we could do a recalculation and modeset
15107                          * right now it would cause a double modeset if
15108                          * fbdev or userspace chooses a different initial mode.
15109                          *
15110                          * If that happens, someone indicated they wanted a
15111                          * mode change, which means it's safe to do a full
15112                          * recalculation.
15113                          */
15114                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15115                 }
15116
15117                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15118                 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15119
15120                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15121                               crtc->base.base.id,
15122                               crtc->active ? "enabled" : "disabled");
15123         }
15124
15125         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15126                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15127
15128                 pll->on = pll->get_hw_state(dev_priv, pll,
15129                                             &pll->config.hw_state);
15130                 pll->active = 0;
15131                 pll->config.crtc_mask = 0;
15132                 for_each_intel_crtc(dev, crtc) {
15133                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15134                                 pll->active++;
15135                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15136                         }
15137                 }
15138
15139                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15140                               pll->name, pll->config.crtc_mask, pll->on);
15141
15142                 if (pll->config.crtc_mask)
15143                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15144         }
15145
15146         for_each_intel_encoder(dev, encoder) {
15147                 pipe = 0;
15148
15149                 if (encoder->get_hw_state(encoder, &pipe)) {
15150                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15151                         encoder->base.crtc = &crtc->base;
15152                         encoder->get_config(encoder, crtc->config);
15153                 } else {
15154                         encoder->base.crtc = NULL;
15155                 }
15156
15157                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15158                               encoder->base.base.id,
15159                               encoder->base.name,
15160                               encoder->base.crtc ? "enabled" : "disabled",
15161                               pipe_name(pipe));
15162         }
15163
15164         for_each_intel_connector(dev, connector) {
15165                 if (connector->get_hw_state(connector)) {
15166                         connector->base.dpms = DRM_MODE_DPMS_ON;
15167                         connector->base.encoder = &connector->encoder->base;
15168                 } else {
15169                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15170                         connector->base.encoder = NULL;
15171                 }
15172                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15173                               connector->base.base.id,
15174                               connector->base.name,
15175                               connector->base.encoder ? "enabled" : "disabled");
15176         }
15177 }
15178
15179 /* Scan out the current hw modeset state,
15180  * and sanitizes it to the current state
15181  */
15182 static void
15183 intel_modeset_setup_hw_state(struct drm_device *dev)
15184 {
15185         struct drm_i915_private *dev_priv = dev->dev_private;
15186         enum pipe pipe;
15187         struct intel_crtc *crtc;
15188         struct intel_encoder *encoder;
15189         int i;
15190
15191         intel_modeset_readout_hw_state(dev);
15192
15193         /* HW state is read out, now we need to sanitize this mess. */
15194         for_each_intel_encoder(dev, encoder) {
15195                 intel_sanitize_encoder(encoder);
15196         }
15197
15198         for_each_pipe(dev_priv, pipe) {
15199                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15200                 intel_sanitize_crtc(crtc);
15201                 intel_dump_pipe_config(crtc, crtc->config,
15202                                        "[setup_hw_state]");
15203         }
15204
15205         intel_modeset_update_connector_atomic_state(dev);
15206
15207         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15208                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15209
15210                 if (!pll->on || pll->active)
15211                         continue;
15212
15213                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15214
15215                 pll->disable(dev_priv, pll);
15216                 pll->on = false;
15217         }
15218
15219         if (IS_VALLEYVIEW(dev))
15220                 vlv_wm_get_hw_state(dev);
15221         else if (IS_GEN9(dev))
15222                 skl_wm_get_hw_state(dev);
15223         else if (HAS_PCH_SPLIT(dev))
15224                 ilk_wm_get_hw_state(dev);
15225
15226         for_each_intel_crtc(dev, crtc) {
15227                 unsigned long put_domains;
15228
15229                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15230                 if (WARN_ON(put_domains))
15231                         modeset_put_power_domains(dev_priv, put_domains);
15232         }
15233         intel_display_set_init_power(dev_priv, false);
15234 }
15235
15236 void intel_display_resume(struct drm_device *dev)
15237 {
15238         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15239         struct intel_connector *conn;
15240         struct intel_plane *plane;
15241         struct drm_crtc *crtc;
15242         int ret;
15243
15244         if (!state)
15245                 return;
15246
15247         state->acquire_ctx = dev->mode_config.acquire_ctx;
15248
15249         /* preserve complete old state, including dpll */
15250         intel_atomic_get_shared_dpll_state(state);
15251
15252         for_each_crtc(dev, crtc) {
15253                 struct drm_crtc_state *crtc_state =
15254                         drm_atomic_get_crtc_state(state, crtc);
15255
15256                 ret = PTR_ERR_OR_ZERO(crtc_state);
15257                 if (ret)
15258                         goto err;
15259
15260                 /* force a restore */
15261                 crtc_state->mode_changed = true;
15262         }
15263
15264         for_each_intel_plane(dev, plane) {
15265                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15266                 if (ret)
15267                         goto err;
15268         }
15269
15270         for_each_intel_connector(dev, conn) {
15271                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15272                 if (ret)
15273                         goto err;
15274         }
15275
15276         intel_modeset_setup_hw_state(dev);
15277
15278         i915_redisable_vga(dev);
15279         ret = drm_atomic_commit(state);
15280         if (!ret)
15281                 return;
15282
15283 err:
15284         DRM_ERROR("Restoring old state failed with %i\n", ret);
15285         drm_atomic_state_free(state);
15286 }
15287
15288 void intel_modeset_gem_init(struct drm_device *dev)
15289 {
15290         struct drm_i915_private *dev_priv = dev->dev_private;
15291         struct drm_crtc *c;
15292         struct drm_i915_gem_object *obj;
15293         int ret;
15294
15295         mutex_lock(&dev->struct_mutex);
15296         intel_init_gt_powersave(dev);
15297         mutex_unlock(&dev->struct_mutex);
15298
15299         /*
15300          * There may be no VBT; and if the BIOS enabled SSC we can
15301          * just keep using it to avoid unnecessary flicker.  Whereas if the
15302          * BIOS isn't using it, don't assume it will work even if the VBT
15303          * indicates as much.
15304          */
15305         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15306                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15307                                                 DREF_SSC1_ENABLE);
15308
15309         intel_modeset_init_hw(dev);
15310
15311         intel_setup_overlay(dev);
15312
15313         /*
15314          * Make sure any fbs we allocated at startup are properly
15315          * pinned & fenced.  When we do the allocation it's too early
15316          * for this.
15317          */
15318         for_each_crtc(dev, c) {
15319                 obj = intel_fb_obj(c->primary->fb);
15320                 if (obj == NULL)
15321                         continue;
15322
15323                 mutex_lock(&dev->struct_mutex);
15324                 ret = intel_pin_and_fence_fb_obj(c->primary,
15325                                                  c->primary->fb,
15326                                                  c->primary->state,
15327                                                  NULL, NULL);
15328                 mutex_unlock(&dev->struct_mutex);
15329                 if (ret) {
15330                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15331                                   to_intel_crtc(c)->pipe);
15332                         drm_framebuffer_unreference(c->primary->fb);
15333                         c->primary->fb = NULL;
15334                         c->primary->crtc = c->primary->state->crtc = NULL;
15335                         update_state_fb(c->primary);
15336                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15337                 }
15338         }
15339
15340         intel_backlight_register(dev);
15341 }
15342
15343 void intel_connector_unregister(struct intel_connector *intel_connector)
15344 {
15345         struct drm_connector *connector = &intel_connector->base;
15346
15347         intel_panel_destroy_backlight(connector);
15348         drm_connector_unregister(connector);
15349 }
15350
15351 void intel_modeset_cleanup(struct drm_device *dev)
15352 {
15353         struct drm_i915_private *dev_priv = dev->dev_private;
15354         struct drm_connector *connector;
15355
15356         intel_disable_gt_powersave(dev);
15357
15358         intel_backlight_unregister(dev);
15359
15360         /*
15361          * Interrupts and polling as the first thing to avoid creating havoc.
15362          * Too much stuff here (turning of connectors, ...) would
15363          * experience fancy races otherwise.
15364          */
15365         intel_irq_uninstall(dev_priv);
15366
15367         /*
15368          * Due to the hpd irq storm handling the hotplug work can re-arm the
15369          * poll handlers. Hence disable polling after hpd handling is shut down.
15370          */
15371         drm_kms_helper_poll_fini(dev);
15372
15373         intel_unregister_dsm_handler();
15374
15375         intel_fbc_disable(dev_priv);
15376
15377         /* flush any delayed tasks or pending work */
15378         flush_scheduled_work();
15379
15380         /* destroy the backlight and sysfs files before encoders/connectors */
15381         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15382                 struct intel_connector *intel_connector;
15383
15384                 intel_connector = to_intel_connector(connector);
15385                 intel_connector->unregister(intel_connector);
15386         }
15387
15388         drm_mode_config_cleanup(dev);
15389
15390         intel_cleanup_overlay(dev);
15391
15392         mutex_lock(&dev->struct_mutex);
15393         intel_cleanup_gt_powersave(dev);
15394         mutex_unlock(&dev->struct_mutex);
15395 }
15396
15397 /*
15398  * Return which encoder is currently attached for connector.
15399  */
15400 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15401 {
15402         return &intel_attached_encoder(connector)->base;
15403 }
15404
15405 void intel_connector_attach_encoder(struct intel_connector *connector,
15406                                     struct intel_encoder *encoder)
15407 {
15408         connector->encoder = encoder;
15409         drm_mode_connector_attach_encoder(&connector->base,
15410                                           &encoder->base);
15411 }
15412
15413 /*
15414  * set vga decode state - true == enable VGA decode
15415  */
15416 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15417 {
15418         struct drm_i915_private *dev_priv = dev->dev_private;
15419         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15420         u16 gmch_ctrl;
15421
15422         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15423                 DRM_ERROR("failed to read control word\n");
15424                 return -EIO;
15425         }
15426
15427         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15428                 return 0;
15429
15430         if (state)
15431                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15432         else
15433                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15434
15435         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15436                 DRM_ERROR("failed to write control word\n");
15437                 return -EIO;
15438         }
15439
15440         return 0;
15441 }
15442
15443 struct intel_display_error_state {
15444
15445         u32 power_well_driver;
15446
15447         int num_transcoders;
15448
15449         struct intel_cursor_error_state {
15450                 u32 control;
15451                 u32 position;
15452                 u32 base;
15453                 u32 size;
15454         } cursor[I915_MAX_PIPES];
15455
15456         struct intel_pipe_error_state {
15457                 bool power_domain_on;
15458                 u32 source;
15459                 u32 stat;
15460         } pipe[I915_MAX_PIPES];
15461
15462         struct intel_plane_error_state {
15463                 u32 control;
15464                 u32 stride;
15465                 u32 size;
15466                 u32 pos;
15467                 u32 addr;
15468                 u32 surface;
15469                 u32 tile_offset;
15470         } plane[I915_MAX_PIPES];
15471
15472         struct intel_transcoder_error_state {
15473                 bool power_domain_on;
15474                 enum transcoder cpu_transcoder;
15475
15476                 u32 conf;
15477
15478                 u32 htotal;
15479                 u32 hblank;
15480                 u32 hsync;
15481                 u32 vtotal;
15482                 u32 vblank;
15483                 u32 vsync;
15484         } transcoder[4];
15485 };
15486
15487 struct intel_display_error_state *
15488 intel_display_capture_error_state(struct drm_device *dev)
15489 {
15490         struct drm_i915_private *dev_priv = dev->dev_private;
15491         struct intel_display_error_state *error;
15492         int transcoders[] = {
15493                 TRANSCODER_A,
15494                 TRANSCODER_B,
15495                 TRANSCODER_C,
15496                 TRANSCODER_EDP,
15497         };
15498         int i;
15499
15500         if (INTEL_INFO(dev)->num_pipes == 0)
15501                 return NULL;
15502
15503         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15504         if (error == NULL)
15505                 return NULL;
15506
15507         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15508                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15509
15510         for_each_pipe(dev_priv, i) {
15511                 error->pipe[i].power_domain_on =
15512                         __intel_display_power_is_enabled(dev_priv,
15513                                                          POWER_DOMAIN_PIPE(i));
15514                 if (!error->pipe[i].power_domain_on)
15515                         continue;
15516
15517                 error->cursor[i].control = I915_READ(CURCNTR(i));
15518                 error->cursor[i].position = I915_READ(CURPOS(i));
15519                 error->cursor[i].base = I915_READ(CURBASE(i));
15520
15521                 error->plane[i].control = I915_READ(DSPCNTR(i));
15522                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15523                 if (INTEL_INFO(dev)->gen <= 3) {
15524                         error->plane[i].size = I915_READ(DSPSIZE(i));
15525                         error->plane[i].pos = I915_READ(DSPPOS(i));
15526                 }
15527                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15528                         error->plane[i].addr = I915_READ(DSPADDR(i));
15529                 if (INTEL_INFO(dev)->gen >= 4) {
15530                         error->plane[i].surface = I915_READ(DSPSURF(i));
15531                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15532                 }
15533
15534                 error->pipe[i].source = I915_READ(PIPESRC(i));
15535
15536                 if (HAS_GMCH_DISPLAY(dev))
15537                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15538         }
15539
15540         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15541         if (HAS_DDI(dev_priv->dev))
15542                 error->num_transcoders++; /* Account for eDP. */
15543
15544         for (i = 0; i < error->num_transcoders; i++) {
15545                 enum transcoder cpu_transcoder = transcoders[i];
15546
15547                 error->transcoder[i].power_domain_on =
15548                         __intel_display_power_is_enabled(dev_priv,
15549                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15550                 if (!error->transcoder[i].power_domain_on)
15551                         continue;
15552
15553                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15554
15555                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15556                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15557                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15558                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15559                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15560                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15561                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15562         }
15563
15564         return error;
15565 }
15566
15567 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15568
15569 void
15570 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15571                                 struct drm_device *dev,
15572                                 struct intel_display_error_state *error)
15573 {
15574         struct drm_i915_private *dev_priv = dev->dev_private;
15575         int i;
15576
15577         if (!error)
15578                 return;
15579
15580         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15581         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15582                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15583                            error->power_well_driver);
15584         for_each_pipe(dev_priv, i) {
15585                 err_printf(m, "Pipe [%d]:\n", i);
15586                 err_printf(m, "  Power: %s\n",
15587                            error->pipe[i].power_domain_on ? "on" : "off");
15588                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15589                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15590
15591                 err_printf(m, "Plane [%d]:\n", i);
15592                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15593                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15594                 if (INTEL_INFO(dev)->gen <= 3) {
15595                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15596                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15597                 }
15598                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15599                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15600                 if (INTEL_INFO(dev)->gen >= 4) {
15601                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15602                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15603                 }
15604
15605                 err_printf(m, "Cursor [%d]:\n", i);
15606                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15607                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15608                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15609         }
15610
15611         for (i = 0; i < error->num_transcoders; i++) {
15612                 err_printf(m, "CPU transcoder: %c\n",
15613                            transcoder_name(error->transcoder[i].cpu_transcoder));
15614                 err_printf(m, "  Power: %s\n",
15615                            error->transcoder[i].power_domain_on ? "on" : "off");
15616                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15617                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15618                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15619                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15620                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15621                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15622                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15623         }
15624 }
15625
15626 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15627 {
15628         struct intel_crtc *crtc;
15629
15630         for_each_intel_crtc(dev, crtc) {
15631                 struct intel_unpin_work *work;
15632
15633                 spin_lock_irq(&dev->event_lock);
15634
15635                 work = crtc->unpin_work;
15636
15637                 if (work && work->event &&
15638                     work->event->base.file_priv == file) {
15639                         kfree(work->event);
15640                         work->event = NULL;
15641                 }
15642
15643                 spin_unlock_irq(&dev->event_lock);
15644         }
15645 }