drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  64
  65 typedef struct {
  66         int     min, max;
  67 } intel_range_t;
  68
  69 typedef struct {
  70         int     dot_limit;
  71         int     p2_slow, p2_fast;
  72 } intel_p2_t;
  73
  74 typedef struct intel_limit intel_limit_t;
  75 struct intel_limit {
  76         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  77         intel_p2_t          p2;
  78 };
  79
  80 int
  81 intel_pch_rawclk(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84
  85         WARN_ON(!HAS_PCH_SPLIT(dev));
  86
  87         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  88 }
  89
  90 static inline u32 /* units of 100MHz */
  91 intel_fdi_link_freq(struct drm_device *dev)
  92 {
  93         if (IS_GEN5(dev)) {
  94                 struct drm_i915_private *dev_priv = dev->dev_private;
  95                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  96         } else
  97                 return 27;
  98 }
  99
 100 static const intel_limit_t intel_limits_i8xx_dac = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 908000, .max = 1512000 },
 103         .n = { .min = 2, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 2, .max = 33 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 4, .p2_fast = 2 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i8xx_dvo = {
 114         .dot = { .min = 25000, .max = 350000 },
 115         .vco = { .min = 908000, .max = 1512000 },
 116         .n = { .min = 2, .max = 16 },
 117         .m = { .min = 96, .max = 140 },
 118         .m1 = { .min = 18, .max = 26 },
 119         .m2 = { .min = 6, .max = 16 },
 120         .p = { .min = 4, .max = 128 },
 121         .p1 = { .min = 2, .max = 33 },
 122         .p2 = { .dot_limit = 165000,
 123                 .p2_slow = 4, .p2_fast = 4 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i8xx_lvds = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 908000, .max = 1512000 },
 129         .n = { .min = 2, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 1, .max = 6 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139 static const intel_limit_t intel_limits_i9xx_sdvo = {
 140         .dot = { .min = 20000, .max = 400000 },
 141         .vco = { .min = 1400000, .max = 2800000 },
 142         .n = { .min = 1, .max = 6 },
 143         .m = { .min = 70, .max = 120 },
 144         .m1 = { .min = 8, .max = 18 },
 145         .m2 = { .min = 3, .max = 7 },
 146         .p = { .min = 5, .max = 80 },
 147         .p1 = { .min = 1, .max = 8 },
 148         .p2 = { .dot_limit = 200000,
 149                 .p2_slow = 10, .p2_fast = 5 },
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_lvds = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 8, .max = 18 },
 158         .m2 = { .min = 3, .max = 7 },
 159         .p = { .min = 7, .max = 98 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 112000,
 162                 .p2_slow = 14, .p2_fast = 7 },
 163 };
 164
 165
 166 static const intel_limit_t intel_limits_g4x_sdvo = {
 167         .dot = { .min = 25000, .max = 270000 },
 168         .vco = { .min = 1750000, .max = 3500000},
 169         .n = { .min = 1, .max = 4 },
 170         .m = { .min = 104, .max = 138 },
 171         .m1 = { .min = 17, .max = 23 },
 172         .m2 = { .min = 5, .max = 11 },
 173         .p = { .min = 10, .max = 30 },
 174         .p1 = { .min = 1, .max = 3},
 175         .p2 = { .dot_limit = 270000,
 176                 .p2_slow = 10,
 177                 .p2_fast = 10
 178         },
 179 };
 180
 181 static const intel_limit_t intel_limits_g4x_hdmi = {
 182         .dot = { .min = 22000, .max = 400000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 16, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 5, .max = 80 },
 189         .p1 = { .min = 1, .max = 8},
 190         .p2 = { .dot_limit = 165000,
 191                 .p2_slow = 10, .p2_fast = 5 },
 192 };
 193
 194 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 195         .dot = { .min = 20000, .max = 115000 },
 196         .vco = { .min = 1750000, .max = 3500000 },
 197         .n = { .min = 1, .max = 3 },
 198         .m = { .min = 104, .max = 138 },
 199         .m1 = { .min = 17, .max = 23 },
 200         .m2 = { .min = 5, .max = 11 },
 201         .p = { .min = 28, .max = 112 },
 202         .p1 = { .min = 2, .max = 8 },
 203         .p2 = { .dot_limit = 0,
 204                 .p2_slow = 14, .p2_fast = 14
 205         },
 206 };
 207
 208 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 209         .dot = { .min = 80000, .max = 224000 },
 210         .vco = { .min = 1750000, .max = 3500000 },
 211         .n = { .min = 1, .max = 3 },
 212         .m = { .min = 104, .max = 138 },
 213         .m1 = { .min = 17, .max = 23 },
 214         .m2 = { .min = 5, .max = 11 },
 215         .p = { .min = 14, .max = 42 },
 216         .p1 = { .min = 2, .max = 6 },
 217         .p2 = { .dot_limit = 0,
 218                 .p2_slow = 7, .p2_fast = 7
 219         },
 220 };
 221
 222 static const intel_limit_t intel_limits_pineview_sdvo = {
 223         .dot = { .min = 20000, .max = 400000},
 224         .vco = { .min = 1700000, .max = 3500000 },
 225         /* Pineview's Ncounter is a ring counter */
 226         .n = { .min = 3, .max = 6 },
 227         .m = { .min = 2, .max = 256 },
 228         /* Pineview only has one combined m divider, which we treat as m2. */
 229         .m1 = { .min = 0, .max = 0 },
 230         .m2 = { .min = 0, .max = 254 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8 },
 233         .p2 = { .dot_limit = 200000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_pineview_lvds = {
 238         .dot = { .min = 20000, .max = 400000 },
 239         .vco = { .min = 1700000, .max = 3500000 },
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         .m1 = { .min = 0, .max = 0 },
 243         .m2 = { .min = 0, .max = 254 },
 244         .p = { .min = 7, .max = 112 },
 245         .p1 = { .min = 1, .max = 8 },
 246         .p2 = { .dot_limit = 112000,
 247                 .p2_slow = 14, .p2_fast = 14 },
 248 };
 249
 250 /* Ironlake / Sandybridge
 251  *
 252  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 253  * the range value for them is (actual_value - 2).
 254  */
 255 static const intel_limit_t intel_limits_ironlake_dac = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 5 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 5, .max = 80 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 10, .p2_fast = 5 },
 266 };
 267
 268 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 269         .dot = { .min = 25000, .max = 350000 },
 270         .vco = { .min = 1760000, .max = 3510000 },
 271         .n = { .min = 1, .max = 3 },
 272         .m = { .min = 79, .max = 118 },
 273         .m1 = { .min = 12, .max = 22 },
 274         .m2 = { .min = 5, .max = 9 },
 275         .p = { .min = 28, .max = 112 },
 276         .p1 = { .min = 2, .max = 8 },
 277         .p2 = { .dot_limit = 225000,
 278                 .p2_slow = 14, .p2_fast = 14 },
 279 };
 280
 281 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 282         .dot = { .min = 25000, .max = 350000 },
 283         .vco = { .min = 1760000, .max = 3510000 },
 284         .n = { .min = 1, .max = 3 },
 285         .m = { .min = 79, .max = 127 },
 286         .m1 = { .min = 12, .max = 22 },
 287         .m2 = { .min = 5, .max = 9 },
 288         .p = { .min = 14, .max = 56 },
 289         .p1 = { .min = 2, .max = 8 },
 290         .p2 = { .dot_limit = 225000,
 291                 .p2_slow = 7, .p2_fast = 7 },
 292 };
 293
 294 /* LVDS 100mhz refclk limits. */
 295 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 296         .dot = { .min = 25000, .max = 350000 },
 297         .vco = { .min = 1760000, .max = 3510000 },
 298         .n = { .min = 1, .max = 2 },
 299         .m = { .min = 79, .max = 126 },
 300         .m1 = { .min = 12, .max = 22 },
 301         .m2 = { .min = 5, .max = 9 },
 302         .p = { .min = 28, .max = 112 },
 303         .p1 = { .min = 2, .max = 8 },
 304         .p2 = { .dot_limit = 225000,
 305                 .p2_slow = 14, .p2_fast = 14 },
 306 };
 307
 308 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 309         .dot = { .min = 25000, .max = 350000 },
 310         .vco = { .min = 1760000, .max = 3510000 },
 311         .n = { .min = 1, .max = 3 },
 312         .m = { .min = 79, .max = 126 },
 313         .m1 = { .min = 12, .max = 22 },
 314         .m2 = { .min = 5, .max = 9 },
 315         .p = { .min = 14, .max = 42 },
 316         .p1 = { .min = 2, .max = 6 },
 317         .p2 = { .dot_limit = 225000,
 318                 .p2_slow = 7, .p2_fast = 7 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv = {
 322          /*
 323           * These are the data rate limits (measured in fast clocks)
 324           * since those are the strictest limits we have. The fast
 325           * clock and actual rate limits are more relaxed, so checking
 326           * them would make no difference.
 327           */
 328         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 329         .vco = { .min = 4000000, .max = 6000000 },
 330         .n = { .min = 1, .max = 7 },
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 335 };
 336
 337 static const intel_limit_t intel_limits_chv = {
 338         /*
 339          * These are the data rate limits (measured in fast clocks)
 340          * since those are the strictest limits we have.  The fast
 341          * clock and actual rate limits are more relaxed, so checking
 342          * them would make no difference.
 343          */
 344         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 345         .vco = { .min = 4860000, .max = 6700000 },
 346         .n = { .min = 1, .max = 1 },
 347         .m1 = { .min = 2, .max = 2 },
 348         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 349         .p1 = { .min = 2, .max = 4 },
 350         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 351 };
 352
 353 static void vlv_clock(int refclk, intel_clock_t *clock)
 354 {
 355         clock->m = clock->m1 * clock->m2;
 356         clock->p = clock->p1 * clock->p2;
 357         if (WARN_ON(clock->n == 0 || clock->p == 0))
 358                 return;
 359         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 360         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 361 }
 362
 363 /**
 364  * Returns whether any output on the specified pipe is of the specified type
 365  */
 366 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 367 {
 368         struct drm_device *dev = crtc->dev;
 369         struct intel_encoder *encoder;
 370
 371         for_each_encoder_on_crtc(dev, crtc, encoder)
 372                 if (encoder->type == type)
 373                         return true;
 374
 375         return false;
 376 }
 377
 378 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 379                                                 int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 385                 if (intel_is_dual_link_lvds(dev)) {
 386                         if (refclk == 100000)
 387                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 388                         else
 389                                 limit = &intel_limits_ironlake_dual_lvds;
 390                 } else {
 391                         if (refclk == 100000)
 392                                 limit = &intel_limits_ironlake_single_lvds_100m;
 393                         else
 394                                 limit = &intel_limits_ironlake_single_lvds;
 395                 }
 396         } else
 397                 limit = &intel_limits_ironlake_dac;
 398
 399         return limit;
 400 }
 401
 402 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 403 {
 404         struct drm_device *dev = crtc->dev;
 405         const intel_limit_t *limit;
 406
 407         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 408                 if (intel_is_dual_link_lvds(dev))
 409                         limit = &intel_limits_g4x_dual_channel_lvds;
 410                 else
 411                         limit = &intel_limits_g4x_single_channel_lvds;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 413                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 414                 limit = &intel_limits_g4x_hdmi;
 415         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 416                 limit = &intel_limits_g4x_sdvo;
 417         } else /* The option is for other outputs */
 418                 limit = &intel_limits_i9xx_sdvo;
 419
 420         return limit;
 421 }
 422
 423 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 424 {
 425         struct drm_device *dev = crtc->dev;
 426         const intel_limit_t *limit;
 427
 428         if (HAS_PCH_SPLIT(dev))
 429                 limit = intel_ironlake_limit(crtc, refclk);
 430         else if (IS_G4X(dev)) {
 431                 limit = intel_g4x_limit(crtc);
 432         } else if (IS_PINEVIEW(dev)) {
 433                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 434                         limit = &intel_limits_pineview_lvds;
 435                 else
 436                         limit = &intel_limits_pineview_sdvo;
 437         } else if (IS_CHERRYVIEW(dev)) {
 438                 limit = &intel_limits_chv;
 439         } else if (IS_VALLEYVIEW(dev)) {
 440                 limit = &intel_limits_vlv;
 441         } else if (!IS_GEN2(dev)) {
 442                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 443                         limit = &intel_limits_i9xx_lvds;
 444                 else
 445                         limit = &intel_limits_i9xx_sdvo;
 446         } else {
 447                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 448                         limit = &intel_limits_i8xx_lvds;
 449                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 450                         limit = &intel_limits_i8xx_dvo;
 451                 else
 452                         limit = &intel_limits_i8xx_dac;
 453         }
 454         return limit;
 455 }
 456
 457 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 458 static void pineview_clock(int refclk, intel_clock_t *clock)
 459 {
 460         clock->m = clock->m2 + 2;
 461         clock->p = clock->p1 * clock->p2;
 462         if (WARN_ON(clock->n == 0 || clock->p == 0))
 463                 return;
 464         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 465         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 466 }
 467
 468 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 469 {
 470         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 471 }
 472
 473 static void i9xx_clock(int refclk, intel_clock_t *clock)
 474 {
 475         clock->m = i9xx_dpll_compute_m(clock);
 476         clock->p = clock->p1 * clock->p2;
 477         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 478                 return;
 479         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 480         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 481 }
 482
 483 static void chv_clock(int refclk, intel_clock_t *clock)
 484 {
 485         clock->m = clock->m1 * clock->m2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return;
 489         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 490                         clock->n << 22);
 491         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 492 }
 493
 494 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 495 /**
 496  * Returns whether the given set of divisors are valid for a given refclk with
 497  * the given connectors.
 498  */
 499
 500 static bool intel_PLL_is_valid(struct drm_device *dev,
 501                                const intel_limit_t *limit,
 502                                const intel_clock_t *clock)
 503 {
 504         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 505                 INTELPllInvalid("n out of range\n");
 506         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 507                 INTELPllInvalid("p1 out of range\n");
 508         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 509                 INTELPllInvalid("m2 out of range\n");
 510         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 511                 INTELPllInvalid("m1 out of range\n");
 512
 513         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 514                 if (clock->m1 <= clock->m2)
 515                         INTELPllInvalid("m1 <= m2\n");
 516
 517         if (!IS_VALLEYVIEW(dev)) {
 518                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 519                         INTELPllInvalid("p out of range\n");
 520                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 521                         INTELPllInvalid("m out of range\n");
 522         }
 523
 524         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 525                 INTELPllInvalid("vco out of range\n");
 526         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 527          * connector, etc., rather than just a single range.
 528          */
 529         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 530                 INTELPllInvalid("dot out of range\n");
 531
 532         return true;
 533 }
 534
 535 static bool
 536 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 537                     int target, int refclk, intel_clock_t *match_clock,
 538                     intel_clock_t *best_clock)
 539 {
 540         struct drm_device *dev = crtc->dev;
 541         intel_clock_t clock;
 542         int err = target;
 543
 544         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 545                 /*
 546                  * For LVDS just rely on its current settings for dual-channel.
 547                  * We haven't figured out how to reliably set up different
 548                  * single/dual channel state, if we even can.
 549                  */
 550                 if (intel_is_dual_link_lvds(dev))
 551                         clock.p2 = limit->p2.p2_fast;
 552                 else
 553                         clock.p2 = limit->p2.p2_slow;
 554         } else {
 555                 if (target < limit->p2.dot_limit)
 556                         clock.p2 = limit->p2.p2_slow;
 557                 else
 558                         clock.p2 = limit->p2.p2_fast;
 559         }
 560
 561         memset(best_clock, 0, sizeof(*best_clock));
 562
 563         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 564              clock.m1++) {
 565                 for (clock.m2 = limit->m2.min;
 566                      clock.m2 <= limit->m2.max; clock.m2++) {
 567                         if (clock.m2 >= clock.m1)
 568                                 break;
 569                         for (clock.n = limit->n.min;
 570                              clock.n <= limit->n.max; clock.n++) {
 571                                 for (clock.p1 = limit->p1.min;
 572                                         clock.p1 <= limit->p1.max; clock.p1++) {
 573                                         int this_err;
 574
 575                                         i9xx_clock(refclk, &clock);
 576                                         if (!intel_PLL_is_valid(dev, limit,
 577                                                                 &clock))
 578                                                 continue;
 579                                         if (match_clock &&
 580                                             clock.p != match_clock->p)
 581                                                 continue;
 582
 583                                         this_err = abs(clock.dot - target);
 584                                         if (this_err < err) {
 585                                                 *best_clock = clock;
 586                                                 err = this_err;
 587                                         }
 588                                 }
 589                         }
 590                 }
 591         }
 592
 593         return (err != target);
 594 }
 595
 596 static bool
 597 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 598                    int target, int refclk, intel_clock_t *match_clock,
 599                    intel_clock_t *best_clock)
 600 {
 601         struct drm_device *dev = crtc->dev;
 602         intel_clock_t clock;
 603         int err = target;
 604
 605         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 606                 /*
 607                  * For LVDS just rely on its current settings for dual-channel.
 608                  * We haven't figured out how to reliably set up different
 609                  * single/dual channel state, if we even can.
 610                  */
 611                 if (intel_is_dual_link_lvds(dev))
 612                         clock.p2 = limit->p2.p2_fast;
 613                 else
 614                         clock.p2 = limit->p2.p2_slow;
 615         } else {
 616                 if (target < limit->p2.dot_limit)
 617                         clock.p2 = limit->p2.p2_slow;
 618                 else
 619                         clock.p2 = limit->p2.p2_fast;
 620         }
 621
 622         memset(best_clock, 0, sizeof(*best_clock));
 623
 624         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 625              clock.m1++) {
 626                 for (clock.m2 = limit->m2.min;
 627                      clock.m2 <= limit->m2.max; clock.m2++) {
 628                         for (clock.n = limit->n.min;
 629                              clock.n <= limit->n.max; clock.n++) {
 630                                 for (clock.p1 = limit->p1.min;
 631                                         clock.p1 <= limit->p1.max; clock.p1++) {
 632                                         int this_err;
 633
 634                                         pineview_clock(refclk, &clock);
 635                                         if (!intel_PLL_is_valid(dev, limit,
 636                                                                 &clock))
 637                                                 continue;
 638                                         if (match_clock &&
 639                                             clock.p != match_clock->p)
 640                                                 continue;
 641
 642                                         this_err = abs(clock.dot - target);
 643                                         if (this_err < err) {
 644                                                 *best_clock = clock;
 645                                                 err = this_err;
 646                                         }
 647                                 }
 648                         }
 649                 }
 650         }
 651
 652         return (err != target);
 653 }
 654
 655 static bool
 656 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 657                    int target, int refclk, intel_clock_t *match_clock,
 658                    intel_clock_t *best_clock)
 659 {
 660         struct drm_device *dev = crtc->dev;
 661         intel_clock_t clock;
 662         int max_n;
 663         bool found;
 664         /* approximately equals target * 0.00585 */
 665         int err_most = (target >> 8) + (target >> 9);
 666         found = false;
 667
 668         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 if (intel_is_dual_link_lvds(dev))
 670                         clock.p2 = limit->p2.p2_fast;
 671                 else
 672                         clock.p2 = limit->p2.p2_slow;
 673         } else {
 674                 if (target < limit->p2.dot_limit)
 675                         clock.p2 = limit->p2.p2_slow;
 676                 else
 677                         clock.p2 = limit->p2.p2_fast;
 678         }
 679
 680         memset(best_clock, 0, sizeof(*best_clock));
 681         max_n = limit->n.max;
 682         /* based on hardware requirement, prefer smaller n to precision */
 683         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 684                 /* based on hardware requirement, prefere larger m1,m2 */
 685                 for (clock.m1 = limit->m1.max;
 686                      clock.m1 >= limit->m1.min; clock.m1--) {
 687                         for (clock.m2 = limit->m2.max;
 688                              clock.m2 >= limit->m2.min; clock.m2--) {
 689                                 for (clock.p1 = limit->p1.max;
 690                                      clock.p1 >= limit->p1.min; clock.p1--) {
 691                                         int this_err;
 692
 693                                         i9xx_clock(refclk, &clock);
 694                                         if (!intel_PLL_is_valid(dev, limit,
 695                                                                 &clock))
 696                                                 continue;
 697
 698                                         this_err = abs(clock.dot - target);
 699                                         if (this_err < err_most) {
 700                                                 *best_clock = clock;
 701                                                 err_most = this_err;
 702                                                 max_n = clock.n;
 703                                                 found = true;
 704                                         }
 705                                 }
 706                         }
 707                 }
 708         }
 709         return found;
 710 }
 711
 712 static bool
 713 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 714                    int target, int refclk, intel_clock_t *match_clock,
 715                    intel_clock_t *best_clock)
 716 {
 717         struct drm_device *dev = crtc->dev;
 718         intel_clock_t clock;
 719         unsigned int bestppm = 1000000;
 720         /* min update 19.2 MHz */
 721         int max_n = min(limit->n.max, refclk / 19200);
 722         bool found = false;
 723
 724         target *= 5; /* fast clock */
 725
 726         memset(best_clock, 0, sizeof(*best_clock));
 727
 728         /* based on hardware requirement, prefer smaller n to precision */
 729         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 730                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 731                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 732                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 733                                 clock.p = clock.p1 * clock.p2;
 734                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 735                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 736                                         unsigned int ppm, diff;
 737
 738                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 739                                                                      refclk * clock.m1);
 740
 741                                         vlv_clock(refclk, &clock);
 742
 743                                         if (!intel_PLL_is_valid(dev, limit,
 744                                                                 &clock))
 745                                                 continue;
 746
 747                                         diff = abs(clock.dot - target);
 748                                         ppm = div_u64(1000000ULL * diff, target);
 749
 750                                         if (ppm < 100 && clock.p > best_clock->p) {
 751                                                 bestppm = 0;
 752                                                 *best_clock = clock;
 753                                                 found = true;
 754                                         }
 755
 756                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 757                                                 bestppm = ppm;
 758                                                 *best_clock = clock;
 759                                                 found = true;
 760                                         }
 761                                 }
 762                         }
 763                 }
 764         }
 765
 766         return found;
 767 }
 768
 769 static bool
 770 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 771                    int target, int refclk, intel_clock_t *match_clock,
 772                    intel_clock_t *best_clock)
 773 {
 774         struct drm_device *dev = crtc->dev;
 775         intel_clock_t clock;
 776         uint64_t m2;
 777         int found = false;
 778
 779         memset(best_clock, 0, sizeof(*best_clock));
 780
 781         /*
 782          * Based on hardware doc, the n always set to 1, and m1 always
 783          * set to 2.  If requires to support 200Mhz refclk, we need to
 784          * revisit this because n may not 1 anymore.
 785          */
 786         clock.n = 1, clock.m1 = 2;
 787         target *= 5;    /* fast clock */
 788
 789         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 790                 for (clock.p2 = limit->p2.p2_fast;
 791                                 clock.p2 >= limit->p2.p2_slow;
 792                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 793
 794                         clock.p = clock.p1 * clock.p2;
 795
 796                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 797                                         clock.n) << 22, refclk * clock.m1);
 798
 799                         if (m2 > INT_MAX/clock.m1)
 800                                 continue;
 801
 802                         clock.m2 = m2;
 803
 804                         chv_clock(refclk, &clock);
 805
 806                         if (!intel_PLL_is_valid(dev, limit, &clock))
 807                                 continue;
 808
 809                         /* based on hardware requirement, prefer bigger p
 810                          */
 811                         if (clock.p > best_clock->p) {
 812                                 *best_clock = clock;
 813                                 found = true;
 814                         }
 815                 }
 816         }
 817
 818         return found;
 819 }
 820
 821 bool intel_crtc_active(struct drm_crtc *crtc)
 822 {
 823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 824
 825         /* Be paranoid as we can arrive here with only partial
 826          * state retrieved from the hardware during setup.
 827          *
 828          * We can ditch the adjusted_mode.crtc_clock check as soon
 829          * as Haswell has gained clock readout/fastboot support.
 830          *
 831          * We can ditch the crtc->primary->fb check as soon as we can
 832          * properly reconstruct framebuffers.
 833          */
 834         return intel_crtc->active && crtc->primary->fb &&
 835                 intel_crtc->config.adjusted_mode.crtc_clock;
 836 }
 837
 838 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 839                                              enum pipe pipe)
 840 {
 841         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 843
 844         return intel_crtc->config.cpu_transcoder;
 845 }
 846
 847 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 848 {
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 851
 852         frame = I915_READ(frame_reg);
 853
 854         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 855                 WARN(1, "vblank wait timed out\n");
 856 }
 857
 858 /**
 859  * intel_wait_for_vblank - wait for vblank on a given pipe
 860  * @dev: drm device
 861  * @pipe: pipe to wait for
 862  *
 863  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 864  * mode setting code.
 865  */
 866 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 867 {
 868         struct drm_i915_private *dev_priv = dev->dev_private;
 869         int pipestat_reg = PIPESTAT(pipe);
 870
 871         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 872                 g4x_wait_for_vblank(dev, pipe);
 873                 return;
 874         }
 875
 876         /* Clear existing vblank status. Note this will clear any other
 877          * sticky status fields as well.
 878          *
 879          * This races with i915_driver_irq_handler() with the result
 880          * that either function could miss a vblank event.  Here it is not
 881          * fatal, as we will either wait upon the next vblank interrupt or
 882          * timeout.  Generally speaking intel_wait_for_vblank() is only
 883          * called during modeset at which time the GPU should be idle and
 884          * should *not* be performing page flips and thus not waiting on
 885          * vblanks...
 886          * Currently, the result of us stealing a vblank from the irq
 887          * handler is that a single frame will be skipped during swapbuffers.
 888          */
 889         I915_WRITE(pipestat_reg,
 890                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 891
 892         /* Wait for vblank interrupt bit to set */
 893         if (wait_for(I915_READ(pipestat_reg) &
 894                      PIPE_VBLANK_INTERRUPT_STATUS,
 895                      50))
 896                 DRM_DEBUG_KMS("vblank wait timed out\n");
 897 }
 898
 899 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 900 {
 901         struct drm_i915_private *dev_priv = dev->dev_private;
 902         u32 reg = PIPEDSL(pipe);
 903         u32 line1, line2;
 904         u32 line_mask;
 905
 906         if (IS_GEN2(dev))
 907                 line_mask = DSL_LINEMASK_GEN2;
 908         else
 909                 line_mask = DSL_LINEMASK_GEN3;
 910
 911         line1 = I915_READ(reg) & line_mask;
 912         mdelay(5);
 913         line2 = I915_READ(reg) & line_mask;
 914
 915         return line1 == line2;
 916 }
 917
 918 /*
 919  * intel_wait_for_pipe_off - wait for pipe to turn off
 920  * @dev: drm device
 921  * @pipe: pipe to wait for
 922  *
 923  * After disabling a pipe, we can't wait for vblank in the usual way,
 924  * spinning on the vblank interrupt status bit, since we won't actually
 925  * see an interrupt when the pipe is disabled.
 926  *
 927  * On Gen4 and above:
 928  *   wait for the pipe register state bit to turn off
 929  *
 930  * Otherwise:
 931  *   wait for the display line value to settle (it usually
 932  *   ends up stopping at the start of the next frame).
 933  *
 934  */
 935 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 936 {
 937         struct drm_i915_private *dev_priv = dev->dev_private;
 938         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 939                                                                       pipe);
 940
 941         if (INTEL_INFO(dev)->gen >= 4) {
 942                 int reg = PIPECONF(cpu_transcoder);
 943
 944                 /* Wait for the Pipe State to go off */
 945                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 946                              100))
 947                         WARN(1, "pipe_off wait timed out\n");
 948         } else {
 949                 /* Wait for the display line to settle */
 950                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 951                         WARN(1, "pipe_off wait timed out\n");
 952         }
 953 }
 954
 955 /*
 956  * ibx_digital_port_connected - is the specified port connected?
 957  * @dev_priv: i915 private structure
 958  * @port: the port to test
 959  *
 960  * Returns true if @port is connected, false otherwise.
 961  */
 962 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 963                                 struct intel_digital_port *port)
 964 {
 965         u32 bit;
 966
 967         if (HAS_PCH_IBX(dev_priv->dev)) {
 968                 switch (port->port) {
 969                 case PORT_B:
 970                         bit = SDE_PORTB_HOTPLUG;
 971                         break;
 972                 case PORT_C:
 973                         bit = SDE_PORTC_HOTPLUG;
 974                         break;
 975                 case PORT_D:
 976                         bit = SDE_PORTD_HOTPLUG;
 977                         break;
 978                 default:
 979                         return true;
 980                 }
 981         } else {
 982                 switch (port->port) {
 983                 case PORT_B:
 984                         bit = SDE_PORTB_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_C:
 987                         bit = SDE_PORTC_HOTPLUG_CPT;
 988                         break;
 989                 case PORT_D:
 990                         bit = SDE_PORTD_HOTPLUG_CPT;
 991                         break;
 992                 default:
 993                         return true;
 994                 }
 995         }
 996
 997         return I915_READ(SDEISR) & bit;
 998 }
 999
1000 static const char *state_string(bool enabled)
1001 {
1002         return enabled ? "on" : "off";
1003 }
1004
1005 /* Only for pre-ILK configs */
1006 void assert_pll(struct drm_i915_private *dev_priv,
1007                 enum pipe pipe, bool state)
1008 {
1009         int reg;
1010         u32 val;
1011         bool cur_state;
1012
1013         reg = DPLL(pipe);
1014         val = I915_READ(reg);
1015         cur_state = !!(val & DPLL_VCO_ENABLE);
1016         WARN(cur_state != state,
1017              "PLL state assertion failure (expected %s, current %s)\n",
1018              state_string(state), state_string(cur_state));
1019 }
1020
1021 /* XXX: the dsi pll is shared between MIPI DSI ports */
1022 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1023 {
1024         u32 val;
1025         bool cur_state;
1026
1027         mutex_lock(&dev_priv->dpio_lock);
1028         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1029         mutex_unlock(&dev_priv->dpio_lock);
1030
1031         cur_state = val & DSI_PLL_VCO_EN;
1032         WARN(cur_state != state,
1033              "DSI PLL state assertion failure (expected %s, current %s)\n",
1034              state_string(state), state_string(cur_state));
1035 }
1036 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1037 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1038
1039 struct intel_shared_dpll *
1040 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1041 {
1042         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1043
1044         if (crtc->config.shared_dpll < 0)
1045                 return NULL;
1046
1047         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1048 }
1049
1050 /* For ILK+ */
1051 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1052                         struct intel_shared_dpll *pll,
1053                         bool state)
1054 {
1055         bool cur_state;
1056         struct intel_dpll_hw_state hw_state;
1057
1058         if (HAS_PCH_LPT(dev_priv->dev)) {
1059                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1060                 return;
1061         }
1062
1063         if (WARN (!pll,
1064                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1065                 return;
1066
1067         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1068         WARN(cur_state != state,
1069              "%s assertion failure (expected %s, current %s)\n",
1070              pll->name, state_string(state), state_string(cur_state));
1071 }
1072
1073 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1074                           enum pipe pipe, bool state)
1075 {
1076         int reg;
1077         u32 val;
1078         bool cur_state;
1079         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1080                                                                       pipe);
1081
1082         if (HAS_DDI(dev_priv->dev)) {
1083                 /* DDI does not have a specific FDI_TX register */
1084                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1085                 val = I915_READ(reg);
1086                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1087         } else {
1088                 reg = FDI_TX_CTL(pipe);
1089                 val = I915_READ(reg);
1090                 cur_state = !!(val & FDI_TX_ENABLE);
1091         }
1092         WARN(cur_state != state,
1093              "FDI TX state assertion failure (expected %s, current %s)\n",
1094              state_string(state), state_string(cur_state));
1095 }
1096 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1097 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1098
1099 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1100                           enum pipe pipe, bool state)
1101 {
1102         int reg;
1103         u32 val;
1104         bool cur_state;
1105
1106         reg = FDI_RX_CTL(pipe);
1107         val = I915_READ(reg);
1108         cur_state = !!(val & FDI_RX_ENABLE);
1109         WARN(cur_state != state,
1110              "FDI RX state assertion failure (expected %s, current %s)\n",
1111              state_string(state), state_string(cur_state));
1112 }
1113 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1114 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1115
1116 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1117                                       enum pipe pipe)
1118 {
1119         int reg;
1120         u32 val;
1121
1122         /* ILK FDI PLL is always enabled */
1123         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1124                 return;
1125
1126         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1127         if (HAS_DDI(dev_priv->dev))
1128                 return;
1129
1130         reg = FDI_TX_CTL(pipe);
1131         val = I915_READ(reg);
1132         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1133 }
1134
1135 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1136                        enum pipe pipe, bool state)
1137 {
1138         int reg;
1139         u32 val;
1140         bool cur_state;
1141
1142         reg = FDI_RX_CTL(pipe);
1143         val = I915_READ(reg);
1144         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1145         WARN(cur_state != state,
1146              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1147              state_string(state), state_string(cur_state));
1148 }
1149
1150 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1151                                   enum pipe pipe)
1152 {
1153         int pp_reg, lvds_reg;
1154         u32 val;
1155         enum pipe panel_pipe = PIPE_A;
1156         bool locked = true;
1157
1158         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1159                 pp_reg = PCH_PP_CONTROL;
1160                 lvds_reg = PCH_LVDS;
1161         } else {
1162                 pp_reg = PP_CONTROL;
1163                 lvds_reg = LVDS;
1164         }
1165
1166         val = I915_READ(pp_reg);
1167         if (!(val & PANEL_POWER_ON) ||
1168             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1169                 locked = false;
1170
1171         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1172                 panel_pipe = PIPE_B;
1173
1174         WARN(panel_pipe == pipe && locked,
1175              "panel assertion failure, pipe %c regs locked\n",
1176              pipe_name(pipe));
1177 }
1178
1179 static void assert_cursor(struct drm_i915_private *dev_priv,
1180                           enum pipe pipe, bool state)
1181 {
1182         struct drm_device *dev = dev_priv->dev;
1183         bool cur_state;
1184
1185         if (IS_845G(dev) || IS_I865G(dev))
1186                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1187         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1188                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1189         else
1190                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1191
1192         WARN(cur_state != state,
1193              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1194              pipe_name(pipe), state_string(state), state_string(cur_state));
1195 }
1196 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1197 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1198
1199 void assert_pipe(struct drm_i915_private *dev_priv,
1200                  enum pipe pipe, bool state)
1201 {
1202         int reg;
1203         u32 val;
1204         bool cur_state;
1205         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1206                                                                       pipe);
1207
1208         /* if we need the pipe A quirk it must be always on */
1209         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1210                 state = true;
1211
1212         if (!intel_display_power_enabled(dev_priv,
1213                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1214                 cur_state = false;
1215         } else {
1216                 reg = PIPECONF(cpu_transcoder);
1217                 val = I915_READ(reg);
1218                 cur_state = !!(val & PIPECONF_ENABLE);
1219         }
1220
1221         WARN(cur_state != state,
1222              "pipe %c assertion failure (expected %s, current %s)\n",
1223              pipe_name(pipe), state_string(state), state_string(cur_state));
1224 }
1225
1226 static void assert_plane(struct drm_i915_private *dev_priv,
1227                          enum plane plane, bool state)
1228 {
1229         int reg;
1230         u32 val;
1231         bool cur_state;
1232
1233         reg = DSPCNTR(plane);
1234         val = I915_READ(reg);
1235         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1236         WARN(cur_state != state,
1237              "plane %c assertion failure (expected %s, current %s)\n",
1238              plane_name(plane), state_string(state), state_string(cur_state));
1239 }
1240
1241 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1242 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1243
1244 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1245                                    enum pipe pipe)
1246 {
1247         struct drm_device *dev = dev_priv->dev;
1248         int reg, i;
1249         u32 val;
1250         int cur_pipe;
1251
1252         /* Primary planes are fixed to pipes on gen4+ */
1253         if (INTEL_INFO(dev)->gen >= 4) {
1254                 reg = DSPCNTR(pipe);
1255                 val = I915_READ(reg);
1256                 WARN(val & DISPLAY_PLANE_ENABLE,
1257                      "plane %c assertion failure, should be disabled but not\n",
1258                      plane_name(pipe));
1259                 return;
1260         }
1261
1262         /* Need to check both planes against the pipe */
1263         for_each_pipe(i) {
1264                 reg = DSPCNTR(i);
1265                 val = I915_READ(reg);
1266                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1267                         DISPPLANE_SEL_PIPE_SHIFT;
1268                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1269                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1270                      plane_name(i), pipe_name(pipe));
1271         }
1272 }
1273
1274 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1275                                     enum pipe pipe)
1276 {
1277         struct drm_device *dev = dev_priv->dev;
1278         int reg, sprite;
1279         u32 val;
1280
1281         if (IS_VALLEYVIEW(dev)) {
1282                 for_each_sprite(pipe, sprite) {
1283                         reg = SPCNTR(pipe, sprite);
1284                         val = I915_READ(reg);
1285                         WARN(val & SP_ENABLE,
1286                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1287                              sprite_name(pipe, sprite), pipe_name(pipe));
1288                 }
1289         } else if (INTEL_INFO(dev)->gen >= 7) {
1290                 reg = SPRCTL(pipe);
1291                 val = I915_READ(reg);
1292                 WARN(val & SPRITE_ENABLE,
1293                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294                      plane_name(pipe), pipe_name(pipe));
1295         } else if (INTEL_INFO(dev)->gen >= 5) {
1296                 reg = DVSCNTR(pipe);
1297                 val = I915_READ(reg);
1298                 WARN(val & DVS_ENABLE,
1299                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1300                      plane_name(pipe), pipe_name(pipe));
1301         }
1302 }
1303
1304 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1305 {
1306         u32 val;
1307         bool enabled;
1308
1309         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1310
1311         val = I915_READ(PCH_DREF_CONTROL);
1312         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1313                             DREF_SUPERSPREAD_SOURCE_MASK));
1314         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1315 }
1316
1317 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1318                                            enum pipe pipe)
1319 {
1320         int reg;
1321         u32 val;
1322         bool enabled;
1323
1324         reg = PCH_TRANSCONF(pipe);
1325         val = I915_READ(reg);
1326         enabled = !!(val & TRANS_ENABLE);
1327         WARN(enabled,
1328              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329              pipe_name(pipe));
1330 }
1331
1332 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1333                             enum pipe pipe, u32 port_sel, u32 val)
1334 {
1335         if ((val & DP_PORT_EN) == 0)
1336                 return false;
1337
1338         if (HAS_PCH_CPT(dev_priv->dev)) {
1339                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1340                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1341                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1342                         return false;
1343         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1344                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1345                         return false;
1346         } else {
1347                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1348                         return false;
1349         }
1350         return true;
1351 }
1352
1353 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1354                               enum pipe pipe, u32 val)
1355 {
1356         if ((val & SDVO_ENABLE) == 0)
1357                 return false;
1358
1359         if (HAS_PCH_CPT(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1361                         return false;
1362         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1363                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1364                         return false;
1365         } else {
1366                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1367                         return false;
1368         }
1369         return true;
1370 }
1371
1372 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1373                               enum pipe pipe, u32 val)
1374 {
1375         if ((val & LVDS_PORT_EN) == 0)
1376                 return false;
1377
1378         if (HAS_PCH_CPT(dev_priv->dev)) {
1379                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1380                         return false;
1381         } else {
1382                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1383                         return false;
1384         }
1385         return true;
1386 }
1387
1388 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1389                               enum pipe pipe, u32 val)
1390 {
1391         if ((val & ADPA_DAC_ENABLE) == 0)
1392                 return false;
1393         if (HAS_PCH_CPT(dev_priv->dev)) {
1394                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1404                                    enum pipe pipe, int reg, u32 port_sel)
1405 {
1406         u32 val = I915_READ(reg);
1407         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1408              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1409              reg, pipe_name(pipe));
1410
1411         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1412              && (val & DP_PIPEB_SELECT),
1413              "IBX PCH dp port still using transcoder B\n");
1414 }
1415
1416 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1417                                      enum pipe pipe, int reg)
1418 {
1419         u32 val = I915_READ(reg);
1420         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1421              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1422              reg, pipe_name(pipe));
1423
1424         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1425              && (val & SDVO_PIPE_B_SELECT),
1426              "IBX PCH hdmi port still using transcoder B\n");
1427 }
1428
1429 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1430                                       enum pipe pipe)
1431 {
1432         int reg;
1433         u32 val;
1434
1435         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1436         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1437         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1438
1439         reg = PCH_ADPA;
1440         val = I915_READ(reg);
1441         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1442              "PCH VGA enabled on transcoder %c, should be disabled\n",
1443              pipe_name(pipe));
1444
1445         reg = PCH_LVDS;
1446         val = I915_READ(reg);
1447         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1448              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1449              pipe_name(pipe));
1450
1451         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1452         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1453         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1454 }
1455
1456 static void intel_init_dpio(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459
1460         if (!IS_VALLEYVIEW(dev))
1461                 return;
1462
1463         /*
1464          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1465          * CHV x1 PHY (DP/HDMI D)
1466          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1467          */
1468         if (IS_CHERRYVIEW(dev)) {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1470                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1471         } else {
1472                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1473         }
1474 }
1475
1476 static void intel_reset_dpio(struct drm_device *dev)
1477 {
1478         struct drm_i915_private *dev_priv = dev->dev_private;
1479
1480         if (!IS_VALLEYVIEW(dev))
1481                 return;
1482
1483         /*
1484          * Enable the CRI clock source so we can get at the display and the
1485          * reference clock for VGA hotplug / manual detection.
1486          */
1487         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1488                    DPLL_REFA_CLK_ENABLE_VLV |
1489                    DPLL_INTEGRATED_CRI_CLK_VLV);
1490
1491         if (IS_CHERRYVIEW(dev)) {
1492                 enum dpio_phy phy;
1493                 u32 val;
1494
1495                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1496                         /* Poll for phypwrgood signal */
1497                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1498                                                 PHY_POWERGOOD(phy), 1))
1499                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1500
1501                         /*
1502                          * Deassert common lane reset for PHY.
1503                          *
1504                          * This should only be done on init and resume from S3
1505                          * with both PLLs disabled, or we risk losing DPIO and
1506                          * PLL synchronization.
1507                          */
1508                         val = I915_READ(DISPLAY_PHY_CONTROL);
1509                         I915_WRITE(DISPLAY_PHY_CONTROL,
1510                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1511                 }
1512
1513         } else {
1514                 /*
1515                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1516                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1517                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1518                  *   b. The other bits such as sfr settings / modesel may all
1519                  *      be set to 0.
1520                  *
1521                  * This should only be done on init and resume from S3 with
1522                  * both PLLs disabled, or we risk losing DPIO and PLL
1523                  * synchronization.
1524                  */
1525                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1526         }
1527 }
1528
1529 static void vlv_enable_pll(struct intel_crtc *crtc)
1530 {
1531         struct drm_device *dev = crtc->base.dev;
1532         struct drm_i915_private *dev_priv = dev->dev_private;
1533         int reg = DPLL(crtc->pipe);
1534         u32 dpll = crtc->config.dpll_hw_state.dpll;
1535
1536         assert_pipe_disabled(dev_priv, crtc->pipe);
1537
1538         /* No really, not for ILK+ */
1539         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1540
1541         /* PLL is protected by panel, make sure we can write it */
1542         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1543                 assert_panel_unlocked(dev_priv, crtc->pipe);
1544
1545         I915_WRITE(reg, dpll);
1546         POSTING_READ(reg);
1547         udelay(150);
1548
1549         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1550                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1551
1552         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1553         POSTING_READ(DPLL_MD(crtc->pipe));
1554
1555         /* We do this three times for luck */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562         I915_WRITE(reg, dpll);
1563         POSTING_READ(reg);
1564         udelay(150); /* wait for warmup */
1565 }
1566
1567 static void chv_enable_pll(struct intel_crtc *crtc)
1568 {
1569         struct drm_device *dev = crtc->base.dev;
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         int pipe = crtc->pipe;
1572         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1573         int dpll = DPLL(crtc->pipe);
1574         u32 tmp;
1575
1576         assert_pipe_disabled(dev_priv, crtc->pipe);
1577
1578         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1579
1580         mutex_lock(&dev_priv->dpio_lock);
1581
1582         /* Enable back the 10bit clock to display controller */
1583         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1584         tmp |= DPIO_DCLKP_EN;
1585         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1586
1587         /*
1588          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1589          */
1590         udelay(1);
1591
1592         /* Enable PLL */
1593         tmp = I915_READ(dpll);
1594         tmp |= DPLL_VCO_ENABLE;
1595         I915_WRITE(dpll, tmp);
1596
1597         /* Check PLL is locked */
1598         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1599                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1600
1601         /* Deassert soft data lane reset*/
1602         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1603         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1604         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1605
1606
1607         mutex_unlock(&dev_priv->dpio_lock);
1608 }
1609
1610 static void i9xx_enable_pll(struct intel_crtc *crtc)
1611 {
1612         struct drm_device *dev = crtc->base.dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614         int reg = DPLL(crtc->pipe);
1615         u32 dpll = crtc->config.dpll_hw_state.dpll;
1616
1617         assert_pipe_disabled(dev_priv, crtc->pipe);
1618
1619         /* No really, not for ILK+ */
1620         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1621
1622         /* PLL is protected by panel, make sure we can write it */
1623         if (IS_MOBILE(dev) && !IS_I830(dev))
1624                 assert_panel_unlocked(dev_priv, crtc->pipe);
1625
1626         I915_WRITE(reg, dpll);
1627
1628         /* Wait for the clocks to stabilize. */
1629         POSTING_READ(reg);
1630         udelay(150);
1631
1632         if (INTEL_INFO(dev)->gen >= 4) {
1633                 I915_WRITE(DPLL_MD(crtc->pipe),
1634                            crtc->config.dpll_hw_state.dpll_md);
1635         } else {
1636                 /* The pixel multiplier can only be updated once the
1637                  * DPLL is enabled and the clocks are stable.
1638                  *
1639                  * So write it again.
1640                  */
1641                 I915_WRITE(reg, dpll);
1642         }
1643
1644         /* We do this three times for luck */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651         I915_WRITE(reg, dpll);
1652         POSTING_READ(reg);
1653         udelay(150); /* wait for warmup */
1654 }
1655
1656 /**
1657  * i9xx_disable_pll - disable a PLL
1658  * @dev_priv: i915 private structure
1659  * @pipe: pipe PLL to disable
1660  *
1661  * Disable the PLL for @pipe, making sure the pipe is off first.
1662  *
1663  * Note!  This is for pre-ILK only.
1664  */
1665 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1666 {
1667         /* Don't disable pipe A or pipe A PLLs if needed */
1668         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1669                 return;
1670
1671         /* Make sure the pipe isn't still relying on us */
1672         assert_pipe_disabled(dev_priv, pipe);
1673
1674         I915_WRITE(DPLL(pipe), 0);
1675         POSTING_READ(DPLL(pipe));
1676 }
1677
1678 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1679 {
1680         u32 val = 0;
1681
1682         /* Make sure the pipe isn't still relying on us */
1683         assert_pipe_disabled(dev_priv, pipe);
1684
1685         /*
1686          * Leave integrated clock source and reference clock enabled for pipe B.
1687          * The latter is needed for VGA hotplug / manual detection.
1688          */
1689         if (pipe == PIPE_B)
1690                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1691         I915_WRITE(DPLL(pipe), val);
1692         POSTING_READ(DPLL(pipe));
1693
1694 }
1695
1696 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1697 {
1698         int dpll = DPLL(pipe);
1699         u32 val;
1700
1701         /* Set PLL en = 0 */
1702         val = I915_READ(dpll);
1703         val &= ~DPLL_VCO_ENABLE;
1704         I915_WRITE(dpll, val);
1705
1706 }
1707
1708 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1709                 struct intel_digital_port *dport)
1710 {
1711         u32 port_mask;
1712         int dpll_reg;
1713
1714         switch (dport->port) {
1715         case PORT_B:
1716                 port_mask = DPLL_PORTB_READY_MASK;
1717                 dpll_reg = DPLL(0);
1718                 break;
1719         case PORT_C:
1720                 port_mask = DPLL_PORTC_READY_MASK;
1721                 dpll_reg = DPLL(0);
1722                 break;
1723         case PORT_D:
1724                 port_mask = DPLL_PORTD_READY_MASK;
1725                 dpll_reg = DPIO_PHY_STATUS;
1726                 break;
1727         default:
1728                 BUG();
1729         }
1730
1731         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1732                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1733                      port_name(dport->port), I915_READ(dpll_reg));
1734 }
1735
1736 /**
1737  * ironlake_enable_shared_dpll - enable PCH PLL
1738  * @dev_priv: i915 private structure
1739  * @pipe: pipe PLL to enable
1740  *
1741  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1742  * drives the transcoder clock.
1743  */
1744 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1745 {
1746         struct drm_device *dev = crtc->base.dev;
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1749
1750         /* PCH PLLs only available on ILK, SNB and IVB */
1751         BUG_ON(INTEL_INFO(dev)->gen < 5);
1752         if (WARN_ON(pll == NULL))
1753                 return;
1754
1755         if (WARN_ON(pll->refcount == 0))
1756                 return;
1757
1758         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1759                       pll->name, pll->active, pll->on,
1760                       crtc->base.base.id);
1761
1762         if (pll->active++) {
1763                 WARN_ON(!pll->on);
1764                 assert_shared_dpll_enabled(dev_priv, pll);
1765                 return;
1766         }
1767         WARN_ON(pll->on);
1768
1769         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1770         pll->enable(dev_priv, pll);
1771         pll->on = true;
1772 }
1773
1774 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1775 {
1776         struct drm_device *dev = crtc->base.dev;
1777         struct drm_i915_private *dev_priv = dev->dev_private;
1778         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1779
1780         /* PCH only available on ILK+ */
1781         BUG_ON(INTEL_INFO(dev)->gen < 5);
1782         if (WARN_ON(pll == NULL))
1783                return;
1784
1785         if (WARN_ON(pll->refcount == 0))
1786                 return;
1787
1788         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1789                       pll->name, pll->active, pll->on,
1790                       crtc->base.base.id);
1791
1792         if (WARN_ON(pll->active == 0)) {
1793                 assert_shared_dpll_disabled(dev_priv, pll);
1794                 return;
1795         }
1796
1797         assert_shared_dpll_enabled(dev_priv, pll);
1798         WARN_ON(!pll->on);
1799         if (--pll->active)
1800                 return;
1801
1802         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1803         pll->disable(dev_priv, pll);
1804         pll->on = false;
1805 }
1806
1807 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1808                                            enum pipe pipe)
1809 {
1810         struct drm_device *dev = dev_priv->dev;
1811         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1813         uint32_t reg, val, pipeconf_val;
1814
1815         /* PCH only available on ILK+ */
1816         BUG_ON(INTEL_INFO(dev)->gen < 5);
1817
1818         /* Make sure PCH DPLL is enabled */
1819         assert_shared_dpll_enabled(dev_priv,
1820                                    intel_crtc_to_shared_dpll(intel_crtc));
1821
1822         /* FDI must be feeding us bits for PCH ports */
1823         assert_fdi_tx_enabled(dev_priv, pipe);
1824         assert_fdi_rx_enabled(dev_priv, pipe);
1825
1826         if (HAS_PCH_CPT(dev)) {
1827                 /* Workaround: Set the timing override bit before enabling the
1828                  * pch transcoder. */
1829                 reg = TRANS_CHICKEN2(pipe);
1830                 val = I915_READ(reg);
1831                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1832                 I915_WRITE(reg, val);
1833         }
1834
1835         reg = PCH_TRANSCONF(pipe);
1836         val = I915_READ(reg);
1837         pipeconf_val = I915_READ(PIPECONF(pipe));
1838
1839         if (HAS_PCH_IBX(dev_priv->dev)) {
1840                 /*
1841                  * make the BPC in transcoder be consistent with
1842                  * that in pipeconf reg.
1843                  */
1844                 val &= ~PIPECONF_BPC_MASK;
1845                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1846         }
1847
1848         val &= ~TRANS_INTERLACE_MASK;
1849         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1850                 if (HAS_PCH_IBX(dev_priv->dev) &&
1851                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1852                         val |= TRANS_LEGACY_INTERLACED_ILK;
1853                 else
1854                         val |= TRANS_INTERLACED;
1855         else
1856                 val |= TRANS_PROGRESSIVE;
1857
1858         I915_WRITE(reg, val | TRANS_ENABLE);
1859         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1860                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1861 }
1862
1863 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1864                                       enum transcoder cpu_transcoder)
1865 {
1866         u32 val, pipeconf_val;
1867
1868         /* PCH only available on ILK+ */
1869         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1870
1871         /* FDI must be feeding us bits for PCH ports */
1872         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1873         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1874
1875         /* Workaround: set timing override bit. */
1876         val = I915_READ(_TRANSA_CHICKEN2);
1877         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1878         I915_WRITE(_TRANSA_CHICKEN2, val);
1879
1880         val = TRANS_ENABLE;
1881         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1882
1883         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1884             PIPECONF_INTERLACED_ILK)
1885                 val |= TRANS_INTERLACED;
1886         else
1887                 val |= TRANS_PROGRESSIVE;
1888
1889         I915_WRITE(LPT_TRANSCONF, val);
1890         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1891                 DRM_ERROR("Failed to enable PCH transcoder\n");
1892 }
1893
1894 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1895                                             enum pipe pipe)
1896 {
1897         struct drm_device *dev = dev_priv->dev;
1898         uint32_t reg, val;
1899
1900         /* FDI relies on the transcoder */
1901         assert_fdi_tx_disabled(dev_priv, pipe);
1902         assert_fdi_rx_disabled(dev_priv, pipe);
1903
1904         /* Ports must be off as well */
1905         assert_pch_ports_disabled(dev_priv, pipe);
1906
1907         reg = PCH_TRANSCONF(pipe);
1908         val = I915_READ(reg);
1909         val &= ~TRANS_ENABLE;
1910         I915_WRITE(reg, val);
1911         /* wait for PCH transcoder off, transcoder state */
1912         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1913                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1914
1915         if (!HAS_PCH_IBX(dev)) {
1916                 /* Workaround: Clear the timing override chicken bit again. */
1917                 reg = TRANS_CHICKEN2(pipe);
1918                 val = I915_READ(reg);
1919                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1920                 I915_WRITE(reg, val);
1921         }
1922 }
1923
1924 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1925 {
1926         u32 val;
1927
1928         val = I915_READ(LPT_TRANSCONF);
1929         val &= ~TRANS_ENABLE;
1930         I915_WRITE(LPT_TRANSCONF, val);
1931         /* wait for PCH transcoder off, transcoder state */
1932         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1933                 DRM_ERROR("Failed to disable PCH transcoder\n");
1934
1935         /* Workaround: clear timing override bit. */
1936         val = I915_READ(_TRANSA_CHICKEN2);
1937         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1938         I915_WRITE(_TRANSA_CHICKEN2, val);
1939 }
1940
1941 /**
1942  * intel_enable_pipe - enable a pipe, asserting requirements
1943  * @crtc: crtc responsible for the pipe
1944  *
1945  * Enable @crtc's pipe, making sure that various hardware specific requirements
1946  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1947  */
1948 static void intel_enable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_device *dev = crtc->base.dev;
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952         enum pipe pipe = crtc->pipe;
1953         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1954                                                                       pipe);
1955         enum pipe pch_transcoder;
1956         int reg;
1957         u32 val;
1958
1959         assert_planes_disabled(dev_priv, pipe);
1960         assert_cursor_disabled(dev_priv, pipe);
1961         assert_sprites_disabled(dev_priv, pipe);
1962
1963         if (HAS_PCH_LPT(dev_priv->dev))
1964                 pch_transcoder = TRANSCODER_A;
1965         else
1966                 pch_transcoder = pipe;
1967
1968         /*
1969          * A pipe without a PLL won't actually be able to drive bits from
1970          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1971          * need the check.
1972          */
1973         if (!HAS_PCH_SPLIT(dev_priv->dev))
1974                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1975                         assert_dsi_pll_enabled(dev_priv);
1976                 else
1977                         assert_pll_enabled(dev_priv, pipe);
1978         else {
1979                 if (crtc->config.has_pch_encoder) {
1980                         /* if driving the PCH, we need FDI enabled */
1981                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1982                         assert_fdi_tx_pll_enabled(dev_priv,
1983                                                   (enum pipe) cpu_transcoder);
1984                 }
1985                 /* FIXME: assert CPU port conditions for SNB+ */
1986         }
1987
1988         reg = PIPECONF(cpu_transcoder);
1989         val = I915_READ(reg);
1990         if (val & PIPECONF_ENABLE) {
1991                 WARN_ON(!(pipe == PIPE_A &&
1992                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1993                 return;
1994         }
1995
1996         I915_WRITE(reg, val | PIPECONF_ENABLE);
1997         POSTING_READ(reg);
1998 }
1999
2000 /**
2001  * intel_disable_pipe - disable a pipe, asserting requirements
2002  * @dev_priv: i915 private structure
2003  * @pipe: pipe to disable
2004  *
2005  * Disable @pipe, making sure that various hardware specific requirements
2006  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2007  *
2008  * @pipe should be %PIPE_A or %PIPE_B.
2009  *
2010  * Will wait until the pipe has shut down before returning.
2011  */
2012 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2013                                enum pipe pipe)
2014 {
2015         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2016                                                                       pipe);
2017         int reg;
2018         u32 val;
2019
2020         /*
2021          * Make sure planes won't keep trying to pump pixels to us,
2022          * or we might hang the display.
2023          */
2024         assert_planes_disabled(dev_priv, pipe);
2025         assert_cursor_disabled(dev_priv, pipe);
2026         assert_sprites_disabled(dev_priv, pipe);
2027
2028         /* Don't disable pipe A or pipe A PLLs if needed */
2029         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2030                 return;
2031
2032         reg = PIPECONF(cpu_transcoder);
2033         val = I915_READ(reg);
2034         if ((val & PIPECONF_ENABLE) == 0)
2035                 return;
2036
2037         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2038         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2039 }
2040
2041 /*
2042  * Plane regs are double buffered, going from enabled->disabled needs a
2043  * trigger in order to latch.  The display address reg provides this.
2044  */
2045 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2046                                enum plane plane)
2047 {
2048         struct drm_device *dev = dev_priv->dev;
2049         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2050
2051         I915_WRITE(reg, I915_READ(reg));
2052         POSTING_READ(reg);
2053 }
2054
2055 /**
2056  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2057  * @dev_priv: i915 private structure
2058  * @plane: plane to enable
2059  * @pipe: pipe being fed
2060  *
2061  * Enable @plane on @pipe, making sure that @pipe is running first.
2062  */
2063 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2064                                           enum plane plane, enum pipe pipe)
2065 {
2066         struct intel_crtc *intel_crtc =
2067                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2068         int reg;
2069         u32 val;
2070
2071         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2072         assert_pipe_enabled(dev_priv, pipe);
2073
2074         if (intel_crtc->primary_enabled)
2075                 return;
2076
2077         intel_crtc->primary_enabled = true;
2078
2079         reg = DSPCNTR(plane);
2080         val = I915_READ(reg);
2081         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2082
2083         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2084         intel_flush_primary_plane(dev_priv, plane);
2085         intel_wait_for_vblank(dev_priv->dev, pipe);
2086 }
2087
2088 /**
2089  * intel_disable_primary_hw_plane - disable the primary hardware plane
2090  * @dev_priv: i915 private structure
2091  * @plane: plane to disable
2092  * @pipe: pipe consuming the data
2093  *
2094  * Disable @plane; should be an independent operation.
2095  */
2096 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2097                                            enum plane plane, enum pipe pipe)
2098 {
2099         struct intel_crtc *intel_crtc =
2100                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2101         int reg;
2102         u32 val;
2103
2104         if (!intel_crtc->primary_enabled)
2105                 return;
2106
2107         intel_crtc->primary_enabled = false;
2108
2109         reg = DSPCNTR(plane);
2110         val = I915_READ(reg);
2111         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2112
2113         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2114         intel_flush_primary_plane(dev_priv, plane);
2115         intel_wait_for_vblank(dev_priv->dev, pipe);
2116 }
2117
2118 static bool need_vtd_wa(struct drm_device *dev)
2119 {
2120 #ifdef CONFIG_INTEL_IOMMU
2121         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2122                 return true;
2123 #endif
2124         return false;
2125 }
2126
2127 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2128 {
2129         int tile_height;
2130
2131         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2132         return ALIGN(height, tile_height);
2133 }
2134
2135 int
2136 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2137                            struct drm_i915_gem_object *obj,
2138                            struct intel_ring_buffer *pipelined)
2139 {
2140         struct drm_i915_private *dev_priv = dev->dev_private;
2141         u32 alignment;
2142         int ret;
2143
2144         switch (obj->tiling_mode) {
2145         case I915_TILING_NONE:
2146                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2147                         alignment = 128 * 1024;
2148                 else if (INTEL_INFO(dev)->gen >= 4)
2149                         alignment = 4 * 1024;
2150                 else
2151                         alignment = 64 * 1024;
2152                 break;
2153         case I915_TILING_X:
2154                 /* pin() will align the object as required by fence */
2155                 alignment = 0;
2156                 break;
2157         case I915_TILING_Y:
2158                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2159                 return -EINVAL;
2160         default:
2161                 BUG();
2162         }
2163
2164         /* Note that the w/a also requires 64 PTE of padding following the
2165          * bo. We currently fill all unused PTE with the shadow page and so
2166          * we should always have valid PTE following the scanout preventing
2167          * the VT-d warning.
2168          */
2169         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2170                 alignment = 256 * 1024;
2171
2172         dev_priv->mm.interruptible = false;
2173         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2174         if (ret)
2175                 goto err_interruptible;
2176
2177         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2178          * fence, whereas 965+ only requires a fence if using
2179          * framebuffer compression.  For simplicity, we always install
2180          * a fence as the cost is not that onerous.
2181          */
2182         ret = i915_gem_object_get_fence(obj);
2183         if (ret)
2184                 goto err_unpin;
2185
2186         i915_gem_object_pin_fence(obj);
2187
2188         dev_priv->mm.interruptible = true;
2189         return 0;
2190
2191 err_unpin:
2192         i915_gem_object_unpin_from_display_plane(obj);
2193 err_interruptible:
2194         dev_priv->mm.interruptible = true;
2195         return ret;
2196 }
2197
2198 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2199 {
2200         i915_gem_object_unpin_fence(obj);
2201         i915_gem_object_unpin_from_display_plane(obj);
2202 }
2203
2204 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2205  * is assumed to be a power-of-two. */
2206 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2207                                              unsigned int tiling_mode,
2208                                              unsigned int cpp,
2209                                              unsigned int pitch)
2210 {
2211         if (tiling_mode != I915_TILING_NONE) {
2212                 unsigned int tile_rows, tiles;
2213
2214                 tile_rows = *y / 8;
2215                 *y %= 8;
2216
2217                 tiles = *x / (512/cpp);
2218                 *x %= 512/cpp;
2219
2220                 return tile_rows * pitch * 8 + tiles * 4096;
2221         } else {
2222                 unsigned int offset;
2223
2224                 offset = *y * pitch + *x * cpp;
2225                 *y = 0;
2226                 *x = (offset & 4095) / cpp;
2227                 return offset & -4096;
2228         }
2229 }
2230
2231 int intel_format_to_fourcc(int format)
2232 {
2233         switch (format) {
2234         case DISPPLANE_8BPP:
2235                 return DRM_FORMAT_C8;
2236         case DISPPLANE_BGRX555:
2237                 return DRM_FORMAT_XRGB1555;
2238         case DISPPLANE_BGRX565:
2239                 return DRM_FORMAT_RGB565;
2240         default:
2241         case DISPPLANE_BGRX888:
2242                 return DRM_FORMAT_XRGB8888;
2243         case DISPPLANE_RGBX888:
2244                 return DRM_FORMAT_XBGR8888;
2245         case DISPPLANE_BGRX101010:
2246                 return DRM_FORMAT_XRGB2101010;
2247         case DISPPLANE_RGBX101010:
2248                 return DRM_FORMAT_XBGR2101010;
2249         }
2250 }
2251
2252 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2253                                   struct intel_plane_config *plane_config)
2254 {
2255         struct drm_device *dev = crtc->base.dev;
2256         struct drm_i915_gem_object *obj = NULL;
2257         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2258         u32 base = plane_config->base;
2259
2260         if (plane_config->size == 0)
2261                 return false;
2262
2263         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2264                                                              plane_config->size);
2265         if (!obj)
2266                 return false;
2267
2268         if (plane_config->tiled) {
2269                 obj->tiling_mode = I915_TILING_X;
2270                 obj->stride = crtc->base.primary->fb->pitches[0];
2271         }
2272
2273         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2274         mode_cmd.width = crtc->base.primary->fb->width;
2275         mode_cmd.height = crtc->base.primary->fb->height;
2276         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2277
2278         mutex_lock(&dev->struct_mutex);
2279
2280         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2281                                    &mode_cmd, obj)) {
2282                 DRM_DEBUG_KMS("intel fb init failed\n");
2283                 goto out_unref_obj;
2284         }
2285
2286         mutex_unlock(&dev->struct_mutex);
2287
2288         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2289         return true;
2290
2291 out_unref_obj:
2292         drm_gem_object_unreference(&obj->base);
2293         mutex_unlock(&dev->struct_mutex);
2294         return false;
2295 }
2296
2297 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2298                                  struct intel_plane_config *plane_config)
2299 {
2300         struct drm_device *dev = intel_crtc->base.dev;
2301         struct drm_crtc *c;
2302         struct intel_crtc *i;
2303         struct intel_framebuffer *fb;
2304
2305         if (!intel_crtc->base.primary->fb)
2306                 return;
2307
2308         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2309                 return;
2310
2311         kfree(intel_crtc->base.primary->fb);
2312         intel_crtc->base.primary->fb = NULL;
2313
2314         /*
2315          * Failed to alloc the obj, check to see if we should share
2316          * an fb with another CRTC instead
2317          */
2318         for_each_crtc(dev, c) {
2319                 i = to_intel_crtc(c);
2320
2321                 if (c == &intel_crtc->base)
2322                         continue;
2323
2324                 if (!i->active || !c->primary->fb)
2325                         continue;
2326
2327                 fb = to_intel_framebuffer(c->primary->fb);
2328                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2329                         drm_framebuffer_reference(c->primary->fb);
2330                         intel_crtc->base.primary->fb = c->primary->fb;
2331                         break;
2332                 }
2333         }
2334 }
2335
2336 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2337                                       struct drm_framebuffer *fb,
2338                                       int x, int y)
2339 {
2340         struct drm_device *dev = crtc->dev;
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343         struct intel_framebuffer *intel_fb;
2344         struct drm_i915_gem_object *obj;
2345         int plane = intel_crtc->plane;
2346         unsigned long linear_offset;
2347         u32 dspcntr;
2348         u32 reg;
2349
2350         intel_fb = to_intel_framebuffer(fb);
2351         obj = intel_fb->obj;
2352
2353         reg = DSPCNTR(plane);
2354         dspcntr = I915_READ(reg);
2355         /* Mask out pixel format bits in case we change it */
2356         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2357         switch (fb->pixel_format) {
2358         case DRM_FORMAT_C8:
2359                 dspcntr |= DISPPLANE_8BPP;
2360                 break;
2361         case DRM_FORMAT_XRGB1555:
2362         case DRM_FORMAT_ARGB1555:
2363                 dspcntr |= DISPPLANE_BGRX555;
2364                 break;
2365         case DRM_FORMAT_RGB565:
2366                 dspcntr |= DISPPLANE_BGRX565;
2367                 break;
2368         case DRM_FORMAT_XRGB8888:
2369         case DRM_FORMAT_ARGB8888:
2370                 dspcntr |= DISPPLANE_BGRX888;
2371                 break;
2372         case DRM_FORMAT_XBGR8888:
2373         case DRM_FORMAT_ABGR8888:
2374                 dspcntr |= DISPPLANE_RGBX888;
2375                 break;
2376         case DRM_FORMAT_XRGB2101010:
2377         case DRM_FORMAT_ARGB2101010:
2378                 dspcntr |= DISPPLANE_BGRX101010;
2379                 break;
2380         case DRM_FORMAT_XBGR2101010:
2381         case DRM_FORMAT_ABGR2101010:
2382                 dspcntr |= DISPPLANE_RGBX101010;
2383                 break;
2384         default:
2385                 BUG();
2386         }
2387
2388         if (INTEL_INFO(dev)->gen >= 4) {
2389                 if (obj->tiling_mode != I915_TILING_NONE)
2390                         dspcntr |= DISPPLANE_TILED;
2391                 else
2392                         dspcntr &= ~DISPPLANE_TILED;
2393         }
2394
2395         if (IS_G4X(dev))
2396                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2397
2398         I915_WRITE(reg, dspcntr);
2399
2400         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2401
2402         if (INTEL_INFO(dev)->gen >= 4) {
2403                 intel_crtc->dspaddr_offset =
2404                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2405                                                        fb->bits_per_pixel / 8,
2406                                                        fb->pitches[0]);
2407                 linear_offset -= intel_crtc->dspaddr_offset;
2408         } else {
2409                 intel_crtc->dspaddr_offset = linear_offset;
2410         }
2411
2412         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2413                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2414                       fb->pitches[0]);
2415         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2416         if (INTEL_INFO(dev)->gen >= 4) {
2417                 I915_WRITE(DSPSURF(plane),
2418                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2419                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2420                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2421         } else
2422                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2423         POSTING_READ(reg);
2424 }
2425
2426 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2427                                           struct drm_framebuffer *fb,
2428                                           int x, int y)
2429 {
2430         struct drm_device *dev = crtc->dev;
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2433         struct intel_framebuffer *intel_fb;
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg;
2439
2440         intel_fb = to_intel_framebuffer(fb);
2441         obj = intel_fb->obj;
2442
2443         reg = DSPCNTR(plane);
2444         dspcntr = I915_READ(reg);
2445         /* Mask out pixel format bits in case we change it */
2446         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2447         switch (fb->pixel_format) {
2448         case DRM_FORMAT_C8:
2449                 dspcntr |= DISPPLANE_8BPP;
2450                 break;
2451         case DRM_FORMAT_RGB565:
2452                 dspcntr |= DISPPLANE_BGRX565;
2453                 break;
2454         case DRM_FORMAT_XRGB8888:
2455         case DRM_FORMAT_ARGB8888:
2456                 dspcntr |= DISPPLANE_BGRX888;
2457                 break;
2458         case DRM_FORMAT_XBGR8888:
2459         case DRM_FORMAT_ABGR8888:
2460                 dspcntr |= DISPPLANE_RGBX888;
2461                 break;
2462         case DRM_FORMAT_XRGB2101010:
2463         case DRM_FORMAT_ARGB2101010:
2464                 dspcntr |= DISPPLANE_BGRX101010;
2465                 break;
2466         case DRM_FORMAT_XBGR2101010:
2467         case DRM_FORMAT_ABGR2101010:
2468                 dspcntr |= DISPPLANE_RGBX101010;
2469                 break;
2470         default:
2471                 BUG();
2472         }
2473
2474         if (obj->tiling_mode != I915_TILING_NONE)
2475                 dspcntr |= DISPPLANE_TILED;
2476         else
2477                 dspcntr &= ~DISPPLANE_TILED;
2478
2479         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2480                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2481         else
2482                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2483
2484         I915_WRITE(reg, dspcntr);
2485
2486         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2487         intel_crtc->dspaddr_offset =
2488                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2489                                                fb->bits_per_pixel / 8,
2490                                                fb->pitches[0]);
2491         linear_offset -= intel_crtc->dspaddr_offset;
2492
2493         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2494                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2495                       fb->pitches[0]);
2496         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2497         I915_WRITE(DSPSURF(plane),
2498                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2499         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2500                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2501         } else {
2502                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2503                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2504         }
2505         POSTING_READ(reg);
2506 }
2507
2508 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2509 static int
2510 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2511                            int x, int y, enum mode_set_atomic state)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515
2516         if (dev_priv->display.disable_fbc)
2517                 dev_priv->display.disable_fbc(dev);
2518         intel_increase_pllclock(crtc);
2519
2520         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2521
2522         return 0;
2523 }
2524
2525 void intel_display_handle_reset(struct drm_device *dev)
2526 {
2527         struct drm_i915_private *dev_priv = dev->dev_private;
2528         struct drm_crtc *crtc;
2529
2530         /*
2531          * Flips in the rings have been nuked by the reset,
2532          * so complete all pending flips so that user space
2533          * will get its events and not get stuck.
2534          *
2535          * Also update the base address of all primary
2536          * planes to the the last fb to make sure we're
2537          * showing the correct fb after a reset.
2538          *
2539          * Need to make two loops over the crtcs so that we
2540          * don't try to grab a crtc mutex before the
2541          * pending_flip_queue really got woken up.
2542          */
2543
2544         for_each_crtc(dev, crtc) {
2545                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546                 enum plane plane = intel_crtc->plane;
2547
2548                 intel_prepare_page_flip(dev, plane);
2549                 intel_finish_page_flip_plane(dev, plane);
2550         }
2551
2552         for_each_crtc(dev, crtc) {
2553                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2554
2555                 mutex_lock(&crtc->mutex);
2556                 /*
2557                  * FIXME: Once we have proper support for primary planes (and
2558                  * disabling them without disabling the entire crtc) allow again
2559                  * a NULL crtc->primary->fb.
2560                  */
2561                 if (intel_crtc->active && crtc->primary->fb)
2562                         dev_priv->display.update_primary_plane(crtc,
2563                                                                crtc->primary->fb,
2564                                                                crtc->x,
2565                                                                crtc->y);
2566                 mutex_unlock(&crtc->mutex);
2567         }
2568 }
2569
2570 static int
2571 intel_finish_fb(struct drm_framebuffer *old_fb)
2572 {
2573         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2574         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2575         bool was_interruptible = dev_priv->mm.interruptible;
2576         int ret;
2577
2578         /* Big Hammer, we also need to ensure that any pending
2579          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2580          * current scanout is retired before unpinning the old
2581          * framebuffer.
2582          *
2583          * This should only fail upon a hung GPU, in which case we
2584          * can safely continue.
2585          */
2586         dev_priv->mm.interruptible = false;
2587         ret = i915_gem_object_finish_gpu(obj);
2588         dev_priv->mm.interruptible = was_interruptible;
2589
2590         return ret;
2591 }
2592
2593 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2594 {
2595         struct drm_device *dev = crtc->dev;
2596         struct drm_i915_private *dev_priv = dev->dev_private;
2597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2598         unsigned long flags;
2599         bool pending;
2600
2601         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2602             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2603                 return false;
2604
2605         spin_lock_irqsave(&dev->event_lock, flags);
2606         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2607         spin_unlock_irqrestore(&dev->event_lock, flags);
2608
2609         return pending;
2610 }
2611
2612 static int
2613 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2614                     struct drm_framebuffer *fb)
2615 {
2616         struct drm_device *dev = crtc->dev;
2617         struct drm_i915_private *dev_priv = dev->dev_private;
2618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2619         struct drm_framebuffer *old_fb;
2620         int ret;
2621
2622         if (intel_crtc_has_pending_flip(crtc)) {
2623                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2624                 return -EBUSY;
2625         }
2626
2627         /* no fb bound */
2628         if (!fb) {
2629                 DRM_ERROR("No FB bound\n");
2630                 return 0;
2631         }
2632
2633         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2634                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2635                           plane_name(intel_crtc->plane),
2636                           INTEL_INFO(dev)->num_pipes);
2637                 return -EINVAL;
2638         }
2639
2640         mutex_lock(&dev->struct_mutex);
2641         ret = intel_pin_and_fence_fb_obj(dev,
2642                                          to_intel_framebuffer(fb)->obj,
2643                                          NULL);
2644         mutex_unlock(&dev->struct_mutex);
2645         if (ret != 0) {
2646                 DRM_ERROR("pin & fence failed\n");
2647                 return ret;
2648         }
2649
2650         /*
2651          * Update pipe size and adjust fitter if needed: the reason for this is
2652          * that in compute_mode_changes we check the native mode (not the pfit
2653          * mode) to see if we can flip rather than do a full mode set. In the
2654          * fastboot case, we'll flip, but if we don't update the pipesrc and
2655          * pfit state, we'll end up with a big fb scanned out into the wrong
2656          * sized surface.
2657          *
2658          * To fix this properly, we need to hoist the checks up into
2659          * compute_mode_changes (or above), check the actual pfit state and
2660          * whether the platform allows pfit disable with pipe active, and only
2661          * then update the pipesrc and pfit state, even on the flip path.
2662          */
2663         if (i915.fastboot) {
2664                 const struct drm_display_mode *adjusted_mode =
2665                         &intel_crtc->config.adjusted_mode;
2666
2667                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2668                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2669                            (adjusted_mode->crtc_vdisplay - 1));
2670                 if (!intel_crtc->config.pch_pfit.enabled &&
2671                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2672                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2673                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2674                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2675                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2676                 }
2677                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2678                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2679         }
2680
2681         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2682
2683         old_fb = crtc->primary->fb;
2684         crtc->primary->fb = fb;
2685         crtc->x = x;
2686         crtc->y = y;
2687
2688         if (old_fb) {
2689                 if (intel_crtc->active && old_fb != fb)
2690                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2691                 mutex_lock(&dev->struct_mutex);
2692                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2693                 mutex_unlock(&dev->struct_mutex);
2694         }
2695
2696         mutex_lock(&dev->struct_mutex);
2697         intel_update_fbc(dev);
2698         intel_edp_psr_update(dev);
2699         mutex_unlock(&dev->struct_mutex);
2700
2701         return 0;
2702 }
2703
2704 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2705 {
2706         struct drm_device *dev = crtc->dev;
2707         struct drm_i915_private *dev_priv = dev->dev_private;
2708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2709         int pipe = intel_crtc->pipe;
2710         u32 reg, temp;
2711
2712         /* enable normal train */
2713         reg = FDI_TX_CTL(pipe);
2714         temp = I915_READ(reg);
2715         if (IS_IVYBRIDGE(dev)) {
2716                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2717                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2718         } else {
2719                 temp &= ~FDI_LINK_TRAIN_NONE;
2720                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2721         }
2722         I915_WRITE(reg, temp);
2723
2724         reg = FDI_RX_CTL(pipe);
2725         temp = I915_READ(reg);
2726         if (HAS_PCH_CPT(dev)) {
2727                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2729         } else {
2730                 temp &= ~FDI_LINK_TRAIN_NONE;
2731                 temp |= FDI_LINK_TRAIN_NONE;
2732         }
2733         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2734
2735         /* wait one idle pattern time */
2736         POSTING_READ(reg);
2737         udelay(1000);
2738
2739         /* IVB wants error correction enabled */
2740         if (IS_IVYBRIDGE(dev))
2741                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2742                            FDI_FE_ERRC_ENABLE);
2743 }
2744
2745 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2746 {
2747         return crtc->base.enabled && crtc->active &&
2748                 crtc->config.has_pch_encoder;
2749 }
2750
2751 static void ivb_modeset_global_resources(struct drm_device *dev)
2752 {
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         struct intel_crtc *pipe_B_crtc =
2755                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2756         struct intel_crtc *pipe_C_crtc =
2757                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2758         uint32_t temp;
2759
2760         /*
2761          * When everything is off disable fdi C so that we could enable fdi B
2762          * with all lanes. Note that we don't care about enabled pipes without
2763          * an enabled pch encoder.
2764          */
2765         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2766             !pipe_has_enabled_pch(pipe_C_crtc)) {
2767                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2768                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2769
2770                 temp = I915_READ(SOUTH_CHICKEN1);
2771                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2772                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2773                 I915_WRITE(SOUTH_CHICKEN1, temp);
2774         }
2775 }
2776
2777 /* The FDI link training functions for ILK/Ibexpeak. */
2778 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2779 {
2780         struct drm_device *dev = crtc->dev;
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783         int pipe = intel_crtc->pipe;
2784         u32 reg, temp, tries;
2785
2786         /* FDI needs bits from pipe first */
2787         assert_pipe_enabled(dev_priv, pipe);
2788
2789         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2790            for train result */
2791         reg = FDI_RX_IMR(pipe);
2792         temp = I915_READ(reg);
2793         temp &= ~FDI_RX_SYMBOL_LOCK;
2794         temp &= ~FDI_RX_BIT_LOCK;
2795         I915_WRITE(reg, temp);
2796         I915_READ(reg);
2797         udelay(150);
2798
2799         /* enable CPU FDI TX and PCH FDI RX */
2800         reg = FDI_TX_CTL(pipe);
2801         temp = I915_READ(reg);
2802         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2803         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         temp &= ~FDI_LINK_TRAIN_NONE;
2811         temp |= FDI_LINK_TRAIN_PATTERN_1;
2812         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2813
2814         POSTING_READ(reg);
2815         udelay(150);
2816
2817         /* Ironlake workaround, enable clock pointer after FDI enable*/
2818         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2819         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2820                    FDI_RX_PHASE_SYNC_POINTER_EN);
2821
2822         reg = FDI_RX_IIR(pipe);
2823         for (tries = 0; tries < 5; tries++) {
2824                 temp = I915_READ(reg);
2825                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2826
2827                 if ((temp & FDI_RX_BIT_LOCK)) {
2828                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2829                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2830                         break;
2831                 }
2832         }
2833         if (tries == 5)
2834                 DRM_ERROR("FDI train 1 fail!\n");
2835
2836         /* Train 2 */
2837         reg = FDI_TX_CTL(pipe);
2838         temp = I915_READ(reg);
2839         temp &= ~FDI_LINK_TRAIN_NONE;
2840         temp |= FDI_LINK_TRAIN_PATTERN_2;
2841         I915_WRITE(reg, temp);
2842
2843         reg = FDI_RX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_2;
2847         I915_WRITE(reg, temp);
2848
2849         POSTING_READ(reg);
2850         udelay(150);
2851
2852         reg = FDI_RX_IIR(pipe);
2853         for (tries = 0; tries < 5; tries++) {
2854                 temp = I915_READ(reg);
2855                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2856
2857                 if (temp & FDI_RX_SYMBOL_LOCK) {
2858                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2859                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2860                         break;
2861                 }
2862         }
2863         if (tries == 5)
2864                 DRM_ERROR("FDI train 2 fail!\n");
2865
2866         DRM_DEBUG_KMS("FDI train done\n");
2867
2868 }
2869
2870 static const int snb_b_fdi_train_param[] = {
2871         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2872         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2873         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2874         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2875 };
2876
2877 /* The FDI link training functions for SNB/Cougarpoint. */
2878 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2879 {
2880         struct drm_device *dev = crtc->dev;
2881         struct drm_i915_private *dev_priv = dev->dev_private;
2882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2883         int pipe = intel_crtc->pipe;
2884         u32 reg, temp, i, retry;
2885
2886         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2887            for train result */
2888         reg = FDI_RX_IMR(pipe);
2889         temp = I915_READ(reg);
2890         temp &= ~FDI_RX_SYMBOL_LOCK;
2891         temp &= ~FDI_RX_BIT_LOCK;
2892         I915_WRITE(reg, temp);
2893
2894         POSTING_READ(reg);
2895         udelay(150);
2896
2897         /* enable CPU FDI TX and PCH FDI RX */
2898         reg = FDI_TX_CTL(pipe);
2899         temp = I915_READ(reg);
2900         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2901         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2902         temp &= ~FDI_LINK_TRAIN_NONE;
2903         temp |= FDI_LINK_TRAIN_PATTERN_1;
2904         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2905         /* SNB-B */
2906         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2907         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2908
2909         I915_WRITE(FDI_RX_MISC(pipe),
2910                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2911
2912         reg = FDI_RX_CTL(pipe);
2913         temp = I915_READ(reg);
2914         if (HAS_PCH_CPT(dev)) {
2915                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2917         } else {
2918                 temp &= ~FDI_LINK_TRAIN_NONE;
2919                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2920         }
2921         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2922
2923         POSTING_READ(reg);
2924         udelay(150);
2925
2926         for (i = 0; i < 4; i++) {
2927                 reg = FDI_TX_CTL(pipe);
2928                 temp = I915_READ(reg);
2929                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2930                 temp |= snb_b_fdi_train_param[i];
2931                 I915_WRITE(reg, temp);
2932
2933                 POSTING_READ(reg);
2934                 udelay(500);
2935
2936                 for (retry = 0; retry < 5; retry++) {
2937                         reg = FDI_RX_IIR(pipe);
2938                         temp = I915_READ(reg);
2939                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2940                         if (temp & FDI_RX_BIT_LOCK) {
2941                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2942                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2943                                 break;
2944                         }
2945                         udelay(50);
2946                 }
2947                 if (retry < 5)
2948                         break;
2949         }
2950         if (i == 4)
2951                 DRM_ERROR("FDI train 1 fail!\n");
2952
2953         /* Train 2 */
2954         reg = FDI_TX_CTL(pipe);
2955         temp = I915_READ(reg);
2956         temp &= ~FDI_LINK_TRAIN_NONE;
2957         temp |= FDI_LINK_TRAIN_PATTERN_2;
2958         if (IS_GEN6(dev)) {
2959                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2960                 /* SNB-B */
2961                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2962         }
2963         I915_WRITE(reg, temp);
2964
2965         reg = FDI_RX_CTL(pipe);
2966         temp = I915_READ(reg);
2967         if (HAS_PCH_CPT(dev)) {
2968                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2969                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2970         } else {
2971                 temp &= ~FDI_LINK_TRAIN_NONE;
2972                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2973         }
2974         I915_WRITE(reg, temp);
2975
2976         POSTING_READ(reg);
2977         udelay(150);
2978
2979         for (i = 0; i < 4; i++) {
2980                 reg = FDI_TX_CTL(pipe);
2981                 temp = I915_READ(reg);
2982                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2983                 temp |= snb_b_fdi_train_param[i];
2984                 I915_WRITE(reg, temp);
2985
2986                 POSTING_READ(reg);
2987                 udelay(500);
2988
2989                 for (retry = 0; retry < 5; retry++) {
2990                         reg = FDI_RX_IIR(pipe);
2991                         temp = I915_READ(reg);
2992                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2993                         if (temp & FDI_RX_SYMBOL_LOCK) {
2994                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2995                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2996                                 break;
2997                         }
2998                         udelay(50);
2999                 }
3000                 if (retry < 5)
3001                         break;
3002         }
3003         if (i == 4)
3004                 DRM_ERROR("FDI train 2 fail!\n");
3005
3006         DRM_DEBUG_KMS("FDI train done.\n");
3007 }
3008
3009 /* Manual link training for Ivy Bridge A0 parts */
3010 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3011 {
3012         struct drm_device *dev = crtc->dev;
3013         struct drm_i915_private *dev_priv = dev->dev_private;
3014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015         int pipe = intel_crtc->pipe;
3016         u32 reg, temp, i, j;
3017
3018         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3019            for train result */
3020         reg = FDI_RX_IMR(pipe);
3021         temp = I915_READ(reg);
3022         temp &= ~FDI_RX_SYMBOL_LOCK;
3023         temp &= ~FDI_RX_BIT_LOCK;
3024         I915_WRITE(reg, temp);
3025
3026         POSTING_READ(reg);
3027         udelay(150);
3028
3029         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3030                       I915_READ(FDI_RX_IIR(pipe)));
3031
3032         /* Try each vswing and preemphasis setting twice before moving on */
3033         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3034                 /* disable first in case we need to retry */
3035                 reg = FDI_TX_CTL(pipe);
3036                 temp = I915_READ(reg);
3037                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3038                 temp &= ~FDI_TX_ENABLE;
3039                 I915_WRITE(reg, temp);
3040
3041                 reg = FDI_RX_CTL(pipe);
3042                 temp = I915_READ(reg);
3043                 temp &= ~FDI_LINK_TRAIN_AUTO;
3044                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3045                 temp &= ~FDI_RX_ENABLE;
3046                 I915_WRITE(reg, temp);
3047
3048                 /* enable CPU FDI TX and PCH FDI RX */
3049                 reg = FDI_TX_CTL(pipe);
3050                 temp = I915_READ(reg);
3051                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3052                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3053                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3054                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3055                 temp |= snb_b_fdi_train_param[j/2];
3056                 temp |= FDI_COMPOSITE_SYNC;
3057                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3058
3059                 I915_WRITE(FDI_RX_MISC(pipe),
3060                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3061
3062                 reg = FDI_RX_CTL(pipe);
3063                 temp = I915_READ(reg);
3064                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3065                 temp |= FDI_COMPOSITE_SYNC;
3066                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3067
3068                 POSTING_READ(reg);
3069                 udelay(1); /* should be 0.5us */
3070
3071                 for (i = 0; i < 4; i++) {
3072                         reg = FDI_RX_IIR(pipe);
3073                         temp = I915_READ(reg);
3074                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3075
3076                         if (temp & FDI_RX_BIT_LOCK ||
3077                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3078                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3079                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3080                                               i);
3081                                 break;
3082                         }
3083                         udelay(1); /* should be 0.5us */
3084                 }
3085                 if (i == 4) {
3086                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3087                         continue;
3088                 }
3089
3090                 /* Train 2 */
3091                 reg = FDI_TX_CTL(pipe);
3092                 temp = I915_READ(reg);
3093                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3094                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3095                 I915_WRITE(reg, temp);
3096
3097                 reg = FDI_RX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3100                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3101                 I915_WRITE(reg, temp);
3102
3103                 POSTING_READ(reg);
3104                 udelay(2); /* should be 1.5us */
3105
3106                 for (i = 0; i < 4; i++) {
3107                         reg = FDI_RX_IIR(pipe);
3108                         temp = I915_READ(reg);
3109                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111                         if (temp & FDI_RX_SYMBOL_LOCK ||
3112                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3113                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3115                                               i);
3116                                 goto train_done;
3117                         }
3118                         udelay(2); /* should be 1.5us */
3119                 }
3120                 if (i == 4)
3121                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3122         }
3123
3124 train_done:
3125         DRM_DEBUG_KMS("FDI train done.\n");
3126 }
3127
3128 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3129 {
3130         struct drm_device *dev = intel_crtc->base.dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         int pipe = intel_crtc->pipe;
3133         u32 reg, temp;
3134
3135
3136         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3137         reg = FDI_RX_CTL(pipe);
3138         temp = I915_READ(reg);
3139         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3140         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3141         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3142         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3143
3144         POSTING_READ(reg);
3145         udelay(200);
3146
3147         /* Switch from Rawclk to PCDclk */
3148         temp = I915_READ(reg);
3149         I915_WRITE(reg, temp | FDI_PCDCLK);
3150
3151         POSTING_READ(reg);
3152         udelay(200);
3153
3154         /* Enable CPU FDI TX PLL, always on for Ironlake */
3155         reg = FDI_TX_CTL(pipe);
3156         temp = I915_READ(reg);
3157         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3158                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3159
3160                 POSTING_READ(reg);
3161                 udelay(100);
3162         }
3163 }
3164
3165 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3166 {
3167         struct drm_device *dev = intel_crtc->base.dev;
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169         int pipe = intel_crtc->pipe;
3170         u32 reg, temp;
3171
3172         /* Switch from PCDclk to Rawclk */
3173         reg = FDI_RX_CTL(pipe);
3174         temp = I915_READ(reg);
3175         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3176
3177         /* Disable CPU FDI TX PLL */
3178         reg = FDI_TX_CTL(pipe);
3179         temp = I915_READ(reg);
3180         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3181
3182         POSTING_READ(reg);
3183         udelay(100);
3184
3185         reg = FDI_RX_CTL(pipe);
3186         temp = I915_READ(reg);
3187         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3188
3189         /* Wait for the clocks to turn off. */
3190         POSTING_READ(reg);
3191         udelay(100);
3192 }
3193
3194 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3195 {
3196         struct drm_device *dev = crtc->dev;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3199         int pipe = intel_crtc->pipe;
3200         u32 reg, temp;
3201
3202         /* disable CPU FDI tx and PCH FDI rx */
3203         reg = FDI_TX_CTL(pipe);
3204         temp = I915_READ(reg);
3205         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3206         POSTING_READ(reg);
3207
3208         reg = FDI_RX_CTL(pipe);
3209         temp = I915_READ(reg);
3210         temp &= ~(0x7 << 16);
3211         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3212         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3213
3214         POSTING_READ(reg);
3215         udelay(100);
3216
3217         /* Ironlake workaround, disable clock pointer after downing FDI */
3218         if (HAS_PCH_IBX(dev))
3219                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3220
3221         /* still set train pattern 1 */
3222         reg = FDI_TX_CTL(pipe);
3223         temp = I915_READ(reg);
3224         temp &= ~FDI_LINK_TRAIN_NONE;
3225         temp |= FDI_LINK_TRAIN_PATTERN_1;
3226         I915_WRITE(reg, temp);
3227
3228         reg = FDI_RX_CTL(pipe);
3229         temp = I915_READ(reg);
3230         if (HAS_PCH_CPT(dev)) {
3231                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3232                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3233         } else {
3234                 temp &= ~FDI_LINK_TRAIN_NONE;
3235                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3236         }
3237         /* BPC in FDI rx is consistent with that in PIPECONF */
3238         temp &= ~(0x07 << 16);
3239         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3240         I915_WRITE(reg, temp);
3241
3242         POSTING_READ(reg);
3243         udelay(100);
3244 }
3245
3246 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3247 {
3248         struct intel_crtc *crtc;
3249
3250         /* Note that we don't need to be called with mode_config.lock here
3251          * as our list of CRTC objects is static for the lifetime of the
3252          * device and so cannot disappear as we iterate. Similarly, we can
3253          * happily treat the predicates as racy, atomic checks as userspace
3254          * cannot claim and pin a new fb without at least acquring the
3255          * struct_mutex and so serialising with us.
3256          */
3257         for_each_intel_crtc(dev, crtc) {
3258                 if (atomic_read(&crtc->unpin_work_count) == 0)
3259                         continue;
3260
3261                 if (crtc->unpin_work)
3262                         intel_wait_for_vblank(dev, crtc->pipe);
3263
3264                 return true;
3265         }
3266
3267         return false;
3268 }
3269
3270 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3271 {
3272         struct drm_device *dev = crtc->dev;
3273         struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275         if (crtc->primary->fb == NULL)
3276                 return;
3277
3278         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3279
3280         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3281                                    !intel_crtc_has_pending_flip(crtc),
3282                                    60*HZ) == 0);
3283
3284         mutex_lock(&dev->struct_mutex);
3285         intel_finish_fb(crtc->primary->fb);
3286         mutex_unlock(&dev->struct_mutex);
3287 }
3288
3289 /* Program iCLKIP clock to the desired frequency */
3290 static void lpt_program_iclkip(struct drm_crtc *crtc)
3291 {
3292         struct drm_device *dev = crtc->dev;
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3295         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3296         u32 temp;
3297
3298         mutex_lock(&dev_priv->dpio_lock);
3299
3300         /* It is necessary to ungate the pixclk gate prior to programming
3301          * the divisors, and gate it back when it is done.
3302          */
3303         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3304
3305         /* Disable SSCCTL */
3306         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3307                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3308                                 SBI_SSCCTL_DISABLE,
3309                         SBI_ICLK);
3310
3311         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3312         if (clock == 20000) {
3313                 auxdiv = 1;
3314                 divsel = 0x41;
3315                 phaseinc = 0x20;
3316         } else {
3317                 /* The iCLK virtual clock root frequency is in MHz,
3318                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3319                  * divisors, it is necessary to divide one by another, so we
3320                  * convert the virtual clock precision to KHz here for higher
3321                  * precision.
3322                  */
3323                 u32 iclk_virtual_root_freq = 172800 * 1000;
3324                 u32 iclk_pi_range = 64;
3325                 u32 desired_divisor, msb_divisor_value, pi_value;
3326
3327                 desired_divisor = (iclk_virtual_root_freq / clock);
3328                 msb_divisor_value = desired_divisor / iclk_pi_range;
3329                 pi_value = desired_divisor % iclk_pi_range;
3330
3331                 auxdiv = 0;
3332                 divsel = msb_divisor_value - 2;
3333                 phaseinc = pi_value;
3334         }
3335
3336         /* This should not happen with any sane values */
3337         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3338                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3339         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3340                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3341
3342         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3343                         clock,
3344                         auxdiv,
3345                         divsel,
3346                         phasedir,
3347                         phaseinc);
3348
3349         /* Program SSCDIVINTPHASE6 */
3350         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3351         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3352         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3353         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3354         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3355         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3356         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3357         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3358
3359         /* Program SSCAUXDIV */
3360         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3361         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3362         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3363         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3364
3365         /* Enable modulator and associated divider */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3367         temp &= ~SBI_SSCCTL_DISABLE;
3368         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3369
3370         /* Wait for initialization time */
3371         udelay(24);
3372
3373         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3374
3375         mutex_unlock(&dev_priv->dpio_lock);
3376 }
3377
3378 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3379                                                 enum pipe pch_transcoder)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3384
3385         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3386                    I915_READ(HTOTAL(cpu_transcoder)));
3387         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3388                    I915_READ(HBLANK(cpu_transcoder)));
3389         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3390                    I915_READ(HSYNC(cpu_transcoder)));
3391
3392         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3393                    I915_READ(VTOTAL(cpu_transcoder)));
3394         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3395                    I915_READ(VBLANK(cpu_transcoder)));
3396         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3397                    I915_READ(VSYNC(cpu_transcoder)));
3398         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3399                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3400 }
3401
3402 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3403 {
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         uint32_t temp;
3406
3407         temp = I915_READ(SOUTH_CHICKEN1);
3408         if (temp & FDI_BC_BIFURCATION_SELECT)
3409                 return;
3410
3411         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3412         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3413
3414         temp |= FDI_BC_BIFURCATION_SELECT;
3415         DRM_DEBUG_KMS("enabling fdi C rx\n");
3416         I915_WRITE(SOUTH_CHICKEN1, temp);
3417         POSTING_READ(SOUTH_CHICKEN1);
3418 }
3419
3420 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424
3425         switch (intel_crtc->pipe) {
3426         case PIPE_A:
3427                 break;
3428         case PIPE_B:
3429                 if (intel_crtc->config.fdi_lanes > 2)
3430                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3431                 else
3432                         cpt_enable_fdi_bc_bifurcation(dev);
3433
3434                 break;
3435         case PIPE_C:
3436                 cpt_enable_fdi_bc_bifurcation(dev);
3437
3438                 break;
3439         default:
3440                 BUG();
3441         }
3442 }
3443
3444 /*
3445  * Enable PCH resources required for PCH ports:
3446  *   - PCH PLLs
3447  *   - FDI training & RX/TX
3448  *   - update transcoder timings
3449  *   - DP transcoding bits
3450  *   - transcoder
3451  */
3452 static void ironlake_pch_enable(struct drm_crtc *crtc)
3453 {
3454         struct drm_device *dev = crtc->dev;
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457         int pipe = intel_crtc->pipe;
3458         u32 reg, temp;
3459
3460         assert_pch_transcoder_disabled(dev_priv, pipe);
3461
3462         if (IS_IVYBRIDGE(dev))
3463                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3464
3465         /* Write the TU size bits before fdi link training, so that error
3466          * detection works. */
3467         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3468                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3469
3470         /* For PCH output, training FDI link */
3471         dev_priv->display.fdi_link_train(crtc);
3472
3473         /* We need to program the right clock selection before writing the pixel
3474          * mutliplier into the DPLL. */
3475         if (HAS_PCH_CPT(dev)) {
3476                 u32 sel;
3477
3478                 temp = I915_READ(PCH_DPLL_SEL);
3479                 temp |= TRANS_DPLL_ENABLE(pipe);
3480                 sel = TRANS_DPLLB_SEL(pipe);
3481                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3482                         temp |= sel;
3483                 else
3484                         temp &= ~sel;
3485                 I915_WRITE(PCH_DPLL_SEL, temp);
3486         }
3487
3488         /* XXX: pch pll's can be enabled any time before we enable the PCH
3489          * transcoder, and we actually should do this to not upset any PCH
3490          * transcoder that already use the clock when we share it.
3491          *
3492          * Note that enable_shared_dpll tries to do the right thing, but
3493          * get_shared_dpll unconditionally resets the pll - we need that to have
3494          * the right LVDS enable sequence. */
3495         ironlake_enable_shared_dpll(intel_crtc);
3496
3497         /* set transcoder timing, panel must allow it */
3498         assert_panel_unlocked(dev_priv, pipe);
3499         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3500
3501         intel_fdi_normal_train(crtc);
3502
3503         /* For PCH DP, enable TRANS_DP_CTL */
3504         if (HAS_PCH_CPT(dev) &&
3505             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3506              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3507                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3508                 reg = TRANS_DP_CTL(pipe);
3509                 temp = I915_READ(reg);
3510                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3511                           TRANS_DP_SYNC_MASK |
3512                           TRANS_DP_BPC_MASK);
3513                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3514                          TRANS_DP_ENH_FRAMING);
3515                 temp |= bpc << 9; /* same format but at 11:9 */
3516
3517                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3518                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3519                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3520                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3521
3522                 switch (intel_trans_dp_port_sel(crtc)) {
3523                 case PCH_DP_B:
3524                         temp |= TRANS_DP_PORT_SEL_B;
3525                         break;
3526                 case PCH_DP_C:
3527                         temp |= TRANS_DP_PORT_SEL_C;
3528                         break;
3529                 case PCH_DP_D:
3530                         temp |= TRANS_DP_PORT_SEL_D;
3531                         break;
3532                 default:
3533                         BUG();
3534                 }
3535
3536                 I915_WRITE(reg, temp);
3537         }
3538
3539         ironlake_enable_pch_transcoder(dev_priv, pipe);
3540 }
3541
3542 static void lpt_pch_enable(struct drm_crtc *crtc)
3543 {
3544         struct drm_device *dev = crtc->dev;
3545         struct drm_i915_private *dev_priv = dev->dev_private;
3546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3547         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3548
3549         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3550
3551         lpt_program_iclkip(crtc);
3552
3553         /* Set transcoder timing. */
3554         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3555
3556         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3557 }
3558
3559 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3560 {
3561         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3562
3563         if (pll == NULL)
3564                 return;
3565
3566         if (pll->refcount == 0) {
3567                 WARN(1, "bad %s refcount\n", pll->name);
3568                 return;
3569         }
3570
3571         if (--pll->refcount == 0) {
3572                 WARN_ON(pll->on);
3573                 WARN_ON(pll->active);
3574         }
3575
3576         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3577 }
3578
3579 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3580 {
3581         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3582         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3583         enum intel_dpll_id i;
3584
3585         if (pll) {
3586                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3587                               crtc->base.base.id, pll->name);
3588                 intel_put_shared_dpll(crtc);
3589         }
3590
3591         if (HAS_PCH_IBX(dev_priv->dev)) {
3592                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3593                 i = (enum intel_dpll_id) crtc->pipe;
3594                 pll = &dev_priv->shared_dplls[i];
3595
3596                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3597                               crtc->base.base.id, pll->name);
3598
3599                 goto found;
3600         }
3601
3602         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3603                 pll = &dev_priv->shared_dplls[i];
3604
3605                 /* Only want to check enabled timings first */
3606                 if (pll->refcount == 0)
3607                         continue;
3608
3609                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3610                            sizeof(pll->hw_state)) == 0) {
3611                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3612                                       crtc->base.base.id,
3613                                       pll->name, pll->refcount, pll->active);
3614
3615                         goto found;
3616                 }
3617         }
3618
3619         /* Ok no matching timings, maybe there's a free one? */
3620         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3621                 pll = &dev_priv->shared_dplls[i];
3622                 if (pll->refcount == 0) {
3623                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3624                                       crtc->base.base.id, pll->name);
3625                         goto found;
3626                 }
3627         }
3628
3629         return NULL;
3630
3631 found:
3632         crtc->config.shared_dpll = i;
3633         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3634                          pipe_name(crtc->pipe));
3635
3636         if (pll->active == 0) {
3637                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3638                        sizeof(pll->hw_state));
3639
3640                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3641                 WARN_ON(pll->on);
3642                 assert_shared_dpll_disabled(dev_priv, pll);
3643
3644                 pll->mode_set(dev_priv, pll);
3645         }
3646         pll->refcount++;
3647
3648         return pll;
3649 }
3650
3651 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3652 {
3653         struct drm_i915_private *dev_priv = dev->dev_private;
3654         int dslreg = PIPEDSL(pipe);
3655         u32 temp;
3656
3657         temp = I915_READ(dslreg);
3658         udelay(500);
3659         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3660                 if (wait_for(I915_READ(dslreg) != temp, 5))
3661                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3662         }
3663 }
3664
3665 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3666 {
3667         struct drm_device *dev = crtc->base.dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         int pipe = crtc->pipe;
3670
3671         if (crtc->config.pch_pfit.enabled) {
3672                 /* Force use of hard-coded filter coefficients
3673                  * as some pre-programmed values are broken,
3674                  * e.g. x201.
3675                  */
3676                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3677                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3678                                                  PF_PIPE_SEL_IVB(pipe));
3679                 else
3680                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3681                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3682                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3683         }
3684 }
3685
3686 static void intel_enable_planes(struct drm_crtc *crtc)
3687 {
3688         struct drm_device *dev = crtc->dev;
3689         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3690         struct drm_plane *plane;
3691         struct intel_plane *intel_plane;
3692
3693         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3694                 intel_plane = to_intel_plane(plane);
3695                 if (intel_plane->pipe == pipe)
3696                         intel_plane_restore(&intel_plane->base);
3697         }
3698 }
3699
3700 static void intel_disable_planes(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3704         struct drm_plane *plane;
3705         struct intel_plane *intel_plane;
3706
3707         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3708                 intel_plane = to_intel_plane(plane);
3709                 if (intel_plane->pipe == pipe)
3710                         intel_plane_disable(&intel_plane->base);
3711         }
3712 }
3713
3714 void hsw_enable_ips(struct intel_crtc *crtc)
3715 {
3716         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3717
3718         if (!crtc->config.ips_enabled)
3719                 return;
3720
3721         /* We can only enable IPS after we enable a plane and wait for a vblank.
3722          * We guarantee that the plane is enabled by calling intel_enable_ips
3723          * only after intel_enable_plane. And intel_enable_plane already waits
3724          * for a vblank, so all we need to do here is to enable the IPS bit. */
3725         assert_plane_enabled(dev_priv, crtc->plane);
3726         if (IS_BROADWELL(crtc->base.dev)) {
3727                 mutex_lock(&dev_priv->rps.hw_lock);
3728                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3729                 mutex_unlock(&dev_priv->rps.hw_lock);
3730                 /* Quoting Art Runyan: "its not safe to expect any particular
3731                  * value in IPS_CTL bit 31 after enabling IPS through the
3732                  * mailbox." Moreover, the mailbox may return a bogus state,
3733                  * so we need to just enable it and continue on.
3734                  */
3735         } else {
3736                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3737                 /* The bit only becomes 1 in the next vblank, so this wait here
3738                  * is essentially intel_wait_for_vblank. If we don't have this
3739                  * and don't wait for vblanks until the end of crtc_enable, then
3740                  * the HW state readout code will complain that the expected
3741                  * IPS_CTL value is not the one we read. */
3742                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3743                         DRM_ERROR("Timed out waiting for IPS enable\n");
3744         }
3745 }
3746
3747 void hsw_disable_ips(struct intel_crtc *crtc)
3748 {
3749         struct drm_device *dev = crtc->base.dev;
3750         struct drm_i915_private *dev_priv = dev->dev_private;
3751
3752         if (!crtc->config.ips_enabled)
3753                 return;
3754
3755         assert_plane_enabled(dev_priv, crtc->plane);
3756         if (IS_BROADWELL(dev)) {
3757                 mutex_lock(&dev_priv->rps.hw_lock);
3758                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3759                 mutex_unlock(&dev_priv->rps.hw_lock);
3760                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3761                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3762                         DRM_ERROR("Timed out waiting for IPS disable\n");
3763         } else {
3764                 I915_WRITE(IPS_CTL, 0);
3765                 POSTING_READ(IPS_CTL);
3766         }
3767
3768         /* We need to wait for a vblank before we can disable the plane. */
3769         intel_wait_for_vblank(dev, crtc->pipe);
3770 }
3771
3772 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3773 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3774 {
3775         struct drm_device *dev = crtc->dev;
3776         struct drm_i915_private *dev_priv = dev->dev_private;
3777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778         enum pipe pipe = intel_crtc->pipe;
3779         int palreg = PALETTE(pipe);
3780         int i;
3781         bool reenable_ips = false;
3782
3783         /* The clocks have to be on to load the palette. */
3784         if (!crtc->enabled || !intel_crtc->active)
3785                 return;
3786
3787         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3788                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3789                         assert_dsi_pll_enabled(dev_priv);
3790                 else
3791                         assert_pll_enabled(dev_priv, pipe);
3792         }
3793
3794         /* use legacy palette for Ironlake */
3795         if (HAS_PCH_SPLIT(dev))
3796                 palreg = LGC_PALETTE(pipe);
3797
3798         /* Workaround : Do not read or write the pipe palette/gamma data while
3799          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3800          */
3801         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3802             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3803              GAMMA_MODE_MODE_SPLIT)) {
3804                 hsw_disable_ips(intel_crtc);
3805                 reenable_ips = true;
3806         }
3807
3808         for (i = 0; i < 256; i++) {
3809                 I915_WRITE(palreg + 4 * i,
3810                            (intel_crtc->lut_r[i] << 16) |
3811                            (intel_crtc->lut_g[i] << 8) |
3812                            intel_crtc->lut_b[i]);
3813         }
3814
3815         if (reenable_ips)
3816                 hsw_enable_ips(intel_crtc);
3817 }
3818
3819 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3820 {
3821         if (!enable && intel_crtc->overlay) {
3822                 struct drm_device *dev = intel_crtc->base.dev;
3823                 struct drm_i915_private *dev_priv = dev->dev_private;
3824
3825                 mutex_lock(&dev->struct_mutex);
3826                 dev_priv->mm.interruptible = false;
3827                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3828                 dev_priv->mm.interruptible = true;
3829                 mutex_unlock(&dev->struct_mutex);
3830         }
3831
3832         /* Let userspace switch the overlay on again. In most cases userspace
3833          * has to recompute where to put it anyway.
3834          */
3835 }
3836
3837 /**
3838  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3839  * cursor plane briefly if not already running after enabling the display
3840  * plane.
3841  * This workaround avoids occasional blank screens when self refresh is
3842  * enabled.
3843  */
3844 static void
3845 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3846 {
3847         u32 cntl = I915_READ(CURCNTR(pipe));
3848
3849         if ((cntl & CURSOR_MODE) == 0) {
3850                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3851
3852                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3853                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3854                 intel_wait_for_vblank(dev_priv->dev, pipe);
3855                 I915_WRITE(CURCNTR(pipe), cntl);
3856                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3857                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3858         }
3859 }
3860
3861 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3862 {
3863         struct drm_device *dev = crtc->dev;
3864         struct drm_i915_private *dev_priv = dev->dev_private;
3865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3866         int pipe = intel_crtc->pipe;
3867         int plane = intel_crtc->plane;
3868
3869         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3870         intel_enable_planes(crtc);
3871         /* The fixup needs to happen before cursor is enabled */
3872         if (IS_G4X(dev))
3873                 g4x_fixup_plane(dev_priv, pipe);
3874         intel_crtc_update_cursor(crtc, true);
3875         intel_crtc_dpms_overlay(intel_crtc, true);
3876
3877         hsw_enable_ips(intel_crtc);
3878
3879         mutex_lock(&dev->struct_mutex);
3880         intel_update_fbc(dev);
3881         intel_edp_psr_update(dev);
3882         mutex_unlock(&dev->struct_mutex);
3883 }
3884
3885 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3886 {
3887         struct drm_device *dev = crtc->dev;
3888         struct drm_i915_private *dev_priv = dev->dev_private;
3889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3890         int pipe = intel_crtc->pipe;
3891         int plane = intel_crtc->plane;
3892
3893         intel_crtc_wait_for_pending_flips(crtc);
3894         drm_vblank_off(dev, pipe);
3895
3896         if (dev_priv->fbc.plane == plane)
3897                 intel_disable_fbc(dev);
3898
3899         hsw_disable_ips(intel_crtc);
3900
3901         intel_crtc_dpms_overlay(intel_crtc, false);
3902         intel_crtc_update_cursor(crtc, false);
3903         intel_disable_planes(crtc);
3904         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3905 }
3906
3907 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3908 {
3909         struct drm_device *dev = crtc->dev;
3910         struct drm_i915_private *dev_priv = dev->dev_private;
3911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3912         struct intel_encoder *encoder;
3913         int pipe = intel_crtc->pipe;
3914
3915         WARN_ON(!crtc->enabled);
3916
3917         if (intel_crtc->active)
3918                 return;
3919
3920         intel_crtc->active = true;
3921
3922         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3923         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3924
3925         for_each_encoder_on_crtc(dev, crtc, encoder)
3926                 if (encoder->pre_enable)
3927                         encoder->pre_enable(encoder);
3928
3929         if (intel_crtc->config.has_pch_encoder) {
3930                 /* Note: FDI PLL enabling _must_ be done before we enable the
3931                  * cpu pipes, hence this is separate from all the other fdi/pch
3932                  * enabling. */
3933                 ironlake_fdi_pll_enable(intel_crtc);
3934         } else {
3935                 assert_fdi_tx_disabled(dev_priv, pipe);
3936                 assert_fdi_rx_disabled(dev_priv, pipe);
3937         }
3938
3939         ironlake_pfit_enable(intel_crtc);
3940
3941         /*
3942          * On ILK+ LUT must be loaded before the pipe is running but with
3943          * clocks enabled
3944          */
3945         intel_crtc_load_lut(crtc);
3946
3947         intel_update_watermarks(crtc);
3948         intel_enable_pipe(intel_crtc);
3949
3950         if (intel_crtc->config.has_pch_encoder)
3951                 ironlake_pch_enable(crtc);
3952
3953         for_each_encoder_on_crtc(dev, crtc, encoder)
3954                 encoder->enable(encoder);
3955
3956         if (HAS_PCH_CPT(dev))
3957                 cpt_verify_modeset(dev, intel_crtc->pipe);
3958
3959         intel_crtc_enable_planes(crtc);
3960
3961         /*
3962          * There seems to be a race in PCH platform hw (at least on some
3963          * outputs) where an enabled pipe still completes any pageflip right
3964          * away (as if the pipe is off) instead of waiting for vblank. As soon
3965          * as the first vblank happend, everything works as expected. Hence just
3966          * wait for one vblank before returning to avoid strange things
3967          * happening.
3968          */
3969         intel_wait_for_vblank(dev, intel_crtc->pipe);
3970 }
3971
3972 /* IPS only exists on ULT machines and is tied to pipe A. */
3973 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3974 {
3975         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3976 }
3977
3978 /*
3979  * This implements the workaround described in the "notes" section of the mode
3980  * set sequence documentation. When going from no pipes or single pipe to
3981  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3982  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3983  */
3984 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3985 {
3986         struct drm_device *dev = crtc->base.dev;
3987         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3988
3989         /* We want to get the other_active_crtc only if there's only 1 other
3990          * active crtc. */
3991         for_each_intel_crtc(dev, crtc_it) {
3992                 if (!crtc_it->active || crtc_it == crtc)
3993                         continue;
3994
3995                 if (other_active_crtc)
3996                         return;
3997
3998                 other_active_crtc = crtc_it;
3999         }
4000         if (!other_active_crtc)
4001                 return;
4002
4003         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4004         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4005 }
4006
4007 static void haswell_crtc_enable(struct drm_crtc *crtc)
4008 {
4009         struct drm_device *dev = crtc->dev;
4010         struct drm_i915_private *dev_priv = dev->dev_private;
4011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4012         struct intel_encoder *encoder;
4013         int pipe = intel_crtc->pipe;
4014
4015         WARN_ON(!crtc->enabled);
4016
4017         if (intel_crtc->active)
4018                 return;
4019
4020         intel_crtc->active = true;
4021
4022         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4023         if (intel_crtc->config.has_pch_encoder)
4024                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4025
4026         if (intel_crtc->config.has_pch_encoder)
4027                 dev_priv->display.fdi_link_train(crtc);
4028
4029         for_each_encoder_on_crtc(dev, crtc, encoder)
4030                 if (encoder->pre_enable)
4031                         encoder->pre_enable(encoder);
4032
4033         intel_ddi_enable_pipe_clock(intel_crtc);
4034
4035         ironlake_pfit_enable(intel_crtc);
4036
4037         /*
4038          * On ILK+ LUT must be loaded before the pipe is running but with
4039          * clocks enabled
4040          */
4041         intel_crtc_load_lut(crtc);
4042
4043         intel_ddi_set_pipe_settings(crtc);
4044         intel_ddi_enable_transcoder_func(crtc);
4045
4046         intel_update_watermarks(crtc);
4047         intel_enable_pipe(intel_crtc);
4048
4049         if (intel_crtc->config.has_pch_encoder)
4050                 lpt_pch_enable(crtc);
4051
4052         for_each_encoder_on_crtc(dev, crtc, encoder) {
4053                 encoder->enable(encoder);
4054                 intel_opregion_notify_encoder(encoder, true);
4055         }
4056
4057         /* If we change the relative order between pipe/planes enabling, we need
4058          * to change the workaround. */
4059         haswell_mode_set_planes_workaround(intel_crtc);
4060         intel_crtc_enable_planes(crtc);
4061 }
4062
4063 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4064 {
4065         struct drm_device *dev = crtc->base.dev;
4066         struct drm_i915_private *dev_priv = dev->dev_private;
4067         int pipe = crtc->pipe;
4068
4069         /* To avoid upsetting the power well on haswell only disable the pfit if
4070          * it's in use. The hw state code will make sure we get this right. */
4071         if (crtc->config.pch_pfit.enabled) {
4072                 I915_WRITE(PF_CTL(pipe), 0);
4073                 I915_WRITE(PF_WIN_POS(pipe), 0);
4074                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4075         }
4076 }
4077
4078 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4079 {
4080         struct drm_device *dev = crtc->dev;
4081         struct drm_i915_private *dev_priv = dev->dev_private;
4082         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4083         struct intel_encoder *encoder;
4084         int pipe = intel_crtc->pipe;
4085         u32 reg, temp;
4086
4087         if (!intel_crtc->active)
4088                 return;
4089
4090         intel_crtc_disable_planes(crtc);
4091
4092         for_each_encoder_on_crtc(dev, crtc, encoder)
4093                 encoder->disable(encoder);
4094
4095         if (intel_crtc->config.has_pch_encoder)
4096                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4097
4098         intel_disable_pipe(dev_priv, pipe);
4099
4100         ironlake_pfit_disable(intel_crtc);
4101
4102         for_each_encoder_on_crtc(dev, crtc, encoder)
4103                 if (encoder->post_disable)
4104                         encoder->post_disable(encoder);
4105
4106         if (intel_crtc->config.has_pch_encoder) {
4107                 ironlake_fdi_disable(crtc);
4108
4109                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4110                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4111
4112                 if (HAS_PCH_CPT(dev)) {
4113                         /* disable TRANS_DP_CTL */
4114                         reg = TRANS_DP_CTL(pipe);
4115                         temp = I915_READ(reg);
4116                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4117                                   TRANS_DP_PORT_SEL_MASK);
4118                         temp |= TRANS_DP_PORT_SEL_NONE;
4119                         I915_WRITE(reg, temp);
4120
4121                         /* disable DPLL_SEL */
4122                         temp = I915_READ(PCH_DPLL_SEL);
4123                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4124                         I915_WRITE(PCH_DPLL_SEL, temp);
4125                 }
4126
4127                 /* disable PCH DPLL */
4128                 intel_disable_shared_dpll(intel_crtc);
4129
4130                 ironlake_fdi_pll_disable(intel_crtc);
4131         }
4132
4133         intel_crtc->active = false;
4134         intel_update_watermarks(crtc);
4135
4136         mutex_lock(&dev->struct_mutex);
4137         intel_update_fbc(dev);
4138         intel_edp_psr_update(dev);
4139         mutex_unlock(&dev->struct_mutex);
4140 }
4141
4142 static void haswell_crtc_disable(struct drm_crtc *crtc)
4143 {
4144         struct drm_device *dev = crtc->dev;
4145         struct drm_i915_private *dev_priv = dev->dev_private;
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         struct intel_encoder *encoder;
4148         int pipe = intel_crtc->pipe;
4149         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4150
4151         if (!intel_crtc->active)
4152                 return;
4153
4154         intel_crtc_disable_planes(crtc);
4155
4156         for_each_encoder_on_crtc(dev, crtc, encoder) {
4157                 intel_opregion_notify_encoder(encoder, false);
4158                 encoder->disable(encoder);
4159         }
4160
4161         if (intel_crtc->config.has_pch_encoder)
4162                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4163         intel_disable_pipe(dev_priv, pipe);
4164
4165         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4166
4167         ironlake_pfit_disable(intel_crtc);
4168
4169         intel_ddi_disable_pipe_clock(intel_crtc);
4170
4171         for_each_encoder_on_crtc(dev, crtc, encoder)
4172                 if (encoder->post_disable)
4173                         encoder->post_disable(encoder);
4174
4175         if (intel_crtc->config.has_pch_encoder) {
4176                 lpt_disable_pch_transcoder(dev_priv);
4177                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4178                 intel_ddi_fdi_disable(crtc);
4179         }
4180
4181         intel_crtc->active = false;
4182         intel_update_watermarks(crtc);
4183
4184         mutex_lock(&dev->struct_mutex);
4185         intel_update_fbc(dev);
4186         intel_edp_psr_update(dev);
4187         mutex_unlock(&dev->struct_mutex);
4188 }
4189
4190 static void ironlake_crtc_off(struct drm_crtc *crtc)
4191 {
4192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4193         intel_put_shared_dpll(intel_crtc);
4194 }
4195
4196 static void haswell_crtc_off(struct drm_crtc *crtc)
4197 {
4198         intel_ddi_put_crtc_pll(crtc);
4199 }
4200
4201 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4202 {
4203         struct drm_device *dev = crtc->base.dev;
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         struct intel_crtc_config *pipe_config = &crtc->config;
4206
4207         if (!crtc->config.gmch_pfit.control)
4208                 return;
4209
4210         /*
4211          * The panel fitter should only be adjusted whilst the pipe is disabled,
4212          * according to register description and PRM.
4213          */
4214         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4215         assert_pipe_disabled(dev_priv, crtc->pipe);
4216
4217         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4218         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4219
4220         /* Border color in case we don't scale up to the full screen. Black by
4221          * default, change to something else for debugging. */
4222         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4223 }
4224
4225 #define for_each_power_domain(domain, mask)                             \
4226         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4227                 if ((1 << (domain)) & (mask))
4228
4229 enum intel_display_power_domain
4230 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4231 {
4232         struct drm_device *dev = intel_encoder->base.dev;
4233         struct intel_digital_port *intel_dig_port;
4234
4235         switch (intel_encoder->type) {
4236         case INTEL_OUTPUT_UNKNOWN:
4237                 /* Only DDI platforms should ever use this output type */
4238                 WARN_ON_ONCE(!HAS_DDI(dev));
4239         case INTEL_OUTPUT_DISPLAYPORT:
4240         case INTEL_OUTPUT_HDMI:
4241         case INTEL_OUTPUT_EDP:
4242                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4243                 switch (intel_dig_port->port) {
4244                 case PORT_A:
4245                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4246                 case PORT_B:
4247                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4248                 case PORT_C:
4249                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4250                 case PORT_D:
4251                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4252                 default:
4253                         WARN_ON_ONCE(1);
4254                         return POWER_DOMAIN_PORT_OTHER;
4255                 }
4256         case INTEL_OUTPUT_ANALOG:
4257                 return POWER_DOMAIN_PORT_CRT;
4258         case INTEL_OUTPUT_DSI:
4259                 return POWER_DOMAIN_PORT_DSI;
4260         default:
4261                 return POWER_DOMAIN_PORT_OTHER;
4262         }
4263 }
4264
4265 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4266 {
4267         struct drm_device *dev = crtc->dev;
4268         struct intel_encoder *intel_encoder;
4269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4270         enum pipe pipe = intel_crtc->pipe;
4271         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4272         unsigned long mask;
4273         enum transcoder transcoder;
4274
4275         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4276
4277         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4278         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4279         if (pfit_enabled)
4280                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4281
4282         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4283                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4284
4285         return mask;
4286 }
4287
4288 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4289                                   bool enable)
4290 {
4291         if (dev_priv->power_domains.init_power_on == enable)
4292                 return;
4293
4294         if (enable)
4295                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4296         else
4297                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4298
4299         dev_priv->power_domains.init_power_on = enable;
4300 }
4301
4302 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4303 {
4304         struct drm_i915_private *dev_priv = dev->dev_private;
4305         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4306         struct intel_crtc *crtc;
4307
4308         /*
4309          * First get all needed power domains, then put all unneeded, to avoid
4310          * any unnecessary toggling of the power wells.
4311          */
4312         for_each_intel_crtc(dev, crtc) {
4313                 enum intel_display_power_domain domain;
4314
4315                 if (!crtc->base.enabled)
4316                         continue;
4317
4318                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4319
4320                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4321                         intel_display_power_get(dev_priv, domain);
4322         }
4323
4324         for_each_intel_crtc(dev, crtc) {
4325                 enum intel_display_power_domain domain;
4326
4327                 for_each_power_domain(domain, crtc->enabled_power_domains)
4328                         intel_display_power_put(dev_priv, domain);
4329
4330                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4331         }
4332
4333         intel_display_set_init_power(dev_priv, false);
4334 }
4335
4336 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4337 {
4338         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4339
4340         /* Obtain SKU information */
4341         mutex_lock(&dev_priv->dpio_lock);
4342         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4343                 CCK_FUSE_HPLL_FREQ_MASK;
4344         mutex_unlock(&dev_priv->dpio_lock);
4345
4346         return vco_freq[hpll_freq];
4347 }
4348
4349 /* Adjust CDclk dividers to allow high res or save power if possible */
4350 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4351 {
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         u32 val, cmd;
4354
4355         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4356         dev_priv->vlv_cdclk_freq = cdclk;
4357
4358         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4359                 cmd = 2;
4360         else if (cdclk == 266)
4361                 cmd = 1;
4362         else
4363                 cmd = 0;
4364
4365         mutex_lock(&dev_priv->rps.hw_lock);
4366         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4367         val &= ~DSPFREQGUAR_MASK;
4368         val |= (cmd << DSPFREQGUAR_SHIFT);
4369         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4370         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4371                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4372                      50)) {
4373                 DRM_ERROR("timed out waiting for CDclk change\n");
4374         }
4375         mutex_unlock(&dev_priv->rps.hw_lock);
4376
4377         if (cdclk == 400) {
4378                 u32 divider, vco;
4379
4380                 vco = valleyview_get_vco(dev_priv);
4381                 divider = ((vco << 1) / cdclk) - 1;
4382
4383                 mutex_lock(&dev_priv->dpio_lock);
4384                 /* adjust cdclk divider */
4385                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4386                 val &= ~0xf;
4387                 val |= divider;
4388                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4389                 mutex_unlock(&dev_priv->dpio_lock);
4390         }
4391
4392         mutex_lock(&dev_priv->dpio_lock);
4393         /* adjust self-refresh exit latency value */
4394         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4395         val &= ~0x7f;
4396
4397         /*
4398          * For high bandwidth configs, we set a higher latency in the bunit
4399          * so that the core display fetch happens in time to avoid underruns.
4400          */
4401         if (cdclk == 400)
4402                 val |= 4500 / 250; /* 4.5 usec */
4403         else
4404                 val |= 3000 / 250; /* 3.0 usec */
4405         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4406         mutex_unlock(&dev_priv->dpio_lock);
4407
4408         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4409         intel_i2c_reset(dev);
4410 }
4411
4412 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4413 {
4414         int cur_cdclk, vco;
4415         int divider;
4416
4417         vco = valleyview_get_vco(dev_priv);
4418
4419         mutex_lock(&dev_priv->dpio_lock);
4420         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4421         mutex_unlock(&dev_priv->dpio_lock);
4422
4423         divider &= 0xf;
4424
4425         cur_cdclk = (vco << 1) / (divider + 1);
4426
4427         return cur_cdclk;
4428 }
4429
4430 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4431                                  int max_pixclk)
4432 {
4433         /*
4434          * Really only a few cases to deal with, as only 4 CDclks are supported:
4435          *   200MHz
4436          *   267MHz
4437          *   320MHz
4438          *   400MHz
4439          * So we check to see whether we're above 90% of the lower bin and
4440          * adjust if needed.
4441          */
4442         if (max_pixclk > 288000) {
4443                 return 400;
4444         } else if (max_pixclk > 240000) {
4445                 return 320;
4446         } else
4447                 return 266;
4448         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4449 }
4450
4451 /* compute the max pixel clock for new configuration */
4452 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4453 {
4454         struct drm_device *dev = dev_priv->dev;
4455         struct intel_crtc *intel_crtc;
4456         int max_pixclk = 0;
4457
4458         for_each_intel_crtc(dev, intel_crtc) {
4459                 if (intel_crtc->new_enabled)
4460                         max_pixclk = max(max_pixclk,
4461                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4462         }
4463
4464         return max_pixclk;
4465 }
4466
4467 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4468                                             unsigned *prepare_pipes)
4469 {
4470         struct drm_i915_private *dev_priv = dev->dev_private;
4471         struct intel_crtc *intel_crtc;
4472         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4473
4474         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4475             dev_priv->vlv_cdclk_freq)
4476                 return;
4477
4478         /* disable/enable all currently active pipes while we change cdclk */
4479         for_each_intel_crtc(dev, intel_crtc)
4480                 if (intel_crtc->base.enabled)
4481                         *prepare_pipes |= (1 << intel_crtc->pipe);
4482 }
4483
4484 static void valleyview_modeset_global_resources(struct drm_device *dev)
4485 {
4486         struct drm_i915_private *dev_priv = dev->dev_private;
4487         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4488         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4489
4490         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4491                 valleyview_set_cdclk(dev, req_cdclk);
4492         modeset_update_crtc_power_domains(dev);
4493 }
4494
4495 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4496 {
4497         struct drm_device *dev = crtc->dev;
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4500         struct intel_encoder *encoder;
4501         int pipe = intel_crtc->pipe;
4502         int plane = intel_crtc->plane;
4503         bool is_dsi;
4504         u32 dspcntr;
4505
4506         WARN_ON(!crtc->enabled);
4507
4508         if (intel_crtc->active)
4509                 return;
4510
4511         /* Set up the display plane register */
4512         dspcntr = DISPPLANE_GAMMA_ENABLE;
4513
4514         if (intel_crtc->config.has_dp_encoder)
4515                 intel_dp_set_m_n(intel_crtc);
4516
4517         intel_set_pipe_timings(intel_crtc);
4518
4519         /* pipesrc and dspsize control the size that is scaled from,
4520          * which should always be the user's requested size.
4521          */
4522         I915_WRITE(DSPSIZE(plane),
4523                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4524                    (intel_crtc->config.pipe_src_w - 1));
4525         I915_WRITE(DSPPOS(plane), 0);
4526
4527         i9xx_set_pipeconf(intel_crtc);
4528
4529         I915_WRITE(DSPCNTR(plane), dspcntr);
4530         POSTING_READ(DSPCNTR(plane));
4531
4532         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4533                                                crtc->x, crtc->y);
4534
4535         intel_crtc->active = true;
4536
4537         for_each_encoder_on_crtc(dev, crtc, encoder)
4538                 if (encoder->pre_pll_enable)
4539                         encoder->pre_pll_enable(encoder);
4540
4541         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4542
4543         if (!is_dsi) {
4544                 if (IS_CHERRYVIEW(dev))
4545                         chv_enable_pll(intel_crtc);
4546                 else
4547                         vlv_enable_pll(intel_crtc);
4548         }
4549
4550         for_each_encoder_on_crtc(dev, crtc, encoder)
4551                 if (encoder->pre_enable)
4552                         encoder->pre_enable(encoder);
4553
4554         i9xx_pfit_enable(intel_crtc);
4555
4556         intel_crtc_load_lut(crtc);
4557
4558         intel_update_watermarks(crtc);
4559         intel_enable_pipe(intel_crtc);
4560         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4561
4562         for_each_encoder_on_crtc(dev, crtc, encoder)
4563                 encoder->enable(encoder);
4564
4565         intel_crtc_enable_planes(crtc);
4566 }
4567
4568 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4573         struct intel_encoder *encoder;
4574         int pipe = intel_crtc->pipe;
4575         int plane = intel_crtc->plane;
4576         u32 dspcntr;
4577
4578         WARN_ON(!crtc->enabled);
4579
4580         if (intel_crtc->active)
4581                 return;
4582
4583         /* Set up the display plane register */
4584         dspcntr = DISPPLANE_GAMMA_ENABLE;
4585
4586         if (pipe == 0)
4587                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4588         else
4589                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4590
4591         if (intel_crtc->config.has_dp_encoder)
4592                 intel_dp_set_m_n(intel_crtc);
4593
4594         intel_set_pipe_timings(intel_crtc);
4595
4596         /* pipesrc and dspsize control the size that is scaled from,
4597          * which should always be the user's requested size.
4598          */
4599         I915_WRITE(DSPSIZE(plane),
4600                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4601                    (intel_crtc->config.pipe_src_w - 1));
4602         I915_WRITE(DSPPOS(plane), 0);
4603
4604         i9xx_set_pipeconf(intel_crtc);
4605
4606         I915_WRITE(DSPCNTR(plane), dspcntr);
4607         POSTING_READ(DSPCNTR(plane));
4608
4609         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4610                                                crtc->x, crtc->y);
4611
4612         intel_crtc->active = true;
4613
4614         for_each_encoder_on_crtc(dev, crtc, encoder)
4615                 if (encoder->pre_enable)
4616                         encoder->pre_enable(encoder);
4617
4618         i9xx_enable_pll(intel_crtc);
4619
4620         i9xx_pfit_enable(intel_crtc);
4621
4622         intel_crtc_load_lut(crtc);
4623
4624         intel_update_watermarks(crtc);
4625         intel_enable_pipe(intel_crtc);
4626         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4627
4628         for_each_encoder_on_crtc(dev, crtc, encoder)
4629                 encoder->enable(encoder);
4630
4631         intel_crtc_enable_planes(crtc);
4632 }
4633
4634 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4635 {
4636         struct drm_device *dev = crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639         if (!crtc->config.gmch_pfit.control)
4640                 return;
4641
4642         assert_pipe_disabled(dev_priv, crtc->pipe);
4643
4644         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4645                          I915_READ(PFIT_CONTROL));
4646         I915_WRITE(PFIT_CONTROL, 0);
4647 }
4648
4649 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4650 {
4651         struct drm_device *dev = crtc->dev;
4652         struct drm_i915_private *dev_priv = dev->dev_private;
4653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4654         struct intel_encoder *encoder;
4655         int pipe = intel_crtc->pipe;
4656
4657         if (!intel_crtc->active)
4658                 return;
4659
4660         intel_crtc_disable_planes(crtc);
4661
4662         for_each_encoder_on_crtc(dev, crtc, encoder)
4663                 encoder->disable(encoder);
4664
4665         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4666         intel_disable_pipe(dev_priv, pipe);
4667
4668         i9xx_pfit_disable(intel_crtc);
4669
4670         for_each_encoder_on_crtc(dev, crtc, encoder)
4671                 if (encoder->post_disable)
4672                         encoder->post_disable(encoder);
4673
4674         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4675                 if (IS_CHERRYVIEW(dev))
4676                         chv_disable_pll(dev_priv, pipe);
4677                 else if (IS_VALLEYVIEW(dev))
4678                         vlv_disable_pll(dev_priv, pipe);
4679                 else
4680                         i9xx_disable_pll(dev_priv, pipe);
4681         }
4682
4683         intel_crtc->active = false;
4684         intel_update_watermarks(crtc);
4685
4686         mutex_lock(&dev->struct_mutex);
4687         intel_update_fbc(dev);
4688         intel_edp_psr_update(dev);
4689         mutex_unlock(&dev->struct_mutex);
4690 }
4691
4692 static void i9xx_crtc_off(struct drm_crtc *crtc)
4693 {
4694 }
4695
4696 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4697                                     bool enabled)
4698 {
4699         struct drm_device *dev = crtc->dev;
4700         struct drm_i915_master_private *master_priv;
4701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702         int pipe = intel_crtc->pipe;
4703
4704         if (!dev->primary->master)
4705                 return;
4706
4707         master_priv = dev->primary->master->driver_priv;
4708         if (!master_priv->sarea_priv)
4709                 return;
4710
4711         switch (pipe) {
4712         case 0:
4713                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4714                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4715                 break;
4716         case 1:
4717                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4718                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4719                 break;
4720         default:
4721                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4722                 break;
4723         }
4724 }
4725
4726 /**
4727  * Sets the power management mode of the pipe and plane.
4728  */
4729 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4730 {
4731         struct drm_device *dev = crtc->dev;
4732         struct drm_i915_private *dev_priv = dev->dev_private;
4733         struct intel_encoder *intel_encoder;
4734         bool enable = false;
4735
4736         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4737                 enable |= intel_encoder->connectors_active;
4738
4739         if (enable)
4740                 dev_priv->display.crtc_enable(crtc);
4741         else
4742                 dev_priv->display.crtc_disable(crtc);
4743
4744         intel_crtc_update_sarea(crtc, enable);
4745 }
4746
4747 static void intel_crtc_disable(struct drm_crtc *crtc)
4748 {
4749         struct drm_device *dev = crtc->dev;
4750         struct drm_connector *connector;
4751         struct drm_i915_private *dev_priv = dev->dev_private;
4752
4753         /* crtc should still be enabled when we disable it. */
4754         WARN_ON(!crtc->enabled);
4755
4756         dev_priv->display.crtc_disable(crtc);
4757         intel_crtc_update_sarea(crtc, false);
4758         dev_priv->display.off(crtc);
4759
4760         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4761         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4762         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4763
4764         if (crtc->primary->fb) {
4765                 mutex_lock(&dev->struct_mutex);
4766                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4767                 mutex_unlock(&dev->struct_mutex);
4768                 crtc->primary->fb = NULL;
4769         }
4770
4771         /* Update computed state. */
4772         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4773                 if (!connector->encoder || !connector->encoder->crtc)
4774                         continue;
4775
4776                 if (connector->encoder->crtc != crtc)
4777                         continue;
4778
4779                 connector->dpms = DRM_MODE_DPMS_OFF;
4780                 to_intel_encoder(connector->encoder)->connectors_active = false;
4781         }
4782 }
4783
4784 void intel_encoder_destroy(struct drm_encoder *encoder)
4785 {
4786         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4787
4788         drm_encoder_cleanup(encoder);
4789         kfree(intel_encoder);
4790 }
4791
4792 /* Simple dpms helper for encoders with just one connector, no cloning and only
4793  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4794  * state of the entire output pipe. */
4795 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4796 {
4797         if (mode == DRM_MODE_DPMS_ON) {
4798                 encoder->connectors_active = true;
4799
4800                 intel_crtc_update_dpms(encoder->base.crtc);
4801         } else {
4802                 encoder->connectors_active = false;
4803
4804                 intel_crtc_update_dpms(encoder->base.crtc);
4805         }
4806 }
4807
4808 /* Cross check the actual hw state with our own modeset state tracking (and it's
4809  * internal consistency). */
4810 static void intel_connector_check_state(struct intel_connector *connector)
4811 {
4812         if (connector->get_hw_state(connector)) {
4813                 struct intel_encoder *encoder = connector->encoder;
4814                 struct drm_crtc *crtc;
4815                 bool encoder_enabled;
4816                 enum pipe pipe;
4817
4818                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4819                               connector->base.base.id,
4820                               drm_get_connector_name(&connector->base));
4821
4822                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4823                      "wrong connector dpms state\n");
4824                 WARN(connector->base.encoder != &encoder->base,
4825                      "active connector not linked to encoder\n");
4826                 WARN(!encoder->connectors_active,
4827                      "encoder->connectors_active not set\n");
4828
4829                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4830                 WARN(!encoder_enabled, "encoder not enabled\n");
4831                 if (WARN_ON(!encoder->base.crtc))
4832                         return;
4833
4834                 crtc = encoder->base.crtc;
4835
4836                 WARN(!crtc->enabled, "crtc not enabled\n");
4837                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4838                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4839                      "encoder active on the wrong pipe\n");
4840         }
4841 }
4842
4843 /* Even simpler default implementation, if there's really no special case to
4844  * consider. */
4845 void intel_connector_dpms(struct drm_connector *connector, int mode)
4846 {
4847         /* All the simple cases only support two dpms states. */
4848         if (mode != DRM_MODE_DPMS_ON)
4849                 mode = DRM_MODE_DPMS_OFF;
4850
4851         if (mode == connector->dpms)
4852                 return;
4853
4854         connector->dpms = mode;
4855
4856         /* Only need to change hw state when actually enabled */
4857         if (connector->encoder)
4858                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4859
4860         intel_modeset_check_state(connector->dev);
4861 }
4862
4863 /* Simple connector->get_hw_state implementation for encoders that support only
4864  * one connector and no cloning and hence the encoder state determines the state
4865  * of the connector. */
4866 bool intel_connector_get_hw_state(struct intel_connector *connector)
4867 {
4868         enum pipe pipe = 0;
4869         struct intel_encoder *encoder = connector->encoder;
4870
4871         return encoder->get_hw_state(encoder, &pipe);
4872 }
4873
4874 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4875                                      struct intel_crtc_config *pipe_config)
4876 {
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct intel_crtc *pipe_B_crtc =
4879                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4880
4881         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4882                       pipe_name(pipe), pipe_config->fdi_lanes);
4883         if (pipe_config->fdi_lanes > 4) {
4884                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4885                               pipe_name(pipe), pipe_config->fdi_lanes);
4886                 return false;
4887         }
4888
4889         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4890                 if (pipe_config->fdi_lanes > 2) {
4891                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4892                                       pipe_config->fdi_lanes);
4893                         return false;
4894                 } else {
4895                         return true;
4896                 }
4897         }
4898
4899         if (INTEL_INFO(dev)->num_pipes == 2)
4900                 return true;
4901
4902         /* Ivybridge 3 pipe is really complicated */
4903         switch (pipe) {
4904         case PIPE_A:
4905                 return true;
4906         case PIPE_B:
4907                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4908                     pipe_config->fdi_lanes > 2) {
4909                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4910                                       pipe_name(pipe), pipe_config->fdi_lanes);
4911                         return false;
4912                 }
4913                 return true;
4914         case PIPE_C:
4915                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4916                     pipe_B_crtc->config.fdi_lanes <= 2) {
4917                         if (pipe_config->fdi_lanes > 2) {
4918                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4919                                               pipe_name(pipe), pipe_config->fdi_lanes);
4920                                 return false;
4921                         }
4922                 } else {
4923                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4924                         return false;
4925                 }
4926                 return true;
4927         default:
4928                 BUG();
4929         }
4930 }
4931
4932 #define RETRY 1
4933 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4934                                        struct intel_crtc_config *pipe_config)
4935 {
4936         struct drm_device *dev = intel_crtc->base.dev;
4937         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4938         int lane, link_bw, fdi_dotclock;
4939         bool setup_ok, needs_recompute = false;
4940
4941 retry:
4942         /* FDI is a binary signal running at ~2.7GHz, encoding
4943          * each output octet as 10 bits. The actual frequency
4944          * is stored as a divider into a 100MHz clock, and the
4945          * mode pixel clock is stored in units of 1KHz.
4946          * Hence the bw of each lane in terms of the mode signal
4947          * is:
4948          */
4949         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4950
4951         fdi_dotclock = adjusted_mode->crtc_clock;
4952
4953         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4954                                            pipe_config->pipe_bpp);
4955
4956         pipe_config->fdi_lanes = lane;
4957
4958         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4959                                link_bw, &pipe_config->fdi_m_n);
4960
4961         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4962                                             intel_crtc->pipe, pipe_config);
4963         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4964                 pipe_config->pipe_bpp -= 2*3;
4965                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4966                               pipe_config->pipe_bpp);
4967                 needs_recompute = true;
4968                 pipe_config->bw_constrained = true;
4969
4970                 goto retry;
4971         }
4972
4973         if (needs_recompute)
4974                 return RETRY;
4975
4976         return setup_ok ? 0 : -EINVAL;
4977 }
4978
4979 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4980                                    struct intel_crtc_config *pipe_config)
4981 {
4982         pipe_config->ips_enabled = i915.enable_ips &&
4983                                    hsw_crtc_supports_ips(crtc) &&
4984                                    pipe_config->pipe_bpp <= 24;
4985 }
4986
4987 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4988                                      struct intel_crtc_config *pipe_config)
4989 {
4990         struct drm_device *dev = crtc->base.dev;
4991         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4992
4993         /* FIXME should check pixel clock limits on all platforms */
4994         if (INTEL_INFO(dev)->gen < 4) {
4995                 struct drm_i915_private *dev_priv = dev->dev_private;
4996                 int clock_limit =
4997                         dev_priv->display.get_display_clock_speed(dev);
4998
4999                 /*
5000                  * Enable pixel doubling when the dot clock
5001                  * is > 90% of the (display) core speed.
5002                  *
5003                  * GDG double wide on either pipe,
5004                  * otherwise pipe A only.
5005                  */
5006                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5007                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5008                         clock_limit *= 2;
5009                         pipe_config->double_wide = true;
5010                 }
5011
5012                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5013                         return -EINVAL;
5014         }
5015
5016         /*
5017          * Pipe horizontal size must be even in:
5018          * - DVO ganged mode
5019          * - LVDS dual channel mode
5020          * - Double wide pipe
5021          */
5022         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5023              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5024                 pipe_config->pipe_src_w &= ~1;
5025
5026         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5027          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5028          */
5029         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5030                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5031                 return -EINVAL;
5032
5033         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5034                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5035         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5036                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5037                  * for lvds. */
5038                 pipe_config->pipe_bpp = 8*3;
5039         }
5040
5041         if (HAS_IPS(dev))
5042                 hsw_compute_ips_config(crtc, pipe_config);
5043
5044         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5045          * clock survives for now. */
5046         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5047                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5048
5049         if (pipe_config->has_pch_encoder)
5050                 return ironlake_fdi_compute_config(crtc, pipe_config);
5051
5052         return 0;
5053 }
5054
5055 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5056 {
5057         return 400000; /* FIXME */
5058 }
5059
5060 static int i945_get_display_clock_speed(struct drm_device *dev)
5061 {
5062         return 400000;
5063 }
5064
5065 static int i915_get_display_clock_speed(struct drm_device *dev)
5066 {
5067         return 333000;
5068 }
5069
5070 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5071 {
5072         return 200000;
5073 }
5074
5075 static int pnv_get_display_clock_speed(struct drm_device *dev)
5076 {
5077         u16 gcfgc = 0;
5078
5079         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5080
5081         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5082         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5083                 return 267000;
5084         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5085                 return 333000;
5086         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5087                 return 444000;
5088         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5089                 return 200000;
5090         default:
5091                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5092         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5093                 return 133000;
5094         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5095                 return 167000;
5096         }
5097 }
5098
5099 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5100 {
5101         u16 gcfgc = 0;
5102
5103         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5104
5105         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5106                 return 133000;
5107         else {
5108                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5109                 case GC_DISPLAY_CLOCK_333_MHZ:
5110                         return 333000;
5111                 default:
5112                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5113                         return 190000;
5114                 }
5115         }
5116 }
5117
5118 static int i865_get_display_clock_speed(struct drm_device *dev)
5119 {
5120         return 266000;
5121 }
5122
5123 static int i855_get_display_clock_speed(struct drm_device *dev)
5124 {
5125         u16 hpllcc = 0;
5126         /* Assume that the hardware is in the high speed state.  This
5127          * should be the default.
5128          */
5129         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5130         case GC_CLOCK_133_200:
5131         case GC_CLOCK_100_200:
5132                 return 200000;
5133         case GC_CLOCK_166_250:
5134                 return 250000;
5135         case GC_CLOCK_100_133:
5136                 return 133000;
5137         }
5138
5139         /* Shouldn't happen */
5140         return 0;
5141 }
5142
5143 static int i830_get_display_clock_speed(struct drm_device *dev)
5144 {
5145         return 133000;
5146 }
5147
5148 static void
5149 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5150 {
5151         while (*num > DATA_LINK_M_N_MASK ||
5152                *den > DATA_LINK_M_N_MASK) {
5153                 *num >>= 1;
5154                 *den >>= 1;
5155         }
5156 }
5157
5158 static void compute_m_n(unsigned int m, unsigned int n,
5159                         uint32_t *ret_m, uint32_t *ret_n)
5160 {
5161         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5162         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5163         intel_reduce_m_n_ratio(ret_m, ret_n);
5164 }
5165
5166 void
5167 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5168                        int pixel_clock, int link_clock,
5169                        struct intel_link_m_n *m_n)
5170 {
5171         m_n->tu = 64;
5172
5173         compute_m_n(bits_per_pixel * pixel_clock,
5174                     link_clock * nlanes * 8,
5175                     &m_n->gmch_m, &m_n->gmch_n);
5176
5177         compute_m_n(pixel_clock, link_clock,
5178                     &m_n->link_m, &m_n->link_n);
5179 }
5180
5181 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5182 {
5183         if (i915.panel_use_ssc >= 0)
5184                 return i915.panel_use_ssc != 0;
5185         return dev_priv->vbt.lvds_use_ssc
5186                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5187 }
5188
5189 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5190 {
5191         struct drm_device *dev = crtc->dev;
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193         int refclk;
5194
5195         if (IS_VALLEYVIEW(dev)) {
5196                 refclk = 100000;
5197         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5198             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5199                 refclk = dev_priv->vbt.lvds_ssc_freq;
5200                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5201         } else if (!IS_GEN2(dev)) {
5202                 refclk = 96000;
5203         } else {
5204                 refclk = 48000;
5205         }
5206
5207         return refclk;
5208 }
5209
5210 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5211 {
5212         return (1 << dpll->n) << 16 | dpll->m2;
5213 }
5214
5215 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5216 {
5217         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5218 }
5219
5220 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5221                                      intel_clock_t *reduced_clock)
5222 {
5223         struct drm_device *dev = crtc->base.dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         int pipe = crtc->pipe;
5226         u32 fp, fp2 = 0;
5227
5228         if (IS_PINEVIEW(dev)) {
5229                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5230                 if (reduced_clock)
5231                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5232         } else {
5233                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5234                 if (reduced_clock)
5235                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5236         }
5237
5238         I915_WRITE(FP0(pipe), fp);
5239         crtc->config.dpll_hw_state.fp0 = fp;
5240
5241         crtc->lowfreq_avail = false;
5242         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5243             reduced_clock && i915.powersave) {
5244                 I915_WRITE(FP1(pipe), fp2);
5245                 crtc->config.dpll_hw_state.fp1 = fp2;
5246                 crtc->lowfreq_avail = true;
5247         } else {
5248                 I915_WRITE(FP1(pipe), fp);
5249                 crtc->config.dpll_hw_state.fp1 = fp;
5250         }
5251 }
5252
5253 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5254                 pipe)
5255 {
5256         u32 reg_val;
5257
5258         /*
5259          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5260          * and set it to a reasonable value instead.
5261          */
5262         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5263         reg_val &= 0xffffff00;
5264         reg_val |= 0x00000030;
5265         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5266
5267         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5268         reg_val &= 0x8cffffff;
5269         reg_val = 0x8c000000;
5270         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5271
5272         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5273         reg_val &= 0xffffff00;
5274         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5275
5276         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5277         reg_val &= 0x00ffffff;
5278         reg_val |= 0xb0000000;
5279         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5280 }
5281
5282 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5283                                          struct intel_link_m_n *m_n)
5284 {
5285         struct drm_device *dev = crtc->base.dev;
5286         struct drm_i915_private *dev_priv = dev->dev_private;
5287         int pipe = crtc->pipe;
5288
5289         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5290         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5291         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5292         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5293 }
5294
5295 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5296                                          struct intel_link_m_n *m_n)
5297 {
5298         struct drm_device *dev = crtc->base.dev;
5299         struct drm_i915_private *dev_priv = dev->dev_private;
5300         int pipe = crtc->pipe;
5301         enum transcoder transcoder = crtc->config.cpu_transcoder;
5302
5303         if (INTEL_INFO(dev)->gen >= 5) {
5304                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5305                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5306                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5307                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5308         } else {
5309                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5310                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5311                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5312                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5313         }
5314 }
5315
5316 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5317 {
5318         if (crtc->config.has_pch_encoder)
5319                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5320         else
5321                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5322 }
5323
5324 static void vlv_update_pll(struct intel_crtc *crtc)
5325 {
5326         struct drm_device *dev = crtc->base.dev;
5327         struct drm_i915_private *dev_priv = dev->dev_private;
5328         int pipe = crtc->pipe;
5329         u32 dpll, mdiv;
5330         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5331         u32 coreclk, reg_val, dpll_md;
5332
5333         mutex_lock(&dev_priv->dpio_lock);
5334
5335         bestn = crtc->config.dpll.n;
5336         bestm1 = crtc->config.dpll.m1;
5337         bestm2 = crtc->config.dpll.m2;
5338         bestp1 = crtc->config.dpll.p1;
5339         bestp2 = crtc->config.dpll.p2;
5340
5341         /* See eDP HDMI DPIO driver vbios notes doc */
5342
5343         /* PLL B needs special handling */
5344         if (pipe)
5345                 vlv_pllb_recal_opamp(dev_priv, pipe);
5346
5347         /* Set up Tx target for periodic Rcomp update */
5348         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5349
5350         /* Disable target IRef on PLL */
5351         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5352         reg_val &= 0x00ffffff;
5353         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5354
5355         /* Disable fast lock */
5356         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5357
5358         /* Set idtafcrecal before PLL is enabled */
5359         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5360         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5361         mdiv |= ((bestn << DPIO_N_SHIFT));
5362         mdiv |= (1 << DPIO_K_SHIFT);
5363
5364         /*
5365          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5366          * but we don't support that).
5367          * Note: don't use the DAC post divider as it seems unstable.
5368          */
5369         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5370         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5371
5372         mdiv |= DPIO_ENABLE_CALIBRATION;
5373         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5374
5375         /* Set HBR and RBR LPF coefficients */
5376         if (crtc->config.port_clock == 162000 ||
5377             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5378             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5379                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5380                                  0x009f0003);
5381         else
5382                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5383                                  0x00d0000f);
5384
5385         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5386             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5387                 /* Use SSC source */
5388                 if (!pipe)
5389                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5390                                          0x0df40000);
5391                 else
5392                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5393                                          0x0df70000);
5394         } else { /* HDMI or VGA */
5395                 /* Use bend source */
5396                 if (!pipe)
5397                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5398                                          0x0df70000);
5399                 else
5400                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5401                                          0x0df40000);
5402         }
5403
5404         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5405         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5406         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5407             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5408                 coreclk |= 0x01000000;
5409         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5410
5411         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5412
5413         /*
5414          * Enable DPIO clock input. We should never disable the reference
5415          * clock for pipe B, since VGA hotplug / manual detection depends
5416          * on it.
5417          */
5418         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5419                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5420         /* We should never disable this, set it here for state tracking */
5421         if (pipe == PIPE_B)
5422                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5423         dpll |= DPLL_VCO_ENABLE;
5424         crtc->config.dpll_hw_state.dpll = dpll;
5425
5426         dpll_md = (crtc->config.pixel_multiplier - 1)
5427                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5428         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5429
5430         mutex_unlock(&dev_priv->dpio_lock);
5431 }
5432
5433 static void chv_update_pll(struct intel_crtc *crtc)
5434 {
5435         struct drm_device *dev = crtc->base.dev;
5436         struct drm_i915_private *dev_priv = dev->dev_private;
5437         int pipe = crtc->pipe;
5438         int dpll_reg = DPLL(crtc->pipe);
5439         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5440         u32 val, loopfilter, intcoeff;
5441         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5442         int refclk;
5443
5444         mutex_lock(&dev_priv->dpio_lock);
5445
5446         bestn = crtc->config.dpll.n;
5447         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5448         bestm1 = crtc->config.dpll.m1;
5449         bestm2 = crtc->config.dpll.m2 >> 22;
5450         bestp1 = crtc->config.dpll.p1;
5451         bestp2 = crtc->config.dpll.p2;
5452
5453         /*
5454          * Enable Refclk and SSC
5455          */
5456         val = I915_READ(dpll_reg);
5457         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5458         I915_WRITE(dpll_reg, val);
5459
5460         /* Propagate soft reset to data lane reset */
5461         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5462         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5463         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5464
5465         /* Disable 10bit clock to display controller */
5466         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5467         val &= ~DPIO_DCLKP_EN;
5468         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5469
5470         /* p1 and p2 divider */
5471         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5472                         5 << DPIO_CHV_S1_DIV_SHIFT |
5473                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5474                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5475                         1 << DPIO_CHV_K_DIV_SHIFT);
5476
5477         /* Feedback post-divider - m2 */
5478         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5479
5480         /* Feedback refclk divider - n and m1 */
5481         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5482                         DPIO_CHV_M1_DIV_BY_2 |
5483                         1 << DPIO_CHV_N_DIV_SHIFT);
5484
5485         /* M2 fraction division */
5486         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5487
5488         /* M2 fraction division enable */
5489         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5490                        DPIO_CHV_FRAC_DIV_EN |
5491                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5492
5493         /* Loop filter */
5494         refclk = i9xx_get_refclk(&crtc->base, 0);
5495         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5496                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5497         if (refclk == 100000)
5498                 intcoeff = 11;
5499         else if (refclk == 38400)
5500                 intcoeff = 10;
5501         else
5502                 intcoeff = 9;
5503         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5504         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5505
5506         /* AFC Recal */
5507         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5508                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5509                         DPIO_AFC_RECAL);
5510
5511         mutex_unlock(&dev_priv->dpio_lock);
5512 }
5513
5514 static void i9xx_update_pll(struct intel_crtc *crtc,
5515                             intel_clock_t *reduced_clock,
5516                             int num_connectors)
5517 {
5518         struct drm_device *dev = crtc->base.dev;
5519         struct drm_i915_private *dev_priv = dev->dev_private;
5520         u32 dpll;
5521         bool is_sdvo;
5522         struct dpll *clock = &crtc->config.dpll;
5523
5524         i9xx_update_pll_dividers(crtc, reduced_clock);
5525
5526         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5527                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5528
5529         dpll = DPLL_VGA_MODE_DIS;
5530
5531         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5532                 dpll |= DPLLB_MODE_LVDS;
5533         else
5534                 dpll |= DPLLB_MODE_DAC_SERIAL;
5535
5536         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5537                 dpll |= (crtc->config.pixel_multiplier - 1)
5538                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5539         }
5540
5541         if (is_sdvo)
5542                 dpll |= DPLL_SDVO_HIGH_SPEED;
5543
5544         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5545                 dpll |= DPLL_SDVO_HIGH_SPEED;
5546
5547         /* compute bitmask from p1 value */
5548         if (IS_PINEVIEW(dev))
5549                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5550         else {
5551                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5552                 if (IS_G4X(dev) && reduced_clock)
5553                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5554         }
5555         switch (clock->p2) {
5556         case 5:
5557                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5558                 break;
5559         case 7:
5560                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5561                 break;
5562         case 10:
5563                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5564                 break;
5565         case 14:
5566                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5567                 break;
5568         }
5569         if (INTEL_INFO(dev)->gen >= 4)
5570                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5571
5572         if (crtc->config.sdvo_tv_clock)
5573                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5574         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5575                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5576                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5577         else
5578                 dpll |= PLL_REF_INPUT_DREFCLK;
5579
5580         dpll |= DPLL_VCO_ENABLE;
5581         crtc->config.dpll_hw_state.dpll = dpll;
5582
5583         if (INTEL_INFO(dev)->gen >= 4) {
5584                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5585                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5586                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5587         }
5588 }
5589
5590 static void i8xx_update_pll(struct intel_crtc *crtc,
5591                             intel_clock_t *reduced_clock,
5592                             int num_connectors)
5593 {
5594         struct drm_device *dev = crtc->base.dev;
5595         struct drm_i915_private *dev_priv = dev->dev_private;
5596         u32 dpll;
5597         struct dpll *clock = &crtc->config.dpll;
5598
5599         i9xx_update_pll_dividers(crtc, reduced_clock);
5600
5601         dpll = DPLL_VGA_MODE_DIS;
5602
5603         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5604                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5605         } else {
5606                 if (clock->p1 == 2)
5607                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5608                 else
5609                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5610                 if (clock->p2 == 4)
5611                         dpll |= PLL_P2_DIVIDE_BY_4;
5612         }
5613
5614         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5615                 dpll |= DPLL_DVO_2X_MODE;
5616
5617         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5618                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5619                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5620         else
5621                 dpll |= PLL_REF_INPUT_DREFCLK;
5622
5623         dpll |= DPLL_VCO_ENABLE;
5624         crtc->config.dpll_hw_state.dpll = dpll;
5625 }
5626
5627 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5628 {
5629         struct drm_device *dev = intel_crtc->base.dev;
5630         struct drm_i915_private *dev_priv = dev->dev_private;
5631         enum pipe pipe = intel_crtc->pipe;
5632         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5633         struct drm_display_mode *adjusted_mode =
5634                 &intel_crtc->config.adjusted_mode;
5635         uint32_t crtc_vtotal, crtc_vblank_end;
5636         int vsyncshift = 0;
5637
5638         /* We need to be careful not to changed the adjusted mode, for otherwise
5639          * the hw state checker will get angry at the mismatch. */
5640         crtc_vtotal = adjusted_mode->crtc_vtotal;
5641         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5642
5643         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5644                 /* the chip adds 2 halflines automatically */
5645                 crtc_vtotal -= 1;
5646                 crtc_vblank_end -= 1;
5647
5648                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5649                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5650                 else
5651                         vsyncshift = adjusted_mode->crtc_hsync_start -
5652                                 adjusted_mode->crtc_htotal / 2;
5653                 if (vsyncshift < 0)
5654                         vsyncshift += adjusted_mode->crtc_htotal;
5655         }
5656
5657         if (INTEL_INFO(dev)->gen > 3)
5658                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5659
5660         I915_WRITE(HTOTAL(cpu_transcoder),
5661                    (adjusted_mode->crtc_hdisplay - 1) |
5662                    ((adjusted_mode->crtc_htotal - 1) << 16));
5663         I915_WRITE(HBLANK(cpu_transcoder),
5664                    (adjusted_mode->crtc_hblank_start - 1) |
5665                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5666         I915_WRITE(HSYNC(cpu_transcoder),
5667                    (adjusted_mode->crtc_hsync_start - 1) |
5668                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5669
5670         I915_WRITE(VTOTAL(cpu_transcoder),
5671                    (adjusted_mode->crtc_vdisplay - 1) |
5672                    ((crtc_vtotal - 1) << 16));
5673         I915_WRITE(VBLANK(cpu_transcoder),
5674                    (adjusted_mode->crtc_vblank_start - 1) |
5675                    ((crtc_vblank_end - 1) << 16));
5676         I915_WRITE(VSYNC(cpu_transcoder),
5677                    (adjusted_mode->crtc_vsync_start - 1) |
5678                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5679
5680         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5681          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5682          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5683          * bits. */
5684         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5685             (pipe == PIPE_B || pipe == PIPE_C))
5686                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5687
5688         /* pipesrc controls the size that is scaled from, which should
5689          * always be the user's requested size.
5690          */
5691         I915_WRITE(PIPESRC(pipe),
5692                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5693                    (intel_crtc->config.pipe_src_h - 1));
5694 }
5695
5696 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5697                                    struct intel_crtc_config *pipe_config)
5698 {
5699         struct drm_device *dev = crtc->base.dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5702         uint32_t tmp;
5703
5704         tmp = I915_READ(HTOTAL(cpu_transcoder));
5705         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5706         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5707         tmp = I915_READ(HBLANK(cpu_transcoder));
5708         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5709         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5710         tmp = I915_READ(HSYNC(cpu_transcoder));
5711         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5712         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5713
5714         tmp = I915_READ(VTOTAL(cpu_transcoder));
5715         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5716         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5717         tmp = I915_READ(VBLANK(cpu_transcoder));
5718         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5719         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5720         tmp = I915_READ(VSYNC(cpu_transcoder));
5721         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5722         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5723
5724         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5725                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5726                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5727                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5728         }
5729
5730         tmp = I915_READ(PIPESRC(crtc->pipe));
5731         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5732         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5733
5734         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5735         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5736 }
5737
5738 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5739                                  struct intel_crtc_config *pipe_config)
5740 {
5741         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5742         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5743         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5744         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5745
5746         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5747         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5748         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5749         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5750
5751         mode->flags = pipe_config->adjusted_mode.flags;
5752
5753         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5754         mode->flags |= pipe_config->adjusted_mode.flags;
5755 }
5756
5757 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5758 {
5759         struct drm_device *dev = intel_crtc->base.dev;
5760         struct drm_i915_private *dev_priv = dev->dev_private;
5761         uint32_t pipeconf;
5762
5763         pipeconf = 0;
5764
5765         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5766             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5767                 pipeconf |= PIPECONF_ENABLE;
5768
5769         if (intel_crtc->config.double_wide)
5770                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5771
5772         /* only g4x and later have fancy bpc/dither controls */
5773         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5774                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5775                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5776                         pipeconf |= PIPECONF_DITHER_EN |
5777                                     PIPECONF_DITHER_TYPE_SP;
5778
5779                 switch (intel_crtc->config.pipe_bpp) {
5780                 case 18:
5781                         pipeconf |= PIPECONF_6BPC;
5782                         break;
5783                 case 24:
5784                         pipeconf |= PIPECONF_8BPC;
5785                         break;
5786                 case 30:
5787                         pipeconf |= PIPECONF_10BPC;
5788                         break;
5789                 default:
5790                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5791                         BUG();
5792                 }
5793         }
5794
5795         if (HAS_PIPE_CXSR(dev)) {
5796                 if (intel_crtc->lowfreq_avail) {
5797                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5798                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5799                 } else {
5800                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5801                 }
5802         }
5803
5804         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5805                 if (INTEL_INFO(dev)->gen < 4 ||
5806                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5807                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5808                 else
5809                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5810         } else
5811                 pipeconf |= PIPECONF_PROGRESSIVE;
5812
5813         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5814                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5815
5816         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5817         POSTING_READ(PIPECONF(intel_crtc->pipe));
5818 }
5819
5820 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5821                               int x, int y,
5822                               struct drm_framebuffer *fb)
5823 {
5824         struct drm_device *dev = crtc->dev;
5825         struct drm_i915_private *dev_priv = dev->dev_private;
5826         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5827         int refclk, num_connectors = 0;
5828         intel_clock_t clock, reduced_clock;
5829         bool ok, has_reduced_clock = false;
5830         bool is_lvds = false, is_dsi = false;
5831         struct intel_encoder *encoder;
5832         const intel_limit_t *limit;
5833
5834         for_each_encoder_on_crtc(dev, crtc, encoder) {
5835                 switch (encoder->type) {
5836                 case INTEL_OUTPUT_LVDS:
5837                         is_lvds = true;
5838                         break;
5839                 case INTEL_OUTPUT_DSI:
5840                         is_dsi = true;
5841                         break;
5842                 }
5843
5844                 num_connectors++;
5845         }
5846
5847         if (is_dsi)
5848                 return 0;
5849
5850         if (!intel_crtc->config.clock_set) {
5851                 refclk = i9xx_get_refclk(crtc, num_connectors);
5852
5853                 /*
5854                  * Returns a set of divisors for the desired target clock with
5855                  * the given refclk, or FALSE.  The returned values represent
5856                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5857                  * 2) / p1 / p2.
5858                  */
5859                 limit = intel_limit(crtc, refclk);
5860                 ok = dev_priv->display.find_dpll(limit, crtc,
5861                                                  intel_crtc->config.port_clock,
5862                                                  refclk, NULL, &clock);
5863                 if (!ok) {
5864                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5865                         return -EINVAL;
5866                 }
5867
5868                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5869                         /*
5870                          * Ensure we match the reduced clock's P to the target
5871                          * clock.  If the clocks don't match, we can't switch
5872                          * the display clock by using the FP0/FP1. In such case
5873                          * we will disable the LVDS downclock feature.
5874                          */
5875                         has_reduced_clock =
5876                                 dev_priv->display.find_dpll(limit, crtc,
5877                                                             dev_priv->lvds_downclock,
5878                                                             refclk, &clock,
5879                                                             &reduced_clock);
5880                 }
5881                 /* Compat-code for transition, will disappear. */
5882                 intel_crtc->config.dpll.n = clock.n;
5883                 intel_crtc->config.dpll.m1 = clock.m1;
5884                 intel_crtc->config.dpll.m2 = clock.m2;
5885                 intel_crtc->config.dpll.p1 = clock.p1;
5886                 intel_crtc->config.dpll.p2 = clock.p2;
5887         }
5888
5889         if (IS_GEN2(dev)) {
5890                 i8xx_update_pll(intel_crtc,
5891                                 has_reduced_clock ? &reduced_clock : NULL,
5892                                 num_connectors);
5893         } else if (IS_CHERRYVIEW(dev)) {
5894                 chv_update_pll(intel_crtc);
5895         } else if (IS_VALLEYVIEW(dev)) {
5896                 vlv_update_pll(intel_crtc);
5897         } else {
5898                 i9xx_update_pll(intel_crtc,
5899                                 has_reduced_clock ? &reduced_clock : NULL,
5900                                 num_connectors);
5901         }
5902
5903         return 0;
5904 }
5905
5906 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5907                                  struct intel_crtc_config *pipe_config)
5908 {
5909         struct drm_device *dev = crtc->base.dev;
5910         struct drm_i915_private *dev_priv = dev->dev_private;
5911         uint32_t tmp;
5912
5913         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5914                 return;
5915
5916         tmp = I915_READ(PFIT_CONTROL);
5917         if (!(tmp & PFIT_ENABLE))
5918                 return;
5919
5920         /* Check whether the pfit is attached to our pipe. */
5921         if (INTEL_INFO(dev)->gen < 4) {
5922                 if (crtc->pipe != PIPE_B)
5923                         return;
5924         } else {
5925                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5926                         return;
5927         }
5928
5929         pipe_config->gmch_pfit.control = tmp;
5930         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5931         if (INTEL_INFO(dev)->gen < 5)
5932                 pipe_config->gmch_pfit.lvds_border_bits =
5933                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5934 }
5935
5936 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5937                                struct intel_crtc_config *pipe_config)
5938 {
5939         struct drm_device *dev = crtc->base.dev;
5940         struct drm_i915_private *dev_priv = dev->dev_private;
5941         int pipe = pipe_config->cpu_transcoder;
5942         intel_clock_t clock;
5943         u32 mdiv;
5944         int refclk = 100000;
5945
5946         mutex_lock(&dev_priv->dpio_lock);
5947         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5948         mutex_unlock(&dev_priv->dpio_lock);
5949
5950         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5951         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5952         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5953         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5954         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5955
5956         vlv_clock(refclk, &clock);
5957
5958         /* clock.dot is the fast clock */
5959         pipe_config->port_clock = clock.dot / 5;
5960 }
5961
5962 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5963                                   struct intel_plane_config *plane_config)
5964 {
5965         struct drm_device *dev = crtc->base.dev;
5966         struct drm_i915_private *dev_priv = dev->dev_private;
5967         u32 val, base, offset;
5968         int pipe = crtc->pipe, plane = crtc->plane;
5969         int fourcc, pixel_format;
5970         int aligned_height;
5971
5972         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5973         if (!crtc->base.primary->fb) {
5974                 DRM_DEBUG_KMS("failed to alloc fb\n");
5975                 return;
5976         }
5977
5978         val = I915_READ(DSPCNTR(plane));
5979
5980         if (INTEL_INFO(dev)->gen >= 4)
5981                 if (val & DISPPLANE_TILED)
5982                         plane_config->tiled = true;
5983
5984         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5985         fourcc = intel_format_to_fourcc(pixel_format);
5986         crtc->base.primary->fb->pixel_format = fourcc;
5987         crtc->base.primary->fb->bits_per_pixel =
5988                 drm_format_plane_cpp(fourcc, 0) * 8;
5989
5990         if (INTEL_INFO(dev)->gen >= 4) {
5991                 if (plane_config->tiled)
5992                         offset = I915_READ(DSPTILEOFF(plane));
5993                 else
5994                         offset = I915_READ(DSPLINOFF(plane));
5995                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5996         } else {
5997                 base = I915_READ(DSPADDR(plane));
5998         }
5999         plane_config->base = base;
6000
6001         val = I915_READ(PIPESRC(pipe));
6002         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6003         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6004
6005         val = I915_READ(DSPSTRIDE(pipe));
6006         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6007
6008         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6009                                             plane_config->tiled);
6010
6011         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6012                                    aligned_height, PAGE_SIZE);
6013
6014         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6015                       pipe, plane, crtc->base.primary->fb->width,
6016                       crtc->base.primary->fb->height,
6017                       crtc->base.primary->fb->bits_per_pixel, base,
6018                       crtc->base.primary->fb->pitches[0],
6019                       plane_config->size);
6020
6021 }
6022
6023 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6024                                struct intel_crtc_config *pipe_config)
6025 {
6026         struct drm_device *dev = crtc->base.dev;
6027         struct drm_i915_private *dev_priv = dev->dev_private;
6028         int pipe = pipe_config->cpu_transcoder;
6029         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6030         intel_clock_t clock;
6031         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6032         int refclk = 100000;
6033
6034         mutex_lock(&dev_priv->dpio_lock);
6035         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6036         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6037         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6038         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6039         mutex_unlock(&dev_priv->dpio_lock);
6040
6041         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6042         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6043         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6044         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6045         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6046
6047         chv_clock(refclk, &clock);
6048
6049         /* clock.dot is the fast clock */
6050         pipe_config->port_clock = clock.dot / 5;
6051 }
6052
6053 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6054                                  struct intel_crtc_config *pipe_config)
6055 {
6056         struct drm_device *dev = crtc->base.dev;
6057         struct drm_i915_private *dev_priv = dev->dev_private;
6058         uint32_t tmp;
6059
6060         if (!intel_display_power_enabled(dev_priv,
6061                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6062                 return false;
6063
6064         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6065         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6066
6067         tmp = I915_READ(PIPECONF(crtc->pipe));
6068         if (!(tmp & PIPECONF_ENABLE))
6069                 return false;
6070
6071         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6072                 switch (tmp & PIPECONF_BPC_MASK) {
6073                 case PIPECONF_6BPC:
6074                         pipe_config->pipe_bpp = 18;
6075                         break;
6076                 case PIPECONF_8BPC:
6077                         pipe_config->pipe_bpp = 24;
6078                         break;
6079                 case PIPECONF_10BPC:
6080                         pipe_config->pipe_bpp = 30;
6081                         break;
6082                 default:
6083                         break;
6084                 }
6085         }
6086
6087         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6088                 pipe_config->limited_color_range = true;
6089
6090         if (INTEL_INFO(dev)->gen < 4)
6091                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6092
6093         intel_get_pipe_timings(crtc, pipe_config);
6094
6095         i9xx_get_pfit_config(crtc, pipe_config);
6096
6097         if (INTEL_INFO(dev)->gen >= 4) {
6098                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6099                 pipe_config->pixel_multiplier =
6100                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6101                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6102                 pipe_config->dpll_hw_state.dpll_md = tmp;
6103         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6104                 tmp = I915_READ(DPLL(crtc->pipe));
6105                 pipe_config->pixel_multiplier =
6106                         ((tmp & SDVO_MULTIPLIER_MASK)
6107                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6108         } else {
6109                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6110                  * port and will be fixed up in the encoder->get_config
6111                  * function. */
6112                 pipe_config->pixel_multiplier = 1;
6113         }
6114         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6115         if (!IS_VALLEYVIEW(dev)) {
6116                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6117                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6118         } else {
6119                 /* Mask out read-only status bits. */
6120                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6121                                                      DPLL_PORTC_READY_MASK |
6122                                                      DPLL_PORTB_READY_MASK);
6123         }
6124
6125         if (IS_CHERRYVIEW(dev))
6126                 chv_crtc_clock_get(crtc, pipe_config);
6127         else if (IS_VALLEYVIEW(dev))
6128                 vlv_crtc_clock_get(crtc, pipe_config);
6129         else
6130                 i9xx_crtc_clock_get(crtc, pipe_config);
6131
6132         return true;
6133 }
6134
6135 static void ironlake_init_pch_refclk(struct drm_device *dev)
6136 {
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138         struct drm_mode_config *mode_config = &dev->mode_config;
6139         struct intel_encoder *encoder;
6140         u32 val, final;
6141         bool has_lvds = false;
6142         bool has_cpu_edp = false;
6143         bool has_panel = false;
6144         bool has_ck505 = false;
6145         bool can_ssc = false;
6146
6147         /* We need to take the global config into account */
6148         list_for_each_entry(encoder, &mode_config->encoder_list,
6149                             base.head) {
6150                 switch (encoder->type) {
6151                 case INTEL_OUTPUT_LVDS:
6152                         has_panel = true;
6153                         has_lvds = true;
6154                         break;
6155                 case INTEL_OUTPUT_EDP:
6156                         has_panel = true;
6157                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6158                                 has_cpu_edp = true;
6159                         break;
6160                 }
6161         }
6162
6163         if (HAS_PCH_IBX(dev)) {
6164                 has_ck505 = dev_priv->vbt.display_clock_mode;
6165                 can_ssc = has_ck505;
6166         } else {
6167                 has_ck505 = false;
6168                 can_ssc = true;
6169         }
6170
6171         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6172                       has_panel, has_lvds, has_ck505);
6173
6174         /* Ironlake: try to setup display ref clock before DPLL
6175          * enabling. This is only under driver's control after
6176          * PCH B stepping, previous chipset stepping should be
6177          * ignoring this setting.
6178          */
6179         val = I915_READ(PCH_DREF_CONTROL);
6180
6181         /* As we must carefully and slowly disable/enable each source in turn,
6182          * compute the final state we want first and check if we need to
6183          * make any changes at all.
6184          */
6185         final = val;
6186         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6187         if (has_ck505)
6188                 final |= DREF_NONSPREAD_CK505_ENABLE;
6189         else
6190                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6191
6192         final &= ~DREF_SSC_SOURCE_MASK;
6193         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6194         final &= ~DREF_SSC1_ENABLE;
6195
6196         if (has_panel) {
6197                 final |= DREF_SSC_SOURCE_ENABLE;
6198
6199                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6200                         final |= DREF_SSC1_ENABLE;
6201
6202                 if (has_cpu_edp) {
6203                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6204                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6205                         else
6206                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6207                 } else
6208                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6209         } else {
6210                 final |= DREF_SSC_SOURCE_DISABLE;
6211                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6212         }
6213
6214         if (final == val)
6215                 return;
6216
6217         /* Always enable nonspread source */
6218         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6219
6220         if (has_ck505)
6221                 val |= DREF_NONSPREAD_CK505_ENABLE;
6222         else
6223                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6224
6225         if (has_panel) {
6226                 val &= ~DREF_SSC_SOURCE_MASK;
6227                 val |= DREF_SSC_SOURCE_ENABLE;
6228
6229                 /* SSC must be turned on before enabling the CPU output  */
6230                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6231                         DRM_DEBUG_KMS("Using SSC on panel\n");
6232                         val |= DREF_SSC1_ENABLE;
6233                 } else
6234                         val &= ~DREF_SSC1_ENABLE;
6235
6236                 /* Get SSC going before enabling the outputs */
6237                 I915_WRITE(PCH_DREF_CONTROL, val);
6238                 POSTING_READ(PCH_DREF_CONTROL);
6239                 udelay(200);
6240
6241                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6242
6243                 /* Enable CPU source on CPU attached eDP */
6244                 if (has_cpu_edp) {
6245                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6246                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6247                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6248                         } else
6249                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6250                 } else
6251                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6252
6253                 I915_WRITE(PCH_DREF_CONTROL, val);
6254                 POSTING_READ(PCH_DREF_CONTROL);
6255                 udelay(200);
6256         } else {
6257                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6258
6259                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6260
6261                 /* Turn off CPU output */
6262                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6263
6264                 I915_WRITE(PCH_DREF_CONTROL, val);
6265                 POSTING_READ(PCH_DREF_CONTROL);
6266                 udelay(200);
6267
6268                 /* Turn off the SSC source */
6269                 val &= ~DREF_SSC_SOURCE_MASK;
6270                 val |= DREF_SSC_SOURCE_DISABLE;
6271
6272                 /* Turn off SSC1 */
6273                 val &= ~DREF_SSC1_ENABLE;
6274
6275                 I915_WRITE(PCH_DREF_CONTROL, val);
6276                 POSTING_READ(PCH_DREF_CONTROL);
6277                 udelay(200);
6278         }
6279
6280         BUG_ON(val != final);
6281 }
6282
6283 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6284 {
6285         uint32_t tmp;
6286
6287         tmp = I915_READ(SOUTH_CHICKEN2);
6288         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6289         I915_WRITE(SOUTH_CHICKEN2, tmp);
6290
6291         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6292                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6293                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6294
6295         tmp = I915_READ(SOUTH_CHICKEN2);
6296         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6297         I915_WRITE(SOUTH_CHICKEN2, tmp);
6298
6299         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6300                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6301                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6302 }
6303
6304 /* WaMPhyProgramming:hsw */
6305 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6306 {
6307         uint32_t tmp;
6308
6309         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6310         tmp &= ~(0xFF << 24);
6311         tmp |= (0x12 << 24);
6312         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6313
6314         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6315         tmp |= (1 << 11);
6316         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6317
6318         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6319         tmp |= (1 << 11);
6320         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6321
6322         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6323         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6324         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6325
6326         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6327         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6328         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6329
6330         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6331         tmp &= ~(7 << 13);
6332         tmp |= (5 << 13);
6333         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6334
6335         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6336         tmp &= ~(7 << 13);
6337         tmp |= (5 << 13);
6338         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6339
6340         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6341         tmp &= ~0xFF;
6342         tmp |= 0x1C;
6343         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6344
6345         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6346         tmp &= ~0xFF;
6347         tmp |= 0x1C;
6348         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6349
6350         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6351         tmp &= ~(0xFF << 16);
6352         tmp |= (0x1C << 16);
6353         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6354
6355         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6356         tmp &= ~(0xFF << 16);
6357         tmp |= (0x1C << 16);
6358         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6359
6360         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6361         tmp |= (1 << 27);
6362         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6363
6364         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6365         tmp |= (1 << 27);
6366         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6367
6368         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6369         tmp &= ~(0xF << 28);
6370         tmp |= (4 << 28);
6371         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6372
6373         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6374         tmp &= ~(0xF << 28);
6375         tmp |= (4 << 28);
6376         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6377 }
6378
6379 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6380  * Programming" based on the parameters passed:
6381  * - Sequence to enable CLKOUT_DP
6382  * - Sequence to enable CLKOUT_DP without spread
6383  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6384  */
6385 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6386                                  bool with_fdi)
6387 {
6388         struct drm_i915_private *dev_priv = dev->dev_private;
6389         uint32_t reg, tmp;
6390
6391         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6392                 with_spread = true;
6393         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6394                  with_fdi, "LP PCH doesn't have FDI\n"))
6395                 with_fdi = false;
6396
6397         mutex_lock(&dev_priv->dpio_lock);
6398
6399         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6400         tmp &= ~SBI_SSCCTL_DISABLE;
6401         tmp |= SBI_SSCCTL_PATHALT;
6402         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6403
6404         udelay(24);
6405
6406         if (with_spread) {
6407                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6408                 tmp &= ~SBI_SSCCTL_PATHALT;
6409                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6410
6411                 if (with_fdi) {
6412                         lpt_reset_fdi_mphy(dev_priv);
6413                         lpt_program_fdi_mphy(dev_priv);
6414                 }
6415         }
6416
6417         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6418                SBI_GEN0 : SBI_DBUFF0;
6419         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6420         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6421         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6422
6423         mutex_unlock(&dev_priv->dpio_lock);
6424 }
6425
6426 /* Sequence to disable CLKOUT_DP */
6427 static void lpt_disable_clkout_dp(struct drm_device *dev)
6428 {
6429         struct drm_i915_private *dev_priv = dev->dev_private;
6430         uint32_t reg, tmp;
6431
6432         mutex_lock(&dev_priv->dpio_lock);
6433
6434         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6435                SBI_GEN0 : SBI_DBUFF0;
6436         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6437         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6438         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6439
6440         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6441         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6442                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6443                         tmp |= SBI_SSCCTL_PATHALT;
6444                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6445                         udelay(32);
6446                 }
6447                 tmp |= SBI_SSCCTL_DISABLE;
6448                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6449         }
6450
6451         mutex_unlock(&dev_priv->dpio_lock);
6452 }
6453
6454 static void lpt_init_pch_refclk(struct drm_device *dev)
6455 {
6456         struct drm_mode_config *mode_config = &dev->mode_config;
6457         struct intel_encoder *encoder;
6458         bool has_vga = false;
6459
6460         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6461                 switch (encoder->type) {
6462                 case INTEL_OUTPUT_ANALOG:
6463                         has_vga = true;
6464                         break;
6465                 }
6466         }
6467
6468         if (has_vga)
6469                 lpt_enable_clkout_dp(dev, true, true);
6470         else
6471                 lpt_disable_clkout_dp(dev);
6472 }
6473
6474 /*
6475  * Initialize reference clocks when the driver loads
6476  */
6477 void intel_init_pch_refclk(struct drm_device *dev)
6478 {
6479         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6480                 ironlake_init_pch_refclk(dev);
6481         else if (HAS_PCH_LPT(dev))
6482                 lpt_init_pch_refclk(dev);
6483 }
6484
6485 static int ironlake_get_refclk(struct drm_crtc *crtc)
6486 {
6487         struct drm_device *dev = crtc->dev;
6488         struct drm_i915_private *dev_priv = dev->dev_private;
6489         struct intel_encoder *encoder;
6490         int num_connectors = 0;
6491         bool is_lvds = false;
6492
6493         for_each_encoder_on_crtc(dev, crtc, encoder) {
6494                 switch (encoder->type) {
6495                 case INTEL_OUTPUT_LVDS:
6496                         is_lvds = true;
6497                         break;
6498                 }
6499                 num_connectors++;
6500         }
6501
6502         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6503                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6504                               dev_priv->vbt.lvds_ssc_freq);
6505                 return dev_priv->vbt.lvds_ssc_freq;
6506         }
6507
6508         return 120000;
6509 }
6510
6511 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6512 {
6513         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6515         int pipe = intel_crtc->pipe;
6516         uint32_t val;
6517
6518         val = 0;
6519
6520         switch (intel_crtc->config.pipe_bpp) {
6521         case 18:
6522                 val |= PIPECONF_6BPC;
6523                 break;
6524         case 24:
6525                 val |= PIPECONF_8BPC;
6526                 break;
6527         case 30:
6528                 val |= PIPECONF_10BPC;
6529                 break;
6530         case 36:
6531                 val |= PIPECONF_12BPC;
6532                 break;
6533         default:
6534                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6535                 BUG();
6536         }
6537
6538         if (intel_crtc->config.dither)
6539                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6540
6541         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6542                 val |= PIPECONF_INTERLACED_ILK;
6543         else
6544                 val |= PIPECONF_PROGRESSIVE;
6545
6546         if (intel_crtc->config.limited_color_range)
6547                 val |= PIPECONF_COLOR_RANGE_SELECT;
6548
6549         I915_WRITE(PIPECONF(pipe), val);
6550         POSTING_READ(PIPECONF(pipe));
6551 }
6552
6553 /*
6554  * Set up the pipe CSC unit.
6555  *
6556  * Currently only full range RGB to limited range RGB conversion
6557  * is supported, but eventually this should handle various
6558  * RGB<->YCbCr scenarios as well.
6559  */
6560 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6561 {
6562         struct drm_device *dev = crtc->dev;
6563         struct drm_i915_private *dev_priv = dev->dev_private;
6564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6565         int pipe = intel_crtc->pipe;
6566         uint16_t coeff = 0x7800; /* 1.0 */
6567
6568         /*
6569          * TODO: Check what kind of values actually come out of the pipe
6570          * with these coeff/postoff values and adjust to get the best
6571          * accuracy. Perhaps we even need to take the bpc value into
6572          * consideration.
6573          */
6574
6575         if (intel_crtc->config.limited_color_range)
6576                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6577
6578         /*
6579          * GY/GU and RY/RU should be the other way around according
6580          * to BSpec, but reality doesn't agree. Just set them up in
6581          * a way that results in the correct picture.
6582          */
6583         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6584         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6585
6586         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6587         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6588
6589         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6590         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6591
6592         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6593         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6594         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6595
6596         if (INTEL_INFO(dev)->gen > 6) {
6597                 uint16_t postoff = 0;
6598
6599                 if (intel_crtc->config.limited_color_range)
6600                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6601
6602                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6603                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6604                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6605
6606                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6607         } else {
6608                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6609
6610                 if (intel_crtc->config.limited_color_range)
6611                         mode |= CSC_BLACK_SCREEN_OFFSET;
6612
6613                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6614         }
6615 }
6616
6617 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6618 {
6619         struct drm_device *dev = crtc->dev;
6620         struct drm_i915_private *dev_priv = dev->dev_private;
6621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6622         enum pipe pipe = intel_crtc->pipe;
6623         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6624         uint32_t val;
6625
6626         val = 0;
6627
6628         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6629                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6630
6631         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6632                 val |= PIPECONF_INTERLACED_ILK;
6633         else
6634                 val |= PIPECONF_PROGRESSIVE;
6635
6636         I915_WRITE(PIPECONF(cpu_transcoder), val);
6637         POSTING_READ(PIPECONF(cpu_transcoder));
6638
6639         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6640         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6641
6642         if (IS_BROADWELL(dev)) {
6643                 val = 0;
6644
6645                 switch (intel_crtc->config.pipe_bpp) {
6646                 case 18:
6647                         val |= PIPEMISC_DITHER_6_BPC;
6648                         break;
6649                 case 24:
6650                         val |= PIPEMISC_DITHER_8_BPC;
6651                         break;
6652                 case 30:
6653                         val |= PIPEMISC_DITHER_10_BPC;
6654                         break;
6655                 case 36:
6656                         val |= PIPEMISC_DITHER_12_BPC;
6657                         break;
6658                 default:
6659                         /* Case prevented by pipe_config_set_bpp. */
6660                         BUG();
6661                 }
6662
6663                 if (intel_crtc->config.dither)
6664                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6665
6666                 I915_WRITE(PIPEMISC(pipe), val);
6667         }
6668 }
6669
6670 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6671                                     intel_clock_t *clock,
6672                                     bool *has_reduced_clock,
6673                                     intel_clock_t *reduced_clock)
6674 {
6675         struct drm_device *dev = crtc->dev;
6676         struct drm_i915_private *dev_priv = dev->dev_private;
6677         struct intel_encoder *intel_encoder;
6678         int refclk;
6679         const intel_limit_t *limit;
6680         bool ret, is_lvds = false;
6681
6682         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6683                 switch (intel_encoder->type) {
6684                 case INTEL_OUTPUT_LVDS:
6685                         is_lvds = true;
6686                         break;
6687                 }
6688         }
6689
6690         refclk = ironlake_get_refclk(crtc);
6691
6692         /*
6693          * Returns a set of divisors for the desired target clock with the given
6694          * refclk, or FALSE.  The returned values represent the clock equation:
6695          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6696          */
6697         limit = intel_limit(crtc, refclk);
6698         ret = dev_priv->display.find_dpll(limit, crtc,
6699                                           to_intel_crtc(crtc)->config.port_clock,
6700                                           refclk, NULL, clock);
6701         if (!ret)
6702                 return false;
6703
6704         if (is_lvds && dev_priv->lvds_downclock_avail) {
6705                 /*
6706                  * Ensure we match the reduced clock's P to the target clock.
6707                  * If the clocks don't match, we can't switch the display clock
6708                  * by using the FP0/FP1. In such case we will disable the LVDS
6709                  * downclock feature.
6710                 */
6711                 *has_reduced_clock =
6712                         dev_priv->display.find_dpll(limit, crtc,
6713                                                     dev_priv->lvds_downclock,
6714                                                     refclk, clock,
6715                                                     reduced_clock);
6716         }
6717
6718         return true;
6719 }
6720
6721 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6722 {
6723         /*
6724          * Account for spread spectrum to avoid
6725          * oversubscribing the link. Max center spread
6726          * is 2.5%; use 5% for safety's sake.
6727          */
6728         u32 bps = target_clock * bpp * 21 / 20;
6729         return DIV_ROUND_UP(bps, link_bw * 8);
6730 }
6731
6732 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6733 {
6734         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6735 }
6736
6737 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6738                                       u32 *fp,
6739                                       intel_clock_t *reduced_clock, u32 *fp2)
6740 {
6741         struct drm_crtc *crtc = &intel_crtc->base;
6742         struct drm_device *dev = crtc->dev;
6743         struct drm_i915_private *dev_priv = dev->dev_private;
6744         struct intel_encoder *intel_encoder;
6745         uint32_t dpll;
6746         int factor, num_connectors = 0;
6747         bool is_lvds = false, is_sdvo = false;
6748
6749         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6750                 switch (intel_encoder->type) {
6751                 case INTEL_OUTPUT_LVDS:
6752                         is_lvds = true;
6753                         break;
6754                 case INTEL_OUTPUT_SDVO:
6755                 case INTEL_OUTPUT_HDMI:
6756                         is_sdvo = true;
6757                         break;
6758                 }
6759
6760                 num_connectors++;
6761         }
6762
6763         /* Enable autotuning of the PLL clock (if permissible) */
6764         factor = 21;
6765         if (is_lvds) {
6766                 if ((intel_panel_use_ssc(dev_priv) &&
6767                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6768                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6769                         factor = 25;
6770         } else if (intel_crtc->config.sdvo_tv_clock)
6771                 factor = 20;
6772
6773         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6774                 *fp |= FP_CB_TUNE;
6775
6776         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6777                 *fp2 |= FP_CB_TUNE;
6778
6779         dpll = 0;
6780
6781         if (is_lvds)
6782                 dpll |= DPLLB_MODE_LVDS;
6783         else
6784                 dpll |= DPLLB_MODE_DAC_SERIAL;
6785
6786         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6787                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6788
6789         if (is_sdvo)
6790                 dpll |= DPLL_SDVO_HIGH_SPEED;
6791         if (intel_crtc->config.has_dp_encoder)
6792                 dpll |= DPLL_SDVO_HIGH_SPEED;
6793
6794         /* compute bitmask from p1 value */
6795         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6796         /* also FPA1 */
6797         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6798
6799         switch (intel_crtc->config.dpll.p2) {
6800         case 5:
6801                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6802                 break;
6803         case 7:
6804                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6805                 break;
6806         case 10:
6807                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6808                 break;
6809         case 14:
6810                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6811                 break;
6812         }
6813
6814         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6815                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6816         else
6817                 dpll |= PLL_REF_INPUT_DREFCLK;
6818
6819         return dpll | DPLL_VCO_ENABLE;
6820 }
6821
6822 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6823                                   int x, int y,
6824                                   struct drm_framebuffer *fb)
6825 {
6826         struct drm_device *dev = crtc->dev;
6827         struct drm_i915_private *dev_priv = dev->dev_private;
6828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6829         int pipe = intel_crtc->pipe;
6830         int plane = intel_crtc->plane;
6831         int num_connectors = 0;
6832         intel_clock_t clock, reduced_clock;
6833         u32 dpll = 0, fp = 0, fp2 = 0;
6834         bool ok, has_reduced_clock = false;
6835         bool is_lvds = false;
6836         struct intel_encoder *encoder;
6837         struct intel_shared_dpll *pll;
6838
6839         for_each_encoder_on_crtc(dev, crtc, encoder) {
6840                 switch (encoder->type) {
6841                 case INTEL_OUTPUT_LVDS:
6842                         is_lvds = true;
6843                         break;
6844                 }
6845
6846                 num_connectors++;
6847         }
6848
6849         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6850              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6851
6852         ok = ironlake_compute_clocks(crtc, &clock,
6853                                      &has_reduced_clock, &reduced_clock);
6854         if (!ok && !intel_crtc->config.clock_set) {
6855                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6856                 return -EINVAL;
6857         }
6858         /* Compat-code for transition, will disappear. */
6859         if (!intel_crtc->config.clock_set) {
6860                 intel_crtc->config.dpll.n = clock.n;
6861                 intel_crtc->config.dpll.m1 = clock.m1;
6862                 intel_crtc->config.dpll.m2 = clock.m2;
6863                 intel_crtc->config.dpll.p1 = clock.p1;
6864                 intel_crtc->config.dpll.p2 = clock.p2;
6865         }
6866
6867         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6868         if (intel_crtc->config.has_pch_encoder) {
6869                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6870                 if (has_reduced_clock)
6871                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6872
6873                 dpll = ironlake_compute_dpll(intel_crtc,
6874                                              &fp, &reduced_clock,
6875                                              has_reduced_clock ? &fp2 : NULL);
6876
6877                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6878                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6879                 if (has_reduced_clock)
6880                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6881                 else
6882                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6883
6884                 pll = intel_get_shared_dpll(intel_crtc);
6885                 if (pll == NULL) {
6886                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6887                                          pipe_name(pipe));
6888                         return -EINVAL;
6889                 }
6890         } else
6891                 intel_put_shared_dpll(intel_crtc);
6892
6893         if (is_lvds && has_reduced_clock && i915.powersave)
6894                 intel_crtc->lowfreq_avail = true;
6895         else
6896                 intel_crtc->lowfreq_avail = false;
6897
6898         if (intel_crtc->config.has_dp_encoder)
6899                 intel_dp_set_m_n(intel_crtc);
6900
6901         intel_set_pipe_timings(intel_crtc);
6902
6903         if (intel_crtc->config.has_pch_encoder) {
6904                 intel_cpu_transcoder_set_m_n(intel_crtc,
6905                                              &intel_crtc->config.fdi_m_n);
6906         }
6907
6908         ironlake_set_pipeconf(crtc);
6909
6910         /* Set up the display plane register */
6911         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6912         POSTING_READ(DSPCNTR(plane));
6913
6914         dev_priv->display.update_primary_plane(crtc, fb, x, y);
6915
6916         return 0;
6917 }
6918
6919 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6920                                          struct intel_link_m_n *m_n)
6921 {
6922         struct drm_device *dev = crtc->base.dev;
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         enum pipe pipe = crtc->pipe;
6925
6926         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6927         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6928         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6929                 & ~TU_SIZE_MASK;
6930         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6931         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6932                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6933 }
6934
6935 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6936                                          enum transcoder transcoder,
6937                                          struct intel_link_m_n *m_n)
6938 {
6939         struct drm_device *dev = crtc->base.dev;
6940         struct drm_i915_private *dev_priv = dev->dev_private;
6941         enum pipe pipe = crtc->pipe;
6942
6943         if (INTEL_INFO(dev)->gen >= 5) {
6944                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6945                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6946                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6947                         & ~TU_SIZE_MASK;
6948                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6949                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6950                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6951         } else {
6952                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6953                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6954                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6955                         & ~TU_SIZE_MASK;
6956                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6957                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6958                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6959         }
6960 }
6961
6962 void intel_dp_get_m_n(struct intel_crtc *crtc,
6963                       struct intel_crtc_config *pipe_config)
6964 {
6965         if (crtc->config.has_pch_encoder)
6966                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6967         else
6968                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6969                                              &pipe_config->dp_m_n);
6970 }
6971
6972 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6973                                         struct intel_crtc_config *pipe_config)
6974 {
6975         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6976                                      &pipe_config->fdi_m_n);
6977 }
6978
6979 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6980                                      struct intel_crtc_config *pipe_config)
6981 {
6982         struct drm_device *dev = crtc->base.dev;
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         uint32_t tmp;
6985
6986         tmp = I915_READ(PF_CTL(crtc->pipe));
6987
6988         if (tmp & PF_ENABLE) {
6989                 pipe_config->pch_pfit.enabled = true;
6990                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6991                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6992
6993                 /* We currently do not free assignements of panel fitters on
6994                  * ivb/hsw (since we don't use the higher upscaling modes which
6995                  * differentiates them) so just WARN about this case for now. */
6996                 if (IS_GEN7(dev)) {
6997                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6998                                 PF_PIPE_SEL_IVB(crtc->pipe));
6999                 }
7000         }
7001 }
7002
7003 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7004                                       struct intel_plane_config *plane_config)
7005 {
7006         struct drm_device *dev = crtc->base.dev;
7007         struct drm_i915_private *dev_priv = dev->dev_private;
7008         u32 val, base, offset;
7009         int pipe = crtc->pipe, plane = crtc->plane;
7010         int fourcc, pixel_format;
7011         int aligned_height;
7012
7013         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7014         if (!crtc->base.primary->fb) {
7015                 DRM_DEBUG_KMS("failed to alloc fb\n");
7016                 return;
7017         }
7018
7019         val = I915_READ(DSPCNTR(plane));
7020
7021         if (INTEL_INFO(dev)->gen >= 4)
7022                 if (val & DISPPLANE_TILED)
7023                         plane_config->tiled = true;
7024
7025         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7026         fourcc = intel_format_to_fourcc(pixel_format);
7027         crtc->base.primary->fb->pixel_format = fourcc;
7028         crtc->base.primary->fb->bits_per_pixel =
7029                 drm_format_plane_cpp(fourcc, 0) * 8;
7030
7031         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7032         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7033                 offset = I915_READ(DSPOFFSET(plane));
7034         } else {
7035                 if (plane_config->tiled)
7036                         offset = I915_READ(DSPTILEOFF(plane));
7037                 else
7038                         offset = I915_READ(DSPLINOFF(plane));
7039         }
7040         plane_config->base = base;
7041
7042         val = I915_READ(PIPESRC(pipe));
7043         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7044         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7045
7046         val = I915_READ(DSPSTRIDE(pipe));
7047         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7048
7049         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7050                                             plane_config->tiled);
7051
7052         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7053                                    aligned_height, PAGE_SIZE);
7054
7055         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7056                       pipe, plane, crtc->base.primary->fb->width,
7057                       crtc->base.primary->fb->height,
7058                       crtc->base.primary->fb->bits_per_pixel, base,
7059                       crtc->base.primary->fb->pitches[0],
7060                       plane_config->size);
7061 }
7062
7063 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7064                                      struct intel_crtc_config *pipe_config)
7065 {
7066         struct drm_device *dev = crtc->base.dev;
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         uint32_t tmp;
7069
7070         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7071         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7072
7073         tmp = I915_READ(PIPECONF(crtc->pipe));
7074         if (!(tmp & PIPECONF_ENABLE))
7075                 return false;
7076
7077         switch (tmp & PIPECONF_BPC_MASK) {
7078         case PIPECONF_6BPC:
7079                 pipe_config->pipe_bpp = 18;
7080                 break;
7081         case PIPECONF_8BPC:
7082                 pipe_config->pipe_bpp = 24;
7083                 break;
7084         case PIPECONF_10BPC:
7085                 pipe_config->pipe_bpp = 30;
7086                 break;
7087         case PIPECONF_12BPC:
7088                 pipe_config->pipe_bpp = 36;
7089                 break;
7090         default:
7091                 break;
7092         }
7093
7094         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7095                 pipe_config->limited_color_range = true;
7096
7097         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7098                 struct intel_shared_dpll *pll;
7099
7100                 pipe_config->has_pch_encoder = true;
7101
7102                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7103                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7104                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7105
7106                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7107
7108                 if (HAS_PCH_IBX(dev_priv->dev)) {
7109                         pipe_config->shared_dpll =
7110                                 (enum intel_dpll_id) crtc->pipe;
7111                 } else {
7112                         tmp = I915_READ(PCH_DPLL_SEL);
7113                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7114                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7115                         else
7116                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7117                 }
7118
7119                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7120
7121                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7122                                            &pipe_config->dpll_hw_state));
7123
7124                 tmp = pipe_config->dpll_hw_state.dpll;
7125                 pipe_config->pixel_multiplier =
7126                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7127                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7128
7129                 ironlake_pch_clock_get(crtc, pipe_config);
7130         } else {
7131                 pipe_config->pixel_multiplier = 1;
7132         }
7133
7134         intel_get_pipe_timings(crtc, pipe_config);
7135
7136         ironlake_get_pfit_config(crtc, pipe_config);
7137
7138         return true;
7139 }
7140
7141 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7142 {
7143         struct drm_device *dev = dev_priv->dev;
7144         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7145         struct intel_crtc *crtc;
7146
7147         for_each_intel_crtc(dev, crtc)
7148                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7149                      pipe_name(crtc->pipe));
7150
7151         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7152         WARN(plls->spll_refcount, "SPLL enabled\n");
7153         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7154         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7155         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7156         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7157              "CPU PWM1 enabled\n");
7158         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7159              "CPU PWM2 enabled\n");
7160         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7161              "PCH PWM1 enabled\n");
7162         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7163              "Utility pin enabled\n");
7164         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7165
7166         /*
7167          * In theory we can still leave IRQs enabled, as long as only the HPD
7168          * interrupts remain enabled. We used to check for that, but since it's
7169          * gen-specific and since we only disable LCPLL after we fully disable
7170          * the interrupts, the check below should be enough.
7171          */
7172         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7173 }
7174
7175 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7176 {
7177         struct drm_device *dev = dev_priv->dev;
7178
7179         if (IS_HASWELL(dev)) {
7180                 mutex_lock(&dev_priv->rps.hw_lock);
7181                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7182                                             val))
7183                         DRM_ERROR("Failed to disable D_COMP\n");
7184                 mutex_unlock(&dev_priv->rps.hw_lock);
7185         } else {
7186                 I915_WRITE(D_COMP, val);
7187         }
7188         POSTING_READ(D_COMP);
7189 }
7190
7191 /*
7192  * This function implements pieces of two sequences from BSpec:
7193  * - Sequence for display software to disable LCPLL
7194  * - Sequence for display software to allow package C8+
7195  * The steps implemented here are just the steps that actually touch the LCPLL
7196  * register. Callers should take care of disabling all the display engine
7197  * functions, doing the mode unset, fixing interrupts, etc.
7198  */
7199 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7200                               bool switch_to_fclk, bool allow_power_down)
7201 {
7202         uint32_t val;
7203
7204         assert_can_disable_lcpll(dev_priv);
7205
7206         val = I915_READ(LCPLL_CTL);
7207
7208         if (switch_to_fclk) {
7209                 val |= LCPLL_CD_SOURCE_FCLK;
7210                 I915_WRITE(LCPLL_CTL, val);
7211
7212                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7213                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7214                         DRM_ERROR("Switching to FCLK failed\n");
7215
7216                 val = I915_READ(LCPLL_CTL);
7217         }
7218
7219         val |= LCPLL_PLL_DISABLE;
7220         I915_WRITE(LCPLL_CTL, val);
7221         POSTING_READ(LCPLL_CTL);
7222
7223         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7224                 DRM_ERROR("LCPLL still locked\n");
7225
7226         val = I915_READ(D_COMP);
7227         val |= D_COMP_COMP_DISABLE;
7228         hsw_write_dcomp(dev_priv, val);
7229         ndelay(100);
7230
7231         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7232                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7233
7234         if (allow_power_down) {
7235                 val = I915_READ(LCPLL_CTL);
7236                 val |= LCPLL_POWER_DOWN_ALLOW;
7237                 I915_WRITE(LCPLL_CTL, val);
7238                 POSTING_READ(LCPLL_CTL);
7239         }
7240 }
7241
7242 /*
7243  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7244  * source.
7245  */
7246 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7247 {
7248         uint32_t val;
7249         unsigned long irqflags;
7250
7251         val = I915_READ(LCPLL_CTL);
7252
7253         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7254                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7255                 return;
7256
7257         /*
7258          * Make sure we're not on PC8 state before disabling PC8, otherwise
7259          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7260          *
7261          * The other problem is that hsw_restore_lcpll() is called as part of
7262          * the runtime PM resume sequence, so we can't just call
7263          * gen6_gt_force_wake_get() because that function calls
7264          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7265          * while we are on the resume sequence. So to solve this problem we have
7266          * to call special forcewake code that doesn't touch runtime PM and
7267          * doesn't enable the forcewake delayed work.
7268          */
7269         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7270         if (dev_priv->uncore.forcewake_count++ == 0)
7271                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7272         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7273
7274         if (val & LCPLL_POWER_DOWN_ALLOW) {
7275                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7276                 I915_WRITE(LCPLL_CTL, val);
7277                 POSTING_READ(LCPLL_CTL);
7278         }
7279
7280         val = I915_READ(D_COMP);
7281         val |= D_COMP_COMP_FORCE;
7282         val &= ~D_COMP_COMP_DISABLE;
7283         hsw_write_dcomp(dev_priv, val);
7284
7285         val = I915_READ(LCPLL_CTL);
7286         val &= ~LCPLL_PLL_DISABLE;
7287         I915_WRITE(LCPLL_CTL, val);
7288
7289         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7290                 DRM_ERROR("LCPLL not locked yet\n");
7291
7292         if (val & LCPLL_CD_SOURCE_FCLK) {
7293                 val = I915_READ(LCPLL_CTL);
7294                 val &= ~LCPLL_CD_SOURCE_FCLK;
7295                 I915_WRITE(LCPLL_CTL, val);
7296
7297                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7298                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7299                         DRM_ERROR("Switching back to LCPLL failed\n");
7300         }
7301
7302         /* See the big comment above. */
7303         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7304         if (--dev_priv->uncore.forcewake_count == 0)
7305                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7306         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7307 }
7308
7309 /*
7310  * Package states C8 and deeper are really deep PC states that can only be
7311  * reached when all the devices on the system allow it, so even if the graphics
7312  * device allows PC8+, it doesn't mean the system will actually get to these
7313  * states. Our driver only allows PC8+ when going into runtime PM.
7314  *
7315  * The requirements for PC8+ are that all the outputs are disabled, the power
7316  * well is disabled and most interrupts are disabled, and these are also
7317  * requirements for runtime PM. When these conditions are met, we manually do
7318  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7319  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7320  * hang the machine.
7321  *
7322  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7323  * the state of some registers, so when we come back from PC8+ we need to
7324  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7325  * need to take care of the registers kept by RC6. Notice that this happens even
7326  * if we don't put the device in PCI D3 state (which is what currently happens
7327  * because of the runtime PM support).
7328  *
7329  * For more, read "Display Sequences for Package C8" on the hardware
7330  * documentation.
7331  */
7332 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7333 {
7334         struct drm_device *dev = dev_priv->dev;
7335         uint32_t val;
7336
7337         DRM_DEBUG_KMS("Enabling package C8+\n");
7338
7339         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7340                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7341                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7342                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7343         }
7344
7345         lpt_disable_clkout_dp(dev);
7346         hsw_disable_lcpll(dev_priv, true, true);
7347 }
7348
7349 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7350 {
7351         struct drm_device *dev = dev_priv->dev;
7352         uint32_t val;
7353
7354         DRM_DEBUG_KMS("Disabling package C8+\n");
7355
7356         hsw_restore_lcpll(dev_priv);
7357         lpt_init_pch_refclk(dev);
7358
7359         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7360                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7361                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7362                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7363         }
7364
7365         intel_prepare_ddi(dev);
7366 }
7367
7368 static void snb_modeset_global_resources(struct drm_device *dev)
7369 {
7370         modeset_update_crtc_power_domains(dev);
7371 }
7372
7373 static void haswell_modeset_global_resources(struct drm_device *dev)
7374 {
7375         modeset_update_crtc_power_domains(dev);
7376 }
7377
7378 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7379                                  int x, int y,
7380                                  struct drm_framebuffer *fb)
7381 {
7382         struct drm_device *dev = crtc->dev;
7383         struct drm_i915_private *dev_priv = dev->dev_private;
7384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7385         int plane = intel_crtc->plane;
7386
7387         if (!intel_ddi_pll_select(intel_crtc))
7388                 return -EINVAL;
7389         intel_ddi_pll_enable(intel_crtc);
7390
7391         intel_crtc->lowfreq_avail = false;
7392
7393         if (intel_crtc->config.has_dp_encoder)
7394                 intel_dp_set_m_n(intel_crtc);
7395
7396         intel_set_pipe_timings(intel_crtc);
7397
7398         if (intel_crtc->config.has_pch_encoder) {
7399                 intel_cpu_transcoder_set_m_n(intel_crtc,
7400                                              &intel_crtc->config.fdi_m_n);
7401         }
7402
7403         haswell_set_pipeconf(crtc);
7404
7405         intel_set_pipe_csc(crtc);
7406
7407         /* Set up the display plane register */
7408         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7409         POSTING_READ(DSPCNTR(plane));
7410
7411         dev_priv->display.update_primary_plane(crtc, fb, x, y);
7412
7413         return 0;
7414 }
7415
7416 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7417                                     struct intel_crtc_config *pipe_config)
7418 {
7419         struct drm_device *dev = crtc->base.dev;
7420         struct drm_i915_private *dev_priv = dev->dev_private;
7421         enum intel_display_power_domain pfit_domain;
7422         uint32_t tmp;
7423
7424         if (!intel_display_power_enabled(dev_priv,
7425                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7426                 return false;
7427
7428         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7429         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7430
7431         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7432         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7433                 enum pipe trans_edp_pipe;
7434                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7435                 default:
7436                         WARN(1, "unknown pipe linked to edp transcoder\n");
7437                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7438                 case TRANS_DDI_EDP_INPUT_A_ON:
7439                         trans_edp_pipe = PIPE_A;
7440                         break;
7441                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7442                         trans_edp_pipe = PIPE_B;
7443                         break;
7444                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7445                         trans_edp_pipe = PIPE_C;
7446                         break;
7447                 }
7448
7449                 if (trans_edp_pipe == crtc->pipe)
7450                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7451         }
7452
7453         if (!intel_display_power_enabled(dev_priv,
7454                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7455                 return false;
7456
7457         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7458         if (!(tmp & PIPECONF_ENABLE))
7459                 return false;
7460
7461         /*
7462          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7463          * DDI E. So just check whether this pipe is wired to DDI E and whether
7464          * the PCH transcoder is on.
7465          */
7466         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7467         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7468             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7469                 pipe_config->has_pch_encoder = true;
7470
7471                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7472                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7473                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7474
7475                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7476         }
7477
7478         intel_get_pipe_timings(crtc, pipe_config);
7479
7480         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7481         if (intel_display_power_enabled(dev_priv, pfit_domain))
7482                 ironlake_get_pfit_config(crtc, pipe_config);
7483
7484         if (IS_HASWELL(dev))
7485                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7486                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7487
7488         pipe_config->pixel_multiplier = 1;
7489
7490         return true;
7491 }
7492
7493 static struct {
7494         int clock;
7495         u32 config;
7496 } hdmi_audio_clock[] = {
7497         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7498         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7499         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7500         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7501         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7502         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7503         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7504         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7505         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7506         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7507 };
7508
7509 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7510 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7511 {
7512         int i;
7513
7514         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7515                 if (mode->clock == hdmi_audio_clock[i].clock)
7516                         break;
7517         }
7518
7519         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7520                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7521                 i = 1;
7522         }
7523
7524         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7525                       hdmi_audio_clock[i].clock,
7526                       hdmi_audio_clock[i].config);
7527
7528         return hdmi_audio_clock[i].config;
7529 }
7530
7531 static bool intel_eld_uptodate(struct drm_connector *connector,
7532                                int reg_eldv, uint32_t bits_eldv,
7533                                int reg_elda, uint32_t bits_elda,
7534                                int reg_edid)
7535 {
7536         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7537         uint8_t *eld = connector->eld;
7538         uint32_t i;
7539
7540         i = I915_READ(reg_eldv);
7541         i &= bits_eldv;
7542
7543         if (!eld[0])
7544                 return !i;
7545
7546         if (!i)
7547                 return false;
7548
7549         i = I915_READ(reg_elda);
7550         i &= ~bits_elda;
7551         I915_WRITE(reg_elda, i);
7552
7553         for (i = 0; i < eld[2]; i++)
7554                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7555                         return false;
7556
7557         return true;
7558 }
7559
7560 static void g4x_write_eld(struct drm_connector *connector,
7561                           struct drm_crtc *crtc,
7562                           struct drm_display_mode *mode)
7563 {
7564         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7565         uint8_t *eld = connector->eld;
7566         uint32_t eldv;
7567         uint32_t len;
7568         uint32_t i;
7569
7570         i = I915_READ(G4X_AUD_VID_DID);
7571
7572         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7573                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7574         else
7575                 eldv = G4X_ELDV_DEVCTG;
7576
7577         if (intel_eld_uptodate(connector,
7578                                G4X_AUD_CNTL_ST, eldv,
7579                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7580                                G4X_HDMIW_HDMIEDID))
7581                 return;
7582
7583         i = I915_READ(G4X_AUD_CNTL_ST);
7584         i &= ~(eldv | G4X_ELD_ADDR);
7585         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7586         I915_WRITE(G4X_AUD_CNTL_ST, i);
7587
7588         if (!eld[0])
7589                 return;
7590
7591         len = min_t(uint8_t, eld[2], len);
7592         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7593         for (i = 0; i < len; i++)
7594                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7595
7596         i = I915_READ(G4X_AUD_CNTL_ST);
7597         i |= eldv;
7598         I915_WRITE(G4X_AUD_CNTL_ST, i);
7599 }
7600
7601 static void haswell_write_eld(struct drm_connector *connector,
7602                               struct drm_crtc *crtc,
7603                               struct drm_display_mode *mode)
7604 {
7605         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7606         uint8_t *eld = connector->eld;
7607         uint32_t eldv;
7608         uint32_t i;
7609         int len;
7610         int pipe = to_intel_crtc(crtc)->pipe;
7611         int tmp;
7612
7613         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7614         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7615         int aud_config = HSW_AUD_CFG(pipe);
7616         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7617
7618         /* Audio output enable */
7619         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7620         tmp = I915_READ(aud_cntrl_st2);
7621         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7622         I915_WRITE(aud_cntrl_st2, tmp);
7623         POSTING_READ(aud_cntrl_st2);
7624
7625         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7626
7627         /* Set ELD valid state */
7628         tmp = I915_READ(aud_cntrl_st2);
7629         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7630         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7631         I915_WRITE(aud_cntrl_st2, tmp);
7632         tmp = I915_READ(aud_cntrl_st2);
7633         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7634
7635         /* Enable HDMI mode */
7636         tmp = I915_READ(aud_config);
7637         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7638         /* clear N_programing_enable and N_value_index */
7639         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7640         I915_WRITE(aud_config, tmp);
7641
7642         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7643
7644         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7645
7646         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7647                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7648                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7649                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7650         } else {
7651                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7652         }
7653
7654         if (intel_eld_uptodate(connector,
7655                                aud_cntrl_st2, eldv,
7656                                aud_cntl_st, IBX_ELD_ADDRESS,
7657                                hdmiw_hdmiedid))
7658                 return;
7659
7660         i = I915_READ(aud_cntrl_st2);
7661         i &= ~eldv;
7662         I915_WRITE(aud_cntrl_st2, i);
7663
7664         if (!eld[0])
7665                 return;
7666
7667         i = I915_READ(aud_cntl_st);
7668         i &= ~IBX_ELD_ADDRESS;
7669         I915_WRITE(aud_cntl_st, i);
7670         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7671         DRM_DEBUG_DRIVER("port num:%d\n", i);
7672
7673         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7674         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7675         for (i = 0; i < len; i++)
7676                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7677
7678         i = I915_READ(aud_cntrl_st2);
7679         i |= eldv;
7680         I915_WRITE(aud_cntrl_st2, i);
7681
7682 }
7683
7684 static void ironlake_write_eld(struct drm_connector *connector,
7685                                struct drm_crtc *crtc,
7686                                struct drm_display_mode *mode)
7687 {
7688         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7689         uint8_t *eld = connector->eld;
7690         uint32_t eldv;
7691         uint32_t i;
7692         int len;
7693         int hdmiw_hdmiedid;
7694         int aud_config;
7695         int aud_cntl_st;
7696         int aud_cntrl_st2;
7697         int pipe = to_intel_crtc(crtc)->pipe;
7698
7699         if (HAS_PCH_IBX(connector->dev)) {
7700                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7701                 aud_config = IBX_AUD_CFG(pipe);
7702                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7703                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7704         } else if (IS_VALLEYVIEW(connector->dev)) {
7705                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7706                 aud_config = VLV_AUD_CFG(pipe);
7707                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7708                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7709         } else {
7710                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7711                 aud_config = CPT_AUD_CFG(pipe);
7712                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7713                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7714         }
7715
7716         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7717
7718         if (IS_VALLEYVIEW(connector->dev))  {
7719                 struct intel_encoder *intel_encoder;
7720                 struct intel_digital_port *intel_dig_port;
7721
7722                 intel_encoder = intel_attached_encoder(connector);
7723                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7724                 i = intel_dig_port->port;
7725         } else {
7726                 i = I915_READ(aud_cntl_st);
7727                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7728                 /* DIP_Port_Select, 0x1 = PortB */
7729         }
7730
7731         if (!i) {
7732                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7733                 /* operate blindly on all ports */
7734                 eldv = IBX_ELD_VALIDB;
7735                 eldv |= IBX_ELD_VALIDB << 4;
7736                 eldv |= IBX_ELD_VALIDB << 8;
7737         } else {
7738                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7739                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7740         }
7741
7742         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7743                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7744                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7745                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7746         } else {
7747                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7748         }
7749
7750         if (intel_eld_uptodate(connector,
7751                                aud_cntrl_st2, eldv,
7752                                aud_cntl_st, IBX_ELD_ADDRESS,
7753                                hdmiw_hdmiedid))
7754                 return;
7755
7756         i = I915_READ(aud_cntrl_st2);
7757         i &= ~eldv;
7758         I915_WRITE(aud_cntrl_st2, i);
7759
7760         if (!eld[0])
7761                 return;
7762
7763         i = I915_READ(aud_cntl_st);
7764         i &= ~IBX_ELD_ADDRESS;
7765         I915_WRITE(aud_cntl_st, i);
7766
7767         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7768         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7769         for (i = 0; i < len; i++)
7770                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7771
7772         i = I915_READ(aud_cntrl_st2);
7773         i |= eldv;
7774         I915_WRITE(aud_cntrl_st2, i);
7775 }
7776
7777 void intel_write_eld(struct drm_encoder *encoder,
7778                      struct drm_display_mode *mode)
7779 {
7780         struct drm_crtc *crtc = encoder->crtc;
7781         struct drm_connector *connector;
7782         struct drm_device *dev = encoder->dev;
7783         struct drm_i915_private *dev_priv = dev->dev_private;
7784
7785         connector = drm_select_eld(encoder, mode);
7786         if (!connector)
7787                 return;
7788
7789         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7790                          connector->base.id,
7791                          drm_get_connector_name(connector),
7792                          connector->encoder->base.id,
7793                          drm_get_encoder_name(connector->encoder));
7794
7795         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7796
7797         if (dev_priv->display.write_eld)
7798                 dev_priv->display.write_eld(connector, crtc, mode);
7799 }
7800
7801 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7802 {
7803         struct drm_device *dev = crtc->dev;
7804         struct drm_i915_private *dev_priv = dev->dev_private;
7805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7806         bool visible = base != 0;
7807         u32 cntl;
7808
7809         if (intel_crtc->cursor_visible == visible)
7810                 return;
7811
7812         cntl = I915_READ(_CURACNTR);
7813         if (visible) {
7814                 /* On these chipsets we can only modify the base whilst
7815                  * the cursor is disabled.
7816                  */
7817                 I915_WRITE(_CURABASE, base);
7818
7819                 cntl &= ~(CURSOR_FORMAT_MASK);
7820                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7821                 cntl |= CURSOR_ENABLE |
7822                         CURSOR_GAMMA_ENABLE |
7823                         CURSOR_FORMAT_ARGB;
7824         } else
7825                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7826         I915_WRITE(_CURACNTR, cntl);
7827
7828         intel_crtc->cursor_visible = visible;
7829 }
7830
7831 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7832 {
7833         struct drm_device *dev = crtc->dev;
7834         struct drm_i915_private *dev_priv = dev->dev_private;
7835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7836         int pipe = intel_crtc->pipe;
7837         bool visible = base != 0;
7838
7839         if (intel_crtc->cursor_visible != visible) {
7840                 int16_t width = intel_crtc->cursor_width;
7841                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7842                 if (base) {
7843                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7844                         cntl |= MCURSOR_GAMMA_ENABLE;
7845
7846                         switch (width) {
7847                         case 64:
7848                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7849                                 break;
7850                         case 128:
7851                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7852                                 break;
7853                         case 256:
7854                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7855                                 break;
7856                         default:
7857                                 WARN_ON(1);
7858                                 return;
7859                         }
7860                         cntl |= pipe << 28; /* Connect to correct pipe */
7861                 } else {
7862                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7863                         cntl |= CURSOR_MODE_DISABLE;
7864                 }
7865                 I915_WRITE(CURCNTR(pipe), cntl);
7866
7867                 intel_crtc->cursor_visible = visible;
7868         }
7869         /* and commit changes on next vblank */
7870         POSTING_READ(CURCNTR(pipe));
7871         I915_WRITE(CURBASE(pipe), base);
7872         POSTING_READ(CURBASE(pipe));
7873 }
7874
7875 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7876 {
7877         struct drm_device *dev = crtc->dev;
7878         struct drm_i915_private *dev_priv = dev->dev_private;
7879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7880         int pipe = intel_crtc->pipe;
7881         bool visible = base != 0;
7882
7883         if (intel_crtc->cursor_visible != visible) {
7884                 int16_t width = intel_crtc->cursor_width;
7885                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7886                 if (base) {
7887                         cntl &= ~CURSOR_MODE;
7888                         cntl |= MCURSOR_GAMMA_ENABLE;
7889                         switch (width) {
7890                         case 64:
7891                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7892                                 break;
7893                         case 128:
7894                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7895                                 break;
7896                         case 256:
7897                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7898                                 break;
7899                         default:
7900                                 WARN_ON(1);
7901                                 return;
7902                         }
7903                 } else {
7904                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7905                         cntl |= CURSOR_MODE_DISABLE;
7906                 }
7907                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7908                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7909                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7910                 }
7911                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7912
7913                 intel_crtc->cursor_visible = visible;
7914         }
7915         /* and commit changes on next vblank */
7916         POSTING_READ(CURCNTR_IVB(pipe));
7917         I915_WRITE(CURBASE_IVB(pipe), base);
7918         POSTING_READ(CURBASE_IVB(pipe));
7919 }
7920
7921 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7922 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7923                                      bool on)
7924 {
7925         struct drm_device *dev = crtc->dev;
7926         struct drm_i915_private *dev_priv = dev->dev_private;
7927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7928         int pipe = intel_crtc->pipe;
7929         int x = intel_crtc->cursor_x;
7930         int y = intel_crtc->cursor_y;
7931         u32 base = 0, pos = 0;
7932         bool visible;
7933
7934         if (on)
7935                 base = intel_crtc->cursor_addr;
7936
7937         if (x >= intel_crtc->config.pipe_src_w)
7938                 base = 0;
7939
7940         if (y >= intel_crtc->config.pipe_src_h)
7941                 base = 0;
7942
7943         if (x < 0) {
7944                 if (x + intel_crtc->cursor_width <= 0)
7945                         base = 0;
7946
7947                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7948                 x = -x;
7949         }
7950         pos |= x << CURSOR_X_SHIFT;
7951
7952         if (y < 0) {
7953                 if (y + intel_crtc->cursor_height <= 0)
7954                         base = 0;
7955
7956                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7957                 y = -y;
7958         }
7959         pos |= y << CURSOR_Y_SHIFT;
7960
7961         visible = base != 0;
7962         if (!visible && !intel_crtc->cursor_visible)
7963                 return;
7964
7965         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7966                 I915_WRITE(CURPOS_IVB(pipe), pos);
7967                 ivb_update_cursor(crtc, base);
7968         } else {
7969                 I915_WRITE(CURPOS(pipe), pos);
7970                 if (IS_845G(dev) || IS_I865G(dev))
7971                         i845_update_cursor(crtc, base);
7972                 else
7973                         i9xx_update_cursor(crtc, base);
7974         }
7975 }
7976
7977 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7978                                  struct drm_file *file,
7979                                  uint32_t handle,
7980                                  uint32_t width, uint32_t height)
7981 {
7982         struct drm_device *dev = crtc->dev;
7983         struct drm_i915_private *dev_priv = dev->dev_private;
7984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7985         struct drm_i915_gem_object *obj;
7986         unsigned old_width;
7987         uint32_t addr;
7988         int ret;
7989
7990         /* if we want to turn off the cursor ignore width and height */
7991         if (!handle) {
7992                 DRM_DEBUG_KMS("cursor off\n");
7993                 addr = 0;
7994                 obj = NULL;
7995                 mutex_lock(&dev->struct_mutex);
7996                 goto finish;
7997         }
7998
7999         /* Check for which cursor types we support */
8000         if (!((width == 64 && height == 64) ||
8001                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8002                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8003                 DRM_DEBUG("Cursor dimension not supported\n");
8004                 return -EINVAL;
8005         }
8006
8007         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8008         if (&obj->base == NULL)
8009                 return -ENOENT;
8010
8011         if (obj->base.size < width * height * 4) {
8012                 DRM_DEBUG_KMS("buffer is to small\n");
8013                 ret = -ENOMEM;
8014                 goto fail;
8015         }
8016
8017         /* we only need to pin inside GTT if cursor is non-phy */
8018         mutex_lock(&dev->struct_mutex);
8019         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8020                 unsigned alignment;
8021
8022                 if (obj->tiling_mode) {
8023                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8024                         ret = -EINVAL;
8025                         goto fail_locked;
8026                 }
8027
8028                 /* Note that the w/a also requires 2 PTE of padding following
8029                  * the bo. We currently fill all unused PTE with the shadow
8030                  * page and so we should always have valid PTE following the
8031                  * cursor preventing the VT-d warning.
8032                  */
8033                 alignment = 0;
8034                 if (need_vtd_wa(dev))
8035                         alignment = 64*1024;
8036
8037                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8038                 if (ret) {
8039                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8040                         goto fail_locked;
8041                 }
8042
8043                 ret = i915_gem_object_put_fence(obj);
8044                 if (ret) {
8045                         DRM_DEBUG_KMS("failed to release fence for cursor");
8046                         goto fail_unpin;
8047                 }
8048
8049                 addr = i915_gem_obj_ggtt_offset(obj);
8050         } else {
8051                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8052                 ret = i915_gem_attach_phys_object(dev, obj,
8053                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8054                                                   align);
8055                 if (ret) {
8056                         DRM_DEBUG_KMS("failed to attach phys object\n");
8057                         goto fail_locked;
8058                 }
8059                 addr = obj->phys_obj->handle->busaddr;
8060         }
8061
8062         if (IS_GEN2(dev))
8063                 I915_WRITE(CURSIZE, (height << 12) | width);
8064
8065  finish:
8066         if (intel_crtc->cursor_bo) {
8067                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8068                         if (intel_crtc->cursor_bo != obj)
8069                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8070                 } else
8071                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8072                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8073         }
8074
8075         mutex_unlock(&dev->struct_mutex);
8076
8077         old_width = intel_crtc->cursor_width;
8078
8079         intel_crtc->cursor_addr = addr;
8080         intel_crtc->cursor_bo = obj;
8081         intel_crtc->cursor_width = width;
8082         intel_crtc->cursor_height = height;
8083
8084         if (intel_crtc->active) {
8085                 if (old_width != width)
8086                         intel_update_watermarks(crtc);
8087                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8088         }
8089
8090         return 0;
8091 fail_unpin:
8092         i915_gem_object_unpin_from_display_plane(obj);
8093 fail_locked:
8094         mutex_unlock(&dev->struct_mutex);
8095 fail:
8096         drm_gem_object_unreference_unlocked(&obj->base);
8097         return ret;
8098 }
8099
8100 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8101 {
8102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8103
8104         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8105         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8106
8107         if (intel_crtc->active)
8108                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8109
8110         return 0;
8111 }
8112
8113 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8114                                  u16 *blue, uint32_t start, uint32_t size)
8115 {
8116         int end = (start + size > 256) ? 256 : start + size, i;
8117         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8118
8119         for (i = start; i < end; i++) {
8120                 intel_crtc->lut_r[i] = red[i] >> 8;
8121                 intel_crtc->lut_g[i] = green[i] >> 8;
8122                 intel_crtc->lut_b[i] = blue[i] >> 8;
8123         }
8124
8125         intel_crtc_load_lut(crtc);
8126 }
8127
8128 /* VESA 640x480x72Hz mode to set on the pipe */
8129 static struct drm_display_mode load_detect_mode = {
8130         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8131                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8132 };
8133
8134 struct drm_framebuffer *
8135 __intel_framebuffer_create(struct drm_device *dev,
8136                            struct drm_mode_fb_cmd2 *mode_cmd,
8137                            struct drm_i915_gem_object *obj)
8138 {
8139         struct intel_framebuffer *intel_fb;
8140         int ret;
8141
8142         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8143         if (!intel_fb) {
8144                 drm_gem_object_unreference_unlocked(&obj->base);
8145                 return ERR_PTR(-ENOMEM);
8146         }
8147
8148         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8149         if (ret)
8150                 goto err;
8151
8152         return &intel_fb->base;
8153 err:
8154         drm_gem_object_unreference_unlocked(&obj->base);
8155         kfree(intel_fb);
8156
8157         return ERR_PTR(ret);
8158 }
8159
8160 static struct drm_framebuffer *
8161 intel_framebuffer_create(struct drm_device *dev,
8162                          struct drm_mode_fb_cmd2 *mode_cmd,
8163                          struct drm_i915_gem_object *obj)
8164 {
8165         struct drm_framebuffer *fb;
8166         int ret;
8167
8168         ret = i915_mutex_lock_interruptible(dev);
8169         if (ret)
8170                 return ERR_PTR(ret);
8171         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8172         mutex_unlock(&dev->struct_mutex);
8173
8174         return fb;
8175 }
8176
8177 static u32
8178 intel_framebuffer_pitch_for_width(int width, int bpp)
8179 {
8180         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8181         return ALIGN(pitch, 64);
8182 }
8183
8184 static u32
8185 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8186 {
8187         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8188         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8189 }
8190
8191 static struct drm_framebuffer *
8192 intel_framebuffer_create_for_mode(struct drm_device *dev,
8193                                   struct drm_display_mode *mode,
8194                                   int depth, int bpp)
8195 {
8196         struct drm_i915_gem_object *obj;
8197         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8198
8199         obj = i915_gem_alloc_object(dev,
8200                                     intel_framebuffer_size_for_mode(mode, bpp));
8201         if (obj == NULL)
8202                 return ERR_PTR(-ENOMEM);
8203
8204         mode_cmd.width = mode->hdisplay;
8205         mode_cmd.height = mode->vdisplay;
8206         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8207                                                                 bpp);
8208         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8209
8210         return intel_framebuffer_create(dev, &mode_cmd, obj);
8211 }
8212
8213 static struct drm_framebuffer *
8214 mode_fits_in_fbdev(struct drm_device *dev,
8215                    struct drm_display_mode *mode)
8216 {
8217 #ifdef CONFIG_DRM_I915_FBDEV
8218         struct drm_i915_private *dev_priv = dev->dev_private;
8219         struct drm_i915_gem_object *obj;
8220         struct drm_framebuffer *fb;
8221
8222         if (!dev_priv->fbdev)
8223                 return NULL;
8224
8225         if (!dev_priv->fbdev->fb)
8226                 return NULL;
8227
8228         obj = dev_priv->fbdev->fb->obj;
8229         BUG_ON(!obj);
8230
8231         fb = &dev_priv->fbdev->fb->base;
8232         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8233                                                                fb->bits_per_pixel))
8234                 return NULL;
8235
8236         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8237                 return NULL;
8238
8239         return fb;
8240 #else
8241         return NULL;
8242 #endif
8243 }
8244
8245 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8246                                 struct drm_display_mode *mode,
8247                                 struct intel_load_detect_pipe *old)
8248 {
8249         struct intel_crtc *intel_crtc;
8250         struct intel_encoder *intel_encoder =
8251                 intel_attached_encoder(connector);
8252         struct drm_crtc *possible_crtc;
8253         struct drm_encoder *encoder = &intel_encoder->base;
8254         struct drm_crtc *crtc = NULL;
8255         struct drm_device *dev = encoder->dev;
8256         struct drm_framebuffer *fb;
8257         int i = -1;
8258
8259         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8260                       connector->base.id, drm_get_connector_name(connector),
8261                       encoder->base.id, drm_get_encoder_name(encoder));
8262
8263         /*
8264          * Algorithm gets a little messy:
8265          *
8266          *   - if the connector already has an assigned crtc, use it (but make
8267          *     sure it's on first)
8268          *
8269          *   - try to find the first unused crtc that can drive this connector,
8270          *     and use that if we find one
8271          */
8272
8273         /* See if we already have a CRTC for this connector */
8274         if (encoder->crtc) {
8275                 crtc = encoder->crtc;
8276
8277                 mutex_lock(&crtc->mutex);
8278
8279                 old->dpms_mode = connector->dpms;
8280                 old->load_detect_temp = false;
8281
8282                 /* Make sure the crtc and connector are running */
8283                 if (connector->dpms != DRM_MODE_DPMS_ON)
8284                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8285
8286                 return true;
8287         }
8288
8289         /* Find an unused one (if possible) */
8290         for_each_crtc(dev, possible_crtc) {
8291                 i++;
8292                 if (!(encoder->possible_crtcs & (1 << i)))
8293                         continue;
8294                 if (!possible_crtc->enabled) {
8295                         crtc = possible_crtc;
8296                         break;
8297                 }
8298         }
8299
8300         /*
8301          * If we didn't find an unused CRTC, don't use any.
8302          */
8303         if (!crtc) {
8304                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8305                 return false;
8306         }
8307
8308         mutex_lock(&crtc->mutex);
8309         intel_encoder->new_crtc = to_intel_crtc(crtc);
8310         to_intel_connector(connector)->new_encoder = intel_encoder;
8311
8312         intel_crtc = to_intel_crtc(crtc);
8313         intel_crtc->new_enabled = true;
8314         intel_crtc->new_config = &intel_crtc->config;
8315         old->dpms_mode = connector->dpms;
8316         old->load_detect_temp = true;
8317         old->release_fb = NULL;
8318
8319         if (!mode)
8320                 mode = &load_detect_mode;
8321
8322         /* We need a framebuffer large enough to accommodate all accesses
8323          * that the plane may generate whilst we perform load detection.
8324          * We can not rely on the fbcon either being present (we get called
8325          * during its initialisation to detect all boot displays, or it may
8326          * not even exist) or that it is large enough to satisfy the
8327          * requested mode.
8328          */
8329         fb = mode_fits_in_fbdev(dev, mode);
8330         if (fb == NULL) {
8331                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8332                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8333                 old->release_fb = fb;
8334         } else
8335                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8336         if (IS_ERR(fb)) {
8337                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8338                 goto fail;
8339         }
8340
8341         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8342                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8343                 if (old->release_fb)
8344                         old->release_fb->funcs->destroy(old->release_fb);
8345                 goto fail;
8346         }
8347
8348         /* let the connector get through one full cycle before testing */
8349         intel_wait_for_vblank(dev, intel_crtc->pipe);
8350         return true;
8351
8352  fail:
8353         intel_crtc->new_enabled = crtc->enabled;
8354         if (intel_crtc->new_enabled)
8355                 intel_crtc->new_config = &intel_crtc->config;
8356         else
8357                 intel_crtc->new_config = NULL;
8358         mutex_unlock(&crtc->mutex);
8359         return false;
8360 }
8361
8362 void intel_release_load_detect_pipe(struct drm_connector *connector,
8363                                     struct intel_load_detect_pipe *old)
8364 {
8365         struct intel_encoder *intel_encoder =
8366                 intel_attached_encoder(connector);
8367         struct drm_encoder *encoder = &intel_encoder->base;
8368         struct drm_crtc *crtc = encoder->crtc;
8369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8370
8371         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8372                       connector->base.id, drm_get_connector_name(connector),
8373                       encoder->base.id, drm_get_encoder_name(encoder));
8374
8375         if (old->load_detect_temp) {
8376                 to_intel_connector(connector)->new_encoder = NULL;
8377                 intel_encoder->new_crtc = NULL;
8378                 intel_crtc->new_enabled = false;
8379                 intel_crtc->new_config = NULL;
8380                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8381
8382                 if (old->release_fb) {
8383                         drm_framebuffer_unregister_private(old->release_fb);
8384                         drm_framebuffer_unreference(old->release_fb);
8385                 }
8386
8387                 mutex_unlock(&crtc->mutex);
8388                 return;
8389         }
8390
8391         /* Switch crtc and encoder back off if necessary */
8392         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8393                 connector->funcs->dpms(connector, old->dpms_mode);
8394
8395         mutex_unlock(&crtc->mutex);
8396 }
8397
8398 static int i9xx_pll_refclk(struct drm_device *dev,
8399                            const struct intel_crtc_config *pipe_config)
8400 {
8401         struct drm_i915_private *dev_priv = dev->dev_private;
8402         u32 dpll = pipe_config->dpll_hw_state.dpll;
8403
8404         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8405                 return dev_priv->vbt.lvds_ssc_freq;
8406         else if (HAS_PCH_SPLIT(dev))
8407                 return 120000;
8408         else if (!IS_GEN2(dev))
8409                 return 96000;
8410         else
8411                 return 48000;
8412 }
8413
8414 /* Returns the clock of the currently programmed mode of the given pipe. */
8415 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8416                                 struct intel_crtc_config *pipe_config)
8417 {
8418         struct drm_device *dev = crtc->base.dev;
8419         struct drm_i915_private *dev_priv = dev->dev_private;
8420         int pipe = pipe_config->cpu_transcoder;
8421         u32 dpll = pipe_config->dpll_hw_state.dpll;
8422         u32 fp;
8423         intel_clock_t clock;
8424         int refclk = i9xx_pll_refclk(dev, pipe_config);
8425
8426         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8427                 fp = pipe_config->dpll_hw_state.fp0;
8428         else
8429                 fp = pipe_config->dpll_hw_state.fp1;
8430
8431         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8432         if (IS_PINEVIEW(dev)) {
8433                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8434                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8435         } else {
8436                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8437                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8438         }
8439
8440         if (!IS_GEN2(dev)) {
8441                 if (IS_PINEVIEW(dev))
8442                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8443                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8444                 else
8445                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8446                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8447
8448                 switch (dpll & DPLL_MODE_MASK) {
8449                 case DPLLB_MODE_DAC_SERIAL:
8450                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8451                                 5 : 10;
8452                         break;
8453                 case DPLLB_MODE_LVDS:
8454                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8455                                 7 : 14;
8456                         break;
8457                 default:
8458                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8459                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8460                         return;
8461                 }
8462
8463                 if (IS_PINEVIEW(dev))
8464                         pineview_clock(refclk, &clock);
8465                 else
8466                         i9xx_clock(refclk, &clock);
8467         } else {
8468                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8469                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8470
8471                 if (is_lvds) {
8472                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8473                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8474
8475                         if (lvds & LVDS_CLKB_POWER_UP)
8476                                 clock.p2 = 7;
8477                         else
8478                                 clock.p2 = 14;
8479                 } else {
8480                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8481                                 clock.p1 = 2;
8482                         else {
8483                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8484                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8485                         }
8486                         if (dpll & PLL_P2_DIVIDE_BY_4)
8487                                 clock.p2 = 4;
8488                         else
8489                                 clock.p2 = 2;
8490                 }
8491
8492                 i9xx_clock(refclk, &clock);
8493         }
8494
8495         /*
8496          * This value includes pixel_multiplier. We will use
8497          * port_clock to compute adjusted_mode.crtc_clock in the
8498          * encoder's get_config() function.
8499          */
8500         pipe_config->port_clock = clock.dot;
8501 }
8502
8503 int intel_dotclock_calculate(int link_freq,
8504                              const struct intel_link_m_n *m_n)
8505 {
8506         /*
8507          * The calculation for the data clock is:
8508          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8509          * But we want to avoid losing precison if possible, so:
8510          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8511          *
8512          * and the link clock is simpler:
8513          * link_clock = (m * link_clock) / n
8514          */
8515
8516         if (!m_n->link_n)
8517                 return 0;
8518
8519         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8520 }
8521
8522 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8523                                    struct intel_crtc_config *pipe_config)
8524 {
8525         struct drm_device *dev = crtc->base.dev;
8526
8527         /* read out port_clock from the DPLL */
8528         i9xx_crtc_clock_get(crtc, pipe_config);
8529
8530         /*
8531          * This value does not include pixel_multiplier.
8532          * We will check that port_clock and adjusted_mode.crtc_clock
8533          * agree once we know their relationship in the encoder's
8534          * get_config() function.
8535          */
8536         pipe_config->adjusted_mode.crtc_clock =
8537                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8538                                          &pipe_config->fdi_m_n);
8539 }
8540
8541 /** Returns the currently programmed mode of the given pipe. */
8542 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8543                                              struct drm_crtc *crtc)
8544 {
8545         struct drm_i915_private *dev_priv = dev->dev_private;
8546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8547         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8548         struct drm_display_mode *mode;
8549         struct intel_crtc_config pipe_config;
8550         int htot = I915_READ(HTOTAL(cpu_transcoder));
8551         int hsync = I915_READ(HSYNC(cpu_transcoder));
8552         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8553         int vsync = I915_READ(VSYNC(cpu_transcoder));
8554         enum pipe pipe = intel_crtc->pipe;
8555
8556         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8557         if (!mode)
8558                 return NULL;
8559
8560         /*
8561          * Construct a pipe_config sufficient for getting the clock info
8562          * back out of crtc_clock_get.
8563          *
8564          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8565          * to use a real value here instead.
8566          */
8567         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8568         pipe_config.pixel_multiplier = 1;
8569         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8570         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8571         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8572         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8573
8574         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8575         mode->hdisplay = (htot & 0xffff) + 1;
8576         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8577         mode->hsync_start = (hsync & 0xffff) + 1;
8578         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8579         mode->vdisplay = (vtot & 0xffff) + 1;
8580         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8581         mode->vsync_start = (vsync & 0xffff) + 1;
8582         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8583
8584         drm_mode_set_name(mode);
8585
8586         return mode;
8587 }
8588
8589 static void intel_increase_pllclock(struct drm_crtc *crtc)
8590 {
8591         struct drm_device *dev = crtc->dev;
8592         struct drm_i915_private *dev_priv = dev->dev_private;
8593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8594         int pipe = intel_crtc->pipe;
8595         int dpll_reg = DPLL(pipe);
8596         int dpll;
8597
8598         if (HAS_PCH_SPLIT(dev))
8599                 return;
8600
8601         if (!dev_priv->lvds_downclock_avail)
8602                 return;
8603
8604         dpll = I915_READ(dpll_reg);
8605         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8606                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8607
8608                 assert_panel_unlocked(dev_priv, pipe);
8609
8610                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8611                 I915_WRITE(dpll_reg, dpll);
8612                 intel_wait_for_vblank(dev, pipe);
8613
8614                 dpll = I915_READ(dpll_reg);
8615                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8616                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8617         }
8618 }
8619
8620 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8621 {
8622         struct drm_device *dev = crtc->dev;
8623         struct drm_i915_private *dev_priv = dev->dev_private;
8624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625
8626         if (HAS_PCH_SPLIT(dev))
8627                 return;
8628
8629         if (!dev_priv->lvds_downclock_avail)
8630                 return;
8631
8632         /*
8633          * Since this is called by a timer, we should never get here in
8634          * the manual case.
8635          */
8636         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8637                 int pipe = intel_crtc->pipe;
8638                 int dpll_reg = DPLL(pipe);
8639                 int dpll;
8640
8641                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8642
8643                 assert_panel_unlocked(dev_priv, pipe);
8644
8645                 dpll = I915_READ(dpll_reg);
8646                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8647                 I915_WRITE(dpll_reg, dpll);
8648                 intel_wait_for_vblank(dev, pipe);
8649                 dpll = I915_READ(dpll_reg);
8650                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8651                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8652         }
8653
8654 }
8655
8656 void intel_mark_busy(struct drm_device *dev)
8657 {
8658         struct drm_i915_private *dev_priv = dev->dev_private;
8659
8660         if (dev_priv->mm.busy)
8661                 return;
8662
8663         intel_runtime_pm_get(dev_priv);
8664         i915_update_gfx_val(dev_priv);
8665         dev_priv->mm.busy = true;
8666 }
8667
8668 void intel_mark_idle(struct drm_device *dev)
8669 {
8670         struct drm_i915_private *dev_priv = dev->dev_private;
8671         struct drm_crtc *crtc;
8672
8673         if (!dev_priv->mm.busy)
8674                 return;
8675
8676         dev_priv->mm.busy = false;
8677
8678         if (!i915.powersave)
8679                 goto out;
8680
8681         for_each_crtc(dev, crtc) {
8682                 if (!crtc->primary->fb)
8683                         continue;
8684
8685                 intel_decrease_pllclock(crtc);
8686         }
8687
8688         if (INTEL_INFO(dev)->gen >= 6)
8689                 gen6_rps_idle(dev->dev_private);
8690
8691 out:
8692         intel_runtime_pm_put(dev_priv);
8693 }
8694
8695 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8696                         struct intel_ring_buffer *ring)
8697 {
8698         struct drm_device *dev = obj->base.dev;
8699         struct drm_crtc *crtc;
8700
8701         if (!i915.powersave)
8702                 return;
8703
8704         for_each_crtc(dev, crtc) {
8705                 if (!crtc->primary->fb)
8706                         continue;
8707
8708                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8709                         continue;
8710
8711                 intel_increase_pllclock(crtc);
8712                 if (ring && intel_fbc_enabled(dev))
8713                         ring->fbc_dirty = true;
8714         }
8715 }
8716
8717 static void intel_crtc_destroy(struct drm_crtc *crtc)
8718 {
8719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8720         struct drm_device *dev = crtc->dev;
8721         struct intel_unpin_work *work;
8722         unsigned long flags;
8723
8724         spin_lock_irqsave(&dev->event_lock, flags);
8725         work = intel_crtc->unpin_work;
8726         intel_crtc->unpin_work = NULL;
8727         spin_unlock_irqrestore(&dev->event_lock, flags);
8728
8729         if (work) {
8730                 cancel_work_sync(&work->work);
8731                 kfree(work);
8732         }
8733
8734         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8735
8736         drm_crtc_cleanup(crtc);
8737
8738         kfree(intel_crtc);
8739 }
8740
8741 static void intel_unpin_work_fn(struct work_struct *__work)
8742 {
8743         struct intel_unpin_work *work =
8744                 container_of(__work, struct intel_unpin_work, work);
8745         struct drm_device *dev = work->crtc->dev;
8746
8747         mutex_lock(&dev->struct_mutex);
8748         intel_unpin_fb_obj(work->old_fb_obj);
8749         drm_gem_object_unreference(&work->pending_flip_obj->base);
8750         drm_gem_object_unreference(&work->old_fb_obj->base);
8751
8752         intel_update_fbc(dev);
8753         mutex_unlock(&dev->struct_mutex);
8754
8755         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8756         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8757
8758         kfree(work);
8759 }
8760
8761 static void do_intel_finish_page_flip(struct drm_device *dev,
8762                                       struct drm_crtc *crtc)
8763 {
8764         struct drm_i915_private *dev_priv = dev->dev_private;
8765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8766         struct intel_unpin_work *work;
8767         unsigned long flags;
8768
8769         /* Ignore early vblank irqs */
8770         if (intel_crtc == NULL)
8771                 return;
8772
8773         spin_lock_irqsave(&dev->event_lock, flags);
8774         work = intel_crtc->unpin_work;
8775
8776         /* Ensure we don't miss a work->pending update ... */
8777         smp_rmb();
8778
8779         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8780                 spin_unlock_irqrestore(&dev->event_lock, flags);
8781                 return;
8782         }
8783
8784         /* and that the unpin work is consistent wrt ->pending. */
8785         smp_rmb();
8786
8787         intel_crtc->unpin_work = NULL;
8788
8789         if (work->event)
8790                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8791
8792         drm_vblank_put(dev, intel_crtc->pipe);
8793
8794         spin_unlock_irqrestore(&dev->event_lock, flags);
8795
8796         wake_up_all(&dev_priv->pending_flip_queue);
8797
8798         queue_work(dev_priv->wq, &work->work);
8799
8800         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8801 }
8802
8803 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8804 {
8805         struct drm_i915_private *dev_priv = dev->dev_private;
8806         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8807
8808         do_intel_finish_page_flip(dev, crtc);
8809 }
8810
8811 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8812 {
8813         struct drm_i915_private *dev_priv = dev->dev_private;
8814         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8815
8816         do_intel_finish_page_flip(dev, crtc);
8817 }
8818
8819 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8820 {
8821         struct drm_i915_private *dev_priv = dev->dev_private;
8822         struct intel_crtc *intel_crtc =
8823                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8824         unsigned long flags;
8825
8826         /* NB: An MMIO update of the plane base pointer will also
8827          * generate a page-flip completion irq, i.e. every modeset
8828          * is also accompanied by a spurious intel_prepare_page_flip().
8829          */
8830         spin_lock_irqsave(&dev->event_lock, flags);
8831         if (intel_crtc->unpin_work)
8832                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8833         spin_unlock_irqrestore(&dev->event_lock, flags);
8834 }
8835
8836 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8837 {
8838         /* Ensure that the work item is consistent when activating it ... */
8839         smp_wmb();
8840         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8841         /* and that it is marked active as soon as the irq could fire. */
8842         smp_wmb();
8843 }
8844
8845 static int intel_gen2_queue_flip(struct drm_device *dev,
8846                                  struct drm_crtc *crtc,
8847                                  struct drm_framebuffer *fb,
8848                                  struct drm_i915_gem_object *obj,
8849                                  uint32_t flags)
8850 {
8851         struct drm_i915_private *dev_priv = dev->dev_private;
8852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8853         u32 flip_mask;
8854         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8855         int ret;
8856
8857         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8858         if (ret)
8859                 goto err;
8860
8861         ret = intel_ring_begin(ring, 6);
8862         if (ret)
8863                 goto err_unpin;
8864
8865         /* Can't queue multiple flips, so wait for the previous
8866          * one to finish before executing the next.
8867          */
8868         if (intel_crtc->plane)
8869                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8870         else
8871                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8872         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8873         intel_ring_emit(ring, MI_NOOP);
8874         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8875                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8876         intel_ring_emit(ring, fb->pitches[0]);
8877         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8878         intel_ring_emit(ring, 0); /* aux display base address, unused */
8879
8880         intel_mark_page_flip_active(intel_crtc);
8881         __intel_ring_advance(ring);
8882         return 0;
8883
8884 err_unpin:
8885         intel_unpin_fb_obj(obj);
8886 err:
8887         return ret;
8888 }
8889
8890 static int intel_gen3_queue_flip(struct drm_device *dev,
8891                                  struct drm_crtc *crtc,
8892                                  struct drm_framebuffer *fb,
8893                                  struct drm_i915_gem_object *obj,
8894                                  uint32_t flags)
8895 {
8896         struct drm_i915_private *dev_priv = dev->dev_private;
8897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8898         u32 flip_mask;
8899         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8900         int ret;
8901
8902         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8903         if (ret)
8904                 goto err;
8905
8906         ret = intel_ring_begin(ring, 6);
8907         if (ret)
8908                 goto err_unpin;
8909
8910         if (intel_crtc->plane)
8911                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8912         else
8913                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8914         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8915         intel_ring_emit(ring, MI_NOOP);
8916         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8917                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8918         intel_ring_emit(ring, fb->pitches[0]);
8919         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8920         intel_ring_emit(ring, MI_NOOP);
8921
8922         intel_mark_page_flip_active(intel_crtc);
8923         __intel_ring_advance(ring);
8924         return 0;
8925
8926 err_unpin:
8927         intel_unpin_fb_obj(obj);
8928 err:
8929         return ret;
8930 }
8931
8932 static int intel_gen4_queue_flip(struct drm_device *dev,
8933                                  struct drm_crtc *crtc,
8934                                  struct drm_framebuffer *fb,
8935                                  struct drm_i915_gem_object *obj,
8936                                  uint32_t flags)
8937 {
8938         struct drm_i915_private *dev_priv = dev->dev_private;
8939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8940         uint32_t pf, pipesrc;
8941         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8942         int ret;
8943
8944         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8945         if (ret)
8946                 goto err;
8947
8948         ret = intel_ring_begin(ring, 4);
8949         if (ret)
8950                 goto err_unpin;
8951
8952         /* i965+ uses the linear or tiled offsets from the
8953          * Display Registers (which do not change across a page-flip)
8954          * so we need only reprogram the base address.
8955          */
8956         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8957                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8958         intel_ring_emit(ring, fb->pitches[0]);
8959         intel_ring_emit(ring,
8960                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8961                         obj->tiling_mode);
8962
8963         /* XXX Enabling the panel-fitter across page-flip is so far
8964          * untested on non-native modes, so ignore it for now.
8965          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8966          */
8967         pf = 0;
8968         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8969         intel_ring_emit(ring, pf | pipesrc);
8970
8971         intel_mark_page_flip_active(intel_crtc);
8972         __intel_ring_advance(ring);
8973         return 0;
8974
8975 err_unpin:
8976         intel_unpin_fb_obj(obj);
8977 err:
8978         return ret;
8979 }
8980
8981 static int intel_gen6_queue_flip(struct drm_device *dev,
8982                                  struct drm_crtc *crtc,
8983                                  struct drm_framebuffer *fb,
8984                                  struct drm_i915_gem_object *obj,
8985                                  uint32_t flags)
8986 {
8987         struct drm_i915_private *dev_priv = dev->dev_private;
8988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8989         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8990         uint32_t pf, pipesrc;
8991         int ret;
8992
8993         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8994         if (ret)
8995                 goto err;
8996
8997         ret = intel_ring_begin(ring, 4);
8998         if (ret)
8999                 goto err_unpin;
9000
9001         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9002                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9003         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9004         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9005
9006         /* Contrary to the suggestions in the documentation,
9007          * "Enable Panel Fitter" does not seem to be required when page
9008          * flipping with a non-native mode, and worse causes a normal
9009          * modeset to fail.
9010          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9011          */
9012         pf = 0;
9013         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9014         intel_ring_emit(ring, pf | pipesrc);
9015
9016         intel_mark_page_flip_active(intel_crtc);
9017         __intel_ring_advance(ring);
9018         return 0;
9019
9020 err_unpin:
9021         intel_unpin_fb_obj(obj);
9022 err:
9023         return ret;
9024 }
9025
9026 static int intel_gen7_queue_flip(struct drm_device *dev,
9027                                  struct drm_crtc *crtc,
9028                                  struct drm_framebuffer *fb,
9029                                  struct drm_i915_gem_object *obj,
9030                                  uint32_t flags)
9031 {
9032         struct drm_i915_private *dev_priv = dev->dev_private;
9033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9034         struct intel_ring_buffer *ring;
9035         uint32_t plane_bit = 0;
9036         int len, ret;
9037
9038         ring = obj->ring;
9039         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9040                 ring = &dev_priv->ring[BCS];
9041
9042         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9043         if (ret)
9044                 goto err;
9045
9046         switch (intel_crtc->plane) {
9047         case PLANE_A:
9048                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9049                 break;
9050         case PLANE_B:
9051                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9052                 break;
9053         case PLANE_C:
9054                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9055                 break;
9056         default:
9057                 WARN_ONCE(1, "unknown plane in flip command\n");
9058                 ret = -ENODEV;
9059                 goto err_unpin;
9060         }
9061
9062         len = 4;
9063         if (ring->id == RCS) {
9064                 len += 6;
9065                 /*
9066                  * On Gen 8, SRM is now taking an extra dword to accommodate
9067                  * 48bits addresses, and we need a NOOP for the batch size to
9068                  * stay even.
9069                  */
9070                 if (IS_GEN8(dev))
9071                         len += 2;
9072         }
9073
9074         /*
9075          * BSpec MI_DISPLAY_FLIP for IVB:
9076          * "The full packet must be contained within the same cache line."
9077          *
9078          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9079          * cacheline, if we ever start emitting more commands before
9080          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9081          * then do the cacheline alignment, and finally emit the
9082          * MI_DISPLAY_FLIP.
9083          */
9084         ret = intel_ring_cacheline_align(ring);
9085         if (ret)
9086                 goto err_unpin;
9087
9088         ret = intel_ring_begin(ring, len);
9089         if (ret)
9090                 goto err_unpin;
9091
9092         /* Unmask the flip-done completion message. Note that the bspec says that
9093          * we should do this for both the BCS and RCS, and that we must not unmask
9094          * more than one flip event at any time (or ensure that one flip message
9095          * can be sent by waiting for flip-done prior to queueing new flips).
9096          * Experimentation says that BCS works despite DERRMR masking all
9097          * flip-done completion events and that unmasking all planes at once
9098          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9099          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9100          */
9101         if (ring->id == RCS) {
9102                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9103                 intel_ring_emit(ring, DERRMR);
9104                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9105                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9106                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9107                 if (IS_GEN8(dev))
9108                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9109                                               MI_SRM_LRM_GLOBAL_GTT);
9110                 else
9111                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9112                                               MI_SRM_LRM_GLOBAL_GTT);
9113                 intel_ring_emit(ring, DERRMR);
9114                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9115                 if (IS_GEN8(dev)) {
9116                         intel_ring_emit(ring, 0);
9117                         intel_ring_emit(ring, MI_NOOP);
9118                 }
9119         }
9120
9121         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9122         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9123         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9124         intel_ring_emit(ring, (MI_NOOP));
9125
9126         intel_mark_page_flip_active(intel_crtc);
9127         __intel_ring_advance(ring);
9128         return 0;
9129
9130 err_unpin:
9131         intel_unpin_fb_obj(obj);
9132 err:
9133         return ret;
9134 }
9135
9136 static int intel_default_queue_flip(struct drm_device *dev,
9137                                     struct drm_crtc *crtc,
9138                                     struct drm_framebuffer *fb,
9139                                     struct drm_i915_gem_object *obj,
9140                                     uint32_t flags)
9141 {
9142         return -ENODEV;
9143 }
9144
9145 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9146                                 struct drm_framebuffer *fb,
9147                                 struct drm_pending_vblank_event *event,
9148                                 uint32_t page_flip_flags)
9149 {
9150         struct drm_device *dev = crtc->dev;
9151         struct drm_i915_private *dev_priv = dev->dev_private;
9152         struct drm_framebuffer *old_fb = crtc->primary->fb;
9153         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9154         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9155         struct intel_unpin_work *work;
9156         unsigned long flags;
9157         int ret;
9158
9159         /* Can't change pixel format via MI display flips. */
9160         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9161                 return -EINVAL;
9162
9163         /*
9164          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9165          * Note that pitch changes could also affect these register.
9166          */
9167         if (INTEL_INFO(dev)->gen > 3 &&
9168             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9169              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9170                 return -EINVAL;
9171
9172         if (i915_terminally_wedged(&dev_priv->gpu_error))
9173                 goto out_hang;
9174
9175         work = kzalloc(sizeof(*work), GFP_KERNEL);
9176         if (work == NULL)
9177                 return -ENOMEM;
9178
9179         work->event = event;
9180         work->crtc = crtc;
9181         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9182         INIT_WORK(&work->work, intel_unpin_work_fn);
9183
9184         ret = drm_vblank_get(dev, intel_crtc->pipe);
9185         if (ret)
9186                 goto free_work;
9187
9188         /* We borrow the event spin lock for protecting unpin_work */
9189         spin_lock_irqsave(&dev->event_lock, flags);
9190         if (intel_crtc->unpin_work) {
9191                 spin_unlock_irqrestore(&dev->event_lock, flags);
9192                 kfree(work);
9193                 drm_vblank_put(dev, intel_crtc->pipe);
9194
9195                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9196                 return -EBUSY;
9197         }
9198         intel_crtc->unpin_work = work;
9199         spin_unlock_irqrestore(&dev->event_lock, flags);
9200
9201         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9202                 flush_workqueue(dev_priv->wq);
9203
9204         ret = i915_mutex_lock_interruptible(dev);
9205         if (ret)
9206                 goto cleanup;
9207
9208         /* Reference the objects for the scheduled work. */
9209         drm_gem_object_reference(&work->old_fb_obj->base);
9210         drm_gem_object_reference(&obj->base);
9211
9212         crtc->primary->fb = fb;
9213
9214         work->pending_flip_obj = obj;
9215
9216         work->enable_stall_check = true;
9217
9218         atomic_inc(&intel_crtc->unpin_work_count);
9219         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9220
9221         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9222         if (ret)
9223                 goto cleanup_pending;
9224
9225         intel_disable_fbc(dev);
9226         intel_mark_fb_busy(obj, NULL);
9227         mutex_unlock(&dev->struct_mutex);
9228
9229         trace_i915_flip_request(intel_crtc->plane, obj);
9230
9231         return 0;
9232
9233 cleanup_pending:
9234         atomic_dec(&intel_crtc->unpin_work_count);
9235         crtc->primary->fb = old_fb;
9236         drm_gem_object_unreference(&work->old_fb_obj->base);
9237         drm_gem_object_unreference(&obj->base);
9238         mutex_unlock(&dev->struct_mutex);
9239
9240 cleanup:
9241         spin_lock_irqsave(&dev->event_lock, flags);
9242         intel_crtc->unpin_work = NULL;
9243         spin_unlock_irqrestore(&dev->event_lock, flags);
9244
9245         drm_vblank_put(dev, intel_crtc->pipe);
9246 free_work:
9247         kfree(work);
9248
9249         if (ret == -EIO) {
9250 out_hang:
9251                 intel_crtc_wait_for_pending_flips(crtc);
9252                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9253                 if (ret == 0 && event)
9254                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9255         }
9256         return ret;
9257 }
9258
9259 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9260         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9261         .load_lut = intel_crtc_load_lut,
9262 };
9263
9264 /**
9265  * intel_modeset_update_staged_output_state
9266  *
9267  * Updates the staged output configuration state, e.g. after we've read out the
9268  * current hw state.
9269  */
9270 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9271 {
9272         struct intel_crtc *crtc;
9273         struct intel_encoder *encoder;
9274         struct intel_connector *connector;
9275
9276         list_for_each_entry(connector, &dev->mode_config.connector_list,
9277                             base.head) {
9278                 connector->new_encoder =
9279                         to_intel_encoder(connector->base.encoder);
9280         }
9281
9282         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9283                             base.head) {
9284                 encoder->new_crtc =
9285                         to_intel_crtc(encoder->base.crtc);
9286         }
9287
9288         for_each_intel_crtc(dev, crtc) {
9289                 crtc->new_enabled = crtc->base.enabled;
9290
9291                 if (crtc->new_enabled)
9292                         crtc->new_config = &crtc->config;
9293                 else
9294                         crtc->new_config = NULL;
9295         }
9296 }
9297
9298 /**
9299  * intel_modeset_commit_output_state
9300  *
9301  * This function copies the stage display pipe configuration to the real one.
9302  */
9303 static void intel_modeset_commit_output_state(struct drm_device *dev)
9304 {
9305         struct intel_crtc *crtc;
9306         struct intel_encoder *encoder;
9307         struct intel_connector *connector;
9308
9309         list_for_each_entry(connector, &dev->mode_config.connector_list,
9310                             base.head) {
9311                 connector->base.encoder = &connector->new_encoder->base;
9312         }
9313
9314         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9315                             base.head) {
9316                 encoder->base.crtc = &encoder->new_crtc->base;
9317         }
9318
9319         for_each_intel_crtc(dev, crtc) {
9320                 crtc->base.enabled = crtc->new_enabled;
9321         }
9322 }
9323
9324 static void
9325 connected_sink_compute_bpp(struct intel_connector *connector,
9326                            struct intel_crtc_config *pipe_config)
9327 {
9328         int bpp = pipe_config->pipe_bpp;
9329
9330         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9331                 connector->base.base.id,
9332                 drm_get_connector_name(&connector->base));
9333
9334         /* Don't use an invalid EDID bpc value */
9335         if (connector->base.display_info.bpc &&
9336             connector->base.display_info.bpc * 3 < bpp) {
9337                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9338                               bpp, connector->base.display_info.bpc*3);
9339                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9340         }
9341
9342         /* Clamp bpp to 8 on screens without EDID 1.4 */
9343         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9344                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9345                               bpp);
9346                 pipe_config->pipe_bpp = 24;
9347         }
9348 }
9349
9350 static int
9351 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9352                           struct drm_framebuffer *fb,
9353                           struct intel_crtc_config *pipe_config)
9354 {
9355         struct drm_device *dev = crtc->base.dev;
9356         struct intel_connector *connector;
9357         int bpp;
9358
9359         switch (fb->pixel_format) {
9360         case DRM_FORMAT_C8:
9361                 bpp = 8*3; /* since we go through a colormap */
9362                 break;
9363         case DRM_FORMAT_XRGB1555:
9364         case DRM_FORMAT_ARGB1555:
9365                 /* checked in intel_framebuffer_init already */
9366                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9367                         return -EINVAL;
9368         case DRM_FORMAT_RGB565:
9369                 bpp = 6*3; /* min is 18bpp */
9370                 break;
9371         case DRM_FORMAT_XBGR8888:
9372         case DRM_FORMAT_ABGR8888:
9373                 /* checked in intel_framebuffer_init already */
9374                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9375                         return -EINVAL;
9376         case DRM_FORMAT_XRGB8888:
9377         case DRM_FORMAT_ARGB8888:
9378                 bpp = 8*3;
9379                 break;
9380         case DRM_FORMAT_XRGB2101010:
9381         case DRM_FORMAT_ARGB2101010:
9382         case DRM_FORMAT_XBGR2101010:
9383         case DRM_FORMAT_ABGR2101010:
9384                 /* checked in intel_framebuffer_init already */
9385                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9386                         return -EINVAL;
9387                 bpp = 10*3;
9388                 break;
9389         /* TODO: gen4+ supports 16 bpc floating point, too. */
9390         default:
9391                 DRM_DEBUG_KMS("unsupported depth\n");
9392                 return -EINVAL;
9393         }
9394
9395         pipe_config->pipe_bpp = bpp;
9396
9397         /* Clamp display bpp to EDID value */
9398         list_for_each_entry(connector, &dev->mode_config.connector_list,
9399                             base.head) {
9400                 if (!connector->new_encoder ||
9401                     connector->new_encoder->new_crtc != crtc)
9402                         continue;
9403
9404                 connected_sink_compute_bpp(connector, pipe_config);
9405         }
9406
9407         return bpp;
9408 }
9409
9410 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9411 {
9412         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9413                         "type: 0x%x flags: 0x%x\n",
9414                 mode->crtc_clock,
9415                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9416                 mode->crtc_hsync_end, mode->crtc_htotal,
9417                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9418                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9419 }
9420
9421 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9422                                    struct intel_crtc_config *pipe_config,
9423                                    const char *context)
9424 {
9425         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9426                       context, pipe_name(crtc->pipe));
9427
9428         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9429         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9430                       pipe_config->pipe_bpp, pipe_config->dither);
9431         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9432                       pipe_config->has_pch_encoder,
9433                       pipe_config->fdi_lanes,
9434                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9435                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9436                       pipe_config->fdi_m_n.tu);
9437         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9438                       pipe_config->has_dp_encoder,
9439                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9440                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9441                       pipe_config->dp_m_n.tu);
9442         DRM_DEBUG_KMS("requested mode:\n");
9443         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9444         DRM_DEBUG_KMS("adjusted mode:\n");
9445         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9446         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9447         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9448         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9449                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9450         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9451                       pipe_config->gmch_pfit.control,
9452                       pipe_config->gmch_pfit.pgm_ratios,
9453                       pipe_config->gmch_pfit.lvds_border_bits);
9454         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9455                       pipe_config->pch_pfit.pos,
9456                       pipe_config->pch_pfit.size,
9457                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9458         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9459         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9460 }
9461
9462 static bool encoders_cloneable(const struct intel_encoder *a,
9463                                const struct intel_encoder *b)
9464 {
9465         /* masks could be asymmetric, so check both ways */
9466         return a == b || (a->cloneable & (1 << b->type) &&
9467                           b->cloneable & (1 << a->type));
9468 }
9469
9470 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9471                                          struct intel_encoder *encoder)
9472 {
9473         struct drm_device *dev = crtc->base.dev;
9474         struct intel_encoder *source_encoder;
9475
9476         list_for_each_entry(source_encoder,
9477                             &dev->mode_config.encoder_list, base.head) {
9478                 if (source_encoder->new_crtc != crtc)
9479                         continue;
9480
9481                 if (!encoders_cloneable(encoder, source_encoder))
9482                         return false;
9483         }
9484
9485         return true;
9486 }
9487
9488 static bool check_encoder_cloning(struct intel_crtc *crtc)
9489 {
9490         struct drm_device *dev = crtc->base.dev;
9491         struct intel_encoder *encoder;
9492
9493         list_for_each_entry(encoder,
9494                             &dev->mode_config.encoder_list, base.head) {
9495                 if (encoder->new_crtc != crtc)
9496                         continue;
9497
9498                 if (!check_single_encoder_cloning(crtc, encoder))
9499                         return false;
9500         }
9501
9502         return true;
9503 }
9504
9505 static struct intel_crtc_config *
9506 intel_modeset_pipe_config(struct drm_crtc *crtc,
9507                           struct drm_framebuffer *fb,
9508                           struct drm_display_mode *mode)
9509 {
9510         struct drm_device *dev = crtc->dev;
9511         struct intel_encoder *encoder;
9512         struct intel_crtc_config *pipe_config;
9513         int plane_bpp, ret = -EINVAL;
9514         bool retry = true;
9515
9516         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9517                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9518                 return ERR_PTR(-EINVAL);
9519         }
9520
9521         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9522         if (!pipe_config)
9523                 return ERR_PTR(-ENOMEM);
9524
9525         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9526         drm_mode_copy(&pipe_config->requested_mode, mode);
9527
9528         pipe_config->cpu_transcoder =
9529                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9530         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9531
9532         /*
9533          * Sanitize sync polarity flags based on requested ones. If neither
9534          * positive or negative polarity is requested, treat this as meaning
9535          * negative polarity.
9536          */
9537         if (!(pipe_config->adjusted_mode.flags &
9538               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9539                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9540
9541         if (!(pipe_config->adjusted_mode.flags &
9542               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9543                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9544
9545         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9546          * plane pixel format and any sink constraints into account. Returns the
9547          * source plane bpp so that dithering can be selected on mismatches
9548          * after encoders and crtc also have had their say. */
9549         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9550                                               fb, pipe_config);
9551         if (plane_bpp < 0)
9552                 goto fail;
9553
9554         /*
9555          * Determine the real pipe dimensions. Note that stereo modes can
9556          * increase the actual pipe size due to the frame doubling and
9557          * insertion of additional space for blanks between the frame. This
9558          * is stored in the crtc timings. We use the requested mode to do this
9559          * computation to clearly distinguish it from the adjusted mode, which
9560          * can be changed by the connectors in the below retry loop.
9561          */
9562         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9563         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9564         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9565
9566 encoder_retry:
9567         /* Ensure the port clock defaults are reset when retrying. */
9568         pipe_config->port_clock = 0;
9569         pipe_config->pixel_multiplier = 1;
9570
9571         /* Fill in default crtc timings, allow encoders to overwrite them. */
9572         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9573
9574         /* Pass our mode to the connectors and the CRTC to give them a chance to
9575          * adjust it according to limitations or connector properties, and also
9576          * a chance to reject the mode entirely.
9577          */
9578         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9579                             base.head) {
9580
9581                 if (&encoder->new_crtc->base != crtc)
9582                         continue;
9583
9584                 if (!(encoder->compute_config(encoder, pipe_config))) {
9585                         DRM_DEBUG_KMS("Encoder config failure\n");
9586                         goto fail;
9587                 }
9588         }
9589
9590         /* Set default port clock if not overwritten by the encoder. Needs to be
9591          * done afterwards in case the encoder adjusts the mode. */
9592         if (!pipe_config->port_clock)
9593                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9594                         * pipe_config->pixel_multiplier;
9595
9596         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9597         if (ret < 0) {
9598                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9599                 goto fail;
9600         }
9601
9602         if (ret == RETRY) {
9603                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9604                         ret = -EINVAL;
9605                         goto fail;
9606                 }
9607
9608                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9609                 retry = false;
9610                 goto encoder_retry;
9611         }
9612
9613         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9614         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9615                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9616
9617         return pipe_config;
9618 fail:
9619         kfree(pipe_config);
9620         return ERR_PTR(ret);
9621 }
9622
9623 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9624  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9625 static void
9626 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9627                              unsigned *prepare_pipes, unsigned *disable_pipes)
9628 {
9629         struct intel_crtc *intel_crtc;
9630         struct drm_device *dev = crtc->dev;
9631         struct intel_encoder *encoder;
9632         struct intel_connector *connector;
9633         struct drm_crtc *tmp_crtc;
9634
9635         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9636
9637         /* Check which crtcs have changed outputs connected to them, these need
9638          * to be part of the prepare_pipes mask. We don't (yet) support global
9639          * modeset across multiple crtcs, so modeset_pipes will only have one
9640          * bit set at most. */
9641         list_for_each_entry(connector, &dev->mode_config.connector_list,
9642                             base.head) {
9643                 if (connector->base.encoder == &connector->new_encoder->base)
9644                         continue;
9645
9646                 if (connector->base.encoder) {
9647                         tmp_crtc = connector->base.encoder->crtc;
9648
9649                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9650                 }
9651
9652                 if (connector->new_encoder)
9653                         *prepare_pipes |=
9654                                 1 << connector->new_encoder->new_crtc->pipe;
9655         }
9656
9657         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9658                             base.head) {
9659                 if (encoder->base.crtc == &encoder->new_crtc->base)
9660                         continue;
9661
9662                 if (encoder->base.crtc) {
9663                         tmp_crtc = encoder->base.crtc;
9664
9665                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9666                 }
9667
9668                 if (encoder->new_crtc)
9669                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9670         }
9671
9672         /* Check for pipes that will be enabled/disabled ... */
9673         for_each_intel_crtc(dev, intel_crtc) {
9674                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9675                         continue;
9676
9677                 if (!intel_crtc->new_enabled)
9678                         *disable_pipes |= 1 << intel_crtc->pipe;
9679                 else
9680                         *prepare_pipes |= 1 << intel_crtc->pipe;
9681         }
9682
9683
9684         /* set_mode is also used to update properties on life display pipes. */
9685         intel_crtc = to_intel_crtc(crtc);
9686         if (intel_crtc->new_enabled)
9687                 *prepare_pipes |= 1 << intel_crtc->pipe;
9688
9689         /*
9690          * For simplicity do a full modeset on any pipe where the output routing
9691          * changed. We could be more clever, but that would require us to be
9692          * more careful with calling the relevant encoder->mode_set functions.
9693          */
9694         if (*prepare_pipes)
9695                 *modeset_pipes = *prepare_pipes;
9696
9697         /* ... and mask these out. */
9698         *modeset_pipes &= ~(*disable_pipes);
9699         *prepare_pipes &= ~(*disable_pipes);
9700
9701         /*
9702          * HACK: We don't (yet) fully support global modesets. intel_set_config
9703          * obies this rule, but the modeset restore mode of
9704          * intel_modeset_setup_hw_state does not.
9705          */
9706         *modeset_pipes &= 1 << intel_crtc->pipe;
9707         *prepare_pipes &= 1 << intel_crtc->pipe;
9708
9709         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9710                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9711 }
9712
9713 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9714 {
9715         struct drm_encoder *encoder;
9716         struct drm_device *dev = crtc->dev;
9717
9718         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9719                 if (encoder->crtc == crtc)
9720                         return true;
9721
9722         return false;
9723 }
9724
9725 static void
9726 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9727 {
9728         struct intel_encoder *intel_encoder;
9729         struct intel_crtc *intel_crtc;
9730         struct drm_connector *connector;
9731
9732         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9733                             base.head) {
9734                 if (!intel_encoder->base.crtc)
9735                         continue;
9736
9737                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9738
9739                 if (prepare_pipes & (1 << intel_crtc->pipe))
9740                         intel_encoder->connectors_active = false;
9741         }
9742
9743         intel_modeset_commit_output_state(dev);
9744
9745         /* Double check state. */
9746         for_each_intel_crtc(dev, intel_crtc) {
9747                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9748                 WARN_ON(intel_crtc->new_config &&
9749                         intel_crtc->new_config != &intel_crtc->config);
9750                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9751         }
9752
9753         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9754                 if (!connector->encoder || !connector->encoder->crtc)
9755                         continue;
9756
9757                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9758
9759                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9760                         struct drm_property *dpms_property =
9761                                 dev->mode_config.dpms_property;
9762
9763                         connector->dpms = DRM_MODE_DPMS_ON;
9764                         drm_object_property_set_value(&connector->base,
9765                                                          dpms_property,
9766                                                          DRM_MODE_DPMS_ON);
9767
9768                         intel_encoder = to_intel_encoder(connector->encoder);
9769                         intel_encoder->connectors_active = true;
9770                 }
9771         }
9772
9773 }
9774
9775 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9776 {
9777         int diff;
9778
9779         if (clock1 == clock2)
9780                 return true;
9781
9782         if (!clock1 || !clock2)
9783                 return false;
9784
9785         diff = abs(clock1 - clock2);
9786
9787         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9788                 return true;
9789
9790         return false;
9791 }
9792
9793 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9794         list_for_each_entry((intel_crtc), \
9795                             &(dev)->mode_config.crtc_list, \
9796                             base.head) \
9797                 if (mask & (1 <<(intel_crtc)->pipe))
9798
9799 static bool
9800 intel_pipe_config_compare(struct drm_device *dev,
9801                           struct intel_crtc_config *current_config,
9802                           struct intel_crtc_config *pipe_config)
9803 {
9804 #define PIPE_CONF_CHECK_X(name) \
9805         if (current_config->name != pipe_config->name) { \
9806                 DRM_ERROR("mismatch in " #name " " \
9807                           "(expected 0x%08x, found 0x%08x)\n", \
9808                           current_config->name, \
9809                           pipe_config->name); \
9810                 return false; \
9811         }
9812
9813 #define PIPE_CONF_CHECK_I(name) \
9814         if (current_config->name != pipe_config->name) { \
9815                 DRM_ERROR("mismatch in " #name " " \
9816                           "(expected %i, found %i)\n", \
9817                           current_config->name, \
9818                           pipe_config->name); \
9819                 return false; \
9820         }
9821
9822 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9823         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9824                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9825                           "(expected %i, found %i)\n", \
9826                           current_config->name & (mask), \
9827                           pipe_config->name & (mask)); \
9828                 return false; \
9829         }
9830
9831 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9832         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9833                 DRM_ERROR("mismatch in " #name " " \
9834                           "(expected %i, found %i)\n", \
9835                           current_config->name, \
9836                           pipe_config->name); \
9837                 return false; \
9838         }
9839
9840 #define PIPE_CONF_QUIRK(quirk)  \
9841         ((current_config->quirks | pipe_config->quirks) & (quirk))
9842
9843         PIPE_CONF_CHECK_I(cpu_transcoder);
9844
9845         PIPE_CONF_CHECK_I(has_pch_encoder);
9846         PIPE_CONF_CHECK_I(fdi_lanes);
9847         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9848         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9849         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9850         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9851         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9852
9853         PIPE_CONF_CHECK_I(has_dp_encoder);
9854         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9855         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9856         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9857         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9858         PIPE_CONF_CHECK_I(dp_m_n.tu);
9859
9860         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9861         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9862         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9863         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9864         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9865         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9866
9867         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9868         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9869         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9870         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9871         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9872         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9873
9874         PIPE_CONF_CHECK_I(pixel_multiplier);
9875         PIPE_CONF_CHECK_I(has_hdmi_sink);
9876         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9877             IS_VALLEYVIEW(dev))
9878                 PIPE_CONF_CHECK_I(limited_color_range);
9879
9880         PIPE_CONF_CHECK_I(has_audio);
9881
9882         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9883                               DRM_MODE_FLAG_INTERLACE);
9884
9885         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9886                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9887                                       DRM_MODE_FLAG_PHSYNC);
9888                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9889                                       DRM_MODE_FLAG_NHSYNC);
9890                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9891                                       DRM_MODE_FLAG_PVSYNC);
9892                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9893                                       DRM_MODE_FLAG_NVSYNC);
9894         }
9895
9896         PIPE_CONF_CHECK_I(pipe_src_w);
9897         PIPE_CONF_CHECK_I(pipe_src_h);
9898
9899         /*
9900          * FIXME: BIOS likes to set up a cloned config with lvds+external
9901          * screen. Since we don't yet re-compute the pipe config when moving
9902          * just the lvds port away to another pipe the sw tracking won't match.
9903          *
9904          * Proper atomic modesets with recomputed global state will fix this.
9905          * Until then just don't check gmch state for inherited modes.
9906          */
9907         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9908                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9909                 /* pfit ratios are autocomputed by the hw on gen4+ */
9910                 if (INTEL_INFO(dev)->gen < 4)
9911                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9912                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9913         }
9914
9915         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9916         if (current_config->pch_pfit.enabled) {
9917                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9918                 PIPE_CONF_CHECK_I(pch_pfit.size);
9919         }
9920
9921         /* BDW+ don't expose a synchronous way to read the state */
9922         if (IS_HASWELL(dev))
9923                 PIPE_CONF_CHECK_I(ips_enabled);
9924
9925         PIPE_CONF_CHECK_I(double_wide);
9926
9927         PIPE_CONF_CHECK_I(shared_dpll);
9928         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9929         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9930         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9931         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9932
9933         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9934                 PIPE_CONF_CHECK_I(pipe_bpp);
9935
9936         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9937         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9938
9939 #undef PIPE_CONF_CHECK_X
9940 #undef PIPE_CONF_CHECK_I
9941 #undef PIPE_CONF_CHECK_FLAGS
9942 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9943 #undef PIPE_CONF_QUIRK
9944
9945         return true;
9946 }
9947
9948 static void
9949 check_connector_state(struct drm_device *dev)
9950 {
9951         struct intel_connector *connector;
9952
9953         list_for_each_entry(connector, &dev->mode_config.connector_list,
9954                             base.head) {
9955                 /* This also checks the encoder/connector hw state with the
9956                  * ->get_hw_state callbacks. */
9957                 intel_connector_check_state(connector);
9958
9959                 WARN(&connector->new_encoder->base != connector->base.encoder,
9960                      "connector's staged encoder doesn't match current encoder\n");
9961         }
9962 }
9963
9964 static void
9965 check_encoder_state(struct drm_device *dev)
9966 {
9967         struct intel_encoder *encoder;
9968         struct intel_connector *connector;
9969
9970         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9971                             base.head) {
9972                 bool enabled = false;
9973                 bool active = false;
9974                 enum pipe pipe, tracked_pipe;
9975
9976                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9977                               encoder->base.base.id,
9978                               drm_get_encoder_name(&encoder->base));
9979
9980                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9981                      "encoder's stage crtc doesn't match current crtc\n");
9982                 WARN(encoder->connectors_active && !encoder->base.crtc,
9983                      "encoder's active_connectors set, but no crtc\n");
9984
9985                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9986                                     base.head) {
9987                         if (connector->base.encoder != &encoder->base)
9988                                 continue;
9989                         enabled = true;
9990                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9991                                 active = true;
9992                 }
9993                 WARN(!!encoder->base.crtc != enabled,
9994                      "encoder's enabled state mismatch "
9995                      "(expected %i, found %i)\n",
9996                      !!encoder->base.crtc, enabled);
9997                 WARN(active && !encoder->base.crtc,
9998                      "active encoder with no crtc\n");
9999
10000                 WARN(encoder->connectors_active != active,
10001                      "encoder's computed active state doesn't match tracked active state "
10002                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10003
10004                 active = encoder->get_hw_state(encoder, &pipe);
10005                 WARN(active != encoder->connectors_active,
10006                      "encoder's hw state doesn't match sw tracking "
10007                      "(expected %i, found %i)\n",
10008                      encoder->connectors_active, active);
10009
10010                 if (!encoder->base.crtc)
10011                         continue;
10012
10013                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10014                 WARN(active && pipe != tracked_pipe,
10015                      "active encoder's pipe doesn't match"
10016                      "(expected %i, found %i)\n",
10017                      tracked_pipe, pipe);
10018
10019         }
10020 }
10021
10022 static void
10023 check_crtc_state(struct drm_device *dev)
10024 {
10025         struct drm_i915_private *dev_priv = dev->dev_private;
10026         struct intel_crtc *crtc;
10027         struct intel_encoder *encoder;
10028         struct intel_crtc_config pipe_config;
10029
10030         for_each_intel_crtc(dev, crtc) {
10031                 bool enabled = false;
10032                 bool active = false;
10033
10034                 memset(&pipe_config, 0, sizeof(pipe_config));
10035
10036                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10037                               crtc->base.base.id);
10038
10039                 WARN(crtc->active && !crtc->base.enabled,
10040                      "active crtc, but not enabled in sw tracking\n");
10041
10042                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10043                                     base.head) {
10044                         if (encoder->base.crtc != &crtc->base)
10045                                 continue;
10046                         enabled = true;
10047                         if (encoder->connectors_active)
10048                                 active = true;
10049                 }
10050
10051                 WARN(active != crtc->active,
10052                      "crtc's computed active state doesn't match tracked active state "
10053                      "(expected %i, found %i)\n", active, crtc->active);
10054                 WARN(enabled != crtc->base.enabled,
10055                      "crtc's computed enabled state doesn't match tracked enabled state "
10056                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10057
10058                 active = dev_priv->display.get_pipe_config(crtc,
10059                                                            &pipe_config);
10060
10061                 /* hw state is inconsistent with the pipe A quirk */
10062                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10063                         active = crtc->active;
10064
10065                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10066                                     base.head) {
10067                         enum pipe pipe;
10068                         if (encoder->base.crtc != &crtc->base)
10069                                 continue;
10070                         if (encoder->get_hw_state(encoder, &pipe))
10071                                 encoder->get_config(encoder, &pipe_config);
10072                 }
10073
10074                 WARN(crtc->active != active,
10075                      "crtc active state doesn't match with hw state "
10076                      "(expected %i, found %i)\n", crtc->active, active);
10077
10078                 if (active &&
10079                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10080                         WARN(1, "pipe state doesn't match!\n");
10081                         intel_dump_pipe_config(crtc, &pipe_config,
10082                                                "[hw state]");
10083                         intel_dump_pipe_config(crtc, &crtc->config,
10084                                                "[sw state]");
10085                 }
10086         }
10087 }
10088
10089 static void
10090 check_shared_dpll_state(struct drm_device *dev)
10091 {
10092         struct drm_i915_private *dev_priv = dev->dev_private;
10093         struct intel_crtc *crtc;
10094         struct intel_dpll_hw_state dpll_hw_state;
10095         int i;
10096
10097         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10098                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10099                 int enabled_crtcs = 0, active_crtcs = 0;
10100                 bool active;
10101
10102                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10103
10104                 DRM_DEBUG_KMS("%s\n", pll->name);
10105
10106                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10107
10108                 WARN(pll->active > pll->refcount,
10109                      "more active pll users than references: %i vs %i\n",
10110                      pll->active, pll->refcount);
10111                 WARN(pll->active && !pll->on,
10112                      "pll in active use but not on in sw tracking\n");
10113                 WARN(pll->on && !pll->active,
10114                      "pll in on but not on in use in sw tracking\n");
10115                 WARN(pll->on != active,
10116                      "pll on state mismatch (expected %i, found %i)\n",
10117                      pll->on, active);
10118
10119                 for_each_intel_crtc(dev, crtc) {
10120                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10121                                 enabled_crtcs++;
10122                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10123                                 active_crtcs++;
10124                 }
10125                 WARN(pll->active != active_crtcs,
10126                      "pll active crtcs mismatch (expected %i, found %i)\n",
10127                      pll->active, active_crtcs);
10128                 WARN(pll->refcount != enabled_crtcs,
10129                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10130                      pll->refcount, enabled_crtcs);
10131
10132                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10133                                        sizeof(dpll_hw_state)),
10134                      "pll hw state mismatch\n");
10135         }
10136 }
10137
10138 void
10139 intel_modeset_check_state(struct drm_device *dev)
10140 {
10141         check_connector_state(dev);
10142         check_encoder_state(dev);
10143         check_crtc_state(dev);
10144         check_shared_dpll_state(dev);
10145 }
10146
10147 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10148                                      int dotclock)
10149 {
10150         /*
10151          * FDI already provided one idea for the dotclock.
10152          * Yell if the encoder disagrees.
10153          */
10154         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10155              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10156              pipe_config->adjusted_mode.crtc_clock, dotclock);
10157 }
10158
10159 static int __intel_set_mode(struct drm_crtc *crtc,
10160                             struct drm_display_mode *mode,
10161                             int x, int y, struct drm_framebuffer *fb)
10162 {
10163         struct drm_device *dev = crtc->dev;
10164         struct drm_i915_private *dev_priv = dev->dev_private;
10165         struct drm_display_mode *saved_mode;
10166         struct intel_crtc_config *pipe_config = NULL;
10167         struct intel_crtc *intel_crtc;
10168         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10169         int ret = 0;
10170
10171         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10172         if (!saved_mode)
10173                 return -ENOMEM;
10174
10175         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10176                                      &prepare_pipes, &disable_pipes);
10177
10178         *saved_mode = crtc->mode;
10179
10180         /* Hack: Because we don't (yet) support global modeset on multiple
10181          * crtcs, we don't keep track of the new mode for more than one crtc.
10182          * Hence simply check whether any bit is set in modeset_pipes in all the
10183          * pieces of code that are not yet converted to deal with mutliple crtcs
10184          * changing their mode at the same time. */
10185         if (modeset_pipes) {
10186                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10187                 if (IS_ERR(pipe_config)) {
10188                         ret = PTR_ERR(pipe_config);
10189                         pipe_config = NULL;
10190
10191                         goto out;
10192                 }
10193                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10194                                        "[modeset]");
10195                 to_intel_crtc(crtc)->new_config = pipe_config;
10196         }
10197
10198         /*
10199          * See if the config requires any additional preparation, e.g.
10200          * to adjust global state with pipes off.  We need to do this
10201          * here so we can get the modeset_pipe updated config for the new
10202          * mode set on this crtc.  For other crtcs we need to use the
10203          * adjusted_mode bits in the crtc directly.
10204          */
10205         if (IS_VALLEYVIEW(dev)) {
10206                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10207
10208                 /* may have added more to prepare_pipes than we should */
10209                 prepare_pipes &= ~disable_pipes;
10210         }
10211
10212         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10213                 intel_crtc_disable(&intel_crtc->base);
10214
10215         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10216                 if (intel_crtc->base.enabled)
10217                         dev_priv->display.crtc_disable(&intel_crtc->base);
10218         }
10219
10220         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10221          * to set it here already despite that we pass it down the callchain.
10222          */
10223         if (modeset_pipes) {
10224                 crtc->mode = *mode;
10225                 /* mode_set/enable/disable functions rely on a correct pipe
10226                  * config. */
10227                 to_intel_crtc(crtc)->config = *pipe_config;
10228                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10229
10230                 /*
10231                  * Calculate and store various constants which
10232                  * are later needed by vblank and swap-completion
10233                  * timestamping. They are derived from true hwmode.
10234                  */
10235                 drm_calc_timestamping_constants(crtc,
10236                                                 &pipe_config->adjusted_mode);
10237         }
10238
10239         /* Only after disabling all output pipelines that will be changed can we
10240          * update the the output configuration. */
10241         intel_modeset_update_state(dev, prepare_pipes);
10242
10243         if (dev_priv->display.modeset_global_resources)
10244                 dev_priv->display.modeset_global_resources(dev);
10245
10246         /* Set up the DPLL and any encoders state that needs to adjust or depend
10247          * on the DPLL.
10248          */
10249         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10250                 struct drm_framebuffer *old_fb;
10251
10252                 mutex_lock(&dev->struct_mutex);
10253                 ret = intel_pin_and_fence_fb_obj(dev,
10254                                                  to_intel_framebuffer(fb)->obj,
10255                                                  NULL);
10256                 if (ret != 0) {
10257                         DRM_ERROR("pin & fence failed\n");
10258                         mutex_unlock(&dev->struct_mutex);
10259                         goto done;
10260                 }
10261                 old_fb = crtc->primary->fb;
10262                 if (old_fb)
10263                         intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10264                 mutex_unlock(&dev->struct_mutex);
10265
10266                 crtc->primary->fb = fb;
10267                 crtc->x = x;
10268                 crtc->y = y;
10269
10270                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10271                                                       x, y, fb);
10272                 if (ret)
10273                         goto done;
10274         }
10275
10276         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10277         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10278                 dev_priv->display.crtc_enable(&intel_crtc->base);
10279
10280         /* FIXME: add subpixel order */
10281 done:
10282         if (ret && crtc->enabled)
10283                 crtc->mode = *saved_mode;
10284
10285 out:
10286         kfree(pipe_config);
10287         kfree(saved_mode);
10288         return ret;
10289 }
10290
10291 static int intel_set_mode(struct drm_crtc *crtc,
10292                           struct drm_display_mode *mode,
10293                           int x, int y, struct drm_framebuffer *fb)
10294 {
10295         int ret;
10296
10297         ret = __intel_set_mode(crtc, mode, x, y, fb);
10298
10299         if (ret == 0)
10300                 intel_modeset_check_state(crtc->dev);
10301
10302         return ret;
10303 }
10304
10305 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10306 {
10307         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10308 }
10309
10310 #undef for_each_intel_crtc_masked
10311
10312 static void intel_set_config_free(struct intel_set_config *config)
10313 {
10314         if (!config)
10315                 return;
10316
10317         kfree(config->save_connector_encoders);
10318         kfree(config->save_encoder_crtcs);
10319         kfree(config->save_crtc_enabled);
10320         kfree(config);
10321 }
10322
10323 static int intel_set_config_save_state(struct drm_device *dev,
10324                                        struct intel_set_config *config)
10325 {
10326         struct drm_crtc *crtc;
10327         struct drm_encoder *encoder;
10328         struct drm_connector *connector;
10329         int count;
10330
10331         config->save_crtc_enabled =
10332                 kcalloc(dev->mode_config.num_crtc,
10333                         sizeof(bool), GFP_KERNEL);
10334         if (!config->save_crtc_enabled)
10335                 return -ENOMEM;
10336
10337         config->save_encoder_crtcs =
10338                 kcalloc(dev->mode_config.num_encoder,
10339                         sizeof(struct drm_crtc *), GFP_KERNEL);
10340         if (!config->save_encoder_crtcs)
10341                 return -ENOMEM;
10342
10343         config->save_connector_encoders =
10344                 kcalloc(dev->mode_config.num_connector,
10345                         sizeof(struct drm_encoder *), GFP_KERNEL);
10346         if (!config->save_connector_encoders)
10347                 return -ENOMEM;
10348
10349         /* Copy data. Note that driver private data is not affected.
10350          * Should anything bad happen only the expected state is
10351          * restored, not the drivers personal bookkeeping.
10352          */
10353         count = 0;
10354         for_each_crtc(dev, crtc) {
10355                 config->save_crtc_enabled[count++] = crtc->enabled;
10356         }
10357
10358         count = 0;
10359         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10360                 config->save_encoder_crtcs[count++] = encoder->crtc;
10361         }
10362
10363         count = 0;
10364         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10365                 config->save_connector_encoders[count++] = connector->encoder;
10366         }
10367
10368         return 0;
10369 }
10370
10371 static void intel_set_config_restore_state(struct drm_device *dev,
10372                                            struct intel_set_config *config)
10373 {
10374         struct intel_crtc *crtc;
10375         struct intel_encoder *encoder;
10376         struct intel_connector *connector;
10377         int count;
10378
10379         count = 0;
10380         for_each_intel_crtc(dev, crtc) {
10381                 crtc->new_enabled = config->save_crtc_enabled[count++];
10382
10383                 if (crtc->new_enabled)
10384                         crtc->new_config = &crtc->config;
10385                 else
10386                         crtc->new_config = NULL;
10387         }
10388
10389         count = 0;
10390         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10391                 encoder->new_crtc =
10392                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10393         }
10394
10395         count = 0;
10396         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10397                 connector->new_encoder =
10398                         to_intel_encoder(config->save_connector_encoders[count++]);
10399         }
10400 }
10401
10402 static bool
10403 is_crtc_connector_off(struct drm_mode_set *set)
10404 {
10405         int i;
10406
10407         if (set->num_connectors == 0)
10408                 return false;
10409
10410         if (WARN_ON(set->connectors == NULL))
10411                 return false;
10412
10413         for (i = 0; i < set->num_connectors; i++)
10414                 if (set->connectors[i]->encoder &&
10415                     set->connectors[i]->encoder->crtc == set->crtc &&
10416                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10417                         return true;
10418
10419         return false;
10420 }
10421
10422 static void
10423 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10424                                       struct intel_set_config *config)
10425 {
10426
10427         /* We should be able to check here if the fb has the same properties
10428          * and then just flip_or_move it */
10429         if (is_crtc_connector_off(set)) {
10430                 config->mode_changed = true;
10431         } else if (set->crtc->primary->fb != set->fb) {
10432                 /* If we have no fb then treat it as a full mode set */
10433                 if (set->crtc->primary->fb == NULL) {
10434                         struct intel_crtc *intel_crtc =
10435                                 to_intel_crtc(set->crtc);
10436
10437                         if (intel_crtc->active && i915.fastboot) {
10438                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10439                                 config->fb_changed = true;
10440                         } else {
10441                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10442                                 config->mode_changed = true;
10443                         }
10444                 } else if (set->fb == NULL) {
10445                         config->mode_changed = true;
10446                 } else if (set->fb->pixel_format !=
10447                            set->crtc->primary->fb->pixel_format) {
10448                         config->mode_changed = true;
10449                 } else {
10450                         config->fb_changed = true;
10451                 }
10452         }
10453
10454         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10455                 config->fb_changed = true;
10456
10457         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10458                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10459                 drm_mode_debug_printmodeline(&set->crtc->mode);
10460                 drm_mode_debug_printmodeline(set->mode);
10461                 config->mode_changed = true;
10462         }
10463
10464         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10465                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10466 }
10467
10468 static int
10469 intel_modeset_stage_output_state(struct drm_device *dev,
10470                                  struct drm_mode_set *set,
10471                                  struct intel_set_config *config)
10472 {
10473         struct intel_connector *connector;
10474         struct intel_encoder *encoder;
10475         struct intel_crtc *crtc;
10476         int ro;
10477
10478         /* The upper layers ensure that we either disable a crtc or have a list
10479          * of connectors. For paranoia, double-check this. */
10480         WARN_ON(!set->fb && (set->num_connectors != 0));
10481         WARN_ON(set->fb && (set->num_connectors == 0));
10482
10483         list_for_each_entry(connector, &dev->mode_config.connector_list,
10484                             base.head) {
10485                 /* Otherwise traverse passed in connector list and get encoders
10486                  * for them. */
10487                 for (ro = 0; ro < set->num_connectors; ro++) {
10488                         if (set->connectors[ro] == &connector->base) {
10489                                 connector->new_encoder = connector->encoder;
10490                                 break;
10491                         }
10492                 }
10493
10494                 /* If we disable the crtc, disable all its connectors. Also, if
10495                  * the connector is on the changing crtc but not on the new
10496                  * connector list, disable it. */
10497                 if ((!set->fb || ro == set->num_connectors) &&
10498                     connector->base.encoder &&
10499                     connector->base.encoder->crtc == set->crtc) {
10500                         connector->new_encoder = NULL;
10501
10502                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10503                                 connector->base.base.id,
10504                                 drm_get_connector_name(&connector->base));
10505                 }
10506
10507
10508                 if (&connector->new_encoder->base != connector->base.encoder) {
10509                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10510                         config->mode_changed = true;
10511                 }
10512         }
10513         /* connector->new_encoder is now updated for all connectors. */
10514
10515         /* Update crtc of enabled connectors. */
10516         list_for_each_entry(connector, &dev->mode_config.connector_list,
10517                             base.head) {
10518                 struct drm_crtc *new_crtc;
10519
10520                 if (!connector->new_encoder)
10521                         continue;
10522
10523                 new_crtc = connector->new_encoder->base.crtc;
10524
10525                 for (ro = 0; ro < set->num_connectors; ro++) {
10526                         if (set->connectors[ro] == &connector->base)
10527                                 new_crtc = set->crtc;
10528                 }
10529
10530                 /* Make sure the new CRTC will work with the encoder */
10531                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10532                                          new_crtc)) {
10533                         return -EINVAL;
10534                 }
10535                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10536
10537                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10538                         connector->base.base.id,
10539                         drm_get_connector_name(&connector->base),
10540                         new_crtc->base.id);
10541         }
10542
10543         /* Check for any encoders that needs to be disabled. */
10544         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10545                             base.head) {
10546                 int num_connectors = 0;
10547                 list_for_each_entry(connector,
10548                                     &dev->mode_config.connector_list,
10549                                     base.head) {
10550                         if (connector->new_encoder == encoder) {
10551                                 WARN_ON(!connector->new_encoder->new_crtc);
10552                                 num_connectors++;
10553                         }
10554                 }
10555
10556                 if (num_connectors == 0)
10557                         encoder->new_crtc = NULL;
10558                 else if (num_connectors > 1)
10559                         return -EINVAL;
10560
10561                 /* Only now check for crtc changes so we don't miss encoders
10562                  * that will be disabled. */
10563                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10564                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10565                         config->mode_changed = true;
10566                 }
10567         }
10568         /* Now we've also updated encoder->new_crtc for all encoders. */
10569
10570         for_each_intel_crtc(dev, crtc) {
10571                 crtc->new_enabled = false;
10572
10573                 list_for_each_entry(encoder,
10574                                     &dev->mode_config.encoder_list,
10575                                     base.head) {
10576                         if (encoder->new_crtc == crtc) {
10577                                 crtc->new_enabled = true;
10578                                 break;
10579                         }
10580                 }
10581
10582                 if (crtc->new_enabled != crtc->base.enabled) {
10583                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10584                                       crtc->new_enabled ? "en" : "dis");
10585                         config->mode_changed = true;
10586                 }
10587
10588                 if (crtc->new_enabled)
10589                         crtc->new_config = &crtc->config;
10590                 else
10591                         crtc->new_config = NULL;
10592         }
10593
10594         return 0;
10595 }
10596
10597 static void disable_crtc_nofb(struct intel_crtc *crtc)
10598 {
10599         struct drm_device *dev = crtc->base.dev;
10600         struct intel_encoder *encoder;
10601         struct intel_connector *connector;
10602
10603         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10604                       pipe_name(crtc->pipe));
10605
10606         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10607                 if (connector->new_encoder &&
10608                     connector->new_encoder->new_crtc == crtc)
10609                         connector->new_encoder = NULL;
10610         }
10611
10612         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10613                 if (encoder->new_crtc == crtc)
10614                         encoder->new_crtc = NULL;
10615         }
10616
10617         crtc->new_enabled = false;
10618         crtc->new_config = NULL;
10619 }
10620
10621 static int intel_crtc_set_config(struct drm_mode_set *set)
10622 {
10623         struct drm_device *dev;
10624         struct drm_mode_set save_set;
10625         struct intel_set_config *config;
10626         int ret;
10627
10628         BUG_ON(!set);
10629         BUG_ON(!set->crtc);
10630         BUG_ON(!set->crtc->helper_private);
10631
10632         /* Enforce sane interface api - has been abused by the fb helper. */
10633         BUG_ON(!set->mode && set->fb);
10634         BUG_ON(set->fb && set->num_connectors == 0);
10635
10636         if (set->fb) {
10637                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10638                                 set->crtc->base.id, set->fb->base.id,
10639                                 (int)set->num_connectors, set->x, set->y);
10640         } else {
10641                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10642         }
10643
10644         dev = set->crtc->dev;
10645
10646         ret = -ENOMEM;
10647         config = kzalloc(sizeof(*config), GFP_KERNEL);
10648         if (!config)
10649                 goto out_config;
10650
10651         ret = intel_set_config_save_state(dev, config);
10652         if (ret)
10653                 goto out_config;
10654
10655         save_set.crtc = set->crtc;
10656         save_set.mode = &set->crtc->mode;
10657         save_set.x = set->crtc->x;
10658         save_set.y = set->crtc->y;
10659         save_set.fb = set->crtc->primary->fb;
10660
10661         /* Compute whether we need a full modeset, only an fb base update or no
10662          * change at all. In the future we might also check whether only the
10663          * mode changed, e.g. for LVDS where we only change the panel fitter in
10664          * such cases. */
10665         intel_set_config_compute_mode_changes(set, config);
10666
10667         ret = intel_modeset_stage_output_state(dev, set, config);
10668         if (ret)
10669                 goto fail;
10670
10671         if (config->mode_changed) {
10672                 ret = intel_set_mode(set->crtc, set->mode,
10673                                      set->x, set->y, set->fb);
10674         } else if (config->fb_changed) {
10675                 intel_crtc_wait_for_pending_flips(set->crtc);
10676
10677                 ret = intel_pipe_set_base(set->crtc,
10678                                           set->x, set->y, set->fb);
10679                 /*
10680                  * In the fastboot case this may be our only check of the
10681                  * state after boot.  It would be better to only do it on
10682                  * the first update, but we don't have a nice way of doing that
10683                  * (and really, set_config isn't used much for high freq page
10684                  * flipping, so increasing its cost here shouldn't be a big
10685                  * deal).
10686                  */
10687                 if (i915.fastboot && ret == 0)
10688                         intel_modeset_check_state(set->crtc->dev);
10689         }
10690
10691         if (ret) {
10692                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10693                               set->crtc->base.id, ret);
10694 fail:
10695                 intel_set_config_restore_state(dev, config);
10696
10697                 /*
10698                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10699                  * force the pipe off to avoid oopsing in the modeset code
10700                  * due to fb==NULL. This should only happen during boot since
10701                  * we don't yet reconstruct the FB from the hardware state.
10702                  */
10703                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10704                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10705
10706                 /* Try to restore the config */
10707                 if (config->mode_changed &&
10708                     intel_set_mode(save_set.crtc, save_set.mode,
10709                                    save_set.x, save_set.y, save_set.fb))
10710                         DRM_ERROR("failed to restore config after modeset failure\n");
10711         }
10712
10713 out_config:
10714         intel_set_config_free(config);
10715         return ret;
10716 }
10717
10718 static const struct drm_crtc_funcs intel_crtc_funcs = {
10719         .cursor_set = intel_crtc_cursor_set,
10720         .cursor_move = intel_crtc_cursor_move,
10721         .gamma_set = intel_crtc_gamma_set,
10722         .set_config = intel_crtc_set_config,
10723         .destroy = intel_crtc_destroy,
10724         .page_flip = intel_crtc_page_flip,
10725 };
10726
10727 static void intel_cpu_pll_init(struct drm_device *dev)
10728 {
10729         if (HAS_DDI(dev))
10730                 intel_ddi_pll_init(dev);
10731 }
10732
10733 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10734                                       struct intel_shared_dpll *pll,
10735                                       struct intel_dpll_hw_state *hw_state)
10736 {
10737         uint32_t val;
10738
10739         val = I915_READ(PCH_DPLL(pll->id));
10740         hw_state->dpll = val;
10741         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10742         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10743
10744         return val & DPLL_VCO_ENABLE;
10745 }
10746
10747 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10748                                   struct intel_shared_dpll *pll)
10749 {
10750         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10751         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10752 }
10753
10754 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10755                                 struct intel_shared_dpll *pll)
10756 {
10757         /* PCH refclock must be enabled first */
10758         ibx_assert_pch_refclk_enabled(dev_priv);
10759
10760         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10761
10762         /* Wait for the clocks to stabilize. */
10763         POSTING_READ(PCH_DPLL(pll->id));
10764         udelay(150);
10765
10766         /* The pixel multiplier can only be updated once the
10767          * DPLL is enabled and the clocks are stable.
10768          *
10769          * So write it again.
10770          */
10771         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10772         POSTING_READ(PCH_DPLL(pll->id));
10773         udelay(200);
10774 }
10775
10776 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10777                                  struct intel_shared_dpll *pll)
10778 {
10779         struct drm_device *dev = dev_priv->dev;
10780         struct intel_crtc *crtc;
10781
10782         /* Make sure no transcoder isn't still depending on us. */
10783         for_each_intel_crtc(dev, crtc) {
10784                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10785                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10786         }
10787
10788         I915_WRITE(PCH_DPLL(pll->id), 0);
10789         POSTING_READ(PCH_DPLL(pll->id));
10790         udelay(200);
10791 }
10792
10793 static char *ibx_pch_dpll_names[] = {
10794         "PCH DPLL A",
10795         "PCH DPLL B",
10796 };
10797
10798 static void ibx_pch_dpll_init(struct drm_device *dev)
10799 {
10800         struct drm_i915_private *dev_priv = dev->dev_private;
10801         int i;
10802
10803         dev_priv->num_shared_dpll = 2;
10804
10805         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10806                 dev_priv->shared_dplls[i].id = i;
10807                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10808                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10809                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10810                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10811                 dev_priv->shared_dplls[i].get_hw_state =
10812                         ibx_pch_dpll_get_hw_state;
10813         }
10814 }
10815
10816 static void intel_shared_dpll_init(struct drm_device *dev)
10817 {
10818         struct drm_i915_private *dev_priv = dev->dev_private;
10819
10820         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10821                 ibx_pch_dpll_init(dev);
10822         else
10823                 dev_priv->num_shared_dpll = 0;
10824
10825         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10826 }
10827
10828 static void intel_crtc_init(struct drm_device *dev, int pipe)
10829 {
10830         struct drm_i915_private *dev_priv = dev->dev_private;
10831         struct intel_crtc *intel_crtc;
10832         int i;
10833
10834         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10835         if (intel_crtc == NULL)
10836                 return;
10837
10838         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10839
10840         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10841         for (i = 0; i < 256; i++) {
10842                 intel_crtc->lut_r[i] = i;
10843                 intel_crtc->lut_g[i] = i;
10844                 intel_crtc->lut_b[i] = i;
10845         }
10846
10847         /*
10848          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10849          * is hooked to plane B. Hence we want plane A feeding pipe B.
10850          */
10851         intel_crtc->pipe = pipe;
10852         intel_crtc->plane = pipe;
10853         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10854                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10855                 intel_crtc->plane = !pipe;
10856         }
10857
10858         init_waitqueue_head(&intel_crtc->vbl_wait);
10859
10860         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10861                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10862         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10863         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10864
10865         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10866 }
10867
10868 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10869 {
10870         struct drm_encoder *encoder = connector->base.encoder;
10871
10872         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10873
10874         if (!encoder)
10875                 return INVALID_PIPE;
10876
10877         return to_intel_crtc(encoder->crtc)->pipe;
10878 }
10879
10880 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10881                                 struct drm_file *file)
10882 {
10883         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10884         struct drm_mode_object *drmmode_obj;
10885         struct intel_crtc *crtc;
10886
10887         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10888                 return -ENODEV;
10889
10890         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10891                         DRM_MODE_OBJECT_CRTC);
10892
10893         if (!drmmode_obj) {
10894                 DRM_ERROR("no such CRTC id\n");
10895                 return -ENOENT;
10896         }
10897
10898         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10899         pipe_from_crtc_id->pipe = crtc->pipe;
10900
10901         return 0;
10902 }
10903
10904 static int intel_encoder_clones(struct intel_encoder *encoder)
10905 {
10906         struct drm_device *dev = encoder->base.dev;
10907         struct intel_encoder *source_encoder;
10908         int index_mask = 0;
10909         int entry = 0;
10910
10911         list_for_each_entry(source_encoder,
10912                             &dev->mode_config.encoder_list, base.head) {
10913                 if (encoders_cloneable(encoder, source_encoder))
10914                         index_mask |= (1 << entry);
10915
10916                 entry++;
10917         }
10918
10919         return index_mask;
10920 }
10921
10922 static bool has_edp_a(struct drm_device *dev)
10923 {
10924         struct drm_i915_private *dev_priv = dev->dev_private;
10925
10926         if (!IS_MOBILE(dev))
10927                 return false;
10928
10929         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10930                 return false;
10931
10932         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10933                 return false;
10934
10935         return true;
10936 }
10937
10938 const char *intel_output_name(int output)
10939 {
10940         static const char *names[] = {
10941                 [INTEL_OUTPUT_UNUSED] = "Unused",
10942                 [INTEL_OUTPUT_ANALOG] = "Analog",
10943                 [INTEL_OUTPUT_DVO] = "DVO",
10944                 [INTEL_OUTPUT_SDVO] = "SDVO",
10945                 [INTEL_OUTPUT_LVDS] = "LVDS",
10946                 [INTEL_OUTPUT_TVOUT] = "TV",
10947                 [INTEL_OUTPUT_HDMI] = "HDMI",
10948                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10949                 [INTEL_OUTPUT_EDP] = "eDP",
10950                 [INTEL_OUTPUT_DSI] = "DSI",
10951                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10952         };
10953
10954         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10955                 return "Invalid";
10956
10957         return names[output];
10958 }
10959
10960 static void intel_setup_outputs(struct drm_device *dev)
10961 {
10962         struct drm_i915_private *dev_priv = dev->dev_private;
10963         struct intel_encoder *encoder;
10964         bool dpd_is_edp = false;
10965
10966         intel_lvds_init(dev);
10967
10968         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10969                 intel_crt_init(dev);
10970
10971         if (HAS_DDI(dev)) {
10972                 int found;
10973
10974                 /* Haswell uses DDI functions to detect digital outputs */
10975                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10976                 /* DDI A only supports eDP */
10977                 if (found)
10978                         intel_ddi_init(dev, PORT_A);
10979
10980                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10981                  * register */
10982                 found = I915_READ(SFUSE_STRAP);
10983
10984                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10985                         intel_ddi_init(dev, PORT_B);
10986                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10987                         intel_ddi_init(dev, PORT_C);
10988                 if (found & SFUSE_STRAP_DDID_DETECTED)
10989                         intel_ddi_init(dev, PORT_D);
10990         } else if (HAS_PCH_SPLIT(dev)) {
10991                 int found;
10992                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10993
10994                 if (has_edp_a(dev))
10995                         intel_dp_init(dev, DP_A, PORT_A);
10996
10997                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10998                         /* PCH SDVOB multiplex with HDMIB */
10999                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11000                         if (!found)
11001                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11002                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11003                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11004                 }
11005
11006                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11007                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11008
11009                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11010                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11011
11012                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11013                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11014
11015                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11016                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11017         } else if (IS_VALLEYVIEW(dev)) {
11018                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11019                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11020                                         PORT_B);
11021                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11022                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11023                 }
11024
11025                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11026                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11027                                         PORT_C);
11028                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11029                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11030                 }
11031
11032                 intel_dsi_init(dev);
11033         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11034                 bool found = false;
11035
11036                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11037                         DRM_DEBUG_KMS("probing SDVOB\n");
11038                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11039                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11040                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11041                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11042                         }
11043
11044                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11045                                 intel_dp_init(dev, DP_B, PORT_B);
11046                 }
11047
11048                 /* Before G4X SDVOC doesn't have its own detect register */
11049
11050                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11051                         DRM_DEBUG_KMS("probing SDVOC\n");
11052                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11053                 }
11054
11055                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11056
11057                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11058                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11059                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11060                         }
11061                         if (SUPPORTS_INTEGRATED_DP(dev))
11062                                 intel_dp_init(dev, DP_C, PORT_C);
11063                 }
11064
11065                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11066                     (I915_READ(DP_D) & DP_DETECTED))
11067                         intel_dp_init(dev, DP_D, PORT_D);
11068         } else if (IS_GEN2(dev))
11069                 intel_dvo_init(dev);
11070
11071         if (SUPPORTS_TV(dev))
11072                 intel_tv_init(dev);
11073
11074         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11075                 encoder->base.possible_crtcs = encoder->crtc_mask;
11076                 encoder->base.possible_clones =
11077                         intel_encoder_clones(encoder);
11078         }
11079
11080         intel_init_pch_refclk(dev);
11081
11082         drm_helper_move_panel_connectors_to_head(dev);
11083 }
11084
11085 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11086 {
11087         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11088
11089         drm_framebuffer_cleanup(fb);
11090         WARN_ON(!intel_fb->obj->framebuffer_references--);
11091         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11092         kfree(intel_fb);
11093 }
11094
11095 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11096                                                 struct drm_file *file,
11097                                                 unsigned int *handle)
11098 {
11099         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11100         struct drm_i915_gem_object *obj = intel_fb->obj;
11101
11102         return drm_gem_handle_create(file, &obj->base, handle);
11103 }
11104
11105 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11106         .destroy = intel_user_framebuffer_destroy,
11107         .create_handle = intel_user_framebuffer_create_handle,
11108 };
11109
11110 static int intel_framebuffer_init(struct drm_device *dev,
11111                                   struct intel_framebuffer *intel_fb,
11112                                   struct drm_mode_fb_cmd2 *mode_cmd,
11113                                   struct drm_i915_gem_object *obj)
11114 {
11115         int aligned_height;
11116         int pitch_limit;
11117         int ret;
11118
11119         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11120
11121         if (obj->tiling_mode == I915_TILING_Y) {
11122                 DRM_DEBUG("hardware does not support tiling Y\n");
11123                 return -EINVAL;
11124         }
11125
11126         if (mode_cmd->pitches[0] & 63) {
11127                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11128                           mode_cmd->pitches[0]);
11129                 return -EINVAL;
11130         }
11131
11132         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11133                 pitch_limit = 32*1024;
11134         } else if (INTEL_INFO(dev)->gen >= 4) {
11135                 if (obj->tiling_mode)
11136                         pitch_limit = 16*1024;
11137                 else
11138                         pitch_limit = 32*1024;
11139         } else if (INTEL_INFO(dev)->gen >= 3) {
11140                 if (obj->tiling_mode)
11141                         pitch_limit = 8*1024;
11142                 else
11143                         pitch_limit = 16*1024;
11144         } else
11145                 /* XXX DSPC is limited to 4k tiled */
11146                 pitch_limit = 8*1024;
11147
11148         if (mode_cmd->pitches[0] > pitch_limit) {
11149                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11150                           obj->tiling_mode ? "tiled" : "linear",
11151                           mode_cmd->pitches[0], pitch_limit);
11152                 return -EINVAL;
11153         }
11154
11155         if (obj->tiling_mode != I915_TILING_NONE &&
11156             mode_cmd->pitches[0] != obj->stride) {
11157                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11158                           mode_cmd->pitches[0], obj->stride);
11159                 return -EINVAL;
11160         }
11161
11162         /* Reject formats not supported by any plane early. */
11163         switch (mode_cmd->pixel_format) {
11164         case DRM_FORMAT_C8:
11165         case DRM_FORMAT_RGB565:
11166         case DRM_FORMAT_XRGB8888:
11167         case DRM_FORMAT_ARGB8888:
11168                 break;
11169         case DRM_FORMAT_XRGB1555:
11170         case DRM_FORMAT_ARGB1555:
11171                 if (INTEL_INFO(dev)->gen > 3) {
11172                         DRM_DEBUG("unsupported pixel format: %s\n",
11173                                   drm_get_format_name(mode_cmd->pixel_format));
11174                         return -EINVAL;
11175                 }
11176                 break;
11177         case DRM_FORMAT_XBGR8888:
11178         case DRM_FORMAT_ABGR8888:
11179         case DRM_FORMAT_XRGB2101010:
11180         case DRM_FORMAT_ARGB2101010:
11181         case DRM_FORMAT_XBGR2101010:
11182         case DRM_FORMAT_ABGR2101010:
11183                 if (INTEL_INFO(dev)->gen < 4) {
11184                         DRM_DEBUG("unsupported pixel format: %s\n",
11185                                   drm_get_format_name(mode_cmd->pixel_format));
11186                         return -EINVAL;
11187                 }
11188                 break;
11189         case DRM_FORMAT_YUYV:
11190         case DRM_FORMAT_UYVY:
11191         case DRM_FORMAT_YVYU:
11192         case DRM_FORMAT_VYUY:
11193                 if (INTEL_INFO(dev)->gen < 5) {
11194                         DRM_DEBUG("unsupported pixel format: %s\n",
11195                                   drm_get_format_name(mode_cmd->pixel_format));
11196                         return -EINVAL;
11197                 }
11198                 break;
11199         default:
11200                 DRM_DEBUG("unsupported pixel format: %s\n",
11201                           drm_get_format_name(mode_cmd->pixel_format));
11202                 return -EINVAL;
11203         }
11204
11205         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11206         if (mode_cmd->offsets[0] != 0)
11207                 return -EINVAL;
11208
11209         aligned_height = intel_align_height(dev, mode_cmd->height,
11210                                             obj->tiling_mode);
11211         /* FIXME drm helper for size checks (especially planar formats)? */
11212         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11213                 return -EINVAL;
11214
11215         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11216         intel_fb->obj = obj;
11217         intel_fb->obj->framebuffer_references++;
11218
11219         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11220         if (ret) {
11221                 DRM_ERROR("framebuffer init failed %d\n", ret);
11222                 return ret;
11223         }
11224
11225         return 0;
11226 }
11227
11228 static struct drm_framebuffer *
11229 intel_user_framebuffer_create(struct drm_device *dev,
11230                               struct drm_file *filp,
11231                               struct drm_mode_fb_cmd2 *mode_cmd)
11232 {
11233         struct drm_i915_gem_object *obj;
11234
11235         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11236                                                 mode_cmd->handles[0]));
11237         if (&obj->base == NULL)
11238                 return ERR_PTR(-ENOENT);
11239
11240         return intel_framebuffer_create(dev, mode_cmd, obj);
11241 }
11242
11243 #ifndef CONFIG_DRM_I915_FBDEV
11244 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11245 {
11246 }
11247 #endif
11248
11249 static const struct drm_mode_config_funcs intel_mode_funcs = {
11250         .fb_create = intel_user_framebuffer_create,
11251         .output_poll_changed = intel_fbdev_output_poll_changed,
11252 };
11253
11254 /* Set up chip specific display functions */
11255 static void intel_init_display(struct drm_device *dev)
11256 {
11257         struct drm_i915_private *dev_priv = dev->dev_private;
11258
11259         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11260                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11261         else if (IS_CHERRYVIEW(dev))
11262                 dev_priv->display.find_dpll = chv_find_best_dpll;
11263         else if (IS_VALLEYVIEW(dev))
11264                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11265         else if (IS_PINEVIEW(dev))
11266                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11267         else
11268                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11269
11270         if (HAS_DDI(dev)) {
11271                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11272                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11273                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11274                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11275                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11276                 dev_priv->display.off = haswell_crtc_off;
11277                 dev_priv->display.update_primary_plane =
11278                         ironlake_update_primary_plane;
11279         } else if (HAS_PCH_SPLIT(dev)) {
11280                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11281                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11282                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11283                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11284                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11285                 dev_priv->display.off = ironlake_crtc_off;
11286                 dev_priv->display.update_primary_plane =
11287                         ironlake_update_primary_plane;
11288         } else if (IS_VALLEYVIEW(dev)) {
11289                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11290                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11291                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11292                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11293                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11294                 dev_priv->display.off = i9xx_crtc_off;
11295                 dev_priv->display.update_primary_plane =
11296                         i9xx_update_primary_plane;
11297         } else {
11298                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11299                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11300                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11301                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11302                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11303                 dev_priv->display.off = i9xx_crtc_off;
11304                 dev_priv->display.update_primary_plane =
11305                         i9xx_update_primary_plane;
11306         }
11307
11308         /* Returns the core display clock speed */
11309         if (IS_VALLEYVIEW(dev))
11310                 dev_priv->display.get_display_clock_speed =
11311                         valleyview_get_display_clock_speed;
11312         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11313                 dev_priv->display.get_display_clock_speed =
11314                         i945_get_display_clock_speed;
11315         else if (IS_I915G(dev))
11316                 dev_priv->display.get_display_clock_speed =
11317                         i915_get_display_clock_speed;
11318         else if (IS_I945GM(dev) || IS_845G(dev))
11319                 dev_priv->display.get_display_clock_speed =
11320                         i9xx_misc_get_display_clock_speed;
11321         else if (IS_PINEVIEW(dev))
11322                 dev_priv->display.get_display_clock_speed =
11323                         pnv_get_display_clock_speed;
11324         else if (IS_I915GM(dev))
11325                 dev_priv->display.get_display_clock_speed =
11326                         i915gm_get_display_clock_speed;
11327         else if (IS_I865G(dev))
11328                 dev_priv->display.get_display_clock_speed =
11329                         i865_get_display_clock_speed;
11330         else if (IS_I85X(dev))
11331                 dev_priv->display.get_display_clock_speed =
11332                         i855_get_display_clock_speed;
11333         else /* 852, 830 */
11334                 dev_priv->display.get_display_clock_speed =
11335                         i830_get_display_clock_speed;
11336
11337         if (HAS_PCH_SPLIT(dev)) {
11338                 if (IS_GEN5(dev)) {
11339                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11340                         dev_priv->display.write_eld = ironlake_write_eld;
11341                 } else if (IS_GEN6(dev)) {
11342                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11343                         dev_priv->display.write_eld = ironlake_write_eld;
11344                         dev_priv->display.modeset_global_resources =
11345                                 snb_modeset_global_resources;
11346                 } else if (IS_IVYBRIDGE(dev)) {
11347                         /* FIXME: detect B0+ stepping and use auto training */
11348                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11349                         dev_priv->display.write_eld = ironlake_write_eld;
11350                         dev_priv->display.modeset_global_resources =
11351                                 ivb_modeset_global_resources;
11352                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11353                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11354                         dev_priv->display.write_eld = haswell_write_eld;
11355                         dev_priv->display.modeset_global_resources =
11356                                 haswell_modeset_global_resources;
11357                 }
11358         } else if (IS_G4X(dev)) {
11359                 dev_priv->display.write_eld = g4x_write_eld;
11360         } else if (IS_VALLEYVIEW(dev)) {
11361                 dev_priv->display.modeset_global_resources =
11362                         valleyview_modeset_global_resources;
11363                 dev_priv->display.write_eld = ironlake_write_eld;
11364         }
11365
11366         /* Default just returns -ENODEV to indicate unsupported */
11367         dev_priv->display.queue_flip = intel_default_queue_flip;
11368
11369         switch (INTEL_INFO(dev)->gen) {
11370         case 2:
11371                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11372                 break;
11373
11374         case 3:
11375                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11376                 break;
11377
11378         case 4:
11379         case 5:
11380                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11381                 break;
11382
11383         case 6:
11384                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11385                 break;
11386         case 7:
11387         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11388                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11389                 break;
11390         }
11391
11392         intel_panel_init_backlight_funcs(dev);
11393 }
11394
11395 /*
11396  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11397  * resume, or other times.  This quirk makes sure that's the case for
11398  * affected systems.
11399  */
11400 static void quirk_pipea_force(struct drm_device *dev)
11401 {
11402         struct drm_i915_private *dev_priv = dev->dev_private;
11403
11404         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11405         DRM_INFO("applying pipe a force quirk\n");
11406 }
11407
11408 /*
11409  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11410  */
11411 static void quirk_ssc_force_disable(struct drm_device *dev)
11412 {
11413         struct drm_i915_private *dev_priv = dev->dev_private;
11414         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11415         DRM_INFO("applying lvds SSC disable quirk\n");
11416 }
11417
11418 /*
11419  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11420  * brightness value
11421  */
11422 static void quirk_invert_brightness(struct drm_device *dev)
11423 {
11424         struct drm_i915_private *dev_priv = dev->dev_private;
11425         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11426         DRM_INFO("applying inverted panel brightness quirk\n");
11427 }
11428
11429 struct intel_quirk {
11430         int device;
11431         int subsystem_vendor;
11432         int subsystem_device;
11433         void (*hook)(struct drm_device *dev);
11434 };
11435
11436 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11437 struct intel_dmi_quirk {
11438         void (*hook)(struct drm_device *dev);
11439         const struct dmi_system_id (*dmi_id_list)[];
11440 };
11441
11442 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11443 {
11444         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11445         return 1;
11446 }
11447
11448 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11449         {
11450                 .dmi_id_list = &(const struct dmi_system_id[]) {
11451                         {
11452                                 .callback = intel_dmi_reverse_brightness,
11453                                 .ident = "NCR Corporation",
11454                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11455                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11456                                 },
11457                         },
11458                         { }  /* terminating entry */
11459                 },
11460                 .hook = quirk_invert_brightness,
11461         },
11462 };
11463
11464 static struct intel_quirk intel_quirks[] = {
11465         /* HP Mini needs pipe A force quirk (LP: #322104) */
11466         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11467
11468         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11469         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11470
11471         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11472         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11473
11474         /* 830 needs to leave pipe A & dpll A up */
11475         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11476
11477         /* Lenovo U160 cannot use SSC on LVDS */
11478         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11479
11480         /* Sony Vaio Y cannot use SSC on LVDS */
11481         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11482
11483         /* Acer Aspire 5734Z must invert backlight brightness */
11484         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11485
11486         /* Acer/eMachines G725 */
11487         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11488
11489         /* Acer/eMachines e725 */
11490         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11491
11492         /* Acer/Packard Bell NCL20 */
11493         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11494
11495         /* Acer Aspire 4736Z */
11496         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11497
11498         /* Acer Aspire 5336 */
11499         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11500 };
11501
11502 static void intel_init_quirks(struct drm_device *dev)
11503 {
11504         struct pci_dev *d = dev->pdev;
11505         int i;
11506
11507         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11508                 struct intel_quirk *q = &intel_quirks[i];
11509
11510                 if (d->device == q->device &&
11511                     (d->subsystem_vendor == q->subsystem_vendor ||
11512                      q->subsystem_vendor == PCI_ANY_ID) &&
11513                     (d->subsystem_device == q->subsystem_device ||
11514                      q->subsystem_device == PCI_ANY_ID))
11515                         q->hook(dev);
11516         }
11517         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11518                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11519                         intel_dmi_quirks[i].hook(dev);
11520         }
11521 }
11522
11523 /* Disable the VGA plane that we never use */
11524 static void i915_disable_vga(struct drm_device *dev)
11525 {
11526         struct drm_i915_private *dev_priv = dev->dev_private;
11527         u8 sr1;
11528         u32 vga_reg = i915_vgacntrl_reg(dev);
11529
11530         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11531         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11532         outb(SR01, VGA_SR_INDEX);
11533         sr1 = inb(VGA_SR_DATA);
11534         outb(sr1 | 1<<5, VGA_SR_DATA);
11535         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11536         udelay(300);
11537
11538         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11539         POSTING_READ(vga_reg);
11540 }
11541
11542 void intel_modeset_init_hw(struct drm_device *dev)
11543 {
11544         intel_prepare_ddi(dev);
11545
11546         intel_init_clock_gating(dev);
11547
11548         intel_reset_dpio(dev);
11549
11550         intel_enable_gt_powersave(dev);
11551 }
11552
11553 void intel_modeset_suspend_hw(struct drm_device *dev)
11554 {
11555         intel_suspend_hw(dev);
11556 }
11557
11558 void intel_modeset_init(struct drm_device *dev)
11559 {
11560         struct drm_i915_private *dev_priv = dev->dev_private;
11561         int sprite, ret;
11562         enum pipe pipe;
11563         struct intel_crtc *crtc;
11564
11565         drm_mode_config_init(dev);
11566
11567         dev->mode_config.min_width = 0;
11568         dev->mode_config.min_height = 0;
11569
11570         dev->mode_config.preferred_depth = 24;
11571         dev->mode_config.prefer_shadow = 1;
11572
11573         dev->mode_config.funcs = &intel_mode_funcs;
11574
11575         intel_init_quirks(dev);
11576
11577         intel_init_pm(dev);
11578
11579         if (INTEL_INFO(dev)->num_pipes == 0)
11580                 return;
11581
11582         intel_init_display(dev);
11583
11584         if (IS_GEN2(dev)) {
11585                 dev->mode_config.max_width = 2048;
11586                 dev->mode_config.max_height = 2048;
11587         } else if (IS_GEN3(dev)) {
11588                 dev->mode_config.max_width = 4096;
11589                 dev->mode_config.max_height = 4096;
11590         } else {
11591                 dev->mode_config.max_width = 8192;
11592                 dev->mode_config.max_height = 8192;
11593         }
11594
11595         if (IS_GEN2(dev)) {
11596                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11597                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11598         } else {
11599                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11600                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11601         }
11602
11603         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11604
11605         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11606                       INTEL_INFO(dev)->num_pipes,
11607                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11608
11609         for_each_pipe(pipe) {
11610                 intel_crtc_init(dev, pipe);
11611                 for_each_sprite(pipe, sprite) {
11612                         ret = intel_plane_init(dev, pipe, sprite);
11613                         if (ret)
11614                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11615                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11616                 }
11617         }
11618
11619         intel_init_dpio(dev);
11620         intel_reset_dpio(dev);
11621
11622         intel_cpu_pll_init(dev);
11623         intel_shared_dpll_init(dev);
11624
11625         /* Just disable it once at startup */
11626         i915_disable_vga(dev);
11627         intel_setup_outputs(dev);
11628
11629         /* Just in case the BIOS is doing something questionable. */
11630         intel_disable_fbc(dev);
11631
11632         mutex_lock(&dev->mode_config.mutex);
11633         intel_modeset_setup_hw_state(dev, false);
11634         mutex_unlock(&dev->mode_config.mutex);
11635
11636         for_each_intel_crtc(dev, crtc) {
11637                 if (!crtc->active)
11638                         continue;
11639
11640                 /*
11641                  * Note that reserving the BIOS fb up front prevents us
11642                  * from stuffing other stolen allocations like the ring
11643                  * on top.  This prevents some ugliness at boot time, and
11644                  * can even allow for smooth boot transitions if the BIOS
11645                  * fb is large enough for the active pipe configuration.
11646                  */
11647                 if (dev_priv->display.get_plane_config) {
11648                         dev_priv->display.get_plane_config(crtc,
11649                                                            &crtc->plane_config);
11650                         /*
11651                          * If the fb is shared between multiple heads, we'll
11652                          * just get the first one.
11653                          */
11654                         intel_find_plane_obj(crtc, &crtc->plane_config);
11655                 }
11656         }
11657 }
11658
11659 static void
11660 intel_connector_break_all_links(struct intel_connector *connector)
11661 {
11662         connector->base.dpms = DRM_MODE_DPMS_OFF;
11663         connector->base.encoder = NULL;
11664         connector->encoder->connectors_active = false;
11665         connector->encoder->base.crtc = NULL;
11666 }
11667
11668 static void intel_enable_pipe_a(struct drm_device *dev)
11669 {
11670         struct intel_connector *connector;
11671         struct drm_connector *crt = NULL;
11672         struct intel_load_detect_pipe load_detect_temp;
11673
11674         /* We can't just switch on the pipe A, we need to set things up with a
11675          * proper mode and output configuration. As a gross hack, enable pipe A
11676          * by enabling the load detect pipe once. */
11677         list_for_each_entry(connector,
11678                             &dev->mode_config.connector_list,
11679                             base.head) {
11680                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11681                         crt = &connector->base;
11682                         break;
11683                 }
11684         }
11685
11686         if (!crt)
11687                 return;
11688
11689         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11690                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11691
11692
11693 }
11694
11695 static bool
11696 intel_check_plane_mapping(struct intel_crtc *crtc)
11697 {
11698         struct drm_device *dev = crtc->base.dev;
11699         struct drm_i915_private *dev_priv = dev->dev_private;
11700         u32 reg, val;
11701
11702         if (INTEL_INFO(dev)->num_pipes == 1)
11703                 return true;
11704
11705         reg = DSPCNTR(!crtc->plane);
11706         val = I915_READ(reg);
11707
11708         if ((val & DISPLAY_PLANE_ENABLE) &&
11709             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11710                 return false;
11711
11712         return true;
11713 }
11714
11715 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11716 {
11717         struct drm_device *dev = crtc->base.dev;
11718         struct drm_i915_private *dev_priv = dev->dev_private;
11719         u32 reg;
11720
11721         /* Clear any frame start delays used for debugging left by the BIOS */
11722         reg = PIPECONF(crtc->config.cpu_transcoder);
11723         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11724
11725         /* We need to sanitize the plane -> pipe mapping first because this will
11726          * disable the crtc (and hence change the state) if it is wrong. Note
11727          * that gen4+ has a fixed plane -> pipe mapping.  */
11728         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11729                 struct intel_connector *connector;
11730                 bool plane;
11731
11732                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11733                               crtc->base.base.id);
11734
11735                 /* Pipe has the wrong plane attached and the plane is active.
11736                  * Temporarily change the plane mapping and disable everything
11737                  * ...  */
11738                 plane = crtc->plane;
11739                 crtc->plane = !plane;
11740                 dev_priv->display.crtc_disable(&crtc->base);
11741                 crtc->plane = plane;
11742
11743                 /* ... and break all links. */
11744                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11745                                     base.head) {
11746                         if (connector->encoder->base.crtc != &crtc->base)
11747                                 continue;
11748
11749                         intel_connector_break_all_links(connector);
11750                 }
11751
11752                 WARN_ON(crtc->active);
11753                 crtc->base.enabled = false;
11754         }
11755
11756         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11757             crtc->pipe == PIPE_A && !crtc->active) {
11758                 /* BIOS forgot to enable pipe A, this mostly happens after
11759                  * resume. Force-enable the pipe to fix this, the update_dpms
11760                  * call below we restore the pipe to the right state, but leave
11761                  * the required bits on. */
11762                 intel_enable_pipe_a(dev);
11763         }
11764
11765         /* Adjust the state of the output pipe according to whether we
11766          * have active connectors/encoders. */
11767         intel_crtc_update_dpms(&crtc->base);
11768
11769         if (crtc->active != crtc->base.enabled) {
11770                 struct intel_encoder *encoder;
11771
11772                 /* This can happen either due to bugs in the get_hw_state
11773                  * functions or because the pipe is force-enabled due to the
11774                  * pipe A quirk. */
11775                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11776                               crtc->base.base.id,
11777                               crtc->base.enabled ? "enabled" : "disabled",
11778                               crtc->active ? "enabled" : "disabled");
11779
11780                 crtc->base.enabled = crtc->active;
11781
11782                 /* Because we only establish the connector -> encoder ->
11783                  * crtc links if something is active, this means the
11784                  * crtc is now deactivated. Break the links. connector
11785                  * -> encoder links are only establish when things are
11786                  *  actually up, hence no need to break them. */
11787                 WARN_ON(crtc->active);
11788
11789                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11790                         WARN_ON(encoder->connectors_active);
11791                         encoder->base.crtc = NULL;
11792                 }
11793         }
11794         if (crtc->active) {
11795                 /*
11796                  * We start out with underrun reporting disabled to avoid races.
11797                  * For correct bookkeeping mark this on active crtcs.
11798                  *
11799                  * No protection against concurrent access is required - at
11800                  * worst a fifo underrun happens which also sets this to false.
11801                  */
11802                 crtc->cpu_fifo_underrun_disabled = true;
11803                 crtc->pch_fifo_underrun_disabled = true;
11804         }
11805 }
11806
11807 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11808 {
11809         struct intel_connector *connector;
11810         struct drm_device *dev = encoder->base.dev;
11811
11812         /* We need to check both for a crtc link (meaning that the
11813          * encoder is active and trying to read from a pipe) and the
11814          * pipe itself being active. */
11815         bool has_active_crtc = encoder->base.crtc &&
11816                 to_intel_crtc(encoder->base.crtc)->active;
11817
11818         if (encoder->connectors_active && !has_active_crtc) {
11819                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11820                               encoder->base.base.id,
11821                               drm_get_encoder_name(&encoder->base));
11822
11823                 /* Connector is active, but has no active pipe. This is
11824                  * fallout from our resume register restoring. Disable
11825                  * the encoder manually again. */
11826                 if (encoder->base.crtc) {
11827                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11828                                       encoder->base.base.id,
11829                                       drm_get_encoder_name(&encoder->base));
11830                         encoder->disable(encoder);
11831                 }
11832
11833                 /* Inconsistent output/port/pipe state happens presumably due to
11834                  * a bug in one of the get_hw_state functions. Or someplace else
11835                  * in our code, like the register restore mess on resume. Clamp
11836                  * things to off as a safer default. */
11837                 list_for_each_entry(connector,
11838                                     &dev->mode_config.connector_list,
11839                                     base.head) {
11840                         if (connector->encoder != encoder)
11841                                 continue;
11842
11843                         intel_connector_break_all_links(connector);
11844                 }
11845         }
11846         /* Enabled encoders without active connectors will be fixed in
11847          * the crtc fixup. */
11848 }
11849
11850 void i915_redisable_vga_power_on(struct drm_device *dev)
11851 {
11852         struct drm_i915_private *dev_priv = dev->dev_private;
11853         u32 vga_reg = i915_vgacntrl_reg(dev);
11854
11855         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11856                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11857                 i915_disable_vga(dev);
11858         }
11859 }
11860
11861 void i915_redisable_vga(struct drm_device *dev)
11862 {
11863         struct drm_i915_private *dev_priv = dev->dev_private;
11864
11865         /* This function can be called both from intel_modeset_setup_hw_state or
11866          * at a very early point in our resume sequence, where the power well
11867          * structures are not yet restored. Since this function is at a very
11868          * paranoid "someone might have enabled VGA while we were not looking"
11869          * level, just check if the power well is enabled instead of trying to
11870          * follow the "don't touch the power well if we don't need it" policy
11871          * the rest of the driver uses. */
11872         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11873                 return;
11874
11875         i915_redisable_vga_power_on(dev);
11876 }
11877
11878 static bool primary_get_hw_state(struct intel_crtc *crtc)
11879 {
11880         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11881
11882         if (!crtc->active)
11883                 return false;
11884
11885         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11886 }
11887
11888 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11889 {
11890         struct drm_i915_private *dev_priv = dev->dev_private;
11891         enum pipe pipe;
11892         struct intel_crtc *crtc;
11893         struct intel_encoder *encoder;
11894         struct intel_connector *connector;
11895         int i;
11896
11897         for_each_intel_crtc(dev, crtc) {
11898                 memset(&crtc->config, 0, sizeof(crtc->config));
11899
11900                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11901
11902                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11903                                                                  &crtc->config);
11904
11905                 crtc->base.enabled = crtc->active;
11906                 crtc->primary_enabled = primary_get_hw_state(crtc);
11907
11908                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11909                               crtc->base.base.id,
11910                               crtc->active ? "enabled" : "disabled");
11911         }
11912
11913         /* FIXME: Smash this into the new shared dpll infrastructure. */
11914         if (HAS_DDI(dev))
11915                 intel_ddi_setup_hw_pll_state(dev);
11916
11917         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11918                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11919
11920                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11921                 pll->active = 0;
11922                 for_each_intel_crtc(dev, crtc) {
11923                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11924                                 pll->active++;
11925                 }
11926                 pll->refcount = pll->active;
11927
11928                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11929                               pll->name, pll->refcount, pll->on);
11930         }
11931
11932         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11933                             base.head) {
11934                 pipe = 0;
11935
11936                 if (encoder->get_hw_state(encoder, &pipe)) {
11937                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11938                         encoder->base.crtc = &crtc->base;
11939                         encoder->get_config(encoder, &crtc->config);
11940                 } else {
11941                         encoder->base.crtc = NULL;
11942                 }
11943
11944                 encoder->connectors_active = false;
11945                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11946                               encoder->base.base.id,
11947                               drm_get_encoder_name(&encoder->base),
11948                               encoder->base.crtc ? "enabled" : "disabled",
11949                               pipe_name(pipe));
11950         }
11951
11952         list_for_each_entry(connector, &dev->mode_config.connector_list,
11953                             base.head) {
11954                 if (connector->get_hw_state(connector)) {
11955                         connector->base.dpms = DRM_MODE_DPMS_ON;
11956                         connector->encoder->connectors_active = true;
11957                         connector->base.encoder = &connector->encoder->base;
11958                 } else {
11959                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11960                         connector->base.encoder = NULL;
11961                 }
11962                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11963                               connector->base.base.id,
11964                               drm_get_connector_name(&connector->base),
11965                               connector->base.encoder ? "enabled" : "disabled");
11966         }
11967 }
11968
11969 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11970  * and i915 state tracking structures. */
11971 void intel_modeset_setup_hw_state(struct drm_device *dev,
11972                                   bool force_restore)
11973 {
11974         struct drm_i915_private *dev_priv = dev->dev_private;
11975         enum pipe pipe;
11976         struct intel_crtc *crtc;
11977         struct intel_encoder *encoder;
11978         int i;
11979
11980         intel_modeset_readout_hw_state(dev);
11981
11982         /*
11983          * Now that we have the config, copy it to each CRTC struct
11984          * Note that this could go away if we move to using crtc_config
11985          * checking everywhere.
11986          */
11987         for_each_intel_crtc(dev, crtc) {
11988                 if (crtc->active && i915.fastboot) {
11989                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11990                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11991                                       crtc->base.base.id);
11992                         drm_mode_debug_printmodeline(&crtc->base.mode);
11993                 }
11994         }
11995
11996         /* HW state is read out, now we need to sanitize this mess. */
11997         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11998                             base.head) {
11999                 intel_sanitize_encoder(encoder);
12000         }
12001
12002         for_each_pipe(pipe) {
12003                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12004                 intel_sanitize_crtc(crtc);
12005                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12006         }
12007
12008         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12009                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12010
12011                 if (!pll->on || pll->active)
12012                         continue;
12013
12014                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12015
12016                 pll->disable(dev_priv, pll);
12017                 pll->on = false;
12018         }
12019
12020         if (HAS_PCH_SPLIT(dev))
12021                 ilk_wm_get_hw_state(dev);
12022
12023         if (force_restore) {
12024                 i915_redisable_vga(dev);
12025
12026                 /*
12027                  * We need to use raw interfaces for restoring state to avoid
12028                  * checking (bogus) intermediate states.
12029                  */
12030                 for_each_pipe(pipe) {
12031                         struct drm_crtc *crtc =
12032                                 dev_priv->pipe_to_crtc_mapping[pipe];
12033
12034                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12035                                          crtc->primary->fb);
12036                 }
12037         } else {
12038                 intel_modeset_update_staged_output_state(dev);
12039         }
12040
12041         intel_modeset_check_state(dev);
12042 }
12043
12044 void intel_modeset_gem_init(struct drm_device *dev)
12045 {
12046         struct drm_crtc *c;
12047         struct intel_framebuffer *fb;
12048
12049         mutex_lock(&dev->struct_mutex);
12050         intel_init_gt_powersave(dev);
12051         mutex_unlock(&dev->struct_mutex);
12052
12053         intel_modeset_init_hw(dev);
12054
12055         intel_setup_overlay(dev);
12056
12057         /*
12058          * Make sure any fbs we allocated at startup are properly
12059          * pinned & fenced.  When we do the allocation it's too early
12060          * for this.
12061          */
12062         mutex_lock(&dev->struct_mutex);
12063         for_each_crtc(dev, c) {
12064                 if (!c->primary->fb)
12065                         continue;
12066
12067                 fb = to_intel_framebuffer(c->primary->fb);
12068                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12069                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12070                                   to_intel_crtc(c)->pipe);
12071                         drm_framebuffer_unreference(c->primary->fb);
12072                         c->primary->fb = NULL;
12073                 }
12074         }
12075         mutex_unlock(&dev->struct_mutex);
12076 }
12077
12078 void intel_connector_unregister(struct intel_connector *intel_connector)
12079 {
12080         struct drm_connector *connector = &intel_connector->base;
12081
12082         intel_panel_destroy_backlight(connector);
12083         drm_sysfs_connector_remove(connector);
12084 }
12085
12086 void intel_modeset_cleanup(struct drm_device *dev)
12087 {
12088         struct drm_i915_private *dev_priv = dev->dev_private;
12089         struct drm_crtc *crtc;
12090         struct drm_connector *connector;
12091
12092         /*
12093          * Interrupts and polling as the first thing to avoid creating havoc.
12094          * Too much stuff here (turning of rps, connectors, ...) would
12095          * experience fancy races otherwise.
12096          */
12097         drm_irq_uninstall(dev);
12098         cancel_work_sync(&dev_priv->hotplug_work);
12099         /*
12100          * Due to the hpd irq storm handling the hotplug work can re-arm the
12101          * poll handlers. Hence disable polling after hpd handling is shut down.
12102          */
12103         drm_kms_helper_poll_fini(dev);
12104
12105         mutex_lock(&dev->struct_mutex);
12106
12107         intel_unregister_dsm_handler();
12108
12109         for_each_crtc(dev, crtc) {
12110                 /* Skip inactive CRTCs */
12111                 if (!crtc->primary->fb)
12112                         continue;
12113
12114                 intel_increase_pllclock(crtc);
12115         }
12116
12117         intel_disable_fbc(dev);
12118
12119         intel_disable_gt_powersave(dev);
12120
12121         ironlake_teardown_rc6(dev);
12122
12123         mutex_unlock(&dev->struct_mutex);
12124
12125         /* flush any delayed tasks or pending work */
12126         flush_scheduled_work();
12127
12128         /* destroy the backlight and sysfs files before encoders/connectors */
12129         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12130                 struct intel_connector *intel_connector;
12131
12132                 intel_connector = to_intel_connector(connector);
12133                 intel_connector->unregister(intel_connector);
12134         }
12135
12136         drm_mode_config_cleanup(dev);
12137
12138         intel_cleanup_overlay(dev);
12139
12140         mutex_lock(&dev->struct_mutex);
12141         intel_cleanup_gt_powersave(dev);
12142         mutex_unlock(&dev->struct_mutex);
12143 }
12144
12145 /*
12146  * Return which encoder is currently attached for connector.
12147  */
12148 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12149 {
12150         return &intel_attached_encoder(connector)->base;
12151 }
12152
12153 void intel_connector_attach_encoder(struct intel_connector *connector,
12154                                     struct intel_encoder *encoder)
12155 {
12156         connector->encoder = encoder;
12157         drm_mode_connector_attach_encoder(&connector->base,
12158                                           &encoder->base);
12159 }
12160
12161 /*
12162  * set vga decode state - true == enable VGA decode
12163  */
12164 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12165 {
12166         struct drm_i915_private *dev_priv = dev->dev_private;
12167         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12168         u16 gmch_ctrl;
12169
12170         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12171                 DRM_ERROR("failed to read control word\n");
12172                 return -EIO;
12173         }
12174
12175         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12176                 return 0;
12177
12178         if (state)
12179                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12180         else
12181                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12182
12183         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12184                 DRM_ERROR("failed to write control word\n");
12185                 return -EIO;
12186         }
12187
12188         return 0;
12189 }
12190
12191 struct intel_display_error_state {
12192
12193         u32 power_well_driver;
12194
12195         int num_transcoders;
12196
12197         struct intel_cursor_error_state {
12198                 u32 control;
12199                 u32 position;
12200                 u32 base;
12201                 u32 size;
12202         } cursor[I915_MAX_PIPES];
12203
12204         struct intel_pipe_error_state {
12205                 bool power_domain_on;
12206                 u32 source;
12207                 u32 stat;
12208         } pipe[I915_MAX_PIPES];
12209
12210         struct intel_plane_error_state {
12211                 u32 control;
12212                 u32 stride;
12213                 u32 size;
12214                 u32 pos;
12215                 u32 addr;
12216                 u32 surface;
12217                 u32 tile_offset;
12218         } plane[I915_MAX_PIPES];
12219
12220         struct intel_transcoder_error_state {
12221                 bool power_domain_on;
12222                 enum transcoder cpu_transcoder;
12223
12224                 u32 conf;
12225
12226                 u32 htotal;
12227                 u32 hblank;
12228                 u32 hsync;
12229                 u32 vtotal;
12230                 u32 vblank;
12231                 u32 vsync;
12232         } transcoder[4];
12233 };
12234
12235 struct intel_display_error_state *
12236 intel_display_capture_error_state(struct drm_device *dev)
12237 {
12238         struct drm_i915_private *dev_priv = dev->dev_private;
12239         struct intel_display_error_state *error;
12240         int transcoders[] = {
12241                 TRANSCODER_A,
12242                 TRANSCODER_B,
12243                 TRANSCODER_C,
12244                 TRANSCODER_EDP,
12245         };
12246         int i;
12247
12248         if (INTEL_INFO(dev)->num_pipes == 0)
12249                 return NULL;
12250
12251         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12252         if (error == NULL)
12253                 return NULL;
12254
12255         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12256                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12257
12258         for_each_pipe(i) {
12259                 error->pipe[i].power_domain_on =
12260                         intel_display_power_enabled_sw(dev_priv,
12261                                                        POWER_DOMAIN_PIPE(i));
12262                 if (!error->pipe[i].power_domain_on)
12263                         continue;
12264
12265                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12266                         error->cursor[i].control = I915_READ(CURCNTR(i));
12267                         error->cursor[i].position = I915_READ(CURPOS(i));
12268                         error->cursor[i].base = I915_READ(CURBASE(i));
12269                 } else {
12270                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12271                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12272                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12273                 }
12274
12275                 error->plane[i].control = I915_READ(DSPCNTR(i));
12276                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12277                 if (INTEL_INFO(dev)->gen <= 3) {
12278                         error->plane[i].size = I915_READ(DSPSIZE(i));
12279                         error->plane[i].pos = I915_READ(DSPPOS(i));
12280                 }
12281                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12282                         error->plane[i].addr = I915_READ(DSPADDR(i));
12283                 if (INTEL_INFO(dev)->gen >= 4) {
12284                         error->plane[i].surface = I915_READ(DSPSURF(i));
12285                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12286                 }
12287
12288                 error->pipe[i].source = I915_READ(PIPESRC(i));
12289
12290                 if (!HAS_PCH_SPLIT(dev))
12291                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12292         }
12293
12294         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12295         if (HAS_DDI(dev_priv->dev))
12296                 error->num_transcoders++; /* Account for eDP. */
12297
12298         for (i = 0; i < error->num_transcoders; i++) {
12299                 enum transcoder cpu_transcoder = transcoders[i];
12300
12301                 error->transcoder[i].power_domain_on =
12302                         intel_display_power_enabled_sw(dev_priv,
12303                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12304                 if (!error->transcoder[i].power_domain_on)
12305                         continue;
12306
12307                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12308
12309                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12310                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12311                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12312                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12313                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12314                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12315                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12316         }
12317
12318         return error;
12319 }
12320
12321 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12322
12323 void
12324 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12325                                 struct drm_device *dev,
12326                                 struct intel_display_error_state *error)
12327 {
12328         int i;
12329
12330         if (!error)
12331                 return;
12332
12333         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12334         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12335                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12336                            error->power_well_driver);
12337         for_each_pipe(i) {
12338                 err_printf(m, "Pipe [%d]:\n", i);
12339                 err_printf(m, "  Power: %s\n",
12340                            error->pipe[i].power_domain_on ? "on" : "off");
12341                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12342                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12343
12344                 err_printf(m, "Plane [%d]:\n", i);
12345                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12346                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12347                 if (INTEL_INFO(dev)->gen <= 3) {
12348                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12349                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12350                 }
12351                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12352                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12353                 if (INTEL_INFO(dev)->gen >= 4) {
12354                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12355                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12356                 }
12357
12358                 err_printf(m, "Cursor [%d]:\n", i);
12359                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12360                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12361                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12362         }
12363
12364         for (i = 0; i < error->num_transcoders; i++) {
12365                 err_printf(m, "CPU transcoder: %c\n",
12366                            transcoder_name(error->transcoder[i].cpu_transcoder));
12367                 err_printf(m, "  Power: %s\n",
12368                            error->transcoder[i].power_domain_on ? "on" : "off");
12369                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12370                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12371                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12372                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12373                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12374                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12375                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12376         }
12377 }