drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc);
  98 static void chv_prepare_pll(struct intel_crtc *crtc);
  99
 100 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 101 {
 102         if (!connector->mst_port)
 103                 return connector->encoder;
 104         else
 105                 return &connector->mst_port->mst_encoders[pipe]->base;
 106 }
 107
 108 typedef struct {
 109         int     min, max;
 110 } intel_range_t;
 111
 112 typedef struct {
 113         int     dot_limit;
 114         int     p2_slow, p2_fast;
 115 } intel_p2_t;
 116
 117 typedef struct intel_limit intel_limit_t;
 118 struct intel_limit {
 119         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 120         intel_p2_t          p2;
 121 };
 122
 123 int
 124 intel_pch_rawclk(struct drm_device *dev)
 125 {
 126         struct drm_i915_private *dev_priv = dev->dev_private;
 127
 128         WARN_ON(!HAS_PCH_SPLIT(dev));
 129
 130         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 131 }
 132
 133 static inline u32 /* units of 100MHz */
 134 intel_fdi_link_freq(struct drm_device *dev)
 135 {
 136         if (IS_GEN5(dev)) {
 137                 struct drm_i915_private *dev_priv = dev->dev_private;
 138                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 139         } else
 140                 return 27;
 141 }
 142
 143 static const intel_limit_t intel_limits_i8xx_dac = {
 144         .dot = { .min = 25000, .max = 350000 },
 145         .vco = { .min = 908000, .max = 1512000 },
 146         .n = { .min = 2, .max = 16 },
 147         .m = { .min = 96, .max = 140 },
 148         .m1 = { .min = 18, .max = 26 },
 149         .m2 = { .min = 6, .max = 16 },
 150         .p = { .min = 4, .max = 128 },
 151         .p1 = { .min = 2, .max = 33 },
 152         .p2 = { .dot_limit = 165000,
 153                 .p2_slow = 4, .p2_fast = 2 },
 154 };
 155
 156 static const intel_limit_t intel_limits_i8xx_dvo = {
 157         .dot = { .min = 25000, .max = 350000 },
 158         .vco = { .min = 908000, .max = 1512000 },
 159         .n = { .min = 2, .max = 16 },
 160         .m = { .min = 96, .max = 140 },
 161         .m1 = { .min = 18, .max = 26 },
 162         .m2 = { .min = 6, .max = 16 },
 163         .p = { .min = 4, .max = 128 },
 164         .p1 = { .min = 2, .max = 33 },
 165         .p2 = { .dot_limit = 165000,
 166                 .p2_slow = 4, .p2_fast = 4 },
 167 };
 168
 169 static const intel_limit_t intel_limits_i8xx_lvds = {
 170         .dot = { .min = 25000, .max = 350000 },
 171         .vco = { .min = 908000, .max = 1512000 },
 172         .n = { .min = 2, .max = 16 },
 173         .m = { .min = 96, .max = 140 },
 174         .m1 = { .min = 18, .max = 26 },
 175         .m2 = { .min = 6, .max = 16 },
 176         .p = { .min = 4, .max = 128 },
 177         .p1 = { .min = 1, .max = 6 },
 178         .p2 = { .dot_limit = 165000,
 179                 .p2_slow = 14, .p2_fast = 7 },
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_sdvo = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 5, .max = 80 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 200000,
 192                 .p2_slow = 10, .p2_fast = 5 },
 193 };
 194
 195 static const intel_limit_t intel_limits_i9xx_lvds = {
 196         .dot = { .min = 20000, .max = 400000 },
 197         .vco = { .min = 1400000, .max = 2800000 },
 198         .n = { .min = 1, .max = 6 },
 199         .m = { .min = 70, .max = 120 },
 200         .m1 = { .min = 8, .max = 18 },
 201         .m2 = { .min = 3, .max = 7 },
 202         .p = { .min = 7, .max = 98 },
 203         .p1 = { .min = 1, .max = 8 },
 204         .p2 = { .dot_limit = 112000,
 205                 .p2_slow = 14, .p2_fast = 7 },
 206 };
 207
 208
 209 static const intel_limit_t intel_limits_g4x_sdvo = {
 210         .dot = { .min = 25000, .max = 270000 },
 211         .vco = { .min = 1750000, .max = 3500000},
 212         .n = { .min = 1, .max = 4 },
 213         .m = { .min = 104, .max = 138 },
 214         .m1 = { .min = 17, .max = 23 },
 215         .m2 = { .min = 5, .max = 11 },
 216         .p = { .min = 10, .max = 30 },
 217         .p1 = { .min = 1, .max = 3},
 218         .p2 = { .dot_limit = 270000,
 219                 .p2_slow = 10,
 220                 .p2_fast = 10
 221         },
 222 };
 223
 224 static const intel_limit_t intel_limits_g4x_hdmi = {
 225         .dot = { .min = 22000, .max = 400000 },
 226         .vco = { .min = 1750000, .max = 3500000},
 227         .n = { .min = 1, .max = 4 },
 228         .m = { .min = 104, .max = 138 },
 229         .m1 = { .min = 16, .max = 23 },
 230         .m2 = { .min = 5, .max = 11 },
 231         .p = { .min = 5, .max = 80 },
 232         .p1 = { .min = 1, .max = 8},
 233         .p2 = { .dot_limit = 165000,
 234                 .p2_slow = 10, .p2_fast = 5 },
 235 };
 236
 237 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 238         .dot = { .min = 20000, .max = 115000 },
 239         .vco = { .min = 1750000, .max = 3500000 },
 240         .n = { .min = 1, .max = 3 },
 241         .m = { .min = 104, .max = 138 },
 242         .m1 = { .min = 17, .max = 23 },
 243         .m2 = { .min = 5, .max = 11 },
 244         .p = { .min = 28, .max = 112 },
 245         .p1 = { .min = 2, .max = 8 },
 246         .p2 = { .dot_limit = 0,
 247                 .p2_slow = 14, .p2_fast = 14
 248         },
 249 };
 250
 251 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 252         .dot = { .min = 80000, .max = 224000 },
 253         .vco = { .min = 1750000, .max = 3500000 },
 254         .n = { .min = 1, .max = 3 },
 255         .m = { .min = 104, .max = 138 },
 256         .m1 = { .min = 17, .max = 23 },
 257         .m2 = { .min = 5, .max = 11 },
 258         .p = { .min = 14, .max = 42 },
 259         .p1 = { .min = 2, .max = 6 },
 260         .p2 = { .dot_limit = 0,
 261                 .p2_slow = 7, .p2_fast = 7
 262         },
 263 };
 264
 265 static const intel_limit_t intel_limits_pineview_sdvo = {
 266         .dot = { .min = 20000, .max = 400000},
 267         .vco = { .min = 1700000, .max = 3500000 },
 268         /* Pineview's Ncounter is a ring counter */
 269         .n = { .min = 3, .max = 6 },
 270         .m = { .min = 2, .max = 256 },
 271         /* Pineview only has one combined m divider, which we treat as m2. */
 272         .m1 = { .min = 0, .max = 0 },
 273         .m2 = { .min = 0, .max = 254 },
 274         .p = { .min = 5, .max = 80 },
 275         .p1 = { .min = 1, .max = 8 },
 276         .p2 = { .dot_limit = 200000,
 277                 .p2_slow = 10, .p2_fast = 5 },
 278 };
 279
 280 static const intel_limit_t intel_limits_pineview_lvds = {
 281         .dot = { .min = 20000, .max = 400000 },
 282         .vco = { .min = 1700000, .max = 3500000 },
 283         .n = { .min = 3, .max = 6 },
 284         .m = { .min = 2, .max = 256 },
 285         .m1 = { .min = 0, .max = 0 },
 286         .m2 = { .min = 0, .max = 254 },
 287         .p = { .min = 7, .max = 112 },
 288         .p1 = { .min = 1, .max = 8 },
 289         .p2 = { .dot_limit = 112000,
 290                 .p2_slow = 14, .p2_fast = 14 },
 291 };
 292
 293 /* Ironlake / Sandybridge
 294  *
 295  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 296  * the range value for them is (actual_value - 2).
 297  */
 298 static const intel_limit_t intel_limits_ironlake_dac = {
 299         .dot = { .min = 25000, .max = 350000 },
 300         .vco = { .min = 1760000, .max = 3510000 },
 301         .n = { .min = 1, .max = 5 },
 302         .m = { .min = 79, .max = 127 },
 303         .m1 = { .min = 12, .max = 22 },
 304         .m2 = { .min = 5, .max = 9 },
 305         .p = { .min = 5, .max = 80 },
 306         .p1 = { .min = 1, .max = 8 },
 307         .p2 = { .dot_limit = 225000,
 308                 .p2_slow = 10, .p2_fast = 5 },
 309 };
 310
 311 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 312         .dot = { .min = 25000, .max = 350000 },
 313         .vco = { .min = 1760000, .max = 3510000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 79, .max = 118 },
 316         .m1 = { .min = 12, .max = 22 },
 317         .m2 = { .min = 5, .max = 9 },
 318         .p = { .min = 28, .max = 112 },
 319         .p1 = { .min = 2, .max = 8 },
 320         .p2 = { .dot_limit = 225000,
 321                 .p2_slow = 14, .p2_fast = 14 },
 322 };
 323
 324 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 325         .dot = { .min = 25000, .max = 350000 },
 326         .vco = { .min = 1760000, .max = 3510000 },
 327         .n = { .min = 1, .max = 3 },
 328         .m = { .min = 79, .max = 127 },
 329         .m1 = { .min = 12, .max = 22 },
 330         .m2 = { .min = 5, .max = 9 },
 331         .p = { .min = 14, .max = 56 },
 332         .p1 = { .min = 2, .max = 8 },
 333         .p2 = { .dot_limit = 225000,
 334                 .p2_slow = 7, .p2_fast = 7 },
 335 };
 336
 337 /* LVDS 100mhz refclk limits. */
 338 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 339         .dot = { .min = 25000, .max = 350000 },
 340         .vco = { .min = 1760000, .max = 3510000 },
 341         .n = { .min = 1, .max = 2 },
 342         .m = { .min = 79, .max = 126 },
 343         .m1 = { .min = 12, .max = 22 },
 344         .m2 = { .min = 5, .max = 9 },
 345         .p = { .min = 28, .max = 112 },
 346         .p1 = { .min = 2, .max = 8 },
 347         .p2 = { .dot_limit = 225000,
 348                 .p2_slow = 14, .p2_fast = 14 },
 349 };
 350
 351 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 352         .dot = { .min = 25000, .max = 350000 },
 353         .vco = { .min = 1760000, .max = 3510000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 79, .max = 126 },
 356         .m1 = { .min = 12, .max = 22 },
 357         .m2 = { .min = 5, .max = 9 },
 358         .p = { .min = 14, .max = 42 },
 359         .p1 = { .min = 2, .max = 6 },
 360         .p2 = { .dot_limit = 225000,
 361                 .p2_slow = 7, .p2_fast = 7 },
 362 };
 363
 364 static const intel_limit_t intel_limits_vlv = {
 365          /*
 366           * These are the data rate limits (measured in fast clocks)
 367           * since those are the strictest limits we have. The fast
 368           * clock and actual rate limits are more relaxed, so checking
 369           * them would make no difference.
 370           */
 371         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m1 = { .min = 2, .max = 3 },
 375         .m2 = { .min = 11, .max = 156 },
 376         .p1 = { .min = 2, .max = 3 },
 377         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 378 };
 379
 380 static const intel_limit_t intel_limits_chv = {
 381         /*
 382          * These are the data rate limits (measured in fast clocks)
 383          * since those are the strictest limits we have.  The fast
 384          * clock and actual rate limits are more relaxed, so checking
 385          * them would make no difference.
 386          */
 387         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 388         .vco = { .min = 4860000, .max = 6700000 },
 389         .n = { .min = 1, .max = 1 },
 390         .m1 = { .min = 2, .max = 2 },
 391         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 392         .p1 = { .min = 2, .max = 4 },
 393         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 394 };
 395
 396 static void vlv_clock(int refclk, intel_clock_t *clock)
 397 {
 398         clock->m = clock->m1 * clock->m2;
 399         clock->p = clock->p1 * clock->p2;
 400         if (WARN_ON(clock->n == 0 || clock->p == 0))
 401                 return;
 402         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 403         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 404 }
 405
 406 /**
 407  * Returns whether any output on the specified pipe is of the specified type
 408  */
 409 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 410 {
 411         struct drm_device *dev = crtc->base.dev;
 412         struct intel_encoder *encoder;
 413
 414         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 415                 if (encoder->type == type)
 416                         return true;
 417
 418         return false;
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->base.dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->base.dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->base.dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_CHERRYVIEW(dev)) {
 481                 limit = &intel_limits_chv;
 482         } else if (IS_VALLEYVIEW(dev)) {
 483                 limit = &intel_limits_vlv;
 484         } else if (!IS_GEN2(dev)) {
 485                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 486                         limit = &intel_limits_i9xx_lvds;
 487                 else
 488                         limit = &intel_limits_i9xx_sdvo;
 489         } else {
 490                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 491                         limit = &intel_limits_i8xx_lvds;
 492                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 493                         limit = &intel_limits_i8xx_dvo;
 494                 else
 495                         limit = &intel_limits_i8xx_dac;
 496         }
 497         return limit;
 498 }
 499
 500 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 501 static void pineview_clock(int refclk, intel_clock_t *clock)
 502 {
 503         clock->m = clock->m2 + 2;
 504         clock->p = clock->p1 * clock->p2;
 505         if (WARN_ON(clock->n == 0 || clock->p == 0))
 506                 return;
 507         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 508         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 509 }
 510
 511 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 512 {
 513         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 514 }
 515
 516 static void i9xx_clock(int refclk, intel_clock_t *clock)
 517 {
 518         clock->m = i9xx_dpll_compute_m(clock);
 519         clock->p = clock->p1 * clock->p2;
 520         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 521                 return;
 522         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 523         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 524 }
 525
 526 static void chv_clock(int refclk, intel_clock_t *clock)
 527 {
 528         clock->m = clock->m1 * clock->m2;
 529         clock->p = clock->p1 * clock->p2;
 530         if (WARN_ON(clock->n == 0 || clock->p == 0))
 531                 return;
 532         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 533                         clock->n << 22);
 534         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_device *dev,
 544                                const intel_limit_t *limit,
 545                                const intel_clock_t *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 557                 if (clock->m1 <= clock->m2)
 558                         INTELPllInvalid("m1 <= m2\n");
 559
 560         if (!IS_VALLEYVIEW(dev)) {
 561                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 562                         INTELPllInvalid("p out of range\n");
 563                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 564                         INTELPllInvalid("m out of range\n");
 565         }
 566
 567         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 568                 INTELPllInvalid("vco out of range\n");
 569         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 570          * connector, etc., rather than just a single range.
 571          */
 572         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 573                 INTELPllInvalid("dot out of range\n");
 574
 575         return true;
 576 }
 577
 578 static bool
 579 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 580                     int target, int refclk, intel_clock_t *match_clock,
 581                     intel_clock_t *best_clock)
 582 {
 583         struct drm_device *dev = crtc->base.dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         if (clock.m2 >= clock.m1)
 611                                 break;
 612                         for (clock.n = limit->n.min;
 613                              clock.n <= limit->n.max; clock.n++) {
 614                                 for (clock.p1 = limit->p1.min;
 615                                         clock.p1 <= limit->p1.max; clock.p1++) {
 616                                         int this_err;
 617
 618                                         i9xx_clock(refclk, &clock);
 619                                         if (!intel_PLL_is_valid(dev, limit,
 620                                                                 &clock))
 621                                                 continue;
 622                                         if (match_clock &&
 623                                             clock.p != match_clock->p)
 624                                                 continue;
 625
 626                                         this_err = abs(clock.dot - target);
 627                                         if (this_err < err) {
 628                                                 *best_clock = clock;
 629                                                 err = this_err;
 630                                         }
 631                                 }
 632                         }
 633                 }
 634         }
 635
 636         return (err != target);
 637 }
 638
 639 static bool
 640 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 641                    int target, int refclk, intel_clock_t *match_clock,
 642                    intel_clock_t *best_clock)
 643 {
 644         struct drm_device *dev = crtc->base.dev;
 645         intel_clock_t clock;
 646         int err = target;
 647
 648         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 649                 /*
 650                  * For LVDS just rely on its current settings for dual-channel.
 651                  * We haven't figured out how to reliably set up different
 652                  * single/dual channel state, if we even can.
 653                  */
 654                 if (intel_is_dual_link_lvds(dev))
 655                         clock.p2 = limit->p2.p2_fast;
 656                 else
 657                         clock.p2 = limit->p2.p2_slow;
 658         } else {
 659                 if (target < limit->p2.dot_limit)
 660                         clock.p2 = limit->p2.p2_slow;
 661                 else
 662                         clock.p2 = limit->p2.p2_fast;
 663         }
 664
 665         memset(best_clock, 0, sizeof(*best_clock));
 666
 667         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 668              clock.m1++) {
 669                 for (clock.m2 = limit->m2.min;
 670                      clock.m2 <= limit->m2.max; clock.m2++) {
 671                         for (clock.n = limit->n.min;
 672                              clock.n <= limit->n.max; clock.n++) {
 673                                 for (clock.p1 = limit->p1.min;
 674                                         clock.p1 <= limit->p1.max; clock.p1++) {
 675                                         int this_err;
 676
 677                                         pineview_clock(refclk, &clock);
 678                                         if (!intel_PLL_is_valid(dev, limit,
 679                                                                 &clock))
 680                                                 continue;
 681                                         if (match_clock &&
 682                                             clock.p != match_clock->p)
 683                                                 continue;
 684
 685                                         this_err = abs(clock.dot - target);
 686                                         if (this_err < err) {
 687                                                 *best_clock = clock;
 688                                                 err = this_err;
 689                                         }
 690                                 }
 691                         }
 692                 }
 693         }
 694
 695         return (err != target);
 696 }
 697
 698 static bool
 699 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 700                    int target, int refclk, intel_clock_t *match_clock,
 701                    intel_clock_t *best_clock)
 702 {
 703         struct drm_device *dev = crtc->base.dev;
 704         intel_clock_t clock;
 705         int max_n;
 706         bool found;
 707         /* approximately equals target * 0.00585 */
 708         int err_most = (target >> 8) + (target >> 9);
 709         found = false;
 710
 711         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 712                 if (intel_is_dual_link_lvds(dev))
 713                         clock.p2 = limit->p2.p2_fast;
 714                 else
 715                         clock.p2 = limit->p2.p2_slow;
 716         } else {
 717                 if (target < limit->p2.dot_limit)
 718                         clock.p2 = limit->p2.p2_slow;
 719                 else
 720                         clock.p2 = limit->p2.p2_fast;
 721         }
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724         max_n = limit->n.max;
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 /* based on hardware requirement, prefere larger m1,m2 */
 728                 for (clock.m1 = limit->m1.max;
 729                      clock.m1 >= limit->m1.min; clock.m1--) {
 730                         for (clock.m2 = limit->m2.max;
 731                              clock.m2 >= limit->m2.min; clock.m2--) {
 732                                 for (clock.p1 = limit->p1.max;
 733                                      clock.p1 >= limit->p1.min; clock.p1--) {
 734                                         int this_err;
 735
 736                                         i9xx_clock(refclk, &clock);
 737                                         if (!intel_PLL_is_valid(dev, limit,
 738                                                                 &clock))
 739                                                 continue;
 740
 741                                         this_err = abs(clock.dot - target);
 742                                         if (this_err < err_most) {
 743                                                 *best_clock = clock;
 744                                                 err_most = this_err;
 745                                                 max_n = clock.n;
 746                                                 found = true;
 747                                         }
 748                                 }
 749                         }
 750                 }
 751         }
 752         return found;
 753 }
 754
 755 static bool
 756 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 757                    int target, int refclk, intel_clock_t *match_clock,
 758                    intel_clock_t *best_clock)
 759 {
 760         struct drm_device *dev = crtc->base.dev;
 761         intel_clock_t clock;
 762         unsigned int bestppm = 1000000;
 763         /* min update 19.2 MHz */
 764         int max_n = min(limit->n.max, refclk / 19200);
 765         bool found = false;
 766
 767         target *= 5; /* fast clock */
 768
 769         memset(best_clock, 0, sizeof(*best_clock));
 770
 771         /* based on hardware requirement, prefer smaller n to precision */
 772         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 773                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 774                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 775                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 776                                 clock.p = clock.p1 * clock.p2;
 777                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 778                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 779                                         unsigned int ppm, diff;
 780
 781                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 782                                                                      refclk * clock.m1);
 783
 784                                         vlv_clock(refclk, &clock);
 785
 786                                         if (!intel_PLL_is_valid(dev, limit,
 787                                                                 &clock))
 788                                                 continue;
 789
 790                                         diff = abs(clock.dot - target);
 791                                         ppm = div_u64(1000000ULL * diff, target);
 792
 793                                         if (ppm < 100 && clock.p > best_clock->p) {
 794                                                 bestppm = 0;
 795                                                 *best_clock = clock;
 796                                                 found = true;
 797                                         }
 798
 799                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 800                                                 bestppm = ppm;
 801                                                 *best_clock = clock;
 802                                                 found = true;
 803                                         }
 804                                 }
 805                         }
 806                 }
 807         }
 808
 809         return found;
 810 }
 811
 812 static bool
 813 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 814                    int target, int refclk, intel_clock_t *match_clock,
 815                    intel_clock_t *best_clock)
 816 {
 817         struct drm_device *dev = crtc->base.dev;
 818         intel_clock_t clock;
 819         uint64_t m2;
 820         int found = false;
 821
 822         memset(best_clock, 0, sizeof(*best_clock));
 823
 824         /*
 825          * Based on hardware doc, the n always set to 1, and m1 always
 826          * set to 2.  If requires to support 200Mhz refclk, we need to
 827          * revisit this because n may not 1 anymore.
 828          */
 829         clock.n = 1, clock.m1 = 2;
 830         target *= 5;    /* fast clock */
 831
 832         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 833                 for (clock.p2 = limit->p2.p2_fast;
 834                                 clock.p2 >= limit->p2.p2_slow;
 835                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 836
 837                         clock.p = clock.p1 * clock.p2;
 838
 839                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 840                                         clock.n) << 22, refclk * clock.m1);
 841
 842                         if (m2 > INT_MAX/clock.m1)
 843                                 continue;
 844
 845                         clock.m2 = m2;
 846
 847                         chv_clock(refclk, &clock);
 848
 849                         if (!intel_PLL_is_valid(dev, limit, &clock))
 850                                 continue;
 851
 852                         /* based on hardware requirement, prefer bigger p
 853                          */
 854                         if (clock.p > best_clock->p) {
 855                                 *best_clock = clock;
 856                                 found = true;
 857                         }
 858                 }
 859         }
 860
 861         return found;
 862 }
 863
 864 bool intel_crtc_active(struct drm_crtc *crtc)
 865 {
 866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 867
 868         /* Be paranoid as we can arrive here with only partial
 869          * state retrieved from the hardware during setup.
 870          *
 871          * We can ditch the adjusted_mode.crtc_clock check as soon
 872          * as Haswell has gained clock readout/fastboot support.
 873          *
 874          * We can ditch the crtc->primary->fb check as soon as we can
 875          * properly reconstruct framebuffers.
 876          */
 877         return intel_crtc->active && crtc->primary->fb &&
 878                 intel_crtc->config.adjusted_mode.crtc_clock;
 879 }
 880
 881 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 882                                              enum pipe pipe)
 883 {
 884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 886
 887         return intel_crtc->config.cpu_transcoder;
 888 }
 889
 890 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 891 {
 892         struct drm_i915_private *dev_priv = dev->dev_private;
 893         u32 reg = PIPEDSL(pipe);
 894         u32 line1, line2;
 895         u32 line_mask;
 896
 897         if (IS_GEN2(dev))
 898                 line_mask = DSL_LINEMASK_GEN2;
 899         else
 900                 line_mask = DSL_LINEMASK_GEN3;
 901
 902         line1 = I915_READ(reg) & line_mask;
 903         mdelay(5);
 904         line2 = I915_READ(reg) & line_mask;
 905
 906         return line1 == line2;
 907 }
 908
 909 /*
 910  * intel_wait_for_pipe_off - wait for pipe to turn off
 911  * @crtc: crtc whose pipe to wait for
 912  *
 913  * After disabling a pipe, we can't wait for vblank in the usual way,
 914  * spinning on the vblank interrupt status bit, since we won't actually
 915  * see an interrupt when the pipe is disabled.
 916  *
 917  * On Gen4 and above:
 918  *   wait for the pipe register state bit to turn off
 919  *
 920  * Otherwise:
 921  *   wait for the display line value to settle (it usually
 922  *   ends up stopping at the start of the next frame).
 923  *
 924  */
 925 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 926 {
 927         struct drm_device *dev = crtc->base.dev;
 928         struct drm_i915_private *dev_priv = dev->dev_private;
 929         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 930         enum pipe pipe = crtc->pipe;
 931
 932         if (INTEL_INFO(dev)->gen >= 4) {
 933                 int reg = PIPECONF(cpu_transcoder);
 934
 935                 /* Wait for the Pipe State to go off */
 936                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 937                              100))
 938                         WARN(1, "pipe_off wait timed out\n");
 939         } else {
 940                 /* Wait for the display line to settle */
 941                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 942                         WARN(1, "pipe_off wait timed out\n");
 943         }
 944 }
 945
 946 /*
 947  * ibx_digital_port_connected - is the specified port connected?
 948  * @dev_priv: i915 private structure
 949  * @port: the port to test
 950  *
 951  * Returns true if @port is connected, false otherwise.
 952  */
 953 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 954                                 struct intel_digital_port *port)
 955 {
 956         u32 bit;
 957
 958         if (HAS_PCH_IBX(dev_priv->dev)) {
 959                 switch (port->port) {
 960                 case PORT_B:
 961                         bit = SDE_PORTB_HOTPLUG;
 962                         break;
 963                 case PORT_C:
 964                         bit = SDE_PORTC_HOTPLUG;
 965                         break;
 966                 case PORT_D:
 967                         bit = SDE_PORTD_HOTPLUG;
 968                         break;
 969                 default:
 970                         return true;
 971                 }
 972         } else {
 973                 switch (port->port) {
 974                 case PORT_B:
 975                         bit = SDE_PORTB_HOTPLUG_CPT;
 976                         break;
 977                 case PORT_C:
 978                         bit = SDE_PORTC_HOTPLUG_CPT;
 979                         break;
 980                 case PORT_D:
 981                         bit = SDE_PORTD_HOTPLUG_CPT;
 982                         break;
 983                 default:
 984                         return true;
 985                 }
 986         }
 987
 988         return I915_READ(SDEISR) & bit;
 989 }
 990
 991 static const char *state_string(bool enabled)
 992 {
 993         return enabled ? "on" : "off";
 994 }
 995
 996 /* Only for pre-ILK configs */
 997 void assert_pll(struct drm_i915_private *dev_priv,
 998                 enum pipe pipe, bool state)
 999 {
1000         int reg;
1001         u32 val;
1002         bool cur_state;
1003
1004         reg = DPLL(pipe);
1005         val = I915_READ(reg);
1006         cur_state = !!(val & DPLL_VCO_ENABLE);
1007         WARN(cur_state != state,
1008              "PLL state assertion failure (expected %s, current %s)\n",
1009              state_string(state), state_string(cur_state));
1010 }
1011
1012 /* XXX: the dsi pll is shared between MIPI DSI ports */
1013 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1014 {
1015         u32 val;
1016         bool cur_state;
1017
1018         mutex_lock(&dev_priv->dpio_lock);
1019         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1020         mutex_unlock(&dev_priv->dpio_lock);
1021
1022         cur_state = val & DSI_PLL_VCO_EN;
1023         WARN(cur_state != state,
1024              "DSI PLL state assertion failure (expected %s, current %s)\n",
1025              state_string(state), state_string(cur_state));
1026 }
1027 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1028 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1029
1030 struct intel_shared_dpll *
1031 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1032 {
1033         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1034
1035         if (crtc->config.shared_dpll < 0)
1036                 return NULL;
1037
1038         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1039 }
1040
1041 /* For ILK+ */
1042 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1043                         struct intel_shared_dpll *pll,
1044                         bool state)
1045 {
1046         bool cur_state;
1047         struct intel_dpll_hw_state hw_state;
1048
1049         if (WARN (!pll,
1050                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1051                 return;
1052
1053         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1054         WARN(cur_state != state,
1055              "%s assertion failure (expected %s, current %s)\n",
1056              pll->name, state_string(state), state_string(cur_state));
1057 }
1058
1059 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1060                           enum pipe pipe, bool state)
1061 {
1062         int reg;
1063         u32 val;
1064         bool cur_state;
1065         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1066                                                                       pipe);
1067
1068         if (HAS_DDI(dev_priv->dev)) {
1069                 /* DDI does not have a specific FDI_TX register */
1070                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1071                 val = I915_READ(reg);
1072                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1073         } else {
1074                 reg = FDI_TX_CTL(pipe);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080              state_string(state), state_string(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         int reg;
1089         u32 val;
1090         bool cur_state;
1091
1092         reg = FDI_RX_CTL(pipe);
1093         val = I915_READ(reg);
1094         cur_state = !!(val & FDI_RX_ENABLE);
1095         WARN(cur_state != state,
1096              "FDI RX state assertion failure (expected %s, current %s)\n",
1097              state_string(state), state_string(cur_state));
1098 }
1099 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1100 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1101
1102 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1103                                       enum pipe pipe)
1104 {
1105         int reg;
1106         u32 val;
1107
1108         /* ILK FDI PLL is always enabled */
1109         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1110                 return;
1111
1112         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1113         if (HAS_DDI(dev_priv->dev))
1114                 return;
1115
1116         reg = FDI_TX_CTL(pipe);
1117         val = I915_READ(reg);
1118         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1119 }
1120
1121 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1122                        enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127
1128         reg = FDI_RX_CTL(pipe);
1129         val = I915_READ(reg);
1130         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1131         WARN(cur_state != state,
1132              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1133              state_string(state), state_string(cur_state));
1134 }
1135
1136 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1137                            enum pipe pipe)
1138 {
1139         struct drm_device *dev = dev_priv->dev;
1140         int pp_reg;
1141         u32 val;
1142         enum pipe panel_pipe = PIPE_A;
1143         bool locked = true;
1144
1145         if (WARN_ON(HAS_DDI(dev)))
1146                 return;
1147
1148         if (HAS_PCH_SPLIT(dev)) {
1149                 u32 port_sel;
1150
1151                 pp_reg = PCH_PP_CONTROL;
1152                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1153
1154                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1155                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1156                         panel_pipe = PIPE_B;
1157                 /* XXX: else fix for eDP */
1158         } else if (IS_VALLEYVIEW(dev)) {
1159                 /* presumably write lock depends on pipe, not port select */
1160                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1161                 panel_pipe = pipe;
1162         } else {
1163                 pp_reg = PP_CONTROL;
1164                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1165                         panel_pipe = PIPE_B;
1166         }
1167
1168         val = I915_READ(pp_reg);
1169         if (!(val & PANEL_POWER_ON) ||
1170             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1171                 locked = false;
1172
1173         WARN(panel_pipe == pipe && locked,
1174              "panel assertion failure, pipe %c regs locked\n",
1175              pipe_name(pipe));
1176 }
1177
1178 static void assert_cursor(struct drm_i915_private *dev_priv,
1179                           enum pipe pipe, bool state)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         bool cur_state;
1183
1184         if (IS_845G(dev) || IS_I865G(dev))
1185                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1186         else
1187                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe quirk it must be always on */
1206         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1207             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1208                 state = true;
1209
1210         if (!intel_display_power_is_enabled(dev_priv,
1211                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1212                 cur_state = false;
1213         } else {
1214                 reg = PIPECONF(cpu_transcoder);
1215                 val = I915_READ(reg);
1216                 cur_state = !!(val & PIPECONF_ENABLE);
1217         }
1218
1219         WARN(cur_state != state,
1220              "pipe %c assertion failure (expected %s, current %s)\n",
1221              pipe_name(pipe), state_string(state), state_string(cur_state));
1222 }
1223
1224 static void assert_plane(struct drm_i915_private *dev_priv,
1225                          enum plane plane, bool state)
1226 {
1227         int reg;
1228         u32 val;
1229         bool cur_state;
1230
1231         reg = DSPCNTR(plane);
1232         val = I915_READ(reg);
1233         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1234         WARN(cur_state != state,
1235              "plane %c assertion failure (expected %s, current %s)\n",
1236              plane_name(plane), state_string(state), state_string(cur_state));
1237 }
1238
1239 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1240 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1241
1242 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1243                                    enum pipe pipe)
1244 {
1245         struct drm_device *dev = dev_priv->dev;
1246         int reg, i;
1247         u32 val;
1248         int cur_pipe;
1249
1250         /* Primary planes are fixed to pipes on gen4+ */
1251         if (INTEL_INFO(dev)->gen >= 4) {
1252                 reg = DSPCNTR(pipe);
1253                 val = I915_READ(reg);
1254                 WARN(val & DISPLAY_PLANE_ENABLE,
1255                      "plane %c assertion failure, should be disabled but not\n",
1256                      plane_name(pipe));
1257                 return;
1258         }
1259
1260         /* Need to check both planes against the pipe */
1261         for_each_pipe(dev_priv, i) {
1262                 reg = DSPCNTR(i);
1263                 val = I915_READ(reg);
1264                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265                         DISPPLANE_SEL_PIPE_SHIFT;
1266                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1267                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268                      plane_name(i), pipe_name(pipe));
1269         }
1270 }
1271
1272 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1273                                     enum pipe pipe)
1274 {
1275         struct drm_device *dev = dev_priv->dev;
1276         int reg, sprite;
1277         u32 val;
1278
1279         if (INTEL_INFO(dev)->gen >= 9) {
1280                 for_each_sprite(pipe, sprite) {
1281                         val = I915_READ(PLANE_CTL(pipe, sprite));
1282                         WARN(val & PLANE_CTL_ENABLE,
1283                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite, pipe_name(pipe));
1285                 }
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 for_each_sprite(pipe, sprite) {
1288                         reg = SPCNTR(pipe, sprite);
1289                         val = I915_READ(reg);
1290                         WARN(val & SP_ENABLE,
1291                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1292                              sprite_name(pipe, sprite), pipe_name(pipe));
1293                 }
1294         } else if (INTEL_INFO(dev)->gen >= 7) {
1295                 reg = SPRCTL(pipe);
1296                 val = I915_READ(reg);
1297                 WARN(val & SPRITE_ENABLE,
1298                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1299                      plane_name(pipe), pipe_name(pipe));
1300         } else if (INTEL_INFO(dev)->gen >= 5) {
1301                 reg = DVSCNTR(pipe);
1302                 val = I915_READ(reg);
1303                 WARN(val & DVS_ENABLE,
1304                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1305                      plane_name(pipe), pipe_name(pipe));
1306         }
1307 }
1308
1309 static void assert_vblank_disabled(struct drm_crtc *crtc)
1310 {
1311         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1312                 drm_crtc_vblank_put(crtc);
1313 }
1314
1315 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1316 {
1317         u32 val;
1318         bool enabled;
1319
1320         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1321
1322         val = I915_READ(PCH_DREF_CONTROL);
1323         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1324                             DREF_SUPERSPREAD_SOURCE_MASK));
1325         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1326 }
1327
1328 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1329                                            enum pipe pipe)
1330 {
1331         int reg;
1332         u32 val;
1333         bool enabled;
1334
1335         reg = PCH_TRANSCONF(pipe);
1336         val = I915_READ(reg);
1337         enabled = !!(val & TRANS_ENABLE);
1338         WARN(enabled,
1339              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1340              pipe_name(pipe));
1341 }
1342
1343 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1344                             enum pipe pipe, u32 port_sel, u32 val)
1345 {
1346         if ((val & DP_PORT_EN) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1351                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1352                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1353                         return false;
1354         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1355                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1356                         return false;
1357         } else {
1358                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1359                         return false;
1360         }
1361         return true;
1362 }
1363
1364 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1365                               enum pipe pipe, u32 val)
1366 {
1367         if ((val & SDVO_ENABLE) == 0)
1368                 return false;
1369
1370         if (HAS_PCH_CPT(dev_priv->dev)) {
1371                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1372                         return false;
1373         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1374                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1375                         return false;
1376         } else {
1377                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1378                         return false;
1379         }
1380         return true;
1381 }
1382
1383 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1384                               enum pipe pipe, u32 val)
1385 {
1386         if ((val & LVDS_PORT_EN) == 0)
1387                 return false;
1388
1389         if (HAS_PCH_CPT(dev_priv->dev)) {
1390                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1391                         return false;
1392         } else {
1393                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1394                         return false;
1395         }
1396         return true;
1397 }
1398
1399 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1400                               enum pipe pipe, u32 val)
1401 {
1402         if ((val & ADPA_DAC_ENABLE) == 0)
1403                 return false;
1404         if (HAS_PCH_CPT(dev_priv->dev)) {
1405                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1406                         return false;
1407         } else {
1408                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1409                         return false;
1410         }
1411         return true;
1412 }
1413
1414 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1415                                    enum pipe pipe, int reg, u32 port_sel)
1416 {
1417         u32 val = I915_READ(reg);
1418         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1419              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1420              reg, pipe_name(pipe));
1421
1422         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1423              && (val & DP_PIPEB_SELECT),
1424              "IBX PCH dp port still using transcoder B\n");
1425 }
1426
1427 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1428                                      enum pipe pipe, int reg)
1429 {
1430         u32 val = I915_READ(reg);
1431         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1432              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1433              reg, pipe_name(pipe));
1434
1435         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1436              && (val & SDVO_PIPE_B_SELECT),
1437              "IBX PCH hdmi port still using transcoder B\n");
1438 }
1439
1440 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1441                                       enum pipe pipe)
1442 {
1443         int reg;
1444         u32 val;
1445
1446         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1447         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1448         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1449
1450         reg = PCH_ADPA;
1451         val = I915_READ(reg);
1452         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1453              "PCH VGA enabled on transcoder %c, should be disabled\n",
1454              pipe_name(pipe));
1455
1456         reg = PCH_LVDS;
1457         val = I915_READ(reg);
1458         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1459              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1460              pipe_name(pipe));
1461
1462         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1463         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1464         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1465 }
1466
1467 static void intel_init_dpio(struct drm_device *dev)
1468 {
1469         struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471         if (!IS_VALLEYVIEW(dev))
1472                 return;
1473
1474         /*
1475          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1476          * CHV x1 PHY (DP/HDMI D)
1477          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1478          */
1479         if (IS_CHERRYVIEW(dev)) {
1480                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1481                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1482         } else {
1483                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1484         }
1485 }
1486
1487 static void vlv_enable_pll(struct intel_crtc *crtc)
1488 {
1489         struct drm_device *dev = crtc->base.dev;
1490         struct drm_i915_private *dev_priv = dev->dev_private;
1491         int reg = DPLL(crtc->pipe);
1492         u32 dpll = crtc->config.dpll_hw_state.dpll;
1493
1494         assert_pipe_disabled(dev_priv, crtc->pipe);
1495
1496         /* No really, not for ILK+ */
1497         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1498
1499         /* PLL is protected by panel, make sure we can write it */
1500         if (IS_MOBILE(dev_priv->dev))
1501                 assert_panel_unlocked(dev_priv, crtc->pipe);
1502
1503         I915_WRITE(reg, dpll);
1504         POSTING_READ(reg);
1505         udelay(150);
1506
1507         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1508                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1509
1510         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1511         POSTING_READ(DPLL_MD(crtc->pipe));
1512
1513         /* We do this three times for luck */
1514         I915_WRITE(reg, dpll);
1515         POSTING_READ(reg);
1516         udelay(150); /* wait for warmup */
1517         I915_WRITE(reg, dpll);
1518         POSTING_READ(reg);
1519         udelay(150); /* wait for warmup */
1520         I915_WRITE(reg, dpll);
1521         POSTING_READ(reg);
1522         udelay(150); /* wait for warmup */
1523 }
1524
1525 static void chv_enable_pll(struct intel_crtc *crtc)
1526 {
1527         struct drm_device *dev = crtc->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         int pipe = crtc->pipe;
1530         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1531         u32 tmp;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1536
1537         mutex_lock(&dev_priv->dpio_lock);
1538
1539         /* Enable back the 10bit clock to display controller */
1540         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1541         tmp |= DPIO_DCLKP_EN;
1542         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1543
1544         /*
1545          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1546          */
1547         udelay(1);
1548
1549         /* Enable PLL */
1550         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1551
1552         /* Check PLL is locked */
1553         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1555
1556         /* not sure when this should be written */
1557         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1558         POSTING_READ(DPLL_MD(pipe));
1559
1560         mutex_unlock(&dev_priv->dpio_lock);
1561 }
1562
1563 static int intel_num_dvo_pipes(struct drm_device *dev)
1564 {
1565         struct intel_crtc *crtc;
1566         int count = 0;
1567
1568         for_each_intel_crtc(dev, crtc)
1569                 count += crtc->active &&
1570                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1571
1572         return count;
1573 }
1574
1575 static void i9xx_enable_pll(struct intel_crtc *crtc)
1576 {
1577         struct drm_device *dev = crtc->base.dev;
1578         struct drm_i915_private *dev_priv = dev->dev_private;
1579         int reg = DPLL(crtc->pipe);
1580         u32 dpll = crtc->config.dpll_hw_state.dpll;
1581
1582         assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584         /* No really, not for ILK+ */
1585         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1586
1587         /* PLL is protected by panel, make sure we can write it */
1588         if (IS_MOBILE(dev) && !IS_I830(dev))
1589                 assert_panel_unlocked(dev_priv, crtc->pipe);
1590
1591         /* Enable DVO 2x clock on both PLLs if necessary */
1592         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1593                 /*
1594                  * It appears to be important that we don't enable this
1595                  * for the current pipe before otherwise configuring the
1596                  * PLL. No idea how this should be handled if multiple
1597                  * DVO outputs are enabled simultaneosly.
1598                  */
1599                 dpll |= DPLL_DVO_2X_MODE;
1600                 I915_WRITE(DPLL(!crtc->pipe),
1601                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1602         }
1603
1604         /* Wait for the clocks to stabilize. */
1605         POSTING_READ(reg);
1606         udelay(150);
1607
1608         if (INTEL_INFO(dev)->gen >= 4) {
1609                 I915_WRITE(DPLL_MD(crtc->pipe),
1610                            crtc->config.dpll_hw_state.dpll_md);
1611         } else {
1612                 /* The pixel multiplier can only be updated once the
1613                  * DPLL is enabled and the clocks are stable.
1614                  *
1615                  * So write it again.
1616                  */
1617                 I915_WRITE(reg, dpll);
1618         }
1619
1620         /* We do this three times for luck */
1621         I915_WRITE(reg, dpll);
1622         POSTING_READ(reg);
1623         udelay(150); /* wait for warmup */
1624         I915_WRITE(reg, dpll);
1625         POSTING_READ(reg);
1626         udelay(150); /* wait for warmup */
1627         I915_WRITE(reg, dpll);
1628         POSTING_READ(reg);
1629         udelay(150); /* wait for warmup */
1630 }
1631
1632 /**
1633  * i9xx_disable_pll - disable a PLL
1634  * @dev_priv: i915 private structure
1635  * @pipe: pipe PLL to disable
1636  *
1637  * Disable the PLL for @pipe, making sure the pipe is off first.
1638  *
1639  * Note!  This is for pre-ILK only.
1640  */
1641 static void i9xx_disable_pll(struct intel_crtc *crtc)
1642 {
1643         struct drm_device *dev = crtc->base.dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         enum pipe pipe = crtc->pipe;
1646
1647         /* Disable DVO 2x clock on both PLLs if necessary */
1648         if (IS_I830(dev) &&
1649             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1650             intel_num_dvo_pipes(dev) == 1) {
1651                 I915_WRITE(DPLL(PIPE_B),
1652                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1653                 I915_WRITE(DPLL(PIPE_A),
1654                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1655         }
1656
1657         /* Don't disable pipe or pipe PLLs if needed */
1658         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1659             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1660                 return;
1661
1662         /* Make sure the pipe isn't still relying on us */
1663         assert_pipe_disabled(dev_priv, pipe);
1664
1665         I915_WRITE(DPLL(pipe), 0);
1666         POSTING_READ(DPLL(pipe));
1667 }
1668
1669 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1670 {
1671         u32 val = 0;
1672
1673         /* Make sure the pipe isn't still relying on us */
1674         assert_pipe_disabled(dev_priv, pipe);
1675
1676         /*
1677          * Leave integrated clock source and reference clock enabled for pipe B.
1678          * The latter is needed for VGA hotplug / manual detection.
1679          */
1680         if (pipe == PIPE_B)
1681                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1682         I915_WRITE(DPLL(pipe), val);
1683         POSTING_READ(DPLL(pipe));
1684
1685 }
1686
1687 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1688 {
1689         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1690         u32 val;
1691
1692         /* Make sure the pipe isn't still relying on us */
1693         assert_pipe_disabled(dev_priv, pipe);
1694
1695         /* Set PLL en = 0 */
1696         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1697         if (pipe != PIPE_A)
1698                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1699         I915_WRITE(DPLL(pipe), val);
1700         POSTING_READ(DPLL(pipe));
1701
1702         mutex_lock(&dev_priv->dpio_lock);
1703
1704         /* Disable 10bit clock to display controller */
1705         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1706         val &= ~DPIO_DCLKP_EN;
1707         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1708
1709         /* disable left/right clock distribution */
1710         if (pipe != PIPE_B) {
1711                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1712                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1713                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1714         } else {
1715                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1716                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1717                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1718         }
1719
1720         mutex_unlock(&dev_priv->dpio_lock);
1721 }
1722
1723 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1724                 struct intel_digital_port *dport)
1725 {
1726         u32 port_mask;
1727         int dpll_reg;
1728
1729         switch (dport->port) {
1730         case PORT_B:
1731                 port_mask = DPLL_PORTB_READY_MASK;
1732                 dpll_reg = DPLL(0);
1733                 break;
1734         case PORT_C:
1735                 port_mask = DPLL_PORTC_READY_MASK;
1736                 dpll_reg = DPLL(0);
1737                 break;
1738         case PORT_D:
1739                 port_mask = DPLL_PORTD_READY_MASK;
1740                 dpll_reg = DPIO_PHY_STATUS;
1741                 break;
1742         default:
1743                 BUG();
1744         }
1745
1746         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1747                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1748                      port_name(dport->port), I915_READ(dpll_reg));
1749 }
1750
1751 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1752 {
1753         struct drm_device *dev = crtc->base.dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1756
1757         if (WARN_ON(pll == NULL))
1758                 return;
1759
1760         WARN_ON(!pll->refcount);
1761         if (pll->active == 0) {
1762                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1763                 WARN_ON(pll->on);
1764                 assert_shared_dpll_disabled(dev_priv, pll);
1765
1766                 pll->mode_set(dev_priv, pll);
1767         }
1768 }
1769
1770 /**
1771  * intel_enable_shared_dpll - enable PCH PLL
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe PLL to enable
1774  *
1775  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1776  * drives the transcoder clock.
1777  */
1778 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1779 {
1780         struct drm_device *dev = crtc->base.dev;
1781         struct drm_i915_private *dev_priv = dev->dev_private;
1782         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1783
1784         if (WARN_ON(pll == NULL))
1785                 return;
1786
1787         if (WARN_ON(pll->refcount == 0))
1788                 return;
1789
1790         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1791                       pll->name, pll->active, pll->on,
1792                       crtc->base.base.id);
1793
1794         if (pll->active++) {
1795                 WARN_ON(!pll->on);
1796                 assert_shared_dpll_enabled(dev_priv, pll);
1797                 return;
1798         }
1799         WARN_ON(pll->on);
1800
1801         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1802
1803         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1804         pll->enable(dev_priv, pll);
1805         pll->on = true;
1806 }
1807
1808 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1809 {
1810         struct drm_device *dev = crtc->base.dev;
1811         struct drm_i915_private *dev_priv = dev->dev_private;
1812         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1813
1814         /* PCH only available on ILK+ */
1815         BUG_ON(INTEL_INFO(dev)->gen < 5);
1816         if (WARN_ON(pll == NULL))
1817                return;
1818
1819         if (WARN_ON(pll->refcount == 0))
1820                 return;
1821
1822         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1823                       pll->name, pll->active, pll->on,
1824                       crtc->base.base.id);
1825
1826         if (WARN_ON(pll->active == 0)) {
1827                 assert_shared_dpll_disabled(dev_priv, pll);
1828                 return;
1829         }
1830
1831         assert_shared_dpll_enabled(dev_priv, pll);
1832         WARN_ON(!pll->on);
1833         if (--pll->active)
1834                 return;
1835
1836         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1837         pll->disable(dev_priv, pll);
1838         pll->on = false;
1839
1840         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1841 }
1842
1843 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1844                                            enum pipe pipe)
1845 {
1846         struct drm_device *dev = dev_priv->dev;
1847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1849         uint32_t reg, val, pipeconf_val;
1850
1851         /* PCH only available on ILK+ */
1852         BUG_ON(!HAS_PCH_SPLIT(dev));
1853
1854         /* Make sure PCH DPLL is enabled */
1855         assert_shared_dpll_enabled(dev_priv,
1856                                    intel_crtc_to_shared_dpll(intel_crtc));
1857
1858         /* FDI must be feeding us bits for PCH ports */
1859         assert_fdi_tx_enabled(dev_priv, pipe);
1860         assert_fdi_rx_enabled(dev_priv, pipe);
1861
1862         if (HAS_PCH_CPT(dev)) {
1863                 /* Workaround: Set the timing override bit before enabling the
1864                  * pch transcoder. */
1865                 reg = TRANS_CHICKEN2(pipe);
1866                 val = I915_READ(reg);
1867                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1868                 I915_WRITE(reg, val);
1869         }
1870
1871         reg = PCH_TRANSCONF(pipe);
1872         val = I915_READ(reg);
1873         pipeconf_val = I915_READ(PIPECONF(pipe));
1874
1875         if (HAS_PCH_IBX(dev_priv->dev)) {
1876                 /*
1877                  * make the BPC in transcoder be consistent with
1878                  * that in pipeconf reg.
1879                  */
1880                 val &= ~PIPECONF_BPC_MASK;
1881                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1882         }
1883
1884         val &= ~TRANS_INTERLACE_MASK;
1885         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1886                 if (HAS_PCH_IBX(dev_priv->dev) &&
1887                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1888                         val |= TRANS_LEGACY_INTERLACED_ILK;
1889                 else
1890                         val |= TRANS_INTERLACED;
1891         else
1892                 val |= TRANS_PROGRESSIVE;
1893
1894         I915_WRITE(reg, val | TRANS_ENABLE);
1895         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1896                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1897 }
1898
1899 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1900                                       enum transcoder cpu_transcoder)
1901 {
1902         u32 val, pipeconf_val;
1903
1904         /* PCH only available on ILK+ */
1905         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1906
1907         /* FDI must be feeding us bits for PCH ports */
1908         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1909         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1910
1911         /* Workaround: set timing override bit. */
1912         val = I915_READ(_TRANSA_CHICKEN2);
1913         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1914         I915_WRITE(_TRANSA_CHICKEN2, val);
1915
1916         val = TRANS_ENABLE;
1917         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1918
1919         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1920             PIPECONF_INTERLACED_ILK)
1921                 val |= TRANS_INTERLACED;
1922         else
1923                 val |= TRANS_PROGRESSIVE;
1924
1925         I915_WRITE(LPT_TRANSCONF, val);
1926         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1927                 DRM_ERROR("Failed to enable PCH transcoder\n");
1928 }
1929
1930 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1931                                             enum pipe pipe)
1932 {
1933         struct drm_device *dev = dev_priv->dev;
1934         uint32_t reg, val;
1935
1936         /* FDI relies on the transcoder */
1937         assert_fdi_tx_disabled(dev_priv, pipe);
1938         assert_fdi_rx_disabled(dev_priv, pipe);
1939
1940         /* Ports must be off as well */
1941         assert_pch_ports_disabled(dev_priv, pipe);
1942
1943         reg = PCH_TRANSCONF(pipe);
1944         val = I915_READ(reg);
1945         val &= ~TRANS_ENABLE;
1946         I915_WRITE(reg, val);
1947         /* wait for PCH transcoder off, transcoder state */
1948         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1949                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1950
1951         if (!HAS_PCH_IBX(dev)) {
1952                 /* Workaround: Clear the timing override chicken bit again. */
1953                 reg = TRANS_CHICKEN2(pipe);
1954                 val = I915_READ(reg);
1955                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1956                 I915_WRITE(reg, val);
1957         }
1958 }
1959
1960 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1961 {
1962         u32 val;
1963
1964         val = I915_READ(LPT_TRANSCONF);
1965         val &= ~TRANS_ENABLE;
1966         I915_WRITE(LPT_TRANSCONF, val);
1967         /* wait for PCH transcoder off, transcoder state */
1968         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1969                 DRM_ERROR("Failed to disable PCH transcoder\n");
1970
1971         /* Workaround: clear timing override bit. */
1972         val = I915_READ(_TRANSA_CHICKEN2);
1973         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1974         I915_WRITE(_TRANSA_CHICKEN2, val);
1975 }
1976
1977 /**
1978  * intel_enable_pipe - enable a pipe, asserting requirements
1979  * @crtc: crtc responsible for the pipe
1980  *
1981  * Enable @crtc's pipe, making sure that various hardware specific requirements
1982  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1983  */
1984 static void intel_enable_pipe(struct intel_crtc *crtc)
1985 {
1986         struct drm_device *dev = crtc->base.dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         enum pipe pipe = crtc->pipe;
1989         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1990                                                                       pipe);
1991         enum pipe pch_transcoder;
1992         int reg;
1993         u32 val;
1994
1995         assert_planes_disabled(dev_priv, pipe);
1996         assert_cursor_disabled(dev_priv, pipe);
1997         assert_sprites_disabled(dev_priv, pipe);
1998
1999         if (HAS_PCH_LPT(dev_priv->dev))
2000                 pch_transcoder = TRANSCODER_A;
2001         else
2002                 pch_transcoder = pipe;
2003
2004         /*
2005          * A pipe without a PLL won't actually be able to drive bits from
2006          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2007          * need the check.
2008          */
2009         if (!HAS_PCH_SPLIT(dev_priv->dev))
2010                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2011                         assert_dsi_pll_enabled(dev_priv);
2012                 else
2013                         assert_pll_enabled(dev_priv, pipe);
2014         else {
2015                 if (crtc->config.has_pch_encoder) {
2016                         /* if driving the PCH, we need FDI enabled */
2017                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2018                         assert_fdi_tx_pll_enabled(dev_priv,
2019                                                   (enum pipe) cpu_transcoder);
2020                 }
2021                 /* FIXME: assert CPU port conditions for SNB+ */
2022         }
2023
2024         reg = PIPECONF(cpu_transcoder);
2025         val = I915_READ(reg);
2026         if (val & PIPECONF_ENABLE) {
2027                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2028                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2029                 return;
2030         }
2031
2032         I915_WRITE(reg, val | PIPECONF_ENABLE);
2033         POSTING_READ(reg);
2034 }
2035
2036 /**
2037  * intel_disable_pipe - disable a pipe, asserting requirements
2038  * @crtc: crtc whose pipes is to be disabled
2039  *
2040  * Disable the pipe of @crtc, making sure that various hardware
2041  * specific requirements are met, if applicable, e.g. plane
2042  * disabled, panel fitter off, etc.
2043  *
2044  * Will wait until the pipe has shut down before returning.
2045  */
2046 static void intel_disable_pipe(struct intel_crtc *crtc)
2047 {
2048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2049         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2050         enum pipe pipe = crtc->pipe;
2051         int reg;
2052         u32 val;
2053
2054         /*
2055          * Make sure planes won't keep trying to pump pixels to us,
2056          * or we might hang the display.
2057          */
2058         assert_planes_disabled(dev_priv, pipe);
2059         assert_cursor_disabled(dev_priv, pipe);
2060         assert_sprites_disabled(dev_priv, pipe);
2061
2062         reg = PIPECONF(cpu_transcoder);
2063         val = I915_READ(reg);
2064         if ((val & PIPECONF_ENABLE) == 0)
2065                 return;
2066
2067         /*
2068          * Double wide has implications for planes
2069          * so best keep it disabled when not needed.
2070          */
2071         if (crtc->config.double_wide)
2072                 val &= ~PIPECONF_DOUBLE_WIDE;
2073
2074         /* Don't disable pipe or pipe PLLs if needed */
2075         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2076             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2077                 val &= ~PIPECONF_ENABLE;
2078
2079         I915_WRITE(reg, val);
2080         if ((val & PIPECONF_ENABLE) == 0)
2081                 intel_wait_for_pipe_off(crtc);
2082 }
2083
2084 /*
2085  * Plane regs are double buffered, going from enabled->disabled needs a
2086  * trigger in order to latch.  The display address reg provides this.
2087  */
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089                                enum plane plane)
2090 {
2091         struct drm_device *dev = dev_priv->dev;
2092         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2093
2094         I915_WRITE(reg, I915_READ(reg));
2095         POSTING_READ(reg);
2096 }
2097
2098 /**
2099  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100  * @plane:  plane to be enabled
2101  * @crtc: crtc for the plane
2102  *
2103  * Enable @plane on @crtc, making sure that the pipe is running first.
2104  */
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106                                           struct drm_crtc *crtc)
2107 {
2108         struct drm_device *dev = plane->dev;
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2114
2115         if (intel_crtc->primary_enabled)
2116                 return;
2117
2118         intel_crtc->primary_enabled = true;
2119
2120         dev_priv->display.update_primary_plane(crtc, plane->fb,
2121                                                crtc->x, crtc->y);
2122
2123         /*
2124          * BDW signals flip done immediately if the plane
2125          * is disabled, even if the plane enable is already
2126          * armed to occur at the next vblank :(
2127          */
2128         if (IS_BROADWELL(dev))
2129                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2130 }
2131
2132 /**
2133  * intel_disable_primary_hw_plane - disable the primary hardware plane
2134  * @plane: plane to be disabled
2135  * @crtc: crtc for the plane
2136  *
2137  * Disable @plane on @crtc, making sure that the pipe is running first.
2138  */
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140                                            struct drm_crtc *crtc)
2141 {
2142         struct drm_device *dev = plane->dev;
2143         struct drm_i915_private *dev_priv = dev->dev_private;
2144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2147
2148         if (!intel_crtc->primary_enabled)
2149                 return;
2150
2151         intel_crtc->primary_enabled = false;
2152
2153         dev_priv->display.update_primary_plane(crtc, plane->fb,
2154                                                crtc->x, crtc->y);
2155 }
2156
2157 static bool need_vtd_wa(struct drm_device *dev)
2158 {
2159 #ifdef CONFIG_INTEL_IOMMU
2160         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161                 return true;
2162 #endif
2163         return false;
2164 }
2165
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167 {
2168         int tile_height;
2169
2170         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171         return ALIGN(height, tile_height);
2172 }
2173
2174 int
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176                            struct drm_i915_gem_object *obj,
2177                            struct intel_engine_cs *pipelined)
2178 {
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180         u32 alignment;
2181         int ret;
2182
2183         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
2185         switch (obj->tiling_mode) {
2186         case I915_TILING_NONE:
2187                 if (INTEL_INFO(dev)->gen >= 9)
2188                         alignment = 256 * 1024;
2189                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2190                         alignment = 128 * 1024;
2191                 else if (INTEL_INFO(dev)->gen >= 4)
2192                         alignment = 4 * 1024;
2193                 else
2194                         alignment = 64 * 1024;
2195                 break;
2196         case I915_TILING_X:
2197                 if (INTEL_INFO(dev)->gen >= 9)
2198                         alignment = 256 * 1024;
2199                 else {
2200                         /* pin() will align the object as required by fence */
2201                         alignment = 0;
2202                 }
2203                 break;
2204         case I915_TILING_Y:
2205                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2206                 return -EINVAL;
2207         default:
2208                 BUG();
2209         }
2210
2211         /* Note that the w/a also requires 64 PTE of padding following the
2212          * bo. We currently fill all unused PTE with the shadow page and so
2213          * we should always have valid PTE following the scanout preventing
2214          * the VT-d warning.
2215          */
2216         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2217                 alignment = 256 * 1024;
2218
2219         /*
2220          * Global gtt pte registers are special registers which actually forward
2221          * writes to a chunk of system memory. Which means that there is no risk
2222          * that the register values disappear as soon as we call
2223          * intel_runtime_pm_put(), so it is correct to wrap only the
2224          * pin/unpin/fence and not more.
2225          */
2226         intel_runtime_pm_get(dev_priv);
2227
2228         dev_priv->mm.interruptible = false;
2229         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230         if (ret)
2231                 goto err_interruptible;
2232
2233         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234          * fence, whereas 965+ only requires a fence if using
2235          * framebuffer compression.  For simplicity, we always install
2236          * a fence as the cost is not that onerous.
2237          */
2238         ret = i915_gem_object_get_fence(obj);
2239         if (ret)
2240                 goto err_unpin;
2241
2242         i915_gem_object_pin_fence(obj);
2243
2244         dev_priv->mm.interruptible = true;
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247
2248 err_unpin:
2249         i915_gem_object_unpin_from_display_plane(obj);
2250 err_interruptible:
2251         dev_priv->mm.interruptible = true;
2252         intel_runtime_pm_put(dev_priv);
2253         return ret;
2254 }
2255
2256 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2257 {
2258         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2259
2260         i915_gem_object_unpin_fence(obj);
2261         i915_gem_object_unpin_from_display_plane(obj);
2262 }
2263
2264 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2265  * is assumed to be a power-of-two. */
2266 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2267                                              unsigned int tiling_mode,
2268                                              unsigned int cpp,
2269                                              unsigned int pitch)
2270 {
2271         if (tiling_mode != I915_TILING_NONE) {
2272                 unsigned int tile_rows, tiles;
2273
2274                 tile_rows = *y / 8;
2275                 *y %= 8;
2276
2277                 tiles = *x / (512/cpp);
2278                 *x %= 512/cpp;
2279
2280                 return tile_rows * pitch * 8 + tiles * 4096;
2281         } else {
2282                 unsigned int offset;
2283
2284                 offset = *y * pitch + *x * cpp;
2285                 *y = 0;
2286                 *x = (offset & 4095) / cpp;
2287                 return offset & -4096;
2288         }
2289 }
2290
2291 int intel_format_to_fourcc(int format)
2292 {
2293         switch (format) {
2294         case DISPPLANE_8BPP:
2295                 return DRM_FORMAT_C8;
2296         case DISPPLANE_BGRX555:
2297                 return DRM_FORMAT_XRGB1555;
2298         case DISPPLANE_BGRX565:
2299                 return DRM_FORMAT_RGB565;
2300         default:
2301         case DISPPLANE_BGRX888:
2302                 return DRM_FORMAT_XRGB8888;
2303         case DISPPLANE_RGBX888:
2304                 return DRM_FORMAT_XBGR8888;
2305         case DISPPLANE_BGRX101010:
2306                 return DRM_FORMAT_XRGB2101010;
2307         case DISPPLANE_RGBX101010:
2308                 return DRM_FORMAT_XBGR2101010;
2309         }
2310 }
2311
2312 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2313                                   struct intel_plane_config *plane_config)
2314 {
2315         struct drm_device *dev = crtc->base.dev;
2316         struct drm_i915_gem_object *obj = NULL;
2317         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2318         u32 base = plane_config->base;
2319
2320         if (plane_config->size == 0)
2321                 return false;
2322
2323         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2324                                                              plane_config->size);
2325         if (!obj)
2326                 return false;
2327
2328         if (plane_config->tiled) {
2329                 obj->tiling_mode = I915_TILING_X;
2330                 obj->stride = crtc->base.primary->fb->pitches[0];
2331         }
2332
2333         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2334         mode_cmd.width = crtc->base.primary->fb->width;
2335         mode_cmd.height = crtc->base.primary->fb->height;
2336         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2337
2338         mutex_lock(&dev->struct_mutex);
2339
2340         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2341                                    &mode_cmd, obj)) {
2342                 DRM_DEBUG_KMS("intel fb init failed\n");
2343                 goto out_unref_obj;
2344         }
2345
2346         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2347         mutex_unlock(&dev->struct_mutex);
2348
2349         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2350         return true;
2351
2352 out_unref_obj:
2353         drm_gem_object_unreference(&obj->base);
2354         mutex_unlock(&dev->struct_mutex);
2355         return false;
2356 }
2357
2358 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2359                                  struct intel_plane_config *plane_config)
2360 {
2361         struct drm_device *dev = intel_crtc->base.dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct drm_crtc *c;
2364         struct intel_crtc *i;
2365         struct drm_i915_gem_object *obj;
2366
2367         if (!intel_crtc->base.primary->fb)
2368                 return;
2369
2370         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2371                 return;
2372
2373         kfree(intel_crtc->base.primary->fb);
2374         intel_crtc->base.primary->fb = NULL;
2375
2376         /*
2377          * Failed to alloc the obj, check to see if we should share
2378          * an fb with another CRTC instead
2379          */
2380         for_each_crtc(dev, c) {
2381                 i = to_intel_crtc(c);
2382
2383                 if (c == &intel_crtc->base)
2384                         continue;
2385
2386                 if (!i->active)
2387                         continue;
2388
2389                 obj = intel_fb_obj(c->primary->fb);
2390                 if (obj == NULL)
2391                         continue;
2392
2393                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2394                         if (obj->tiling_mode != I915_TILING_NONE)
2395                                 dev_priv->preserve_bios_swizzle = true;
2396
2397                         drm_framebuffer_reference(c->primary->fb);
2398                         intel_crtc->base.primary->fb = c->primary->fb;
2399                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2400                         break;
2401                 }
2402         }
2403 }
2404
2405 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2406                                       struct drm_framebuffer *fb,
2407                                       int x, int y)
2408 {
2409         struct drm_device *dev = crtc->dev;
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412         struct drm_i915_gem_object *obj;
2413         int plane = intel_crtc->plane;
2414         unsigned long linear_offset;
2415         u32 dspcntr;
2416         u32 reg = DSPCNTR(plane);
2417         int pixel_size;
2418
2419         if (!intel_crtc->primary_enabled) {
2420                 I915_WRITE(reg, 0);
2421                 if (INTEL_INFO(dev)->gen >= 4)
2422                         I915_WRITE(DSPSURF(plane), 0);
2423                 else
2424                         I915_WRITE(DSPADDR(plane), 0);
2425                 POSTING_READ(reg);
2426                 return;
2427         }
2428
2429         obj = intel_fb_obj(fb);
2430         if (WARN_ON(obj == NULL))
2431                 return;
2432
2433         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2434
2435         dspcntr = DISPPLANE_GAMMA_ENABLE;
2436
2437         dspcntr |= DISPLAY_PLANE_ENABLE;
2438
2439         if (INTEL_INFO(dev)->gen < 4) {
2440                 if (intel_crtc->pipe == PIPE_B)
2441                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2442
2443                 /* pipesrc and dspsize control the size that is scaled from,
2444                  * which should always be the user's requested size.
2445                  */
2446                 I915_WRITE(DSPSIZE(plane),
2447                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2448                            (intel_crtc->config.pipe_src_w - 1));
2449                 I915_WRITE(DSPPOS(plane), 0);
2450         }
2451
2452         switch (fb->pixel_format) {
2453         case DRM_FORMAT_C8:
2454                 dspcntr |= DISPPLANE_8BPP;
2455                 break;
2456         case DRM_FORMAT_XRGB1555:
2457         case DRM_FORMAT_ARGB1555:
2458                 dspcntr |= DISPPLANE_BGRX555;
2459                 break;
2460         case DRM_FORMAT_RGB565:
2461                 dspcntr |= DISPPLANE_BGRX565;
2462                 break;
2463         case DRM_FORMAT_XRGB8888:
2464         case DRM_FORMAT_ARGB8888:
2465                 dspcntr |= DISPPLANE_BGRX888;
2466                 break;
2467         case DRM_FORMAT_XBGR8888:
2468         case DRM_FORMAT_ABGR8888:
2469                 dspcntr |= DISPPLANE_RGBX888;
2470                 break;
2471         case DRM_FORMAT_XRGB2101010:
2472         case DRM_FORMAT_ARGB2101010:
2473                 dspcntr |= DISPPLANE_BGRX101010;
2474                 break;
2475         case DRM_FORMAT_XBGR2101010:
2476         case DRM_FORMAT_ABGR2101010:
2477                 dspcntr |= DISPPLANE_RGBX101010;
2478                 break;
2479         default:
2480                 BUG();
2481         }
2482
2483         if (INTEL_INFO(dev)->gen >= 4 &&
2484             obj->tiling_mode != I915_TILING_NONE)
2485                 dspcntr |= DISPPLANE_TILED;
2486
2487         if (IS_G4X(dev))
2488                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2489
2490         linear_offset = y * fb->pitches[0] + x * pixel_size;
2491
2492         if (INTEL_INFO(dev)->gen >= 4) {
2493                 intel_crtc->dspaddr_offset =
2494                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2495                                                        pixel_size,
2496                                                        fb->pitches[0]);
2497                 linear_offset -= intel_crtc->dspaddr_offset;
2498         } else {
2499                 intel_crtc->dspaddr_offset = linear_offset;
2500         }
2501
2502         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2503                 dspcntr |= DISPPLANE_ROTATE_180;
2504
2505                 x += (intel_crtc->config.pipe_src_w - 1);
2506                 y += (intel_crtc->config.pipe_src_h - 1);
2507
2508                 /* Finding the last pixel of the last line of the display
2509                 data and adding to linear_offset*/
2510                 linear_offset +=
2511                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2512                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2513         }
2514
2515         I915_WRITE(reg, dspcntr);
2516
2517         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2519                       fb->pitches[0]);
2520         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2521         if (INTEL_INFO(dev)->gen >= 4) {
2522                 I915_WRITE(DSPSURF(plane),
2523                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2524                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526         } else
2527                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2528         POSTING_READ(reg);
2529 }
2530
2531 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2532                                           struct drm_framebuffer *fb,
2533                                           int x, int y)
2534 {
2535         struct drm_device *dev = crtc->dev;
2536         struct drm_i915_private *dev_priv = dev->dev_private;
2537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2538         struct drm_i915_gem_object *obj;
2539         int plane = intel_crtc->plane;
2540         unsigned long linear_offset;
2541         u32 dspcntr;
2542         u32 reg = DSPCNTR(plane);
2543         int pixel_size;
2544
2545         if (!intel_crtc->primary_enabled) {
2546                 I915_WRITE(reg, 0);
2547                 I915_WRITE(DSPSURF(plane), 0);
2548                 POSTING_READ(reg);
2549                 return;
2550         }
2551
2552         obj = intel_fb_obj(fb);
2553         if (WARN_ON(obj == NULL))
2554                 return;
2555
2556         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2557
2558         dspcntr = DISPPLANE_GAMMA_ENABLE;
2559
2560         dspcntr |= DISPLAY_PLANE_ENABLE;
2561
2562         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2563                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2564
2565         switch (fb->pixel_format) {
2566         case DRM_FORMAT_C8:
2567                 dspcntr |= DISPPLANE_8BPP;
2568                 break;
2569         case DRM_FORMAT_RGB565:
2570                 dspcntr |= DISPPLANE_BGRX565;
2571                 break;
2572         case DRM_FORMAT_XRGB8888:
2573         case DRM_FORMAT_ARGB8888:
2574                 dspcntr |= DISPPLANE_BGRX888;
2575                 break;
2576         case DRM_FORMAT_XBGR8888:
2577         case DRM_FORMAT_ABGR8888:
2578                 dspcntr |= DISPPLANE_RGBX888;
2579                 break;
2580         case DRM_FORMAT_XRGB2101010:
2581         case DRM_FORMAT_ARGB2101010:
2582                 dspcntr |= DISPPLANE_BGRX101010;
2583                 break;
2584         case DRM_FORMAT_XBGR2101010:
2585         case DRM_FORMAT_ABGR2101010:
2586                 dspcntr |= DISPPLANE_RGBX101010;
2587                 break;
2588         default:
2589                 BUG();
2590         }
2591
2592         if (obj->tiling_mode != I915_TILING_NONE)
2593                 dspcntr |= DISPPLANE_TILED;
2594
2595         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2596                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2597
2598         linear_offset = y * fb->pitches[0] + x * pixel_size;
2599         intel_crtc->dspaddr_offset =
2600                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2601                                                pixel_size,
2602                                                fb->pitches[0]);
2603         linear_offset -= intel_crtc->dspaddr_offset;
2604         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2605                 dspcntr |= DISPPLANE_ROTATE_180;
2606
2607                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2608                         x += (intel_crtc->config.pipe_src_w - 1);
2609                         y += (intel_crtc->config.pipe_src_h - 1);
2610
2611                         /* Finding the last pixel of the last line of the display
2612                         data and adding to linear_offset*/
2613                         linear_offset +=
2614                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2615                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2616                 }
2617         }
2618
2619         I915_WRITE(reg, dspcntr);
2620
2621         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2622                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2623                       fb->pitches[0]);
2624         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2625         I915_WRITE(DSPSURF(plane),
2626                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2627         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2628                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2629         } else {
2630                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2631                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2632         }
2633         POSTING_READ(reg);
2634 }
2635
2636 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2637                                          struct drm_framebuffer *fb,
2638                                          int x, int y)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         struct intel_framebuffer *intel_fb;
2644         struct drm_i915_gem_object *obj;
2645         int pipe = intel_crtc->pipe;
2646         u32 plane_ctl, stride;
2647
2648         if (!intel_crtc->primary_enabled) {
2649                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2650                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2651                 POSTING_READ(PLANE_CTL(pipe, 0));
2652                 return;
2653         }
2654
2655         plane_ctl = PLANE_CTL_ENABLE |
2656                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2657                     PLANE_CTL_PIPE_CSC_ENABLE;
2658
2659         switch (fb->pixel_format) {
2660         case DRM_FORMAT_RGB565:
2661                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2662                 break;
2663         case DRM_FORMAT_XRGB8888:
2664                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2665                 break;
2666         case DRM_FORMAT_XBGR8888:
2667                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2668                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2669                 break;
2670         case DRM_FORMAT_XRGB2101010:
2671                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2672                 break;
2673         case DRM_FORMAT_XBGR2101010:
2674                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2675                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2676                 break;
2677         default:
2678                 BUG();
2679         }
2680
2681         intel_fb = to_intel_framebuffer(fb);
2682         obj = intel_fb->obj;
2683
2684         /*
2685          * The stride is either expressed as a multiple of 64 bytes chunks for
2686          * linear buffers or in number of tiles for tiled buffers.
2687          */
2688         switch (obj->tiling_mode) {
2689         case I915_TILING_NONE:
2690                 stride = fb->pitches[0] >> 6;
2691                 break;
2692         case I915_TILING_X:
2693                 plane_ctl |= PLANE_CTL_TILED_X;
2694                 stride = fb->pitches[0] >> 9;
2695                 break;
2696         default:
2697                 BUG();
2698         }
2699
2700         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2701         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2702                 plane_ctl |= PLANE_CTL_ROTATE_180;
2703
2704         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2705
2706         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2707                       i915_gem_obj_ggtt_offset(obj),
2708                       x, y, fb->width, fb->height,
2709                       fb->pitches[0]);
2710
2711         I915_WRITE(PLANE_POS(pipe, 0), 0);
2712         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2713         I915_WRITE(PLANE_SIZE(pipe, 0),
2714                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2715                    (intel_crtc->config.pipe_src_w - 1));
2716         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2717         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2718
2719         POSTING_READ(PLANE_SURF(pipe, 0));
2720 }
2721
2722 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2723 static int
2724 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2725                            int x, int y, enum mode_set_atomic state)
2726 {
2727         struct drm_device *dev = crtc->dev;
2728         struct drm_i915_private *dev_priv = dev->dev_private;
2729
2730         if (dev_priv->display.disable_fbc)
2731                 dev_priv->display.disable_fbc(dev);
2732
2733         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2734
2735         return 0;
2736 }
2737
2738 void intel_display_handle_reset(struct drm_device *dev)
2739 {
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct drm_crtc *crtc;
2742
2743         /*
2744          * Flips in the rings have been nuked by the reset,
2745          * so complete all pending flips so that user space
2746          * will get its events and not get stuck.
2747          *
2748          * Also update the base address of all primary
2749          * planes to the the last fb to make sure we're
2750          * showing the correct fb after a reset.
2751          *
2752          * Need to make two loops over the crtcs so that we
2753          * don't try to grab a crtc mutex before the
2754          * pending_flip_queue really got woken up.
2755          */
2756
2757         for_each_crtc(dev, crtc) {
2758                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759                 enum plane plane = intel_crtc->plane;
2760
2761                 intel_prepare_page_flip(dev, plane);
2762                 intel_finish_page_flip_plane(dev, plane);
2763         }
2764
2765         for_each_crtc(dev, crtc) {
2766                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767
2768                 drm_modeset_lock(&crtc->mutex, NULL);
2769                 /*
2770                  * FIXME: Once we have proper support for primary planes (and
2771                  * disabling them without disabling the entire crtc) allow again
2772                  * a NULL crtc->primary->fb.
2773                  */
2774                 if (intel_crtc->active && crtc->primary->fb)
2775                         dev_priv->display.update_primary_plane(crtc,
2776                                                                crtc->primary->fb,
2777                                                                crtc->x,
2778                                                                crtc->y);
2779                 drm_modeset_unlock(&crtc->mutex);
2780         }
2781 }
2782
2783 static int
2784 intel_finish_fb(struct drm_framebuffer *old_fb)
2785 {
2786         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2787         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2788         bool was_interruptible = dev_priv->mm.interruptible;
2789         int ret;
2790
2791         /* Big Hammer, we also need to ensure that any pending
2792          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2793          * current scanout is retired before unpinning the old
2794          * framebuffer.
2795          *
2796          * This should only fail upon a hung GPU, in which case we
2797          * can safely continue.
2798          */
2799         dev_priv->mm.interruptible = false;
2800         ret = i915_gem_object_finish_gpu(obj);
2801         dev_priv->mm.interruptible = was_interruptible;
2802
2803         return ret;
2804 }
2805
2806 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2807 {
2808         struct drm_device *dev = crtc->dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2811         bool pending;
2812
2813         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2814             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2815                 return false;
2816
2817         spin_lock_irq(&dev->event_lock);
2818         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2819         spin_unlock_irq(&dev->event_lock);
2820
2821         return pending;
2822 }
2823
2824 static void intel_update_pipe_size(struct intel_crtc *crtc)
2825 {
2826         struct drm_device *dev = crtc->base.dev;
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         const struct drm_display_mode *adjusted_mode;
2829
2830         if (!i915.fastboot)
2831                 return;
2832
2833         /*
2834          * Update pipe size and adjust fitter if needed: the reason for this is
2835          * that in compute_mode_changes we check the native mode (not the pfit
2836          * mode) to see if we can flip rather than do a full mode set. In the
2837          * fastboot case, we'll flip, but if we don't update the pipesrc and
2838          * pfit state, we'll end up with a big fb scanned out into the wrong
2839          * sized surface.
2840          *
2841          * To fix this properly, we need to hoist the checks up into
2842          * compute_mode_changes (or above), check the actual pfit state and
2843          * whether the platform allows pfit disable with pipe active, and only
2844          * then update the pipesrc and pfit state, even on the flip path.
2845          */
2846
2847         adjusted_mode = &crtc->config.adjusted_mode;
2848
2849         I915_WRITE(PIPESRC(crtc->pipe),
2850                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2851                    (adjusted_mode->crtc_vdisplay - 1));
2852         if (!crtc->config.pch_pfit.enabled &&
2853             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2854              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2855                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2856                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2857                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2858         }
2859         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2860         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2861 }
2862
2863 static int
2864 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2865                     struct drm_framebuffer *fb)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870         enum pipe pipe = intel_crtc->pipe;
2871         struct drm_framebuffer *old_fb = crtc->primary->fb;
2872         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2873         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2874         int ret;
2875
2876         if (intel_crtc_has_pending_flip(crtc)) {
2877                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2878                 return -EBUSY;
2879         }
2880
2881         /* no fb bound */
2882         if (!fb) {
2883                 DRM_ERROR("No FB bound\n");
2884                 return 0;
2885         }
2886
2887         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2888                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2889                           plane_name(intel_crtc->plane),
2890                           INTEL_INFO(dev)->num_pipes);
2891                 return -EINVAL;
2892         }
2893
2894         mutex_lock(&dev->struct_mutex);
2895         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2896         if (ret == 0)
2897                 i915_gem_track_fb(old_obj, obj,
2898                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2899         mutex_unlock(&dev->struct_mutex);
2900         if (ret != 0) {
2901                 DRM_ERROR("pin & fence failed\n");
2902                 return ret;
2903         }
2904
2905         intel_update_pipe_size(intel_crtc);
2906
2907         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2908
2909         if (intel_crtc->active)
2910                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2911
2912         crtc->primary->fb = fb;
2913         crtc->x = x;
2914         crtc->y = y;
2915
2916         if (old_fb) {
2917                 if (intel_crtc->active && old_fb != fb)
2918                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2919                 mutex_lock(&dev->struct_mutex);
2920                 intel_unpin_fb_obj(old_obj);
2921                 mutex_unlock(&dev->struct_mutex);
2922         }
2923
2924         mutex_lock(&dev->struct_mutex);
2925         intel_update_fbc(dev);
2926         mutex_unlock(&dev->struct_mutex);
2927
2928         return 0;
2929 }
2930
2931 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2932 {
2933         struct drm_device *dev = crtc->dev;
2934         struct drm_i915_private *dev_priv = dev->dev_private;
2935         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936         int pipe = intel_crtc->pipe;
2937         u32 reg, temp;
2938
2939         /* enable normal train */
2940         reg = FDI_TX_CTL(pipe);
2941         temp = I915_READ(reg);
2942         if (IS_IVYBRIDGE(dev)) {
2943                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2944                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2945         } else {
2946                 temp &= ~FDI_LINK_TRAIN_NONE;
2947                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2948         }
2949         I915_WRITE(reg, temp);
2950
2951         reg = FDI_RX_CTL(pipe);
2952         temp = I915_READ(reg);
2953         if (HAS_PCH_CPT(dev)) {
2954                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2955                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2956         } else {
2957                 temp &= ~FDI_LINK_TRAIN_NONE;
2958                 temp |= FDI_LINK_TRAIN_NONE;
2959         }
2960         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2961
2962         /* wait one idle pattern time */
2963         POSTING_READ(reg);
2964         udelay(1000);
2965
2966         /* IVB wants error correction enabled */
2967         if (IS_IVYBRIDGE(dev))
2968                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2969                            FDI_FE_ERRC_ENABLE);
2970 }
2971
2972 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2973 {
2974         return crtc->base.enabled && crtc->active &&
2975                 crtc->config.has_pch_encoder;
2976 }
2977
2978 static void ivb_modeset_global_resources(struct drm_device *dev)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         struct intel_crtc *pipe_B_crtc =
2982                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2983         struct intel_crtc *pipe_C_crtc =
2984                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2985         uint32_t temp;
2986
2987         /*
2988          * When everything is off disable fdi C so that we could enable fdi B
2989          * with all lanes. Note that we don't care about enabled pipes without
2990          * an enabled pch encoder.
2991          */
2992         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2993             !pipe_has_enabled_pch(pipe_C_crtc)) {
2994                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2995                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2996
2997                 temp = I915_READ(SOUTH_CHICKEN1);
2998                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2999                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3000                 I915_WRITE(SOUTH_CHICKEN1, temp);
3001         }
3002 }
3003
3004 /* The FDI link training functions for ILK/Ibexpeak. */
3005 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3006 {
3007         struct drm_device *dev = crtc->dev;
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010         int pipe = intel_crtc->pipe;
3011         u32 reg, temp, tries;
3012
3013         /* FDI needs bits from pipe first */
3014         assert_pipe_enabled(dev_priv, pipe);
3015
3016         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3017            for train result */
3018         reg = FDI_RX_IMR(pipe);
3019         temp = I915_READ(reg);
3020         temp &= ~FDI_RX_SYMBOL_LOCK;
3021         temp &= ~FDI_RX_BIT_LOCK;
3022         I915_WRITE(reg, temp);
3023         I915_READ(reg);
3024         udelay(150);
3025
3026         /* enable CPU FDI TX and PCH FDI RX */
3027         reg = FDI_TX_CTL(pipe);
3028         temp = I915_READ(reg);
3029         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3030         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3031         temp &= ~FDI_LINK_TRAIN_NONE;
3032         temp |= FDI_LINK_TRAIN_PATTERN_1;
3033         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3034
3035         reg = FDI_RX_CTL(pipe);
3036         temp = I915_READ(reg);
3037         temp &= ~FDI_LINK_TRAIN_NONE;
3038         temp |= FDI_LINK_TRAIN_PATTERN_1;
3039         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3040
3041         POSTING_READ(reg);
3042         udelay(150);
3043
3044         /* Ironlake workaround, enable clock pointer after FDI enable*/
3045         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3046         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3047                    FDI_RX_PHASE_SYNC_POINTER_EN);
3048
3049         reg = FDI_RX_IIR(pipe);
3050         for (tries = 0; tries < 5; tries++) {
3051                 temp = I915_READ(reg);
3052                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3053
3054                 if ((temp & FDI_RX_BIT_LOCK)) {
3055                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3056                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3057                         break;
3058                 }
3059         }
3060         if (tries == 5)
3061                 DRM_ERROR("FDI train 1 fail!\n");
3062
3063         /* Train 2 */
3064         reg = FDI_TX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         temp &= ~FDI_LINK_TRAIN_NONE;
3067         temp |= FDI_LINK_TRAIN_PATTERN_2;
3068         I915_WRITE(reg, temp);
3069
3070         reg = FDI_RX_CTL(pipe);
3071         temp = I915_READ(reg);
3072         temp &= ~FDI_LINK_TRAIN_NONE;
3073         temp |= FDI_LINK_TRAIN_PATTERN_2;
3074         I915_WRITE(reg, temp);
3075
3076         POSTING_READ(reg);
3077         udelay(150);
3078
3079         reg = FDI_RX_IIR(pipe);
3080         for (tries = 0; tries < 5; tries++) {
3081                 temp = I915_READ(reg);
3082                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3083
3084                 if (temp & FDI_RX_SYMBOL_LOCK) {
3085                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3086                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3087                         break;
3088                 }
3089         }
3090         if (tries == 5)
3091                 DRM_ERROR("FDI train 2 fail!\n");
3092
3093         DRM_DEBUG_KMS("FDI train done\n");
3094
3095 }
3096
3097 static const int snb_b_fdi_train_param[] = {
3098         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3099         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3100         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3101         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3102 };
3103
3104 /* The FDI link training functions for SNB/Cougarpoint. */
3105 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3106 {
3107         struct drm_device *dev = crtc->dev;
3108         struct drm_i915_private *dev_priv = dev->dev_private;
3109         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110         int pipe = intel_crtc->pipe;
3111         u32 reg, temp, i, retry;
3112
3113         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3114            for train result */
3115         reg = FDI_RX_IMR(pipe);
3116         temp = I915_READ(reg);
3117         temp &= ~FDI_RX_SYMBOL_LOCK;
3118         temp &= ~FDI_RX_BIT_LOCK;
3119         I915_WRITE(reg, temp);
3120
3121         POSTING_READ(reg);
3122         udelay(150);
3123
3124         /* enable CPU FDI TX and PCH FDI RX */
3125         reg = FDI_TX_CTL(pipe);
3126         temp = I915_READ(reg);
3127         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3128         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3129         temp &= ~FDI_LINK_TRAIN_NONE;
3130         temp |= FDI_LINK_TRAIN_PATTERN_1;
3131         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3132         /* SNB-B */
3133         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3134         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3135
3136         I915_WRITE(FDI_RX_MISC(pipe),
3137                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3138
3139         reg = FDI_RX_CTL(pipe);
3140         temp = I915_READ(reg);
3141         if (HAS_PCH_CPT(dev)) {
3142                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3143                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3144         } else {
3145                 temp &= ~FDI_LINK_TRAIN_NONE;
3146                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3147         }
3148         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(150);
3152
3153         for (i = 0; i < 4; i++) {
3154                 reg = FDI_TX_CTL(pipe);
3155                 temp = I915_READ(reg);
3156                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3157                 temp |= snb_b_fdi_train_param[i];
3158                 I915_WRITE(reg, temp);
3159
3160                 POSTING_READ(reg);
3161                 udelay(500);
3162
3163                 for (retry = 0; retry < 5; retry++) {
3164                         reg = FDI_RX_IIR(pipe);
3165                         temp = I915_READ(reg);
3166                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3167                         if (temp & FDI_RX_BIT_LOCK) {
3168                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3169                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3170                                 break;
3171                         }
3172                         udelay(50);
3173                 }
3174                 if (retry < 5)
3175                         break;
3176         }
3177         if (i == 4)
3178                 DRM_ERROR("FDI train 1 fail!\n");
3179
3180         /* Train 2 */
3181         reg = FDI_TX_CTL(pipe);
3182         temp = I915_READ(reg);
3183         temp &= ~FDI_LINK_TRAIN_NONE;
3184         temp |= FDI_LINK_TRAIN_PATTERN_2;
3185         if (IS_GEN6(dev)) {
3186                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3187                 /* SNB-B */
3188                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3189         }
3190         I915_WRITE(reg, temp);
3191
3192         reg = FDI_RX_CTL(pipe);
3193         temp = I915_READ(reg);
3194         if (HAS_PCH_CPT(dev)) {
3195                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3196                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3197         } else {
3198                 temp &= ~FDI_LINK_TRAIN_NONE;
3199                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3200         }
3201         I915_WRITE(reg, temp);
3202
3203         POSTING_READ(reg);
3204         udelay(150);
3205
3206         for (i = 0; i < 4; i++) {
3207                 reg = FDI_TX_CTL(pipe);
3208                 temp = I915_READ(reg);
3209                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3210                 temp |= snb_b_fdi_train_param[i];
3211                 I915_WRITE(reg, temp);
3212
3213                 POSTING_READ(reg);
3214                 udelay(500);
3215
3216                 for (retry = 0; retry < 5; retry++) {
3217                         reg = FDI_RX_IIR(pipe);
3218                         temp = I915_READ(reg);
3219                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3220                         if (temp & FDI_RX_SYMBOL_LOCK) {
3221                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3222                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3223                                 break;
3224                         }
3225                         udelay(50);
3226                 }
3227                 if (retry < 5)
3228                         break;
3229         }
3230         if (i == 4)
3231                 DRM_ERROR("FDI train 2 fail!\n");
3232
3233         DRM_DEBUG_KMS("FDI train done.\n");
3234 }
3235
3236 /* Manual link training for Ivy Bridge A0 parts */
3237 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3238 {
3239         struct drm_device *dev = crtc->dev;
3240         struct drm_i915_private *dev_priv = dev->dev_private;
3241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242         int pipe = intel_crtc->pipe;
3243         u32 reg, temp, i, j;
3244
3245         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3246            for train result */
3247         reg = FDI_RX_IMR(pipe);
3248         temp = I915_READ(reg);
3249         temp &= ~FDI_RX_SYMBOL_LOCK;
3250         temp &= ~FDI_RX_BIT_LOCK;
3251         I915_WRITE(reg, temp);
3252
3253         POSTING_READ(reg);
3254         udelay(150);
3255
3256         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3257                       I915_READ(FDI_RX_IIR(pipe)));
3258
3259         /* Try each vswing and preemphasis setting twice before moving on */
3260         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3261                 /* disable first in case we need to retry */
3262                 reg = FDI_TX_CTL(pipe);
3263                 temp = I915_READ(reg);
3264                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3265                 temp &= ~FDI_TX_ENABLE;
3266                 I915_WRITE(reg, temp);
3267
3268                 reg = FDI_RX_CTL(pipe);
3269                 temp = I915_READ(reg);
3270                 temp &= ~FDI_LINK_TRAIN_AUTO;
3271                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3272                 temp &= ~FDI_RX_ENABLE;
3273                 I915_WRITE(reg, temp);
3274
3275                 /* enable CPU FDI TX and PCH FDI RX */
3276                 reg = FDI_TX_CTL(pipe);
3277                 temp = I915_READ(reg);
3278                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3279                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3280                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3281                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3282                 temp |= snb_b_fdi_train_param[j/2];
3283                 temp |= FDI_COMPOSITE_SYNC;
3284                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3285
3286                 I915_WRITE(FDI_RX_MISC(pipe),
3287                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3288
3289                 reg = FDI_RX_CTL(pipe);
3290                 temp = I915_READ(reg);
3291                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3292                 temp |= FDI_COMPOSITE_SYNC;
3293                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3294
3295                 POSTING_READ(reg);
3296                 udelay(1); /* should be 0.5us */
3297
3298                 for (i = 0; i < 4; i++) {
3299                         reg = FDI_RX_IIR(pipe);
3300                         temp = I915_READ(reg);
3301                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3302
3303                         if (temp & FDI_RX_BIT_LOCK ||
3304                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3305                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3306                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3307                                               i);
3308                                 break;
3309                         }
3310                         udelay(1); /* should be 0.5us */
3311                 }
3312                 if (i == 4) {
3313                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3314                         continue;
3315                 }
3316
3317                 /* Train 2 */
3318                 reg = FDI_TX_CTL(pipe);
3319                 temp = I915_READ(reg);
3320                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3321                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3322                 I915_WRITE(reg, temp);
3323
3324                 reg = FDI_RX_CTL(pipe);
3325                 temp = I915_READ(reg);
3326                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3327                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3328                 I915_WRITE(reg, temp);
3329
3330                 POSTING_READ(reg);
3331                 udelay(2); /* should be 1.5us */
3332
3333                 for (i = 0; i < 4; i++) {
3334                         reg = FDI_RX_IIR(pipe);
3335                         temp = I915_READ(reg);
3336                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3337
3338                         if (temp & FDI_RX_SYMBOL_LOCK ||
3339                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3340                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3341                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3342                                               i);
3343                                 goto train_done;
3344                         }
3345                         udelay(2); /* should be 1.5us */
3346                 }
3347                 if (i == 4)
3348                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3349         }
3350
3351 train_done:
3352         DRM_DEBUG_KMS("FDI train done.\n");
3353 }
3354
3355 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3356 {
3357         struct drm_device *dev = intel_crtc->base.dev;
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         int pipe = intel_crtc->pipe;
3360         u32 reg, temp;
3361
3362
3363         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3364         reg = FDI_RX_CTL(pipe);
3365         temp = I915_READ(reg);
3366         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3367         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3368         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3369         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3370
3371         POSTING_READ(reg);
3372         udelay(200);
3373
3374         /* Switch from Rawclk to PCDclk */
3375         temp = I915_READ(reg);
3376         I915_WRITE(reg, temp | FDI_PCDCLK);
3377
3378         POSTING_READ(reg);
3379         udelay(200);
3380
3381         /* Enable CPU FDI TX PLL, always on for Ironlake */
3382         reg = FDI_TX_CTL(pipe);
3383         temp = I915_READ(reg);
3384         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3385                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3386
3387                 POSTING_READ(reg);
3388                 udelay(100);
3389         }
3390 }
3391
3392 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3393 {
3394         struct drm_device *dev = intel_crtc->base.dev;
3395         struct drm_i915_private *dev_priv = dev->dev_private;
3396         int pipe = intel_crtc->pipe;
3397         u32 reg, temp;
3398
3399         /* Switch from PCDclk to Rawclk */
3400         reg = FDI_RX_CTL(pipe);
3401         temp = I915_READ(reg);
3402         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3403
3404         /* Disable CPU FDI TX PLL */
3405         reg = FDI_TX_CTL(pipe);
3406         temp = I915_READ(reg);
3407         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3408
3409         POSTING_READ(reg);
3410         udelay(100);
3411
3412         reg = FDI_RX_CTL(pipe);
3413         temp = I915_READ(reg);
3414         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3415
3416         /* Wait for the clocks to turn off. */
3417         POSTING_READ(reg);
3418         udelay(100);
3419 }
3420
3421 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3422 {
3423         struct drm_device *dev = crtc->dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426         int pipe = intel_crtc->pipe;
3427         u32 reg, temp;
3428
3429         /* disable CPU FDI tx and PCH FDI rx */
3430         reg = FDI_TX_CTL(pipe);
3431         temp = I915_READ(reg);
3432         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3433         POSTING_READ(reg);
3434
3435         reg = FDI_RX_CTL(pipe);
3436         temp = I915_READ(reg);
3437         temp &= ~(0x7 << 16);
3438         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3439         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3440
3441         POSTING_READ(reg);
3442         udelay(100);
3443
3444         /* Ironlake workaround, disable clock pointer after downing FDI */
3445         if (HAS_PCH_IBX(dev))
3446                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447
3448         /* still set train pattern 1 */
3449         reg = FDI_TX_CTL(pipe);
3450         temp = I915_READ(reg);
3451         temp &= ~FDI_LINK_TRAIN_NONE;
3452         temp |= FDI_LINK_TRAIN_PATTERN_1;
3453         I915_WRITE(reg, temp);
3454
3455         reg = FDI_RX_CTL(pipe);
3456         temp = I915_READ(reg);
3457         if (HAS_PCH_CPT(dev)) {
3458                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3459                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3460         } else {
3461                 temp &= ~FDI_LINK_TRAIN_NONE;
3462                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3463         }
3464         /* BPC in FDI rx is consistent with that in PIPECONF */
3465         temp &= ~(0x07 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471 }
3472
3473 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3474 {
3475         struct intel_crtc *crtc;
3476
3477         /* Note that we don't need to be called with mode_config.lock here
3478          * as our list of CRTC objects is static for the lifetime of the
3479          * device and so cannot disappear as we iterate. Similarly, we can
3480          * happily treat the predicates as racy, atomic checks as userspace
3481          * cannot claim and pin a new fb without at least acquring the
3482          * struct_mutex and so serialising with us.
3483          */
3484         for_each_intel_crtc(dev, crtc) {
3485                 if (atomic_read(&crtc->unpin_work_count) == 0)
3486                         continue;
3487
3488                 if (crtc->unpin_work)
3489                         intel_wait_for_vblank(dev, crtc->pipe);
3490
3491                 return true;
3492         }
3493
3494         return false;
3495 }
3496
3497 static void page_flip_completed(struct intel_crtc *intel_crtc)
3498 {
3499         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3500         struct intel_unpin_work *work = intel_crtc->unpin_work;
3501
3502         /* ensure that the unpin work is consistent wrt ->pending. */
3503         smp_rmb();
3504         intel_crtc->unpin_work = NULL;
3505
3506         if (work->event)
3507                 drm_send_vblank_event(intel_crtc->base.dev,
3508                                       intel_crtc->pipe,
3509                                       work->event);
3510
3511         drm_crtc_vblank_put(&intel_crtc->base);
3512
3513         wake_up_all(&dev_priv->pending_flip_queue);
3514         queue_work(dev_priv->wq, &work->work);
3515
3516         trace_i915_flip_complete(intel_crtc->plane,
3517                                  work->pending_flip_obj);
3518 }
3519
3520 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3521 {
3522         struct drm_device *dev = crtc->dev;
3523         struct drm_i915_private *dev_priv = dev->dev_private;
3524
3525         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3526         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3527                                        !intel_crtc_has_pending_flip(crtc),
3528                                        60*HZ) == 0)) {
3529                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530
3531                 spin_lock_irq(&dev->event_lock);
3532                 if (intel_crtc->unpin_work) {
3533                         WARN_ONCE(1, "Removing stuck page flip\n");
3534                         page_flip_completed(intel_crtc);
3535                 }
3536                 spin_unlock_irq(&dev->event_lock);
3537         }
3538
3539         if (crtc->primary->fb) {
3540                 mutex_lock(&dev->struct_mutex);
3541                 intel_finish_fb(crtc->primary->fb);
3542                 mutex_unlock(&dev->struct_mutex);
3543         }
3544 }
3545
3546 /* Program iCLKIP clock to the desired frequency */
3547 static void lpt_program_iclkip(struct drm_crtc *crtc)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3552         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3553         u32 temp;
3554
3555         mutex_lock(&dev_priv->dpio_lock);
3556
3557         /* It is necessary to ungate the pixclk gate prior to programming
3558          * the divisors, and gate it back when it is done.
3559          */
3560         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3561
3562         /* Disable SSCCTL */
3563         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3564                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3565                                 SBI_SSCCTL_DISABLE,
3566                         SBI_ICLK);
3567
3568         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3569         if (clock == 20000) {
3570                 auxdiv = 1;
3571                 divsel = 0x41;
3572                 phaseinc = 0x20;
3573         } else {
3574                 /* The iCLK virtual clock root frequency is in MHz,
3575                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3576                  * divisors, it is necessary to divide one by another, so we
3577                  * convert the virtual clock precision to KHz here for higher
3578                  * precision.
3579                  */
3580                 u32 iclk_virtual_root_freq = 172800 * 1000;
3581                 u32 iclk_pi_range = 64;
3582                 u32 desired_divisor, msb_divisor_value, pi_value;
3583
3584                 desired_divisor = (iclk_virtual_root_freq / clock);
3585                 msb_divisor_value = desired_divisor / iclk_pi_range;
3586                 pi_value = desired_divisor % iclk_pi_range;
3587
3588                 auxdiv = 0;
3589                 divsel = msb_divisor_value - 2;
3590                 phaseinc = pi_value;
3591         }
3592
3593         /* This should not happen with any sane values */
3594         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3595                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3596         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3597                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3598
3599         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3600                         clock,
3601                         auxdiv,
3602                         divsel,
3603                         phasedir,
3604                         phaseinc);
3605
3606         /* Program SSCDIVINTPHASE6 */
3607         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3608         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3609         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3610         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3611         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3612         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3613         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3614         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3615
3616         /* Program SSCAUXDIV */
3617         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3618         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3619         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3620         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3621
3622         /* Enable modulator and associated divider */
3623         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3624         temp &= ~SBI_SSCCTL_DISABLE;
3625         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3626
3627         /* Wait for initialization time */
3628         udelay(24);
3629
3630         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3631
3632         mutex_unlock(&dev_priv->dpio_lock);
3633 }
3634
3635 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3636                                                 enum pipe pch_transcoder)
3637 {
3638         struct drm_device *dev = crtc->base.dev;
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3641
3642         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3643                    I915_READ(HTOTAL(cpu_transcoder)));
3644         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3645                    I915_READ(HBLANK(cpu_transcoder)));
3646         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3647                    I915_READ(HSYNC(cpu_transcoder)));
3648
3649         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3650                    I915_READ(VTOTAL(cpu_transcoder)));
3651         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3652                    I915_READ(VBLANK(cpu_transcoder)));
3653         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3654                    I915_READ(VSYNC(cpu_transcoder)));
3655         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3656                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3657 }
3658
3659 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3660 {
3661         struct drm_i915_private *dev_priv = dev->dev_private;
3662         uint32_t temp;
3663
3664         temp = I915_READ(SOUTH_CHICKEN1);
3665         if (temp & FDI_BC_BIFURCATION_SELECT)
3666                 return;
3667
3668         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3669         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3670
3671         temp |= FDI_BC_BIFURCATION_SELECT;
3672         DRM_DEBUG_KMS("enabling fdi C rx\n");
3673         I915_WRITE(SOUTH_CHICKEN1, temp);
3674         POSTING_READ(SOUTH_CHICKEN1);
3675 }
3676
3677 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3678 {
3679         struct drm_device *dev = intel_crtc->base.dev;
3680         struct drm_i915_private *dev_priv = dev->dev_private;
3681
3682         switch (intel_crtc->pipe) {
3683         case PIPE_A:
3684                 break;
3685         case PIPE_B:
3686                 if (intel_crtc->config.fdi_lanes > 2)
3687                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3688                 else
3689                         cpt_enable_fdi_bc_bifurcation(dev);
3690
3691                 break;
3692         case PIPE_C:
3693                 cpt_enable_fdi_bc_bifurcation(dev);
3694
3695                 break;
3696         default:
3697                 BUG();
3698         }
3699 }
3700
3701 /*
3702  * Enable PCH resources required for PCH ports:
3703  *   - PCH PLLs
3704  *   - FDI training & RX/TX
3705  *   - update transcoder timings
3706  *   - DP transcoding bits
3707  *   - transcoder
3708  */
3709 static void ironlake_pch_enable(struct drm_crtc *crtc)
3710 {
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714         int pipe = intel_crtc->pipe;
3715         u32 reg, temp;
3716
3717         assert_pch_transcoder_disabled(dev_priv, pipe);
3718
3719         if (IS_IVYBRIDGE(dev))
3720                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3721
3722         /* Write the TU size bits before fdi link training, so that error
3723          * detection works. */
3724         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3725                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3726
3727         /* For PCH output, training FDI link */
3728         dev_priv->display.fdi_link_train(crtc);
3729
3730         /* We need to program the right clock selection before writing the pixel
3731          * mutliplier into the DPLL. */
3732         if (HAS_PCH_CPT(dev)) {
3733                 u32 sel;
3734
3735                 temp = I915_READ(PCH_DPLL_SEL);
3736                 temp |= TRANS_DPLL_ENABLE(pipe);
3737                 sel = TRANS_DPLLB_SEL(pipe);
3738                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3739                         temp |= sel;
3740                 else
3741                         temp &= ~sel;
3742                 I915_WRITE(PCH_DPLL_SEL, temp);
3743         }
3744
3745         /* XXX: pch pll's can be enabled any time before we enable the PCH
3746          * transcoder, and we actually should do this to not upset any PCH
3747          * transcoder that already use the clock when we share it.
3748          *
3749          * Note that enable_shared_dpll tries to do the right thing, but
3750          * get_shared_dpll unconditionally resets the pll - we need that to have
3751          * the right LVDS enable sequence. */
3752         intel_enable_shared_dpll(intel_crtc);
3753
3754         /* set transcoder timing, panel must allow it */
3755         assert_panel_unlocked(dev_priv, pipe);
3756         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3757
3758         intel_fdi_normal_train(crtc);
3759
3760         /* For PCH DP, enable TRANS_DP_CTL */
3761         if (HAS_PCH_CPT(dev) &&
3762             (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3763              intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
3764                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3765                 reg = TRANS_DP_CTL(pipe);
3766                 temp = I915_READ(reg);
3767                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3768                           TRANS_DP_SYNC_MASK |
3769                           TRANS_DP_BPC_MASK);
3770                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3771                          TRANS_DP_ENH_FRAMING);
3772                 temp |= bpc << 9; /* same format but at 11:9 */
3773
3774                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3775                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3776                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3777                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3778
3779                 switch (intel_trans_dp_port_sel(crtc)) {
3780                 case PCH_DP_B:
3781                         temp |= TRANS_DP_PORT_SEL_B;
3782                         break;
3783                 case PCH_DP_C:
3784                         temp |= TRANS_DP_PORT_SEL_C;
3785                         break;
3786                 case PCH_DP_D:
3787                         temp |= TRANS_DP_PORT_SEL_D;
3788                         break;
3789                 default:
3790                         BUG();
3791                 }
3792
3793                 I915_WRITE(reg, temp);
3794         }
3795
3796         ironlake_enable_pch_transcoder(dev_priv, pipe);
3797 }
3798
3799 static void lpt_pch_enable(struct drm_crtc *crtc)
3800 {
3801         struct drm_device *dev = crtc->dev;
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3805
3806         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3807
3808         lpt_program_iclkip(crtc);
3809
3810         /* Set transcoder timing. */
3811         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3812
3813         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3814 }
3815
3816 void intel_put_shared_dpll(struct intel_crtc *crtc)
3817 {
3818         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3819
3820         if (pll == NULL)
3821                 return;
3822
3823         if (pll->refcount == 0) {
3824                 WARN(1, "bad %s refcount\n", pll->name);
3825                 return;
3826         }
3827
3828         if (--pll->refcount == 0) {
3829                 WARN_ON(pll->on);
3830                 WARN_ON(pll->active);
3831         }
3832
3833         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3834 }
3835
3836 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3837 {
3838         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3839         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3840         enum intel_dpll_id i;
3841
3842         if (pll) {
3843                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3844                               crtc->base.base.id, pll->name);
3845                 intel_put_shared_dpll(crtc);
3846         }
3847
3848         if (HAS_PCH_IBX(dev_priv->dev)) {
3849                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3850                 i = (enum intel_dpll_id) crtc->pipe;
3851                 pll = &dev_priv->shared_dplls[i];
3852
3853                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3854                               crtc->base.base.id, pll->name);
3855
3856                 WARN_ON(pll->refcount);
3857
3858                 goto found;
3859         }
3860
3861         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3862                 pll = &dev_priv->shared_dplls[i];
3863
3864                 /* Only want to check enabled timings first */
3865                 if (pll->refcount == 0)
3866                         continue;
3867
3868                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3869                            sizeof(pll->hw_state)) == 0) {
3870                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3871                                       crtc->base.base.id,
3872                                       pll->name, pll->refcount, pll->active);
3873
3874                         goto found;
3875                 }
3876         }
3877
3878         /* Ok no matching timings, maybe there's a free one? */
3879         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3880                 pll = &dev_priv->shared_dplls[i];
3881                 if (pll->refcount == 0) {
3882                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3883                                       crtc->base.base.id, pll->name);
3884                         goto found;
3885                 }
3886         }
3887
3888         return NULL;
3889
3890 found:
3891         if (pll->refcount == 0)
3892                 pll->hw_state = crtc->config.dpll_hw_state;
3893
3894         crtc->config.shared_dpll = i;
3895         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3896                          pipe_name(crtc->pipe));
3897
3898         pll->refcount++;
3899
3900         return pll;
3901 }
3902
3903 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3904 {
3905         struct drm_i915_private *dev_priv = dev->dev_private;
3906         int dslreg = PIPEDSL(pipe);
3907         u32 temp;
3908
3909         temp = I915_READ(dslreg);
3910         udelay(500);
3911         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3912                 if (wait_for(I915_READ(dslreg) != temp, 5))
3913                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3914         }
3915 }
3916
3917 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3918 {
3919         struct drm_device *dev = crtc->base.dev;
3920         struct drm_i915_private *dev_priv = dev->dev_private;
3921         int pipe = crtc->pipe;
3922
3923         if (crtc->config.pch_pfit.enabled) {
3924                 /* Force use of hard-coded filter coefficients
3925                  * as some pre-programmed values are broken,
3926                  * e.g. x201.
3927                  */
3928                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3929                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3930                                                  PF_PIPE_SEL_IVB(pipe));
3931                 else
3932                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3933                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3934                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3935         }
3936 }
3937
3938 static void intel_enable_planes(struct drm_crtc *crtc)
3939 {
3940         struct drm_device *dev = crtc->dev;
3941         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3942         struct drm_plane *plane;
3943         struct intel_plane *intel_plane;
3944
3945         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3946                 intel_plane = to_intel_plane(plane);
3947                 if (intel_plane->pipe == pipe)
3948                         intel_plane_restore(&intel_plane->base);
3949         }
3950 }
3951
3952 static void intel_disable_planes(struct drm_crtc *crtc)
3953 {
3954         struct drm_device *dev = crtc->dev;
3955         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3956         struct drm_plane *plane;
3957         struct intel_plane *intel_plane;
3958
3959         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3960                 intel_plane = to_intel_plane(plane);
3961                 if (intel_plane->pipe == pipe)
3962                         intel_plane_disable(&intel_plane->base);
3963         }
3964 }
3965
3966 void hsw_enable_ips(struct intel_crtc *crtc)
3967 {
3968         struct drm_device *dev = crtc->base.dev;
3969         struct drm_i915_private *dev_priv = dev->dev_private;
3970
3971         if (!crtc->config.ips_enabled)
3972                 return;
3973
3974         /* We can only enable IPS after we enable a plane and wait for a vblank */
3975         intel_wait_for_vblank(dev, crtc->pipe);
3976
3977         assert_plane_enabled(dev_priv, crtc->plane);
3978         if (IS_BROADWELL(dev)) {
3979                 mutex_lock(&dev_priv->rps.hw_lock);
3980                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3981                 mutex_unlock(&dev_priv->rps.hw_lock);
3982                 /* Quoting Art Runyan: "its not safe to expect any particular
3983                  * value in IPS_CTL bit 31 after enabling IPS through the
3984                  * mailbox." Moreover, the mailbox may return a bogus state,
3985                  * so we need to just enable it and continue on.
3986                  */
3987         } else {
3988                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3989                 /* The bit only becomes 1 in the next vblank, so this wait here
3990                  * is essentially intel_wait_for_vblank. If we don't have this
3991                  * and don't wait for vblanks until the end of crtc_enable, then
3992                  * the HW state readout code will complain that the expected
3993                  * IPS_CTL value is not the one we read. */
3994                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3995                         DRM_ERROR("Timed out waiting for IPS enable\n");
3996         }
3997 }
3998
3999 void hsw_disable_ips(struct intel_crtc *crtc)
4000 {
4001         struct drm_device *dev = crtc->base.dev;
4002         struct drm_i915_private *dev_priv = dev->dev_private;
4003
4004         if (!crtc->config.ips_enabled)
4005                 return;
4006
4007         assert_plane_enabled(dev_priv, crtc->plane);
4008         if (IS_BROADWELL(dev)) {
4009                 mutex_lock(&dev_priv->rps.hw_lock);
4010                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4011                 mutex_unlock(&dev_priv->rps.hw_lock);
4012                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4013                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4014                         DRM_ERROR("Timed out waiting for IPS disable\n");
4015         } else {
4016                 I915_WRITE(IPS_CTL, 0);
4017                 POSTING_READ(IPS_CTL);
4018         }
4019
4020         /* We need to wait for a vblank before we can disable the plane. */
4021         intel_wait_for_vblank(dev, crtc->pipe);
4022 }
4023
4024 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4025 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4026 {
4027         struct drm_device *dev = crtc->dev;
4028         struct drm_i915_private *dev_priv = dev->dev_private;
4029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4030         enum pipe pipe = intel_crtc->pipe;
4031         int palreg = PALETTE(pipe);
4032         int i;
4033         bool reenable_ips = false;
4034
4035         /* The clocks have to be on to load the palette. */
4036         if (!crtc->enabled || !intel_crtc->active)
4037                 return;
4038
4039         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4040                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4041                         assert_dsi_pll_enabled(dev_priv);
4042                 else
4043                         assert_pll_enabled(dev_priv, pipe);
4044         }
4045
4046         /* use legacy palette for Ironlake */
4047         if (!HAS_GMCH_DISPLAY(dev))
4048                 palreg = LGC_PALETTE(pipe);
4049
4050         /* Workaround : Do not read or write the pipe palette/gamma data while
4051          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4052          */
4053         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4054             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4055              GAMMA_MODE_MODE_SPLIT)) {
4056                 hsw_disable_ips(intel_crtc);
4057                 reenable_ips = true;
4058         }
4059
4060         for (i = 0; i < 256; i++) {
4061                 I915_WRITE(palreg + 4 * i,
4062                            (intel_crtc->lut_r[i] << 16) |
4063                            (intel_crtc->lut_g[i] << 8) |
4064                            intel_crtc->lut_b[i]);
4065         }
4066
4067         if (reenable_ips)
4068                 hsw_enable_ips(intel_crtc);
4069 }
4070
4071 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4072 {
4073         if (!enable && intel_crtc->overlay) {
4074                 struct drm_device *dev = intel_crtc->base.dev;
4075                 struct drm_i915_private *dev_priv = dev->dev_private;
4076
4077                 mutex_lock(&dev->struct_mutex);
4078                 dev_priv->mm.interruptible = false;
4079                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4080                 dev_priv->mm.interruptible = true;
4081                 mutex_unlock(&dev->struct_mutex);
4082         }
4083
4084         /* Let userspace switch the overlay on again. In most cases userspace
4085          * has to recompute where to put it anyway.
4086          */
4087 }
4088
4089 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4090 {
4091         struct drm_device *dev = crtc->dev;
4092         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093         int pipe = intel_crtc->pipe;
4094
4095         intel_enable_primary_hw_plane(crtc->primary, crtc);
4096         intel_enable_planes(crtc);
4097         intel_crtc_update_cursor(crtc, true);
4098         intel_crtc_dpms_overlay(intel_crtc, true);
4099
4100         hsw_enable_ips(intel_crtc);
4101
4102         mutex_lock(&dev->struct_mutex);
4103         intel_update_fbc(dev);
4104         mutex_unlock(&dev->struct_mutex);
4105
4106         /*
4107          * FIXME: Once we grow proper nuclear flip support out of this we need
4108          * to compute the mask of flip planes precisely. For the time being
4109          * consider this a flip from a NULL plane.
4110          */
4111         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4112 }
4113
4114 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         int pipe = intel_crtc->pipe;
4120         int plane = intel_crtc->plane;
4121
4122         intel_crtc_wait_for_pending_flips(crtc);
4123
4124         if (dev_priv->fbc.plane == plane)
4125                 intel_disable_fbc(dev);
4126
4127         hsw_disable_ips(intel_crtc);
4128
4129         intel_crtc_dpms_overlay(intel_crtc, false);
4130         intel_crtc_update_cursor(crtc, false);
4131         intel_disable_planes(crtc);
4132         intel_disable_primary_hw_plane(crtc->primary, crtc);
4133
4134         /*
4135          * FIXME: Once we grow proper nuclear flip support out of this we need
4136          * to compute the mask of flip planes precisely. For the time being
4137          * consider this a flip to a NULL plane.
4138          */
4139         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4140 }
4141
4142 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4143 {
4144         struct drm_device *dev = crtc->dev;
4145         struct drm_i915_private *dev_priv = dev->dev_private;
4146         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4147         struct intel_encoder *encoder;
4148         int pipe = intel_crtc->pipe;
4149
4150         WARN_ON(!crtc->enabled);
4151
4152         if (intel_crtc->active)
4153                 return;
4154
4155         if (intel_crtc->config.has_pch_encoder)
4156                 intel_prepare_shared_dpll(intel_crtc);
4157
4158         if (intel_crtc->config.has_dp_encoder)
4159                 intel_dp_set_m_n(intel_crtc);
4160
4161         intel_set_pipe_timings(intel_crtc);
4162
4163         if (intel_crtc->config.has_pch_encoder) {
4164                 intel_cpu_transcoder_set_m_n(intel_crtc,
4165                                      &intel_crtc->config.fdi_m_n, NULL);
4166         }
4167
4168         ironlake_set_pipeconf(crtc);
4169
4170         intel_crtc->active = true;
4171
4172         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4173         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->pre_enable)
4177                         encoder->pre_enable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 /* Note: FDI PLL enabling _must_ be done before we enable the
4181                  * cpu pipes, hence this is separate from all the other fdi/pch
4182                  * enabling. */
4183                 ironlake_fdi_pll_enable(intel_crtc);
4184         } else {
4185                 assert_fdi_tx_disabled(dev_priv, pipe);
4186                 assert_fdi_rx_disabled(dev_priv, pipe);
4187         }
4188
4189         ironlake_pfit_enable(intel_crtc);
4190
4191         /*
4192          * On ILK+ LUT must be loaded before the pipe is running but with
4193          * clocks enabled
4194          */
4195         intel_crtc_load_lut(crtc);
4196
4197         intel_update_watermarks(crtc);
4198         intel_enable_pipe(intel_crtc);
4199
4200         if (intel_crtc->config.has_pch_encoder)
4201                 ironlake_pch_enable(crtc);
4202
4203         for_each_encoder_on_crtc(dev, crtc, encoder)
4204                 encoder->enable(encoder);
4205
4206         if (HAS_PCH_CPT(dev))
4207                 cpt_verify_modeset(dev, intel_crtc->pipe);
4208
4209         assert_vblank_disabled(crtc);
4210         drm_crtc_vblank_on(crtc);
4211
4212         intel_crtc_enable_planes(crtc);
4213 }
4214
4215 /* IPS only exists on ULT machines and is tied to pipe A. */
4216 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4217 {
4218         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4219 }
4220
4221 /*
4222  * This implements the workaround described in the "notes" section of the mode
4223  * set sequence documentation. When going from no pipes or single pipe to
4224  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4225  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4226  */
4227 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4228 {
4229         struct drm_device *dev = crtc->base.dev;
4230         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4231
4232         /* We want to get the other_active_crtc only if there's only 1 other
4233          * active crtc. */
4234         for_each_intel_crtc(dev, crtc_it) {
4235                 if (!crtc_it->active || crtc_it == crtc)
4236                         continue;
4237
4238                 if (other_active_crtc)
4239                         return;
4240
4241                 other_active_crtc = crtc_it;
4242         }
4243         if (!other_active_crtc)
4244                 return;
4245
4246         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4247         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4248 }
4249
4250 static void haswell_crtc_enable(struct drm_crtc *crtc)
4251 {
4252         struct drm_device *dev = crtc->dev;
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4255         struct intel_encoder *encoder;
4256         int pipe = intel_crtc->pipe;
4257
4258         WARN_ON(!crtc->enabled);
4259
4260         if (intel_crtc->active)
4261                 return;
4262
4263         if (intel_crtc_to_shared_dpll(intel_crtc))
4264                 intel_enable_shared_dpll(intel_crtc);
4265
4266         if (intel_crtc->config.has_dp_encoder)
4267                 intel_dp_set_m_n(intel_crtc);
4268
4269         intel_set_pipe_timings(intel_crtc);
4270
4271         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4272                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4273                            intel_crtc->config.pixel_multiplier - 1);
4274         }
4275
4276         if (intel_crtc->config.has_pch_encoder) {
4277                 intel_cpu_transcoder_set_m_n(intel_crtc,
4278                                      &intel_crtc->config.fdi_m_n, NULL);
4279         }
4280
4281         haswell_set_pipeconf(crtc);
4282
4283         intel_set_pipe_csc(crtc);
4284
4285         intel_crtc->active = true;
4286
4287         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4288         for_each_encoder_on_crtc(dev, crtc, encoder)
4289                 if (encoder->pre_enable)
4290                         encoder->pre_enable(encoder);
4291
4292         if (intel_crtc->config.has_pch_encoder) {
4293                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4294                                                       true);
4295                 dev_priv->display.fdi_link_train(crtc);
4296         }
4297
4298         intel_ddi_enable_pipe_clock(intel_crtc);
4299
4300         ironlake_pfit_enable(intel_crtc);
4301
4302         /*
4303          * On ILK+ LUT must be loaded before the pipe is running but with
4304          * clocks enabled
4305          */
4306         intel_crtc_load_lut(crtc);
4307
4308         intel_ddi_set_pipe_settings(crtc);
4309         intel_ddi_enable_transcoder_func(crtc);
4310
4311         intel_update_watermarks(crtc);
4312         intel_enable_pipe(intel_crtc);
4313
4314         if (intel_crtc->config.has_pch_encoder)
4315                 lpt_pch_enable(crtc);
4316
4317         if (intel_crtc->config.dp_encoder_is_mst)
4318                 intel_ddi_set_vc_payload_alloc(crtc, true);
4319
4320         for_each_encoder_on_crtc(dev, crtc, encoder) {
4321                 encoder->enable(encoder);
4322                 intel_opregion_notify_encoder(encoder, true);
4323         }
4324
4325         assert_vblank_disabled(crtc);
4326         drm_crtc_vblank_on(crtc);
4327
4328         /* If we change the relative order between pipe/planes enabling, we need
4329          * to change the workaround. */
4330         haswell_mode_set_planes_workaround(intel_crtc);
4331         intel_crtc_enable_planes(crtc);
4332 }
4333
4334 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4335 {
4336         struct drm_device *dev = crtc->base.dev;
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338         int pipe = crtc->pipe;
4339
4340         /* To avoid upsetting the power well on haswell only disable the pfit if
4341          * it's in use. The hw state code will make sure we get this right. */
4342         if (crtc->config.pch_pfit.enabled) {
4343                 I915_WRITE(PF_CTL(pipe), 0);
4344                 I915_WRITE(PF_WIN_POS(pipe), 0);
4345                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4346         }
4347 }
4348
4349 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4350 {
4351         struct drm_device *dev = crtc->dev;
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354         struct intel_encoder *encoder;
4355         int pipe = intel_crtc->pipe;
4356         u32 reg, temp;
4357
4358         if (!intel_crtc->active)
4359                 return;
4360
4361         intel_crtc_disable_planes(crtc);
4362
4363         drm_crtc_vblank_off(crtc);
4364         assert_vblank_disabled(crtc);
4365
4366         for_each_encoder_on_crtc(dev, crtc, encoder)
4367                 encoder->disable(encoder);
4368
4369         if (intel_crtc->config.has_pch_encoder)
4370                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4371
4372         intel_disable_pipe(intel_crtc);
4373
4374         ironlake_pfit_disable(intel_crtc);
4375
4376         for_each_encoder_on_crtc(dev, crtc, encoder)
4377                 if (encoder->post_disable)
4378                         encoder->post_disable(encoder);
4379
4380         if (intel_crtc->config.has_pch_encoder) {
4381                 ironlake_fdi_disable(crtc);
4382
4383                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4384                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4385
4386                 if (HAS_PCH_CPT(dev)) {
4387                         /* disable TRANS_DP_CTL */
4388                         reg = TRANS_DP_CTL(pipe);
4389                         temp = I915_READ(reg);
4390                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4391                                   TRANS_DP_PORT_SEL_MASK);
4392                         temp |= TRANS_DP_PORT_SEL_NONE;
4393                         I915_WRITE(reg, temp);
4394
4395                         /* disable DPLL_SEL */
4396                         temp = I915_READ(PCH_DPLL_SEL);
4397                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4398                         I915_WRITE(PCH_DPLL_SEL, temp);
4399                 }
4400
4401                 /* disable PCH DPLL */
4402                 intel_disable_shared_dpll(intel_crtc);
4403
4404                 ironlake_fdi_pll_disable(intel_crtc);
4405         }
4406
4407         intel_crtc->active = false;
4408         intel_update_watermarks(crtc);
4409
4410         mutex_lock(&dev->struct_mutex);
4411         intel_update_fbc(dev);
4412         mutex_unlock(&dev->struct_mutex);
4413 }
4414
4415 static void haswell_crtc_disable(struct drm_crtc *crtc)
4416 {
4417         struct drm_device *dev = crtc->dev;
4418         struct drm_i915_private *dev_priv = dev->dev_private;
4419         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4420         struct intel_encoder *encoder;
4421         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4422
4423         if (!intel_crtc->active)
4424                 return;
4425
4426         intel_crtc_disable_planes(crtc);
4427
4428         drm_crtc_vblank_off(crtc);
4429         assert_vblank_disabled(crtc);
4430
4431         for_each_encoder_on_crtc(dev, crtc, encoder) {
4432                 intel_opregion_notify_encoder(encoder, false);
4433                 encoder->disable(encoder);
4434         }
4435
4436         if (intel_crtc->config.has_pch_encoder)
4437                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4438                                                       false);
4439         intel_disable_pipe(intel_crtc);
4440
4441         if (intel_crtc->config.dp_encoder_is_mst)
4442                 intel_ddi_set_vc_payload_alloc(crtc, false);
4443
4444         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4445
4446         ironlake_pfit_disable(intel_crtc);
4447
4448         intel_ddi_disable_pipe_clock(intel_crtc);
4449
4450         if (intel_crtc->config.has_pch_encoder) {
4451                 lpt_disable_pch_transcoder(dev_priv);
4452                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4453                                                       true);
4454                 intel_ddi_fdi_disable(crtc);
4455         }
4456
4457         for_each_encoder_on_crtc(dev, crtc, encoder)
4458                 if (encoder->post_disable)
4459                         encoder->post_disable(encoder);
4460
4461         intel_crtc->active = false;
4462         intel_update_watermarks(crtc);
4463
4464         mutex_lock(&dev->struct_mutex);
4465         intel_update_fbc(dev);
4466         mutex_unlock(&dev->struct_mutex);
4467
4468         if (intel_crtc_to_shared_dpll(intel_crtc))
4469                 intel_disable_shared_dpll(intel_crtc);
4470 }
4471
4472 static void ironlake_crtc_off(struct drm_crtc *crtc)
4473 {
4474         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4475         intel_put_shared_dpll(intel_crtc);
4476 }
4477
4478
4479 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4480 {
4481         struct drm_device *dev = crtc->base.dev;
4482         struct drm_i915_private *dev_priv = dev->dev_private;
4483         struct intel_crtc_config *pipe_config = &crtc->config;
4484
4485         if (!crtc->config.gmch_pfit.control)
4486                 return;
4487
4488         /*
4489          * The panel fitter should only be adjusted whilst the pipe is disabled,
4490          * according to register description and PRM.
4491          */
4492         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4493         assert_pipe_disabled(dev_priv, crtc->pipe);
4494
4495         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4496         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4497
4498         /* Border color in case we don't scale up to the full screen. Black by
4499          * default, change to something else for debugging. */
4500         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4501 }
4502
4503 static enum intel_display_power_domain port_to_power_domain(enum port port)
4504 {
4505         switch (port) {
4506         case PORT_A:
4507                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4508         case PORT_B:
4509                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4510         case PORT_C:
4511                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4512         case PORT_D:
4513                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4514         default:
4515                 WARN_ON_ONCE(1);
4516                 return POWER_DOMAIN_PORT_OTHER;
4517         }
4518 }
4519
4520 #define for_each_power_domain(domain, mask)                             \
4521         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4522                 if ((1 << (domain)) & (mask))
4523
4524 enum intel_display_power_domain
4525 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4526 {
4527         struct drm_device *dev = intel_encoder->base.dev;
4528         struct intel_digital_port *intel_dig_port;
4529
4530         switch (intel_encoder->type) {
4531         case INTEL_OUTPUT_UNKNOWN:
4532                 /* Only DDI platforms should ever use this output type */
4533                 WARN_ON_ONCE(!HAS_DDI(dev));
4534         case INTEL_OUTPUT_DISPLAYPORT:
4535         case INTEL_OUTPUT_HDMI:
4536         case INTEL_OUTPUT_EDP:
4537                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4538                 return port_to_power_domain(intel_dig_port->port);
4539         case INTEL_OUTPUT_DP_MST:
4540                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4541                 return port_to_power_domain(intel_dig_port->port);
4542         case INTEL_OUTPUT_ANALOG:
4543                 return POWER_DOMAIN_PORT_CRT;
4544         case INTEL_OUTPUT_DSI:
4545                 return POWER_DOMAIN_PORT_DSI;
4546         default:
4547                 return POWER_DOMAIN_PORT_OTHER;
4548         }
4549 }
4550
4551 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4552 {
4553         struct drm_device *dev = crtc->dev;
4554         struct intel_encoder *intel_encoder;
4555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556         enum pipe pipe = intel_crtc->pipe;
4557         unsigned long mask;
4558         enum transcoder transcoder;
4559
4560         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4561
4562         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4563         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4564         if (intel_crtc->config.pch_pfit.enabled ||
4565             intel_crtc->config.pch_pfit.force_thru)
4566                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4567
4568         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4569                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4570
4571         return mask;
4572 }
4573
4574 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4575 {
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4578         struct intel_crtc *crtc;
4579
4580         /*
4581          * First get all needed power domains, then put all unneeded, to avoid
4582          * any unnecessary toggling of the power wells.
4583          */
4584         for_each_intel_crtc(dev, crtc) {
4585                 enum intel_display_power_domain domain;
4586
4587                 if (!crtc->base.enabled)
4588                         continue;
4589
4590                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4591
4592                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4593                         intel_display_power_get(dev_priv, domain);
4594         }
4595
4596         for_each_intel_crtc(dev, crtc) {
4597                 enum intel_display_power_domain domain;
4598
4599                 for_each_power_domain(domain, crtc->enabled_power_domains)
4600                         intel_display_power_put(dev_priv, domain);
4601
4602                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4603         }
4604
4605         intel_display_set_init_power(dev_priv, false);
4606 }
4607
4608 /* returns HPLL frequency in kHz */
4609 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4610 {
4611         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4612
4613         /* Obtain SKU information */
4614         mutex_lock(&dev_priv->dpio_lock);
4615         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4616                 CCK_FUSE_HPLL_FREQ_MASK;
4617         mutex_unlock(&dev_priv->dpio_lock);
4618
4619         return vco_freq[hpll_freq] * 1000;
4620 }
4621
4622 static void vlv_update_cdclk(struct drm_device *dev)
4623 {
4624         struct drm_i915_private *dev_priv = dev->dev_private;
4625
4626         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4627         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4628                          dev_priv->vlv_cdclk_freq);
4629
4630         /*
4631          * Program the gmbus_freq based on the cdclk frequency.
4632          * BSpec erroneously claims we should aim for 4MHz, but
4633          * in fact 1MHz is the correct frequency.
4634          */
4635         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4636 }
4637
4638 /* Adjust CDclk dividers to allow high res or save power if possible */
4639 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4640 {
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         u32 val, cmd;
4643
4644         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4645
4646         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4647                 cmd = 2;
4648         else if (cdclk == 266667)
4649                 cmd = 1;
4650         else
4651                 cmd = 0;
4652
4653         mutex_lock(&dev_priv->rps.hw_lock);
4654         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4655         val &= ~DSPFREQGUAR_MASK;
4656         val |= (cmd << DSPFREQGUAR_SHIFT);
4657         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4658         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4659                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4660                      50)) {
4661                 DRM_ERROR("timed out waiting for CDclk change\n");
4662         }
4663         mutex_unlock(&dev_priv->rps.hw_lock);
4664
4665         if (cdclk == 400000) {
4666                 u32 divider, vco;
4667
4668                 vco = valleyview_get_vco(dev_priv);
4669                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4670
4671                 mutex_lock(&dev_priv->dpio_lock);
4672                 /* adjust cdclk divider */
4673                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4674                 val &= ~DISPLAY_FREQUENCY_VALUES;
4675                 val |= divider;
4676                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4677
4678                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4679                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4680                              50))
4681                         DRM_ERROR("timed out waiting for CDclk change\n");
4682                 mutex_unlock(&dev_priv->dpio_lock);
4683         }
4684
4685         mutex_lock(&dev_priv->dpio_lock);
4686         /* adjust self-refresh exit latency value */
4687         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4688         val &= ~0x7f;
4689
4690         /*
4691          * For high bandwidth configs, we set a higher latency in the bunit
4692          * so that the core display fetch happens in time to avoid underruns.
4693          */
4694         if (cdclk == 400000)
4695                 val |= 4500 / 250; /* 4.5 usec */
4696         else
4697                 val |= 3000 / 250; /* 3.0 usec */
4698         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4699         mutex_unlock(&dev_priv->dpio_lock);
4700
4701         vlv_update_cdclk(dev);
4702 }
4703
4704 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4705 {
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707         u32 val, cmd;
4708
4709         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4710
4711         switch (cdclk) {
4712         case 400000:
4713                 cmd = 3;
4714                 break;
4715         case 333333:
4716         case 320000:
4717                 cmd = 2;
4718                 break;
4719         case 266667:
4720                 cmd = 1;
4721                 break;
4722         case 200000:
4723                 cmd = 0;
4724                 break;
4725         default:
4726                 WARN_ON(1);
4727                 return;
4728         }
4729
4730         mutex_lock(&dev_priv->rps.hw_lock);
4731         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4732         val &= ~DSPFREQGUAR_MASK_CHV;
4733         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4734         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4735         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4736                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4737                      50)) {
4738                 DRM_ERROR("timed out waiting for CDclk change\n");
4739         }
4740         mutex_unlock(&dev_priv->rps.hw_lock);
4741
4742         vlv_update_cdclk(dev);
4743 }
4744
4745 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4746                                  int max_pixclk)
4747 {
4748         int vco = valleyview_get_vco(dev_priv);
4749         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4750
4751         /* FIXME: Punit isn't quite ready yet */
4752         if (IS_CHERRYVIEW(dev_priv->dev))
4753                 return 400000;
4754
4755         /*
4756          * Really only a few cases to deal with, as only 4 CDclks are supported:
4757          *   200MHz
4758          *   267MHz
4759          *   320/333MHz (depends on HPLL freq)
4760          *   400MHz
4761          * So we check to see whether we're above 90% of the lower bin and
4762          * adjust if needed.
4763          *
4764          * We seem to get an unstable or solid color picture at 200MHz.
4765          * Not sure what's wrong. For now use 200MHz only when all pipes
4766          * are off.
4767          */
4768         if (max_pixclk > freq_320*9/10)
4769                 return 400000;
4770         else if (max_pixclk > 266667*9/10)
4771                 return freq_320;
4772         else if (max_pixclk > 0)
4773                 return 266667;
4774         else
4775                 return 200000;
4776 }
4777
4778 /* compute the max pixel clock for new configuration */
4779 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4780 {
4781         struct drm_device *dev = dev_priv->dev;
4782         struct intel_crtc *intel_crtc;
4783         int max_pixclk = 0;
4784
4785         for_each_intel_crtc(dev, intel_crtc) {
4786                 if (intel_crtc->new_enabled)
4787                         max_pixclk = max(max_pixclk,
4788                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4789         }
4790
4791         return max_pixclk;
4792 }
4793
4794 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4795                                             unsigned *prepare_pipes)
4796 {
4797         struct drm_i915_private *dev_priv = dev->dev_private;
4798         struct intel_crtc *intel_crtc;
4799         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4800
4801         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4802             dev_priv->vlv_cdclk_freq)
4803                 return;
4804
4805         /* disable/enable all currently active pipes while we change cdclk */
4806         for_each_intel_crtc(dev, intel_crtc)
4807                 if (intel_crtc->base.enabled)
4808                         *prepare_pipes |= (1 << intel_crtc->pipe);
4809 }
4810
4811 static void valleyview_modeset_global_resources(struct drm_device *dev)
4812 {
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4815         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4816
4817         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4818                 if (IS_CHERRYVIEW(dev))
4819                         cherryview_set_cdclk(dev, req_cdclk);
4820                 else
4821                         valleyview_set_cdclk(dev, req_cdclk);
4822         }
4823
4824         modeset_update_crtc_power_domains(dev);
4825 }
4826
4827 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4828 {
4829         struct drm_device *dev = crtc->dev;
4830         struct drm_i915_private *dev_priv = to_i915(dev);
4831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832         struct intel_encoder *encoder;
4833         int pipe = intel_crtc->pipe;
4834         bool is_dsi;
4835
4836         WARN_ON(!crtc->enabled);
4837
4838         if (intel_crtc->active)
4839                 return;
4840
4841         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4842
4843         if (!is_dsi) {
4844                 if (IS_CHERRYVIEW(dev))
4845                         chv_prepare_pll(intel_crtc);
4846                 else
4847                         vlv_prepare_pll(intel_crtc);
4848         }
4849
4850         if (intel_crtc->config.has_dp_encoder)
4851                 intel_dp_set_m_n(intel_crtc);
4852
4853         intel_set_pipe_timings(intel_crtc);
4854
4855         i9xx_set_pipeconf(intel_crtc);
4856
4857         intel_crtc->active = true;
4858
4859         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4860
4861         for_each_encoder_on_crtc(dev, crtc, encoder)
4862                 if (encoder->pre_pll_enable)
4863                         encoder->pre_pll_enable(encoder);
4864
4865         if (!is_dsi) {
4866                 if (IS_CHERRYVIEW(dev))
4867                         chv_enable_pll(intel_crtc);
4868                 else
4869                         vlv_enable_pll(intel_crtc);
4870         }
4871
4872         for_each_encoder_on_crtc(dev, crtc, encoder)
4873                 if (encoder->pre_enable)
4874                         encoder->pre_enable(encoder);
4875
4876         i9xx_pfit_enable(intel_crtc);
4877
4878         intel_crtc_load_lut(crtc);
4879
4880         intel_update_watermarks(crtc);
4881         intel_enable_pipe(intel_crtc);
4882
4883         for_each_encoder_on_crtc(dev, crtc, encoder)
4884                 encoder->enable(encoder);
4885
4886         assert_vblank_disabled(crtc);
4887         drm_crtc_vblank_on(crtc);
4888
4889         intel_crtc_enable_planes(crtc);
4890
4891         /* Underruns don't raise interrupts, so check manually. */
4892         i9xx_check_fifo_underruns(dev_priv);
4893 }
4894
4895 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4896 {
4897         struct drm_device *dev = crtc->base.dev;
4898         struct drm_i915_private *dev_priv = dev->dev_private;
4899
4900         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4901         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4902 }
4903
4904 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4905 {
4906         struct drm_device *dev = crtc->dev;
4907         struct drm_i915_private *dev_priv = to_i915(dev);
4908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909         struct intel_encoder *encoder;
4910         int pipe = intel_crtc->pipe;
4911
4912         WARN_ON(!crtc->enabled);
4913
4914         if (intel_crtc->active)
4915                 return;
4916
4917         i9xx_set_pll_dividers(intel_crtc);
4918
4919         if (intel_crtc->config.has_dp_encoder)
4920                 intel_dp_set_m_n(intel_crtc);
4921
4922         intel_set_pipe_timings(intel_crtc);
4923
4924         i9xx_set_pipeconf(intel_crtc);
4925
4926         intel_crtc->active = true;
4927
4928         if (!IS_GEN2(dev))
4929                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4930
4931         for_each_encoder_on_crtc(dev, crtc, encoder)
4932                 if (encoder->pre_enable)
4933                         encoder->pre_enable(encoder);
4934
4935         i9xx_enable_pll(intel_crtc);
4936
4937         i9xx_pfit_enable(intel_crtc);
4938
4939         intel_crtc_load_lut(crtc);
4940
4941         intel_update_watermarks(crtc);
4942         intel_enable_pipe(intel_crtc);
4943
4944         for_each_encoder_on_crtc(dev, crtc, encoder)
4945                 encoder->enable(encoder);
4946
4947         assert_vblank_disabled(crtc);
4948         drm_crtc_vblank_on(crtc);
4949
4950         intel_crtc_enable_planes(crtc);
4951
4952         /*
4953          * Gen2 reports pipe underruns whenever all planes are disabled.
4954          * So don't enable underrun reporting before at least some planes
4955          * are enabled.
4956          * FIXME: Need to fix the logic to work when we turn off all planes
4957          * but leave the pipe running.
4958          */
4959         if (IS_GEN2(dev))
4960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961
4962         /* Underruns don't raise interrupts, so check manually. */
4963         i9xx_check_fifo_underruns(dev_priv);
4964 }
4965
4966 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4967 {
4968         struct drm_device *dev = crtc->base.dev;
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970
4971         if (!crtc->config.gmch_pfit.control)
4972                 return;
4973
4974         assert_pipe_disabled(dev_priv, crtc->pipe);
4975
4976         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4977                          I915_READ(PFIT_CONTROL));
4978         I915_WRITE(PFIT_CONTROL, 0);
4979 }
4980
4981 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4982 {
4983         struct drm_device *dev = crtc->dev;
4984         struct drm_i915_private *dev_priv = dev->dev_private;
4985         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4986         struct intel_encoder *encoder;
4987         int pipe = intel_crtc->pipe;
4988
4989         if (!intel_crtc->active)
4990                 return;
4991
4992         /*
4993          * Gen2 reports pipe underruns whenever all planes are disabled.
4994          * So diasble underrun reporting before all the planes get disabled.
4995          * FIXME: Need to fix the logic to work when we turn off all planes
4996          * but leave the pipe running.
4997          */
4998         if (IS_GEN2(dev))
4999                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5000
5001         /*
5002          * Vblank time updates from the shadow to live plane control register
5003          * are blocked if the memory self-refresh mode is active at that
5004          * moment. So to make sure the plane gets truly disabled, disable
5005          * first the self-refresh mode. The self-refresh enable bit in turn
5006          * will be checked/applied by the HW only at the next frame start
5007          * event which is after the vblank start event, so we need to have a
5008          * wait-for-vblank between disabling the plane and the pipe.
5009          */
5010         intel_set_memory_cxsr(dev_priv, false);
5011         intel_crtc_disable_planes(crtc);
5012
5013         /*
5014          * On gen2 planes are double buffered but the pipe isn't, so we must
5015          * wait for planes to fully turn off before disabling the pipe.
5016          * We also need to wait on all gmch platforms because of the
5017          * self-refresh mode constraint explained above.
5018          */
5019         intel_wait_for_vblank(dev, pipe);
5020
5021         drm_crtc_vblank_off(crtc);
5022         assert_vblank_disabled(crtc);
5023
5024         for_each_encoder_on_crtc(dev, crtc, encoder)
5025                 encoder->disable(encoder);
5026
5027         intel_disable_pipe(intel_crtc);
5028
5029         i9xx_pfit_disable(intel_crtc);
5030
5031         for_each_encoder_on_crtc(dev, crtc, encoder)
5032                 if (encoder->post_disable)
5033                         encoder->post_disable(encoder);
5034
5035         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5036                 if (IS_CHERRYVIEW(dev))
5037                         chv_disable_pll(dev_priv, pipe);
5038                 else if (IS_VALLEYVIEW(dev))
5039                         vlv_disable_pll(dev_priv, pipe);
5040                 else
5041                         i9xx_disable_pll(intel_crtc);
5042         }
5043
5044         if (!IS_GEN2(dev))
5045                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5046
5047         intel_crtc->active = false;
5048         intel_update_watermarks(crtc);
5049
5050         mutex_lock(&dev->struct_mutex);
5051         intel_update_fbc(dev);
5052         mutex_unlock(&dev->struct_mutex);
5053 }
5054
5055 static void i9xx_crtc_off(struct drm_crtc *crtc)
5056 {
5057 }
5058
5059 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5060                                     bool enabled)
5061 {
5062         struct drm_device *dev = crtc->dev;
5063         struct drm_i915_master_private *master_priv;
5064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065         int pipe = intel_crtc->pipe;
5066
5067         if (!dev->primary->master)
5068                 return;
5069
5070         master_priv = dev->primary->master->driver_priv;
5071         if (!master_priv->sarea_priv)
5072                 return;
5073
5074         switch (pipe) {
5075         case 0:
5076                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5077                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5078                 break;
5079         case 1:
5080                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5081                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5082                 break;
5083         default:
5084                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5085                 break;
5086         }
5087 }
5088
5089 /* Master function to enable/disable CRTC and corresponding power wells */
5090 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5091 {
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095         enum intel_display_power_domain domain;
5096         unsigned long domains;
5097
5098         if (enable) {
5099                 if (!intel_crtc->active) {
5100                         domains = get_crtc_power_domains(crtc);
5101                         for_each_power_domain(domain, domains)
5102                                 intel_display_power_get(dev_priv, domain);
5103                         intel_crtc->enabled_power_domains = domains;
5104
5105                         dev_priv->display.crtc_enable(crtc);
5106                 }
5107         } else {
5108                 if (intel_crtc->active) {
5109                         dev_priv->display.crtc_disable(crtc);
5110
5111                         domains = intel_crtc->enabled_power_domains;
5112                         for_each_power_domain(domain, domains)
5113                                 intel_display_power_put(dev_priv, domain);
5114                         intel_crtc->enabled_power_domains = 0;
5115                 }
5116         }
5117 }
5118
5119 /**
5120  * Sets the power management mode of the pipe and plane.
5121  */
5122 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5123 {
5124         struct drm_device *dev = crtc->dev;
5125         struct intel_encoder *intel_encoder;
5126         bool enable = false;
5127
5128         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5129                 enable |= intel_encoder->connectors_active;
5130
5131         intel_crtc_control(crtc, enable);
5132
5133         intel_crtc_update_sarea(crtc, enable);
5134 }
5135
5136 static void intel_crtc_disable(struct drm_crtc *crtc)
5137 {
5138         struct drm_device *dev = crtc->dev;
5139         struct drm_connector *connector;
5140         struct drm_i915_private *dev_priv = dev->dev_private;
5141         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5142         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5143
5144         /* crtc should still be enabled when we disable it. */
5145         WARN_ON(!crtc->enabled);
5146
5147         dev_priv->display.crtc_disable(crtc);
5148         intel_crtc_update_sarea(crtc, false);
5149         dev_priv->display.off(crtc);
5150
5151         if (crtc->primary->fb) {
5152                 mutex_lock(&dev->struct_mutex);
5153                 intel_unpin_fb_obj(old_obj);
5154                 i915_gem_track_fb(old_obj, NULL,
5155                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5156                 mutex_unlock(&dev->struct_mutex);
5157                 crtc->primary->fb = NULL;
5158         }
5159
5160         /* Update computed state. */
5161         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5162                 if (!connector->encoder || !connector->encoder->crtc)
5163                         continue;
5164
5165                 if (connector->encoder->crtc != crtc)
5166                         continue;
5167
5168                 connector->dpms = DRM_MODE_DPMS_OFF;
5169                 to_intel_encoder(connector->encoder)->connectors_active = false;
5170         }
5171 }
5172
5173 void intel_encoder_destroy(struct drm_encoder *encoder)
5174 {
5175         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5176
5177         drm_encoder_cleanup(encoder);
5178         kfree(intel_encoder);
5179 }
5180
5181 /* Simple dpms helper for encoders with just one connector, no cloning and only
5182  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5183  * state of the entire output pipe. */
5184 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5185 {
5186         if (mode == DRM_MODE_DPMS_ON) {
5187                 encoder->connectors_active = true;
5188
5189                 intel_crtc_update_dpms(encoder->base.crtc);
5190         } else {
5191                 encoder->connectors_active = false;
5192
5193                 intel_crtc_update_dpms(encoder->base.crtc);
5194         }
5195 }
5196
5197 /* Cross check the actual hw state with our own modeset state tracking (and it's
5198  * internal consistency). */
5199 static void intel_connector_check_state(struct intel_connector *connector)
5200 {
5201         if (connector->get_hw_state(connector)) {
5202                 struct intel_encoder *encoder = connector->encoder;
5203                 struct drm_crtc *crtc;
5204                 bool encoder_enabled;
5205                 enum pipe pipe;
5206
5207                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5208                               connector->base.base.id,
5209                               connector->base.name);
5210
5211                 /* there is no real hw state for MST connectors */
5212                 if (connector->mst_port)
5213                         return;
5214
5215                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5216                      "wrong connector dpms state\n");
5217                 WARN(connector->base.encoder != &encoder->base,
5218                      "active connector not linked to encoder\n");
5219
5220                 if (encoder) {
5221                         WARN(!encoder->connectors_active,
5222                              "encoder->connectors_active not set\n");
5223
5224                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5225                         WARN(!encoder_enabled, "encoder not enabled\n");
5226                         if (WARN_ON(!encoder->base.crtc))
5227                                 return;
5228
5229                         crtc = encoder->base.crtc;
5230
5231                         WARN(!crtc->enabled, "crtc not enabled\n");
5232                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5233                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5234                              "encoder active on the wrong pipe\n");
5235                 }
5236         }
5237 }
5238
5239 /* Even simpler default implementation, if there's really no special case to
5240  * consider. */
5241 void intel_connector_dpms(struct drm_connector *connector, int mode)
5242 {
5243         /* All the simple cases only support two dpms states. */
5244         if (mode != DRM_MODE_DPMS_ON)
5245                 mode = DRM_MODE_DPMS_OFF;
5246
5247         if (mode == connector->dpms)
5248                 return;
5249
5250         connector->dpms = mode;
5251
5252         /* Only need to change hw state when actually enabled */
5253         if (connector->encoder)
5254                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5255
5256         intel_modeset_check_state(connector->dev);
5257 }
5258
5259 /* Simple connector->get_hw_state implementation for encoders that support only
5260  * one connector and no cloning and hence the encoder state determines the state
5261  * of the connector. */
5262 bool intel_connector_get_hw_state(struct intel_connector *connector)
5263 {
5264         enum pipe pipe = 0;
5265         struct intel_encoder *encoder = connector->encoder;
5266
5267         return encoder->get_hw_state(encoder, &pipe);
5268 }
5269
5270 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5271                                      struct intel_crtc_config *pipe_config)
5272 {
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         struct intel_crtc *pipe_B_crtc =
5275                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5276
5277         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5278                       pipe_name(pipe), pipe_config->fdi_lanes);
5279         if (pipe_config->fdi_lanes > 4) {
5280                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5281                               pipe_name(pipe), pipe_config->fdi_lanes);
5282                 return false;
5283         }
5284
5285         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5286                 if (pipe_config->fdi_lanes > 2) {
5287                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5288                                       pipe_config->fdi_lanes);
5289                         return false;
5290                 } else {
5291                         return true;
5292                 }
5293         }
5294
5295         if (INTEL_INFO(dev)->num_pipes == 2)
5296                 return true;
5297
5298         /* Ivybridge 3 pipe is really complicated */
5299         switch (pipe) {
5300         case PIPE_A:
5301                 return true;
5302         case PIPE_B:
5303                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5304                     pipe_config->fdi_lanes > 2) {
5305                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5306                                       pipe_name(pipe), pipe_config->fdi_lanes);
5307                         return false;
5308                 }
5309                 return true;
5310         case PIPE_C:
5311                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5312                     pipe_B_crtc->config.fdi_lanes <= 2) {
5313                         if (pipe_config->fdi_lanes > 2) {
5314                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5315                                               pipe_name(pipe), pipe_config->fdi_lanes);
5316                                 return false;
5317                         }
5318                 } else {
5319                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5320                         return false;
5321                 }
5322                 return true;
5323         default:
5324                 BUG();
5325         }
5326 }
5327
5328 #define RETRY 1
5329 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5330                                        struct intel_crtc_config *pipe_config)
5331 {
5332         struct drm_device *dev = intel_crtc->base.dev;
5333         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5334         int lane, link_bw, fdi_dotclock;
5335         bool setup_ok, needs_recompute = false;
5336
5337 retry:
5338         /* FDI is a binary signal running at ~2.7GHz, encoding
5339          * each output octet as 10 bits. The actual frequency
5340          * is stored as a divider into a 100MHz clock, and the
5341          * mode pixel clock is stored in units of 1KHz.
5342          * Hence the bw of each lane in terms of the mode signal
5343          * is:
5344          */
5345         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5346
5347         fdi_dotclock = adjusted_mode->crtc_clock;
5348
5349         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5350                                            pipe_config->pipe_bpp);
5351
5352         pipe_config->fdi_lanes = lane;
5353
5354         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5355                                link_bw, &pipe_config->fdi_m_n);
5356
5357         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5358                                             intel_crtc->pipe, pipe_config);
5359         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5360                 pipe_config->pipe_bpp -= 2*3;
5361                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5362                               pipe_config->pipe_bpp);
5363                 needs_recompute = true;
5364                 pipe_config->bw_constrained = true;
5365
5366                 goto retry;
5367         }
5368
5369         if (needs_recompute)
5370                 return RETRY;
5371
5372         return setup_ok ? 0 : -EINVAL;
5373 }
5374
5375 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5376                                    struct intel_crtc_config *pipe_config)
5377 {
5378         pipe_config->ips_enabled = i915.enable_ips &&
5379                                    hsw_crtc_supports_ips(crtc) &&
5380                                    pipe_config->pipe_bpp <= 24;
5381 }
5382
5383 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5384                                      struct intel_crtc_config *pipe_config)
5385 {
5386         struct drm_device *dev = crtc->base.dev;
5387         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5388
5389         /* FIXME should check pixel clock limits on all platforms */
5390         if (INTEL_INFO(dev)->gen < 4) {
5391                 struct drm_i915_private *dev_priv = dev->dev_private;
5392                 int clock_limit =
5393                         dev_priv->display.get_display_clock_speed(dev);
5394
5395                 /*
5396                  * Enable pixel doubling when the dot clock
5397                  * is > 90% of the (display) core speed.
5398                  *
5399                  * GDG double wide on either pipe,
5400                  * otherwise pipe A only.
5401                  */
5402                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5403                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5404                         clock_limit *= 2;
5405                         pipe_config->double_wide = true;
5406                 }
5407
5408                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5409                         return -EINVAL;
5410         }
5411
5412         /*
5413          * Pipe horizontal size must be even in:
5414          * - DVO ganged mode
5415          * - LVDS dual channel mode
5416          * - Double wide pipe
5417          */
5418         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5419              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5420                 pipe_config->pipe_src_w &= ~1;
5421
5422         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5423          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5424          */
5425         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5426                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5427                 return -EINVAL;
5428
5429         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5430                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5431         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5432                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5433                  * for lvds. */
5434                 pipe_config->pipe_bpp = 8*3;
5435         }
5436
5437         if (HAS_IPS(dev))
5438                 hsw_compute_ips_config(crtc, pipe_config);
5439
5440         /*
5441          * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5442          * old clock survives for now.
5443          */
5444         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5445                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5446
5447         if (pipe_config->has_pch_encoder)
5448                 return ironlake_fdi_compute_config(crtc, pipe_config);
5449
5450         return 0;
5451 }
5452
5453 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5454 {
5455         struct drm_i915_private *dev_priv = dev->dev_private;
5456         int vco = valleyview_get_vco(dev_priv);
5457         u32 val;
5458         int divider;
5459
5460         /* FIXME: Punit isn't quite ready yet */
5461         if (IS_CHERRYVIEW(dev))
5462                 return 400000;
5463
5464         mutex_lock(&dev_priv->dpio_lock);
5465         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5466         mutex_unlock(&dev_priv->dpio_lock);
5467
5468         divider = val & DISPLAY_FREQUENCY_VALUES;
5469
5470         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5471              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5472              "cdclk change in progress\n");
5473
5474         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5475 }
5476
5477 static int i945_get_display_clock_speed(struct drm_device *dev)
5478 {
5479         return 400000;
5480 }
5481
5482 static int i915_get_display_clock_speed(struct drm_device *dev)
5483 {
5484         return 333000;
5485 }
5486
5487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5488 {
5489         return 200000;
5490 }
5491
5492 static int pnv_get_display_clock_speed(struct drm_device *dev)
5493 {
5494         u16 gcfgc = 0;
5495
5496         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5497
5498         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5499         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5500                 return 267000;
5501         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5502                 return 333000;
5503         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5504                 return 444000;
5505         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5506                 return 200000;
5507         default:
5508                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5509         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5510                 return 133000;
5511         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5512                 return 167000;
5513         }
5514 }
5515
5516 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5517 {
5518         u16 gcfgc = 0;
5519
5520         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5521
5522         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5523                 return 133000;
5524         else {
5525                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5526                 case GC_DISPLAY_CLOCK_333_MHZ:
5527                         return 333000;
5528                 default:
5529                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5530                         return 190000;
5531                 }
5532         }
5533 }
5534
5535 static int i865_get_display_clock_speed(struct drm_device *dev)
5536 {
5537         return 266000;
5538 }
5539
5540 static int i855_get_display_clock_speed(struct drm_device *dev)
5541 {
5542         u16 hpllcc = 0;
5543         /* Assume that the hardware is in the high speed state.  This
5544          * should be the default.
5545          */
5546         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5547         case GC_CLOCK_133_200:
5548         case GC_CLOCK_100_200:
5549                 return 200000;
5550         case GC_CLOCK_166_250:
5551                 return 250000;
5552         case GC_CLOCK_100_133:
5553                 return 133000;
5554         }
5555
5556         /* Shouldn't happen */
5557         return 0;
5558 }
5559
5560 static int i830_get_display_clock_speed(struct drm_device *dev)
5561 {
5562         return 133000;
5563 }
5564
5565 static void
5566 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5567 {
5568         while (*num > DATA_LINK_M_N_MASK ||
5569                *den > DATA_LINK_M_N_MASK) {
5570                 *num >>= 1;
5571                 *den >>= 1;
5572         }
5573 }
5574
5575 static void compute_m_n(unsigned int m, unsigned int n,
5576                         uint32_t *ret_m, uint32_t *ret_n)
5577 {
5578         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5579         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5580         intel_reduce_m_n_ratio(ret_m, ret_n);
5581 }
5582
5583 void
5584 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5585                        int pixel_clock, int link_clock,
5586                        struct intel_link_m_n *m_n)
5587 {
5588         m_n->tu = 64;
5589
5590         compute_m_n(bits_per_pixel * pixel_clock,
5591                     link_clock * nlanes * 8,
5592                     &m_n->gmch_m, &m_n->gmch_n);
5593
5594         compute_m_n(pixel_clock, link_clock,
5595                     &m_n->link_m, &m_n->link_n);
5596 }
5597
5598 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5599 {
5600         if (i915.panel_use_ssc >= 0)
5601                 return i915.panel_use_ssc != 0;
5602         return dev_priv->vbt.lvds_use_ssc
5603                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5604 }
5605
5606 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5607 {
5608         struct drm_device *dev = crtc->base.dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         int refclk;
5611
5612         if (IS_VALLEYVIEW(dev)) {
5613                 refclk = 100000;
5614         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5615             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5616                 refclk = dev_priv->vbt.lvds_ssc_freq;
5617                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5618         } else if (!IS_GEN2(dev)) {
5619                 refclk = 96000;
5620         } else {
5621                 refclk = 48000;
5622         }
5623
5624         return refclk;
5625 }
5626
5627 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5628 {
5629         return (1 << dpll->n) << 16 | dpll->m2;
5630 }
5631
5632 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5633 {
5634         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5635 }
5636
5637 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5638                                      intel_clock_t *reduced_clock)
5639 {
5640         struct drm_device *dev = crtc->base.dev;
5641         u32 fp, fp2 = 0;
5642
5643         if (IS_PINEVIEW(dev)) {
5644                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5645                 if (reduced_clock)
5646                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5647         } else {
5648                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5649                 if (reduced_clock)
5650                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5651         }
5652
5653         crtc->config.dpll_hw_state.fp0 = fp;
5654
5655         crtc->lowfreq_avail = false;
5656         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5657             reduced_clock && i915.powersave) {
5658                 crtc->config.dpll_hw_state.fp1 = fp2;
5659                 crtc->lowfreq_avail = true;
5660         } else {
5661                 crtc->config.dpll_hw_state.fp1 = fp;
5662         }
5663 }
5664
5665 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5666                 pipe)
5667 {
5668         u32 reg_val;
5669
5670         /*
5671          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5672          * and set it to a reasonable value instead.
5673          */
5674         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5675         reg_val &= 0xffffff00;
5676         reg_val |= 0x00000030;
5677         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5678
5679         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5680         reg_val &= 0x8cffffff;
5681         reg_val = 0x8c000000;
5682         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5683
5684         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5685         reg_val &= 0xffffff00;
5686         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5687
5688         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5689         reg_val &= 0x00ffffff;
5690         reg_val |= 0xb0000000;
5691         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5692 }
5693
5694 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5695                                          struct intel_link_m_n *m_n)
5696 {
5697         struct drm_device *dev = crtc->base.dev;
5698         struct drm_i915_private *dev_priv = dev->dev_private;
5699         int pipe = crtc->pipe;
5700
5701         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5702         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5703         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5704         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5705 }
5706
5707 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5708                                          struct intel_link_m_n *m_n,
5709                                          struct intel_link_m_n *m2_n2)
5710 {
5711         struct drm_device *dev = crtc->base.dev;
5712         struct drm_i915_private *dev_priv = dev->dev_private;
5713         int pipe = crtc->pipe;
5714         enum transcoder transcoder = crtc->config.cpu_transcoder;
5715
5716         if (INTEL_INFO(dev)->gen >= 5) {
5717                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5718                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5719                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5720                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5721                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5722                  * for gen < 8) and if DRRS is supported (to make sure the
5723                  * registers are not unnecessarily accessed).
5724                  */
5725                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5726                         crtc->config.has_drrs) {
5727                         I915_WRITE(PIPE_DATA_M2(transcoder),
5728                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5729                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5730                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5731                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5732                 }
5733         } else {
5734                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5736                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5737                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5738         }
5739 }
5740
5741 void intel_dp_set_m_n(struct intel_crtc *crtc)
5742 {
5743         if (crtc->config.has_pch_encoder)
5744                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5745         else
5746                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5747                                                    &crtc->config.dp_m2_n2);
5748 }
5749
5750 static void vlv_update_pll(struct intel_crtc *crtc)
5751 {
5752         u32 dpll, dpll_md;
5753
5754         /*
5755          * Enable DPIO clock input. We should never disable the reference
5756          * clock for pipe B, since VGA hotplug / manual detection depends
5757          * on it.
5758          */
5759         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5760                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5761         /* We should never disable this, set it here for state tracking */
5762         if (crtc->pipe == PIPE_B)
5763                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5764         dpll |= DPLL_VCO_ENABLE;
5765         crtc->config.dpll_hw_state.dpll = dpll;
5766
5767         dpll_md = (crtc->config.pixel_multiplier - 1)
5768                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5769         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5770 }
5771
5772 static void vlv_prepare_pll(struct intel_crtc *crtc)
5773 {
5774         struct drm_device *dev = crtc->base.dev;
5775         struct drm_i915_private *dev_priv = dev->dev_private;
5776         int pipe = crtc->pipe;
5777         u32 mdiv;
5778         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5779         u32 coreclk, reg_val;
5780
5781         mutex_lock(&dev_priv->dpio_lock);
5782
5783         bestn = crtc->config.dpll.n;
5784         bestm1 = crtc->config.dpll.m1;
5785         bestm2 = crtc->config.dpll.m2;
5786         bestp1 = crtc->config.dpll.p1;
5787         bestp2 = crtc->config.dpll.p2;
5788
5789         /* See eDP HDMI DPIO driver vbios notes doc */
5790
5791         /* PLL B needs special handling */
5792         if (pipe == PIPE_B)
5793                 vlv_pllb_recal_opamp(dev_priv, pipe);
5794
5795         /* Set up Tx target for periodic Rcomp update */
5796         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5797
5798         /* Disable target IRef on PLL */
5799         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5800         reg_val &= 0x00ffffff;
5801         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5802
5803         /* Disable fast lock */
5804         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5805
5806         /* Set idtafcrecal before PLL is enabled */
5807         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5808         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5809         mdiv |= ((bestn << DPIO_N_SHIFT));
5810         mdiv |= (1 << DPIO_K_SHIFT);
5811
5812         /*
5813          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5814          * but we don't support that).
5815          * Note: don't use the DAC post divider as it seems unstable.
5816          */
5817         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5818         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5819
5820         mdiv |= DPIO_ENABLE_CALIBRATION;
5821         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5822
5823         /* Set HBR and RBR LPF coefficients */
5824         if (crtc->config.port_clock == 162000 ||
5825             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5826             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5827                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5828                                  0x009f0003);
5829         else
5830                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5831                                  0x00d0000f);
5832
5833         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
5834             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5835                 /* Use SSC source */
5836                 if (pipe == PIPE_A)
5837                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5838                                          0x0df40000);
5839                 else
5840                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5841                                          0x0df70000);
5842         } else { /* HDMI or VGA */
5843                 /* Use bend source */
5844                 if (pipe == PIPE_A)
5845                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5846                                          0x0df70000);
5847                 else
5848                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5849                                          0x0df40000);
5850         }
5851
5852         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5853         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5854         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5855             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5856                 coreclk |= 0x01000000;
5857         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5858
5859         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5860         mutex_unlock(&dev_priv->dpio_lock);
5861 }
5862
5863 static void chv_update_pll(struct intel_crtc *crtc)
5864 {
5865         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5866                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5867                 DPLL_VCO_ENABLE;
5868         if (crtc->pipe != PIPE_A)
5869                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5870
5871         crtc->config.dpll_hw_state.dpll_md =
5872                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5873 }
5874
5875 static void chv_prepare_pll(struct intel_crtc *crtc)
5876 {
5877         struct drm_device *dev = crtc->base.dev;
5878         struct drm_i915_private *dev_priv = dev->dev_private;
5879         int pipe = crtc->pipe;
5880         int dpll_reg = DPLL(crtc->pipe);
5881         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5882         u32 loopfilter, intcoeff;
5883         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5884         int refclk;
5885
5886         bestn = crtc->config.dpll.n;
5887         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5888         bestm1 = crtc->config.dpll.m1;
5889         bestm2 = crtc->config.dpll.m2 >> 22;
5890         bestp1 = crtc->config.dpll.p1;
5891         bestp2 = crtc->config.dpll.p2;
5892
5893         /*
5894          * Enable Refclk and SSC
5895          */
5896         I915_WRITE(dpll_reg,
5897                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5898
5899         mutex_lock(&dev_priv->dpio_lock);
5900
5901         /* p1 and p2 divider */
5902         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5903                         5 << DPIO_CHV_S1_DIV_SHIFT |
5904                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5905                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5906                         1 << DPIO_CHV_K_DIV_SHIFT);
5907
5908         /* Feedback post-divider - m2 */
5909         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5910
5911         /* Feedback refclk divider - n and m1 */
5912         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5913                         DPIO_CHV_M1_DIV_BY_2 |
5914                         1 << DPIO_CHV_N_DIV_SHIFT);
5915
5916         /* M2 fraction division */
5917         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5918
5919         /* M2 fraction division enable */
5920         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5921                        DPIO_CHV_FRAC_DIV_EN |
5922                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5923
5924         /* Loop filter */
5925         refclk = i9xx_get_refclk(crtc, 0);
5926         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5927                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5928         if (refclk == 100000)
5929                 intcoeff = 11;
5930         else if (refclk == 38400)
5931                 intcoeff = 10;
5932         else
5933                 intcoeff = 9;
5934         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5935         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5936
5937         /* AFC Recal */
5938         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5939                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5940                         DPIO_AFC_RECAL);
5941
5942         mutex_unlock(&dev_priv->dpio_lock);
5943 }
5944
5945 static void i9xx_update_pll(struct intel_crtc *crtc,
5946                             intel_clock_t *reduced_clock,
5947                             int num_connectors)
5948 {
5949         struct drm_device *dev = crtc->base.dev;
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         u32 dpll;
5952         bool is_sdvo;
5953         struct dpll *clock = &crtc->config.dpll;
5954
5955         i9xx_update_pll_dividers(crtc, reduced_clock);
5956
5957         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
5958                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
5959
5960         dpll = DPLL_VGA_MODE_DIS;
5961
5962         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
5963                 dpll |= DPLLB_MODE_LVDS;
5964         else
5965                 dpll |= DPLLB_MODE_DAC_SERIAL;
5966
5967         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5968                 dpll |= (crtc->config.pixel_multiplier - 1)
5969                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5970         }
5971
5972         if (is_sdvo)
5973                 dpll |= DPLL_SDVO_HIGH_SPEED;
5974
5975         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
5976                 dpll |= DPLL_SDVO_HIGH_SPEED;
5977
5978         /* compute bitmask from p1 value */
5979         if (IS_PINEVIEW(dev))
5980                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5981         else {
5982                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5983                 if (IS_G4X(dev) && reduced_clock)
5984                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5985         }
5986         switch (clock->p2) {
5987         case 5:
5988                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5989                 break;
5990         case 7:
5991                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5992                 break;
5993         case 10:
5994                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5995                 break;
5996         case 14:
5997                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5998                 break;
5999         }
6000         if (INTEL_INFO(dev)->gen >= 4)
6001                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6002
6003         if (crtc->config.sdvo_tv_clock)
6004                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6005         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6006                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6007                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6008         else
6009                 dpll |= PLL_REF_INPUT_DREFCLK;
6010
6011         dpll |= DPLL_VCO_ENABLE;
6012         crtc->config.dpll_hw_state.dpll = dpll;
6013
6014         if (INTEL_INFO(dev)->gen >= 4) {
6015                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6016                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6018         }
6019 }
6020
6021 static void i8xx_update_pll(struct intel_crtc *crtc,
6022                             intel_clock_t *reduced_clock,
6023                             int num_connectors)
6024 {
6025         struct drm_device *dev = crtc->base.dev;
6026         struct drm_i915_private *dev_priv = dev->dev_private;
6027         u32 dpll;
6028         struct dpll *clock = &crtc->config.dpll;
6029
6030         i9xx_update_pll_dividers(crtc, reduced_clock);
6031
6032         dpll = DPLL_VGA_MODE_DIS;
6033
6034         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6035                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6036         } else {
6037                 if (clock->p1 == 2)
6038                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6039                 else
6040                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6041                 if (clock->p2 == 4)
6042                         dpll |= PLL_P2_DIVIDE_BY_4;
6043         }
6044
6045         if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
6046                 dpll |= DPLL_DVO_2X_MODE;
6047
6048         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
6049                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6050                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6051         else
6052                 dpll |= PLL_REF_INPUT_DREFCLK;
6053
6054         dpll |= DPLL_VCO_ENABLE;
6055         crtc->config.dpll_hw_state.dpll = dpll;
6056 }
6057
6058 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6059 {
6060         struct drm_device *dev = intel_crtc->base.dev;
6061         struct drm_i915_private *dev_priv = dev->dev_private;
6062         enum pipe pipe = intel_crtc->pipe;
6063         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6064         struct drm_display_mode *adjusted_mode =
6065                 &intel_crtc->config.adjusted_mode;
6066         uint32_t crtc_vtotal, crtc_vblank_end;
6067         int vsyncshift = 0;
6068
6069         /* We need to be careful not to changed the adjusted mode, for otherwise
6070          * the hw state checker will get angry at the mismatch. */
6071         crtc_vtotal = adjusted_mode->crtc_vtotal;
6072         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6073
6074         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6075                 /* the chip adds 2 halflines automatically */
6076                 crtc_vtotal -= 1;
6077                 crtc_vblank_end -= 1;
6078
6079                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6080                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6081                 else
6082                         vsyncshift = adjusted_mode->crtc_hsync_start -
6083                                 adjusted_mode->crtc_htotal / 2;
6084                 if (vsyncshift < 0)
6085                         vsyncshift += adjusted_mode->crtc_htotal;
6086         }
6087
6088         if (INTEL_INFO(dev)->gen > 3)
6089                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6090
6091         I915_WRITE(HTOTAL(cpu_transcoder),
6092                    (adjusted_mode->crtc_hdisplay - 1) |
6093                    ((adjusted_mode->crtc_htotal - 1) << 16));
6094         I915_WRITE(HBLANK(cpu_transcoder),
6095                    (adjusted_mode->crtc_hblank_start - 1) |
6096                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6097         I915_WRITE(HSYNC(cpu_transcoder),
6098                    (adjusted_mode->crtc_hsync_start - 1) |
6099                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6100
6101         I915_WRITE(VTOTAL(cpu_transcoder),
6102                    (adjusted_mode->crtc_vdisplay - 1) |
6103                    ((crtc_vtotal - 1) << 16));
6104         I915_WRITE(VBLANK(cpu_transcoder),
6105                    (adjusted_mode->crtc_vblank_start - 1) |
6106                    ((crtc_vblank_end - 1) << 16));
6107         I915_WRITE(VSYNC(cpu_transcoder),
6108                    (adjusted_mode->crtc_vsync_start - 1) |
6109                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6110
6111         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6112          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6113          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6114          * bits. */
6115         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6116             (pipe == PIPE_B || pipe == PIPE_C))
6117                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6118
6119         /* pipesrc controls the size that is scaled from, which should
6120          * always be the user's requested size.
6121          */
6122         I915_WRITE(PIPESRC(pipe),
6123                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6124                    (intel_crtc->config.pipe_src_h - 1));
6125 }
6126
6127 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6128                                    struct intel_crtc_config *pipe_config)
6129 {
6130         struct drm_device *dev = crtc->base.dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6133         uint32_t tmp;
6134
6135         tmp = I915_READ(HTOTAL(cpu_transcoder));
6136         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6137         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6138         tmp = I915_READ(HBLANK(cpu_transcoder));
6139         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6140         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6141         tmp = I915_READ(HSYNC(cpu_transcoder));
6142         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6143         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6144
6145         tmp = I915_READ(VTOTAL(cpu_transcoder));
6146         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6147         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6148         tmp = I915_READ(VBLANK(cpu_transcoder));
6149         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6150         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6151         tmp = I915_READ(VSYNC(cpu_transcoder));
6152         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6153         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6154
6155         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6156                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6157                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6158                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6159         }
6160
6161         tmp = I915_READ(PIPESRC(crtc->pipe));
6162         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6163         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6164
6165         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6166         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6167 }
6168
6169 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6170                                  struct intel_crtc_config *pipe_config)
6171 {
6172         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6173         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6174         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6175         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6176
6177         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6178         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6179         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6180         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6181
6182         mode->flags = pipe_config->adjusted_mode.flags;
6183
6184         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6185         mode->flags |= pipe_config->adjusted_mode.flags;
6186 }
6187
6188 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6189 {
6190         struct drm_device *dev = intel_crtc->base.dev;
6191         struct drm_i915_private *dev_priv = dev->dev_private;
6192         uint32_t pipeconf;
6193
6194         pipeconf = 0;
6195
6196         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6197             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6198                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6199
6200         if (intel_crtc->config.double_wide)
6201                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6202
6203         /* only g4x and later have fancy bpc/dither controls */
6204         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6205                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6206                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6207                         pipeconf |= PIPECONF_DITHER_EN |
6208                                     PIPECONF_DITHER_TYPE_SP;
6209
6210                 switch (intel_crtc->config.pipe_bpp) {
6211                 case 18:
6212                         pipeconf |= PIPECONF_6BPC;
6213                         break;
6214                 case 24:
6215                         pipeconf |= PIPECONF_8BPC;
6216                         break;
6217                 case 30:
6218                         pipeconf |= PIPECONF_10BPC;
6219                         break;
6220                 default:
6221                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6222                         BUG();
6223                 }
6224         }
6225
6226         if (HAS_PIPE_CXSR(dev)) {
6227                 if (intel_crtc->lowfreq_avail) {
6228                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6229                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6230                 } else {
6231                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6232                 }
6233         }
6234
6235         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6236                 if (INTEL_INFO(dev)->gen < 4 ||
6237                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6238                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6239                 else
6240                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6241         } else
6242                 pipeconf |= PIPECONF_PROGRESSIVE;
6243
6244         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6245                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6246
6247         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6248         POSTING_READ(PIPECONF(intel_crtc->pipe));
6249 }
6250
6251 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6252                               int x, int y,
6253                               struct drm_framebuffer *fb)
6254 {
6255         struct drm_device *dev = crtc->base.dev;
6256         struct drm_i915_private *dev_priv = dev->dev_private;
6257         int refclk, num_connectors = 0;
6258         intel_clock_t clock, reduced_clock;
6259         bool ok, has_reduced_clock = false;
6260         bool is_lvds = false, is_dsi = false;
6261         struct intel_encoder *encoder;
6262         const intel_limit_t *limit;
6263
6264         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
6265                 switch (encoder->type) {
6266                 case INTEL_OUTPUT_LVDS:
6267                         is_lvds = true;
6268                         break;
6269                 case INTEL_OUTPUT_DSI:
6270                         is_dsi = true;
6271                         break;
6272                 default:
6273                         break;
6274                 }
6275
6276                 num_connectors++;
6277         }
6278
6279         if (is_dsi)
6280                 return 0;
6281
6282         if (!crtc->config.clock_set) {
6283                 refclk = i9xx_get_refclk(crtc, num_connectors);
6284
6285                 /*
6286                  * Returns a set of divisors for the desired target clock with
6287                  * the given refclk, or FALSE.  The returned values represent
6288                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6289                  * 2) / p1 / p2.
6290                  */
6291                 limit = intel_limit(crtc, refclk);
6292                 ok = dev_priv->display.find_dpll(limit, crtc,
6293                                                  crtc->config.port_clock,
6294                                                  refclk, NULL, &clock);
6295                 if (!ok) {
6296                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6297                         return -EINVAL;
6298                 }
6299
6300                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6301                         /*
6302                          * Ensure we match the reduced clock's P to the target
6303                          * clock.  If the clocks don't match, we can't switch
6304                          * the display clock by using the FP0/FP1. In such case
6305                          * we will disable the LVDS downclock feature.
6306                          */
6307                         has_reduced_clock =
6308                                 dev_priv->display.find_dpll(limit, crtc,
6309                                                             dev_priv->lvds_downclock,
6310                                                             refclk, &clock,
6311                                                             &reduced_clock);
6312                 }
6313                 /* Compat-code for transition, will disappear. */
6314                 crtc->config.dpll.n = clock.n;
6315                 crtc->config.dpll.m1 = clock.m1;
6316                 crtc->config.dpll.m2 = clock.m2;
6317                 crtc->config.dpll.p1 = clock.p1;
6318                 crtc->config.dpll.p2 = clock.p2;
6319         }
6320
6321         if (IS_GEN2(dev)) {
6322                 i8xx_update_pll(crtc,
6323                                 has_reduced_clock ? &reduced_clock : NULL,
6324                                 num_connectors);
6325         } else if (IS_CHERRYVIEW(dev)) {
6326                 chv_update_pll(crtc);
6327         } else if (IS_VALLEYVIEW(dev)) {
6328                 vlv_update_pll(crtc);
6329         } else {
6330                 i9xx_update_pll(crtc,
6331                                 has_reduced_clock ? &reduced_clock : NULL,
6332                                 num_connectors);
6333         }
6334
6335         return 0;
6336 }
6337
6338 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6339                                  struct intel_crtc_config *pipe_config)
6340 {
6341         struct drm_device *dev = crtc->base.dev;
6342         struct drm_i915_private *dev_priv = dev->dev_private;
6343         uint32_t tmp;
6344
6345         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6346                 return;
6347
6348         tmp = I915_READ(PFIT_CONTROL);
6349         if (!(tmp & PFIT_ENABLE))
6350                 return;
6351
6352         /* Check whether the pfit is attached to our pipe. */
6353         if (INTEL_INFO(dev)->gen < 4) {
6354                 if (crtc->pipe != PIPE_B)
6355                         return;
6356         } else {
6357                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6358                         return;
6359         }
6360
6361         pipe_config->gmch_pfit.control = tmp;
6362         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6363         if (INTEL_INFO(dev)->gen < 5)
6364                 pipe_config->gmch_pfit.lvds_border_bits =
6365                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6366 }
6367
6368 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6369                                struct intel_crtc_config *pipe_config)
6370 {
6371         struct drm_device *dev = crtc->base.dev;
6372         struct drm_i915_private *dev_priv = dev->dev_private;
6373         int pipe = pipe_config->cpu_transcoder;
6374         intel_clock_t clock;
6375         u32 mdiv;
6376         int refclk = 100000;
6377
6378         /* In case of MIPI DPLL will not even be used */
6379         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6380                 return;
6381
6382         mutex_lock(&dev_priv->dpio_lock);
6383         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6384         mutex_unlock(&dev_priv->dpio_lock);
6385
6386         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6387         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6388         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6389         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6390         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6391
6392         vlv_clock(refclk, &clock);
6393
6394         /* clock.dot is the fast clock */
6395         pipe_config->port_clock = clock.dot / 5;
6396 }
6397
6398 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6399                                   struct intel_plane_config *plane_config)
6400 {
6401         struct drm_device *dev = crtc->base.dev;
6402         struct drm_i915_private *dev_priv = dev->dev_private;
6403         u32 val, base, offset;
6404         int pipe = crtc->pipe, plane = crtc->plane;
6405         int fourcc, pixel_format;
6406         int aligned_height;
6407
6408         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6409         if (!crtc->base.primary->fb) {
6410                 DRM_DEBUG_KMS("failed to alloc fb\n");
6411                 return;
6412         }
6413
6414         val = I915_READ(DSPCNTR(plane));
6415
6416         if (INTEL_INFO(dev)->gen >= 4)
6417                 if (val & DISPPLANE_TILED)
6418                         plane_config->tiled = true;
6419
6420         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6421         fourcc = intel_format_to_fourcc(pixel_format);
6422         crtc->base.primary->fb->pixel_format = fourcc;
6423         crtc->base.primary->fb->bits_per_pixel =
6424                 drm_format_plane_cpp(fourcc, 0) * 8;
6425
6426         if (INTEL_INFO(dev)->gen >= 4) {
6427                 if (plane_config->tiled)
6428                         offset = I915_READ(DSPTILEOFF(plane));
6429                 else
6430                         offset = I915_READ(DSPLINOFF(plane));
6431                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6432         } else {
6433                 base = I915_READ(DSPADDR(plane));
6434         }
6435         plane_config->base = base;
6436
6437         val = I915_READ(PIPESRC(pipe));
6438         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6439         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6440
6441         val = I915_READ(DSPSTRIDE(pipe));
6442         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6443
6444         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6445                                             plane_config->tiled);
6446
6447         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6448                                         aligned_height);
6449
6450         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6451                       pipe, plane, crtc->base.primary->fb->width,
6452                       crtc->base.primary->fb->height,
6453                       crtc->base.primary->fb->bits_per_pixel, base,
6454                       crtc->base.primary->fb->pitches[0],
6455                       plane_config->size);
6456
6457 }
6458
6459 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6460                                struct intel_crtc_config *pipe_config)
6461 {
6462         struct drm_device *dev = crtc->base.dev;
6463         struct drm_i915_private *dev_priv = dev->dev_private;
6464         int pipe = pipe_config->cpu_transcoder;
6465         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6466         intel_clock_t clock;
6467         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6468         int refclk = 100000;
6469
6470         mutex_lock(&dev_priv->dpio_lock);
6471         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6472         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6473         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6474         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6475         mutex_unlock(&dev_priv->dpio_lock);
6476
6477         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6478         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6479         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6480         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6481         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6482
6483         chv_clock(refclk, &clock);
6484
6485         /* clock.dot is the fast clock */
6486         pipe_config->port_clock = clock.dot / 5;
6487 }
6488
6489 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6490                                  struct intel_crtc_config *pipe_config)
6491 {
6492         struct drm_device *dev = crtc->base.dev;
6493         struct drm_i915_private *dev_priv = dev->dev_private;
6494         uint32_t tmp;
6495
6496         if (!intel_display_power_is_enabled(dev_priv,
6497                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6498                 return false;
6499
6500         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6501         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6502
6503         tmp = I915_READ(PIPECONF(crtc->pipe));
6504         if (!(tmp & PIPECONF_ENABLE))
6505                 return false;
6506
6507         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6508                 switch (tmp & PIPECONF_BPC_MASK) {
6509                 case PIPECONF_6BPC:
6510                         pipe_config->pipe_bpp = 18;
6511                         break;
6512                 case PIPECONF_8BPC:
6513                         pipe_config->pipe_bpp = 24;
6514                         break;
6515                 case PIPECONF_10BPC:
6516                         pipe_config->pipe_bpp = 30;
6517                         break;
6518                 default:
6519                         break;
6520                 }
6521         }
6522
6523         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6524                 pipe_config->limited_color_range = true;
6525
6526         if (INTEL_INFO(dev)->gen < 4)
6527                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6528
6529         intel_get_pipe_timings(crtc, pipe_config);
6530
6531         i9xx_get_pfit_config(crtc, pipe_config);
6532
6533         if (INTEL_INFO(dev)->gen >= 4) {
6534                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6535                 pipe_config->pixel_multiplier =
6536                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6537                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6538                 pipe_config->dpll_hw_state.dpll_md = tmp;
6539         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6540                 tmp = I915_READ(DPLL(crtc->pipe));
6541                 pipe_config->pixel_multiplier =
6542                         ((tmp & SDVO_MULTIPLIER_MASK)
6543                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6544         } else {
6545                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6546                  * port and will be fixed up in the encoder->get_config
6547                  * function. */
6548                 pipe_config->pixel_multiplier = 1;
6549         }
6550         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6551         if (!IS_VALLEYVIEW(dev)) {
6552                 /*
6553                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6554                  * on 830. Filter it out here so that we don't
6555                  * report errors due to that.
6556                  */
6557                 if (IS_I830(dev))
6558                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6559
6560                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6561                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6562         } else {
6563                 /* Mask out read-only status bits. */
6564                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6565                                                      DPLL_PORTC_READY_MASK |
6566                                                      DPLL_PORTB_READY_MASK);
6567         }
6568
6569         if (IS_CHERRYVIEW(dev))
6570                 chv_crtc_clock_get(crtc, pipe_config);
6571         else if (IS_VALLEYVIEW(dev))
6572                 vlv_crtc_clock_get(crtc, pipe_config);
6573         else
6574                 i9xx_crtc_clock_get(crtc, pipe_config);
6575
6576         return true;
6577 }
6578
6579 static void ironlake_init_pch_refclk(struct drm_device *dev)
6580 {
6581         struct drm_i915_private *dev_priv = dev->dev_private;
6582         struct intel_encoder *encoder;
6583         u32 val, final;
6584         bool has_lvds = false;
6585         bool has_cpu_edp = false;
6586         bool has_panel = false;
6587         bool has_ck505 = false;
6588         bool can_ssc = false;
6589
6590         /* We need to take the global config into account */
6591         for_each_intel_encoder(dev, encoder) {
6592                 switch (encoder->type) {
6593                 case INTEL_OUTPUT_LVDS:
6594                         has_panel = true;
6595                         has_lvds = true;
6596                         break;
6597                 case INTEL_OUTPUT_EDP:
6598                         has_panel = true;
6599                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6600                                 has_cpu_edp = true;
6601                         break;
6602                 default:
6603                         break;
6604                 }
6605         }
6606
6607         if (HAS_PCH_IBX(dev)) {
6608                 has_ck505 = dev_priv->vbt.display_clock_mode;
6609                 can_ssc = has_ck505;
6610         } else {
6611                 has_ck505 = false;
6612                 can_ssc = true;
6613         }
6614
6615         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6616                       has_panel, has_lvds, has_ck505);
6617
6618         /* Ironlake: try to setup display ref clock before DPLL
6619          * enabling. This is only under driver's control after
6620          * PCH B stepping, previous chipset stepping should be
6621          * ignoring this setting.
6622          */
6623         val = I915_READ(PCH_DREF_CONTROL);
6624
6625         /* As we must carefully and slowly disable/enable each source in turn,
6626          * compute the final state we want first and check if we need to
6627          * make any changes at all.
6628          */
6629         final = val;
6630         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6631         if (has_ck505)
6632                 final |= DREF_NONSPREAD_CK505_ENABLE;
6633         else
6634                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6635
6636         final &= ~DREF_SSC_SOURCE_MASK;
6637         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6638         final &= ~DREF_SSC1_ENABLE;
6639
6640         if (has_panel) {
6641                 final |= DREF_SSC_SOURCE_ENABLE;
6642
6643                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6644                         final |= DREF_SSC1_ENABLE;
6645
6646                 if (has_cpu_edp) {
6647                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6648                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6649                         else
6650                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6651                 } else
6652                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6653         } else {
6654                 final |= DREF_SSC_SOURCE_DISABLE;
6655                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6656         }
6657
6658         if (final == val)
6659                 return;
6660
6661         /* Always enable nonspread source */
6662         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6663
6664         if (has_ck505)
6665                 val |= DREF_NONSPREAD_CK505_ENABLE;
6666         else
6667                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6668
6669         if (has_panel) {
6670                 val &= ~DREF_SSC_SOURCE_MASK;
6671                 val |= DREF_SSC_SOURCE_ENABLE;
6672
6673                 /* SSC must be turned on before enabling the CPU output  */
6674                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6675                         DRM_DEBUG_KMS("Using SSC on panel\n");
6676                         val |= DREF_SSC1_ENABLE;
6677                 } else
6678                         val &= ~DREF_SSC1_ENABLE;
6679
6680                 /* Get SSC going before enabling the outputs */
6681                 I915_WRITE(PCH_DREF_CONTROL, val);
6682                 POSTING_READ(PCH_DREF_CONTROL);
6683                 udelay(200);
6684
6685                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6686
6687                 /* Enable CPU source on CPU attached eDP */
6688                 if (has_cpu_edp) {
6689                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6690                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6691                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6692                         } else
6693                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6694                 } else
6695                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6696
6697                 I915_WRITE(PCH_DREF_CONTROL, val);
6698                 POSTING_READ(PCH_DREF_CONTROL);
6699                 udelay(200);
6700         } else {
6701                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6702
6703                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6704
6705                 /* Turn off CPU output */
6706                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6707
6708                 I915_WRITE(PCH_DREF_CONTROL, val);
6709                 POSTING_READ(PCH_DREF_CONTROL);
6710                 udelay(200);
6711
6712                 /* Turn off the SSC source */
6713                 val &= ~DREF_SSC_SOURCE_MASK;
6714                 val |= DREF_SSC_SOURCE_DISABLE;
6715
6716                 /* Turn off SSC1 */
6717                 val &= ~DREF_SSC1_ENABLE;
6718
6719                 I915_WRITE(PCH_DREF_CONTROL, val);
6720                 POSTING_READ(PCH_DREF_CONTROL);
6721                 udelay(200);
6722         }
6723
6724         BUG_ON(val != final);
6725 }
6726
6727 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6728 {
6729         uint32_t tmp;
6730
6731         tmp = I915_READ(SOUTH_CHICKEN2);
6732         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6733         I915_WRITE(SOUTH_CHICKEN2, tmp);
6734
6735         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6736                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6737                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6738
6739         tmp = I915_READ(SOUTH_CHICKEN2);
6740         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6741         I915_WRITE(SOUTH_CHICKEN2, tmp);
6742
6743         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6744                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6745                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6746 }
6747
6748 /* WaMPhyProgramming:hsw */
6749 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6750 {
6751         uint32_t tmp;
6752
6753         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6754         tmp &= ~(0xFF << 24);
6755         tmp |= (0x12 << 24);
6756         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6757
6758         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6759         tmp |= (1 << 11);
6760         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6761
6762         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6763         tmp |= (1 << 11);
6764         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6765
6766         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6767         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6768         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6769
6770         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6771         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6772         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6773
6774         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6775         tmp &= ~(7 << 13);
6776         tmp |= (5 << 13);
6777         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6778
6779         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6780         tmp &= ~(7 << 13);
6781         tmp |= (5 << 13);
6782         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6783
6784         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6785         tmp &= ~0xFF;
6786         tmp |= 0x1C;
6787         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6788
6789         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6790         tmp &= ~0xFF;
6791         tmp |= 0x1C;
6792         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6793
6794         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6795         tmp &= ~(0xFF << 16);
6796         tmp |= (0x1C << 16);
6797         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6798
6799         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6800         tmp &= ~(0xFF << 16);
6801         tmp |= (0x1C << 16);
6802         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6803
6804         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6805         tmp |= (1 << 27);
6806         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6807
6808         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6809         tmp |= (1 << 27);
6810         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6811
6812         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6813         tmp &= ~(0xF << 28);
6814         tmp |= (4 << 28);
6815         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6816
6817         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6818         tmp &= ~(0xF << 28);
6819         tmp |= (4 << 28);
6820         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6821 }
6822
6823 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6824  * Programming" based on the parameters passed:
6825  * - Sequence to enable CLKOUT_DP
6826  * - Sequence to enable CLKOUT_DP without spread
6827  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6828  */
6829 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6830                                  bool with_fdi)
6831 {
6832         struct drm_i915_private *dev_priv = dev->dev_private;
6833         uint32_t reg, tmp;
6834
6835         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6836                 with_spread = true;
6837         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6838                  with_fdi, "LP PCH doesn't have FDI\n"))
6839                 with_fdi = false;
6840
6841         mutex_lock(&dev_priv->dpio_lock);
6842
6843         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6844         tmp &= ~SBI_SSCCTL_DISABLE;
6845         tmp |= SBI_SSCCTL_PATHALT;
6846         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6847
6848         udelay(24);
6849
6850         if (with_spread) {
6851                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6852                 tmp &= ~SBI_SSCCTL_PATHALT;
6853                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6854
6855                 if (with_fdi) {
6856                         lpt_reset_fdi_mphy(dev_priv);
6857                         lpt_program_fdi_mphy(dev_priv);
6858                 }
6859         }
6860
6861         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6862                SBI_GEN0 : SBI_DBUFF0;
6863         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6864         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6865         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6866
6867         mutex_unlock(&dev_priv->dpio_lock);
6868 }
6869
6870 /* Sequence to disable CLKOUT_DP */
6871 static void lpt_disable_clkout_dp(struct drm_device *dev)
6872 {
6873         struct drm_i915_private *dev_priv = dev->dev_private;
6874         uint32_t reg, tmp;
6875
6876         mutex_lock(&dev_priv->dpio_lock);
6877
6878         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6879                SBI_GEN0 : SBI_DBUFF0;
6880         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6881         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6882         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6883
6884         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6885         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6886                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6887                         tmp |= SBI_SSCCTL_PATHALT;
6888                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6889                         udelay(32);
6890                 }
6891                 tmp |= SBI_SSCCTL_DISABLE;
6892                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6893         }
6894
6895         mutex_unlock(&dev_priv->dpio_lock);
6896 }
6897
6898 static void lpt_init_pch_refclk(struct drm_device *dev)
6899 {
6900         struct intel_encoder *encoder;
6901         bool has_vga = false;
6902
6903         for_each_intel_encoder(dev, encoder) {
6904                 switch (encoder->type) {
6905                 case INTEL_OUTPUT_ANALOG:
6906                         has_vga = true;
6907                         break;
6908                 default:
6909                         break;
6910                 }
6911         }
6912
6913         if (has_vga)
6914                 lpt_enable_clkout_dp(dev, true, true);
6915         else
6916                 lpt_disable_clkout_dp(dev);
6917 }
6918
6919 /*
6920  * Initialize reference clocks when the driver loads
6921  */
6922 void intel_init_pch_refclk(struct drm_device *dev)
6923 {
6924         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6925                 ironlake_init_pch_refclk(dev);
6926         else if (HAS_PCH_LPT(dev))
6927                 lpt_init_pch_refclk(dev);
6928 }
6929
6930 static int ironlake_get_refclk(struct drm_crtc *crtc)
6931 {
6932         struct drm_device *dev = crtc->dev;
6933         struct drm_i915_private *dev_priv = dev->dev_private;
6934         struct intel_encoder *encoder;
6935         int num_connectors = 0;
6936         bool is_lvds = false;
6937
6938         for_each_encoder_on_crtc(dev, crtc, encoder) {
6939                 switch (encoder->type) {
6940                 case INTEL_OUTPUT_LVDS:
6941                         is_lvds = true;
6942                         break;
6943                 default:
6944                         break;
6945                 }
6946                 num_connectors++;
6947         }
6948
6949         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6950                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6951                               dev_priv->vbt.lvds_ssc_freq);
6952                 return dev_priv->vbt.lvds_ssc_freq;
6953         }
6954
6955         return 120000;
6956 }
6957
6958 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6959 {
6960         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6961         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6962         int pipe = intel_crtc->pipe;
6963         uint32_t val;
6964
6965         val = 0;
6966
6967         switch (intel_crtc->config.pipe_bpp) {
6968         case 18:
6969                 val |= PIPECONF_6BPC;
6970                 break;
6971         case 24:
6972                 val |= PIPECONF_8BPC;
6973                 break;
6974         case 30:
6975                 val |= PIPECONF_10BPC;
6976                 break;
6977         case 36:
6978                 val |= PIPECONF_12BPC;
6979                 break;
6980         default:
6981                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6982                 BUG();
6983         }
6984
6985         if (intel_crtc->config.dither)
6986                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6987
6988         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6989                 val |= PIPECONF_INTERLACED_ILK;
6990         else
6991                 val |= PIPECONF_PROGRESSIVE;
6992
6993         if (intel_crtc->config.limited_color_range)
6994                 val |= PIPECONF_COLOR_RANGE_SELECT;
6995
6996         I915_WRITE(PIPECONF(pipe), val);
6997         POSTING_READ(PIPECONF(pipe));
6998 }
6999
7000 /*
7001  * Set up the pipe CSC unit.
7002  *
7003  * Currently only full range RGB to limited range RGB conversion
7004  * is supported, but eventually this should handle various
7005  * RGB<->YCbCr scenarios as well.
7006  */
7007 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7008 {
7009         struct drm_device *dev = crtc->dev;
7010         struct drm_i915_private *dev_priv = dev->dev_private;
7011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7012         int pipe = intel_crtc->pipe;
7013         uint16_t coeff = 0x7800; /* 1.0 */
7014
7015         /*
7016          * TODO: Check what kind of values actually come out of the pipe
7017          * with these coeff/postoff values and adjust to get the best
7018          * accuracy. Perhaps we even need to take the bpc value into
7019          * consideration.
7020          */
7021
7022         if (intel_crtc->config.limited_color_range)
7023                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7024
7025         /*
7026          * GY/GU and RY/RU should be the other way around according
7027          * to BSpec, but reality doesn't agree. Just set them up in
7028          * a way that results in the correct picture.
7029          */
7030         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7031         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7032
7033         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7034         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7035
7036         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7037         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7038
7039         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7040         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7041         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7042
7043         if (INTEL_INFO(dev)->gen > 6) {
7044                 uint16_t postoff = 0;
7045
7046                 if (intel_crtc->config.limited_color_range)
7047                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7048
7049                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7050                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7051                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7052
7053                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7054         } else {
7055                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7056
7057                 if (intel_crtc->config.limited_color_range)
7058                         mode |= CSC_BLACK_SCREEN_OFFSET;
7059
7060                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7061         }
7062 }
7063
7064 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7065 {
7066         struct drm_device *dev = crtc->dev;
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7069         enum pipe pipe = intel_crtc->pipe;
7070         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7071         uint32_t val;
7072
7073         val = 0;
7074
7075         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7076                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7077
7078         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7079                 val |= PIPECONF_INTERLACED_ILK;
7080         else
7081                 val |= PIPECONF_PROGRESSIVE;
7082
7083         I915_WRITE(PIPECONF(cpu_transcoder), val);
7084         POSTING_READ(PIPECONF(cpu_transcoder));
7085
7086         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7087         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7088
7089         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7090                 val = 0;
7091
7092                 switch (intel_crtc->config.pipe_bpp) {
7093                 case 18:
7094                         val |= PIPEMISC_DITHER_6_BPC;
7095                         break;
7096                 case 24:
7097                         val |= PIPEMISC_DITHER_8_BPC;
7098                         break;
7099                 case 30:
7100                         val |= PIPEMISC_DITHER_10_BPC;
7101                         break;
7102                 case 36:
7103                         val |= PIPEMISC_DITHER_12_BPC;
7104                         break;
7105                 default:
7106                         /* Case prevented by pipe_config_set_bpp. */
7107                         BUG();
7108                 }
7109
7110                 if (intel_crtc->config.dither)
7111                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7112
7113                 I915_WRITE(PIPEMISC(pipe), val);
7114         }
7115 }
7116
7117 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7118                                     intel_clock_t *clock,
7119                                     bool *has_reduced_clock,
7120                                     intel_clock_t *reduced_clock)
7121 {
7122         struct drm_device *dev = crtc->dev;
7123         struct drm_i915_private *dev_priv = dev->dev_private;
7124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125         int refclk;
7126         const intel_limit_t *limit;
7127         bool ret, is_lvds = false;
7128
7129         is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
7130
7131         refclk = ironlake_get_refclk(crtc);
7132
7133         /*
7134          * Returns a set of divisors for the desired target clock with the given
7135          * refclk, or FALSE.  The returned values represent the clock equation:
7136          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7137          */
7138         limit = intel_limit(intel_crtc, refclk);
7139         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7140                                           intel_crtc->config.port_clock,
7141                                           refclk, NULL, clock);
7142         if (!ret)
7143                 return false;
7144
7145         if (is_lvds && dev_priv->lvds_downclock_avail) {
7146                 /*
7147                  * Ensure we match the reduced clock's P to the target clock.
7148                  * If the clocks don't match, we can't switch the display clock
7149                  * by using the FP0/FP1. In such case we will disable the LVDS
7150                  * downclock feature.
7151                 */
7152                 *has_reduced_clock =
7153                         dev_priv->display.find_dpll(limit, intel_crtc,
7154                                                     dev_priv->lvds_downclock,
7155                                                     refclk, clock,
7156                                                     reduced_clock);
7157         }
7158
7159         return true;
7160 }
7161
7162 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7163 {
7164         /*
7165          * Account for spread spectrum to avoid
7166          * oversubscribing the link. Max center spread
7167          * is 2.5%; use 5% for safety's sake.
7168          */
7169         u32 bps = target_clock * bpp * 21 / 20;
7170         return DIV_ROUND_UP(bps, link_bw * 8);
7171 }
7172
7173 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7174 {
7175         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7176 }
7177
7178 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7179                                       u32 *fp,
7180                                       intel_clock_t *reduced_clock, u32 *fp2)
7181 {
7182         struct drm_crtc *crtc = &intel_crtc->base;
7183         struct drm_device *dev = crtc->dev;
7184         struct drm_i915_private *dev_priv = dev->dev_private;
7185         struct intel_encoder *intel_encoder;
7186         uint32_t dpll;
7187         int factor, num_connectors = 0;
7188         bool is_lvds = false, is_sdvo = false;
7189
7190         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7191                 switch (intel_encoder->type) {
7192                 case INTEL_OUTPUT_LVDS:
7193                         is_lvds = true;
7194                         break;
7195                 case INTEL_OUTPUT_SDVO:
7196                 case INTEL_OUTPUT_HDMI:
7197                         is_sdvo = true;
7198                         break;
7199                 default:
7200                         break;
7201                 }
7202
7203                 num_connectors++;
7204         }
7205
7206         /* Enable autotuning of the PLL clock (if permissible) */
7207         factor = 21;
7208         if (is_lvds) {
7209                 if ((intel_panel_use_ssc(dev_priv) &&
7210                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7211                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7212                         factor = 25;
7213         } else if (intel_crtc->config.sdvo_tv_clock)
7214                 factor = 20;
7215
7216         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7217                 *fp |= FP_CB_TUNE;
7218
7219         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7220                 *fp2 |= FP_CB_TUNE;
7221
7222         dpll = 0;
7223
7224         if (is_lvds)
7225                 dpll |= DPLLB_MODE_LVDS;
7226         else
7227                 dpll |= DPLLB_MODE_DAC_SERIAL;
7228
7229         dpll |= (intel_crtc->config.pixel_multiplier - 1)
7230                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7231
7232         if (is_sdvo)
7233                 dpll |= DPLL_SDVO_HIGH_SPEED;
7234         if (intel_crtc->config.has_dp_encoder)
7235                 dpll |= DPLL_SDVO_HIGH_SPEED;
7236
7237         /* compute bitmask from p1 value */
7238         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7239         /* also FPA1 */
7240         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7241
7242         switch (intel_crtc->config.dpll.p2) {
7243         case 5:
7244                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7245                 break;
7246         case 7:
7247                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7248                 break;
7249         case 10:
7250                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7251                 break;
7252         case 14:
7253                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7254                 break;
7255         }
7256
7257         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7258                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7259         else
7260                 dpll |= PLL_REF_INPUT_DREFCLK;
7261
7262         return dpll | DPLL_VCO_ENABLE;
7263 }
7264
7265 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7266                                   int x, int y,
7267                                   struct drm_framebuffer *fb)
7268 {
7269         struct drm_device *dev = crtc->base.dev;
7270         intel_clock_t clock, reduced_clock;
7271         u32 dpll = 0, fp = 0, fp2 = 0;
7272         bool ok, has_reduced_clock = false;
7273         bool is_lvds = false;
7274         struct intel_shared_dpll *pll;
7275
7276         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7277
7278         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7279              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7280
7281         ok = ironlake_compute_clocks(&crtc->base, &clock,
7282                                      &has_reduced_clock, &reduced_clock);
7283         if (!ok && !crtc->config.clock_set) {
7284                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7285                 return -EINVAL;
7286         }
7287         /* Compat-code for transition, will disappear. */
7288         if (!crtc->config.clock_set) {
7289                 crtc->config.dpll.n = clock.n;
7290                 crtc->config.dpll.m1 = clock.m1;
7291                 crtc->config.dpll.m2 = clock.m2;
7292                 crtc->config.dpll.p1 = clock.p1;
7293                 crtc->config.dpll.p2 = clock.p2;
7294         }
7295
7296         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7297         if (crtc->config.has_pch_encoder) {
7298                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
7299                 if (has_reduced_clock)
7300                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7301
7302                 dpll = ironlake_compute_dpll(crtc,
7303                                              &fp, &reduced_clock,
7304                                              has_reduced_clock ? &fp2 : NULL);
7305
7306                 crtc->config.dpll_hw_state.dpll = dpll;
7307                 crtc->config.dpll_hw_state.fp0 = fp;
7308                 if (has_reduced_clock)
7309                         crtc->config.dpll_hw_state.fp1 = fp2;
7310                 else
7311                         crtc->config.dpll_hw_state.fp1 = fp;
7312
7313                 pll = intel_get_shared_dpll(crtc);
7314                 if (pll == NULL) {
7315                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7316                                          pipe_name(crtc->pipe));
7317                         return -EINVAL;
7318                 }
7319         } else
7320                 intel_put_shared_dpll(crtc);
7321
7322         if (is_lvds && has_reduced_clock && i915.powersave)
7323                 crtc->lowfreq_avail = true;
7324         else
7325                 crtc->lowfreq_avail = false;
7326
7327         return 0;
7328 }
7329
7330 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7331                                          struct intel_link_m_n *m_n)
7332 {
7333         struct drm_device *dev = crtc->base.dev;
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335         enum pipe pipe = crtc->pipe;
7336
7337         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7338         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7339         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7340                 & ~TU_SIZE_MASK;
7341         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7342         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7343                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7344 }
7345
7346 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7347                                          enum transcoder transcoder,
7348                                          struct intel_link_m_n *m_n,
7349                                          struct intel_link_m_n *m2_n2)
7350 {
7351         struct drm_device *dev = crtc->base.dev;
7352         struct drm_i915_private *dev_priv = dev->dev_private;
7353         enum pipe pipe = crtc->pipe;
7354
7355         if (INTEL_INFO(dev)->gen >= 5) {
7356                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7357                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7358                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7359                         & ~TU_SIZE_MASK;
7360                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7361                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7362                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7363                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7364                  * gen < 8) and if DRRS is supported (to make sure the
7365                  * registers are not unnecessarily read).
7366                  */
7367                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7368                         crtc->config.has_drrs) {
7369                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7370                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7371                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7372                                         & ~TU_SIZE_MASK;
7373                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7374                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7375                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7376                 }
7377         } else {
7378                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7379                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7380                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7381                         & ~TU_SIZE_MASK;
7382                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7383                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7384                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7385         }
7386 }
7387
7388 void intel_dp_get_m_n(struct intel_crtc *crtc,
7389                       struct intel_crtc_config *pipe_config)
7390 {
7391         if (crtc->config.has_pch_encoder)
7392                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7393         else
7394                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7395                                              &pipe_config->dp_m_n,
7396                                              &pipe_config->dp_m2_n2);
7397 }
7398
7399 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7400                                         struct intel_crtc_config *pipe_config)
7401 {
7402         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7403                                      &pipe_config->fdi_m_n, NULL);
7404 }
7405
7406 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7407                                      struct intel_crtc_config *pipe_config)
7408 {
7409         struct drm_device *dev = crtc->base.dev;
7410         struct drm_i915_private *dev_priv = dev->dev_private;
7411         uint32_t tmp;
7412
7413         tmp = I915_READ(PF_CTL(crtc->pipe));
7414
7415         if (tmp & PF_ENABLE) {
7416                 pipe_config->pch_pfit.enabled = true;
7417                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7418                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7419
7420                 /* We currently do not free assignements of panel fitters on
7421                  * ivb/hsw (since we don't use the higher upscaling modes which
7422                  * differentiates them) so just WARN about this case for now. */
7423                 if (IS_GEN7(dev)) {
7424                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7425                                 PF_PIPE_SEL_IVB(crtc->pipe));
7426                 }
7427         }
7428 }
7429
7430 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7431                                       struct intel_plane_config *plane_config)
7432 {
7433         struct drm_device *dev = crtc->base.dev;
7434         struct drm_i915_private *dev_priv = dev->dev_private;
7435         u32 val, base, offset;
7436         int pipe = crtc->pipe, plane = crtc->plane;
7437         int fourcc, pixel_format;
7438         int aligned_height;
7439
7440         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7441         if (!crtc->base.primary->fb) {
7442                 DRM_DEBUG_KMS("failed to alloc fb\n");
7443                 return;
7444         }
7445
7446         val = I915_READ(DSPCNTR(plane));
7447
7448         if (INTEL_INFO(dev)->gen >= 4)
7449                 if (val & DISPPLANE_TILED)
7450                         plane_config->tiled = true;
7451
7452         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7453         fourcc = intel_format_to_fourcc(pixel_format);
7454         crtc->base.primary->fb->pixel_format = fourcc;
7455         crtc->base.primary->fb->bits_per_pixel =
7456                 drm_format_plane_cpp(fourcc, 0) * 8;
7457
7458         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7459         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7460                 offset = I915_READ(DSPOFFSET(plane));
7461         } else {
7462                 if (plane_config->tiled)
7463                         offset = I915_READ(DSPTILEOFF(plane));
7464                 else
7465                         offset = I915_READ(DSPLINOFF(plane));
7466         }
7467         plane_config->base = base;
7468
7469         val = I915_READ(PIPESRC(pipe));
7470         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7471         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7472
7473         val = I915_READ(DSPSTRIDE(pipe));
7474         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7475
7476         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7477                                             plane_config->tiled);
7478
7479         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7480                                         aligned_height);
7481
7482         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7483                       pipe, plane, crtc->base.primary->fb->width,
7484                       crtc->base.primary->fb->height,
7485                       crtc->base.primary->fb->bits_per_pixel, base,
7486                       crtc->base.primary->fb->pitches[0],
7487                       plane_config->size);
7488 }
7489
7490 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7491                                      struct intel_crtc_config *pipe_config)
7492 {
7493         struct drm_device *dev = crtc->base.dev;
7494         struct drm_i915_private *dev_priv = dev->dev_private;
7495         uint32_t tmp;
7496
7497         if (!intel_display_power_is_enabled(dev_priv,
7498                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7499                 return false;
7500
7501         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7502         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7503
7504         tmp = I915_READ(PIPECONF(crtc->pipe));
7505         if (!(tmp & PIPECONF_ENABLE))
7506                 return false;
7507
7508         switch (tmp & PIPECONF_BPC_MASK) {
7509         case PIPECONF_6BPC:
7510                 pipe_config->pipe_bpp = 18;
7511                 break;
7512         case PIPECONF_8BPC:
7513                 pipe_config->pipe_bpp = 24;
7514                 break;
7515         case PIPECONF_10BPC:
7516                 pipe_config->pipe_bpp = 30;
7517                 break;
7518         case PIPECONF_12BPC:
7519                 pipe_config->pipe_bpp = 36;
7520                 break;
7521         default:
7522                 break;
7523         }
7524
7525         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7526                 pipe_config->limited_color_range = true;
7527
7528         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7529                 struct intel_shared_dpll *pll;
7530
7531                 pipe_config->has_pch_encoder = true;
7532
7533                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7534                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7535                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7536
7537                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7538
7539                 if (HAS_PCH_IBX(dev_priv->dev)) {
7540                         pipe_config->shared_dpll =
7541                                 (enum intel_dpll_id) crtc->pipe;
7542                 } else {
7543                         tmp = I915_READ(PCH_DPLL_SEL);
7544                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7545                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7546                         else
7547                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7548                 }
7549
7550                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7551
7552                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7553                                            &pipe_config->dpll_hw_state));
7554
7555                 tmp = pipe_config->dpll_hw_state.dpll;
7556                 pipe_config->pixel_multiplier =
7557                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7558                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7559
7560                 ironlake_pch_clock_get(crtc, pipe_config);
7561         } else {
7562                 pipe_config->pixel_multiplier = 1;
7563         }
7564
7565         intel_get_pipe_timings(crtc, pipe_config);
7566
7567         ironlake_get_pfit_config(crtc, pipe_config);
7568
7569         return true;
7570 }
7571
7572 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7573 {
7574         struct drm_device *dev = dev_priv->dev;
7575         struct intel_crtc *crtc;
7576
7577         for_each_intel_crtc(dev, crtc)
7578                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7579                      pipe_name(crtc->pipe));
7580
7581         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7582         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7583         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7584         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7585         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7586         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7587              "CPU PWM1 enabled\n");
7588         if (IS_HASWELL(dev))
7589                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7590                      "CPU PWM2 enabled\n");
7591         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7592              "PCH PWM1 enabled\n");
7593         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7594              "Utility pin enabled\n");
7595         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7596
7597         /*
7598          * In theory we can still leave IRQs enabled, as long as only the HPD
7599          * interrupts remain enabled. We used to check for that, but since it's
7600          * gen-specific and since we only disable LCPLL after we fully disable
7601          * the interrupts, the check below should be enough.
7602          */
7603         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7604 }
7605
7606 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7607 {
7608         struct drm_device *dev = dev_priv->dev;
7609
7610         if (IS_HASWELL(dev))
7611                 return I915_READ(D_COMP_HSW);
7612         else
7613                 return I915_READ(D_COMP_BDW);
7614 }
7615
7616 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7617 {
7618         struct drm_device *dev = dev_priv->dev;
7619
7620         if (IS_HASWELL(dev)) {
7621                 mutex_lock(&dev_priv->rps.hw_lock);
7622                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7623                                             val))
7624                         DRM_ERROR("Failed to write to D_COMP\n");
7625                 mutex_unlock(&dev_priv->rps.hw_lock);
7626         } else {
7627                 I915_WRITE(D_COMP_BDW, val);
7628                 POSTING_READ(D_COMP_BDW);
7629         }
7630 }
7631
7632 /*
7633  * This function implements pieces of two sequences from BSpec:
7634  * - Sequence for display software to disable LCPLL
7635  * - Sequence for display software to allow package C8+
7636  * The steps implemented here are just the steps that actually touch the LCPLL
7637  * register. Callers should take care of disabling all the display engine
7638  * functions, doing the mode unset, fixing interrupts, etc.
7639  */
7640 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7641                               bool switch_to_fclk, bool allow_power_down)
7642 {
7643         uint32_t val;
7644
7645         assert_can_disable_lcpll(dev_priv);
7646
7647         val = I915_READ(LCPLL_CTL);
7648
7649         if (switch_to_fclk) {
7650                 val |= LCPLL_CD_SOURCE_FCLK;
7651                 I915_WRITE(LCPLL_CTL, val);
7652
7653                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7654                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7655                         DRM_ERROR("Switching to FCLK failed\n");
7656
7657                 val = I915_READ(LCPLL_CTL);
7658         }
7659
7660         val |= LCPLL_PLL_DISABLE;
7661         I915_WRITE(LCPLL_CTL, val);
7662         POSTING_READ(LCPLL_CTL);
7663
7664         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7665                 DRM_ERROR("LCPLL still locked\n");
7666
7667         val = hsw_read_dcomp(dev_priv);
7668         val |= D_COMP_COMP_DISABLE;
7669         hsw_write_dcomp(dev_priv, val);
7670         ndelay(100);
7671
7672         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7673                      1))
7674                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7675
7676         if (allow_power_down) {
7677                 val = I915_READ(LCPLL_CTL);
7678                 val |= LCPLL_POWER_DOWN_ALLOW;
7679                 I915_WRITE(LCPLL_CTL, val);
7680                 POSTING_READ(LCPLL_CTL);
7681         }
7682 }
7683
7684 /*
7685  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7686  * source.
7687  */
7688 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7689 {
7690         uint32_t val;
7691
7692         val = I915_READ(LCPLL_CTL);
7693
7694         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7695                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7696                 return;
7697
7698         /*
7699          * Make sure we're not on PC8 state before disabling PC8, otherwise
7700          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7701          *
7702          * The other problem is that hsw_restore_lcpll() is called as part of
7703          * the runtime PM resume sequence, so we can't just call
7704          * gen6_gt_force_wake_get() because that function calls
7705          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7706          * while we are on the resume sequence. So to solve this problem we have
7707          * to call special forcewake code that doesn't touch runtime PM and
7708          * doesn't enable the forcewake delayed work.
7709          */
7710         spin_lock_irq(&dev_priv->uncore.lock);
7711         if (dev_priv->uncore.forcewake_count++ == 0)
7712                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7713         spin_unlock_irq(&dev_priv->uncore.lock);
7714
7715         if (val & LCPLL_POWER_DOWN_ALLOW) {
7716                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7717                 I915_WRITE(LCPLL_CTL, val);
7718                 POSTING_READ(LCPLL_CTL);
7719         }
7720
7721         val = hsw_read_dcomp(dev_priv);
7722         val |= D_COMP_COMP_FORCE;
7723         val &= ~D_COMP_COMP_DISABLE;
7724         hsw_write_dcomp(dev_priv, val);
7725
7726         val = I915_READ(LCPLL_CTL);
7727         val &= ~LCPLL_PLL_DISABLE;
7728         I915_WRITE(LCPLL_CTL, val);
7729
7730         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7731                 DRM_ERROR("LCPLL not locked yet\n");
7732
7733         if (val & LCPLL_CD_SOURCE_FCLK) {
7734                 val = I915_READ(LCPLL_CTL);
7735                 val &= ~LCPLL_CD_SOURCE_FCLK;
7736                 I915_WRITE(LCPLL_CTL, val);
7737
7738                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7739                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7740                         DRM_ERROR("Switching back to LCPLL failed\n");
7741         }
7742
7743         /* See the big comment above. */
7744         spin_lock_irq(&dev_priv->uncore.lock);
7745         if (--dev_priv->uncore.forcewake_count == 0)
7746                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7747         spin_unlock_irq(&dev_priv->uncore.lock);
7748 }
7749
7750 /*
7751  * Package states C8 and deeper are really deep PC states that can only be
7752  * reached when all the devices on the system allow it, so even if the graphics
7753  * device allows PC8+, it doesn't mean the system will actually get to these
7754  * states. Our driver only allows PC8+ when going into runtime PM.
7755  *
7756  * The requirements for PC8+ are that all the outputs are disabled, the power
7757  * well is disabled and most interrupts are disabled, and these are also
7758  * requirements for runtime PM. When these conditions are met, we manually do
7759  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7760  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7761  * hang the machine.
7762  *
7763  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7764  * the state of some registers, so when we come back from PC8+ we need to
7765  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7766  * need to take care of the registers kept by RC6. Notice that this happens even
7767  * if we don't put the device in PCI D3 state (which is what currently happens
7768  * because of the runtime PM support).
7769  *
7770  * For more, read "Display Sequences for Package C8" on the hardware
7771  * documentation.
7772  */
7773 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7774 {
7775         struct drm_device *dev = dev_priv->dev;
7776         uint32_t val;
7777
7778         DRM_DEBUG_KMS("Enabling package C8+\n");
7779
7780         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7781                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7782                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7783                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7784         }
7785
7786         lpt_disable_clkout_dp(dev);
7787         hsw_disable_lcpll(dev_priv, true, true);
7788 }
7789
7790 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7791 {
7792         struct drm_device *dev = dev_priv->dev;
7793         uint32_t val;
7794
7795         DRM_DEBUG_KMS("Disabling package C8+\n");
7796
7797         hsw_restore_lcpll(dev_priv);
7798         lpt_init_pch_refclk(dev);
7799
7800         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7801                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7802                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7803                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7804         }
7805
7806         intel_prepare_ddi(dev);
7807 }
7808
7809 static void snb_modeset_global_resources(struct drm_device *dev)
7810 {
7811         modeset_update_crtc_power_domains(dev);
7812 }
7813
7814 static void haswell_modeset_global_resources(struct drm_device *dev)
7815 {
7816         modeset_update_crtc_power_domains(dev);
7817 }
7818
7819 static int haswell_crtc_mode_set(struct intel_crtc *crtc,
7820                                  int x, int y,
7821                                  struct drm_framebuffer *fb)
7822 {
7823         if (!intel_ddi_pll_select(crtc))
7824                 return -EINVAL;
7825
7826         crtc->lowfreq_avail = false;
7827
7828         return 0;
7829 }
7830
7831 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7832                                 enum port port,
7833                                 struct intel_crtc_config *pipe_config)
7834 {
7835         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7836
7837         switch (pipe_config->ddi_pll_sel) {
7838         case PORT_CLK_SEL_WRPLL1:
7839                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7840                 break;
7841         case PORT_CLK_SEL_WRPLL2:
7842                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7843                 break;
7844         }
7845 }
7846
7847 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7848                                        struct intel_crtc_config *pipe_config)
7849 {
7850         struct drm_device *dev = crtc->base.dev;
7851         struct drm_i915_private *dev_priv = dev->dev_private;
7852         struct intel_shared_dpll *pll;
7853         enum port port;
7854         uint32_t tmp;
7855
7856         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7857
7858         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7859
7860         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7861
7862         if (pipe_config->shared_dpll >= 0) {
7863                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7864
7865                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7866                                            &pipe_config->dpll_hw_state));
7867         }
7868
7869         /*
7870          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7871          * DDI E. So just check whether this pipe is wired to DDI E and whether
7872          * the PCH transcoder is on.
7873          */
7874         if (INTEL_INFO(dev)->gen < 9 &&
7875             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7876                 pipe_config->has_pch_encoder = true;
7877
7878                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7879                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7880                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7881
7882                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7883         }
7884 }
7885
7886 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7887                                     struct intel_crtc_config *pipe_config)
7888 {
7889         struct drm_device *dev = crtc->base.dev;
7890         struct drm_i915_private *dev_priv = dev->dev_private;
7891         enum intel_display_power_domain pfit_domain;
7892         uint32_t tmp;
7893
7894         if (!intel_display_power_is_enabled(dev_priv,
7895                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7896                 return false;
7897
7898         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7899         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7900
7901         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7902         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7903                 enum pipe trans_edp_pipe;
7904                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7905                 default:
7906                         WARN(1, "unknown pipe linked to edp transcoder\n");
7907                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7908                 case TRANS_DDI_EDP_INPUT_A_ON:
7909                         trans_edp_pipe = PIPE_A;
7910                         break;
7911                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7912                         trans_edp_pipe = PIPE_B;
7913                         break;
7914                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7915                         trans_edp_pipe = PIPE_C;
7916                         break;
7917                 }
7918
7919                 if (trans_edp_pipe == crtc->pipe)
7920                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7921         }
7922
7923         if (!intel_display_power_is_enabled(dev_priv,
7924                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7925                 return false;
7926
7927         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7928         if (!(tmp & PIPECONF_ENABLE))
7929                 return false;
7930
7931         haswell_get_ddi_port_state(crtc, pipe_config);
7932
7933         intel_get_pipe_timings(crtc, pipe_config);
7934
7935         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7936         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
7937                 ironlake_get_pfit_config(crtc, pipe_config);
7938
7939         if (IS_HASWELL(dev))
7940                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7941                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7942
7943         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7944                 pipe_config->pixel_multiplier =
7945                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7946         } else {
7947                 pipe_config->pixel_multiplier = 1;
7948         }
7949
7950         return true;
7951 }
7952
7953 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7954 {
7955         struct drm_device *dev = crtc->dev;
7956         struct drm_i915_private *dev_priv = dev->dev_private;
7957         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7958         uint32_t cntl = 0, size = 0;
7959
7960         if (base) {
7961                 unsigned int width = intel_crtc->cursor_width;
7962                 unsigned int height = intel_crtc->cursor_height;
7963                 unsigned int stride = roundup_pow_of_two(width) * 4;
7964
7965                 switch (stride) {
7966                 default:
7967                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
7968                                   width, stride);
7969                         stride = 256;
7970                         /* fallthrough */
7971                 case 256:
7972                 case 512:
7973                 case 1024:
7974                 case 2048:
7975                         break;
7976                 }
7977
7978                 cntl |= CURSOR_ENABLE |
7979                         CURSOR_GAMMA_ENABLE |
7980                         CURSOR_FORMAT_ARGB |
7981                         CURSOR_STRIDE(stride);
7982
7983                 size = (height << 12) | width;
7984         }
7985
7986         if (intel_crtc->cursor_cntl != 0 &&
7987             (intel_crtc->cursor_base != base ||
7988              intel_crtc->cursor_size != size ||
7989              intel_crtc->cursor_cntl != cntl)) {
7990                 /* On these chipsets we can only modify the base/size/stride
7991                  * whilst the cursor is disabled.
7992                  */
7993                 I915_WRITE(_CURACNTR, 0);
7994                 POSTING_READ(_CURACNTR);
7995                 intel_crtc->cursor_cntl = 0;
7996         }
7997
7998         if (intel_crtc->cursor_base != base) {
7999                 I915_WRITE(_CURABASE, base);
8000                 intel_crtc->cursor_base = base;
8001         }
8002
8003         if (intel_crtc->cursor_size != size) {
8004                 I915_WRITE(CURSIZE, size);
8005                 intel_crtc->cursor_size = size;
8006         }
8007
8008         if (intel_crtc->cursor_cntl != cntl) {
8009                 I915_WRITE(_CURACNTR, cntl);
8010                 POSTING_READ(_CURACNTR);
8011                 intel_crtc->cursor_cntl = cntl;
8012         }
8013 }
8014
8015 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8016 {
8017         struct drm_device *dev = crtc->dev;
8018         struct drm_i915_private *dev_priv = dev->dev_private;
8019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8020         int pipe = intel_crtc->pipe;
8021         uint32_t cntl;
8022
8023         cntl = 0;
8024         if (base) {
8025                 cntl = MCURSOR_GAMMA_ENABLE;
8026                 switch (intel_crtc->cursor_width) {
8027                         case 64:
8028                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8029                                 break;
8030                         case 128:
8031                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8032                                 break;
8033                         case 256:
8034                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8035                                 break;
8036                         default:
8037                                 WARN_ON(1);
8038                                 return;
8039                 }
8040                 cntl |= pipe << 28; /* Connect to correct pipe */
8041
8042                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8043                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8044         }
8045
8046         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8047                 cntl |= CURSOR_ROTATE_180;
8048
8049         if (intel_crtc->cursor_cntl != cntl) {
8050                 I915_WRITE(CURCNTR(pipe), cntl);
8051                 POSTING_READ(CURCNTR(pipe));
8052                 intel_crtc->cursor_cntl = cntl;
8053         }
8054
8055         /* and commit changes on next vblank */
8056         I915_WRITE(CURBASE(pipe), base);
8057         POSTING_READ(CURBASE(pipe));
8058
8059         intel_crtc->cursor_base = base;
8060 }
8061
8062 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8063 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8064                                      bool on)
8065 {
8066         struct drm_device *dev = crtc->dev;
8067         struct drm_i915_private *dev_priv = dev->dev_private;
8068         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8069         int pipe = intel_crtc->pipe;
8070         int x = crtc->cursor_x;
8071         int y = crtc->cursor_y;
8072         u32 base = 0, pos = 0;
8073
8074         if (on)
8075                 base = intel_crtc->cursor_addr;
8076
8077         if (x >= intel_crtc->config.pipe_src_w)
8078                 base = 0;
8079
8080         if (y >= intel_crtc->config.pipe_src_h)
8081                 base = 0;
8082
8083         if (x < 0) {
8084                 if (x + intel_crtc->cursor_width <= 0)
8085                         base = 0;
8086
8087                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8088                 x = -x;
8089         }
8090         pos |= x << CURSOR_X_SHIFT;
8091
8092         if (y < 0) {
8093                 if (y + intel_crtc->cursor_height <= 0)
8094                         base = 0;
8095
8096                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8097                 y = -y;
8098         }
8099         pos |= y << CURSOR_Y_SHIFT;
8100
8101         if (base == 0 && intel_crtc->cursor_base == 0)
8102                 return;
8103
8104         I915_WRITE(CURPOS(pipe), pos);
8105
8106         /* ILK+ do this automagically */
8107         if (HAS_GMCH_DISPLAY(dev) &&
8108                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8109                 base += (intel_crtc->cursor_height *
8110                         intel_crtc->cursor_width - 1) * 4;
8111         }
8112
8113         if (IS_845G(dev) || IS_I865G(dev))
8114                 i845_update_cursor(crtc, base);
8115         else
8116                 i9xx_update_cursor(crtc, base);
8117 }
8118
8119 static bool cursor_size_ok(struct drm_device *dev,
8120                            uint32_t width, uint32_t height)
8121 {
8122         if (width == 0 || height == 0)
8123                 return false;
8124
8125         /*
8126          * 845g/865g are special in that they are only limited by
8127          * the width of their cursors, the height is arbitrary up to
8128          * the precision of the register. Everything else requires
8129          * square cursors, limited to a few power-of-two sizes.
8130          */
8131         if (IS_845G(dev) || IS_I865G(dev)) {
8132                 if ((width & 63) != 0)
8133                         return false;
8134
8135                 if (width > (IS_845G(dev) ? 64 : 512))
8136                         return false;
8137
8138                 if (height > 1023)
8139                         return false;
8140         } else {
8141                 switch (width | height) {
8142                 case 256:
8143                 case 128:
8144                         if (IS_GEN2(dev))
8145                                 return false;
8146                 case 64:
8147                         break;
8148                 default:
8149                         return false;
8150                 }
8151         }
8152
8153         return true;
8154 }
8155
8156 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8157                                      struct drm_i915_gem_object *obj,
8158                                      uint32_t width, uint32_t height)
8159 {
8160         struct drm_device *dev = crtc->dev;
8161         struct drm_i915_private *dev_priv = dev->dev_private;
8162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8163         enum pipe pipe = intel_crtc->pipe;
8164         unsigned old_width;
8165         uint32_t addr;
8166         int ret;
8167
8168         /* if we want to turn off the cursor ignore width and height */
8169         if (!obj) {
8170                 DRM_DEBUG_KMS("cursor off\n");
8171                 addr = 0;
8172                 mutex_lock(&dev->struct_mutex);
8173                 goto finish;
8174         }
8175
8176         /* we only need to pin inside GTT if cursor is non-phy */
8177         mutex_lock(&dev->struct_mutex);
8178         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8179                 unsigned alignment;
8180
8181                 /*
8182                  * Global gtt pte registers are special registers which actually
8183                  * forward writes to a chunk of system memory. Which means that
8184                  * there is no risk that the register values disappear as soon
8185                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8186                  * only the pin/unpin/fence and not more.
8187                  */
8188                 intel_runtime_pm_get(dev_priv);
8189
8190                 /* Note that the w/a also requires 2 PTE of padding following
8191                  * the bo. We currently fill all unused PTE with the shadow
8192                  * page and so we should always have valid PTE following the
8193                  * cursor preventing the VT-d warning.
8194                  */
8195                 alignment = 0;
8196                 if (need_vtd_wa(dev))
8197                         alignment = 64*1024;
8198
8199                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8200                 if (ret) {
8201                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8202                         intel_runtime_pm_put(dev_priv);
8203                         goto fail_locked;
8204                 }
8205
8206                 ret = i915_gem_object_put_fence(obj);
8207                 if (ret) {
8208                         DRM_DEBUG_KMS("failed to release fence for cursor");
8209                         intel_runtime_pm_put(dev_priv);
8210                         goto fail_unpin;
8211                 }
8212
8213                 addr = i915_gem_obj_ggtt_offset(obj);
8214
8215                 intel_runtime_pm_put(dev_priv);
8216         } else {
8217                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8218                 ret = i915_gem_object_attach_phys(obj, align);
8219                 if (ret) {
8220                         DRM_DEBUG_KMS("failed to attach phys object\n");
8221                         goto fail_locked;
8222                 }
8223                 addr = obj->phys_handle->busaddr;
8224         }
8225
8226  finish:
8227         if (intel_crtc->cursor_bo) {
8228                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8229                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8230         }
8231
8232         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8233                           INTEL_FRONTBUFFER_CURSOR(pipe));
8234         mutex_unlock(&dev->struct_mutex);
8235
8236         old_width = intel_crtc->cursor_width;
8237
8238         intel_crtc->cursor_addr = addr;
8239         intel_crtc->cursor_bo = obj;
8240         intel_crtc->cursor_width = width;
8241         intel_crtc->cursor_height = height;
8242
8243         if (intel_crtc->active) {
8244                 if (old_width != width)
8245                         intel_update_watermarks(crtc);
8246                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8247
8248                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8249         }
8250
8251         return 0;
8252 fail_unpin:
8253         i915_gem_object_unpin_from_display_plane(obj);
8254 fail_locked:
8255         mutex_unlock(&dev->struct_mutex);
8256         return ret;
8257 }
8258
8259 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8260                                  u16 *blue, uint32_t start, uint32_t size)
8261 {
8262         int end = (start + size > 256) ? 256 : start + size, i;
8263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8264
8265         for (i = start; i < end; i++) {
8266                 intel_crtc->lut_r[i] = red[i] >> 8;
8267                 intel_crtc->lut_g[i] = green[i] >> 8;
8268                 intel_crtc->lut_b[i] = blue[i] >> 8;
8269         }
8270
8271         intel_crtc_load_lut(crtc);
8272 }
8273
8274 /* VESA 640x480x72Hz mode to set on the pipe */
8275 static struct drm_display_mode load_detect_mode = {
8276         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8277                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8278 };
8279
8280 struct drm_framebuffer *
8281 __intel_framebuffer_create(struct drm_device *dev,
8282                            struct drm_mode_fb_cmd2 *mode_cmd,
8283                            struct drm_i915_gem_object *obj)
8284 {
8285         struct intel_framebuffer *intel_fb;
8286         int ret;
8287
8288         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8289         if (!intel_fb) {
8290                 drm_gem_object_unreference_unlocked(&obj->base);
8291                 return ERR_PTR(-ENOMEM);
8292         }
8293
8294         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8295         if (ret)
8296                 goto err;
8297
8298         return &intel_fb->base;
8299 err:
8300         drm_gem_object_unreference_unlocked(&obj->base);
8301         kfree(intel_fb);
8302
8303         return ERR_PTR(ret);
8304 }
8305
8306 static struct drm_framebuffer *
8307 intel_framebuffer_create(struct drm_device *dev,
8308                          struct drm_mode_fb_cmd2 *mode_cmd,
8309                          struct drm_i915_gem_object *obj)
8310 {
8311         struct drm_framebuffer *fb;
8312         int ret;
8313
8314         ret = i915_mutex_lock_interruptible(dev);
8315         if (ret)
8316                 return ERR_PTR(ret);
8317         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8318         mutex_unlock(&dev->struct_mutex);
8319
8320         return fb;
8321 }
8322
8323 static u32
8324 intel_framebuffer_pitch_for_width(int width, int bpp)
8325 {
8326         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8327         return ALIGN(pitch, 64);
8328 }
8329
8330 static u32
8331 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8332 {
8333         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8334         return PAGE_ALIGN(pitch * mode->vdisplay);
8335 }
8336
8337 static struct drm_framebuffer *
8338 intel_framebuffer_create_for_mode(struct drm_device *dev,
8339                                   struct drm_display_mode *mode,
8340                                   int depth, int bpp)
8341 {
8342         struct drm_i915_gem_object *obj;
8343         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8344
8345         obj = i915_gem_alloc_object(dev,
8346                                     intel_framebuffer_size_for_mode(mode, bpp));
8347         if (obj == NULL)
8348                 return ERR_PTR(-ENOMEM);
8349
8350         mode_cmd.width = mode->hdisplay;
8351         mode_cmd.height = mode->vdisplay;
8352         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8353                                                                 bpp);
8354         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8355
8356         return intel_framebuffer_create(dev, &mode_cmd, obj);
8357 }
8358
8359 static struct drm_framebuffer *
8360 mode_fits_in_fbdev(struct drm_device *dev,
8361                    struct drm_display_mode *mode)
8362 {
8363 #ifdef CONFIG_DRM_I915_FBDEV
8364         struct drm_i915_private *dev_priv = dev->dev_private;
8365         struct drm_i915_gem_object *obj;
8366         struct drm_framebuffer *fb;
8367
8368         if (!dev_priv->fbdev)
8369                 return NULL;
8370
8371         if (!dev_priv->fbdev->fb)
8372                 return NULL;
8373
8374         obj = dev_priv->fbdev->fb->obj;
8375         BUG_ON(!obj);
8376
8377         fb = &dev_priv->fbdev->fb->base;
8378         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8379                                                                fb->bits_per_pixel))
8380                 return NULL;
8381
8382         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8383                 return NULL;
8384
8385         return fb;
8386 #else
8387         return NULL;
8388 #endif
8389 }
8390
8391 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8392                                 struct drm_display_mode *mode,
8393                                 struct intel_load_detect_pipe *old,
8394                                 struct drm_modeset_acquire_ctx *ctx)
8395 {
8396         struct intel_crtc *intel_crtc;
8397         struct intel_encoder *intel_encoder =
8398                 intel_attached_encoder(connector);
8399         struct drm_crtc *possible_crtc;
8400         struct drm_encoder *encoder = &intel_encoder->base;
8401         struct drm_crtc *crtc = NULL;
8402         struct drm_device *dev = encoder->dev;
8403         struct drm_framebuffer *fb;
8404         struct drm_mode_config *config = &dev->mode_config;
8405         int ret, i = -1;
8406
8407         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8408                       connector->base.id, connector->name,
8409                       encoder->base.id, encoder->name);
8410
8411 retry:
8412         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8413         if (ret)
8414                 goto fail_unlock;
8415
8416         /*
8417          * Algorithm gets a little messy:
8418          *
8419          *   - if the connector already has an assigned crtc, use it (but make
8420          *     sure it's on first)
8421          *
8422          *   - try to find the first unused crtc that can drive this connector,
8423          *     and use that if we find one
8424          */
8425
8426         /* See if we already have a CRTC for this connector */
8427         if (encoder->crtc) {
8428                 crtc = encoder->crtc;
8429
8430                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8431                 if (ret)
8432                         goto fail_unlock;
8433
8434                 old->dpms_mode = connector->dpms;
8435                 old->load_detect_temp = false;
8436
8437                 /* Make sure the crtc and connector are running */
8438                 if (connector->dpms != DRM_MODE_DPMS_ON)
8439                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8440
8441                 return true;
8442         }
8443
8444         /* Find an unused one (if possible) */
8445         for_each_crtc(dev, possible_crtc) {
8446                 i++;
8447                 if (!(encoder->possible_crtcs & (1 << i)))
8448                         continue;
8449                 if (possible_crtc->enabled)
8450                         continue;
8451                 /* This can occur when applying the pipe A quirk on resume. */
8452                 if (to_intel_crtc(possible_crtc)->new_enabled)
8453                         continue;
8454
8455                 crtc = possible_crtc;
8456                 break;
8457         }
8458
8459         /*
8460          * If we didn't find an unused CRTC, don't use any.
8461          */
8462         if (!crtc) {
8463                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8464                 goto fail_unlock;
8465         }
8466
8467         ret = drm_modeset_lock(&crtc->mutex, ctx);
8468         if (ret)
8469                 goto fail_unlock;
8470         intel_encoder->new_crtc = to_intel_crtc(crtc);
8471         to_intel_connector(connector)->new_encoder = intel_encoder;
8472
8473         intel_crtc = to_intel_crtc(crtc);
8474         intel_crtc->new_enabled = true;
8475         intel_crtc->new_config = &intel_crtc->config;
8476         old->dpms_mode = connector->dpms;
8477         old->load_detect_temp = true;
8478         old->release_fb = NULL;
8479
8480         if (!mode)
8481                 mode = &load_detect_mode;
8482
8483         /* We need a framebuffer large enough to accommodate all accesses
8484          * that the plane may generate whilst we perform load detection.
8485          * We can not rely on the fbcon either being present (we get called
8486          * during its initialisation to detect all boot displays, or it may
8487          * not even exist) or that it is large enough to satisfy the
8488          * requested mode.
8489          */
8490         fb = mode_fits_in_fbdev(dev, mode);
8491         if (fb == NULL) {
8492                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8493                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8494                 old->release_fb = fb;
8495         } else
8496                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8497         if (IS_ERR(fb)) {
8498                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8499                 goto fail;
8500         }
8501
8502         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8503                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8504                 if (old->release_fb)
8505                         old->release_fb->funcs->destroy(old->release_fb);
8506                 goto fail;
8507         }
8508
8509         /* let the connector get through one full cycle before testing */
8510         intel_wait_for_vblank(dev, intel_crtc->pipe);
8511         return true;
8512
8513  fail:
8514         intel_crtc->new_enabled = crtc->enabled;
8515         if (intel_crtc->new_enabled)
8516                 intel_crtc->new_config = &intel_crtc->config;
8517         else
8518                 intel_crtc->new_config = NULL;
8519 fail_unlock:
8520         if (ret == -EDEADLK) {
8521                 drm_modeset_backoff(ctx);
8522                 goto retry;
8523         }
8524
8525         return false;
8526 }
8527
8528 void intel_release_load_detect_pipe(struct drm_connector *connector,
8529                                     struct intel_load_detect_pipe *old)
8530 {
8531         struct intel_encoder *intel_encoder =
8532                 intel_attached_encoder(connector);
8533         struct drm_encoder *encoder = &intel_encoder->base;
8534         struct drm_crtc *crtc = encoder->crtc;
8535         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8536
8537         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8538                       connector->base.id, connector->name,
8539                       encoder->base.id, encoder->name);
8540
8541         if (old->load_detect_temp) {
8542                 to_intel_connector(connector)->new_encoder = NULL;
8543                 intel_encoder->new_crtc = NULL;
8544                 intel_crtc->new_enabled = false;
8545                 intel_crtc->new_config = NULL;
8546                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8547
8548                 if (old->release_fb) {
8549                         drm_framebuffer_unregister_private(old->release_fb);
8550                         drm_framebuffer_unreference(old->release_fb);
8551                 }
8552
8553                 return;
8554         }
8555
8556         /* Switch crtc and encoder back off if necessary */
8557         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8558                 connector->funcs->dpms(connector, old->dpms_mode);
8559 }
8560
8561 static int i9xx_pll_refclk(struct drm_device *dev,
8562                            const struct intel_crtc_config *pipe_config)
8563 {
8564         struct drm_i915_private *dev_priv = dev->dev_private;
8565         u32 dpll = pipe_config->dpll_hw_state.dpll;
8566
8567         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8568                 return dev_priv->vbt.lvds_ssc_freq;
8569         else if (HAS_PCH_SPLIT(dev))
8570                 return 120000;
8571         else if (!IS_GEN2(dev))
8572                 return 96000;
8573         else
8574                 return 48000;
8575 }
8576
8577 /* Returns the clock of the currently programmed mode of the given pipe. */
8578 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8579                                 struct intel_crtc_config *pipe_config)
8580 {
8581         struct drm_device *dev = crtc->base.dev;
8582         struct drm_i915_private *dev_priv = dev->dev_private;
8583         int pipe = pipe_config->cpu_transcoder;
8584         u32 dpll = pipe_config->dpll_hw_state.dpll;
8585         u32 fp;
8586         intel_clock_t clock;
8587         int refclk = i9xx_pll_refclk(dev, pipe_config);
8588
8589         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8590                 fp = pipe_config->dpll_hw_state.fp0;
8591         else
8592                 fp = pipe_config->dpll_hw_state.fp1;
8593
8594         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8595         if (IS_PINEVIEW(dev)) {
8596                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8597                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8598         } else {
8599                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8600                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8601         }
8602
8603         if (!IS_GEN2(dev)) {
8604                 if (IS_PINEVIEW(dev))
8605                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8606                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8607                 else
8608                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8609                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8610
8611                 switch (dpll & DPLL_MODE_MASK) {
8612                 case DPLLB_MODE_DAC_SERIAL:
8613                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8614                                 5 : 10;
8615                         break;
8616                 case DPLLB_MODE_LVDS:
8617                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8618                                 7 : 14;
8619                         break;
8620                 default:
8621                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8622                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8623                         return;
8624                 }
8625
8626                 if (IS_PINEVIEW(dev))
8627                         pineview_clock(refclk, &clock);
8628                 else
8629                         i9xx_clock(refclk, &clock);
8630         } else {
8631                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8632                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8633
8634                 if (is_lvds) {
8635                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8636                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8637
8638                         if (lvds & LVDS_CLKB_POWER_UP)
8639                                 clock.p2 = 7;
8640                         else
8641                                 clock.p2 = 14;
8642                 } else {
8643                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8644                                 clock.p1 = 2;
8645                         else {
8646                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8647                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8648                         }
8649                         if (dpll & PLL_P2_DIVIDE_BY_4)
8650                                 clock.p2 = 4;
8651                         else
8652                                 clock.p2 = 2;
8653                 }
8654
8655                 i9xx_clock(refclk, &clock);
8656         }
8657
8658         /*
8659          * This value includes pixel_multiplier. We will use
8660          * port_clock to compute adjusted_mode.crtc_clock in the
8661          * encoder's get_config() function.
8662          */
8663         pipe_config->port_clock = clock.dot;
8664 }
8665
8666 int intel_dotclock_calculate(int link_freq,
8667                              const struct intel_link_m_n *m_n)
8668 {
8669         /*
8670          * The calculation for the data clock is:
8671          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8672          * But we want to avoid losing precison if possible, so:
8673          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8674          *
8675          * and the link clock is simpler:
8676          * link_clock = (m * link_clock) / n
8677          */
8678
8679         if (!m_n->link_n)
8680                 return 0;
8681
8682         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8683 }
8684
8685 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8686                                    struct intel_crtc_config *pipe_config)
8687 {
8688         struct drm_device *dev = crtc->base.dev;
8689
8690         /* read out port_clock from the DPLL */
8691         i9xx_crtc_clock_get(crtc, pipe_config);
8692
8693         /*
8694          * This value does not include pixel_multiplier.
8695          * We will check that port_clock and adjusted_mode.crtc_clock
8696          * agree once we know their relationship in the encoder's
8697          * get_config() function.
8698          */
8699         pipe_config->adjusted_mode.crtc_clock =
8700                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8701                                          &pipe_config->fdi_m_n);
8702 }
8703
8704 /** Returns the currently programmed mode of the given pipe. */
8705 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8706                                              struct drm_crtc *crtc)
8707 {
8708         struct drm_i915_private *dev_priv = dev->dev_private;
8709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8710         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8711         struct drm_display_mode *mode;
8712         struct intel_crtc_config pipe_config;
8713         int htot = I915_READ(HTOTAL(cpu_transcoder));
8714         int hsync = I915_READ(HSYNC(cpu_transcoder));
8715         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8716         int vsync = I915_READ(VSYNC(cpu_transcoder));
8717         enum pipe pipe = intel_crtc->pipe;
8718
8719         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8720         if (!mode)
8721                 return NULL;
8722
8723         /*
8724          * Construct a pipe_config sufficient for getting the clock info
8725          * back out of crtc_clock_get.
8726          *
8727          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8728          * to use a real value here instead.
8729          */
8730         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8731         pipe_config.pixel_multiplier = 1;
8732         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8733         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8734         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8735         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8736
8737         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8738         mode->hdisplay = (htot & 0xffff) + 1;
8739         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8740         mode->hsync_start = (hsync & 0xffff) + 1;
8741         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8742         mode->vdisplay = (vtot & 0xffff) + 1;
8743         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8744         mode->vsync_start = (vsync & 0xffff) + 1;
8745         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8746
8747         drm_mode_set_name(mode);
8748
8749         return mode;
8750 }
8751
8752 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8753 {
8754         struct drm_device *dev = crtc->dev;
8755         struct drm_i915_private *dev_priv = dev->dev_private;
8756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8757
8758         if (!HAS_GMCH_DISPLAY(dev))
8759                 return;
8760
8761         if (!dev_priv->lvds_downclock_avail)
8762                 return;
8763
8764         /*
8765          * Since this is called by a timer, we should never get here in
8766          * the manual case.
8767          */
8768         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8769                 int pipe = intel_crtc->pipe;
8770                 int dpll_reg = DPLL(pipe);
8771                 int dpll;
8772
8773                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8774
8775                 assert_panel_unlocked(dev_priv, pipe);
8776
8777                 dpll = I915_READ(dpll_reg);
8778                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8779                 I915_WRITE(dpll_reg, dpll);
8780                 intel_wait_for_vblank(dev, pipe);
8781                 dpll = I915_READ(dpll_reg);
8782                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8783                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8784         }
8785
8786 }
8787
8788 void intel_mark_busy(struct drm_device *dev)
8789 {
8790         struct drm_i915_private *dev_priv = dev->dev_private;
8791
8792         if (dev_priv->mm.busy)
8793                 return;
8794
8795         intel_runtime_pm_get(dev_priv);
8796         i915_update_gfx_val(dev_priv);
8797         dev_priv->mm.busy = true;
8798 }
8799
8800 void intel_mark_idle(struct drm_device *dev)
8801 {
8802         struct drm_i915_private *dev_priv = dev->dev_private;
8803         struct drm_crtc *crtc;
8804
8805         if (!dev_priv->mm.busy)
8806                 return;
8807
8808         dev_priv->mm.busy = false;
8809
8810         if (!i915.powersave)
8811                 goto out;
8812
8813         for_each_crtc(dev, crtc) {
8814                 if (!crtc->primary->fb)
8815                         continue;
8816
8817                 intel_decrease_pllclock(crtc);
8818         }
8819
8820         if (INTEL_INFO(dev)->gen >= 6)
8821                 gen6_rps_idle(dev->dev_private);
8822
8823 out:
8824         intel_runtime_pm_put(dev_priv);
8825 }
8826
8827 static void intel_crtc_destroy(struct drm_crtc *crtc)
8828 {
8829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8830         struct drm_device *dev = crtc->dev;
8831         struct intel_unpin_work *work;
8832
8833         spin_lock_irq(&dev->event_lock);
8834         work = intel_crtc->unpin_work;
8835         intel_crtc->unpin_work = NULL;
8836         spin_unlock_irq(&dev->event_lock);
8837
8838         if (work) {
8839                 cancel_work_sync(&work->work);
8840                 kfree(work);
8841         }
8842
8843         drm_crtc_cleanup(crtc);
8844
8845         kfree(intel_crtc);
8846 }
8847
8848 static void intel_unpin_work_fn(struct work_struct *__work)
8849 {
8850         struct intel_unpin_work *work =
8851                 container_of(__work, struct intel_unpin_work, work);
8852         struct drm_device *dev = work->crtc->dev;
8853         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8854
8855         mutex_lock(&dev->struct_mutex);
8856         intel_unpin_fb_obj(work->old_fb_obj);
8857         drm_gem_object_unreference(&work->pending_flip_obj->base);
8858         drm_gem_object_unreference(&work->old_fb_obj->base);
8859
8860         intel_update_fbc(dev);
8861         mutex_unlock(&dev->struct_mutex);
8862
8863         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8864
8865         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8866         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8867
8868         kfree(work);
8869 }
8870
8871 static void do_intel_finish_page_flip(struct drm_device *dev,
8872                                       struct drm_crtc *crtc)
8873 {
8874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8875         struct intel_unpin_work *work;
8876         unsigned long flags;
8877
8878         /* Ignore early vblank irqs */
8879         if (intel_crtc == NULL)
8880                 return;
8881
8882         /*
8883          * This is called both by irq handlers and the reset code (to complete
8884          * lost pageflips) so needs the full irqsave spinlocks.
8885          */
8886         spin_lock_irqsave(&dev->event_lock, flags);
8887         work = intel_crtc->unpin_work;
8888
8889         /* Ensure we don't miss a work->pending update ... */
8890         smp_rmb();
8891
8892         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8893                 spin_unlock_irqrestore(&dev->event_lock, flags);
8894                 return;
8895         }
8896
8897         page_flip_completed(intel_crtc);
8898
8899         spin_unlock_irqrestore(&dev->event_lock, flags);
8900 }
8901
8902 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8903 {
8904         struct drm_i915_private *dev_priv = dev->dev_private;
8905         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8906
8907         do_intel_finish_page_flip(dev, crtc);
8908 }
8909
8910 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8911 {
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8914
8915         do_intel_finish_page_flip(dev, crtc);
8916 }
8917
8918 /* Is 'a' after or equal to 'b'? */
8919 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8920 {
8921         return !((a - b) & 0x80000000);
8922 }
8923
8924 static bool page_flip_finished(struct intel_crtc *crtc)
8925 {
8926         struct drm_device *dev = crtc->base.dev;
8927         struct drm_i915_private *dev_priv = dev->dev_private;
8928
8929         /*
8930          * The relevant registers doen't exist on pre-ctg.
8931          * As the flip done interrupt doesn't trigger for mmio
8932          * flips on gmch platforms, a flip count check isn't
8933          * really needed there. But since ctg has the registers,
8934          * include it in the check anyway.
8935          */
8936         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8937                 return true;
8938
8939         /*
8940          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8941          * used the same base address. In that case the mmio flip might
8942          * have completed, but the CS hasn't even executed the flip yet.
8943          *
8944          * A flip count check isn't enough as the CS might have updated
8945          * the base address just after start of vblank, but before we
8946          * managed to process the interrupt. This means we'd complete the
8947          * CS flip too soon.
8948          *
8949          * Combining both checks should get us a good enough result. It may
8950          * still happen that the CS flip has been executed, but has not
8951          * yet actually completed. But in case the base address is the same
8952          * anyway, we don't really care.
8953          */
8954         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8955                 crtc->unpin_work->gtt_offset &&
8956                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8957                                     crtc->unpin_work->flip_count);
8958 }
8959
8960 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8961 {
8962         struct drm_i915_private *dev_priv = dev->dev_private;
8963         struct intel_crtc *intel_crtc =
8964                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8965         unsigned long flags;
8966
8967
8968         /*
8969          * This is called both by irq handlers and the reset code (to complete
8970          * lost pageflips) so needs the full irqsave spinlocks.
8971          *
8972          * NB: An MMIO update of the plane base pointer will also
8973          * generate a page-flip completion irq, i.e. every modeset
8974          * is also accompanied by a spurious intel_prepare_page_flip().
8975          */
8976         spin_lock_irqsave(&dev->event_lock, flags);
8977         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8978                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8979         spin_unlock_irqrestore(&dev->event_lock, flags);
8980 }
8981
8982 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8983 {
8984         /* Ensure that the work item is consistent when activating it ... */
8985         smp_wmb();
8986         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8987         /* and that it is marked active as soon as the irq could fire. */
8988         smp_wmb();
8989 }
8990
8991 static int intel_gen2_queue_flip(struct drm_device *dev,
8992                                  struct drm_crtc *crtc,
8993                                  struct drm_framebuffer *fb,
8994                                  struct drm_i915_gem_object *obj,
8995                                  struct intel_engine_cs *ring,
8996                                  uint32_t flags)
8997 {
8998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8999         u32 flip_mask;
9000         int ret;
9001
9002         ret = intel_ring_begin(ring, 6);
9003         if (ret)
9004                 return ret;
9005
9006         /* Can't queue multiple flips, so wait for the previous
9007          * one to finish before executing the next.
9008          */
9009         if (intel_crtc->plane)
9010                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9011         else
9012                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9013         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9014         intel_ring_emit(ring, MI_NOOP);
9015         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9016                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9017         intel_ring_emit(ring, fb->pitches[0]);
9018         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9019         intel_ring_emit(ring, 0); /* aux display base address, unused */
9020
9021         intel_mark_page_flip_active(intel_crtc);
9022         __intel_ring_advance(ring);
9023         return 0;
9024 }
9025
9026 static int intel_gen3_queue_flip(struct drm_device *dev,
9027                                  struct drm_crtc *crtc,
9028                                  struct drm_framebuffer *fb,
9029                                  struct drm_i915_gem_object *obj,
9030                                  struct intel_engine_cs *ring,
9031                                  uint32_t flags)
9032 {
9033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9034         u32 flip_mask;
9035         int ret;
9036
9037         ret = intel_ring_begin(ring, 6);
9038         if (ret)
9039                 return ret;
9040
9041         if (intel_crtc->plane)
9042                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9043         else
9044                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9045         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9046         intel_ring_emit(ring, MI_NOOP);
9047         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9048                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9049         intel_ring_emit(ring, fb->pitches[0]);
9050         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9051         intel_ring_emit(ring, MI_NOOP);
9052
9053         intel_mark_page_flip_active(intel_crtc);
9054         __intel_ring_advance(ring);
9055         return 0;
9056 }
9057
9058 static int intel_gen4_queue_flip(struct drm_device *dev,
9059                                  struct drm_crtc *crtc,
9060                                  struct drm_framebuffer *fb,
9061                                  struct drm_i915_gem_object *obj,
9062                                  struct intel_engine_cs *ring,
9063                                  uint32_t flags)
9064 {
9065         struct drm_i915_private *dev_priv = dev->dev_private;
9066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9067         uint32_t pf, pipesrc;
9068         int ret;
9069
9070         ret = intel_ring_begin(ring, 4);
9071         if (ret)
9072                 return ret;
9073
9074         /* i965+ uses the linear or tiled offsets from the
9075          * Display Registers (which do not change across a page-flip)
9076          * so we need only reprogram the base address.
9077          */
9078         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9079                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9080         intel_ring_emit(ring, fb->pitches[0]);
9081         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9082                         obj->tiling_mode);
9083
9084         /* XXX Enabling the panel-fitter across page-flip is so far
9085          * untested on non-native modes, so ignore it for now.
9086          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9087          */
9088         pf = 0;
9089         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9090         intel_ring_emit(ring, pf | pipesrc);
9091
9092         intel_mark_page_flip_active(intel_crtc);
9093         __intel_ring_advance(ring);
9094         return 0;
9095 }
9096
9097 static int intel_gen6_queue_flip(struct drm_device *dev,
9098                                  struct drm_crtc *crtc,
9099                                  struct drm_framebuffer *fb,
9100                                  struct drm_i915_gem_object *obj,
9101                                  struct intel_engine_cs *ring,
9102                                  uint32_t flags)
9103 {
9104         struct drm_i915_private *dev_priv = dev->dev_private;
9105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9106         uint32_t pf, pipesrc;
9107         int ret;
9108
9109         ret = intel_ring_begin(ring, 4);
9110         if (ret)
9111                 return ret;
9112
9113         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9114                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9115         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9116         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9117
9118         /* Contrary to the suggestions in the documentation,
9119          * "Enable Panel Fitter" does not seem to be required when page
9120          * flipping with a non-native mode, and worse causes a normal
9121          * modeset to fail.
9122          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9123          */
9124         pf = 0;
9125         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9126         intel_ring_emit(ring, pf | pipesrc);
9127
9128         intel_mark_page_flip_active(intel_crtc);
9129         __intel_ring_advance(ring);
9130         return 0;
9131 }
9132
9133 static int intel_gen7_queue_flip(struct drm_device *dev,
9134                                  struct drm_crtc *crtc,
9135                                  struct drm_framebuffer *fb,
9136                                  struct drm_i915_gem_object *obj,
9137                                  struct intel_engine_cs *ring,
9138                                  uint32_t flags)
9139 {
9140         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9141         uint32_t plane_bit = 0;
9142         int len, ret;
9143
9144         switch (intel_crtc->plane) {
9145         case PLANE_A:
9146                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9147                 break;
9148         case PLANE_B:
9149                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9150                 break;
9151         case PLANE_C:
9152                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9153                 break;
9154         default:
9155                 WARN_ONCE(1, "unknown plane in flip command\n");
9156                 return -ENODEV;
9157         }
9158
9159         len = 4;
9160         if (ring->id == RCS) {
9161                 len += 6;
9162                 /*
9163                  * On Gen 8, SRM is now taking an extra dword to accommodate
9164                  * 48bits addresses, and we need a NOOP for the batch size to
9165                  * stay even.
9166                  */
9167                 if (IS_GEN8(dev))
9168                         len += 2;
9169         }
9170
9171         /*
9172          * BSpec MI_DISPLAY_FLIP for IVB:
9173          * "The full packet must be contained within the same cache line."
9174          *
9175          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9176          * cacheline, if we ever start emitting more commands before
9177          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9178          * then do the cacheline alignment, and finally emit the
9179          * MI_DISPLAY_FLIP.
9180          */
9181         ret = intel_ring_cacheline_align(ring);
9182         if (ret)
9183                 return ret;
9184
9185         ret = intel_ring_begin(ring, len);
9186         if (ret)
9187                 return ret;
9188
9189         /* Unmask the flip-done completion message. Note that the bspec says that
9190          * we should do this for both the BCS and RCS, and that we must not unmask
9191          * more than one flip event at any time (or ensure that one flip message
9192          * can be sent by waiting for flip-done prior to queueing new flips).
9193          * Experimentation says that BCS works despite DERRMR masking all
9194          * flip-done completion events and that unmasking all planes at once
9195          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9196          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9197          */
9198         if (ring->id == RCS) {
9199                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9200                 intel_ring_emit(ring, DERRMR);
9201                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9202                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9203                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9204                 if (IS_GEN8(dev))
9205                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9206                                               MI_SRM_LRM_GLOBAL_GTT);
9207                 else
9208                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9209                                               MI_SRM_LRM_GLOBAL_GTT);
9210                 intel_ring_emit(ring, DERRMR);
9211                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9212                 if (IS_GEN8(dev)) {
9213                         intel_ring_emit(ring, 0);
9214                         intel_ring_emit(ring, MI_NOOP);
9215                 }
9216         }
9217
9218         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9219         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9220         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9221         intel_ring_emit(ring, (MI_NOOP));
9222
9223         intel_mark_page_flip_active(intel_crtc);
9224         __intel_ring_advance(ring);
9225         return 0;
9226 }
9227
9228 static bool use_mmio_flip(struct intel_engine_cs *ring,
9229                           struct drm_i915_gem_object *obj)
9230 {
9231         /*
9232          * This is not being used for older platforms, because
9233          * non-availability of flip done interrupt forces us to use
9234          * CS flips. Older platforms derive flip done using some clever
9235          * tricks involving the flip_pending status bits and vblank irqs.
9236          * So using MMIO flips there would disrupt this mechanism.
9237          */
9238
9239         if (ring == NULL)
9240                 return true;
9241
9242         if (INTEL_INFO(ring->dev)->gen < 5)
9243                 return false;
9244
9245         if (i915.use_mmio_flip < 0)
9246                 return false;
9247         else if (i915.use_mmio_flip > 0)
9248                 return true;
9249         else if (i915.enable_execlists)
9250                 return true;
9251         else
9252                 return ring != obj->ring;
9253 }
9254
9255 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9256 {
9257         struct drm_device *dev = intel_crtc->base.dev;
9258         struct drm_i915_private *dev_priv = dev->dev_private;
9259         struct intel_framebuffer *intel_fb =
9260                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9261         struct drm_i915_gem_object *obj = intel_fb->obj;
9262         u32 dspcntr;
9263         u32 reg;
9264
9265         intel_mark_page_flip_active(intel_crtc);
9266
9267         reg = DSPCNTR(intel_crtc->plane);
9268         dspcntr = I915_READ(reg);
9269
9270         if (obj->tiling_mode != I915_TILING_NONE)
9271                 dspcntr |= DISPPLANE_TILED;
9272         else
9273                 dspcntr &= ~DISPPLANE_TILED;
9274
9275         I915_WRITE(reg, dspcntr);
9276
9277         I915_WRITE(DSPSURF(intel_crtc->plane),
9278                    intel_crtc->unpin_work->gtt_offset);
9279         POSTING_READ(DSPSURF(intel_crtc->plane));
9280 }
9281
9282 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9283 {
9284         struct intel_engine_cs *ring;
9285         int ret;
9286
9287         lockdep_assert_held(&obj->base.dev->struct_mutex);
9288
9289         if (!obj->last_write_seqno)
9290                 return 0;
9291
9292         ring = obj->ring;
9293
9294         if (i915_seqno_passed(ring->get_seqno(ring, true),
9295                               obj->last_write_seqno))
9296                 return 0;
9297
9298         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9299         if (ret)
9300                 return ret;
9301
9302         if (WARN_ON(!ring->irq_get(ring)))
9303                 return 0;
9304
9305         return 1;
9306 }
9307
9308 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9309 {
9310         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9311         struct intel_crtc *intel_crtc;
9312         unsigned long irq_flags;
9313         u32 seqno;
9314
9315         seqno = ring->get_seqno(ring, false);
9316
9317         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9318         for_each_intel_crtc(ring->dev, intel_crtc) {
9319                 struct intel_mmio_flip *mmio_flip;
9320
9321                 mmio_flip = &intel_crtc->mmio_flip;
9322                 if (mmio_flip->seqno == 0)
9323                         continue;
9324
9325                 if (ring->id != mmio_flip->ring_id)
9326                         continue;
9327
9328                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9329                         intel_do_mmio_flip(intel_crtc);
9330                         mmio_flip->seqno = 0;
9331                         ring->irq_put(ring);
9332                 }
9333         }
9334         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9335 }
9336
9337 static int intel_queue_mmio_flip(struct drm_device *dev,
9338                                  struct drm_crtc *crtc,
9339                                  struct drm_framebuffer *fb,
9340                                  struct drm_i915_gem_object *obj,
9341                                  struct intel_engine_cs *ring,
9342                                  uint32_t flags)
9343 {
9344         struct drm_i915_private *dev_priv = dev->dev_private;
9345         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9346         int ret;
9347
9348         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9349                 return -EBUSY;
9350
9351         ret = intel_postpone_flip(obj);
9352         if (ret < 0)
9353                 return ret;
9354         if (ret == 0) {
9355                 intel_do_mmio_flip(intel_crtc);
9356                 return 0;
9357         }
9358
9359         spin_lock_irq(&dev_priv->mmio_flip_lock);
9360         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9361         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9362         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9363
9364         /*
9365          * Double check to catch cases where irq fired before
9366          * mmio flip data was ready
9367          */
9368         intel_notify_mmio_flip(obj->ring);
9369         return 0;
9370 }
9371
9372 static int intel_default_queue_flip(struct drm_device *dev,
9373                                     struct drm_crtc *crtc,
9374                                     struct drm_framebuffer *fb,
9375                                     struct drm_i915_gem_object *obj,
9376                                     struct intel_engine_cs *ring,
9377                                     uint32_t flags)
9378 {
9379         return -ENODEV;
9380 }
9381
9382 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9383                                          struct drm_crtc *crtc)
9384 {
9385         struct drm_i915_private *dev_priv = dev->dev_private;
9386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9387         struct intel_unpin_work *work = intel_crtc->unpin_work;
9388         u32 addr;
9389
9390         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9391                 return true;
9392
9393         if (!work->enable_stall_check)
9394                 return false;
9395
9396         if (work->flip_ready_vblank == 0) {
9397                 if (work->flip_queued_ring &&
9398                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9399                                        work->flip_queued_seqno))
9400                         return false;
9401
9402                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9403         }
9404
9405         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9406                 return false;
9407
9408         /* Potential stall - if we see that the flip has happened,
9409          * assume a missed interrupt. */
9410         if (INTEL_INFO(dev)->gen >= 4)
9411                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9412         else
9413                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9414
9415         /* There is a potential issue here with a false positive after a flip
9416          * to the same address. We could address this by checking for a
9417          * non-incrementing frame counter.
9418          */
9419         return addr == work->gtt_offset;
9420 }
9421
9422 void intel_check_page_flip(struct drm_device *dev, int pipe)
9423 {
9424         struct drm_i915_private *dev_priv = dev->dev_private;
9425         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9426         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9427
9428         WARN_ON(!in_irq());
9429
9430         if (crtc == NULL)
9431                 return;
9432
9433         spin_lock(&dev->event_lock);
9434         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9435                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9436                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9437                 page_flip_completed(intel_crtc);
9438         }
9439         spin_unlock(&dev->event_lock);
9440 }
9441
9442 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9443                                 struct drm_framebuffer *fb,
9444                                 struct drm_pending_vblank_event *event,
9445                                 uint32_t page_flip_flags)
9446 {
9447         struct drm_device *dev = crtc->dev;
9448         struct drm_i915_private *dev_priv = dev->dev_private;
9449         struct drm_framebuffer *old_fb = crtc->primary->fb;
9450         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9451         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9452         enum pipe pipe = intel_crtc->pipe;
9453         struct intel_unpin_work *work;
9454         struct intel_engine_cs *ring;
9455         int ret;
9456
9457         /*
9458          * drm_mode_page_flip_ioctl() should already catch this, but double
9459          * check to be safe.  In the future we may enable pageflipping from
9460          * a disabled primary plane.
9461          */
9462         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9463                 return -EBUSY;
9464
9465         /* Can't change pixel format via MI display flips. */
9466         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9467                 return -EINVAL;
9468
9469         /*
9470          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9471          * Note that pitch changes could also affect these register.
9472          */
9473         if (INTEL_INFO(dev)->gen > 3 &&
9474             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9475              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9476                 return -EINVAL;
9477
9478         if (i915_terminally_wedged(&dev_priv->gpu_error))
9479                 goto out_hang;
9480
9481         work = kzalloc(sizeof(*work), GFP_KERNEL);
9482         if (work == NULL)
9483                 return -ENOMEM;
9484
9485         work->event = event;
9486         work->crtc = crtc;
9487         work->old_fb_obj = intel_fb_obj(old_fb);
9488         INIT_WORK(&work->work, intel_unpin_work_fn);
9489
9490         ret = drm_crtc_vblank_get(crtc);
9491         if (ret)
9492                 goto free_work;
9493
9494         /* We borrow the event spin lock for protecting unpin_work */
9495         spin_lock_irq(&dev->event_lock);
9496         if (intel_crtc->unpin_work) {
9497                 /* Before declaring the flip queue wedged, check if
9498                  * the hardware completed the operation behind our backs.
9499                  */
9500                 if (__intel_pageflip_stall_check(dev, crtc)) {
9501                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9502                         page_flip_completed(intel_crtc);
9503                 } else {
9504                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9505                         spin_unlock_irq(&dev->event_lock);
9506
9507                         drm_crtc_vblank_put(crtc);
9508                         kfree(work);
9509                         return -EBUSY;
9510                 }
9511         }
9512         intel_crtc->unpin_work = work;
9513         spin_unlock_irq(&dev->event_lock);
9514
9515         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9516                 flush_workqueue(dev_priv->wq);
9517
9518         ret = i915_mutex_lock_interruptible(dev);
9519         if (ret)
9520                 goto cleanup;
9521
9522         /* Reference the objects for the scheduled work. */
9523         drm_gem_object_reference(&work->old_fb_obj->base);
9524         drm_gem_object_reference(&obj->base);
9525
9526         crtc->primary->fb = fb;
9527
9528         work->pending_flip_obj = obj;
9529
9530         atomic_inc(&intel_crtc->unpin_work_count);
9531         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9532
9533         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9534                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9535
9536         if (IS_VALLEYVIEW(dev)) {
9537                 ring = &dev_priv->ring[BCS];
9538                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9539                         /* vlv: DISPLAY_FLIP fails to change tiling */
9540                         ring = NULL;
9541         } else if (IS_IVYBRIDGE(dev)) {
9542                 ring = &dev_priv->ring[BCS];
9543         } else if (INTEL_INFO(dev)->gen >= 7) {
9544                 ring = obj->ring;
9545                 if (ring == NULL || ring->id != RCS)
9546                         ring = &dev_priv->ring[BCS];
9547         } else {
9548                 ring = &dev_priv->ring[RCS];
9549         }
9550
9551         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9552         if (ret)
9553                 goto cleanup_pending;
9554
9555         work->gtt_offset =
9556                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9557
9558         if (use_mmio_flip(ring, obj)) {
9559                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9560                                             page_flip_flags);
9561                 if (ret)
9562                         goto cleanup_unpin;
9563
9564                 work->flip_queued_seqno = obj->last_write_seqno;
9565                 work->flip_queued_ring = obj->ring;
9566         } else {
9567                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9568                                                    page_flip_flags);
9569                 if (ret)
9570                         goto cleanup_unpin;
9571
9572                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9573                 work->flip_queued_ring = ring;
9574         }
9575
9576         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9577         work->enable_stall_check = true;
9578
9579         i915_gem_track_fb(work->old_fb_obj, obj,
9580                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9581
9582         intel_disable_fbc(dev);
9583         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9584         mutex_unlock(&dev->struct_mutex);
9585
9586         trace_i915_flip_request(intel_crtc->plane, obj);
9587
9588         return 0;
9589
9590 cleanup_unpin:
9591         intel_unpin_fb_obj(obj);
9592 cleanup_pending:
9593         atomic_dec(&intel_crtc->unpin_work_count);
9594         crtc->primary->fb = old_fb;
9595         drm_gem_object_unreference(&work->old_fb_obj->base);
9596         drm_gem_object_unreference(&obj->base);
9597         mutex_unlock(&dev->struct_mutex);
9598
9599 cleanup:
9600         spin_lock_irq(&dev->event_lock);
9601         intel_crtc->unpin_work = NULL;
9602         spin_unlock_irq(&dev->event_lock);
9603
9604         drm_crtc_vblank_put(crtc);
9605 free_work:
9606         kfree(work);
9607
9608         if (ret == -EIO) {
9609 out_hang:
9610                 intel_crtc_wait_for_pending_flips(crtc);
9611                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9612                 if (ret == 0 && event) {
9613                         spin_lock_irq(&dev->event_lock);
9614                         drm_send_vblank_event(dev, pipe, event);
9615                         spin_unlock_irq(&dev->event_lock);
9616                 }
9617         }
9618         return ret;
9619 }
9620
9621 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9622         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9623         .load_lut = intel_crtc_load_lut,
9624 };
9625
9626 /**
9627  * intel_modeset_update_staged_output_state
9628  *
9629  * Updates the staged output configuration state, e.g. after we've read out the
9630  * current hw state.
9631  */
9632 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9633 {
9634         struct intel_crtc *crtc;
9635         struct intel_encoder *encoder;
9636         struct intel_connector *connector;
9637
9638         list_for_each_entry(connector, &dev->mode_config.connector_list,
9639                             base.head) {
9640                 connector->new_encoder =
9641                         to_intel_encoder(connector->base.encoder);
9642         }
9643
9644         for_each_intel_encoder(dev, encoder) {
9645                 encoder->new_crtc =
9646                         to_intel_crtc(encoder->base.crtc);
9647         }
9648
9649         for_each_intel_crtc(dev, crtc) {
9650                 crtc->new_enabled = crtc->base.enabled;
9651
9652                 if (crtc->new_enabled)
9653                         crtc->new_config = &crtc->config;
9654                 else
9655                         crtc->new_config = NULL;
9656         }
9657 }
9658
9659 /**
9660  * intel_modeset_commit_output_state
9661  *
9662  * This function copies the stage display pipe configuration to the real one.
9663  */
9664 static void intel_modeset_commit_output_state(struct drm_device *dev)
9665 {
9666         struct intel_crtc *crtc;
9667         struct intel_encoder *encoder;
9668         struct intel_connector *connector;
9669
9670         list_for_each_entry(connector, &dev->mode_config.connector_list,
9671                             base.head) {
9672                 connector->base.encoder = &connector->new_encoder->base;
9673         }
9674
9675         for_each_intel_encoder(dev, encoder) {
9676                 encoder->base.crtc = &encoder->new_crtc->base;
9677         }
9678
9679         for_each_intel_crtc(dev, crtc) {
9680                 crtc->base.enabled = crtc->new_enabled;
9681         }
9682 }
9683
9684 static void
9685 connected_sink_compute_bpp(struct intel_connector *connector,
9686                            struct intel_crtc_config *pipe_config)
9687 {
9688         int bpp = pipe_config->pipe_bpp;
9689
9690         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9691                 connector->base.base.id,
9692                 connector->base.name);
9693
9694         /* Don't use an invalid EDID bpc value */
9695         if (connector->base.display_info.bpc &&
9696             connector->base.display_info.bpc * 3 < bpp) {
9697                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9698                               bpp, connector->base.display_info.bpc*3);
9699                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9700         }
9701
9702         /* Clamp bpp to 8 on screens without EDID 1.4 */
9703         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9704                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9705                               bpp);
9706                 pipe_config->pipe_bpp = 24;
9707         }
9708 }
9709
9710 static int
9711 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9712                           struct drm_framebuffer *fb,
9713                           struct intel_crtc_config *pipe_config)
9714 {
9715         struct drm_device *dev = crtc->base.dev;
9716         struct intel_connector *connector;
9717         int bpp;
9718
9719         switch (fb->pixel_format) {
9720         case DRM_FORMAT_C8:
9721                 bpp = 8*3; /* since we go through a colormap */
9722                 break;
9723         case DRM_FORMAT_XRGB1555:
9724         case DRM_FORMAT_ARGB1555:
9725                 /* checked in intel_framebuffer_init already */
9726                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9727                         return -EINVAL;
9728         case DRM_FORMAT_RGB565:
9729                 bpp = 6*3; /* min is 18bpp */
9730                 break;
9731         case DRM_FORMAT_XBGR8888:
9732         case DRM_FORMAT_ABGR8888:
9733                 /* checked in intel_framebuffer_init already */
9734                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9735                         return -EINVAL;
9736         case DRM_FORMAT_XRGB8888:
9737         case DRM_FORMAT_ARGB8888:
9738                 bpp = 8*3;
9739                 break;
9740         case DRM_FORMAT_XRGB2101010:
9741         case DRM_FORMAT_ARGB2101010:
9742         case DRM_FORMAT_XBGR2101010:
9743         case DRM_FORMAT_ABGR2101010:
9744                 /* checked in intel_framebuffer_init already */
9745                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9746                         return -EINVAL;
9747                 bpp = 10*3;
9748                 break;
9749         /* TODO: gen4+ supports 16 bpc floating point, too. */
9750         default:
9751                 DRM_DEBUG_KMS("unsupported depth\n");
9752                 return -EINVAL;
9753         }
9754
9755         pipe_config->pipe_bpp = bpp;
9756
9757         /* Clamp display bpp to EDID value */
9758         list_for_each_entry(connector, &dev->mode_config.connector_list,
9759                             base.head) {
9760                 if (!connector->new_encoder ||
9761                     connector->new_encoder->new_crtc != crtc)
9762                         continue;
9763
9764                 connected_sink_compute_bpp(connector, pipe_config);
9765         }
9766
9767         return bpp;
9768 }
9769
9770 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9771 {
9772         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9773                         "type: 0x%x flags: 0x%x\n",
9774                 mode->crtc_clock,
9775                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9776                 mode->crtc_hsync_end, mode->crtc_htotal,
9777                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9778                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9779 }
9780
9781 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9782                                    struct intel_crtc_config *pipe_config,
9783                                    const char *context)
9784 {
9785         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9786                       context, pipe_name(crtc->pipe));
9787
9788         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9789         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9790                       pipe_config->pipe_bpp, pipe_config->dither);
9791         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9792                       pipe_config->has_pch_encoder,
9793                       pipe_config->fdi_lanes,
9794                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9795                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9796                       pipe_config->fdi_m_n.tu);
9797         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9798                       pipe_config->has_dp_encoder,
9799                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9800                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9801                       pipe_config->dp_m_n.tu);
9802
9803         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9804                       pipe_config->has_dp_encoder,
9805                       pipe_config->dp_m2_n2.gmch_m,
9806                       pipe_config->dp_m2_n2.gmch_n,
9807                       pipe_config->dp_m2_n2.link_m,
9808                       pipe_config->dp_m2_n2.link_n,
9809                       pipe_config->dp_m2_n2.tu);
9810
9811         DRM_DEBUG_KMS("requested mode:\n");
9812         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9813         DRM_DEBUG_KMS("adjusted mode:\n");
9814         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9815         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9816         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9817         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9818                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9819         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9820                       pipe_config->gmch_pfit.control,
9821                       pipe_config->gmch_pfit.pgm_ratios,
9822                       pipe_config->gmch_pfit.lvds_border_bits);
9823         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9824                       pipe_config->pch_pfit.pos,
9825                       pipe_config->pch_pfit.size,
9826                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9827         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9828         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9829 }
9830
9831 static bool encoders_cloneable(const struct intel_encoder *a,
9832                                const struct intel_encoder *b)
9833 {
9834         /* masks could be asymmetric, so check both ways */
9835         return a == b || (a->cloneable & (1 << b->type) &&
9836                           b->cloneable & (1 << a->type));
9837 }
9838
9839 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9840                                          struct intel_encoder *encoder)
9841 {
9842         struct drm_device *dev = crtc->base.dev;
9843         struct intel_encoder *source_encoder;
9844
9845         for_each_intel_encoder(dev, source_encoder) {
9846                 if (source_encoder->new_crtc != crtc)
9847                         continue;
9848
9849                 if (!encoders_cloneable(encoder, source_encoder))
9850                         return false;
9851         }
9852
9853         return true;
9854 }
9855
9856 static bool check_encoder_cloning(struct intel_crtc *crtc)
9857 {
9858         struct drm_device *dev = crtc->base.dev;
9859         struct intel_encoder *encoder;
9860
9861         for_each_intel_encoder(dev, encoder) {
9862                 if (encoder->new_crtc != crtc)
9863                         continue;
9864
9865                 if (!check_single_encoder_cloning(crtc, encoder))
9866                         return false;
9867         }
9868
9869         return true;
9870 }
9871
9872 static struct intel_crtc_config *
9873 intel_modeset_pipe_config(struct drm_crtc *crtc,
9874                           struct drm_framebuffer *fb,
9875                           struct drm_display_mode *mode)
9876 {
9877         struct drm_device *dev = crtc->dev;
9878         struct intel_encoder *encoder;
9879         struct intel_crtc_config *pipe_config;
9880         int plane_bpp, ret = -EINVAL;
9881         bool retry = true;
9882
9883         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9884                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9885                 return ERR_PTR(-EINVAL);
9886         }
9887
9888         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9889         if (!pipe_config)
9890                 return ERR_PTR(-ENOMEM);
9891
9892         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9893         drm_mode_copy(&pipe_config->requested_mode, mode);
9894
9895         pipe_config->cpu_transcoder =
9896                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9897         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9898
9899         /*
9900          * Sanitize sync polarity flags based on requested ones. If neither
9901          * positive or negative polarity is requested, treat this as meaning
9902          * negative polarity.
9903          */
9904         if (!(pipe_config->adjusted_mode.flags &
9905               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9906                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9907
9908         if (!(pipe_config->adjusted_mode.flags &
9909               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9910                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9911
9912         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9913          * plane pixel format and any sink constraints into account. Returns the
9914          * source plane bpp so that dithering can be selected on mismatches
9915          * after encoders and crtc also have had their say. */
9916         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9917                                               fb, pipe_config);
9918         if (plane_bpp < 0)
9919                 goto fail;
9920
9921         /*
9922          * Determine the real pipe dimensions. Note that stereo modes can
9923          * increase the actual pipe size due to the frame doubling and
9924          * insertion of additional space for blanks between the frame. This
9925          * is stored in the crtc timings. We use the requested mode to do this
9926          * computation to clearly distinguish it from the adjusted mode, which
9927          * can be changed by the connectors in the below retry loop.
9928          */
9929         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9930         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9931         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9932
9933 encoder_retry:
9934         /* Ensure the port clock defaults are reset when retrying. */
9935         pipe_config->port_clock = 0;
9936         pipe_config->pixel_multiplier = 1;
9937
9938         /* Fill in default crtc timings, allow encoders to overwrite them. */
9939         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9940
9941         /* Pass our mode to the connectors and the CRTC to give them a chance to
9942          * adjust it according to limitations or connector properties, and also
9943          * a chance to reject the mode entirely.
9944          */
9945         for_each_intel_encoder(dev, encoder) {
9946
9947                 if (&encoder->new_crtc->base != crtc)
9948                         continue;
9949
9950                 if (!(encoder->compute_config(encoder, pipe_config))) {
9951                         DRM_DEBUG_KMS("Encoder config failure\n");
9952                         goto fail;
9953                 }
9954         }
9955
9956         /* Set default port clock if not overwritten by the encoder. Needs to be
9957          * done afterwards in case the encoder adjusts the mode. */
9958         if (!pipe_config->port_clock)
9959                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9960                         * pipe_config->pixel_multiplier;
9961
9962         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9963         if (ret < 0) {
9964                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9965                 goto fail;
9966         }
9967
9968         if (ret == RETRY) {
9969                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9970                         ret = -EINVAL;
9971                         goto fail;
9972                 }
9973
9974                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9975                 retry = false;
9976                 goto encoder_retry;
9977         }
9978
9979         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9980         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9981                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9982
9983         return pipe_config;
9984 fail:
9985         kfree(pipe_config);
9986         return ERR_PTR(ret);
9987 }
9988
9989 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9990  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9991 static void
9992 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9993                              unsigned *prepare_pipes, unsigned *disable_pipes)
9994 {
9995         struct intel_crtc *intel_crtc;
9996         struct drm_device *dev = crtc->dev;
9997         struct intel_encoder *encoder;
9998         struct intel_connector *connector;
9999         struct drm_crtc *tmp_crtc;
10000
10001         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10002
10003         /* Check which crtcs have changed outputs connected to them, these need
10004          * to be part of the prepare_pipes mask. We don't (yet) support global
10005          * modeset across multiple crtcs, so modeset_pipes will only have one
10006          * bit set at most. */
10007         list_for_each_entry(connector, &dev->mode_config.connector_list,
10008                             base.head) {
10009                 if (connector->base.encoder == &connector->new_encoder->base)
10010                         continue;
10011
10012                 if (connector->base.encoder) {
10013                         tmp_crtc = connector->base.encoder->crtc;
10014
10015                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10016                 }
10017
10018                 if (connector->new_encoder)
10019                         *prepare_pipes |=
10020                                 1 << connector->new_encoder->new_crtc->pipe;
10021         }
10022
10023         for_each_intel_encoder(dev, encoder) {
10024                 if (encoder->base.crtc == &encoder->new_crtc->base)
10025                         continue;
10026
10027                 if (encoder->base.crtc) {
10028                         tmp_crtc = encoder->base.crtc;
10029
10030                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10031                 }
10032
10033                 if (encoder->new_crtc)
10034                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10035         }
10036
10037         /* Check for pipes that will be enabled/disabled ... */
10038         for_each_intel_crtc(dev, intel_crtc) {
10039                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10040                         continue;
10041
10042                 if (!intel_crtc->new_enabled)
10043                         *disable_pipes |= 1 << intel_crtc->pipe;
10044                 else
10045                         *prepare_pipes |= 1 << intel_crtc->pipe;
10046         }
10047
10048
10049         /* set_mode is also used to update properties on life display pipes. */
10050         intel_crtc = to_intel_crtc(crtc);
10051         if (intel_crtc->new_enabled)
10052                 *prepare_pipes |= 1 << intel_crtc->pipe;
10053
10054         /*
10055          * For simplicity do a full modeset on any pipe where the output routing
10056          * changed. We could be more clever, but that would require us to be
10057          * more careful with calling the relevant encoder->mode_set functions.
10058          */
10059         if (*prepare_pipes)
10060                 *modeset_pipes = *prepare_pipes;
10061
10062         /* ... and mask these out. */
10063         *modeset_pipes &= ~(*disable_pipes);
10064         *prepare_pipes &= ~(*disable_pipes);
10065
10066         /*
10067          * HACK: We don't (yet) fully support global modesets. intel_set_config
10068          * obies this rule, but the modeset restore mode of
10069          * intel_modeset_setup_hw_state does not.
10070          */
10071         *modeset_pipes &= 1 << intel_crtc->pipe;
10072         *prepare_pipes &= 1 << intel_crtc->pipe;
10073
10074         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10075                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10076 }
10077
10078 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10079 {
10080         struct drm_encoder *encoder;
10081         struct drm_device *dev = crtc->dev;
10082
10083         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10084                 if (encoder->crtc == crtc)
10085                         return true;
10086
10087         return false;
10088 }
10089
10090 static void
10091 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10092 {
10093         struct intel_encoder *intel_encoder;
10094         struct intel_crtc *intel_crtc;
10095         struct drm_connector *connector;
10096
10097         for_each_intel_encoder(dev, intel_encoder) {
10098                 if (!intel_encoder->base.crtc)
10099                         continue;
10100
10101                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10102
10103                 if (prepare_pipes & (1 << intel_crtc->pipe))
10104                         intel_encoder->connectors_active = false;
10105         }
10106
10107         intel_modeset_commit_output_state(dev);
10108
10109         /* Double check state. */
10110         for_each_intel_crtc(dev, intel_crtc) {
10111                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10112                 WARN_ON(intel_crtc->new_config &&
10113                         intel_crtc->new_config != &intel_crtc->config);
10114                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10115         }
10116
10117         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10118                 if (!connector->encoder || !connector->encoder->crtc)
10119                         continue;
10120
10121                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10122
10123                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10124                         struct drm_property *dpms_property =
10125                                 dev->mode_config.dpms_property;
10126
10127                         connector->dpms = DRM_MODE_DPMS_ON;
10128                         drm_object_property_set_value(&connector->base,
10129                                                          dpms_property,
10130                                                          DRM_MODE_DPMS_ON);
10131
10132                         intel_encoder = to_intel_encoder(connector->encoder);
10133                         intel_encoder->connectors_active = true;
10134                 }
10135         }
10136
10137 }
10138
10139 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10140 {
10141         int diff;
10142
10143         if (clock1 == clock2)
10144                 return true;
10145
10146         if (!clock1 || !clock2)
10147                 return false;
10148
10149         diff = abs(clock1 - clock2);
10150
10151         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10152                 return true;
10153
10154         return false;
10155 }
10156
10157 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10158         list_for_each_entry((intel_crtc), \
10159                             &(dev)->mode_config.crtc_list, \
10160                             base.head) \
10161                 if (mask & (1 <<(intel_crtc)->pipe))
10162
10163 static bool
10164 intel_pipe_config_compare(struct drm_device *dev,
10165                           struct intel_crtc_config *current_config,
10166                           struct intel_crtc_config *pipe_config)
10167 {
10168 #define PIPE_CONF_CHECK_X(name) \
10169         if (current_config->name != pipe_config->name) { \
10170                 DRM_ERROR("mismatch in " #name " " \
10171                           "(expected 0x%08x, found 0x%08x)\n", \
10172                           current_config->name, \
10173                           pipe_config->name); \
10174                 return false; \
10175         }
10176
10177 #define PIPE_CONF_CHECK_I(name) \
10178         if (current_config->name != pipe_config->name) { \
10179                 DRM_ERROR("mismatch in " #name " " \
10180                           "(expected %i, found %i)\n", \
10181                           current_config->name, \
10182                           pipe_config->name); \
10183                 return false; \
10184         }
10185
10186 /* This is required for BDW+ where there is only one set of registers for
10187  * switching between high and low RR.
10188  * This macro can be used whenever a comparison has to be made between one
10189  * hw state and multiple sw state variables.
10190  */
10191 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10192         if ((current_config->name != pipe_config->name) && \
10193                 (current_config->alt_name != pipe_config->name)) { \
10194                         DRM_ERROR("mismatch in " #name " " \
10195                                   "(expected %i or %i, found %i)\n", \
10196                                   current_config->name, \
10197                                   current_config->alt_name, \
10198                                   pipe_config->name); \
10199                         return false; \
10200         }
10201
10202 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10203         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10204                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10205                           "(expected %i, found %i)\n", \
10206                           current_config->name & (mask), \
10207                           pipe_config->name & (mask)); \
10208                 return false; \
10209         }
10210
10211 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10212         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10213                 DRM_ERROR("mismatch in " #name " " \
10214                           "(expected %i, found %i)\n", \
10215                           current_config->name, \
10216                           pipe_config->name); \
10217                 return false; \
10218         }
10219
10220 #define PIPE_CONF_QUIRK(quirk)  \
10221         ((current_config->quirks | pipe_config->quirks) & (quirk))
10222
10223         PIPE_CONF_CHECK_I(cpu_transcoder);
10224
10225         PIPE_CONF_CHECK_I(has_pch_encoder);
10226         PIPE_CONF_CHECK_I(fdi_lanes);
10227         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10228         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10229         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10230         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10231         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10232
10233         PIPE_CONF_CHECK_I(has_dp_encoder);
10234
10235         if (INTEL_INFO(dev)->gen < 8) {
10236                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10237                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10238                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10239                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10240                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10241
10242                 if (current_config->has_drrs) {
10243                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10244                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10245                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10246                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10247                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10248                 }
10249         } else {
10250                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10251                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10252                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10253                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10254                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10255         }
10256
10257         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10258         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10259         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10260         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10261         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10262         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10263
10264         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10265         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10266         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10267         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10268         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10269         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10270
10271         PIPE_CONF_CHECK_I(pixel_multiplier);
10272         PIPE_CONF_CHECK_I(has_hdmi_sink);
10273         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10274             IS_VALLEYVIEW(dev))
10275                 PIPE_CONF_CHECK_I(limited_color_range);
10276
10277         PIPE_CONF_CHECK_I(has_audio);
10278
10279         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10280                               DRM_MODE_FLAG_INTERLACE);
10281
10282         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10283                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10284                                       DRM_MODE_FLAG_PHSYNC);
10285                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10286                                       DRM_MODE_FLAG_NHSYNC);
10287                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10288                                       DRM_MODE_FLAG_PVSYNC);
10289                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10290                                       DRM_MODE_FLAG_NVSYNC);
10291         }
10292
10293         PIPE_CONF_CHECK_I(pipe_src_w);
10294         PIPE_CONF_CHECK_I(pipe_src_h);
10295
10296         /*
10297          * FIXME: BIOS likes to set up a cloned config with lvds+external
10298          * screen. Since we don't yet re-compute the pipe config when moving
10299          * just the lvds port away to another pipe the sw tracking won't match.
10300          *
10301          * Proper atomic modesets with recomputed global state will fix this.
10302          * Until then just don't check gmch state for inherited modes.
10303          */
10304         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10305                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10306                 /* pfit ratios are autocomputed by the hw on gen4+ */
10307                 if (INTEL_INFO(dev)->gen < 4)
10308                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10309                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10310         }
10311
10312         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10313         if (current_config->pch_pfit.enabled) {
10314                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10315                 PIPE_CONF_CHECK_I(pch_pfit.size);
10316         }
10317
10318         /* BDW+ don't expose a synchronous way to read the state */
10319         if (IS_HASWELL(dev))
10320                 PIPE_CONF_CHECK_I(ips_enabled);
10321
10322         PIPE_CONF_CHECK_I(double_wide);
10323
10324         PIPE_CONF_CHECK_X(ddi_pll_sel);
10325
10326         PIPE_CONF_CHECK_I(shared_dpll);
10327         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10328         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10329         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10330         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10331         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10332
10333         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10334                 PIPE_CONF_CHECK_I(pipe_bpp);
10335
10336         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10337         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10338
10339 #undef PIPE_CONF_CHECK_X
10340 #undef PIPE_CONF_CHECK_I
10341 #undef PIPE_CONF_CHECK_I_ALT
10342 #undef PIPE_CONF_CHECK_FLAGS
10343 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10344 #undef PIPE_CONF_QUIRK
10345
10346         return true;
10347 }
10348
10349 static void
10350 check_connector_state(struct drm_device *dev)
10351 {
10352         struct intel_connector *connector;
10353
10354         list_for_each_entry(connector, &dev->mode_config.connector_list,
10355                             base.head) {
10356                 /* This also checks the encoder/connector hw state with the
10357                  * ->get_hw_state callbacks. */
10358                 intel_connector_check_state(connector);
10359
10360                 WARN(&connector->new_encoder->base != connector->base.encoder,
10361                      "connector's staged encoder doesn't match current encoder\n");
10362         }
10363 }
10364
10365 static void
10366 check_encoder_state(struct drm_device *dev)
10367 {
10368         struct intel_encoder *encoder;
10369         struct intel_connector *connector;
10370
10371         for_each_intel_encoder(dev, encoder) {
10372                 bool enabled = false;
10373                 bool active = false;
10374                 enum pipe pipe, tracked_pipe;
10375
10376                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10377                               encoder->base.base.id,
10378                               encoder->base.name);
10379
10380                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10381                      "encoder's stage crtc doesn't match current crtc\n");
10382                 WARN(encoder->connectors_active && !encoder->base.crtc,
10383                      "encoder's active_connectors set, but no crtc\n");
10384
10385                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10386                                     base.head) {
10387                         if (connector->base.encoder != &encoder->base)
10388                                 continue;
10389                         enabled = true;
10390                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10391                                 active = true;
10392                 }
10393                 /*
10394                  * for MST connectors if we unplug the connector is gone
10395                  * away but the encoder is still connected to a crtc
10396                  * until a modeset happens in response to the hotplug.
10397                  */
10398                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10399                         continue;
10400
10401                 WARN(!!encoder->base.crtc != enabled,
10402                      "encoder's enabled state mismatch "
10403                      "(expected %i, found %i)\n",
10404                      !!encoder->base.crtc, enabled);
10405                 WARN(active && !encoder->base.crtc,
10406                      "active encoder with no crtc\n");
10407
10408                 WARN(encoder->connectors_active != active,
10409                      "encoder's computed active state doesn't match tracked active state "
10410                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10411
10412                 active = encoder->get_hw_state(encoder, &pipe);
10413                 WARN(active != encoder->connectors_active,
10414                      "encoder's hw state doesn't match sw tracking "
10415                      "(expected %i, found %i)\n",
10416                      encoder->connectors_active, active);
10417
10418                 if (!encoder->base.crtc)
10419                         continue;
10420
10421                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10422                 WARN(active && pipe != tracked_pipe,
10423                      "active encoder's pipe doesn't match"
10424                      "(expected %i, found %i)\n",
10425                      tracked_pipe, pipe);
10426
10427         }
10428 }
10429
10430 static void
10431 check_crtc_state(struct drm_device *dev)
10432 {
10433         struct drm_i915_private *dev_priv = dev->dev_private;
10434         struct intel_crtc *crtc;
10435         struct intel_encoder *encoder;
10436         struct intel_crtc_config pipe_config;
10437
10438         for_each_intel_crtc(dev, crtc) {
10439                 bool enabled = false;
10440                 bool active = false;
10441
10442                 memset(&pipe_config, 0, sizeof(pipe_config));
10443
10444                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10445                               crtc->base.base.id);
10446
10447                 WARN(crtc->active && !crtc->base.enabled,
10448                      "active crtc, but not enabled in sw tracking\n");
10449
10450                 for_each_intel_encoder(dev, encoder) {
10451                         if (encoder->base.crtc != &crtc->base)
10452                                 continue;
10453                         enabled = true;
10454                         if (encoder->connectors_active)
10455                                 active = true;
10456                 }
10457
10458                 WARN(active != crtc->active,
10459                      "crtc's computed active state doesn't match tracked active state "
10460                      "(expected %i, found %i)\n", active, crtc->active);
10461                 WARN(enabled != crtc->base.enabled,
10462                      "crtc's computed enabled state doesn't match tracked enabled state "
10463                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10464
10465                 active = dev_priv->display.get_pipe_config(crtc,
10466                                                            &pipe_config);
10467
10468                 /* hw state is inconsistent with the pipe quirk */
10469                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10470                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10471                         active = crtc->active;
10472
10473                 for_each_intel_encoder(dev, encoder) {
10474                         enum pipe pipe;
10475                         if (encoder->base.crtc != &crtc->base)
10476                                 continue;
10477                         if (encoder->get_hw_state(encoder, &pipe))
10478                                 encoder->get_config(encoder, &pipe_config);
10479                 }
10480
10481                 WARN(crtc->active != active,
10482                      "crtc active state doesn't match with hw state "
10483                      "(expected %i, found %i)\n", crtc->active, active);
10484
10485                 if (active &&
10486                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10487                         WARN(1, "pipe state doesn't match!\n");
10488                         intel_dump_pipe_config(crtc, &pipe_config,
10489                                                "[hw state]");
10490                         intel_dump_pipe_config(crtc, &crtc->config,
10491                                                "[sw state]");
10492                 }
10493         }
10494 }
10495
10496 static void
10497 check_shared_dpll_state(struct drm_device *dev)
10498 {
10499         struct drm_i915_private *dev_priv = dev->dev_private;
10500         struct intel_crtc *crtc;
10501         struct intel_dpll_hw_state dpll_hw_state;
10502         int i;
10503
10504         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10505                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10506                 int enabled_crtcs = 0, active_crtcs = 0;
10507                 bool active;
10508
10509                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10510
10511                 DRM_DEBUG_KMS("%s\n", pll->name);
10512
10513                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10514
10515                 WARN(pll->active > pll->refcount,
10516                      "more active pll users than references: %i vs %i\n",
10517                      pll->active, pll->refcount);
10518                 WARN(pll->active && !pll->on,
10519                      "pll in active use but not on in sw tracking\n");
10520                 WARN(pll->on && !pll->active,
10521                      "pll in on but not on in use in sw tracking\n");
10522                 WARN(pll->on != active,
10523                      "pll on state mismatch (expected %i, found %i)\n",
10524                      pll->on, active);
10525
10526                 for_each_intel_crtc(dev, crtc) {
10527                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10528                                 enabled_crtcs++;
10529                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10530                                 active_crtcs++;
10531                 }
10532                 WARN(pll->active != active_crtcs,
10533                      "pll active crtcs mismatch (expected %i, found %i)\n",
10534                      pll->active, active_crtcs);
10535                 WARN(pll->refcount != enabled_crtcs,
10536                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10537                      pll->refcount, enabled_crtcs);
10538
10539                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10540                                        sizeof(dpll_hw_state)),
10541                      "pll hw state mismatch\n");
10542         }
10543 }
10544
10545 void
10546 intel_modeset_check_state(struct drm_device *dev)
10547 {
10548         check_connector_state(dev);
10549         check_encoder_state(dev);
10550         check_crtc_state(dev);
10551         check_shared_dpll_state(dev);
10552 }
10553
10554 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10555                                      int dotclock)
10556 {
10557         /*
10558          * FDI already provided one idea for the dotclock.
10559          * Yell if the encoder disagrees.
10560          */
10561         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10562              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10563              pipe_config->adjusted_mode.crtc_clock, dotclock);
10564 }
10565
10566 static void update_scanline_offset(struct intel_crtc *crtc)
10567 {
10568         struct drm_device *dev = crtc->base.dev;
10569
10570         /*
10571          * The scanline counter increments at the leading edge of hsync.
10572          *
10573          * On most platforms it starts counting from vtotal-1 on the
10574          * first active line. That means the scanline counter value is
10575          * always one less than what we would expect. Ie. just after
10576          * start of vblank, which also occurs at start of hsync (on the
10577          * last active line), the scanline counter will read vblank_start-1.
10578          *
10579          * On gen2 the scanline counter starts counting from 1 instead
10580          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10581          * to keep the value positive), instead of adding one.
10582          *
10583          * On HSW+ the behaviour of the scanline counter depends on the output
10584          * type. For DP ports it behaves like most other platforms, but on HDMI
10585          * there's an extra 1 line difference. So we need to add two instead of
10586          * one to the value.
10587          */
10588         if (IS_GEN2(dev)) {
10589                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10590                 int vtotal;
10591
10592                 vtotal = mode->crtc_vtotal;
10593                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10594                         vtotal /= 2;
10595
10596                 crtc->scanline_offset = vtotal - 1;
10597         } else if (HAS_DDI(dev) &&
10598                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10599                 crtc->scanline_offset = 2;
10600         } else
10601                 crtc->scanline_offset = 1;
10602 }
10603
10604 static int __intel_set_mode(struct drm_crtc *crtc,
10605                             struct drm_display_mode *mode,
10606                             int x, int y, struct drm_framebuffer *fb)
10607 {
10608         struct drm_device *dev = crtc->dev;
10609         struct drm_i915_private *dev_priv = dev->dev_private;
10610         struct drm_display_mode *saved_mode;
10611         struct intel_crtc_config *pipe_config = NULL;
10612         struct intel_crtc *intel_crtc;
10613         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10614         int ret = 0;
10615
10616         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10617         if (!saved_mode)
10618                 return -ENOMEM;
10619
10620         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10621                                      &prepare_pipes, &disable_pipes);
10622
10623         *saved_mode = crtc->mode;
10624
10625         /* Hack: Because we don't (yet) support global modeset on multiple
10626          * crtcs, we don't keep track of the new mode for more than one crtc.
10627          * Hence simply check whether any bit is set in modeset_pipes in all the
10628          * pieces of code that are not yet converted to deal with mutliple crtcs
10629          * changing their mode at the same time. */
10630         if (modeset_pipes) {
10631                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10632                 if (IS_ERR(pipe_config)) {
10633                         ret = PTR_ERR(pipe_config);
10634                         pipe_config = NULL;
10635
10636                         goto out;
10637                 }
10638                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10639                                        "[modeset]");
10640                 to_intel_crtc(crtc)->new_config = pipe_config;
10641         }
10642
10643         /*
10644          * See if the config requires any additional preparation, e.g.
10645          * to adjust global state with pipes off.  We need to do this
10646          * here so we can get the modeset_pipe updated config for the new
10647          * mode set on this crtc.  For other crtcs we need to use the
10648          * adjusted_mode bits in the crtc directly.
10649          */
10650         if (IS_VALLEYVIEW(dev)) {
10651                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10652
10653                 /* may have added more to prepare_pipes than we should */
10654                 prepare_pipes &= ~disable_pipes;
10655         }
10656
10657         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10658                 intel_crtc_disable(&intel_crtc->base);
10659
10660         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10661                 if (intel_crtc->base.enabled)
10662                         dev_priv->display.crtc_disable(&intel_crtc->base);
10663         }
10664
10665         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10666          * to set it here already despite that we pass it down the callchain.
10667          */
10668         if (modeset_pipes) {
10669                 crtc->mode = *mode;
10670                 /* mode_set/enable/disable functions rely on a correct pipe
10671                  * config. */
10672                 to_intel_crtc(crtc)->config = *pipe_config;
10673                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10674
10675                 /*
10676                  * Calculate and store various constants which
10677                  * are later needed by vblank and swap-completion
10678                  * timestamping. They are derived from true hwmode.
10679                  */
10680                 drm_calc_timestamping_constants(crtc,
10681                                                 &pipe_config->adjusted_mode);
10682         }
10683
10684         /* Only after disabling all output pipelines that will be changed can we
10685          * update the the output configuration. */
10686         intel_modeset_update_state(dev, prepare_pipes);
10687
10688         if (dev_priv->display.modeset_global_resources)
10689                 dev_priv->display.modeset_global_resources(dev);
10690
10691         /* Set up the DPLL and any encoders state that needs to adjust or depend
10692          * on the DPLL.
10693          */
10694         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10695                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10696                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10697                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10698
10699                 mutex_lock(&dev->struct_mutex);
10700                 ret = intel_pin_and_fence_fb_obj(dev,
10701                                                  obj,
10702                                                  NULL);
10703                 if (ret != 0) {
10704                         DRM_ERROR("pin & fence failed\n");
10705                         mutex_unlock(&dev->struct_mutex);
10706                         goto done;
10707                 }
10708                 if (old_fb)
10709                         intel_unpin_fb_obj(old_obj);
10710                 i915_gem_track_fb(old_obj, obj,
10711                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10712                 mutex_unlock(&dev->struct_mutex);
10713
10714                 crtc->primary->fb = fb;
10715                 crtc->x = x;
10716                 crtc->y = y;
10717
10718                 ret = dev_priv->display.crtc_mode_set(intel_crtc, x, y, fb);
10719                 if (ret)
10720                         goto done;
10721         }
10722
10723         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10724         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10725                 update_scanline_offset(intel_crtc);
10726
10727                 dev_priv->display.crtc_enable(&intel_crtc->base);
10728         }
10729
10730         /* FIXME: add subpixel order */
10731 done:
10732         if (ret && crtc->enabled)
10733                 crtc->mode = *saved_mode;
10734
10735 out:
10736         kfree(pipe_config);
10737         kfree(saved_mode);
10738         return ret;
10739 }
10740
10741 static int intel_set_mode(struct drm_crtc *crtc,
10742                           struct drm_display_mode *mode,
10743                           int x, int y, struct drm_framebuffer *fb)
10744 {
10745         int ret;
10746
10747         ret = __intel_set_mode(crtc, mode, x, y, fb);
10748
10749         if (ret == 0)
10750                 intel_modeset_check_state(crtc->dev);
10751
10752         return ret;
10753 }
10754
10755 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10756 {
10757         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10758 }
10759
10760 #undef for_each_intel_crtc_masked
10761
10762 static void intel_set_config_free(struct intel_set_config *config)
10763 {
10764         if (!config)
10765                 return;
10766
10767         kfree(config->save_connector_encoders);
10768         kfree(config->save_encoder_crtcs);
10769         kfree(config->save_crtc_enabled);
10770         kfree(config);
10771 }
10772
10773 static int intel_set_config_save_state(struct drm_device *dev,
10774                                        struct intel_set_config *config)
10775 {
10776         struct drm_crtc *crtc;
10777         struct drm_encoder *encoder;
10778         struct drm_connector *connector;
10779         int count;
10780
10781         config->save_crtc_enabled =
10782                 kcalloc(dev->mode_config.num_crtc,
10783                         sizeof(bool), GFP_KERNEL);
10784         if (!config->save_crtc_enabled)
10785                 return -ENOMEM;
10786
10787         config->save_encoder_crtcs =
10788                 kcalloc(dev->mode_config.num_encoder,
10789                         sizeof(struct drm_crtc *), GFP_KERNEL);
10790         if (!config->save_encoder_crtcs)
10791                 return -ENOMEM;
10792
10793         config->save_connector_encoders =
10794                 kcalloc(dev->mode_config.num_connector,
10795                         sizeof(struct drm_encoder *), GFP_KERNEL);
10796         if (!config->save_connector_encoders)
10797                 return -ENOMEM;
10798
10799         /* Copy data. Note that driver private data is not affected.
10800          * Should anything bad happen only the expected state is
10801          * restored, not the drivers personal bookkeeping.
10802          */
10803         count = 0;
10804         for_each_crtc(dev, crtc) {
10805                 config->save_crtc_enabled[count++] = crtc->enabled;
10806         }
10807
10808         count = 0;
10809         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10810                 config->save_encoder_crtcs[count++] = encoder->crtc;
10811         }
10812
10813         count = 0;
10814         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10815                 config->save_connector_encoders[count++] = connector->encoder;
10816         }
10817
10818         return 0;
10819 }
10820
10821 static void intel_set_config_restore_state(struct drm_device *dev,
10822                                            struct intel_set_config *config)
10823 {
10824         struct intel_crtc *crtc;
10825         struct intel_encoder *encoder;
10826         struct intel_connector *connector;
10827         int count;
10828
10829         count = 0;
10830         for_each_intel_crtc(dev, crtc) {
10831                 crtc->new_enabled = config->save_crtc_enabled[count++];
10832
10833                 if (crtc->new_enabled)
10834                         crtc->new_config = &crtc->config;
10835                 else
10836                         crtc->new_config = NULL;
10837         }
10838
10839         count = 0;
10840         for_each_intel_encoder(dev, encoder) {
10841                 encoder->new_crtc =
10842                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10843         }
10844
10845         count = 0;
10846         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10847                 connector->new_encoder =
10848                         to_intel_encoder(config->save_connector_encoders[count++]);
10849         }
10850 }
10851
10852 static bool
10853 is_crtc_connector_off(struct drm_mode_set *set)
10854 {
10855         int i;
10856
10857         if (set->num_connectors == 0)
10858                 return false;
10859
10860         if (WARN_ON(set->connectors == NULL))
10861                 return false;
10862
10863         for (i = 0; i < set->num_connectors; i++)
10864                 if (set->connectors[i]->encoder &&
10865                     set->connectors[i]->encoder->crtc == set->crtc &&
10866                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10867                         return true;
10868
10869         return false;
10870 }
10871
10872 static void
10873 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10874                                       struct intel_set_config *config)
10875 {
10876
10877         /* We should be able to check here if the fb has the same properties
10878          * and then just flip_or_move it */
10879         if (is_crtc_connector_off(set)) {
10880                 config->mode_changed = true;
10881         } else if (set->crtc->primary->fb != set->fb) {
10882                 /*
10883                  * If we have no fb, we can only flip as long as the crtc is
10884                  * active, otherwise we need a full mode set.  The crtc may
10885                  * be active if we've only disabled the primary plane, or
10886                  * in fastboot situations.
10887                  */
10888                 if (set->crtc->primary->fb == NULL) {
10889                         struct intel_crtc *intel_crtc =
10890                                 to_intel_crtc(set->crtc);
10891
10892                         if (intel_crtc->active) {
10893                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10894                                 config->fb_changed = true;
10895                         } else {
10896                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10897                                 config->mode_changed = true;
10898                         }
10899                 } else if (set->fb == NULL) {
10900                         config->mode_changed = true;
10901                 } else if (set->fb->pixel_format !=
10902                            set->crtc->primary->fb->pixel_format) {
10903                         config->mode_changed = true;
10904                 } else {
10905                         config->fb_changed = true;
10906                 }
10907         }
10908
10909         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10910                 config->fb_changed = true;
10911
10912         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10913                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10914                 drm_mode_debug_printmodeline(&set->crtc->mode);
10915                 drm_mode_debug_printmodeline(set->mode);
10916                 config->mode_changed = true;
10917         }
10918
10919         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10920                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10921 }
10922
10923 static int
10924 intel_modeset_stage_output_state(struct drm_device *dev,
10925                                  struct drm_mode_set *set,
10926                                  struct intel_set_config *config)
10927 {
10928         struct intel_connector *connector;
10929         struct intel_encoder *encoder;
10930         struct intel_crtc *crtc;
10931         int ro;
10932
10933         /* The upper layers ensure that we either disable a crtc or have a list
10934          * of connectors. For paranoia, double-check this. */
10935         WARN_ON(!set->fb && (set->num_connectors != 0));
10936         WARN_ON(set->fb && (set->num_connectors == 0));
10937
10938         list_for_each_entry(connector, &dev->mode_config.connector_list,
10939                             base.head) {
10940                 /* Otherwise traverse passed in connector list and get encoders
10941                  * for them. */
10942                 for (ro = 0; ro < set->num_connectors; ro++) {
10943                         if (set->connectors[ro] == &connector->base) {
10944                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
10945                                 break;
10946                         }
10947                 }
10948
10949                 /* If we disable the crtc, disable all its connectors. Also, if
10950                  * the connector is on the changing crtc but not on the new
10951                  * connector list, disable it. */
10952                 if ((!set->fb || ro == set->num_connectors) &&
10953                     connector->base.encoder &&
10954                     connector->base.encoder->crtc == set->crtc) {
10955                         connector->new_encoder = NULL;
10956
10957                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10958                                 connector->base.base.id,
10959                                 connector->base.name);
10960                 }
10961
10962
10963                 if (&connector->new_encoder->base != connector->base.encoder) {
10964                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10965                         config->mode_changed = true;
10966                 }
10967         }
10968         /* connector->new_encoder is now updated for all connectors. */
10969
10970         /* Update crtc of enabled connectors. */
10971         list_for_each_entry(connector, &dev->mode_config.connector_list,
10972                             base.head) {
10973                 struct drm_crtc *new_crtc;
10974
10975                 if (!connector->new_encoder)
10976                         continue;
10977
10978                 new_crtc = connector->new_encoder->base.crtc;
10979
10980                 for (ro = 0; ro < set->num_connectors; ro++) {
10981                         if (set->connectors[ro] == &connector->base)
10982                                 new_crtc = set->crtc;
10983                 }
10984
10985                 /* Make sure the new CRTC will work with the encoder */
10986                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10987                                          new_crtc)) {
10988                         return -EINVAL;
10989                 }
10990                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
10991
10992                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10993                         connector->base.base.id,
10994                         connector->base.name,
10995                         new_crtc->base.id);
10996         }
10997
10998         /* Check for any encoders that needs to be disabled. */
10999         for_each_intel_encoder(dev, encoder) {
11000                 int num_connectors = 0;
11001                 list_for_each_entry(connector,
11002                                     &dev->mode_config.connector_list,
11003                                     base.head) {
11004                         if (connector->new_encoder == encoder) {
11005                                 WARN_ON(!connector->new_encoder->new_crtc);
11006                                 num_connectors++;
11007                         }
11008                 }
11009
11010                 if (num_connectors == 0)
11011                         encoder->new_crtc = NULL;
11012                 else if (num_connectors > 1)
11013                         return -EINVAL;
11014
11015                 /* Only now check for crtc changes so we don't miss encoders
11016                  * that will be disabled. */
11017                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11018                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11019                         config->mode_changed = true;
11020                 }
11021         }
11022         /* Now we've also updated encoder->new_crtc for all encoders. */
11023         list_for_each_entry(connector, &dev->mode_config.connector_list,
11024                             base.head) {
11025                 if (connector->new_encoder)
11026                         if (connector->new_encoder != connector->encoder)
11027                                 connector->encoder = connector->new_encoder;
11028         }
11029         for_each_intel_crtc(dev, crtc) {
11030                 crtc->new_enabled = false;
11031
11032                 for_each_intel_encoder(dev, encoder) {
11033                         if (encoder->new_crtc == crtc) {
11034                                 crtc->new_enabled = true;
11035                                 break;
11036                         }
11037                 }
11038
11039                 if (crtc->new_enabled != crtc->base.enabled) {
11040                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11041                                       crtc->new_enabled ? "en" : "dis");
11042                         config->mode_changed = true;
11043                 }
11044
11045                 if (crtc->new_enabled)
11046                         crtc->new_config = &crtc->config;
11047                 else
11048                         crtc->new_config = NULL;
11049         }
11050
11051         return 0;
11052 }
11053
11054 static void disable_crtc_nofb(struct intel_crtc *crtc)
11055 {
11056         struct drm_device *dev = crtc->base.dev;
11057         struct intel_encoder *encoder;
11058         struct intel_connector *connector;
11059
11060         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11061                       pipe_name(crtc->pipe));
11062
11063         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11064                 if (connector->new_encoder &&
11065                     connector->new_encoder->new_crtc == crtc)
11066                         connector->new_encoder = NULL;
11067         }
11068
11069         for_each_intel_encoder(dev, encoder) {
11070                 if (encoder->new_crtc == crtc)
11071                         encoder->new_crtc = NULL;
11072         }
11073
11074         crtc->new_enabled = false;
11075         crtc->new_config = NULL;
11076 }
11077
11078 static int intel_crtc_set_config(struct drm_mode_set *set)
11079 {
11080         struct drm_device *dev;
11081         struct drm_mode_set save_set;
11082         struct intel_set_config *config;
11083         int ret;
11084
11085         BUG_ON(!set);
11086         BUG_ON(!set->crtc);
11087         BUG_ON(!set->crtc->helper_private);
11088
11089         /* Enforce sane interface api - has been abused by the fb helper. */
11090         BUG_ON(!set->mode && set->fb);
11091         BUG_ON(set->fb && set->num_connectors == 0);
11092
11093         if (set->fb) {
11094                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11095                                 set->crtc->base.id, set->fb->base.id,
11096                                 (int)set->num_connectors, set->x, set->y);
11097         } else {
11098                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11099         }
11100
11101         dev = set->crtc->dev;
11102
11103         ret = -ENOMEM;
11104         config = kzalloc(sizeof(*config), GFP_KERNEL);
11105         if (!config)
11106                 goto out_config;
11107
11108         ret = intel_set_config_save_state(dev, config);
11109         if (ret)
11110                 goto out_config;
11111
11112         save_set.crtc = set->crtc;
11113         save_set.mode = &set->crtc->mode;
11114         save_set.x = set->crtc->x;
11115         save_set.y = set->crtc->y;
11116         save_set.fb = set->crtc->primary->fb;
11117
11118         /* Compute whether we need a full modeset, only an fb base update or no
11119          * change at all. In the future we might also check whether only the
11120          * mode changed, e.g. for LVDS where we only change the panel fitter in
11121          * such cases. */
11122         intel_set_config_compute_mode_changes(set, config);
11123
11124         ret = intel_modeset_stage_output_state(dev, set, config);
11125         if (ret)
11126                 goto fail;
11127
11128         if (config->mode_changed) {
11129                 ret = intel_set_mode(set->crtc, set->mode,
11130                                      set->x, set->y, set->fb);
11131         } else if (config->fb_changed) {
11132                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11133
11134                 intel_crtc_wait_for_pending_flips(set->crtc);
11135
11136                 ret = intel_pipe_set_base(set->crtc,
11137                                           set->x, set->y, set->fb);
11138
11139                 /*
11140                  * We need to make sure the primary plane is re-enabled if it
11141                  * has previously been turned off.
11142                  */
11143                 if (!intel_crtc->primary_enabled && ret == 0) {
11144                         WARN_ON(!intel_crtc->active);
11145                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11146                 }
11147
11148                 /*
11149                  * In the fastboot case this may be our only check of the
11150                  * state after boot.  It would be better to only do it on
11151                  * the first update, but we don't have a nice way of doing that
11152                  * (and really, set_config isn't used much for high freq page
11153                  * flipping, so increasing its cost here shouldn't be a big
11154                  * deal).
11155                  */
11156                 if (i915.fastboot && ret == 0)
11157                         intel_modeset_check_state(set->crtc->dev);
11158         }
11159
11160         if (ret) {
11161                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11162                               set->crtc->base.id, ret);
11163 fail:
11164                 intel_set_config_restore_state(dev, config);
11165
11166                 /*
11167                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11168                  * force the pipe off to avoid oopsing in the modeset code
11169                  * due to fb==NULL. This should only happen during boot since
11170                  * we don't yet reconstruct the FB from the hardware state.
11171                  */
11172                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11173                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11174
11175                 /* Try to restore the config */
11176                 if (config->mode_changed &&
11177                     intel_set_mode(save_set.crtc, save_set.mode,
11178                                    save_set.x, save_set.y, save_set.fb))
11179                         DRM_ERROR("failed to restore config after modeset failure\n");
11180         }
11181
11182 out_config:
11183         intel_set_config_free(config);
11184         return ret;
11185 }
11186
11187 static const struct drm_crtc_funcs intel_crtc_funcs = {
11188         .gamma_set = intel_crtc_gamma_set,
11189         .set_config = intel_crtc_set_config,
11190         .destroy = intel_crtc_destroy,
11191         .page_flip = intel_crtc_page_flip,
11192 };
11193
11194 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11195                                       struct intel_shared_dpll *pll,
11196                                       struct intel_dpll_hw_state *hw_state)
11197 {
11198         uint32_t val;
11199
11200         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11201                 return false;
11202
11203         val = I915_READ(PCH_DPLL(pll->id));
11204         hw_state->dpll = val;
11205         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11206         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11207
11208         return val & DPLL_VCO_ENABLE;
11209 }
11210
11211 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11212                                   struct intel_shared_dpll *pll)
11213 {
11214         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11215         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11216 }
11217
11218 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11219                                 struct intel_shared_dpll *pll)
11220 {
11221         /* PCH refclock must be enabled first */
11222         ibx_assert_pch_refclk_enabled(dev_priv);
11223
11224         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11225
11226         /* Wait for the clocks to stabilize. */
11227         POSTING_READ(PCH_DPLL(pll->id));
11228         udelay(150);
11229
11230         /* The pixel multiplier can only be updated once the
11231          * DPLL is enabled and the clocks are stable.
11232          *
11233          * So write it again.
11234          */
11235         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11236         POSTING_READ(PCH_DPLL(pll->id));
11237         udelay(200);
11238 }
11239
11240 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11241                                  struct intel_shared_dpll *pll)
11242 {
11243         struct drm_device *dev = dev_priv->dev;
11244         struct intel_crtc *crtc;
11245
11246         /* Make sure no transcoder isn't still depending on us. */
11247         for_each_intel_crtc(dev, crtc) {
11248                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11249                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11250         }
11251
11252         I915_WRITE(PCH_DPLL(pll->id), 0);
11253         POSTING_READ(PCH_DPLL(pll->id));
11254         udelay(200);
11255 }
11256
11257 static char *ibx_pch_dpll_names[] = {
11258         "PCH DPLL A",
11259         "PCH DPLL B",
11260 };
11261
11262 static void ibx_pch_dpll_init(struct drm_device *dev)
11263 {
11264         struct drm_i915_private *dev_priv = dev->dev_private;
11265         int i;
11266
11267         dev_priv->num_shared_dpll = 2;
11268
11269         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11270                 dev_priv->shared_dplls[i].id = i;
11271                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11272                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11273                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11274                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11275                 dev_priv->shared_dplls[i].get_hw_state =
11276                         ibx_pch_dpll_get_hw_state;
11277         }
11278 }
11279
11280 static void intel_shared_dpll_init(struct drm_device *dev)
11281 {
11282         struct drm_i915_private *dev_priv = dev->dev_private;
11283
11284         if (HAS_DDI(dev))
11285                 intel_ddi_pll_init(dev);
11286         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11287                 ibx_pch_dpll_init(dev);
11288         else
11289                 dev_priv->num_shared_dpll = 0;
11290
11291         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11292 }
11293
11294 static int
11295 intel_primary_plane_disable(struct drm_plane *plane)
11296 {
11297         struct drm_device *dev = plane->dev;
11298         struct intel_crtc *intel_crtc;
11299
11300         if (!plane->fb)
11301                 return 0;
11302
11303         BUG_ON(!plane->crtc);
11304
11305         intel_crtc = to_intel_crtc(plane->crtc);
11306
11307         /*
11308          * Even though we checked plane->fb above, it's still possible that
11309          * the primary plane has been implicitly disabled because the crtc
11310          * coordinates given weren't visible, or because we detected
11311          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11312          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11313          * In either case, we need to unpin the FB and let the fb pointer get
11314          * updated, but otherwise we don't need to touch the hardware.
11315          */
11316         if (!intel_crtc->primary_enabled)
11317                 goto disable_unpin;
11318
11319         intel_crtc_wait_for_pending_flips(plane->crtc);
11320         intel_disable_primary_hw_plane(plane, plane->crtc);
11321
11322 disable_unpin:
11323         mutex_lock(&dev->struct_mutex);
11324         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11325                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11326         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11327         mutex_unlock(&dev->struct_mutex);
11328         plane->fb = NULL;
11329
11330         return 0;
11331 }
11332
11333 static int
11334 intel_check_primary_plane(struct drm_plane *plane,
11335                           struct intel_plane_state *state)
11336 {
11337         struct drm_crtc *crtc = state->crtc;
11338         struct drm_framebuffer *fb = state->fb;
11339         struct drm_rect *dest = &state->dst;
11340         struct drm_rect *src = &state->src;
11341         const struct drm_rect *clip = &state->clip;
11342
11343         return drm_plane_helper_check_update(plane, crtc, fb,
11344                                              src, dest, clip,
11345                                              DRM_PLANE_HELPER_NO_SCALING,
11346                                              DRM_PLANE_HELPER_NO_SCALING,
11347                                              false, true, &state->visible);
11348 }
11349
11350 static int
11351 intel_commit_primary_plane(struct drm_plane *plane,
11352                            struct intel_plane_state *state)
11353 {
11354         struct drm_crtc *crtc = state->crtc;
11355         struct drm_framebuffer *fb = state->fb;
11356         struct drm_device *dev = crtc->dev;
11357         struct drm_i915_private *dev_priv = dev->dev_private;
11358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11359         enum pipe pipe = intel_crtc->pipe;
11360         struct drm_framebuffer *old_fb = plane->fb;
11361         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11362         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11363         struct intel_plane *intel_plane = to_intel_plane(plane);
11364         struct drm_rect *src = &state->src;
11365         int ret;
11366
11367         intel_crtc_wait_for_pending_flips(crtc);
11368
11369         if (intel_crtc_has_pending_flip(crtc)) {
11370                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11371                 return -EBUSY;
11372         }
11373
11374         if (plane->fb != fb) {
11375                 mutex_lock(&dev->struct_mutex);
11376                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11377                 if (ret == 0)
11378                         i915_gem_track_fb(old_obj, obj,
11379                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11380                 mutex_unlock(&dev->struct_mutex);
11381                 if (ret != 0) {
11382                         DRM_DEBUG_KMS("pin & fence failed\n");
11383                         return ret;
11384                 }
11385         }
11386
11387         crtc->primary->fb = fb;
11388         crtc->x = src->x1;
11389         crtc->y = src->y1;
11390
11391         intel_plane->crtc_x = state->orig_dst.x1;
11392         intel_plane->crtc_y = state->orig_dst.y1;
11393         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11394         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11395         intel_plane->src_x = state->orig_src.x1;
11396         intel_plane->src_y = state->orig_src.y1;
11397         intel_plane->src_w = drm_rect_width(&state->orig_src);
11398         intel_plane->src_h = drm_rect_height(&state->orig_src);
11399         intel_plane->obj = obj;
11400
11401         if (intel_crtc->active) {
11402                 /*
11403                  * FBC does not work on some platforms for rotated
11404                  * planes, so disable it when rotation is not 0 and
11405                  * update it when rotation is set back to 0.
11406                  *
11407                  * FIXME: This is redundant with the fbc update done in
11408                  * the primary plane enable function except that that
11409                  * one is done too late. We eventually need to unify
11410                  * this.
11411                  */
11412                 if (intel_crtc->primary_enabled &&
11413                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11414                     dev_priv->fbc.plane == intel_crtc->plane &&
11415                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11416                         intel_disable_fbc(dev);
11417                 }
11418
11419                 if (state->visible) {
11420                         bool was_enabled = intel_crtc->primary_enabled;
11421
11422                         /* FIXME: kill this fastboot hack */
11423                         intel_update_pipe_size(intel_crtc);
11424
11425                         intel_crtc->primary_enabled = true;
11426
11427                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11428                                         crtc->x, crtc->y);
11429
11430                         /*
11431                          * BDW signals flip done immediately if the plane
11432                          * is disabled, even if the plane enable is already
11433                          * armed to occur at the next vblank :(
11434                          */
11435                         if (IS_BROADWELL(dev) && !was_enabled)
11436                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11437                 } else {
11438                         /*
11439                          * If clipping results in a non-visible primary plane,
11440                          * we'll disable the primary plane.  Note that this is
11441                          * a bit different than what happens if userspace
11442                          * explicitly disables the plane by passing fb=0
11443                          * because plane->fb still gets set and pinned.
11444                          */
11445                         intel_disable_primary_hw_plane(plane, crtc);
11446                 }
11447
11448                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11449
11450                 mutex_lock(&dev->struct_mutex);
11451                 intel_update_fbc(dev);
11452                 mutex_unlock(&dev->struct_mutex);
11453         }
11454
11455         if (old_fb && old_fb != fb) {
11456                 if (intel_crtc->active)
11457                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11458
11459                 mutex_lock(&dev->struct_mutex);
11460                 intel_unpin_fb_obj(old_obj);
11461                 mutex_unlock(&dev->struct_mutex);
11462         }
11463
11464         return 0;
11465 }
11466
11467 static int
11468 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11469                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11470                              unsigned int crtc_w, unsigned int crtc_h,
11471                              uint32_t src_x, uint32_t src_y,
11472                              uint32_t src_w, uint32_t src_h)
11473 {
11474         struct intel_plane_state state;
11475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11476         int ret;
11477
11478         state.crtc = crtc;
11479         state.fb = fb;
11480
11481         /* sample coordinates in 16.16 fixed point */
11482         state.src.x1 = src_x;
11483         state.src.x2 = src_x + src_w;
11484         state.src.y1 = src_y;
11485         state.src.y2 = src_y + src_h;
11486
11487         /* integer pixels */
11488         state.dst.x1 = crtc_x;
11489         state.dst.x2 = crtc_x + crtc_w;
11490         state.dst.y1 = crtc_y;
11491         state.dst.y2 = crtc_y + crtc_h;
11492
11493         state.clip.x1 = 0;
11494         state.clip.y1 = 0;
11495         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11496         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11497
11498         state.orig_src = state.src;
11499         state.orig_dst = state.dst;
11500
11501         ret = intel_check_primary_plane(plane, &state);
11502         if (ret)
11503                 return ret;
11504
11505         intel_commit_primary_plane(plane, &state);
11506
11507         return 0;
11508 }
11509
11510 /* Common destruction function for both primary and cursor planes */
11511 static void intel_plane_destroy(struct drm_plane *plane)
11512 {
11513         struct intel_plane *intel_plane = to_intel_plane(plane);
11514         drm_plane_cleanup(plane);
11515         kfree(intel_plane);
11516 }
11517
11518 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11519         .update_plane = intel_primary_plane_setplane,
11520         .disable_plane = intel_primary_plane_disable,
11521         .destroy = intel_plane_destroy,
11522         .set_property = intel_plane_set_property
11523 };
11524
11525 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11526                                                     int pipe)
11527 {
11528         struct intel_plane *primary;
11529         const uint32_t *intel_primary_formats;
11530         int num_formats;
11531
11532         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11533         if (primary == NULL)
11534                 return NULL;
11535
11536         primary->can_scale = false;
11537         primary->max_downscale = 1;
11538         primary->pipe = pipe;
11539         primary->plane = pipe;
11540         primary->rotation = BIT(DRM_ROTATE_0);
11541         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11542                 primary->plane = !pipe;
11543
11544         if (INTEL_INFO(dev)->gen <= 3) {
11545                 intel_primary_formats = intel_primary_formats_gen2;
11546                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11547         } else {
11548                 intel_primary_formats = intel_primary_formats_gen4;
11549                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11550         }
11551
11552         drm_universal_plane_init(dev, &primary->base, 0,
11553                                  &intel_primary_plane_funcs,
11554                                  intel_primary_formats, num_formats,
11555                                  DRM_PLANE_TYPE_PRIMARY);
11556
11557         if (INTEL_INFO(dev)->gen >= 4) {
11558                 if (!dev->mode_config.rotation_property)
11559                         dev->mode_config.rotation_property =
11560                                 drm_mode_create_rotation_property(dev,
11561                                                         BIT(DRM_ROTATE_0) |
11562                                                         BIT(DRM_ROTATE_180));
11563                 if (dev->mode_config.rotation_property)
11564                         drm_object_attach_property(&primary->base.base,
11565                                 dev->mode_config.rotation_property,
11566                                 primary->rotation);
11567         }
11568
11569         return &primary->base;
11570 }
11571
11572 static int
11573 intel_cursor_plane_disable(struct drm_plane *plane)
11574 {
11575         if (!plane->fb)
11576                 return 0;
11577
11578         BUG_ON(!plane->crtc);
11579
11580         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11581 }
11582
11583 static int
11584 intel_check_cursor_plane(struct drm_plane *plane,
11585                          struct intel_plane_state *state)
11586 {
11587         struct drm_crtc *crtc = state->crtc;
11588         struct drm_device *dev = crtc->dev;
11589         struct drm_framebuffer *fb = state->fb;
11590         struct drm_rect *dest = &state->dst;
11591         struct drm_rect *src = &state->src;
11592         const struct drm_rect *clip = &state->clip;
11593         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11594         int crtc_w, crtc_h;
11595         unsigned stride;
11596         int ret;
11597
11598         ret = drm_plane_helper_check_update(plane, crtc, fb,
11599                                             src, dest, clip,
11600                                             DRM_PLANE_HELPER_NO_SCALING,
11601                                             DRM_PLANE_HELPER_NO_SCALING,
11602                                             true, true, &state->visible);
11603         if (ret)
11604                 return ret;
11605
11606
11607         /* if we want to turn off the cursor ignore width and height */
11608         if (!obj)
11609                 return 0;
11610
11611         /* Check for which cursor types we support */
11612         crtc_w = drm_rect_width(&state->orig_dst);
11613         crtc_h = drm_rect_height(&state->orig_dst);
11614         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11615                 DRM_DEBUG("Cursor dimension not supported\n");
11616                 return -EINVAL;
11617         }
11618
11619         stride = roundup_pow_of_two(crtc_w) * 4;
11620         if (obj->base.size < stride * crtc_h) {
11621                 DRM_DEBUG_KMS("buffer is too small\n");
11622                 return -ENOMEM;
11623         }
11624
11625         if (fb == crtc->cursor->fb)
11626                 return 0;
11627
11628         /* we only need to pin inside GTT if cursor is non-phy */
11629         mutex_lock(&dev->struct_mutex);
11630         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11631                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11632                 ret = -EINVAL;
11633         }
11634         mutex_unlock(&dev->struct_mutex);
11635
11636         return ret;
11637 }
11638
11639 static int
11640 intel_commit_cursor_plane(struct drm_plane *plane,
11641                           struct intel_plane_state *state)
11642 {
11643         struct drm_crtc *crtc = state->crtc;
11644         struct drm_framebuffer *fb = state->fb;
11645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11646         struct intel_plane *intel_plane = to_intel_plane(plane);
11647         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11648         struct drm_i915_gem_object *obj = intel_fb->obj;
11649         int crtc_w, crtc_h;
11650
11651         crtc->cursor_x = state->orig_dst.x1;
11652         crtc->cursor_y = state->orig_dst.y1;
11653
11654         intel_plane->crtc_x = state->orig_dst.x1;
11655         intel_plane->crtc_y = state->orig_dst.y1;
11656         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11657         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11658         intel_plane->src_x = state->orig_src.x1;
11659         intel_plane->src_y = state->orig_src.y1;
11660         intel_plane->src_w = drm_rect_width(&state->orig_src);
11661         intel_plane->src_h = drm_rect_height(&state->orig_src);
11662         intel_plane->obj = obj;
11663
11664         if (fb != crtc->cursor->fb) {
11665                 crtc_w = drm_rect_width(&state->orig_dst);
11666                 crtc_h = drm_rect_height(&state->orig_dst);
11667                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11668         } else {
11669                 intel_crtc_update_cursor(crtc, state->visible);
11670
11671                 intel_frontbuffer_flip(crtc->dev,
11672                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11673
11674                 return 0;
11675         }
11676 }
11677
11678 static int
11679 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11680                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11681                           unsigned int crtc_w, unsigned int crtc_h,
11682                           uint32_t src_x, uint32_t src_y,
11683                           uint32_t src_w, uint32_t src_h)
11684 {
11685         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11686         struct intel_plane_state state;
11687         int ret;
11688
11689         state.crtc = crtc;
11690         state.fb = fb;
11691
11692         /* sample coordinates in 16.16 fixed point */
11693         state.src.x1 = src_x;
11694         state.src.x2 = src_x + src_w;
11695         state.src.y1 = src_y;
11696         state.src.y2 = src_y + src_h;
11697
11698         /* integer pixels */
11699         state.dst.x1 = crtc_x;
11700         state.dst.x2 = crtc_x + crtc_w;
11701         state.dst.y1 = crtc_y;
11702         state.dst.y2 = crtc_y + crtc_h;
11703
11704         state.clip.x1 = 0;
11705         state.clip.y1 = 0;
11706         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11707         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11708
11709         state.orig_src = state.src;
11710         state.orig_dst = state.dst;
11711
11712         ret = intel_check_cursor_plane(plane, &state);
11713         if (ret)
11714                 return ret;
11715
11716         return intel_commit_cursor_plane(plane, &state);
11717 }
11718
11719 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11720         .update_plane = intel_cursor_plane_update,
11721         .disable_plane = intel_cursor_plane_disable,
11722         .destroy = intel_plane_destroy,
11723         .set_property = intel_plane_set_property,
11724 };
11725
11726 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11727                                                    int pipe)
11728 {
11729         struct intel_plane *cursor;
11730
11731         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11732         if (cursor == NULL)
11733                 return NULL;
11734
11735         cursor->can_scale = false;
11736         cursor->max_downscale = 1;
11737         cursor->pipe = pipe;
11738         cursor->plane = pipe;
11739         cursor->rotation = BIT(DRM_ROTATE_0);
11740
11741         drm_universal_plane_init(dev, &cursor->base, 0,
11742                                  &intel_cursor_plane_funcs,
11743                                  intel_cursor_formats,
11744                                  ARRAY_SIZE(intel_cursor_formats),
11745                                  DRM_PLANE_TYPE_CURSOR);
11746
11747         if (INTEL_INFO(dev)->gen >= 4) {
11748                 if (!dev->mode_config.rotation_property)
11749                         dev->mode_config.rotation_property =
11750                                 drm_mode_create_rotation_property(dev,
11751                                                         BIT(DRM_ROTATE_0) |
11752                                                         BIT(DRM_ROTATE_180));
11753                 if (dev->mode_config.rotation_property)
11754                         drm_object_attach_property(&cursor->base.base,
11755                                 dev->mode_config.rotation_property,
11756                                 cursor->rotation);
11757         }
11758
11759         return &cursor->base;
11760 }
11761
11762 static void intel_crtc_init(struct drm_device *dev, int pipe)
11763 {
11764         struct drm_i915_private *dev_priv = dev->dev_private;
11765         struct intel_crtc *intel_crtc;
11766         struct drm_plane *primary = NULL;
11767         struct drm_plane *cursor = NULL;
11768         int i, ret;
11769
11770         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11771         if (intel_crtc == NULL)
11772                 return;
11773
11774         primary = intel_primary_plane_create(dev, pipe);
11775         if (!primary)
11776                 goto fail;
11777
11778         cursor = intel_cursor_plane_create(dev, pipe);
11779         if (!cursor)
11780                 goto fail;
11781
11782         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11783                                         cursor, &intel_crtc_funcs);
11784         if (ret)
11785                 goto fail;
11786
11787         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11788         for (i = 0; i < 256; i++) {
11789                 intel_crtc->lut_r[i] = i;
11790                 intel_crtc->lut_g[i] = i;
11791                 intel_crtc->lut_b[i] = i;
11792         }
11793
11794         /*
11795          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11796          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11797          */
11798         intel_crtc->pipe = pipe;
11799         intel_crtc->plane = pipe;
11800         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11801                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11802                 intel_crtc->plane = !pipe;
11803         }
11804
11805         intel_crtc->cursor_base = ~0;
11806         intel_crtc->cursor_cntl = ~0;
11807         intel_crtc->cursor_size = ~0;
11808
11809         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11810                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11811         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11812         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11813
11814         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11815
11816         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11817         return;
11818
11819 fail:
11820         if (primary)
11821                 drm_plane_cleanup(primary);
11822         if (cursor)
11823                 drm_plane_cleanup(cursor);
11824         kfree(intel_crtc);
11825 }
11826
11827 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11828 {
11829         struct drm_encoder *encoder = connector->base.encoder;
11830         struct drm_device *dev = connector->base.dev;
11831
11832         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11833
11834         if (!encoder)
11835                 return INVALID_PIPE;
11836
11837         return to_intel_crtc(encoder->crtc)->pipe;
11838 }
11839
11840 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11841                                 struct drm_file *file)
11842 {
11843         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11844         struct drm_crtc *drmmode_crtc;
11845         struct intel_crtc *crtc;
11846
11847         if (!drm_core_check_feature(dev, DRIVER_MODESET))
11848                 return -ENODEV;
11849
11850         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11851
11852         if (!drmmode_crtc) {
11853                 DRM_ERROR("no such CRTC id\n");
11854                 return -ENOENT;
11855         }
11856
11857         crtc = to_intel_crtc(drmmode_crtc);
11858         pipe_from_crtc_id->pipe = crtc->pipe;
11859
11860         return 0;
11861 }
11862
11863 static int intel_encoder_clones(struct intel_encoder *encoder)
11864 {
11865         struct drm_device *dev = encoder->base.dev;
11866         struct intel_encoder *source_encoder;
11867         int index_mask = 0;
11868         int entry = 0;
11869
11870         for_each_intel_encoder(dev, source_encoder) {
11871                 if (encoders_cloneable(encoder, source_encoder))
11872                         index_mask |= (1 << entry);
11873
11874                 entry++;
11875         }
11876
11877         return index_mask;
11878 }
11879
11880 static bool has_edp_a(struct drm_device *dev)
11881 {
11882         struct drm_i915_private *dev_priv = dev->dev_private;
11883
11884         if (!IS_MOBILE(dev))
11885                 return false;
11886
11887         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11888                 return false;
11889
11890         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11891                 return false;
11892
11893         return true;
11894 }
11895
11896 const char *intel_output_name(int output)
11897 {
11898         static const char *names[] = {
11899                 [INTEL_OUTPUT_UNUSED] = "Unused",
11900                 [INTEL_OUTPUT_ANALOG] = "Analog",
11901                 [INTEL_OUTPUT_DVO] = "DVO",
11902                 [INTEL_OUTPUT_SDVO] = "SDVO",
11903                 [INTEL_OUTPUT_LVDS] = "LVDS",
11904                 [INTEL_OUTPUT_TVOUT] = "TV",
11905                 [INTEL_OUTPUT_HDMI] = "HDMI",
11906                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11907                 [INTEL_OUTPUT_EDP] = "eDP",
11908                 [INTEL_OUTPUT_DSI] = "DSI",
11909                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11910         };
11911
11912         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11913                 return "Invalid";
11914
11915         return names[output];
11916 }
11917
11918 static bool intel_crt_present(struct drm_device *dev)
11919 {
11920         struct drm_i915_private *dev_priv = dev->dev_private;
11921
11922         if (INTEL_INFO(dev)->gen >= 9)
11923                 return false;
11924
11925         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
11926                 return false;
11927
11928         if (IS_CHERRYVIEW(dev))
11929                 return false;
11930
11931         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11932                 return false;
11933
11934         return true;
11935 }
11936
11937 static void intel_setup_outputs(struct drm_device *dev)
11938 {
11939         struct drm_i915_private *dev_priv = dev->dev_private;
11940         struct intel_encoder *encoder;
11941         bool dpd_is_edp = false;
11942
11943         intel_lvds_init(dev);
11944
11945         if (intel_crt_present(dev))
11946                 intel_crt_init(dev);
11947
11948         if (HAS_DDI(dev)) {
11949                 int found;
11950
11951                 /* Haswell uses DDI functions to detect digital outputs */
11952                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11953                 /* DDI A only supports eDP */
11954                 if (found)
11955                         intel_ddi_init(dev, PORT_A);
11956
11957                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11958                  * register */
11959                 found = I915_READ(SFUSE_STRAP);
11960
11961                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11962                         intel_ddi_init(dev, PORT_B);
11963                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11964                         intel_ddi_init(dev, PORT_C);
11965                 if (found & SFUSE_STRAP_DDID_DETECTED)
11966                         intel_ddi_init(dev, PORT_D);
11967         } else if (HAS_PCH_SPLIT(dev)) {
11968                 int found;
11969                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11970
11971                 if (has_edp_a(dev))
11972                         intel_dp_init(dev, DP_A, PORT_A);
11973
11974                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11975                         /* PCH SDVOB multiplex with HDMIB */
11976                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11977                         if (!found)
11978                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11979                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11980                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11981                 }
11982
11983                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11984                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11985
11986                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11987                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11988
11989                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11990                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11991
11992                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11993                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11994         } else if (IS_VALLEYVIEW(dev)) {
11995                 /*
11996                  * The DP_DETECTED bit is the latched state of the DDC
11997                  * SDA pin at boot. However since eDP doesn't require DDC
11998                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
11999                  * eDP ports may have been muxed to an alternate function.
12000                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12001                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12002                  * detect eDP ports.
12003                  */
12004                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12005                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12006                                         PORT_B);
12007                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12008                     intel_dp_is_edp(dev, PORT_B))
12009                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12010
12011                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12012                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12013                                         PORT_C);
12014                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12015                     intel_dp_is_edp(dev, PORT_C))
12016                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12017
12018                 if (IS_CHERRYVIEW(dev)) {
12019                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12020                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12021                                                 PORT_D);
12022                         /* eDP not supported on port D, so don't check VBT */
12023                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12024                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12025                 }
12026
12027                 intel_dsi_init(dev);
12028         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12029                 bool found = false;
12030
12031                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12032                         DRM_DEBUG_KMS("probing SDVOB\n");
12033                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12034                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12035                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12036                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12037                         }
12038
12039                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12040                                 intel_dp_init(dev, DP_B, PORT_B);
12041                 }
12042
12043                 /* Before G4X SDVOC doesn't have its own detect register */
12044
12045                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12046                         DRM_DEBUG_KMS("probing SDVOC\n");
12047                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12048                 }
12049
12050                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12051
12052                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12053                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12054                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12055                         }
12056                         if (SUPPORTS_INTEGRATED_DP(dev))
12057                                 intel_dp_init(dev, DP_C, PORT_C);
12058                 }
12059
12060                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12061                     (I915_READ(DP_D) & DP_DETECTED))
12062                         intel_dp_init(dev, DP_D, PORT_D);
12063         } else if (IS_GEN2(dev))
12064                 intel_dvo_init(dev);
12065
12066         if (SUPPORTS_TV(dev))
12067                 intel_tv_init(dev);
12068
12069         intel_edp_psr_init(dev);
12070
12071         for_each_intel_encoder(dev, encoder) {
12072                 encoder->base.possible_crtcs = encoder->crtc_mask;
12073                 encoder->base.possible_clones =
12074                         intel_encoder_clones(encoder);
12075         }
12076
12077         intel_init_pch_refclk(dev);
12078
12079         drm_helper_move_panel_connectors_to_head(dev);
12080 }
12081
12082 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12083 {
12084         struct drm_device *dev = fb->dev;
12085         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12086
12087         drm_framebuffer_cleanup(fb);
12088         mutex_lock(&dev->struct_mutex);
12089         WARN_ON(!intel_fb->obj->framebuffer_references--);
12090         drm_gem_object_unreference(&intel_fb->obj->base);
12091         mutex_unlock(&dev->struct_mutex);
12092         kfree(intel_fb);
12093 }
12094
12095 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12096                                                 struct drm_file *file,
12097                                                 unsigned int *handle)
12098 {
12099         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12100         struct drm_i915_gem_object *obj = intel_fb->obj;
12101
12102         return drm_gem_handle_create(file, &obj->base, handle);
12103 }
12104
12105 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12106         .destroy = intel_user_framebuffer_destroy,
12107         .create_handle = intel_user_framebuffer_create_handle,
12108 };
12109
12110 static int intel_framebuffer_init(struct drm_device *dev,
12111                                   struct intel_framebuffer *intel_fb,
12112                                   struct drm_mode_fb_cmd2 *mode_cmd,
12113                                   struct drm_i915_gem_object *obj)
12114 {
12115         int aligned_height;
12116         int pitch_limit;
12117         int ret;
12118
12119         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12120
12121         if (obj->tiling_mode == I915_TILING_Y) {
12122                 DRM_DEBUG("hardware does not support tiling Y\n");
12123                 return -EINVAL;
12124         }
12125
12126         if (mode_cmd->pitches[0] & 63) {
12127                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12128                           mode_cmd->pitches[0]);
12129                 return -EINVAL;
12130         }
12131
12132         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12133                 pitch_limit = 32*1024;
12134         } else if (INTEL_INFO(dev)->gen >= 4) {
12135                 if (obj->tiling_mode)
12136                         pitch_limit = 16*1024;
12137                 else
12138                         pitch_limit = 32*1024;
12139         } else if (INTEL_INFO(dev)->gen >= 3) {
12140                 if (obj->tiling_mode)
12141                         pitch_limit = 8*1024;
12142                 else
12143                         pitch_limit = 16*1024;
12144         } else
12145                 /* XXX DSPC is limited to 4k tiled */
12146                 pitch_limit = 8*1024;
12147
12148         if (mode_cmd->pitches[0] > pitch_limit) {
12149                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12150                           obj->tiling_mode ? "tiled" : "linear",
12151                           mode_cmd->pitches[0], pitch_limit);
12152                 return -EINVAL;
12153         }
12154
12155         if (obj->tiling_mode != I915_TILING_NONE &&
12156             mode_cmd->pitches[0] != obj->stride) {
12157                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12158                           mode_cmd->pitches[0], obj->stride);
12159                 return -EINVAL;
12160         }
12161
12162         /* Reject formats not supported by any plane early. */
12163         switch (mode_cmd->pixel_format) {
12164         case DRM_FORMAT_C8:
12165         case DRM_FORMAT_RGB565:
12166         case DRM_FORMAT_XRGB8888:
12167         case DRM_FORMAT_ARGB8888:
12168                 break;
12169         case DRM_FORMAT_XRGB1555:
12170         case DRM_FORMAT_ARGB1555:
12171                 if (INTEL_INFO(dev)->gen > 3) {
12172                         DRM_DEBUG("unsupported pixel format: %s\n",
12173                                   drm_get_format_name(mode_cmd->pixel_format));
12174                         return -EINVAL;
12175                 }
12176                 break;
12177         case DRM_FORMAT_XBGR8888:
12178         case DRM_FORMAT_ABGR8888:
12179         case DRM_FORMAT_XRGB2101010:
12180         case DRM_FORMAT_ARGB2101010:
12181         case DRM_FORMAT_XBGR2101010:
12182         case DRM_FORMAT_ABGR2101010:
12183                 if (INTEL_INFO(dev)->gen < 4) {
12184                         DRM_DEBUG("unsupported pixel format: %s\n",
12185                                   drm_get_format_name(mode_cmd->pixel_format));
12186                         return -EINVAL;
12187                 }
12188                 break;
12189         case DRM_FORMAT_YUYV:
12190         case DRM_FORMAT_UYVY:
12191         case DRM_FORMAT_YVYU:
12192         case DRM_FORMAT_VYUY:
12193                 if (INTEL_INFO(dev)->gen < 5) {
12194                         DRM_DEBUG("unsupported pixel format: %s\n",
12195                                   drm_get_format_name(mode_cmd->pixel_format));
12196                         return -EINVAL;
12197                 }
12198                 break;
12199         default:
12200                 DRM_DEBUG("unsupported pixel format: %s\n",
12201                           drm_get_format_name(mode_cmd->pixel_format));
12202                 return -EINVAL;
12203         }
12204
12205         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12206         if (mode_cmd->offsets[0] != 0)
12207                 return -EINVAL;
12208
12209         aligned_height = intel_align_height(dev, mode_cmd->height,
12210                                             obj->tiling_mode);
12211         /* FIXME drm helper for size checks (especially planar formats)? */
12212         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12213                 return -EINVAL;
12214
12215         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12216         intel_fb->obj = obj;
12217         intel_fb->obj->framebuffer_references++;
12218
12219         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12220         if (ret) {
12221                 DRM_ERROR("framebuffer init failed %d\n", ret);
12222                 return ret;
12223         }
12224
12225         return 0;
12226 }
12227
12228 static struct drm_framebuffer *
12229 intel_user_framebuffer_create(struct drm_device *dev,
12230                               struct drm_file *filp,
12231                               struct drm_mode_fb_cmd2 *mode_cmd)
12232 {
12233         struct drm_i915_gem_object *obj;
12234
12235         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12236                                                 mode_cmd->handles[0]));
12237         if (&obj->base == NULL)
12238                 return ERR_PTR(-ENOENT);
12239
12240         return intel_framebuffer_create(dev, mode_cmd, obj);
12241 }
12242
12243 #ifndef CONFIG_DRM_I915_FBDEV
12244 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12245 {
12246 }
12247 #endif
12248
12249 static const struct drm_mode_config_funcs intel_mode_funcs = {
12250         .fb_create = intel_user_framebuffer_create,
12251         .output_poll_changed = intel_fbdev_output_poll_changed,
12252 };
12253
12254 /* Set up chip specific display functions */
12255 static void intel_init_display(struct drm_device *dev)
12256 {
12257         struct drm_i915_private *dev_priv = dev->dev_private;
12258
12259         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12260                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12261         else if (IS_CHERRYVIEW(dev))
12262                 dev_priv->display.find_dpll = chv_find_best_dpll;
12263         else if (IS_VALLEYVIEW(dev))
12264                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12265         else if (IS_PINEVIEW(dev))
12266                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12267         else
12268                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12269
12270         if (HAS_DDI(dev)) {
12271                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12272                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12273                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12274                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12275                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12276                 dev_priv->display.off = ironlake_crtc_off;
12277                 if (INTEL_INFO(dev)->gen >= 9)
12278                         dev_priv->display.update_primary_plane =
12279                                 skylake_update_primary_plane;
12280                 else
12281                         dev_priv->display.update_primary_plane =
12282                                 ironlake_update_primary_plane;
12283         } else if (HAS_PCH_SPLIT(dev)) {
12284                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12285                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12286                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12287                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12288                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12289                 dev_priv->display.off = ironlake_crtc_off;
12290                 dev_priv->display.update_primary_plane =
12291                         ironlake_update_primary_plane;
12292         } else if (IS_VALLEYVIEW(dev)) {
12293                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12294                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12295                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12296                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12297                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12298                 dev_priv->display.off = i9xx_crtc_off;
12299                 dev_priv->display.update_primary_plane =
12300                         i9xx_update_primary_plane;
12301         } else {
12302                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12303                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12304                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12305                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12306                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12307                 dev_priv->display.off = i9xx_crtc_off;
12308                 dev_priv->display.update_primary_plane =
12309                         i9xx_update_primary_plane;
12310         }
12311
12312         /* Returns the core display clock speed */
12313         if (IS_VALLEYVIEW(dev))
12314                 dev_priv->display.get_display_clock_speed =
12315                         valleyview_get_display_clock_speed;
12316         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12317                 dev_priv->display.get_display_clock_speed =
12318                         i945_get_display_clock_speed;
12319         else if (IS_I915G(dev))
12320                 dev_priv->display.get_display_clock_speed =
12321                         i915_get_display_clock_speed;
12322         else if (IS_I945GM(dev) || IS_845G(dev))
12323                 dev_priv->display.get_display_clock_speed =
12324                         i9xx_misc_get_display_clock_speed;
12325         else if (IS_PINEVIEW(dev))
12326                 dev_priv->display.get_display_clock_speed =
12327                         pnv_get_display_clock_speed;
12328         else if (IS_I915GM(dev))
12329                 dev_priv->display.get_display_clock_speed =
12330                         i915gm_get_display_clock_speed;
12331         else if (IS_I865G(dev))
12332                 dev_priv->display.get_display_clock_speed =
12333                         i865_get_display_clock_speed;
12334         else if (IS_I85X(dev))
12335                 dev_priv->display.get_display_clock_speed =
12336                         i855_get_display_clock_speed;
12337         else /* 852, 830 */
12338                 dev_priv->display.get_display_clock_speed =
12339                         i830_get_display_clock_speed;
12340
12341         if (IS_GEN5(dev)) {
12342                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12343         } else if (IS_GEN6(dev)) {
12344                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12345                 dev_priv->display.modeset_global_resources =
12346                         snb_modeset_global_resources;
12347         } else if (IS_IVYBRIDGE(dev)) {
12348                 /* FIXME: detect B0+ stepping and use auto training */
12349                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12350                 dev_priv->display.modeset_global_resources =
12351                         ivb_modeset_global_resources;
12352         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12353                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12354                 dev_priv->display.modeset_global_resources =
12355                         haswell_modeset_global_resources;
12356         } else if (IS_VALLEYVIEW(dev)) {
12357                 dev_priv->display.modeset_global_resources =
12358                         valleyview_modeset_global_resources;
12359         } else if (INTEL_INFO(dev)->gen >= 9) {
12360                 dev_priv->display.modeset_global_resources =
12361                         haswell_modeset_global_resources;
12362         }
12363
12364         /* Default just returns -ENODEV to indicate unsupported */
12365         dev_priv->display.queue_flip = intel_default_queue_flip;
12366
12367         switch (INTEL_INFO(dev)->gen) {
12368         case 2:
12369                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12370                 break;
12371
12372         case 3:
12373                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12374                 break;
12375
12376         case 4:
12377         case 5:
12378                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12379                 break;
12380
12381         case 6:
12382                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12383                 break;
12384         case 7:
12385         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12386                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12387                 break;
12388         }
12389
12390         intel_panel_init_backlight_funcs(dev);
12391
12392         mutex_init(&dev_priv->pps_mutex);
12393 }
12394
12395 /*
12396  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12397  * resume, or other times.  This quirk makes sure that's the case for
12398  * affected systems.
12399  */
12400 static void quirk_pipea_force(struct drm_device *dev)
12401 {
12402         struct drm_i915_private *dev_priv = dev->dev_private;
12403
12404         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12405         DRM_INFO("applying pipe a force quirk\n");
12406 }
12407
12408 static void quirk_pipeb_force(struct drm_device *dev)
12409 {
12410         struct drm_i915_private *dev_priv = dev->dev_private;
12411
12412         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12413         DRM_INFO("applying pipe b force quirk\n");
12414 }
12415
12416 /*
12417  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12418  */
12419 static void quirk_ssc_force_disable(struct drm_device *dev)
12420 {
12421         struct drm_i915_private *dev_priv = dev->dev_private;
12422         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12423         DRM_INFO("applying lvds SSC disable quirk\n");
12424 }
12425
12426 /*
12427  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12428  * brightness value
12429  */
12430 static void quirk_invert_brightness(struct drm_device *dev)
12431 {
12432         struct drm_i915_private *dev_priv = dev->dev_private;
12433         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12434         DRM_INFO("applying inverted panel brightness quirk\n");
12435 }
12436
12437 /* Some VBT's incorrectly indicate no backlight is present */
12438 static void quirk_backlight_present(struct drm_device *dev)
12439 {
12440         struct drm_i915_private *dev_priv = dev->dev_private;
12441         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12442         DRM_INFO("applying backlight present quirk\n");
12443 }
12444
12445 struct intel_quirk {
12446         int device;
12447         int subsystem_vendor;
12448         int subsystem_device;
12449         void (*hook)(struct drm_device *dev);
12450 };
12451
12452 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12453 struct intel_dmi_quirk {
12454         void (*hook)(struct drm_device *dev);
12455         const struct dmi_system_id (*dmi_id_list)[];
12456 };
12457
12458 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12459 {
12460         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12461         return 1;
12462 }
12463
12464 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12465         {
12466                 .dmi_id_list = &(const struct dmi_system_id[]) {
12467                         {
12468                                 .callback = intel_dmi_reverse_brightness,
12469                                 .ident = "NCR Corporation",
12470                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12471                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12472                                 },
12473                         },
12474                         { }  /* terminating entry */
12475                 },
12476                 .hook = quirk_invert_brightness,
12477         },
12478 };
12479
12480 static struct intel_quirk intel_quirks[] = {
12481         /* HP Mini needs pipe A force quirk (LP: #322104) */
12482         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12483
12484         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12485         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12486
12487         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12488         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12489
12490         /* 830 needs to leave pipe A & dpll A up */
12491         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12492
12493         /* 830 needs to leave pipe B & dpll B up */
12494         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12495
12496         /* Lenovo U160 cannot use SSC on LVDS */
12497         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12498
12499         /* Sony Vaio Y cannot use SSC on LVDS */
12500         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12501
12502         /* Acer Aspire 5734Z must invert backlight brightness */
12503         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12504
12505         /* Acer/eMachines G725 */
12506         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12507
12508         /* Acer/eMachines e725 */
12509         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12510
12511         /* Acer/Packard Bell NCL20 */
12512         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12513
12514         /* Acer Aspire 4736Z */
12515         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12516
12517         /* Acer Aspire 5336 */
12518         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12519
12520         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12521         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12522
12523         /* Acer C720 Chromebook (Core i3 4005U) */
12524         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12525
12526         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12527         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12528
12529         /* HP Chromebook 14 (Celeron 2955U) */
12530         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12531 };
12532
12533 static void intel_init_quirks(struct drm_device *dev)
12534 {
12535         struct pci_dev *d = dev->pdev;
12536         int i;
12537
12538         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12539                 struct intel_quirk *q = &intel_quirks[i];
12540
12541                 if (d->device == q->device &&
12542                     (d->subsystem_vendor == q->subsystem_vendor ||
12543                      q->subsystem_vendor == PCI_ANY_ID) &&
12544                     (d->subsystem_device == q->subsystem_device ||
12545                      q->subsystem_device == PCI_ANY_ID))
12546                         q->hook(dev);
12547         }
12548         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12549                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12550                         intel_dmi_quirks[i].hook(dev);
12551         }
12552 }
12553
12554 /* Disable the VGA plane that we never use */
12555 static void i915_disable_vga(struct drm_device *dev)
12556 {
12557         struct drm_i915_private *dev_priv = dev->dev_private;
12558         u8 sr1;
12559         u32 vga_reg = i915_vgacntrl_reg(dev);
12560
12561         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12562         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12563         outb(SR01, VGA_SR_INDEX);
12564         sr1 = inb(VGA_SR_DATA);
12565         outb(sr1 | 1<<5, VGA_SR_DATA);
12566         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12567         udelay(300);
12568
12569         /*
12570          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12571          * from S3 without preserving (some of?) the other bits.
12572          */
12573         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12574         POSTING_READ(vga_reg);
12575 }
12576
12577 void intel_modeset_init_hw(struct drm_device *dev)
12578 {
12579         intel_prepare_ddi(dev);
12580
12581         if (IS_VALLEYVIEW(dev))
12582                 vlv_update_cdclk(dev);
12583
12584         intel_init_clock_gating(dev);
12585
12586         intel_enable_gt_powersave(dev);
12587 }
12588
12589 void intel_modeset_init(struct drm_device *dev)
12590 {
12591         struct drm_i915_private *dev_priv = dev->dev_private;
12592         int sprite, ret;
12593         enum pipe pipe;
12594         struct intel_crtc *crtc;
12595
12596         drm_mode_config_init(dev);
12597
12598         dev->mode_config.min_width = 0;
12599         dev->mode_config.min_height = 0;
12600
12601         dev->mode_config.preferred_depth = 24;
12602         dev->mode_config.prefer_shadow = 1;
12603
12604         dev->mode_config.funcs = &intel_mode_funcs;
12605
12606         intel_init_quirks(dev);
12607
12608         intel_init_pm(dev);
12609
12610         if (INTEL_INFO(dev)->num_pipes == 0)
12611                 return;
12612
12613         intel_init_display(dev);
12614         intel_init_audio(dev);
12615
12616         if (IS_GEN2(dev)) {
12617                 dev->mode_config.max_width = 2048;
12618                 dev->mode_config.max_height = 2048;
12619         } else if (IS_GEN3(dev)) {
12620                 dev->mode_config.max_width = 4096;
12621                 dev->mode_config.max_height = 4096;
12622         } else {
12623                 dev->mode_config.max_width = 8192;
12624                 dev->mode_config.max_height = 8192;
12625         }
12626
12627         if (IS_845G(dev) || IS_I865G(dev)) {
12628                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12629                 dev->mode_config.cursor_height = 1023;
12630         } else if (IS_GEN2(dev)) {
12631                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12632                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12633         } else {
12634                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12635                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12636         }
12637
12638         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12639
12640         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12641                       INTEL_INFO(dev)->num_pipes,
12642                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12643
12644         for_each_pipe(dev_priv, pipe) {
12645                 intel_crtc_init(dev, pipe);
12646                 for_each_sprite(pipe, sprite) {
12647                         ret = intel_plane_init(dev, pipe, sprite);
12648                         if (ret)
12649                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12650                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12651                 }
12652         }
12653
12654         intel_init_dpio(dev);
12655
12656         intel_shared_dpll_init(dev);
12657
12658         /* save the BIOS value before clobbering it */
12659         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12660         /* Just disable it once at startup */
12661         i915_disable_vga(dev);
12662         intel_setup_outputs(dev);
12663
12664         /* Just in case the BIOS is doing something questionable. */
12665         intel_disable_fbc(dev);
12666
12667         drm_modeset_lock_all(dev);
12668         intel_modeset_setup_hw_state(dev, false);
12669         drm_modeset_unlock_all(dev);
12670
12671         for_each_intel_crtc(dev, crtc) {
12672                 if (!crtc->active)
12673                         continue;
12674
12675                 /*
12676                  * Note that reserving the BIOS fb up front prevents us
12677                  * from stuffing other stolen allocations like the ring
12678                  * on top.  This prevents some ugliness at boot time, and
12679                  * can even allow for smooth boot transitions if the BIOS
12680                  * fb is large enough for the active pipe configuration.
12681                  */
12682                 if (dev_priv->display.get_plane_config) {
12683                         dev_priv->display.get_plane_config(crtc,
12684                                                            &crtc->plane_config);
12685                         /*
12686                          * If the fb is shared between multiple heads, we'll
12687                          * just get the first one.
12688                          */
12689                         intel_find_plane_obj(crtc, &crtc->plane_config);
12690                 }
12691         }
12692 }
12693
12694 static void intel_enable_pipe_a(struct drm_device *dev)
12695 {
12696         struct intel_connector *connector;
12697         struct drm_connector *crt = NULL;
12698         struct intel_load_detect_pipe load_detect_temp;
12699         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12700
12701         /* We can't just switch on the pipe A, we need to set things up with a
12702          * proper mode and output configuration. As a gross hack, enable pipe A
12703          * by enabling the load detect pipe once. */
12704         list_for_each_entry(connector,
12705                             &dev->mode_config.connector_list,
12706                             base.head) {
12707                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12708                         crt = &connector->base;
12709                         break;
12710                 }
12711         }
12712
12713         if (!crt)
12714                 return;
12715
12716         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12717                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12718 }
12719
12720 static bool
12721 intel_check_plane_mapping(struct intel_crtc *crtc)
12722 {
12723         struct drm_device *dev = crtc->base.dev;
12724         struct drm_i915_private *dev_priv = dev->dev_private;
12725         u32 reg, val;
12726
12727         if (INTEL_INFO(dev)->num_pipes == 1)
12728                 return true;
12729
12730         reg = DSPCNTR(!crtc->plane);
12731         val = I915_READ(reg);
12732
12733         if ((val & DISPLAY_PLANE_ENABLE) &&
12734             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12735                 return false;
12736
12737         return true;
12738 }
12739
12740 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12741 {
12742         struct drm_device *dev = crtc->base.dev;
12743         struct drm_i915_private *dev_priv = dev->dev_private;
12744         u32 reg;
12745
12746         /* Clear any frame start delays used for debugging left by the BIOS */
12747         reg = PIPECONF(crtc->config.cpu_transcoder);
12748         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12749
12750         /* restore vblank interrupts to correct state */
12751         if (crtc->active) {
12752                 update_scanline_offset(crtc);
12753                 drm_vblank_on(dev, crtc->pipe);
12754         } else
12755                 drm_vblank_off(dev, crtc->pipe);
12756
12757         /* We need to sanitize the plane -> pipe mapping first because this will
12758          * disable the crtc (and hence change the state) if it is wrong. Note
12759          * that gen4+ has a fixed plane -> pipe mapping.  */
12760         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12761                 struct intel_connector *connector;
12762                 bool plane;
12763
12764                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12765                               crtc->base.base.id);
12766
12767                 /* Pipe has the wrong plane attached and the plane is active.
12768                  * Temporarily change the plane mapping and disable everything
12769                  * ...  */
12770                 plane = crtc->plane;
12771                 crtc->plane = !plane;
12772                 crtc->primary_enabled = true;
12773                 dev_priv->display.crtc_disable(&crtc->base);
12774                 crtc->plane = plane;
12775
12776                 /* ... and break all links. */
12777                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12778                                     base.head) {
12779                         if (connector->encoder->base.crtc != &crtc->base)
12780                                 continue;
12781
12782                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12783                         connector->base.encoder = NULL;
12784                 }
12785                 /* multiple connectors may have the same encoder:
12786                  *  handle them and break crtc link separately */
12787                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12788                                     base.head)
12789                         if (connector->encoder->base.crtc == &crtc->base) {
12790                                 connector->encoder->base.crtc = NULL;
12791                                 connector->encoder->connectors_active = false;
12792                         }
12793
12794                 WARN_ON(crtc->active);
12795                 crtc->base.enabled = false;
12796         }
12797
12798         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12799             crtc->pipe == PIPE_A && !crtc->active) {
12800                 /* BIOS forgot to enable pipe A, this mostly happens after
12801                  * resume. Force-enable the pipe to fix this, the update_dpms
12802                  * call below we restore the pipe to the right state, but leave
12803                  * the required bits on. */
12804                 intel_enable_pipe_a(dev);
12805         }
12806
12807         /* Adjust the state of the output pipe according to whether we
12808          * have active connectors/encoders. */
12809         intel_crtc_update_dpms(&crtc->base);
12810
12811         if (crtc->active != crtc->base.enabled) {
12812                 struct intel_encoder *encoder;
12813
12814                 /* This can happen either due to bugs in the get_hw_state
12815                  * functions or because the pipe is force-enabled due to the
12816                  * pipe A quirk. */
12817                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12818                               crtc->base.base.id,
12819                               crtc->base.enabled ? "enabled" : "disabled",
12820                               crtc->active ? "enabled" : "disabled");
12821
12822                 crtc->base.enabled = crtc->active;
12823
12824                 /* Because we only establish the connector -> encoder ->
12825                  * crtc links if something is active, this means the
12826                  * crtc is now deactivated. Break the links. connector
12827                  * -> encoder links are only establish when things are
12828                  *  actually up, hence no need to break them. */
12829                 WARN_ON(crtc->active);
12830
12831                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12832                         WARN_ON(encoder->connectors_active);
12833                         encoder->base.crtc = NULL;
12834                 }
12835         }
12836
12837         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
12838                 /*
12839                  * We start out with underrun reporting disabled to avoid races.
12840                  * For correct bookkeeping mark this on active crtcs.
12841                  *
12842                  * Also on gmch platforms we dont have any hardware bits to
12843                  * disable the underrun reporting. Which means we need to start
12844                  * out with underrun reporting disabled also on inactive pipes,
12845                  * since otherwise we'll complain about the garbage we read when
12846                  * e.g. coming up after runtime pm.
12847                  *
12848                  * No protection against concurrent access is required - at
12849                  * worst a fifo underrun happens which also sets this to false.
12850                  */
12851                 crtc->cpu_fifo_underrun_disabled = true;
12852                 crtc->pch_fifo_underrun_disabled = true;
12853         }
12854 }
12855
12856 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12857 {
12858         struct intel_connector *connector;
12859         struct drm_device *dev = encoder->base.dev;
12860
12861         /* We need to check both for a crtc link (meaning that the
12862          * encoder is active and trying to read from a pipe) and the
12863          * pipe itself being active. */
12864         bool has_active_crtc = encoder->base.crtc &&
12865                 to_intel_crtc(encoder->base.crtc)->active;
12866
12867         if (encoder->connectors_active && !has_active_crtc) {
12868                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12869                               encoder->base.base.id,
12870                               encoder->base.name);
12871
12872                 /* Connector is active, but has no active pipe. This is
12873                  * fallout from our resume register restoring. Disable
12874                  * the encoder manually again. */
12875                 if (encoder->base.crtc) {
12876                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12877                                       encoder->base.base.id,
12878                                       encoder->base.name);
12879                         encoder->disable(encoder);
12880                         if (encoder->post_disable)
12881                                 encoder->post_disable(encoder);
12882                 }
12883                 encoder->base.crtc = NULL;
12884                 encoder->connectors_active = false;
12885
12886                 /* Inconsistent output/port/pipe state happens presumably due to
12887                  * a bug in one of the get_hw_state functions. Or someplace else
12888                  * in our code, like the register restore mess on resume. Clamp
12889                  * things to off as a safer default. */
12890                 list_for_each_entry(connector,
12891                                     &dev->mode_config.connector_list,
12892                                     base.head) {
12893                         if (connector->encoder != encoder)
12894                                 continue;
12895                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12896                         connector->base.encoder = NULL;
12897                 }
12898         }
12899         /* Enabled encoders without active connectors will be fixed in
12900          * the crtc fixup. */
12901 }
12902
12903 void i915_redisable_vga_power_on(struct drm_device *dev)
12904 {
12905         struct drm_i915_private *dev_priv = dev->dev_private;
12906         u32 vga_reg = i915_vgacntrl_reg(dev);
12907
12908         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12909                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12910                 i915_disable_vga(dev);
12911         }
12912 }
12913
12914 void i915_redisable_vga(struct drm_device *dev)
12915 {
12916         struct drm_i915_private *dev_priv = dev->dev_private;
12917
12918         /* This function can be called both from intel_modeset_setup_hw_state or
12919          * at a very early point in our resume sequence, where the power well
12920          * structures are not yet restored. Since this function is at a very
12921          * paranoid "someone might have enabled VGA while we were not looking"
12922          * level, just check if the power well is enabled instead of trying to
12923          * follow the "don't touch the power well if we don't need it" policy
12924          * the rest of the driver uses. */
12925         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
12926                 return;
12927
12928         i915_redisable_vga_power_on(dev);
12929 }
12930
12931 static bool primary_get_hw_state(struct intel_crtc *crtc)
12932 {
12933         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12934
12935         if (!crtc->active)
12936                 return false;
12937
12938         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12939 }
12940
12941 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12942 {
12943         struct drm_i915_private *dev_priv = dev->dev_private;
12944         enum pipe pipe;
12945         struct intel_crtc *crtc;
12946         struct intel_encoder *encoder;
12947         struct intel_connector *connector;
12948         int i;
12949
12950         for_each_intel_crtc(dev, crtc) {
12951                 memset(&crtc->config, 0, sizeof(crtc->config));
12952
12953                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12954
12955                 crtc->active = dev_priv->display.get_pipe_config(crtc,
12956                                                                  &crtc->config);
12957
12958                 crtc->base.enabled = crtc->active;
12959                 crtc->primary_enabled = primary_get_hw_state(crtc);
12960
12961                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12962                               crtc->base.base.id,
12963                               crtc->active ? "enabled" : "disabled");
12964         }
12965
12966         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12967                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12968
12969                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12970                 pll->active = 0;
12971                 for_each_intel_crtc(dev, crtc) {
12972                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12973                                 pll->active++;
12974                 }
12975                 pll->refcount = pll->active;
12976
12977                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12978                               pll->name, pll->refcount, pll->on);
12979
12980                 if (pll->refcount)
12981                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12982         }
12983
12984         for_each_intel_encoder(dev, encoder) {
12985                 pipe = 0;
12986
12987                 if (encoder->get_hw_state(encoder, &pipe)) {
12988                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12989                         encoder->base.crtc = &crtc->base;
12990                         encoder->get_config(encoder, &crtc->config);
12991                 } else {
12992                         encoder->base.crtc = NULL;
12993                 }
12994
12995                 encoder->connectors_active = false;
12996                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12997                               encoder->base.base.id,
12998                               encoder->base.name,
12999                               encoder->base.crtc ? "enabled" : "disabled",
13000                               pipe_name(pipe));
13001         }
13002
13003         list_for_each_entry(connector, &dev->mode_config.connector_list,
13004                             base.head) {
13005                 if (connector->get_hw_state(connector)) {
13006                         connector->base.dpms = DRM_MODE_DPMS_ON;
13007                         connector->encoder->connectors_active = true;
13008                         connector->base.encoder = &connector->encoder->base;
13009                 } else {
13010                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13011                         connector->base.encoder = NULL;
13012                 }
13013                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13014                               connector->base.base.id,
13015                               connector->base.name,
13016                               connector->base.encoder ? "enabled" : "disabled");
13017         }
13018 }
13019
13020 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13021  * and i915 state tracking structures. */
13022 void intel_modeset_setup_hw_state(struct drm_device *dev,
13023                                   bool force_restore)
13024 {
13025         struct drm_i915_private *dev_priv = dev->dev_private;
13026         enum pipe pipe;
13027         struct intel_crtc *crtc;
13028         struct intel_encoder *encoder;
13029         int i;
13030
13031         intel_modeset_readout_hw_state(dev);
13032
13033         /*
13034          * Now that we have the config, copy it to each CRTC struct
13035          * Note that this could go away if we move to using crtc_config
13036          * checking everywhere.
13037          */
13038         for_each_intel_crtc(dev, crtc) {
13039                 if (crtc->active && i915.fastboot) {
13040                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13041                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13042                                       crtc->base.base.id);
13043                         drm_mode_debug_printmodeline(&crtc->base.mode);
13044                 }
13045         }
13046
13047         /* HW state is read out, now we need to sanitize this mess. */
13048         for_each_intel_encoder(dev, encoder) {
13049                 intel_sanitize_encoder(encoder);
13050         }
13051
13052         for_each_pipe(dev_priv, pipe) {
13053                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13054                 intel_sanitize_crtc(crtc);
13055                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13056         }
13057
13058         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13059                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13060
13061                 if (!pll->on || pll->active)
13062                         continue;
13063
13064                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13065
13066                 pll->disable(dev_priv, pll);
13067                 pll->on = false;
13068         }
13069
13070         if (HAS_PCH_SPLIT(dev))
13071                 ilk_wm_get_hw_state(dev);
13072
13073         if (force_restore) {
13074                 i915_redisable_vga(dev);
13075
13076                 /*
13077                  * We need to use raw interfaces for restoring state to avoid
13078                  * checking (bogus) intermediate states.
13079                  */
13080                 for_each_pipe(dev_priv, pipe) {
13081                         struct drm_crtc *crtc =
13082                                 dev_priv->pipe_to_crtc_mapping[pipe];
13083
13084                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13085                                          crtc->primary->fb);
13086                 }
13087         } else {
13088                 intel_modeset_update_staged_output_state(dev);
13089         }
13090
13091         intel_modeset_check_state(dev);
13092 }
13093
13094 void intel_modeset_gem_init(struct drm_device *dev)
13095 {
13096         struct drm_crtc *c;
13097         struct drm_i915_gem_object *obj;
13098
13099         mutex_lock(&dev->struct_mutex);
13100         intel_init_gt_powersave(dev);
13101         mutex_unlock(&dev->struct_mutex);
13102
13103         intel_modeset_init_hw(dev);
13104
13105         intel_setup_overlay(dev);
13106
13107         /*
13108          * Make sure any fbs we allocated at startup are properly
13109          * pinned & fenced.  When we do the allocation it's too early
13110          * for this.
13111          */
13112         mutex_lock(&dev->struct_mutex);
13113         for_each_crtc(dev, c) {
13114                 obj = intel_fb_obj(c->primary->fb);
13115                 if (obj == NULL)
13116                         continue;
13117
13118                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13119                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13120                                   to_intel_crtc(c)->pipe);
13121                         drm_framebuffer_unreference(c->primary->fb);
13122                         c->primary->fb = NULL;
13123                 }
13124         }
13125         mutex_unlock(&dev->struct_mutex);
13126 }
13127
13128 void intel_connector_unregister(struct intel_connector *intel_connector)
13129 {
13130         struct drm_connector *connector = &intel_connector->base;
13131
13132         intel_panel_destroy_backlight(connector);
13133         drm_connector_unregister(connector);
13134 }
13135
13136 void intel_modeset_cleanup(struct drm_device *dev)
13137 {
13138         struct drm_i915_private *dev_priv = dev->dev_private;
13139         struct drm_connector *connector;
13140
13141         /*
13142          * Interrupts and polling as the first thing to avoid creating havoc.
13143          * Too much stuff here (turning of rps, connectors, ...) would
13144          * experience fancy races otherwise.
13145          */
13146         intel_irq_uninstall(dev_priv);
13147
13148         /*
13149          * Due to the hpd irq storm handling the hotplug work can re-arm the
13150          * poll handlers. Hence disable polling after hpd handling is shut down.
13151          */
13152         drm_kms_helper_poll_fini(dev);
13153
13154         mutex_lock(&dev->struct_mutex);
13155
13156         intel_unregister_dsm_handler();
13157
13158         intel_disable_fbc(dev);
13159
13160         intel_disable_gt_powersave(dev);
13161
13162         ironlake_teardown_rc6(dev);
13163
13164         mutex_unlock(&dev->struct_mutex);
13165
13166         /* flush any delayed tasks or pending work */
13167         flush_scheduled_work();
13168
13169         /* destroy the backlight and sysfs files before encoders/connectors */
13170         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13171                 struct intel_connector *intel_connector;
13172
13173                 intel_connector = to_intel_connector(connector);
13174                 intel_connector->unregister(intel_connector);
13175         }
13176
13177         drm_mode_config_cleanup(dev);
13178
13179         intel_cleanup_overlay(dev);
13180
13181         mutex_lock(&dev->struct_mutex);
13182         intel_cleanup_gt_powersave(dev);
13183         mutex_unlock(&dev->struct_mutex);
13184 }
13185
13186 /*
13187  * Return which encoder is currently attached for connector.
13188  */
13189 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13190 {
13191         return &intel_attached_encoder(connector)->base;
13192 }
13193
13194 void intel_connector_attach_encoder(struct intel_connector *connector,
13195                                     struct intel_encoder *encoder)
13196 {
13197         connector->encoder = encoder;
13198         drm_mode_connector_attach_encoder(&connector->base,
13199                                           &encoder->base);
13200 }
13201
13202 /*
13203  * set vga decode state - true == enable VGA decode
13204  */
13205 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13206 {
13207         struct drm_i915_private *dev_priv = dev->dev_private;
13208         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13209         u16 gmch_ctrl;
13210
13211         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13212                 DRM_ERROR("failed to read control word\n");
13213                 return -EIO;
13214         }
13215
13216         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13217                 return 0;
13218
13219         if (state)
13220                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13221         else
13222                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13223
13224         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13225                 DRM_ERROR("failed to write control word\n");
13226                 return -EIO;
13227         }
13228
13229         return 0;
13230 }
13231
13232 struct intel_display_error_state {
13233
13234         u32 power_well_driver;
13235
13236         int num_transcoders;
13237
13238         struct intel_cursor_error_state {
13239                 u32 control;
13240                 u32 position;
13241                 u32 base;
13242                 u32 size;
13243         } cursor[I915_MAX_PIPES];
13244
13245         struct intel_pipe_error_state {
13246                 bool power_domain_on;
13247                 u32 source;
13248                 u32 stat;
13249         } pipe[I915_MAX_PIPES];
13250
13251         struct intel_plane_error_state {
13252                 u32 control;
13253                 u32 stride;
13254                 u32 size;
13255                 u32 pos;
13256                 u32 addr;
13257                 u32 surface;
13258                 u32 tile_offset;
13259         } plane[I915_MAX_PIPES];
13260
13261         struct intel_transcoder_error_state {
13262                 bool power_domain_on;
13263                 enum transcoder cpu_transcoder;
13264
13265                 u32 conf;
13266
13267                 u32 htotal;
13268                 u32 hblank;
13269                 u32 hsync;
13270                 u32 vtotal;
13271                 u32 vblank;
13272                 u32 vsync;
13273         } transcoder[4];
13274 };
13275
13276 struct intel_display_error_state *
13277 intel_display_capture_error_state(struct drm_device *dev)
13278 {
13279         struct drm_i915_private *dev_priv = dev->dev_private;
13280         struct intel_display_error_state *error;
13281         int transcoders[] = {
13282                 TRANSCODER_A,
13283                 TRANSCODER_B,
13284                 TRANSCODER_C,
13285                 TRANSCODER_EDP,
13286         };
13287         int i;
13288
13289         if (INTEL_INFO(dev)->num_pipes == 0)
13290                 return NULL;
13291
13292         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13293         if (error == NULL)
13294                 return NULL;
13295
13296         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13297                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13298
13299         for_each_pipe(dev_priv, i) {
13300                 error->pipe[i].power_domain_on =
13301                         __intel_display_power_is_enabled(dev_priv,
13302                                                          POWER_DOMAIN_PIPE(i));
13303                 if (!error->pipe[i].power_domain_on)
13304                         continue;
13305
13306                 error->cursor[i].control = I915_READ(CURCNTR(i));
13307                 error->cursor[i].position = I915_READ(CURPOS(i));
13308                 error->cursor[i].base = I915_READ(CURBASE(i));
13309
13310                 error->plane[i].control = I915_READ(DSPCNTR(i));
13311                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13312                 if (INTEL_INFO(dev)->gen <= 3) {
13313                         error->plane[i].size = I915_READ(DSPSIZE(i));
13314                         error->plane[i].pos = I915_READ(DSPPOS(i));
13315                 }
13316                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13317                         error->plane[i].addr = I915_READ(DSPADDR(i));
13318                 if (INTEL_INFO(dev)->gen >= 4) {
13319                         error->plane[i].surface = I915_READ(DSPSURF(i));
13320                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13321                 }
13322
13323                 error->pipe[i].source = I915_READ(PIPESRC(i));
13324
13325                 if (HAS_GMCH_DISPLAY(dev))
13326                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13327         }
13328
13329         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13330         if (HAS_DDI(dev_priv->dev))
13331                 error->num_transcoders++; /* Account for eDP. */
13332
13333         for (i = 0; i < error->num_transcoders; i++) {
13334                 enum transcoder cpu_transcoder = transcoders[i];
13335
13336                 error->transcoder[i].power_domain_on =
13337                         __intel_display_power_is_enabled(dev_priv,
13338                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13339                 if (!error->transcoder[i].power_domain_on)
13340                         continue;
13341
13342                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13343
13344                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13345                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13346                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13347                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13348                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13349                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13350                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13351         }
13352
13353         return error;
13354 }
13355
13356 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13357
13358 void
13359 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13360                                 struct drm_device *dev,
13361                                 struct intel_display_error_state *error)
13362 {
13363         struct drm_i915_private *dev_priv = dev->dev_private;
13364         int i;
13365
13366         if (!error)
13367                 return;
13368
13369         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13370         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13371                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13372                            error->power_well_driver);
13373         for_each_pipe(dev_priv, i) {
13374                 err_printf(m, "Pipe [%d]:\n", i);
13375                 err_printf(m, "  Power: %s\n",
13376                            error->pipe[i].power_domain_on ? "on" : "off");
13377                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13378                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13379
13380                 err_printf(m, "Plane [%d]:\n", i);
13381                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13382                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13383                 if (INTEL_INFO(dev)->gen <= 3) {
13384                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13385                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13386                 }
13387                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13388                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13389                 if (INTEL_INFO(dev)->gen >= 4) {
13390                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13391                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13392                 }
13393
13394                 err_printf(m, "Cursor [%d]:\n", i);
13395                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13396                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13397                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13398         }
13399
13400         for (i = 0; i < error->num_transcoders; i++) {
13401                 err_printf(m, "CPU transcoder: %c\n",
13402                            transcoder_name(error->transcoder[i].cpu_transcoder));
13403                 err_printf(m, "  Power: %s\n",
13404                            error->transcoder[i].power_domain_on ? "on" : "off");
13405                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13406                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13407                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13408                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13409                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13410                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13411                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13412         }
13413 }
13414
13415 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13416 {
13417         struct intel_crtc *crtc;
13418
13419         for_each_intel_crtc(dev, crtc) {
13420                 struct intel_unpin_work *work;
13421
13422                 spin_lock_irq(&dev->event_lock);
13423
13424                 work = crtc->unpin_work;
13425
13426                 if (work && work->event &&
13427                     work->event->base.file_priv == file) {
13428                         kfree(work->event);
13429                         work->event = NULL;
13430                 }
13431
13432                 spin_unlock_irq(&dev->event_lock);
13433         }
13434 }