drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct drm_crtc *crtc;
2772
2773         /*
2774          * Flips in the rings have been nuked by the reset,
2775          * so complete all pending flips so that user space
2776          * will get its events and not get stuck.
2777          *
2778          * Also update the base address of all primary
2779          * planes to the the last fb to make sure we're
2780          * showing the correct fb after a reset.
2781          *
2782          * Need to make two loops over the crtcs so that we
2783          * don't try to grab a crtc mutex before the
2784          * pending_flip_queue really got woken up.
2785          */
2786
2787         for_each_crtc(dev, crtc) {
2788                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789                 enum plane plane = intel_crtc->plane;
2790
2791                 intel_prepare_page_flip(dev, plane);
2792                 intel_finish_page_flip_plane(dev, plane);
2793         }
2794
2795         for_each_crtc(dev, crtc) {
2796                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798                 drm_modeset_lock(&crtc->mutex, NULL);
2799                 /*
2800                  * FIXME: Once we have proper support for primary planes (and
2801                  * disabling them without disabling the entire crtc) allow again
2802                  * a NULL crtc->primary->fb.
2803                  */
2804                 if (intel_crtc->active && crtc->primary->fb)
2805                         dev_priv->display.update_primary_plane(crtc,
2806                                                                crtc->primary->fb,
2807                                                                crtc->x,
2808                                                                crtc->y);
2809                 drm_modeset_unlock(&crtc->mutex);
2810         }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818         bool was_interruptible = dev_priv->mm.interruptible;
2819         int ret;
2820
2821         /* Big Hammer, we also need to ensure that any pending
2822          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823          * current scanout is retired before unpinning the old
2824          * framebuffer.
2825          *
2826          * This should only fail upon a hung GPU, in which case we
2827          * can safely continue.
2828          */
2829         dev_priv->mm.interruptible = false;
2830         ret = i915_gem_object_finish_gpu(obj);
2831         dev_priv->mm.interruptible = was_interruptible;
2832
2833         return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841         bool pending;
2842
2843         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845                 return false;
2846
2847         spin_lock_irq(&dev->event_lock);
2848         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849         spin_unlock_irq(&dev->event_lock);
2850
2851         return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->base.dev;
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         const struct drm_display_mode *adjusted_mode;
2859
2860         if (!i915.fastboot)
2861                 return;
2862
2863         /*
2864          * Update pipe size and adjust fitter if needed: the reason for this is
2865          * that in compute_mode_changes we check the native mode (not the pfit
2866          * mode) to see if we can flip rather than do a full mode set. In the
2867          * fastboot case, we'll flip, but if we don't update the pipesrc and
2868          * pfit state, we'll end up with a big fb scanned out into the wrong
2869          * sized surface.
2870          *
2871          * To fix this properly, we need to hoist the checks up into
2872          * compute_mode_changes (or above), check the actual pfit state and
2873          * whether the platform allows pfit disable with pipe active, and only
2874          * then update the pipesrc and pfit state, even on the flip path.
2875          */
2876
2877         adjusted_mode = &crtc->config.adjusted_mode;
2878
2879         I915_WRITE(PIPESRC(crtc->pipe),
2880                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881                    (adjusted_mode->crtc_vdisplay - 1));
2882         if (!crtc->config.pch_pfit.enabled &&
2883             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888         }
2889         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895                     struct drm_framebuffer *fb)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900         enum pipe pipe = intel_crtc->pipe;
2901         struct drm_framebuffer *old_fb = crtc->primary->fb;
2902         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903         int ret;
2904
2905         if (intel_crtc_has_pending_flip(crtc)) {
2906                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907                 return -EBUSY;
2908         }
2909
2910         /* no fb bound */
2911         if (!fb) {
2912                 DRM_ERROR("No FB bound\n");
2913                 return 0;
2914         }
2915
2916         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918                           plane_name(intel_crtc->plane),
2919                           INTEL_INFO(dev)->num_pipes);
2920                 return -EINVAL;
2921         }
2922
2923         mutex_lock(&dev->struct_mutex);
2924         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925         if (ret == 0)
2926                 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2928         mutex_unlock(&dev->struct_mutex);
2929         if (ret != 0) {
2930                 DRM_ERROR("pin & fence failed\n");
2931                 return ret;
2932         }
2933
2934         intel_update_pipe_size(intel_crtc);
2935
2936         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2937
2938         if (intel_crtc->active)
2939                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940
2941         crtc->primary->fb = fb;
2942         crtc->x = x;
2943         crtc->y = y;
2944
2945         if (old_fb) {
2946                 if (intel_crtc->active && old_fb != fb)
2947                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2948                 mutex_lock(&dev->struct_mutex);
2949                 intel_unpin_fb_obj(old_obj);
2950                 mutex_unlock(&dev->struct_mutex);
2951         }
2952
2953         mutex_lock(&dev->struct_mutex);
2954         intel_update_fbc(dev);
2955         mutex_unlock(&dev->struct_mutex);
2956
2957         return 0;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965         int pipe = intel_crtc->pipe;
2966         u32 reg, temp;
2967
2968         /* enable normal train */
2969         reg = FDI_TX_CTL(pipe);
2970         temp = I915_READ(reg);
2971         if (IS_IVYBRIDGE(dev)) {
2972                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974         } else {
2975                 temp &= ~FDI_LINK_TRAIN_NONE;
2976                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977         }
2978         I915_WRITE(reg, temp);
2979
2980         reg = FDI_RX_CTL(pipe);
2981         temp = I915_READ(reg);
2982         if (HAS_PCH_CPT(dev)) {
2983                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985         } else {
2986                 temp &= ~FDI_LINK_TRAIN_NONE;
2987                 temp |= FDI_LINK_TRAIN_NONE;
2988         }
2989         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991         /* wait one idle pattern time */
2992         POSTING_READ(reg);
2993         udelay(1000);
2994
2995         /* IVB wants error correction enabled */
2996         if (IS_IVYBRIDGE(dev))
2997                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998                            FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003         return crtc->base.enabled && crtc->active &&
3004                 crtc->config.has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010         struct intel_crtc *pipe_B_crtc =
3011                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012         struct intel_crtc *pipe_C_crtc =
3013                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014         uint32_t temp;
3015
3016         /*
3017          * When everything is off disable fdi C so that we could enable fdi B
3018          * with all lanes. Note that we don't care about enabled pipes without
3019          * an enabled pch encoder.
3020          */
3021         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022             !pipe_has_enabled_pch(pipe_C_crtc)) {
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026                 temp = I915_READ(SOUTH_CHICKEN1);
3027                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029                 I915_WRITE(SOUTH_CHICKEN1, temp);
3030         }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036         struct drm_device *dev = crtc->dev;
3037         struct drm_i915_private *dev_priv = dev->dev_private;
3038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039         int pipe = intel_crtc->pipe;
3040         u32 reg, temp, tries;
3041
3042         /* FDI needs bits from pipe first */
3043         assert_pipe_enabled(dev_priv, pipe);
3044
3045         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046            for train result */
3047         reg = FDI_RX_IMR(pipe);
3048         temp = I915_READ(reg);
3049         temp &= ~FDI_RX_SYMBOL_LOCK;
3050         temp &= ~FDI_RX_BIT_LOCK;
3051         I915_WRITE(reg, temp);
3052         I915_READ(reg);
3053         udelay(150);
3054
3055         /* enable CPU FDI TX and PCH FDI RX */
3056         reg = FDI_TX_CTL(pipe);
3057         temp = I915_READ(reg);
3058         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3060         temp &= ~FDI_LINK_TRAIN_NONE;
3061         temp |= FDI_LINK_TRAIN_PATTERN_1;
3062         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064         reg = FDI_RX_CTL(pipe);
3065         temp = I915_READ(reg);
3066         temp &= ~FDI_LINK_TRAIN_NONE;
3067         temp |= FDI_LINK_TRAIN_PATTERN_1;
3068         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070         POSTING_READ(reg);
3071         udelay(150);
3072
3073         /* Ironlake workaround, enable clock pointer after FDI enable*/
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076                    FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078         reg = FDI_RX_IIR(pipe);
3079         for (tries = 0; tries < 5; tries++) {
3080                 temp = I915_READ(reg);
3081                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083                 if ((temp & FDI_RX_BIT_LOCK)) {
3084                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3085                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086                         break;
3087                 }
3088         }
3089         if (tries == 5)
3090                 DRM_ERROR("FDI train 1 fail!\n");
3091
3092         /* Train 2 */
3093         reg = FDI_TX_CTL(pipe);
3094         temp = I915_READ(reg);
3095         temp &= ~FDI_LINK_TRAIN_NONE;
3096         temp |= FDI_LINK_TRAIN_PATTERN_2;
3097         I915_WRITE(reg, temp);
3098
3099         reg = FDI_RX_CTL(pipe);
3100         temp = I915_READ(reg);
3101         temp &= ~FDI_LINK_TRAIN_NONE;
3102         temp |= FDI_LINK_TRAIN_PATTERN_2;
3103         I915_WRITE(reg, temp);
3104
3105         POSTING_READ(reg);
3106         udelay(150);
3107
3108         reg = FDI_RX_IIR(pipe);
3109         for (tries = 0; tries < 5; tries++) {
3110                 temp = I915_READ(reg);
3111                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113                 if (temp & FDI_RX_SYMBOL_LOCK) {
3114                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3116                         break;
3117                 }
3118         }
3119         if (tries == 5)
3120                 DRM_ERROR("FDI train 2 fail!\n");
3121
3122         DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136         struct drm_device *dev = crtc->dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139         int pipe = intel_crtc->pipe;
3140         u32 reg, temp, i, retry;
3141
3142         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143            for train result */
3144         reg = FDI_RX_IMR(pipe);
3145         temp = I915_READ(reg);
3146         temp &= ~FDI_RX_SYMBOL_LOCK;
3147         temp &= ~FDI_RX_BIT_LOCK;
3148         I915_WRITE(reg, temp);
3149
3150         POSTING_READ(reg);
3151         udelay(150);
3152
3153         /* enable CPU FDI TX and PCH FDI RX */
3154         reg = FDI_TX_CTL(pipe);
3155         temp = I915_READ(reg);
3156         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3158         temp &= ~FDI_LINK_TRAIN_NONE;
3159         temp |= FDI_LINK_TRAIN_PATTERN_1;
3160         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161         /* SNB-B */
3162         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165         I915_WRITE(FDI_RX_MISC(pipe),
3166                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168         reg = FDI_RX_CTL(pipe);
3169         temp = I915_READ(reg);
3170         if (HAS_PCH_CPT(dev)) {
3171                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173         } else {
3174                 temp &= ~FDI_LINK_TRAIN_NONE;
3175                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176         }
3177         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179         POSTING_READ(reg);
3180         udelay(150);
3181
3182         for (i = 0; i < 4; i++) {
3183                 reg = FDI_TX_CTL(pipe);
3184                 temp = I915_READ(reg);
3185                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186                 temp |= snb_b_fdi_train_param[i];
3187                 I915_WRITE(reg, temp);
3188
3189                 POSTING_READ(reg);
3190                 udelay(500);
3191
3192                 for (retry = 0; retry < 5; retry++) {
3193                         reg = FDI_RX_IIR(pipe);
3194                         temp = I915_READ(reg);
3195                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196                         if (temp & FDI_RX_BIT_LOCK) {
3197                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199                                 break;
3200                         }
3201                         udelay(50);
3202                 }
3203                 if (retry < 5)
3204                         break;
3205         }
3206         if (i == 4)
3207                 DRM_ERROR("FDI train 1 fail!\n");
3208
3209         /* Train 2 */
3210         reg = FDI_TX_CTL(pipe);
3211         temp = I915_READ(reg);
3212         temp &= ~FDI_LINK_TRAIN_NONE;
3213         temp |= FDI_LINK_TRAIN_PATTERN_2;
3214         if (IS_GEN6(dev)) {
3215                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216                 /* SNB-B */
3217                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218         }
3219         I915_WRITE(reg, temp);
3220
3221         reg = FDI_RX_CTL(pipe);
3222         temp = I915_READ(reg);
3223         if (HAS_PCH_CPT(dev)) {
3224                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226         } else {
3227                 temp &= ~FDI_LINK_TRAIN_NONE;
3228                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229         }
3230         I915_WRITE(reg, temp);
3231
3232         POSTING_READ(reg);
3233         udelay(150);
3234
3235         for (i = 0; i < 4; i++) {
3236                 reg = FDI_TX_CTL(pipe);
3237                 temp = I915_READ(reg);
3238                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239                 temp |= snb_b_fdi_train_param[i];
3240                 I915_WRITE(reg, temp);
3241
3242                 POSTING_READ(reg);
3243                 udelay(500);
3244
3245                 for (retry = 0; retry < 5; retry++) {
3246                         reg = FDI_RX_IIR(pipe);
3247                         temp = I915_READ(reg);
3248                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249                         if (temp & FDI_RX_SYMBOL_LOCK) {
3250                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252                                 break;
3253                         }
3254                         udelay(50);
3255                 }
3256                 if (retry < 5)
3257                         break;
3258         }
3259         if (i == 4)
3260                 DRM_ERROR("FDI train 2 fail!\n");
3261
3262         DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268         struct drm_device *dev = crtc->dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271         int pipe = intel_crtc->pipe;
3272         u32 reg, temp, i, j;
3273
3274         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275            for train result */
3276         reg = FDI_RX_IMR(pipe);
3277         temp = I915_READ(reg);
3278         temp &= ~FDI_RX_SYMBOL_LOCK;
3279         temp &= ~FDI_RX_BIT_LOCK;
3280         I915_WRITE(reg, temp);
3281
3282         POSTING_READ(reg);
3283         udelay(150);
3284
3285         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286                       I915_READ(FDI_RX_IIR(pipe)));
3287
3288         /* Try each vswing and preemphasis setting twice before moving on */
3289         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290                 /* disable first in case we need to retry */
3291                 reg = FDI_TX_CTL(pipe);
3292                 temp = I915_READ(reg);
3293                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294                 temp &= ~FDI_TX_ENABLE;
3295                 I915_WRITE(reg, temp);
3296
3297                 reg = FDI_RX_CTL(pipe);
3298                 temp = I915_READ(reg);
3299                 temp &= ~FDI_LINK_TRAIN_AUTO;
3300                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301                 temp &= ~FDI_RX_ENABLE;
3302                 I915_WRITE(reg, temp);
3303
3304                 /* enable CPU FDI TX and PCH FDI RX */
3305                 reg = FDI_TX_CTL(pipe);
3306                 temp = I915_READ(reg);
3307                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3309                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311                 temp |= snb_b_fdi_train_param[j/2];
3312                 temp |= FDI_COMPOSITE_SYNC;
3313                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315                 I915_WRITE(FDI_RX_MISC(pipe),
3316                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318                 reg = FDI_RX_CTL(pipe);
3319                 temp = I915_READ(reg);
3320                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321                 temp |= FDI_COMPOSITE_SYNC;
3322                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324                 POSTING_READ(reg);
3325                 udelay(1); /* should be 0.5us */
3326
3327                 for (i = 0; i < 4; i++) {
3328                         reg = FDI_RX_IIR(pipe);
3329                         temp = I915_READ(reg);
3330                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332                         if (temp & FDI_RX_BIT_LOCK ||
3333                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336                                               i);
3337                                 break;
3338                         }
3339                         udelay(1); /* should be 0.5us */
3340                 }
3341                 if (i == 4) {
3342                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343                         continue;
3344                 }
3345
3346                 /* Train 2 */
3347                 reg = FDI_TX_CTL(pipe);
3348                 temp = I915_READ(reg);
3349                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351                 I915_WRITE(reg, temp);
3352
3353                 reg = FDI_RX_CTL(pipe);
3354                 temp = I915_READ(reg);
3355                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357                 I915_WRITE(reg, temp);
3358
3359                 POSTING_READ(reg);
3360                 udelay(2); /* should be 1.5us */
3361
3362                 for (i = 0; i < 4; i++) {
3363                         reg = FDI_RX_IIR(pipe);
3364                         temp = I915_READ(reg);
3365                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367                         if (temp & FDI_RX_SYMBOL_LOCK ||
3368                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371                                               i);
3372                                 goto train_done;
3373                         }
3374                         udelay(2); /* should be 1.5us */
3375                 }
3376                 if (i == 4)
3377                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378         }
3379
3380 train_done:
3381         DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386         struct drm_device *dev = intel_crtc->base.dev;
3387         struct drm_i915_private *dev_priv = dev->dev_private;
3388         int pipe = intel_crtc->pipe;
3389         u32 reg, temp;
3390
3391
3392         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393         reg = FDI_RX_CTL(pipe);
3394         temp = I915_READ(reg);
3395         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3397         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400         POSTING_READ(reg);
3401         udelay(200);
3402
3403         /* Switch from Rawclk to PCDclk */
3404         temp = I915_READ(reg);
3405         I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407         POSTING_READ(reg);
3408         udelay(200);
3409
3410         /* Enable CPU FDI TX PLL, always on for Ironlake */
3411         reg = FDI_TX_CTL(pipe);
3412         temp = I915_READ(reg);
3413         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416                 POSTING_READ(reg);
3417                 udelay(100);
3418         }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423         struct drm_device *dev = intel_crtc->base.dev;
3424         struct drm_i915_private *dev_priv = dev->dev_private;
3425         int pipe = intel_crtc->pipe;
3426         u32 reg, temp;
3427
3428         /* Switch from PCDclk to Rawclk */
3429         reg = FDI_RX_CTL(pipe);
3430         temp = I915_READ(reg);
3431         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433         /* Disable CPU FDI TX PLL */
3434         reg = FDI_TX_CTL(pipe);
3435         temp = I915_READ(reg);
3436         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438         POSTING_READ(reg);
3439         udelay(100);
3440
3441         reg = FDI_RX_CTL(pipe);
3442         temp = I915_READ(reg);
3443         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445         /* Wait for the clocks to turn off. */
3446         POSTING_READ(reg);
3447         udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452         struct drm_device *dev = crtc->dev;
3453         struct drm_i915_private *dev_priv = dev->dev_private;
3454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455         int pipe = intel_crtc->pipe;
3456         u32 reg, temp;
3457
3458         /* disable CPU FDI tx and PCH FDI rx */
3459         reg = FDI_TX_CTL(pipe);
3460         temp = I915_READ(reg);
3461         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462         POSTING_READ(reg);
3463
3464         reg = FDI_RX_CTL(pipe);
3465         temp = I915_READ(reg);
3466         temp &= ~(0x7 << 16);
3467         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470         POSTING_READ(reg);
3471         udelay(100);
3472
3473         /* Ironlake workaround, disable clock pointer after downing FDI */
3474         if (HAS_PCH_IBX(dev))
3475                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477         /* still set train pattern 1 */
3478         reg = FDI_TX_CTL(pipe);
3479         temp = I915_READ(reg);
3480         temp &= ~FDI_LINK_TRAIN_NONE;
3481         temp |= FDI_LINK_TRAIN_PATTERN_1;
3482         I915_WRITE(reg, temp);
3483
3484         reg = FDI_RX_CTL(pipe);
3485         temp = I915_READ(reg);
3486         if (HAS_PCH_CPT(dev)) {
3487                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489         } else {
3490                 temp &= ~FDI_LINK_TRAIN_NONE;
3491                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492         }
3493         /* BPC in FDI rx is consistent with that in PIPECONF */
3494         temp &= ~(0x07 << 16);
3495         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496         I915_WRITE(reg, temp);
3497
3498         POSTING_READ(reg);
3499         udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504         struct intel_crtc *crtc;
3505
3506         /* Note that we don't need to be called with mode_config.lock here
3507          * as our list of CRTC objects is static for the lifetime of the
3508          * device and so cannot disappear as we iterate. Similarly, we can
3509          * happily treat the predicates as racy, atomic checks as userspace
3510          * cannot claim and pin a new fb without at least acquring the
3511          * struct_mutex and so serialising with us.
3512          */
3513         for_each_intel_crtc(dev, crtc) {
3514                 if (atomic_read(&crtc->unpin_work_count) == 0)
3515                         continue;
3516
3517                 if (crtc->unpin_work)
3518                         intel_wait_for_vblank(dev, crtc->pipe);
3519
3520                 return true;
3521         }
3522
3523         return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529         struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531         /* ensure that the unpin work is consistent wrt ->pending. */
3532         smp_rmb();
3533         intel_crtc->unpin_work = NULL;
3534
3535         if (work->event)
3536                 drm_send_vblank_event(intel_crtc->base.dev,
3537                                       intel_crtc->pipe,
3538                                       work->event);
3539
3540         drm_crtc_vblank_put(&intel_crtc->base);
3541
3542         wake_up_all(&dev_priv->pending_flip_queue);
3543         queue_work(dev_priv->wq, &work->work);
3544
3545         trace_i915_flip_complete(intel_crtc->plane,
3546                                  work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->dev;
3552         struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556                                        !intel_crtc_has_pending_flip(crtc),
3557                                        60*HZ) == 0)) {
3558                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560                 spin_lock_irq(&dev->event_lock);
3561                 if (intel_crtc->unpin_work) {
3562                         WARN_ONCE(1, "Removing stuck page flip\n");
3563                         page_flip_completed(intel_crtc);
3564                 }
3565                 spin_unlock_irq(&dev->event_lock);
3566         }
3567
3568         if (crtc->primary->fb) {
3569                 mutex_lock(&dev->struct_mutex);
3570                 intel_finish_fb(crtc->primary->fb);
3571                 mutex_unlock(&dev->struct_mutex);
3572         }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578         struct drm_device *dev = crtc->dev;
3579         struct drm_i915_private *dev_priv = dev->dev_private;
3580         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3581         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582         u32 temp;
3583
3584         mutex_lock(&dev_priv->dpio_lock);
3585
3586         /* It is necessary to ungate the pixclk gate prior to programming
3587          * the divisors, and gate it back when it is done.
3588          */
3589         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591         /* Disable SSCCTL */
3592         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594                                 SBI_SSCCTL_DISABLE,
3595                         SBI_ICLK);
3596
3597         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598         if (clock == 20000) {
3599                 auxdiv = 1;
3600                 divsel = 0x41;
3601                 phaseinc = 0x20;
3602         } else {
3603                 /* The iCLK virtual clock root frequency is in MHz,
3604                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3605                  * divisors, it is necessary to divide one by another, so we
3606                  * convert the virtual clock precision to KHz here for higher
3607                  * precision.
3608                  */
3609                 u32 iclk_virtual_root_freq = 172800 * 1000;
3610                 u32 iclk_pi_range = 64;
3611                 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613                 desired_divisor = (iclk_virtual_root_freq / clock);
3614                 msb_divisor_value = desired_divisor / iclk_pi_range;
3615                 pi_value = desired_divisor % iclk_pi_range;
3616
3617                 auxdiv = 0;
3618                 divsel = msb_divisor_value - 2;
3619                 phaseinc = pi_value;
3620         }
3621
3622         /* This should not happen with any sane values */
3623         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629                         clock,
3630                         auxdiv,
3631                         divsel,
3632                         phasedir,
3633                         phaseinc);
3634
3635         /* Program SSCDIVINTPHASE6 */
3636         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645         /* Program SSCAUXDIV */
3646         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651         /* Enable modulator and associated divider */
3652         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653         temp &= ~SBI_SSCCTL_DISABLE;
3654         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656         /* Wait for initialization time */
3657         udelay(24);
3658
3659         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661         mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665                                                 enum pipe pch_transcoder)
3666 {
3667         struct drm_device *dev = crtc->base.dev;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670
3671         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672                    I915_READ(HTOTAL(cpu_transcoder)));
3673         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674                    I915_READ(HBLANK(cpu_transcoder)));
3675         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676                    I915_READ(HSYNC(cpu_transcoder)));
3677
3678         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679                    I915_READ(VTOTAL(cpu_transcoder)));
3680         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681                    I915_READ(VBLANK(cpu_transcoder)));
3682         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683                    I915_READ(VSYNC(cpu_transcoder)));
3684         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690         struct drm_i915_private *dev_priv = dev->dev_private;
3691         uint32_t temp;
3692
3693         temp = I915_READ(SOUTH_CHICKEN1);
3694         if (temp & FDI_BC_BIFURCATION_SELECT)
3695                 return;
3696
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700         temp |= FDI_BC_BIFURCATION_SELECT;
3701         DRM_DEBUG_KMS("enabling fdi C rx\n");
3702         I915_WRITE(SOUTH_CHICKEN1, temp);
3703         POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708         struct drm_device *dev = intel_crtc->base.dev;
3709         struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711         switch (intel_crtc->pipe) {
3712         case PIPE_A:
3713                 break;
3714         case PIPE_B:
3715                 if (intel_crtc->config.fdi_lanes > 2)
3716                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717                 else
3718                         cpt_enable_fdi_bc_bifurcation(dev);
3719
3720                 break;
3721         case PIPE_C:
3722                 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724                 break;
3725         default:
3726                 BUG();
3727         }
3728 }
3729
3730 /*
3731  * Enable PCH resources required for PCH ports:
3732  *   - PCH PLLs
3733  *   - FDI training & RX/TX
3734  *   - update transcoder timings
3735  *   - DP transcoding bits
3736  *   - transcoder
3737  */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740         struct drm_device *dev = crtc->dev;
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743         int pipe = intel_crtc->pipe;
3744         u32 reg, temp;
3745
3746         assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748         if (IS_IVYBRIDGE(dev))
3749                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751         /* Write the TU size bits before fdi link training, so that error
3752          * detection works. */
3753         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756         /* For PCH output, training FDI link */
3757         dev_priv->display.fdi_link_train(crtc);
3758
3759         /* We need to program the right clock selection before writing the pixel
3760          * mutliplier into the DPLL. */
3761         if (HAS_PCH_CPT(dev)) {
3762                 u32 sel;
3763
3764                 temp = I915_READ(PCH_DPLL_SEL);
3765                 temp |= TRANS_DPLL_ENABLE(pipe);
3766                 sel = TRANS_DPLLB_SEL(pipe);
3767                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3768                         temp |= sel;
3769                 else
3770                         temp &= ~sel;
3771                 I915_WRITE(PCH_DPLL_SEL, temp);
3772         }
3773
3774         /* XXX: pch pll's can be enabled any time before we enable the PCH
3775          * transcoder, and we actually should do this to not upset any PCH
3776          * transcoder that already use the clock when we share it.
3777          *
3778          * Note that enable_shared_dpll tries to do the right thing, but
3779          * get_shared_dpll unconditionally resets the pll - we need that to have
3780          * the right LVDS enable sequence. */
3781         intel_enable_shared_dpll(intel_crtc);
3782
3783         /* set transcoder timing, panel must allow it */
3784         assert_panel_unlocked(dev_priv, pipe);
3785         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787         intel_fdi_normal_train(crtc);
3788
3789         /* For PCH DP, enable TRANS_DP_CTL */
3790         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3791                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792                 reg = TRANS_DP_CTL(pipe);
3793                 temp = I915_READ(reg);
3794                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795                           TRANS_DP_SYNC_MASK |
3796                           TRANS_DP_BPC_MASK);
3797                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798                          TRANS_DP_ENH_FRAMING);
3799                 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806                 switch (intel_trans_dp_port_sel(crtc)) {
3807                 case PCH_DP_B:
3808                         temp |= TRANS_DP_PORT_SEL_B;
3809                         break;
3810                 case PCH_DP_C:
3811                         temp |= TRANS_DP_PORT_SEL_C;
3812                         break;
3813                 case PCH_DP_D:
3814                         temp |= TRANS_DP_PORT_SEL_D;
3815                         break;
3816                 default:
3817                         BUG();
3818                 }
3819
3820                 I915_WRITE(reg, temp);
3821         }
3822
3823         ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828         struct drm_device *dev = crtc->dev;
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3832
3833         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835         lpt_program_iclkip(crtc);
3836
3837         /* Set transcoder timing. */
3838         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847         if (pll == NULL)
3848                 return;
3849
3850         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851                 WARN(1, "bad %s crtc mask\n", pll->name);
3852                 return;
3853         }
3854
3855         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856         if (pll->config.crtc_mask == 0) {
3857                 WARN_ON(pll->on);
3858                 WARN_ON(pll->active);
3859         }
3860
3861         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3865 {
3866         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3867         struct intel_shared_dpll *pll;
3868         enum intel_dpll_id i;
3869
3870         if (HAS_PCH_IBX(dev_priv->dev)) {
3871                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872                 i = (enum intel_dpll_id) crtc->pipe;
3873                 pll = &dev_priv->shared_dplls[i];
3874
3875                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876                               crtc->base.base.id, pll->name);
3877
3878                 WARN_ON(pll->new_config->crtc_mask);
3879
3880                 goto found;
3881         }
3882
3883         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884                 pll = &dev_priv->shared_dplls[i];
3885
3886                 /* Only want to check enabled timings first */
3887                 if (pll->new_config->crtc_mask == 0)
3888                         continue;
3889
3890                 if (memcmp(&crtc->new_config->dpll_hw_state,
3891                            &pll->new_config->hw_state,
3892                            sizeof(pll->new_config->hw_state)) == 0) {
3893                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894                                       crtc->base.base.id, pll->name,
3895                                       pll->new_config->crtc_mask,
3896                                       pll->active);
3897                         goto found;
3898                 }
3899         }
3900
3901         /* Ok no matching timings, maybe there's a free one? */
3902         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3903                 pll = &dev_priv->shared_dplls[i];
3904                 if (pll->new_config->crtc_mask == 0) {
3905                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906                                       crtc->base.base.id, pll->name);
3907                         goto found;
3908                 }
3909         }
3910
3911         return NULL;
3912
3913 found:
3914         if (pll->new_config->crtc_mask == 0)
3915                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3916
3917         crtc->new_config->shared_dpll = i;
3918         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919                          pipe_name(crtc->pipe));
3920
3921         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3922
3923         return pll;
3924 }
3925
3926 /**
3927  * intel_shared_dpll_start_config - start a new PLL staged config
3928  * @dev_priv: DRM device
3929  * @clear_pipes: mask of pipes that will have their PLLs freed
3930  *
3931  * Starts a new PLL staged config, copying the current config but
3932  * releasing the references of pipes specified in clear_pipes.
3933  */
3934 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3935                                           unsigned clear_pipes)
3936 {
3937         struct intel_shared_dpll *pll;
3938         enum intel_dpll_id i;
3939
3940         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3941                 pll = &dev_priv->shared_dplls[i];
3942
3943                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944                                           GFP_KERNEL);
3945                 if (!pll->new_config)
3946                         goto cleanup;
3947
3948                 pll->new_config->crtc_mask &= ~clear_pipes;
3949         }
3950
3951         return 0;
3952
3953 cleanup:
3954         while (--i >= 0) {
3955                 pll = &dev_priv->shared_dplls[i];
3956                 pll->new_config = NULL;
3957         }
3958
3959         return -ENOMEM;
3960 }
3961
3962 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3963 {
3964         struct intel_shared_dpll *pll;
3965         enum intel_dpll_id i;
3966
3967         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3968                 pll = &dev_priv->shared_dplls[i];
3969
3970                 WARN_ON(pll->new_config == &pll->config);
3971
3972                 pll->config = *pll->new_config;
3973                 kfree(pll->new_config);
3974                 pll->new_config = NULL;
3975         }
3976 }
3977
3978 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3979 {
3980         struct intel_shared_dpll *pll;
3981         enum intel_dpll_id i;
3982
3983         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3984                 pll = &dev_priv->shared_dplls[i];
3985
3986                 WARN_ON(pll->new_config == &pll->config);
3987
3988                 kfree(pll->new_config);
3989                 pll->new_config = NULL;
3990         }
3991 }
3992
3993 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3994 {
3995         struct drm_i915_private *dev_priv = dev->dev_private;
3996         int dslreg = PIPEDSL(pipe);
3997         u32 temp;
3998
3999         temp = I915_READ(dslreg);
4000         udelay(500);
4001         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4002                 if (wait_for(I915_READ(dslreg) != temp, 5))
4003                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4004         }
4005 }
4006
4007 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4008 {
4009         struct drm_device *dev = crtc->base.dev;
4010         struct drm_i915_private *dev_priv = dev->dev_private;
4011         int pipe = crtc->pipe;
4012
4013         if (crtc->config.pch_pfit.enabled) {
4014                 /* Force use of hard-coded filter coefficients
4015                  * as some pre-programmed values are broken,
4016                  * e.g. x201.
4017                  */
4018                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4019                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4020                                                  PF_PIPE_SEL_IVB(pipe));
4021                 else
4022                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4023                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4024                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4025         }
4026 }
4027
4028 static void intel_enable_planes(struct drm_crtc *crtc)
4029 {
4030         struct drm_device *dev = crtc->dev;
4031         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4032         struct drm_plane *plane;
4033         struct intel_plane *intel_plane;
4034
4035         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4036                 intel_plane = to_intel_plane(plane);
4037                 if (intel_plane->pipe == pipe)
4038                         intel_plane_restore(&intel_plane->base);
4039         }
4040 }
4041
4042 static void intel_disable_planes(struct drm_crtc *crtc)
4043 {
4044         struct drm_device *dev = crtc->dev;
4045         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4046         struct drm_plane *plane;
4047         struct intel_plane *intel_plane;
4048
4049         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4050                 intel_plane = to_intel_plane(plane);
4051                 if (intel_plane->pipe == pipe)
4052                         intel_plane_disable(&intel_plane->base);
4053         }
4054 }
4055
4056 void hsw_enable_ips(struct intel_crtc *crtc)
4057 {
4058         struct drm_device *dev = crtc->base.dev;
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060
4061         if (!crtc->config.ips_enabled)
4062                 return;
4063
4064         /* We can only enable IPS after we enable a plane and wait for a vblank */
4065         intel_wait_for_vblank(dev, crtc->pipe);
4066
4067         assert_plane_enabled(dev_priv, crtc->plane);
4068         if (IS_BROADWELL(dev)) {
4069                 mutex_lock(&dev_priv->rps.hw_lock);
4070                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4071                 mutex_unlock(&dev_priv->rps.hw_lock);
4072                 /* Quoting Art Runyan: "its not safe to expect any particular
4073                  * value in IPS_CTL bit 31 after enabling IPS through the
4074                  * mailbox." Moreover, the mailbox may return a bogus state,
4075                  * so we need to just enable it and continue on.
4076                  */
4077         } else {
4078                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4079                 /* The bit only becomes 1 in the next vblank, so this wait here
4080                  * is essentially intel_wait_for_vblank. If we don't have this
4081                  * and don't wait for vblanks until the end of crtc_enable, then
4082                  * the HW state readout code will complain that the expected
4083                  * IPS_CTL value is not the one we read. */
4084                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4085                         DRM_ERROR("Timed out waiting for IPS enable\n");
4086         }
4087 }
4088
4089 void hsw_disable_ips(struct intel_crtc *crtc)
4090 {
4091         struct drm_device *dev = crtc->base.dev;
4092         struct drm_i915_private *dev_priv = dev->dev_private;
4093
4094         if (!crtc->config.ips_enabled)
4095                 return;
4096
4097         assert_plane_enabled(dev_priv, crtc->plane);
4098         if (IS_BROADWELL(dev)) {
4099                 mutex_lock(&dev_priv->rps.hw_lock);
4100                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4101                 mutex_unlock(&dev_priv->rps.hw_lock);
4102                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4103                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4104                         DRM_ERROR("Timed out waiting for IPS disable\n");
4105         } else {
4106                 I915_WRITE(IPS_CTL, 0);
4107                 POSTING_READ(IPS_CTL);
4108         }
4109
4110         /* We need to wait for a vblank before we can disable the plane. */
4111         intel_wait_for_vblank(dev, crtc->pipe);
4112 }
4113
4114 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4115 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4116 {
4117         struct drm_device *dev = crtc->dev;
4118         struct drm_i915_private *dev_priv = dev->dev_private;
4119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4120         enum pipe pipe = intel_crtc->pipe;
4121         int palreg = PALETTE(pipe);
4122         int i;
4123         bool reenable_ips = false;
4124
4125         /* The clocks have to be on to load the palette. */
4126         if (!crtc->enabled || !intel_crtc->active)
4127                 return;
4128
4129         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4130                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4131                         assert_dsi_pll_enabled(dev_priv);
4132                 else
4133                         assert_pll_enabled(dev_priv, pipe);
4134         }
4135
4136         /* use legacy palette for Ironlake */
4137         if (!HAS_GMCH_DISPLAY(dev))
4138                 palreg = LGC_PALETTE(pipe);
4139
4140         /* Workaround : Do not read or write the pipe palette/gamma data while
4141          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4142          */
4143         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4144             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4145              GAMMA_MODE_MODE_SPLIT)) {
4146                 hsw_disable_ips(intel_crtc);
4147                 reenable_ips = true;
4148         }
4149
4150         for (i = 0; i < 256; i++) {
4151                 I915_WRITE(palreg + 4 * i,
4152                            (intel_crtc->lut_r[i] << 16) |
4153                            (intel_crtc->lut_g[i] << 8) |
4154                            intel_crtc->lut_b[i]);
4155         }
4156
4157         if (reenable_ips)
4158                 hsw_enable_ips(intel_crtc);
4159 }
4160
4161 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4162 {
4163         if (!enable && intel_crtc->overlay) {
4164                 struct drm_device *dev = intel_crtc->base.dev;
4165                 struct drm_i915_private *dev_priv = dev->dev_private;
4166
4167                 mutex_lock(&dev->struct_mutex);
4168                 dev_priv->mm.interruptible = false;
4169                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4170                 dev_priv->mm.interruptible = true;
4171                 mutex_unlock(&dev->struct_mutex);
4172         }
4173
4174         /* Let userspace switch the overlay on again. In most cases userspace
4175          * has to recompute where to put it anyway.
4176          */
4177 }
4178
4179 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4180 {
4181         struct drm_device *dev = crtc->dev;
4182         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183         int pipe = intel_crtc->pipe;
4184
4185         intel_enable_primary_hw_plane(crtc->primary, crtc);
4186         intel_enable_planes(crtc);
4187         intel_crtc_update_cursor(crtc, true);
4188         intel_crtc_dpms_overlay(intel_crtc, true);
4189
4190         hsw_enable_ips(intel_crtc);
4191
4192         mutex_lock(&dev->struct_mutex);
4193         intel_update_fbc(dev);
4194         mutex_unlock(&dev->struct_mutex);
4195
4196         /*
4197          * FIXME: Once we grow proper nuclear flip support out of this we need
4198          * to compute the mask of flip planes precisely. For the time being
4199          * consider this a flip from a NULL plane.
4200          */
4201         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4202 }
4203
4204 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209         int pipe = intel_crtc->pipe;
4210         int plane = intel_crtc->plane;
4211
4212         intel_crtc_wait_for_pending_flips(crtc);
4213
4214         if (dev_priv->fbc.plane == plane)
4215                 intel_disable_fbc(dev);
4216
4217         hsw_disable_ips(intel_crtc);
4218
4219         intel_crtc_dpms_overlay(intel_crtc, false);
4220         intel_crtc_update_cursor(crtc, false);
4221         intel_disable_planes(crtc);
4222         intel_disable_primary_hw_plane(crtc->primary, crtc);
4223
4224         /*
4225          * FIXME: Once we grow proper nuclear flip support out of this we need
4226          * to compute the mask of flip planes precisely. For the time being
4227          * consider this a flip to a NULL plane.
4228          */
4229         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4230 }
4231
4232 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4233 {
4234         struct drm_device *dev = crtc->dev;
4235         struct drm_i915_private *dev_priv = dev->dev_private;
4236         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4237         struct intel_encoder *encoder;
4238         int pipe = intel_crtc->pipe;
4239
4240         WARN_ON(!crtc->enabled);
4241
4242         if (intel_crtc->active)
4243                 return;
4244
4245         if (intel_crtc->config.has_pch_encoder)
4246                 intel_prepare_shared_dpll(intel_crtc);
4247
4248         if (intel_crtc->config.has_dp_encoder)
4249                 intel_dp_set_m_n(intel_crtc);
4250
4251         intel_set_pipe_timings(intel_crtc);
4252
4253         if (intel_crtc->config.has_pch_encoder) {
4254                 intel_cpu_transcoder_set_m_n(intel_crtc,
4255                                      &intel_crtc->config.fdi_m_n, NULL);
4256         }
4257
4258         ironlake_set_pipeconf(crtc);
4259
4260         intel_crtc->active = true;
4261
4262         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4263         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4264
4265         for_each_encoder_on_crtc(dev, crtc, encoder)
4266                 if (encoder->pre_enable)
4267                         encoder->pre_enable(encoder);
4268
4269         if (intel_crtc->config.has_pch_encoder) {
4270                 /* Note: FDI PLL enabling _must_ be done before we enable the
4271                  * cpu pipes, hence this is separate from all the other fdi/pch
4272                  * enabling. */
4273                 ironlake_fdi_pll_enable(intel_crtc);
4274         } else {
4275                 assert_fdi_tx_disabled(dev_priv, pipe);
4276                 assert_fdi_rx_disabled(dev_priv, pipe);
4277         }
4278
4279         ironlake_pfit_enable(intel_crtc);
4280
4281         /*
4282          * On ILK+ LUT must be loaded before the pipe is running but with
4283          * clocks enabled
4284          */
4285         intel_crtc_load_lut(crtc);
4286
4287         intel_update_watermarks(crtc);
4288         intel_enable_pipe(intel_crtc);
4289
4290         if (intel_crtc->config.has_pch_encoder)
4291                 ironlake_pch_enable(crtc);
4292
4293         for_each_encoder_on_crtc(dev, crtc, encoder)
4294                 encoder->enable(encoder);
4295
4296         if (HAS_PCH_CPT(dev))
4297                 cpt_verify_modeset(dev, intel_crtc->pipe);
4298
4299         assert_vblank_disabled(crtc);
4300         drm_crtc_vblank_on(crtc);
4301
4302         intel_crtc_enable_planes(crtc);
4303 }
4304
4305 /* IPS only exists on ULT machines and is tied to pipe A. */
4306 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4307 {
4308         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4309 }
4310
4311 /*
4312  * This implements the workaround described in the "notes" section of the mode
4313  * set sequence documentation. When going from no pipes or single pipe to
4314  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4315  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4316  */
4317 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4318 {
4319         struct drm_device *dev = crtc->base.dev;
4320         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4321
4322         /* We want to get the other_active_crtc only if there's only 1 other
4323          * active crtc. */
4324         for_each_intel_crtc(dev, crtc_it) {
4325                 if (!crtc_it->active || crtc_it == crtc)
4326                         continue;
4327
4328                 if (other_active_crtc)
4329                         return;
4330
4331                 other_active_crtc = crtc_it;
4332         }
4333         if (!other_active_crtc)
4334                 return;
4335
4336         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4338 }
4339
4340 static void haswell_crtc_enable(struct drm_crtc *crtc)
4341 {
4342         struct drm_device *dev = crtc->dev;
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4345         struct intel_encoder *encoder;
4346         int pipe = intel_crtc->pipe;
4347
4348         WARN_ON(!crtc->enabled);
4349
4350         if (intel_crtc->active)
4351                 return;
4352
4353         if (intel_crtc_to_shared_dpll(intel_crtc))
4354                 intel_enable_shared_dpll(intel_crtc);
4355
4356         if (intel_crtc->config.has_dp_encoder)
4357                 intel_dp_set_m_n(intel_crtc);
4358
4359         intel_set_pipe_timings(intel_crtc);
4360
4361         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4362                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4363                            intel_crtc->config.pixel_multiplier - 1);
4364         }
4365
4366         if (intel_crtc->config.has_pch_encoder) {
4367                 intel_cpu_transcoder_set_m_n(intel_crtc,
4368                                      &intel_crtc->config.fdi_m_n, NULL);
4369         }
4370
4371         haswell_set_pipeconf(crtc);
4372
4373         intel_set_pipe_csc(crtc);
4374
4375         intel_crtc->active = true;
4376
4377         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4378         for_each_encoder_on_crtc(dev, crtc, encoder)
4379                 if (encoder->pre_enable)
4380                         encoder->pre_enable(encoder);
4381
4382         if (intel_crtc->config.has_pch_encoder) {
4383                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4384                                                       true);
4385                 dev_priv->display.fdi_link_train(crtc);
4386         }
4387
4388         intel_ddi_enable_pipe_clock(intel_crtc);
4389
4390         ironlake_pfit_enable(intel_crtc);
4391
4392         /*
4393          * On ILK+ LUT must be loaded before the pipe is running but with
4394          * clocks enabled
4395          */
4396         intel_crtc_load_lut(crtc);
4397
4398         intel_ddi_set_pipe_settings(crtc);
4399         intel_ddi_enable_transcoder_func(crtc);
4400
4401         intel_update_watermarks(crtc);
4402         intel_enable_pipe(intel_crtc);
4403
4404         if (intel_crtc->config.has_pch_encoder)
4405                 lpt_pch_enable(crtc);
4406
4407         if (intel_crtc->config.dp_encoder_is_mst)
4408                 intel_ddi_set_vc_payload_alloc(crtc, true);
4409
4410         for_each_encoder_on_crtc(dev, crtc, encoder) {
4411                 encoder->enable(encoder);
4412                 intel_opregion_notify_encoder(encoder, true);
4413         }
4414
4415         assert_vblank_disabled(crtc);
4416         drm_crtc_vblank_on(crtc);
4417
4418         /* If we change the relative order between pipe/planes enabling, we need
4419          * to change the workaround. */
4420         haswell_mode_set_planes_workaround(intel_crtc);
4421         intel_crtc_enable_planes(crtc);
4422 }
4423
4424 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4425 {
4426         struct drm_device *dev = crtc->base.dev;
4427         struct drm_i915_private *dev_priv = dev->dev_private;
4428         int pipe = crtc->pipe;
4429
4430         /* To avoid upsetting the power well on haswell only disable the pfit if
4431          * it's in use. The hw state code will make sure we get this right. */
4432         if (crtc->config.pch_pfit.enabled) {
4433                 I915_WRITE(PF_CTL(pipe), 0);
4434                 I915_WRITE(PF_WIN_POS(pipe), 0);
4435                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4436         }
4437 }
4438
4439 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4440 {
4441         struct drm_device *dev = crtc->dev;
4442         struct drm_i915_private *dev_priv = dev->dev_private;
4443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4444         struct intel_encoder *encoder;
4445         int pipe = intel_crtc->pipe;
4446         u32 reg, temp;
4447
4448         if (!intel_crtc->active)
4449                 return;
4450
4451         intel_crtc_disable_planes(crtc);
4452
4453         drm_crtc_vblank_off(crtc);
4454         assert_vblank_disabled(crtc);
4455
4456         for_each_encoder_on_crtc(dev, crtc, encoder)
4457                 encoder->disable(encoder);
4458
4459         if (intel_crtc->config.has_pch_encoder)
4460                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4461
4462         intel_disable_pipe(intel_crtc);
4463
4464         ironlake_pfit_disable(intel_crtc);
4465
4466         for_each_encoder_on_crtc(dev, crtc, encoder)
4467                 if (encoder->post_disable)
4468                         encoder->post_disable(encoder);
4469
4470         if (intel_crtc->config.has_pch_encoder) {
4471                 ironlake_fdi_disable(crtc);
4472
4473                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4474                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4475
4476                 if (HAS_PCH_CPT(dev)) {
4477                         /* disable TRANS_DP_CTL */
4478                         reg = TRANS_DP_CTL(pipe);
4479                         temp = I915_READ(reg);
4480                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4481                                   TRANS_DP_PORT_SEL_MASK);
4482                         temp |= TRANS_DP_PORT_SEL_NONE;
4483                         I915_WRITE(reg, temp);
4484
4485                         /* disable DPLL_SEL */
4486                         temp = I915_READ(PCH_DPLL_SEL);
4487                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4488                         I915_WRITE(PCH_DPLL_SEL, temp);
4489                 }
4490
4491                 /* disable PCH DPLL */
4492                 intel_disable_shared_dpll(intel_crtc);
4493
4494                 ironlake_fdi_pll_disable(intel_crtc);
4495         }
4496
4497         intel_crtc->active = false;
4498         intel_update_watermarks(crtc);
4499
4500         mutex_lock(&dev->struct_mutex);
4501         intel_update_fbc(dev);
4502         mutex_unlock(&dev->struct_mutex);
4503 }
4504
4505 static void haswell_crtc_disable(struct drm_crtc *crtc)
4506 {
4507         struct drm_device *dev = crtc->dev;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4510         struct intel_encoder *encoder;
4511         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4512
4513         if (!intel_crtc->active)
4514                 return;
4515
4516         intel_crtc_disable_planes(crtc);
4517
4518         drm_crtc_vblank_off(crtc);
4519         assert_vblank_disabled(crtc);
4520
4521         for_each_encoder_on_crtc(dev, crtc, encoder) {
4522                 intel_opregion_notify_encoder(encoder, false);
4523                 encoder->disable(encoder);
4524         }
4525
4526         if (intel_crtc->config.has_pch_encoder)
4527                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4528                                                       false);
4529         intel_disable_pipe(intel_crtc);
4530
4531         if (intel_crtc->config.dp_encoder_is_mst)
4532                 intel_ddi_set_vc_payload_alloc(crtc, false);
4533
4534         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4535
4536         ironlake_pfit_disable(intel_crtc);
4537
4538         intel_ddi_disable_pipe_clock(intel_crtc);
4539
4540         if (intel_crtc->config.has_pch_encoder) {
4541                 lpt_disable_pch_transcoder(dev_priv);
4542                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4543                                                       true);
4544                 intel_ddi_fdi_disable(crtc);
4545         }
4546
4547         for_each_encoder_on_crtc(dev, crtc, encoder)
4548                 if (encoder->post_disable)
4549                         encoder->post_disable(encoder);
4550
4551         intel_crtc->active = false;
4552         intel_update_watermarks(crtc);
4553
4554         mutex_lock(&dev->struct_mutex);
4555         intel_update_fbc(dev);
4556         mutex_unlock(&dev->struct_mutex);
4557
4558         if (intel_crtc_to_shared_dpll(intel_crtc))
4559                 intel_disable_shared_dpll(intel_crtc);
4560 }
4561
4562 static void ironlake_crtc_off(struct drm_crtc *crtc)
4563 {
4564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565         intel_put_shared_dpll(intel_crtc);
4566 }
4567
4568
4569 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4570 {
4571         struct drm_device *dev = crtc->base.dev;
4572         struct drm_i915_private *dev_priv = dev->dev_private;
4573         struct intel_crtc_config *pipe_config = &crtc->config;
4574
4575         if (!crtc->config.gmch_pfit.control)
4576                 return;
4577
4578         /*
4579          * The panel fitter should only be adjusted whilst the pipe is disabled,
4580          * according to register description and PRM.
4581          */
4582         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4583         assert_pipe_disabled(dev_priv, crtc->pipe);
4584
4585         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4586         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4587
4588         /* Border color in case we don't scale up to the full screen. Black by
4589          * default, change to something else for debugging. */
4590         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4591 }
4592
4593 static enum intel_display_power_domain port_to_power_domain(enum port port)
4594 {
4595         switch (port) {
4596         case PORT_A:
4597                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4598         case PORT_B:
4599                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4600         case PORT_C:
4601                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4602         case PORT_D:
4603                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4604         default:
4605                 WARN_ON_ONCE(1);
4606                 return POWER_DOMAIN_PORT_OTHER;
4607         }
4608 }
4609
4610 #define for_each_power_domain(domain, mask)                             \
4611         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4612                 if ((1 << (domain)) & (mask))
4613
4614 enum intel_display_power_domain
4615 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4616 {
4617         struct drm_device *dev = intel_encoder->base.dev;
4618         struct intel_digital_port *intel_dig_port;
4619
4620         switch (intel_encoder->type) {
4621         case INTEL_OUTPUT_UNKNOWN:
4622                 /* Only DDI platforms should ever use this output type */
4623                 WARN_ON_ONCE(!HAS_DDI(dev));
4624         case INTEL_OUTPUT_DISPLAYPORT:
4625         case INTEL_OUTPUT_HDMI:
4626         case INTEL_OUTPUT_EDP:
4627                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4628                 return port_to_power_domain(intel_dig_port->port);
4629         case INTEL_OUTPUT_DP_MST:
4630                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4631                 return port_to_power_domain(intel_dig_port->port);
4632         case INTEL_OUTPUT_ANALOG:
4633                 return POWER_DOMAIN_PORT_CRT;
4634         case INTEL_OUTPUT_DSI:
4635                 return POWER_DOMAIN_PORT_DSI;
4636         default:
4637                 return POWER_DOMAIN_PORT_OTHER;
4638         }
4639 }
4640
4641 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->dev;
4644         struct intel_encoder *intel_encoder;
4645         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4646         enum pipe pipe = intel_crtc->pipe;
4647         unsigned long mask;
4648         enum transcoder transcoder;
4649
4650         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4651
4652         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4653         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4654         if (intel_crtc->config.pch_pfit.enabled ||
4655             intel_crtc->config.pch_pfit.force_thru)
4656                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4657
4658         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4659                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4660
4661         return mask;
4662 }
4663
4664 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4665 {
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4668         struct intel_crtc *crtc;
4669
4670         /*
4671          * First get all needed power domains, then put all unneeded, to avoid
4672          * any unnecessary toggling of the power wells.
4673          */
4674         for_each_intel_crtc(dev, crtc) {
4675                 enum intel_display_power_domain domain;
4676
4677                 if (!crtc->base.enabled)
4678                         continue;
4679
4680                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4681
4682                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4683                         intel_display_power_get(dev_priv, domain);
4684         }
4685
4686         if (dev_priv->display.modeset_global_resources)
4687                 dev_priv->display.modeset_global_resources(dev);
4688
4689         for_each_intel_crtc(dev, crtc) {
4690                 enum intel_display_power_domain domain;
4691
4692                 for_each_power_domain(domain, crtc->enabled_power_domains)
4693                         intel_display_power_put(dev_priv, domain);
4694
4695                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4696         }
4697
4698         intel_display_set_init_power(dev_priv, false);
4699 }
4700
4701 /* returns HPLL frequency in kHz */
4702 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4703 {
4704         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4705
4706         /* Obtain SKU information */
4707         mutex_lock(&dev_priv->dpio_lock);
4708         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4709                 CCK_FUSE_HPLL_FREQ_MASK;
4710         mutex_unlock(&dev_priv->dpio_lock);
4711
4712         return vco_freq[hpll_freq] * 1000;
4713 }
4714
4715 static void vlv_update_cdclk(struct drm_device *dev)
4716 {
4717         struct drm_i915_private *dev_priv = dev->dev_private;
4718
4719         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4720         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4721                          dev_priv->vlv_cdclk_freq);
4722
4723         /*
4724          * Program the gmbus_freq based on the cdclk frequency.
4725          * BSpec erroneously claims we should aim for 4MHz, but
4726          * in fact 1MHz is the correct frequency.
4727          */
4728         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4729 }
4730
4731 /* Adjust CDclk dividers to allow high res or save power if possible */
4732 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4733 {
4734         struct drm_i915_private *dev_priv = dev->dev_private;
4735         u32 val, cmd;
4736
4737         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4738
4739         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4740                 cmd = 2;
4741         else if (cdclk == 266667)
4742                 cmd = 1;
4743         else
4744                 cmd = 0;
4745
4746         mutex_lock(&dev_priv->rps.hw_lock);
4747         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4748         val &= ~DSPFREQGUAR_MASK;
4749         val |= (cmd << DSPFREQGUAR_SHIFT);
4750         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4751         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4752                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4753                      50)) {
4754                 DRM_ERROR("timed out waiting for CDclk change\n");
4755         }
4756         mutex_unlock(&dev_priv->rps.hw_lock);
4757
4758         if (cdclk == 400000) {
4759                 u32 divider;
4760
4761                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4762
4763                 mutex_lock(&dev_priv->dpio_lock);
4764                 /* adjust cdclk divider */
4765                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4766                 val &= ~DISPLAY_FREQUENCY_VALUES;
4767                 val |= divider;
4768                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4769
4770                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4771                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4772                              50))
4773                         DRM_ERROR("timed out waiting for CDclk change\n");
4774                 mutex_unlock(&dev_priv->dpio_lock);
4775         }
4776
4777         mutex_lock(&dev_priv->dpio_lock);
4778         /* adjust self-refresh exit latency value */
4779         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4780         val &= ~0x7f;
4781
4782         /*
4783          * For high bandwidth configs, we set a higher latency in the bunit
4784          * so that the core display fetch happens in time to avoid underruns.
4785          */
4786         if (cdclk == 400000)
4787                 val |= 4500 / 250; /* 4.5 usec */
4788         else
4789                 val |= 3000 / 250; /* 3.0 usec */
4790         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4791         mutex_unlock(&dev_priv->dpio_lock);
4792
4793         vlv_update_cdclk(dev);
4794 }
4795
4796 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4797 {
4798         struct drm_i915_private *dev_priv = dev->dev_private;
4799         u32 val, cmd;
4800
4801         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4802
4803         switch (cdclk) {
4804         case 400000:
4805                 cmd = 3;
4806                 break;
4807         case 333333:
4808         case 320000:
4809                 cmd = 2;
4810                 break;
4811         case 266667:
4812                 cmd = 1;
4813                 break;
4814         case 200000:
4815                 cmd = 0;
4816                 break;
4817         default:
4818                 WARN_ON(1);
4819                 return;
4820         }
4821
4822         mutex_lock(&dev_priv->rps.hw_lock);
4823         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4824         val &= ~DSPFREQGUAR_MASK_CHV;
4825         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4826         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4827         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4828                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4829                      50)) {
4830                 DRM_ERROR("timed out waiting for CDclk change\n");
4831         }
4832         mutex_unlock(&dev_priv->rps.hw_lock);
4833
4834         vlv_update_cdclk(dev);
4835 }
4836
4837 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4838                                  int max_pixclk)
4839 {
4840         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4841
4842         /* FIXME: Punit isn't quite ready yet */
4843         if (IS_CHERRYVIEW(dev_priv->dev))
4844                 return 400000;
4845
4846         /*
4847          * Really only a few cases to deal with, as only 4 CDclks are supported:
4848          *   200MHz
4849          *   267MHz
4850          *   320/333MHz (depends on HPLL freq)
4851          *   400MHz
4852          * So we check to see whether we're above 90% of the lower bin and
4853          * adjust if needed.
4854          *
4855          * We seem to get an unstable or solid color picture at 200MHz.
4856          * Not sure what's wrong. For now use 200MHz only when all pipes
4857          * are off.
4858          */
4859         if (max_pixclk > freq_320*9/10)
4860                 return 400000;
4861         else if (max_pixclk > 266667*9/10)
4862                 return freq_320;
4863         else if (max_pixclk > 0)
4864                 return 266667;
4865         else
4866                 return 200000;
4867 }
4868
4869 /* compute the max pixel clock for new configuration */
4870 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4871 {
4872         struct drm_device *dev = dev_priv->dev;
4873         struct intel_crtc *intel_crtc;
4874         int max_pixclk = 0;
4875
4876         for_each_intel_crtc(dev, intel_crtc) {
4877                 if (intel_crtc->new_enabled)
4878                         max_pixclk = max(max_pixclk,
4879                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4880         }
4881
4882         return max_pixclk;
4883 }
4884
4885 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4886                                             unsigned *prepare_pipes)
4887 {
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         struct intel_crtc *intel_crtc;
4890         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4891
4892         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4893             dev_priv->vlv_cdclk_freq)
4894                 return;
4895
4896         /* disable/enable all currently active pipes while we change cdclk */
4897         for_each_intel_crtc(dev, intel_crtc)
4898                 if (intel_crtc->base.enabled)
4899                         *prepare_pipes |= (1 << intel_crtc->pipe);
4900 }
4901
4902 static void valleyview_modeset_global_resources(struct drm_device *dev)
4903 {
4904         struct drm_i915_private *dev_priv = dev->dev_private;
4905         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4906         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4907
4908         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4909                 if (IS_CHERRYVIEW(dev))
4910                         cherryview_set_cdclk(dev, req_cdclk);
4911                 else
4912                         valleyview_set_cdclk(dev, req_cdclk);
4913         }
4914 }
4915
4916 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4917 {
4918         struct drm_device *dev = crtc->dev;
4919         struct drm_i915_private *dev_priv = to_i915(dev);
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         struct intel_encoder *encoder;
4922         int pipe = intel_crtc->pipe;
4923         bool is_dsi;
4924
4925         WARN_ON(!crtc->enabled);
4926
4927         if (intel_crtc->active)
4928                 return;
4929
4930         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4931
4932         if (!is_dsi) {
4933                 if (IS_CHERRYVIEW(dev))
4934                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4935                 else
4936                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4937         }
4938
4939         if (intel_crtc->config.has_dp_encoder)
4940                 intel_dp_set_m_n(intel_crtc);
4941
4942         intel_set_pipe_timings(intel_crtc);
4943
4944         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4945                 struct drm_i915_private *dev_priv = dev->dev_private;
4946
4947                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4948                 I915_WRITE(CHV_CANVAS(pipe), 0);
4949         }
4950
4951         i9xx_set_pipeconf(intel_crtc);
4952
4953         intel_crtc->active = true;
4954
4955         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4956
4957         for_each_encoder_on_crtc(dev, crtc, encoder)
4958                 if (encoder->pre_pll_enable)
4959                         encoder->pre_pll_enable(encoder);
4960
4961         if (!is_dsi) {
4962                 if (IS_CHERRYVIEW(dev))
4963                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4964                 else
4965                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4966         }
4967
4968         for_each_encoder_on_crtc(dev, crtc, encoder)
4969                 if (encoder->pre_enable)
4970                         encoder->pre_enable(encoder);
4971
4972         i9xx_pfit_enable(intel_crtc);
4973
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_update_watermarks(crtc);
4977         intel_enable_pipe(intel_crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder)
4980                 encoder->enable(encoder);
4981
4982         assert_vblank_disabled(crtc);
4983         drm_crtc_vblank_on(crtc);
4984
4985         intel_crtc_enable_planes(crtc);
4986
4987         /* Underruns don't raise interrupts, so check manually. */
4988         i9xx_check_fifo_underruns(dev_priv);
4989 }
4990
4991 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4992 {
4993         struct drm_device *dev = crtc->base.dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995
4996         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4997         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4998 }
4999
5000 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5001 {
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_private *dev_priv = to_i915(dev);
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005         struct intel_encoder *encoder;
5006         int pipe = intel_crtc->pipe;
5007
5008         WARN_ON(!crtc->enabled);
5009
5010         if (intel_crtc->active)
5011                 return;
5012
5013         i9xx_set_pll_dividers(intel_crtc);
5014
5015         if (intel_crtc->config.has_dp_encoder)
5016                 intel_dp_set_m_n(intel_crtc);
5017
5018         intel_set_pipe_timings(intel_crtc);
5019
5020         i9xx_set_pipeconf(intel_crtc);
5021
5022         intel_crtc->active = true;
5023
5024         if (!IS_GEN2(dev))
5025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->pre_enable)
5029                         encoder->pre_enable(encoder);
5030
5031         i9xx_enable_pll(intel_crtc);
5032
5033         i9xx_pfit_enable(intel_crtc);
5034
5035         intel_crtc_load_lut(crtc);
5036
5037         intel_update_watermarks(crtc);
5038         intel_enable_pipe(intel_crtc);
5039
5040         for_each_encoder_on_crtc(dev, crtc, encoder)
5041                 encoder->enable(encoder);
5042
5043         assert_vblank_disabled(crtc);
5044         drm_crtc_vblank_on(crtc);
5045
5046         intel_crtc_enable_planes(crtc);
5047
5048         /*
5049          * Gen2 reports pipe underruns whenever all planes are disabled.
5050          * So don't enable underrun reporting before at least some planes
5051          * are enabled.
5052          * FIXME: Need to fix the logic to work when we turn off all planes
5053          * but leave the pipe running.
5054          */
5055         if (IS_GEN2(dev))
5056                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5057
5058         /* Underruns don't raise interrupts, so check manually. */
5059         i9xx_check_fifo_underruns(dev_priv);
5060 }
5061
5062 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5063 {
5064         struct drm_device *dev = crtc->base.dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066
5067         if (!crtc->config.gmch_pfit.control)
5068                 return;
5069
5070         assert_pipe_disabled(dev_priv, crtc->pipe);
5071
5072         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5073                          I915_READ(PFIT_CONTROL));
5074         I915_WRITE(PFIT_CONTROL, 0);
5075 }
5076
5077 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5078 {
5079         struct drm_device *dev = crtc->dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         struct intel_encoder *encoder;
5083         int pipe = intel_crtc->pipe;
5084
5085         if (!intel_crtc->active)
5086                 return;
5087
5088         /*
5089          * Gen2 reports pipe underruns whenever all planes are disabled.
5090          * So diasble underrun reporting before all the planes get disabled.
5091          * FIXME: Need to fix the logic to work when we turn off all planes
5092          * but leave the pipe running.
5093          */
5094         if (IS_GEN2(dev))
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5096
5097         /*
5098          * Vblank time updates from the shadow to live plane control register
5099          * are blocked if the memory self-refresh mode is active at that
5100          * moment. So to make sure the plane gets truly disabled, disable
5101          * first the self-refresh mode. The self-refresh enable bit in turn
5102          * will be checked/applied by the HW only at the next frame start
5103          * event which is after the vblank start event, so we need to have a
5104          * wait-for-vblank between disabling the plane and the pipe.
5105          */
5106         intel_set_memory_cxsr(dev_priv, false);
5107         intel_crtc_disable_planes(crtc);
5108
5109         /*
5110          * On gen2 planes are double buffered but the pipe isn't, so we must
5111          * wait for planes to fully turn off before disabling the pipe.
5112          * We also need to wait on all gmch platforms because of the
5113          * self-refresh mode constraint explained above.
5114          */
5115         intel_wait_for_vblank(dev, pipe);
5116
5117         drm_crtc_vblank_off(crtc);
5118         assert_vblank_disabled(crtc);
5119
5120         for_each_encoder_on_crtc(dev, crtc, encoder)
5121                 encoder->disable(encoder);
5122
5123         intel_disable_pipe(intel_crtc);
5124
5125         i9xx_pfit_disable(intel_crtc);
5126
5127         for_each_encoder_on_crtc(dev, crtc, encoder)
5128                 if (encoder->post_disable)
5129                         encoder->post_disable(encoder);
5130
5131         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5132                 if (IS_CHERRYVIEW(dev))
5133                         chv_disable_pll(dev_priv, pipe);
5134                 else if (IS_VALLEYVIEW(dev))
5135                         vlv_disable_pll(dev_priv, pipe);
5136                 else
5137                         i9xx_disable_pll(intel_crtc);
5138         }
5139
5140         if (!IS_GEN2(dev))
5141                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143         intel_crtc->active = false;
5144         intel_update_watermarks(crtc);
5145
5146         mutex_lock(&dev->struct_mutex);
5147         intel_update_fbc(dev);
5148         mutex_unlock(&dev->struct_mutex);
5149 }
5150
5151 static void i9xx_crtc_off(struct drm_crtc *crtc)
5152 {
5153 }
5154
5155 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5156                                     bool enabled)
5157 {
5158         struct drm_device *dev = crtc->dev;
5159         struct drm_i915_master_private *master_priv;
5160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161         int pipe = intel_crtc->pipe;
5162
5163         if (!dev->primary->master)
5164                 return;
5165
5166         master_priv = dev->primary->master->driver_priv;
5167         if (!master_priv->sarea_priv)
5168                 return;
5169
5170         switch (pipe) {
5171         case 0:
5172                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5173                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5174                 break;
5175         case 1:
5176                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5177                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5178                 break;
5179         default:
5180                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5181                 break;
5182         }
5183 }
5184
5185 /* Master function to enable/disable CRTC and corresponding power wells */
5186 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5187 {
5188         struct drm_device *dev = crtc->dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191         enum intel_display_power_domain domain;
5192         unsigned long domains;
5193
5194         if (enable) {
5195                 if (!intel_crtc->active) {
5196                         domains = get_crtc_power_domains(crtc);
5197                         for_each_power_domain(domain, domains)
5198                                 intel_display_power_get(dev_priv, domain);
5199                         intel_crtc->enabled_power_domains = domains;
5200
5201                         dev_priv->display.crtc_enable(crtc);
5202                 }
5203         } else {
5204                 if (intel_crtc->active) {
5205                         dev_priv->display.crtc_disable(crtc);
5206
5207                         domains = intel_crtc->enabled_power_domains;
5208                         for_each_power_domain(domain, domains)
5209                                 intel_display_power_put(dev_priv, domain);
5210                         intel_crtc->enabled_power_domains = 0;
5211                 }
5212         }
5213 }
5214
5215 /**
5216  * Sets the power management mode of the pipe and plane.
5217  */
5218 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5219 {
5220         struct drm_device *dev = crtc->dev;
5221         struct intel_encoder *intel_encoder;
5222         bool enable = false;
5223
5224         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225                 enable |= intel_encoder->connectors_active;
5226
5227         intel_crtc_control(crtc, enable);
5228
5229         intel_crtc_update_sarea(crtc, enable);
5230 }
5231
5232 static void intel_crtc_disable(struct drm_crtc *crtc)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_connector *connector;
5236         struct drm_i915_private *dev_priv = dev->dev_private;
5237         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5238         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5239
5240         /* crtc should still be enabled when we disable it. */
5241         WARN_ON(!crtc->enabled);
5242
5243         dev_priv->display.crtc_disable(crtc);
5244         intel_crtc_update_sarea(crtc, false);
5245         dev_priv->display.off(crtc);
5246
5247         if (crtc->primary->fb) {
5248                 mutex_lock(&dev->struct_mutex);
5249                 intel_unpin_fb_obj(old_obj);
5250                 i915_gem_track_fb(old_obj, NULL,
5251                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5252                 mutex_unlock(&dev->struct_mutex);
5253                 crtc->primary->fb = NULL;
5254         }
5255
5256         /* Update computed state. */
5257         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258                 if (!connector->encoder || !connector->encoder->crtc)
5259                         continue;
5260
5261                 if (connector->encoder->crtc != crtc)
5262                         continue;
5263
5264                 connector->dpms = DRM_MODE_DPMS_OFF;
5265                 to_intel_encoder(connector->encoder)->connectors_active = false;
5266         }
5267 }
5268
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5270 {
5271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273         drm_encoder_cleanup(encoder);
5274         kfree(intel_encoder);
5275 }
5276
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279  * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5281 {
5282         if (mode == DRM_MODE_DPMS_ON) {
5283                 encoder->connectors_active = true;
5284
5285                 intel_crtc_update_dpms(encoder->base.crtc);
5286         } else {
5287                 encoder->connectors_active = false;
5288
5289                 intel_crtc_update_dpms(encoder->base.crtc);
5290         }
5291 }
5292
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294  * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5296 {
5297         if (connector->get_hw_state(connector)) {
5298                 struct intel_encoder *encoder = connector->encoder;
5299                 struct drm_crtc *crtc;
5300                 bool encoder_enabled;
5301                 enum pipe pipe;
5302
5303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304                               connector->base.base.id,
5305                               connector->base.name);
5306
5307                 /* there is no real hw state for MST connectors */
5308                 if (connector->mst_port)
5309                         return;
5310
5311                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312                      "wrong connector dpms state\n");
5313                 WARN(connector->base.encoder != &encoder->base,
5314                      "active connector not linked to encoder\n");
5315
5316                 if (encoder) {
5317                         WARN(!encoder->connectors_active,
5318                              "encoder->connectors_active not set\n");
5319
5320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321                         WARN(!encoder_enabled, "encoder not enabled\n");
5322                         if (WARN_ON(!encoder->base.crtc))
5323                                 return;
5324
5325                         crtc = encoder->base.crtc;
5326
5327                         WARN(!crtc->enabled, "crtc not enabled\n");
5328                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5330                              "encoder active on the wrong pipe\n");
5331                 }
5332         }
5333 }
5334
5335 /* Even simpler default implementation, if there's really no special case to
5336  * consider. */
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5338 {
5339         /* All the simple cases only support two dpms states. */
5340         if (mode != DRM_MODE_DPMS_ON)
5341                 mode = DRM_MODE_DPMS_OFF;
5342
5343         if (mode == connector->dpms)
5344                 return;
5345
5346         connector->dpms = mode;
5347
5348         /* Only need to change hw state when actually enabled */
5349         if (connector->encoder)
5350                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5351
5352         intel_modeset_check_state(connector->dev);
5353 }
5354
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356  * one connector and no cloning and hence the encoder state determines the state
5357  * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5359 {
5360         enum pipe pipe = 0;
5361         struct intel_encoder *encoder = connector->encoder;
5362
5363         return encoder->get_hw_state(encoder, &pipe);
5364 }
5365
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367                                      struct intel_crtc_config *pipe_config)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *pipe_B_crtc =
5371                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374                       pipe_name(pipe), pipe_config->fdi_lanes);
5375         if (pipe_config->fdi_lanes > 4) {
5376                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377                               pipe_name(pipe), pipe_config->fdi_lanes);
5378                 return false;
5379         }
5380
5381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382                 if (pipe_config->fdi_lanes > 2) {
5383                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384                                       pipe_config->fdi_lanes);
5385                         return false;
5386                 } else {
5387                         return true;
5388                 }
5389         }
5390
5391         if (INTEL_INFO(dev)->num_pipes == 2)
5392                 return true;
5393
5394         /* Ivybridge 3 pipe is really complicated */
5395         switch (pipe) {
5396         case PIPE_A:
5397                 return true;
5398         case PIPE_B:
5399                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400                     pipe_config->fdi_lanes > 2) {
5401                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402                                       pipe_name(pipe), pipe_config->fdi_lanes);
5403                         return false;
5404                 }
5405                 return true;
5406         case PIPE_C:
5407                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408                     pipe_B_crtc->config.fdi_lanes <= 2) {
5409                         if (pipe_config->fdi_lanes > 2) {
5410                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411                                               pipe_name(pipe), pipe_config->fdi_lanes);
5412                                 return false;
5413                         }
5414                 } else {
5415                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416                         return false;
5417                 }
5418                 return true;
5419         default:
5420                 BUG();
5421         }
5422 }
5423
5424 #define RETRY 1
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426                                        struct intel_crtc_config *pipe_config)
5427 {
5428         struct drm_device *dev = intel_crtc->base.dev;
5429         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430         int lane, link_bw, fdi_dotclock;
5431         bool setup_ok, needs_recompute = false;
5432
5433 retry:
5434         /* FDI is a binary signal running at ~2.7GHz, encoding
5435          * each output octet as 10 bits. The actual frequency
5436          * is stored as a divider into a 100MHz clock, and the
5437          * mode pixel clock is stored in units of 1KHz.
5438          * Hence the bw of each lane in terms of the mode signal
5439          * is:
5440          */
5441         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
5443         fdi_dotclock = adjusted_mode->crtc_clock;
5444
5445         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446                                            pipe_config->pipe_bpp);
5447
5448         pipe_config->fdi_lanes = lane;
5449
5450         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451                                link_bw, &pipe_config->fdi_m_n);
5452
5453         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454                                             intel_crtc->pipe, pipe_config);
5455         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456                 pipe_config->pipe_bpp -= 2*3;
5457                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458                               pipe_config->pipe_bpp);
5459                 needs_recompute = true;
5460                 pipe_config->bw_constrained = true;
5461
5462                 goto retry;
5463         }
5464
5465         if (needs_recompute)
5466                 return RETRY;
5467
5468         return setup_ok ? 0 : -EINVAL;
5469 }
5470
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472                                    struct intel_crtc_config *pipe_config)
5473 {
5474         pipe_config->ips_enabled = i915.enable_ips &&
5475                                    hsw_crtc_supports_ips(crtc) &&
5476                                    pipe_config->pipe_bpp <= 24;
5477 }
5478
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480                                      struct intel_crtc_config *pipe_config)
5481 {
5482         struct drm_device *dev = crtc->base.dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5485
5486         /* FIXME should check pixel clock limits on all platforms */
5487         if (INTEL_INFO(dev)->gen < 4) {
5488                 int clock_limit =
5489                         dev_priv->display.get_display_clock_speed(dev);
5490
5491                 /*
5492                  * Enable pixel doubling when the dot clock
5493                  * is > 90% of the (display) core speed.
5494                  *
5495                  * GDG double wide on either pipe,
5496                  * otherwise pipe A only.
5497                  */
5498                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5500                         clock_limit *= 2;
5501                         pipe_config->double_wide = true;
5502                 }
5503
5504                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5505                         return -EINVAL;
5506         }
5507
5508         /*
5509          * Pipe horizontal size must be even in:
5510          * - DVO ganged mode
5511          * - LVDS dual channel mode
5512          * - Double wide pipe
5513          */
5514         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516                 pipe_config->pipe_src_w &= ~1;
5517
5518         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5520          */
5521         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5523                 return -EINVAL;
5524
5525         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529                  * for lvds. */
5530                 pipe_config->pipe_bpp = 8*3;
5531         }
5532
5533         if (HAS_IPS(dev))
5534                 hsw_compute_ips_config(crtc, pipe_config);
5535
5536         if (pipe_config->has_pch_encoder)
5537                 return ironlake_fdi_compute_config(crtc, pipe_config);
5538
5539         return 0;
5540 }
5541
5542 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         u32 val;
5546         int divider;
5547
5548         /* FIXME: Punit isn't quite ready yet */
5549         if (IS_CHERRYVIEW(dev))
5550                 return 400000;
5551
5552         if (dev_priv->hpll_freq == 0)
5553                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5554
5555         mutex_lock(&dev_priv->dpio_lock);
5556         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5557         mutex_unlock(&dev_priv->dpio_lock);
5558
5559         divider = val & DISPLAY_FREQUENCY_VALUES;
5560
5561         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5562              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5563              "cdclk change in progress\n");
5564
5565         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5566 }
5567
5568 static int i945_get_display_clock_speed(struct drm_device *dev)
5569 {
5570         return 400000;
5571 }
5572
5573 static int i915_get_display_clock_speed(struct drm_device *dev)
5574 {
5575         return 333000;
5576 }
5577
5578 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5579 {
5580         return 200000;
5581 }
5582
5583 static int pnv_get_display_clock_speed(struct drm_device *dev)
5584 {
5585         u16 gcfgc = 0;
5586
5587         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5588
5589         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5590         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5591                 return 267000;
5592         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5593                 return 333000;
5594         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5595                 return 444000;
5596         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5597                 return 200000;
5598         default:
5599                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5600         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5601                 return 133000;
5602         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5603                 return 167000;
5604         }
5605 }
5606
5607 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5608 {
5609         u16 gcfgc = 0;
5610
5611         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5612
5613         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5614                 return 133000;
5615         else {
5616                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5617                 case GC_DISPLAY_CLOCK_333_MHZ:
5618                         return 333000;
5619                 default:
5620                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5621                         return 190000;
5622                 }
5623         }
5624 }
5625
5626 static int i865_get_display_clock_speed(struct drm_device *dev)
5627 {
5628         return 266000;
5629 }
5630
5631 static int i855_get_display_clock_speed(struct drm_device *dev)
5632 {
5633         u16 hpllcc = 0;
5634         /* Assume that the hardware is in the high speed state.  This
5635          * should be the default.
5636          */
5637         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5638         case GC_CLOCK_133_200:
5639         case GC_CLOCK_100_200:
5640                 return 200000;
5641         case GC_CLOCK_166_250:
5642                 return 250000;
5643         case GC_CLOCK_100_133:
5644                 return 133000;
5645         }
5646
5647         /* Shouldn't happen */
5648         return 0;
5649 }
5650
5651 static int i830_get_display_clock_speed(struct drm_device *dev)
5652 {
5653         return 133000;
5654 }
5655
5656 static void
5657 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5658 {
5659         while (*num > DATA_LINK_M_N_MASK ||
5660                *den > DATA_LINK_M_N_MASK) {
5661                 *num >>= 1;
5662                 *den >>= 1;
5663         }
5664 }
5665
5666 static void compute_m_n(unsigned int m, unsigned int n,
5667                         uint32_t *ret_m, uint32_t *ret_n)
5668 {
5669         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5670         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5671         intel_reduce_m_n_ratio(ret_m, ret_n);
5672 }
5673
5674 void
5675 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5676                        int pixel_clock, int link_clock,
5677                        struct intel_link_m_n *m_n)
5678 {
5679         m_n->tu = 64;
5680
5681         compute_m_n(bits_per_pixel * pixel_clock,
5682                     link_clock * nlanes * 8,
5683                     &m_n->gmch_m, &m_n->gmch_n);
5684
5685         compute_m_n(pixel_clock, link_clock,
5686                     &m_n->link_m, &m_n->link_n);
5687 }
5688
5689 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5690 {
5691         if (i915.panel_use_ssc >= 0)
5692                 return i915.panel_use_ssc != 0;
5693         return dev_priv->vbt.lvds_use_ssc
5694                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5695 }
5696
5697 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5698 {
5699         struct drm_device *dev = crtc->base.dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         int refclk;
5702
5703         if (IS_VALLEYVIEW(dev)) {
5704                 refclk = 100000;
5705         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5706             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5707                 refclk = dev_priv->vbt.lvds_ssc_freq;
5708                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5709         } else if (!IS_GEN2(dev)) {
5710                 refclk = 96000;
5711         } else {
5712                 refclk = 48000;
5713         }
5714
5715         return refclk;
5716 }
5717
5718 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5719 {
5720         return (1 << dpll->n) << 16 | dpll->m2;
5721 }
5722
5723 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5724 {
5725         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5726 }
5727
5728 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5729                                      intel_clock_t *reduced_clock)
5730 {
5731         struct drm_device *dev = crtc->base.dev;
5732         u32 fp, fp2 = 0;
5733
5734         if (IS_PINEVIEW(dev)) {
5735                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5736                 if (reduced_clock)
5737                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5738         } else {
5739                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5740                 if (reduced_clock)
5741                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5742         }
5743
5744         crtc->config.dpll_hw_state.fp0 = fp;
5745
5746         crtc->lowfreq_avail = false;
5747         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5748             reduced_clock && i915.powersave) {
5749                 crtc->config.dpll_hw_state.fp1 = fp2;
5750                 crtc->lowfreq_avail = true;
5751         } else {
5752                 crtc->config.dpll_hw_state.fp1 = fp;
5753         }
5754 }
5755
5756 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5757                 pipe)
5758 {
5759         u32 reg_val;
5760
5761         /*
5762          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5763          * and set it to a reasonable value instead.
5764          */
5765         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5766         reg_val &= 0xffffff00;
5767         reg_val |= 0x00000030;
5768         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5769
5770         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5771         reg_val &= 0x8cffffff;
5772         reg_val = 0x8c000000;
5773         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5774
5775         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5776         reg_val &= 0xffffff00;
5777         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5778
5779         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5780         reg_val &= 0x00ffffff;
5781         reg_val |= 0xb0000000;
5782         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5783 }
5784
5785 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5786                                          struct intel_link_m_n *m_n)
5787 {
5788         struct drm_device *dev = crtc->base.dev;
5789         struct drm_i915_private *dev_priv = dev->dev_private;
5790         int pipe = crtc->pipe;
5791
5792         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5793         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5794         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5795         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5796 }
5797
5798 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5799                                          struct intel_link_m_n *m_n,
5800                                          struct intel_link_m_n *m2_n2)
5801 {
5802         struct drm_device *dev = crtc->base.dev;
5803         struct drm_i915_private *dev_priv = dev->dev_private;
5804         int pipe = crtc->pipe;
5805         enum transcoder transcoder = crtc->config.cpu_transcoder;
5806
5807         if (INTEL_INFO(dev)->gen >= 5) {
5808                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5809                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5810                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5811                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5812                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5813                  * for gen < 8) and if DRRS is supported (to make sure the
5814                  * registers are not unnecessarily accessed).
5815                  */
5816                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5817                         crtc->config.has_drrs) {
5818                         I915_WRITE(PIPE_DATA_M2(transcoder),
5819                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5820                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5821                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5822                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5823                 }
5824         } else {
5825                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5827                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5828                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5829         }
5830 }
5831
5832 void intel_dp_set_m_n(struct intel_crtc *crtc)
5833 {
5834         if (crtc->config.has_pch_encoder)
5835                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5836         else
5837                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5838                                                    &crtc->config.dp_m2_n2);
5839 }
5840
5841 static void vlv_update_pll(struct intel_crtc *crtc,
5842                            struct intel_crtc_config *pipe_config)
5843 {
5844         u32 dpll, dpll_md;
5845
5846         /*
5847          * Enable DPIO clock input. We should never disable the reference
5848          * clock for pipe B, since VGA hotplug / manual detection depends
5849          * on it.
5850          */
5851         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5852                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5853         /* We should never disable this, set it here for state tracking */
5854         if (crtc->pipe == PIPE_B)
5855                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5856         dpll |= DPLL_VCO_ENABLE;
5857         pipe_config->dpll_hw_state.dpll = dpll;
5858
5859         dpll_md = (pipe_config->pixel_multiplier - 1)
5860                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5861         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5862 }
5863
5864 static void vlv_prepare_pll(struct intel_crtc *crtc,
5865                             const struct intel_crtc_config *pipe_config)
5866 {
5867         struct drm_device *dev = crtc->base.dev;
5868         struct drm_i915_private *dev_priv = dev->dev_private;
5869         int pipe = crtc->pipe;
5870         u32 mdiv;
5871         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5872         u32 coreclk, reg_val;
5873
5874         mutex_lock(&dev_priv->dpio_lock);
5875
5876         bestn = pipe_config->dpll.n;
5877         bestm1 = pipe_config->dpll.m1;
5878         bestm2 = pipe_config->dpll.m2;
5879         bestp1 = pipe_config->dpll.p1;
5880         bestp2 = pipe_config->dpll.p2;
5881
5882         /* See eDP HDMI DPIO driver vbios notes doc */
5883
5884         /* PLL B needs special handling */
5885         if (pipe == PIPE_B)
5886                 vlv_pllb_recal_opamp(dev_priv, pipe);
5887
5888         /* Set up Tx target for periodic Rcomp update */
5889         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5890
5891         /* Disable target IRef on PLL */
5892         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5893         reg_val &= 0x00ffffff;
5894         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5895
5896         /* Disable fast lock */
5897         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5898
5899         /* Set idtafcrecal before PLL is enabled */
5900         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5901         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5902         mdiv |= ((bestn << DPIO_N_SHIFT));
5903         mdiv |= (1 << DPIO_K_SHIFT);
5904
5905         /*
5906          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5907          * but we don't support that).
5908          * Note: don't use the DAC post divider as it seems unstable.
5909          */
5910         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5911         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5912
5913         mdiv |= DPIO_ENABLE_CALIBRATION;
5914         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5915
5916         /* Set HBR and RBR LPF coefficients */
5917         if (pipe_config->port_clock == 162000 ||
5918             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5919             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5920                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5921                                  0x009f0003);
5922         else
5923                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5924                                  0x00d0000f);
5925
5926         if (crtc->config.has_dp_encoder) {
5927                 /* Use SSC source */
5928                 if (pipe == PIPE_A)
5929                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5930                                          0x0df40000);
5931                 else
5932                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5933                                          0x0df70000);
5934         } else { /* HDMI or VGA */
5935                 /* Use bend source */
5936                 if (pipe == PIPE_A)
5937                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938                                          0x0df70000);
5939                 else
5940                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5941                                          0x0df40000);
5942         }
5943
5944         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5945         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5946         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5947             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5948                 coreclk |= 0x01000000;
5949         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5950
5951         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5952         mutex_unlock(&dev_priv->dpio_lock);
5953 }
5954
5955 static void chv_update_pll(struct intel_crtc *crtc,
5956                            struct intel_crtc_config *pipe_config)
5957 {
5958         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5959                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5960                 DPLL_VCO_ENABLE;
5961         if (crtc->pipe != PIPE_A)
5962                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5963
5964         pipe_config->dpll_hw_state.dpll_md =
5965                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5966 }
5967
5968 static void chv_prepare_pll(struct intel_crtc *crtc,
5969                             const struct intel_crtc_config *pipe_config)
5970 {
5971         struct drm_device *dev = crtc->base.dev;
5972         struct drm_i915_private *dev_priv = dev->dev_private;
5973         int pipe = crtc->pipe;
5974         int dpll_reg = DPLL(crtc->pipe);
5975         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5976         u32 loopfilter, intcoeff;
5977         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5978         int refclk;
5979
5980         bestn = pipe_config->dpll.n;
5981         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5982         bestm1 = pipe_config->dpll.m1;
5983         bestm2 = pipe_config->dpll.m2 >> 22;
5984         bestp1 = pipe_config->dpll.p1;
5985         bestp2 = pipe_config->dpll.p2;
5986
5987         /*
5988          * Enable Refclk and SSC
5989          */
5990         I915_WRITE(dpll_reg,
5991                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5992
5993         mutex_lock(&dev_priv->dpio_lock);
5994
5995         /* p1 and p2 divider */
5996         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5997                         5 << DPIO_CHV_S1_DIV_SHIFT |
5998                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5999                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6000                         1 << DPIO_CHV_K_DIV_SHIFT);
6001
6002         /* Feedback post-divider - m2 */
6003         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6004
6005         /* Feedback refclk divider - n and m1 */
6006         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6007                         DPIO_CHV_M1_DIV_BY_2 |
6008                         1 << DPIO_CHV_N_DIV_SHIFT);
6009
6010         /* M2 fraction division */
6011         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6012
6013         /* M2 fraction division enable */
6014         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6015                        DPIO_CHV_FRAC_DIV_EN |
6016                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6017
6018         /* Loop filter */
6019         refclk = i9xx_get_refclk(crtc, 0);
6020         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6021                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6022         if (refclk == 100000)
6023                 intcoeff = 11;
6024         else if (refclk == 38400)
6025                 intcoeff = 10;
6026         else
6027                 intcoeff = 9;
6028         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6029         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6030
6031         /* AFC Recal */
6032         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6033                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6034                         DPIO_AFC_RECAL);
6035
6036         mutex_unlock(&dev_priv->dpio_lock);
6037 }
6038
6039 /**
6040  * vlv_force_pll_on - forcibly enable just the PLL
6041  * @dev_priv: i915 private structure
6042  * @pipe: pipe PLL to enable
6043  * @dpll: PLL configuration
6044  *
6045  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6046  * in cases where we need the PLL enabled even when @pipe is not going to
6047  * be enabled.
6048  */
6049 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6050                       const struct dpll *dpll)
6051 {
6052         struct intel_crtc *crtc =
6053                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6054         struct intel_crtc_config pipe_config = {
6055                 .pixel_multiplier = 1,
6056                 .dpll = *dpll,
6057         };
6058
6059         if (IS_CHERRYVIEW(dev)) {
6060                 chv_update_pll(crtc, &pipe_config);
6061                 chv_prepare_pll(crtc, &pipe_config);
6062                 chv_enable_pll(crtc, &pipe_config);
6063         } else {
6064                 vlv_update_pll(crtc, &pipe_config);
6065                 vlv_prepare_pll(crtc, &pipe_config);
6066                 vlv_enable_pll(crtc, &pipe_config);
6067         }
6068 }
6069
6070 /**
6071  * vlv_force_pll_off - forcibly disable just the PLL
6072  * @dev_priv: i915 private structure
6073  * @pipe: pipe PLL to disable
6074  *
6075  * Disable the PLL for @pipe. To be used in cases where we need
6076  * the PLL enabled even when @pipe is not going to be enabled.
6077  */
6078 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6079 {
6080         if (IS_CHERRYVIEW(dev))
6081                 chv_disable_pll(to_i915(dev), pipe);
6082         else
6083                 vlv_disable_pll(to_i915(dev), pipe);
6084 }
6085
6086 static void i9xx_update_pll(struct intel_crtc *crtc,
6087                             intel_clock_t *reduced_clock,
6088                             int num_connectors)
6089 {
6090         struct drm_device *dev = crtc->base.dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         u32 dpll;
6093         bool is_sdvo;
6094         struct dpll *clock = &crtc->new_config->dpll;
6095
6096         i9xx_update_pll_dividers(crtc, reduced_clock);
6097
6098         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6099                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6100
6101         dpll = DPLL_VGA_MODE_DIS;
6102
6103         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6104                 dpll |= DPLLB_MODE_LVDS;
6105         else
6106                 dpll |= DPLLB_MODE_DAC_SERIAL;
6107
6108         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6109                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6110                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6111         }
6112
6113         if (is_sdvo)
6114                 dpll |= DPLL_SDVO_HIGH_SPEED;
6115
6116         if (crtc->new_config->has_dp_encoder)
6117                 dpll |= DPLL_SDVO_HIGH_SPEED;
6118
6119         /* compute bitmask from p1 value */
6120         if (IS_PINEVIEW(dev))
6121                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6122         else {
6123                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6124                 if (IS_G4X(dev) && reduced_clock)
6125                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6126         }
6127         switch (clock->p2) {
6128         case 5:
6129                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6130                 break;
6131         case 7:
6132                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6133                 break;
6134         case 10:
6135                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6136                 break;
6137         case 14:
6138                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6139                 break;
6140         }
6141         if (INTEL_INFO(dev)->gen >= 4)
6142                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6143
6144         if (crtc->new_config->sdvo_tv_clock)
6145                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6146         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6147                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6148                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6149         else
6150                 dpll |= PLL_REF_INPUT_DREFCLK;
6151
6152         dpll |= DPLL_VCO_ENABLE;
6153         crtc->new_config->dpll_hw_state.dpll = dpll;
6154
6155         if (INTEL_INFO(dev)->gen >= 4) {
6156                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6157                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6158                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6159         }
6160 }
6161
6162 static void i8xx_update_pll(struct intel_crtc *crtc,
6163                             intel_clock_t *reduced_clock,
6164                             int num_connectors)
6165 {
6166         struct drm_device *dev = crtc->base.dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         u32 dpll;
6169         struct dpll *clock = &crtc->new_config->dpll;
6170
6171         i9xx_update_pll_dividers(crtc, reduced_clock);
6172
6173         dpll = DPLL_VGA_MODE_DIS;
6174
6175         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6176                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6177         } else {
6178                 if (clock->p1 == 2)
6179                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6180                 else
6181                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6182                 if (clock->p2 == 4)
6183                         dpll |= PLL_P2_DIVIDE_BY_4;
6184         }
6185
6186         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6187                 dpll |= DPLL_DVO_2X_MODE;
6188
6189         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6190                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6191                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6192         else
6193                 dpll |= PLL_REF_INPUT_DREFCLK;
6194
6195         dpll |= DPLL_VCO_ENABLE;
6196         crtc->new_config->dpll_hw_state.dpll = dpll;
6197 }
6198
6199 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6200 {
6201         struct drm_device *dev = intel_crtc->base.dev;
6202         struct drm_i915_private *dev_priv = dev->dev_private;
6203         enum pipe pipe = intel_crtc->pipe;
6204         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6205         struct drm_display_mode *adjusted_mode =
6206                 &intel_crtc->config.adjusted_mode;
6207         uint32_t crtc_vtotal, crtc_vblank_end;
6208         int vsyncshift = 0;
6209
6210         /* We need to be careful not to changed the adjusted mode, for otherwise
6211          * the hw state checker will get angry at the mismatch. */
6212         crtc_vtotal = adjusted_mode->crtc_vtotal;
6213         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6214
6215         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6216                 /* the chip adds 2 halflines automatically */
6217                 crtc_vtotal -= 1;
6218                 crtc_vblank_end -= 1;
6219
6220                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6221                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6222                 else
6223                         vsyncshift = adjusted_mode->crtc_hsync_start -
6224                                 adjusted_mode->crtc_htotal / 2;
6225                 if (vsyncshift < 0)
6226                         vsyncshift += adjusted_mode->crtc_htotal;
6227         }
6228
6229         if (INTEL_INFO(dev)->gen > 3)
6230                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6231
6232         I915_WRITE(HTOTAL(cpu_transcoder),
6233                    (adjusted_mode->crtc_hdisplay - 1) |
6234                    ((adjusted_mode->crtc_htotal - 1) << 16));
6235         I915_WRITE(HBLANK(cpu_transcoder),
6236                    (adjusted_mode->crtc_hblank_start - 1) |
6237                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6238         I915_WRITE(HSYNC(cpu_transcoder),
6239                    (adjusted_mode->crtc_hsync_start - 1) |
6240                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6241
6242         I915_WRITE(VTOTAL(cpu_transcoder),
6243                    (adjusted_mode->crtc_vdisplay - 1) |
6244                    ((crtc_vtotal - 1) << 16));
6245         I915_WRITE(VBLANK(cpu_transcoder),
6246                    (adjusted_mode->crtc_vblank_start - 1) |
6247                    ((crtc_vblank_end - 1) << 16));
6248         I915_WRITE(VSYNC(cpu_transcoder),
6249                    (adjusted_mode->crtc_vsync_start - 1) |
6250                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6251
6252         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6253          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6254          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6255          * bits. */
6256         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6257             (pipe == PIPE_B || pipe == PIPE_C))
6258                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6259
6260         /* pipesrc controls the size that is scaled from, which should
6261          * always be the user's requested size.
6262          */
6263         I915_WRITE(PIPESRC(pipe),
6264                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6265                    (intel_crtc->config.pipe_src_h - 1));
6266 }
6267
6268 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6269                                    struct intel_crtc_config *pipe_config)
6270 {
6271         struct drm_device *dev = crtc->base.dev;
6272         struct drm_i915_private *dev_priv = dev->dev_private;
6273         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6274         uint32_t tmp;
6275
6276         tmp = I915_READ(HTOTAL(cpu_transcoder));
6277         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6278         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6279         tmp = I915_READ(HBLANK(cpu_transcoder));
6280         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6281         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6282         tmp = I915_READ(HSYNC(cpu_transcoder));
6283         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6284         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6285
6286         tmp = I915_READ(VTOTAL(cpu_transcoder));
6287         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6288         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6289         tmp = I915_READ(VBLANK(cpu_transcoder));
6290         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6291         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6292         tmp = I915_READ(VSYNC(cpu_transcoder));
6293         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6294         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6295
6296         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6297                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6298                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6299                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6300         }
6301
6302         tmp = I915_READ(PIPESRC(crtc->pipe));
6303         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6304         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6305
6306         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6307         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6308 }
6309
6310 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6311                                  struct intel_crtc_config *pipe_config)
6312 {
6313         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6314         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6315         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6316         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6317
6318         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6319         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6320         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6321         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6322
6323         mode->flags = pipe_config->adjusted_mode.flags;
6324
6325         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6326         mode->flags |= pipe_config->adjusted_mode.flags;
6327 }
6328
6329 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6330 {
6331         struct drm_device *dev = intel_crtc->base.dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         uint32_t pipeconf;
6334
6335         pipeconf = 0;
6336
6337         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6338             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6339                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6340
6341         if (intel_crtc->config.double_wide)
6342                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6343
6344         /* only g4x and later have fancy bpc/dither controls */
6345         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6346                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6347                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6348                         pipeconf |= PIPECONF_DITHER_EN |
6349                                     PIPECONF_DITHER_TYPE_SP;
6350
6351                 switch (intel_crtc->config.pipe_bpp) {
6352                 case 18:
6353                         pipeconf |= PIPECONF_6BPC;
6354                         break;
6355                 case 24:
6356                         pipeconf |= PIPECONF_8BPC;
6357                         break;
6358                 case 30:
6359                         pipeconf |= PIPECONF_10BPC;
6360                         break;
6361                 default:
6362                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6363                         BUG();
6364                 }
6365         }
6366
6367         if (HAS_PIPE_CXSR(dev)) {
6368                 if (intel_crtc->lowfreq_avail) {
6369                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6370                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6371                 } else {
6372                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6373                 }
6374         }
6375
6376         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6377                 if (INTEL_INFO(dev)->gen < 4 ||
6378                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6379                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6380                 else
6381                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6382         } else
6383                 pipeconf |= PIPECONF_PROGRESSIVE;
6384
6385         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6386                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6387
6388         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6389         POSTING_READ(PIPECONF(intel_crtc->pipe));
6390 }
6391
6392 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6393 {
6394         struct drm_device *dev = crtc->base.dev;
6395         struct drm_i915_private *dev_priv = dev->dev_private;
6396         int refclk, num_connectors = 0;
6397         intel_clock_t clock, reduced_clock;
6398         bool ok, has_reduced_clock = false;
6399         bool is_lvds = false, is_dsi = false;
6400         struct intel_encoder *encoder;
6401         const intel_limit_t *limit;
6402
6403         for_each_intel_encoder(dev, encoder) {
6404                 if (encoder->new_crtc != crtc)
6405                         continue;
6406
6407                 switch (encoder->type) {
6408                 case INTEL_OUTPUT_LVDS:
6409                         is_lvds = true;
6410                         break;
6411                 case INTEL_OUTPUT_DSI:
6412                         is_dsi = true;
6413                         break;
6414                 default:
6415                         break;
6416                 }
6417
6418                 num_connectors++;
6419         }
6420
6421         if (is_dsi)
6422                 return 0;
6423
6424         if (!crtc->new_config->clock_set) {
6425                 refclk = i9xx_get_refclk(crtc, num_connectors);
6426
6427                 /*
6428                  * Returns a set of divisors for the desired target clock with
6429                  * the given refclk, or FALSE.  The returned values represent
6430                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6431                  * 2) / p1 / p2.
6432                  */
6433                 limit = intel_limit(crtc, refclk);
6434                 ok = dev_priv->display.find_dpll(limit, crtc,
6435                                                  crtc->new_config->port_clock,
6436                                                  refclk, NULL, &clock);
6437                 if (!ok) {
6438                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6439                         return -EINVAL;
6440                 }
6441
6442                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6443                         /*
6444                          * Ensure we match the reduced clock's P to the target
6445                          * clock.  If the clocks don't match, we can't switch
6446                          * the display clock by using the FP0/FP1. In such case
6447                          * we will disable the LVDS downclock feature.
6448                          */
6449                         has_reduced_clock =
6450                                 dev_priv->display.find_dpll(limit, crtc,
6451                                                             dev_priv->lvds_downclock,
6452                                                             refclk, &clock,
6453                                                             &reduced_clock);
6454                 }
6455                 /* Compat-code for transition, will disappear. */
6456                 crtc->new_config->dpll.n = clock.n;
6457                 crtc->new_config->dpll.m1 = clock.m1;
6458                 crtc->new_config->dpll.m2 = clock.m2;
6459                 crtc->new_config->dpll.p1 = clock.p1;
6460                 crtc->new_config->dpll.p2 = clock.p2;
6461         }
6462
6463         if (IS_GEN2(dev)) {
6464                 i8xx_update_pll(crtc,
6465                                 has_reduced_clock ? &reduced_clock : NULL,
6466                                 num_connectors);
6467         } else if (IS_CHERRYVIEW(dev)) {
6468                 chv_update_pll(crtc, crtc->new_config);
6469         } else if (IS_VALLEYVIEW(dev)) {
6470                 vlv_update_pll(crtc, crtc->new_config);
6471         } else {
6472                 i9xx_update_pll(crtc,
6473                                 has_reduced_clock ? &reduced_clock : NULL,
6474                                 num_connectors);
6475         }
6476
6477         return 0;
6478 }
6479
6480 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6481                                  struct intel_crtc_config *pipe_config)
6482 {
6483         struct drm_device *dev = crtc->base.dev;
6484         struct drm_i915_private *dev_priv = dev->dev_private;
6485         uint32_t tmp;
6486
6487         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6488                 return;
6489
6490         tmp = I915_READ(PFIT_CONTROL);
6491         if (!(tmp & PFIT_ENABLE))
6492                 return;
6493
6494         /* Check whether the pfit is attached to our pipe. */
6495         if (INTEL_INFO(dev)->gen < 4) {
6496                 if (crtc->pipe != PIPE_B)
6497                         return;
6498         } else {
6499                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6500                         return;
6501         }
6502
6503         pipe_config->gmch_pfit.control = tmp;
6504         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6505         if (INTEL_INFO(dev)->gen < 5)
6506                 pipe_config->gmch_pfit.lvds_border_bits =
6507                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6508 }
6509
6510 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6511                                struct intel_crtc_config *pipe_config)
6512 {
6513         struct drm_device *dev = crtc->base.dev;
6514         struct drm_i915_private *dev_priv = dev->dev_private;
6515         int pipe = pipe_config->cpu_transcoder;
6516         intel_clock_t clock;
6517         u32 mdiv;
6518         int refclk = 100000;
6519
6520         /* In case of MIPI DPLL will not even be used */
6521         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6522                 return;
6523
6524         mutex_lock(&dev_priv->dpio_lock);
6525         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6526         mutex_unlock(&dev_priv->dpio_lock);
6527
6528         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6529         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6530         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6531         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6532         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6533
6534         vlv_clock(refclk, &clock);
6535
6536         /* clock.dot is the fast clock */
6537         pipe_config->port_clock = clock.dot / 5;
6538 }
6539
6540 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6541                                   struct intel_plane_config *plane_config)
6542 {
6543         struct drm_device *dev = crtc->base.dev;
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545         u32 val, base, offset;
6546         int pipe = crtc->pipe, plane = crtc->plane;
6547         int fourcc, pixel_format;
6548         int aligned_height;
6549
6550         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6551         if (!crtc->base.primary->fb) {
6552                 DRM_DEBUG_KMS("failed to alloc fb\n");
6553                 return;
6554         }
6555
6556         val = I915_READ(DSPCNTR(plane));
6557
6558         if (INTEL_INFO(dev)->gen >= 4)
6559                 if (val & DISPPLANE_TILED)
6560                         plane_config->tiled = true;
6561
6562         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6563         fourcc = intel_format_to_fourcc(pixel_format);
6564         crtc->base.primary->fb->pixel_format = fourcc;
6565         crtc->base.primary->fb->bits_per_pixel =
6566                 drm_format_plane_cpp(fourcc, 0) * 8;
6567
6568         if (INTEL_INFO(dev)->gen >= 4) {
6569                 if (plane_config->tiled)
6570                         offset = I915_READ(DSPTILEOFF(plane));
6571                 else
6572                         offset = I915_READ(DSPLINOFF(plane));
6573                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6574         } else {
6575                 base = I915_READ(DSPADDR(plane));
6576         }
6577         plane_config->base = base;
6578
6579         val = I915_READ(PIPESRC(pipe));
6580         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6581         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6582
6583         val = I915_READ(DSPSTRIDE(pipe));
6584         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6585
6586         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6587                                             plane_config->tiled);
6588
6589         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6590                                         aligned_height);
6591
6592         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6593                       pipe, plane, crtc->base.primary->fb->width,
6594                       crtc->base.primary->fb->height,
6595                       crtc->base.primary->fb->bits_per_pixel, base,
6596                       crtc->base.primary->fb->pitches[0],
6597                       plane_config->size);
6598
6599 }
6600
6601 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6602                                struct intel_crtc_config *pipe_config)
6603 {
6604         struct drm_device *dev = crtc->base.dev;
6605         struct drm_i915_private *dev_priv = dev->dev_private;
6606         int pipe = pipe_config->cpu_transcoder;
6607         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6608         intel_clock_t clock;
6609         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6610         int refclk = 100000;
6611
6612         mutex_lock(&dev_priv->dpio_lock);
6613         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6614         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6615         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6616         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6617         mutex_unlock(&dev_priv->dpio_lock);
6618
6619         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6620         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6621         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6622         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6623         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6624
6625         chv_clock(refclk, &clock);
6626
6627         /* clock.dot is the fast clock */
6628         pipe_config->port_clock = clock.dot / 5;
6629 }
6630
6631 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6632                                  struct intel_crtc_config *pipe_config)
6633 {
6634         struct drm_device *dev = crtc->base.dev;
6635         struct drm_i915_private *dev_priv = dev->dev_private;
6636         uint32_t tmp;
6637
6638         if (!intel_display_power_is_enabled(dev_priv,
6639                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6640                 return false;
6641
6642         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6643         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6644
6645         tmp = I915_READ(PIPECONF(crtc->pipe));
6646         if (!(tmp & PIPECONF_ENABLE))
6647                 return false;
6648
6649         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6650                 switch (tmp & PIPECONF_BPC_MASK) {
6651                 case PIPECONF_6BPC:
6652                         pipe_config->pipe_bpp = 18;
6653                         break;
6654                 case PIPECONF_8BPC:
6655                         pipe_config->pipe_bpp = 24;
6656                         break;
6657                 case PIPECONF_10BPC:
6658                         pipe_config->pipe_bpp = 30;
6659                         break;
6660                 default:
6661                         break;
6662                 }
6663         }
6664
6665         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6666                 pipe_config->limited_color_range = true;
6667
6668         if (INTEL_INFO(dev)->gen < 4)
6669                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6670
6671         intel_get_pipe_timings(crtc, pipe_config);
6672
6673         i9xx_get_pfit_config(crtc, pipe_config);
6674
6675         if (INTEL_INFO(dev)->gen >= 4) {
6676                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6677                 pipe_config->pixel_multiplier =
6678                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6679                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6680                 pipe_config->dpll_hw_state.dpll_md = tmp;
6681         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6682                 tmp = I915_READ(DPLL(crtc->pipe));
6683                 pipe_config->pixel_multiplier =
6684                         ((tmp & SDVO_MULTIPLIER_MASK)
6685                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6686         } else {
6687                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6688                  * port and will be fixed up in the encoder->get_config
6689                  * function. */
6690                 pipe_config->pixel_multiplier = 1;
6691         }
6692         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6693         if (!IS_VALLEYVIEW(dev)) {
6694                 /*
6695                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6696                  * on 830. Filter it out here so that we don't
6697                  * report errors due to that.
6698                  */
6699                 if (IS_I830(dev))
6700                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6701
6702                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6703                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6704         } else {
6705                 /* Mask out read-only status bits. */
6706                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6707                                                      DPLL_PORTC_READY_MASK |
6708                                                      DPLL_PORTB_READY_MASK);
6709         }
6710
6711         if (IS_CHERRYVIEW(dev))
6712                 chv_crtc_clock_get(crtc, pipe_config);
6713         else if (IS_VALLEYVIEW(dev))
6714                 vlv_crtc_clock_get(crtc, pipe_config);
6715         else
6716                 i9xx_crtc_clock_get(crtc, pipe_config);
6717
6718         return true;
6719 }
6720
6721 static void ironlake_init_pch_refclk(struct drm_device *dev)
6722 {
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         struct intel_encoder *encoder;
6725         u32 val, final;
6726         bool has_lvds = false;
6727         bool has_cpu_edp = false;
6728         bool has_panel = false;
6729         bool has_ck505 = false;
6730         bool can_ssc = false;
6731
6732         /* We need to take the global config into account */
6733         for_each_intel_encoder(dev, encoder) {
6734                 switch (encoder->type) {
6735                 case INTEL_OUTPUT_LVDS:
6736                         has_panel = true;
6737                         has_lvds = true;
6738                         break;
6739                 case INTEL_OUTPUT_EDP:
6740                         has_panel = true;
6741                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6742                                 has_cpu_edp = true;
6743                         break;
6744                 default:
6745                         break;
6746                 }
6747         }
6748
6749         if (HAS_PCH_IBX(dev)) {
6750                 has_ck505 = dev_priv->vbt.display_clock_mode;
6751                 can_ssc = has_ck505;
6752         } else {
6753                 has_ck505 = false;
6754                 can_ssc = true;
6755         }
6756
6757         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6758                       has_panel, has_lvds, has_ck505);
6759
6760         /* Ironlake: try to setup display ref clock before DPLL
6761          * enabling. This is only under driver's control after
6762          * PCH B stepping, previous chipset stepping should be
6763          * ignoring this setting.
6764          */
6765         val = I915_READ(PCH_DREF_CONTROL);
6766
6767         /* As we must carefully and slowly disable/enable each source in turn,
6768          * compute the final state we want first and check if we need to
6769          * make any changes at all.
6770          */
6771         final = val;
6772         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6773         if (has_ck505)
6774                 final |= DREF_NONSPREAD_CK505_ENABLE;
6775         else
6776                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6777
6778         final &= ~DREF_SSC_SOURCE_MASK;
6779         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6780         final &= ~DREF_SSC1_ENABLE;
6781
6782         if (has_panel) {
6783                 final |= DREF_SSC_SOURCE_ENABLE;
6784
6785                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6786                         final |= DREF_SSC1_ENABLE;
6787
6788                 if (has_cpu_edp) {
6789                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6790                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6791                         else
6792                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6793                 } else
6794                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6795         } else {
6796                 final |= DREF_SSC_SOURCE_DISABLE;
6797                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6798         }
6799
6800         if (final == val)
6801                 return;
6802
6803         /* Always enable nonspread source */
6804         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6805
6806         if (has_ck505)
6807                 val |= DREF_NONSPREAD_CK505_ENABLE;
6808         else
6809                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6810
6811         if (has_panel) {
6812                 val &= ~DREF_SSC_SOURCE_MASK;
6813                 val |= DREF_SSC_SOURCE_ENABLE;
6814
6815                 /* SSC must be turned on before enabling the CPU output  */
6816                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6817                         DRM_DEBUG_KMS("Using SSC on panel\n");
6818                         val |= DREF_SSC1_ENABLE;
6819                 } else
6820                         val &= ~DREF_SSC1_ENABLE;
6821
6822                 /* Get SSC going before enabling the outputs */
6823                 I915_WRITE(PCH_DREF_CONTROL, val);
6824                 POSTING_READ(PCH_DREF_CONTROL);
6825                 udelay(200);
6826
6827                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6828
6829                 /* Enable CPU source on CPU attached eDP */
6830                 if (has_cpu_edp) {
6831                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6832                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6833                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6834                         } else
6835                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6836                 } else
6837                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6838
6839                 I915_WRITE(PCH_DREF_CONTROL, val);
6840                 POSTING_READ(PCH_DREF_CONTROL);
6841                 udelay(200);
6842         } else {
6843                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6844
6845                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6846
6847                 /* Turn off CPU output */
6848                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6849
6850                 I915_WRITE(PCH_DREF_CONTROL, val);
6851                 POSTING_READ(PCH_DREF_CONTROL);
6852                 udelay(200);
6853
6854                 /* Turn off the SSC source */
6855                 val &= ~DREF_SSC_SOURCE_MASK;
6856                 val |= DREF_SSC_SOURCE_DISABLE;
6857
6858                 /* Turn off SSC1 */
6859                 val &= ~DREF_SSC1_ENABLE;
6860
6861                 I915_WRITE(PCH_DREF_CONTROL, val);
6862                 POSTING_READ(PCH_DREF_CONTROL);
6863                 udelay(200);
6864         }
6865
6866         BUG_ON(val != final);
6867 }
6868
6869 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6870 {
6871         uint32_t tmp;
6872
6873         tmp = I915_READ(SOUTH_CHICKEN2);
6874         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6875         I915_WRITE(SOUTH_CHICKEN2, tmp);
6876
6877         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6878                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6879                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6880
6881         tmp = I915_READ(SOUTH_CHICKEN2);
6882         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6883         I915_WRITE(SOUTH_CHICKEN2, tmp);
6884
6885         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6886                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6887                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6888 }
6889
6890 /* WaMPhyProgramming:hsw */
6891 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6892 {
6893         uint32_t tmp;
6894
6895         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6896         tmp &= ~(0xFF << 24);
6897         tmp |= (0x12 << 24);
6898         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6899
6900         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6901         tmp |= (1 << 11);
6902         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6903
6904         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6905         tmp |= (1 << 11);
6906         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6907
6908         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6909         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6910         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6911
6912         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6913         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6914         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6915
6916         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6917         tmp &= ~(7 << 13);
6918         tmp |= (5 << 13);
6919         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6920
6921         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6922         tmp &= ~(7 << 13);
6923         tmp |= (5 << 13);
6924         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6925
6926         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6927         tmp &= ~0xFF;
6928         tmp |= 0x1C;
6929         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6930
6931         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6932         tmp &= ~0xFF;
6933         tmp |= 0x1C;
6934         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6935
6936         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6937         tmp &= ~(0xFF << 16);
6938         tmp |= (0x1C << 16);
6939         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6940
6941         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6942         tmp &= ~(0xFF << 16);
6943         tmp |= (0x1C << 16);
6944         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6945
6946         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6947         tmp |= (1 << 27);
6948         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6949
6950         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6951         tmp |= (1 << 27);
6952         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6953
6954         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6955         tmp &= ~(0xF << 28);
6956         tmp |= (4 << 28);
6957         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6958
6959         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6960         tmp &= ~(0xF << 28);
6961         tmp |= (4 << 28);
6962         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6963 }
6964
6965 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6966  * Programming" based on the parameters passed:
6967  * - Sequence to enable CLKOUT_DP
6968  * - Sequence to enable CLKOUT_DP without spread
6969  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6970  */
6971 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6972                                  bool with_fdi)
6973 {
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         uint32_t reg, tmp;
6976
6977         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6978                 with_spread = true;
6979         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6980                  with_fdi, "LP PCH doesn't have FDI\n"))
6981                 with_fdi = false;
6982
6983         mutex_lock(&dev_priv->dpio_lock);
6984
6985         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6986         tmp &= ~SBI_SSCCTL_DISABLE;
6987         tmp |= SBI_SSCCTL_PATHALT;
6988         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6989
6990         udelay(24);
6991
6992         if (with_spread) {
6993                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994                 tmp &= ~SBI_SSCCTL_PATHALT;
6995                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6996
6997                 if (with_fdi) {
6998                         lpt_reset_fdi_mphy(dev_priv);
6999                         lpt_program_fdi_mphy(dev_priv);
7000                 }
7001         }
7002
7003         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7004                SBI_GEN0 : SBI_DBUFF0;
7005         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7006         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7007         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7008
7009         mutex_unlock(&dev_priv->dpio_lock);
7010 }
7011
7012 /* Sequence to disable CLKOUT_DP */
7013 static void lpt_disable_clkout_dp(struct drm_device *dev)
7014 {
7015         struct drm_i915_private *dev_priv = dev->dev_private;
7016         uint32_t reg, tmp;
7017
7018         mutex_lock(&dev_priv->dpio_lock);
7019
7020         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7021                SBI_GEN0 : SBI_DBUFF0;
7022         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7023         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7024         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7025
7026         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7027         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7028                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7029                         tmp |= SBI_SSCCTL_PATHALT;
7030                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7031                         udelay(32);
7032                 }
7033                 tmp |= SBI_SSCCTL_DISABLE;
7034                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7035         }
7036
7037         mutex_unlock(&dev_priv->dpio_lock);
7038 }
7039
7040 static void lpt_init_pch_refclk(struct drm_device *dev)
7041 {
7042         struct intel_encoder *encoder;
7043         bool has_vga = false;
7044
7045         for_each_intel_encoder(dev, encoder) {
7046                 switch (encoder->type) {
7047                 case INTEL_OUTPUT_ANALOG:
7048                         has_vga = true;
7049                         break;
7050                 default:
7051                         break;
7052                 }
7053         }
7054
7055         if (has_vga)
7056                 lpt_enable_clkout_dp(dev, true, true);
7057         else
7058                 lpt_disable_clkout_dp(dev);
7059 }
7060
7061 /*
7062  * Initialize reference clocks when the driver loads
7063  */
7064 void intel_init_pch_refclk(struct drm_device *dev)
7065 {
7066         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7067                 ironlake_init_pch_refclk(dev);
7068         else if (HAS_PCH_LPT(dev))
7069                 lpt_init_pch_refclk(dev);
7070 }
7071
7072 static int ironlake_get_refclk(struct drm_crtc *crtc)
7073 {
7074         struct drm_device *dev = crtc->dev;
7075         struct drm_i915_private *dev_priv = dev->dev_private;
7076         struct intel_encoder *encoder;
7077         int num_connectors = 0;
7078         bool is_lvds = false;
7079
7080         for_each_intel_encoder(dev, encoder) {
7081                 if (encoder->new_crtc != to_intel_crtc(crtc))
7082                         continue;
7083
7084                 switch (encoder->type) {
7085                 case INTEL_OUTPUT_LVDS:
7086                         is_lvds = true;
7087                         break;
7088                 default:
7089                         break;
7090                 }
7091                 num_connectors++;
7092         }
7093
7094         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7095                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7096                               dev_priv->vbt.lvds_ssc_freq);
7097                 return dev_priv->vbt.lvds_ssc_freq;
7098         }
7099
7100         return 120000;
7101 }
7102
7103 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7104 {
7105         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7107         int pipe = intel_crtc->pipe;
7108         uint32_t val;
7109
7110         val = 0;
7111
7112         switch (intel_crtc->config.pipe_bpp) {
7113         case 18:
7114                 val |= PIPECONF_6BPC;
7115                 break;
7116         case 24:
7117                 val |= PIPECONF_8BPC;
7118                 break;
7119         case 30:
7120                 val |= PIPECONF_10BPC;
7121                 break;
7122         case 36:
7123                 val |= PIPECONF_12BPC;
7124                 break;
7125         default:
7126                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7127                 BUG();
7128         }
7129
7130         if (intel_crtc->config.dither)
7131                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7132
7133         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7134                 val |= PIPECONF_INTERLACED_ILK;
7135         else
7136                 val |= PIPECONF_PROGRESSIVE;
7137
7138         if (intel_crtc->config.limited_color_range)
7139                 val |= PIPECONF_COLOR_RANGE_SELECT;
7140
7141         I915_WRITE(PIPECONF(pipe), val);
7142         POSTING_READ(PIPECONF(pipe));
7143 }
7144
7145 /*
7146  * Set up the pipe CSC unit.
7147  *
7148  * Currently only full range RGB to limited range RGB conversion
7149  * is supported, but eventually this should handle various
7150  * RGB<->YCbCr scenarios as well.
7151  */
7152 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7153 {
7154         struct drm_device *dev = crtc->dev;
7155         struct drm_i915_private *dev_priv = dev->dev_private;
7156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7157         int pipe = intel_crtc->pipe;
7158         uint16_t coeff = 0x7800; /* 1.0 */
7159
7160         /*
7161          * TODO: Check what kind of values actually come out of the pipe
7162          * with these coeff/postoff values and adjust to get the best
7163          * accuracy. Perhaps we even need to take the bpc value into
7164          * consideration.
7165          */
7166
7167         if (intel_crtc->config.limited_color_range)
7168                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7169
7170         /*
7171          * GY/GU and RY/RU should be the other way around according
7172          * to BSpec, but reality doesn't agree. Just set them up in
7173          * a way that results in the correct picture.
7174          */
7175         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7176         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7177
7178         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7179         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7180
7181         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7182         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7183
7184         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7185         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7186         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7187
7188         if (INTEL_INFO(dev)->gen > 6) {
7189                 uint16_t postoff = 0;
7190
7191                 if (intel_crtc->config.limited_color_range)
7192                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7193
7194                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7195                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7196                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7197
7198                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7199         } else {
7200                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7201
7202                 if (intel_crtc->config.limited_color_range)
7203                         mode |= CSC_BLACK_SCREEN_OFFSET;
7204
7205                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7206         }
7207 }
7208
7209 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7210 {
7211         struct drm_device *dev = crtc->dev;
7212         struct drm_i915_private *dev_priv = dev->dev_private;
7213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7214         enum pipe pipe = intel_crtc->pipe;
7215         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7216         uint32_t val;
7217
7218         val = 0;
7219
7220         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7221                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7222
7223         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7224                 val |= PIPECONF_INTERLACED_ILK;
7225         else
7226                 val |= PIPECONF_PROGRESSIVE;
7227
7228         I915_WRITE(PIPECONF(cpu_transcoder), val);
7229         POSTING_READ(PIPECONF(cpu_transcoder));
7230
7231         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7232         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7233
7234         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7235                 val = 0;
7236
7237                 switch (intel_crtc->config.pipe_bpp) {
7238                 case 18:
7239                         val |= PIPEMISC_DITHER_6_BPC;
7240                         break;
7241                 case 24:
7242                         val |= PIPEMISC_DITHER_8_BPC;
7243                         break;
7244                 case 30:
7245                         val |= PIPEMISC_DITHER_10_BPC;
7246                         break;
7247                 case 36:
7248                         val |= PIPEMISC_DITHER_12_BPC;
7249                         break;
7250                 default:
7251                         /* Case prevented by pipe_config_set_bpp. */
7252                         BUG();
7253                 }
7254
7255                 if (intel_crtc->config.dither)
7256                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7257
7258                 I915_WRITE(PIPEMISC(pipe), val);
7259         }
7260 }
7261
7262 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7263                                     intel_clock_t *clock,
7264                                     bool *has_reduced_clock,
7265                                     intel_clock_t *reduced_clock)
7266 {
7267         struct drm_device *dev = crtc->dev;
7268         struct drm_i915_private *dev_priv = dev->dev_private;
7269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270         int refclk;
7271         const intel_limit_t *limit;
7272         bool ret, is_lvds = false;
7273
7274         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7275
7276         refclk = ironlake_get_refclk(crtc);
7277
7278         /*
7279          * Returns a set of divisors for the desired target clock with the given
7280          * refclk, or FALSE.  The returned values represent the clock equation:
7281          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7282          */
7283         limit = intel_limit(intel_crtc, refclk);
7284         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7285                                           intel_crtc->new_config->port_clock,
7286                                           refclk, NULL, clock);
7287         if (!ret)
7288                 return false;
7289
7290         if (is_lvds && dev_priv->lvds_downclock_avail) {
7291                 /*
7292                  * Ensure we match the reduced clock's P to the target clock.
7293                  * If the clocks don't match, we can't switch the display clock
7294                  * by using the FP0/FP1. In such case we will disable the LVDS
7295                  * downclock feature.
7296                 */
7297                 *has_reduced_clock =
7298                         dev_priv->display.find_dpll(limit, intel_crtc,
7299                                                     dev_priv->lvds_downclock,
7300                                                     refclk, clock,
7301                                                     reduced_clock);
7302         }
7303
7304         return true;
7305 }
7306
7307 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7308 {
7309         /*
7310          * Account for spread spectrum to avoid
7311          * oversubscribing the link. Max center spread
7312          * is 2.5%; use 5% for safety's sake.
7313          */
7314         u32 bps = target_clock * bpp * 21 / 20;
7315         return DIV_ROUND_UP(bps, link_bw * 8);
7316 }
7317
7318 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7319 {
7320         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7321 }
7322
7323 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7324                                       u32 *fp,
7325                                       intel_clock_t *reduced_clock, u32 *fp2)
7326 {
7327         struct drm_crtc *crtc = &intel_crtc->base;
7328         struct drm_device *dev = crtc->dev;
7329         struct drm_i915_private *dev_priv = dev->dev_private;
7330         struct intel_encoder *intel_encoder;
7331         uint32_t dpll;
7332         int factor, num_connectors = 0;
7333         bool is_lvds = false, is_sdvo = false;
7334
7335         for_each_intel_encoder(dev, intel_encoder) {
7336                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7337                         continue;
7338
7339                 switch (intel_encoder->type) {
7340                 case INTEL_OUTPUT_LVDS:
7341                         is_lvds = true;
7342                         break;
7343                 case INTEL_OUTPUT_SDVO:
7344                 case INTEL_OUTPUT_HDMI:
7345                         is_sdvo = true;
7346                         break;
7347                 default:
7348                         break;
7349                 }
7350
7351                 num_connectors++;
7352         }
7353
7354         /* Enable autotuning of the PLL clock (if permissible) */
7355         factor = 21;
7356         if (is_lvds) {
7357                 if ((intel_panel_use_ssc(dev_priv) &&
7358                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7359                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7360                         factor = 25;
7361         } else if (intel_crtc->new_config->sdvo_tv_clock)
7362                 factor = 20;
7363
7364         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7365                 *fp |= FP_CB_TUNE;
7366
7367         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7368                 *fp2 |= FP_CB_TUNE;
7369
7370         dpll = 0;
7371
7372         if (is_lvds)
7373                 dpll |= DPLLB_MODE_LVDS;
7374         else
7375                 dpll |= DPLLB_MODE_DAC_SERIAL;
7376
7377         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7378                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7379
7380         if (is_sdvo)
7381                 dpll |= DPLL_SDVO_HIGH_SPEED;
7382         if (intel_crtc->new_config->has_dp_encoder)
7383                 dpll |= DPLL_SDVO_HIGH_SPEED;
7384
7385         /* compute bitmask from p1 value */
7386         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7387         /* also FPA1 */
7388         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7389
7390         switch (intel_crtc->new_config->dpll.p2) {
7391         case 5:
7392                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7393                 break;
7394         case 7:
7395                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7396                 break;
7397         case 10:
7398                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7399                 break;
7400         case 14:
7401                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7402                 break;
7403         }
7404
7405         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7406                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7407         else
7408                 dpll |= PLL_REF_INPUT_DREFCLK;
7409
7410         return dpll | DPLL_VCO_ENABLE;
7411 }
7412
7413 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7414 {
7415         struct drm_device *dev = crtc->base.dev;
7416         intel_clock_t clock, reduced_clock;
7417         u32 dpll = 0, fp = 0, fp2 = 0;
7418         bool ok, has_reduced_clock = false;
7419         bool is_lvds = false;
7420         struct intel_shared_dpll *pll;
7421
7422         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7423
7424         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7425              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7426
7427         ok = ironlake_compute_clocks(&crtc->base, &clock,
7428                                      &has_reduced_clock, &reduced_clock);
7429         if (!ok && !crtc->new_config->clock_set) {
7430                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7431                 return -EINVAL;
7432         }
7433         /* Compat-code for transition, will disappear. */
7434         if (!crtc->new_config->clock_set) {
7435                 crtc->new_config->dpll.n = clock.n;
7436                 crtc->new_config->dpll.m1 = clock.m1;
7437                 crtc->new_config->dpll.m2 = clock.m2;
7438                 crtc->new_config->dpll.p1 = clock.p1;
7439                 crtc->new_config->dpll.p2 = clock.p2;
7440         }
7441
7442         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7443         if (crtc->new_config->has_pch_encoder) {
7444                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7445                 if (has_reduced_clock)
7446                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7447
7448                 dpll = ironlake_compute_dpll(crtc,
7449                                              &fp, &reduced_clock,
7450                                              has_reduced_clock ? &fp2 : NULL);
7451
7452                 crtc->new_config->dpll_hw_state.dpll = dpll;
7453                 crtc->new_config->dpll_hw_state.fp0 = fp;
7454                 if (has_reduced_clock)
7455                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7456                 else
7457                         crtc->new_config->dpll_hw_state.fp1 = fp;
7458
7459                 pll = intel_get_shared_dpll(crtc);
7460                 if (pll == NULL) {
7461                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7462                                          pipe_name(crtc->pipe));
7463                         return -EINVAL;
7464                 }
7465         }
7466
7467         if (is_lvds && has_reduced_clock && i915.powersave)
7468                 crtc->lowfreq_avail = true;
7469         else
7470                 crtc->lowfreq_avail = false;
7471
7472         return 0;
7473 }
7474
7475 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7476                                          struct intel_link_m_n *m_n)
7477 {
7478         struct drm_device *dev = crtc->base.dev;
7479         struct drm_i915_private *dev_priv = dev->dev_private;
7480         enum pipe pipe = crtc->pipe;
7481
7482         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7483         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7484         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7485                 & ~TU_SIZE_MASK;
7486         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7487         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7488                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7489 }
7490
7491 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7492                                          enum transcoder transcoder,
7493                                          struct intel_link_m_n *m_n,
7494                                          struct intel_link_m_n *m2_n2)
7495 {
7496         struct drm_device *dev = crtc->base.dev;
7497         struct drm_i915_private *dev_priv = dev->dev_private;
7498         enum pipe pipe = crtc->pipe;
7499
7500         if (INTEL_INFO(dev)->gen >= 5) {
7501                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7502                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7503                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7504                         & ~TU_SIZE_MASK;
7505                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7506                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7507                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7508                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7509                  * gen < 8) and if DRRS is supported (to make sure the
7510                  * registers are not unnecessarily read).
7511                  */
7512                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7513                         crtc->config.has_drrs) {
7514                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7515                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7516                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7517                                         & ~TU_SIZE_MASK;
7518                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7519                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7520                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7521                 }
7522         } else {
7523                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7524                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7525                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7526                         & ~TU_SIZE_MASK;
7527                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7528                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7529                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7530         }
7531 }
7532
7533 void intel_dp_get_m_n(struct intel_crtc *crtc,
7534                       struct intel_crtc_config *pipe_config)
7535 {
7536         if (crtc->config.has_pch_encoder)
7537                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7538         else
7539                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7540                                              &pipe_config->dp_m_n,
7541                                              &pipe_config->dp_m2_n2);
7542 }
7543
7544 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7545                                         struct intel_crtc_config *pipe_config)
7546 {
7547         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7548                                      &pipe_config->fdi_m_n, NULL);
7549 }
7550
7551 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7552                                      struct intel_crtc_config *pipe_config)
7553 {
7554         struct drm_device *dev = crtc->base.dev;
7555         struct drm_i915_private *dev_priv = dev->dev_private;
7556         uint32_t tmp;
7557
7558         tmp = I915_READ(PF_CTL(crtc->pipe));
7559
7560         if (tmp & PF_ENABLE) {
7561                 pipe_config->pch_pfit.enabled = true;
7562                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7563                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7564
7565                 /* We currently do not free assignements of panel fitters on
7566                  * ivb/hsw (since we don't use the higher upscaling modes which
7567                  * differentiates them) so just WARN about this case for now. */
7568                 if (IS_GEN7(dev)) {
7569                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7570                                 PF_PIPE_SEL_IVB(crtc->pipe));
7571                 }
7572         }
7573 }
7574
7575 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7576                                       struct intel_plane_config *plane_config)
7577 {
7578         struct drm_device *dev = crtc->base.dev;
7579         struct drm_i915_private *dev_priv = dev->dev_private;
7580         u32 val, base, offset;
7581         int pipe = crtc->pipe, plane = crtc->plane;
7582         int fourcc, pixel_format;
7583         int aligned_height;
7584
7585         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7586         if (!crtc->base.primary->fb) {
7587                 DRM_DEBUG_KMS("failed to alloc fb\n");
7588                 return;
7589         }
7590
7591         val = I915_READ(DSPCNTR(plane));
7592
7593         if (INTEL_INFO(dev)->gen >= 4)
7594                 if (val & DISPPLANE_TILED)
7595                         plane_config->tiled = true;
7596
7597         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7598         fourcc = intel_format_to_fourcc(pixel_format);
7599         crtc->base.primary->fb->pixel_format = fourcc;
7600         crtc->base.primary->fb->bits_per_pixel =
7601                 drm_format_plane_cpp(fourcc, 0) * 8;
7602
7603         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7604         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7605                 offset = I915_READ(DSPOFFSET(plane));
7606         } else {
7607                 if (plane_config->tiled)
7608                         offset = I915_READ(DSPTILEOFF(plane));
7609                 else
7610                         offset = I915_READ(DSPLINOFF(plane));
7611         }
7612         plane_config->base = base;
7613
7614         val = I915_READ(PIPESRC(pipe));
7615         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7616         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7617
7618         val = I915_READ(DSPSTRIDE(pipe));
7619         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7620
7621         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7622                                             plane_config->tiled);
7623
7624         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7625                                         aligned_height);
7626
7627         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7628                       pipe, plane, crtc->base.primary->fb->width,
7629                       crtc->base.primary->fb->height,
7630                       crtc->base.primary->fb->bits_per_pixel, base,
7631                       crtc->base.primary->fb->pitches[0],
7632                       plane_config->size);
7633 }
7634
7635 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7636                                      struct intel_crtc_config *pipe_config)
7637 {
7638         struct drm_device *dev = crtc->base.dev;
7639         struct drm_i915_private *dev_priv = dev->dev_private;
7640         uint32_t tmp;
7641
7642         if (!intel_display_power_is_enabled(dev_priv,
7643                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7644                 return false;
7645
7646         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7647         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7648
7649         tmp = I915_READ(PIPECONF(crtc->pipe));
7650         if (!(tmp & PIPECONF_ENABLE))
7651                 return false;
7652
7653         switch (tmp & PIPECONF_BPC_MASK) {
7654         case PIPECONF_6BPC:
7655                 pipe_config->pipe_bpp = 18;
7656                 break;
7657         case PIPECONF_8BPC:
7658                 pipe_config->pipe_bpp = 24;
7659                 break;
7660         case PIPECONF_10BPC:
7661                 pipe_config->pipe_bpp = 30;
7662                 break;
7663         case PIPECONF_12BPC:
7664                 pipe_config->pipe_bpp = 36;
7665                 break;
7666         default:
7667                 break;
7668         }
7669
7670         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7671                 pipe_config->limited_color_range = true;
7672
7673         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7674                 struct intel_shared_dpll *pll;
7675
7676                 pipe_config->has_pch_encoder = true;
7677
7678                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7679                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7680                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7681
7682                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7683
7684                 if (HAS_PCH_IBX(dev_priv->dev)) {
7685                         pipe_config->shared_dpll =
7686                                 (enum intel_dpll_id) crtc->pipe;
7687                 } else {
7688                         tmp = I915_READ(PCH_DPLL_SEL);
7689                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7690                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7691                         else
7692                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7693                 }
7694
7695                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7696
7697                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7698                                            &pipe_config->dpll_hw_state));
7699
7700                 tmp = pipe_config->dpll_hw_state.dpll;
7701                 pipe_config->pixel_multiplier =
7702                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7703                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7704
7705                 ironlake_pch_clock_get(crtc, pipe_config);
7706         } else {
7707                 pipe_config->pixel_multiplier = 1;
7708         }
7709
7710         intel_get_pipe_timings(crtc, pipe_config);
7711
7712         ironlake_get_pfit_config(crtc, pipe_config);
7713
7714         return true;
7715 }
7716
7717 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7718 {
7719         struct drm_device *dev = dev_priv->dev;
7720         struct intel_crtc *crtc;
7721
7722         for_each_intel_crtc(dev, crtc)
7723                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7724                      pipe_name(crtc->pipe));
7725
7726         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7727         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7728         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7729         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7730         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7731         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7732              "CPU PWM1 enabled\n");
7733         if (IS_HASWELL(dev))
7734                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7735                      "CPU PWM2 enabled\n");
7736         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7737              "PCH PWM1 enabled\n");
7738         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7739              "Utility pin enabled\n");
7740         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7741
7742         /*
7743          * In theory we can still leave IRQs enabled, as long as only the HPD
7744          * interrupts remain enabled. We used to check for that, but since it's
7745          * gen-specific and since we only disable LCPLL after we fully disable
7746          * the interrupts, the check below should be enough.
7747          */
7748         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7749 }
7750
7751 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7752 {
7753         struct drm_device *dev = dev_priv->dev;
7754
7755         if (IS_HASWELL(dev))
7756                 return I915_READ(D_COMP_HSW);
7757         else
7758                 return I915_READ(D_COMP_BDW);
7759 }
7760
7761 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7762 {
7763         struct drm_device *dev = dev_priv->dev;
7764
7765         if (IS_HASWELL(dev)) {
7766                 mutex_lock(&dev_priv->rps.hw_lock);
7767                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7768                                             val))
7769                         DRM_ERROR("Failed to write to D_COMP\n");
7770                 mutex_unlock(&dev_priv->rps.hw_lock);
7771         } else {
7772                 I915_WRITE(D_COMP_BDW, val);
7773                 POSTING_READ(D_COMP_BDW);
7774         }
7775 }
7776
7777 /*
7778  * This function implements pieces of two sequences from BSpec:
7779  * - Sequence for display software to disable LCPLL
7780  * - Sequence for display software to allow package C8+
7781  * The steps implemented here are just the steps that actually touch the LCPLL
7782  * register. Callers should take care of disabling all the display engine
7783  * functions, doing the mode unset, fixing interrupts, etc.
7784  */
7785 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7786                               bool switch_to_fclk, bool allow_power_down)
7787 {
7788         uint32_t val;
7789
7790         assert_can_disable_lcpll(dev_priv);
7791
7792         val = I915_READ(LCPLL_CTL);
7793
7794         if (switch_to_fclk) {
7795                 val |= LCPLL_CD_SOURCE_FCLK;
7796                 I915_WRITE(LCPLL_CTL, val);
7797
7798                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7799                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7800                         DRM_ERROR("Switching to FCLK failed\n");
7801
7802                 val = I915_READ(LCPLL_CTL);
7803         }
7804
7805         val |= LCPLL_PLL_DISABLE;
7806         I915_WRITE(LCPLL_CTL, val);
7807         POSTING_READ(LCPLL_CTL);
7808
7809         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7810                 DRM_ERROR("LCPLL still locked\n");
7811
7812         val = hsw_read_dcomp(dev_priv);
7813         val |= D_COMP_COMP_DISABLE;
7814         hsw_write_dcomp(dev_priv, val);
7815         ndelay(100);
7816
7817         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7818                      1))
7819                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7820
7821         if (allow_power_down) {
7822                 val = I915_READ(LCPLL_CTL);
7823                 val |= LCPLL_POWER_DOWN_ALLOW;
7824                 I915_WRITE(LCPLL_CTL, val);
7825                 POSTING_READ(LCPLL_CTL);
7826         }
7827 }
7828
7829 /*
7830  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7831  * source.
7832  */
7833 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7834 {
7835         uint32_t val;
7836
7837         val = I915_READ(LCPLL_CTL);
7838
7839         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7840                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7841                 return;
7842
7843         /*
7844          * Make sure we're not on PC8 state before disabling PC8, otherwise
7845          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7846          *
7847          * The other problem is that hsw_restore_lcpll() is called as part of
7848          * the runtime PM resume sequence, so we can't just call
7849          * gen6_gt_force_wake_get() because that function calls
7850          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7851          * while we are on the resume sequence. So to solve this problem we have
7852          * to call special forcewake code that doesn't touch runtime PM and
7853          * doesn't enable the forcewake delayed work.
7854          */
7855         spin_lock_irq(&dev_priv->uncore.lock);
7856         if (dev_priv->uncore.forcewake_count++ == 0)
7857                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7858         spin_unlock_irq(&dev_priv->uncore.lock);
7859
7860         if (val & LCPLL_POWER_DOWN_ALLOW) {
7861                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7862                 I915_WRITE(LCPLL_CTL, val);
7863                 POSTING_READ(LCPLL_CTL);
7864         }
7865
7866         val = hsw_read_dcomp(dev_priv);
7867         val |= D_COMP_COMP_FORCE;
7868         val &= ~D_COMP_COMP_DISABLE;
7869         hsw_write_dcomp(dev_priv, val);
7870
7871         val = I915_READ(LCPLL_CTL);
7872         val &= ~LCPLL_PLL_DISABLE;
7873         I915_WRITE(LCPLL_CTL, val);
7874
7875         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7876                 DRM_ERROR("LCPLL not locked yet\n");
7877
7878         if (val & LCPLL_CD_SOURCE_FCLK) {
7879                 val = I915_READ(LCPLL_CTL);
7880                 val &= ~LCPLL_CD_SOURCE_FCLK;
7881                 I915_WRITE(LCPLL_CTL, val);
7882
7883                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7884                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7885                         DRM_ERROR("Switching back to LCPLL failed\n");
7886         }
7887
7888         /* See the big comment above. */
7889         spin_lock_irq(&dev_priv->uncore.lock);
7890         if (--dev_priv->uncore.forcewake_count == 0)
7891                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7892         spin_unlock_irq(&dev_priv->uncore.lock);
7893 }
7894
7895 /*
7896  * Package states C8 and deeper are really deep PC states that can only be
7897  * reached when all the devices on the system allow it, so even if the graphics
7898  * device allows PC8+, it doesn't mean the system will actually get to these
7899  * states. Our driver only allows PC8+ when going into runtime PM.
7900  *
7901  * The requirements for PC8+ are that all the outputs are disabled, the power
7902  * well is disabled and most interrupts are disabled, and these are also
7903  * requirements for runtime PM. When these conditions are met, we manually do
7904  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7905  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7906  * hang the machine.
7907  *
7908  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7909  * the state of some registers, so when we come back from PC8+ we need to
7910  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7911  * need to take care of the registers kept by RC6. Notice that this happens even
7912  * if we don't put the device in PCI D3 state (which is what currently happens
7913  * because of the runtime PM support).
7914  *
7915  * For more, read "Display Sequences for Package C8" on the hardware
7916  * documentation.
7917  */
7918 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7919 {
7920         struct drm_device *dev = dev_priv->dev;
7921         uint32_t val;
7922
7923         DRM_DEBUG_KMS("Enabling package C8+\n");
7924
7925         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7926                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7927                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7928                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7929         }
7930
7931         lpt_disable_clkout_dp(dev);
7932         hsw_disable_lcpll(dev_priv, true, true);
7933 }
7934
7935 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7936 {
7937         struct drm_device *dev = dev_priv->dev;
7938         uint32_t val;
7939
7940         DRM_DEBUG_KMS("Disabling package C8+\n");
7941
7942         hsw_restore_lcpll(dev_priv);
7943         lpt_init_pch_refclk(dev);
7944
7945         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7946                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7947                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7948                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7949         }
7950
7951         intel_prepare_ddi(dev);
7952 }
7953
7954 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7955 {
7956         if (!intel_ddi_pll_select(crtc))
7957                 return -EINVAL;
7958
7959         crtc->lowfreq_avail = false;
7960
7961         return 0;
7962 }
7963
7964 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7965                                 enum port port,
7966                                 struct intel_crtc_config *pipe_config)
7967 {
7968         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7969
7970         switch (pipe_config->ddi_pll_sel) {
7971         case PORT_CLK_SEL_WRPLL1:
7972                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7973                 break;
7974         case PORT_CLK_SEL_WRPLL2:
7975                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7976                 break;
7977         }
7978 }
7979
7980 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7981                                        struct intel_crtc_config *pipe_config)
7982 {
7983         struct drm_device *dev = crtc->base.dev;
7984         struct drm_i915_private *dev_priv = dev->dev_private;
7985         struct intel_shared_dpll *pll;
7986         enum port port;
7987         uint32_t tmp;
7988
7989         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7990
7991         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7992
7993         haswell_get_ddi_pll(dev_priv, port, pipe_config);
7994
7995         if (pipe_config->shared_dpll >= 0) {
7996                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7997
7998                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7999                                            &pipe_config->dpll_hw_state));
8000         }
8001
8002         /*
8003          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8004          * DDI E. So just check whether this pipe is wired to DDI E and whether
8005          * the PCH transcoder is on.
8006          */
8007         if (INTEL_INFO(dev)->gen < 9 &&
8008             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8009                 pipe_config->has_pch_encoder = true;
8010
8011                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8012                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8013                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8014
8015                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8016         }
8017 }
8018
8019 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8020                                     struct intel_crtc_config *pipe_config)
8021 {
8022         struct drm_device *dev = crtc->base.dev;
8023         struct drm_i915_private *dev_priv = dev->dev_private;
8024         enum intel_display_power_domain pfit_domain;
8025         uint32_t tmp;
8026
8027         if (!intel_display_power_is_enabled(dev_priv,
8028                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8029                 return false;
8030
8031         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8032         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8033
8034         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8035         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8036                 enum pipe trans_edp_pipe;
8037                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8038                 default:
8039                         WARN(1, "unknown pipe linked to edp transcoder\n");
8040                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8041                 case TRANS_DDI_EDP_INPUT_A_ON:
8042                         trans_edp_pipe = PIPE_A;
8043                         break;
8044                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8045                         trans_edp_pipe = PIPE_B;
8046                         break;
8047                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8048                         trans_edp_pipe = PIPE_C;
8049                         break;
8050                 }
8051
8052                 if (trans_edp_pipe == crtc->pipe)
8053                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8054         }
8055
8056         if (!intel_display_power_is_enabled(dev_priv,
8057                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8058                 return false;
8059
8060         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8061         if (!(tmp & PIPECONF_ENABLE))
8062                 return false;
8063
8064         haswell_get_ddi_port_state(crtc, pipe_config);
8065
8066         intel_get_pipe_timings(crtc, pipe_config);
8067
8068         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8069         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8070                 ironlake_get_pfit_config(crtc, pipe_config);
8071
8072         if (IS_HASWELL(dev))
8073                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8074                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8075
8076         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8077                 pipe_config->pixel_multiplier =
8078                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8079         } else {
8080                 pipe_config->pixel_multiplier = 1;
8081         }
8082
8083         return true;
8084 }
8085
8086 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8087 {
8088         struct drm_device *dev = crtc->dev;
8089         struct drm_i915_private *dev_priv = dev->dev_private;
8090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8091         uint32_t cntl = 0, size = 0;
8092
8093         if (base) {
8094                 unsigned int width = intel_crtc->cursor_width;
8095                 unsigned int height = intel_crtc->cursor_height;
8096                 unsigned int stride = roundup_pow_of_two(width) * 4;
8097
8098                 switch (stride) {
8099                 default:
8100                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8101                                   width, stride);
8102                         stride = 256;
8103                         /* fallthrough */
8104                 case 256:
8105                 case 512:
8106                 case 1024:
8107                 case 2048:
8108                         break;
8109                 }
8110
8111                 cntl |= CURSOR_ENABLE |
8112                         CURSOR_GAMMA_ENABLE |
8113                         CURSOR_FORMAT_ARGB |
8114                         CURSOR_STRIDE(stride);
8115
8116                 size = (height << 12) | width;
8117         }
8118
8119         if (intel_crtc->cursor_cntl != 0 &&
8120             (intel_crtc->cursor_base != base ||
8121              intel_crtc->cursor_size != size ||
8122              intel_crtc->cursor_cntl != cntl)) {
8123                 /* On these chipsets we can only modify the base/size/stride
8124                  * whilst the cursor is disabled.
8125                  */
8126                 I915_WRITE(_CURACNTR, 0);
8127                 POSTING_READ(_CURACNTR);
8128                 intel_crtc->cursor_cntl = 0;
8129         }
8130
8131         if (intel_crtc->cursor_base != base) {
8132                 I915_WRITE(_CURABASE, base);
8133                 intel_crtc->cursor_base = base;
8134         }
8135
8136         if (intel_crtc->cursor_size != size) {
8137                 I915_WRITE(CURSIZE, size);
8138                 intel_crtc->cursor_size = size;
8139         }
8140
8141         if (intel_crtc->cursor_cntl != cntl) {
8142                 I915_WRITE(_CURACNTR, cntl);
8143                 POSTING_READ(_CURACNTR);
8144                 intel_crtc->cursor_cntl = cntl;
8145         }
8146 }
8147
8148 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8149 {
8150         struct drm_device *dev = crtc->dev;
8151         struct drm_i915_private *dev_priv = dev->dev_private;
8152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8153         int pipe = intel_crtc->pipe;
8154         uint32_t cntl;
8155
8156         cntl = 0;
8157         if (base) {
8158                 cntl = MCURSOR_GAMMA_ENABLE;
8159                 switch (intel_crtc->cursor_width) {
8160                         case 64:
8161                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8162                                 break;
8163                         case 128:
8164                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8165                                 break;
8166                         case 256:
8167                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8168                                 break;
8169                         default:
8170                                 WARN_ON(1);
8171                                 return;
8172                 }
8173                 cntl |= pipe << 28; /* Connect to correct pipe */
8174
8175                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8176                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8177         }
8178
8179         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8180                 cntl |= CURSOR_ROTATE_180;
8181
8182         if (intel_crtc->cursor_cntl != cntl) {
8183                 I915_WRITE(CURCNTR(pipe), cntl);
8184                 POSTING_READ(CURCNTR(pipe));
8185                 intel_crtc->cursor_cntl = cntl;
8186         }
8187
8188         /* and commit changes on next vblank */
8189         I915_WRITE(CURBASE(pipe), base);
8190         POSTING_READ(CURBASE(pipe));
8191
8192         intel_crtc->cursor_base = base;
8193 }
8194
8195 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8196 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8197                                      bool on)
8198 {
8199         struct drm_device *dev = crtc->dev;
8200         struct drm_i915_private *dev_priv = dev->dev_private;
8201         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8202         int pipe = intel_crtc->pipe;
8203         int x = crtc->cursor_x;
8204         int y = crtc->cursor_y;
8205         u32 base = 0, pos = 0;
8206
8207         if (on)
8208                 base = intel_crtc->cursor_addr;
8209
8210         if (x >= intel_crtc->config.pipe_src_w)
8211                 base = 0;
8212
8213         if (y >= intel_crtc->config.pipe_src_h)
8214                 base = 0;
8215
8216         if (x < 0) {
8217                 if (x + intel_crtc->cursor_width <= 0)
8218                         base = 0;
8219
8220                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8221                 x = -x;
8222         }
8223         pos |= x << CURSOR_X_SHIFT;
8224
8225         if (y < 0) {
8226                 if (y + intel_crtc->cursor_height <= 0)
8227                         base = 0;
8228
8229                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8230                 y = -y;
8231         }
8232         pos |= y << CURSOR_Y_SHIFT;
8233
8234         if (base == 0 && intel_crtc->cursor_base == 0)
8235                 return;
8236
8237         I915_WRITE(CURPOS(pipe), pos);
8238
8239         /* ILK+ do this automagically */
8240         if (HAS_GMCH_DISPLAY(dev) &&
8241                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8242                 base += (intel_crtc->cursor_height *
8243                         intel_crtc->cursor_width - 1) * 4;
8244         }
8245
8246         if (IS_845G(dev) || IS_I865G(dev))
8247                 i845_update_cursor(crtc, base);
8248         else
8249                 i9xx_update_cursor(crtc, base);
8250 }
8251
8252 static bool cursor_size_ok(struct drm_device *dev,
8253                            uint32_t width, uint32_t height)
8254 {
8255         if (width == 0 || height == 0)
8256                 return false;
8257
8258         /*
8259          * 845g/865g are special in that they are only limited by
8260          * the width of their cursors, the height is arbitrary up to
8261          * the precision of the register. Everything else requires
8262          * square cursors, limited to a few power-of-two sizes.
8263          */
8264         if (IS_845G(dev) || IS_I865G(dev)) {
8265                 if ((width & 63) != 0)
8266                         return false;
8267
8268                 if (width > (IS_845G(dev) ? 64 : 512))
8269                         return false;
8270
8271                 if (height > 1023)
8272                         return false;
8273         } else {
8274                 switch (width | height) {
8275                 case 256:
8276                 case 128:
8277                         if (IS_GEN2(dev))
8278                                 return false;
8279                 case 64:
8280                         break;
8281                 default:
8282                         return false;
8283                 }
8284         }
8285
8286         return true;
8287 }
8288
8289 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8290                                      struct drm_i915_gem_object *obj,
8291                                      uint32_t width, uint32_t height)
8292 {
8293         struct drm_device *dev = crtc->dev;
8294         struct drm_i915_private *dev_priv = dev->dev_private;
8295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8296         enum pipe pipe = intel_crtc->pipe;
8297         unsigned old_width;
8298         uint32_t addr;
8299         int ret;
8300
8301         /* if we want to turn off the cursor ignore width and height */
8302         if (!obj) {
8303                 DRM_DEBUG_KMS("cursor off\n");
8304                 addr = 0;
8305                 mutex_lock(&dev->struct_mutex);
8306                 goto finish;
8307         }
8308
8309         /* we only need to pin inside GTT if cursor is non-phy */
8310         mutex_lock(&dev->struct_mutex);
8311         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8312                 unsigned alignment;
8313
8314                 /*
8315                  * Global gtt pte registers are special registers which actually
8316                  * forward writes to a chunk of system memory. Which means that
8317                  * there is no risk that the register values disappear as soon
8318                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8319                  * only the pin/unpin/fence and not more.
8320                  */
8321                 intel_runtime_pm_get(dev_priv);
8322
8323                 /* Note that the w/a also requires 2 PTE of padding following
8324                  * the bo. We currently fill all unused PTE with the shadow
8325                  * page and so we should always have valid PTE following the
8326                  * cursor preventing the VT-d warning.
8327                  */
8328                 alignment = 0;
8329                 if (need_vtd_wa(dev))
8330                         alignment = 64*1024;
8331
8332                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8333                 if (ret) {
8334                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8335                         intel_runtime_pm_put(dev_priv);
8336                         goto fail_locked;
8337                 }
8338
8339                 ret = i915_gem_object_put_fence(obj);
8340                 if (ret) {
8341                         DRM_DEBUG_KMS("failed to release fence for cursor");
8342                         intel_runtime_pm_put(dev_priv);
8343                         goto fail_unpin;
8344                 }
8345
8346                 addr = i915_gem_obj_ggtt_offset(obj);
8347
8348                 intel_runtime_pm_put(dev_priv);
8349         } else {
8350                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8351                 ret = i915_gem_object_attach_phys(obj, align);
8352                 if (ret) {
8353                         DRM_DEBUG_KMS("failed to attach phys object\n");
8354                         goto fail_locked;
8355                 }
8356                 addr = obj->phys_handle->busaddr;
8357         }
8358
8359  finish:
8360         if (intel_crtc->cursor_bo) {
8361                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8362                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8363         }
8364
8365         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8366                           INTEL_FRONTBUFFER_CURSOR(pipe));
8367         mutex_unlock(&dev->struct_mutex);
8368
8369         old_width = intel_crtc->cursor_width;
8370
8371         intel_crtc->cursor_addr = addr;
8372         intel_crtc->cursor_bo = obj;
8373         intel_crtc->cursor_width = width;
8374         intel_crtc->cursor_height = height;
8375
8376         if (intel_crtc->active) {
8377                 if (old_width != width)
8378                         intel_update_watermarks(crtc);
8379                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8380
8381                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8382         }
8383
8384         return 0;
8385 fail_unpin:
8386         i915_gem_object_unpin_from_display_plane(obj);
8387 fail_locked:
8388         mutex_unlock(&dev->struct_mutex);
8389         return ret;
8390 }
8391
8392 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8393                                  u16 *blue, uint32_t start, uint32_t size)
8394 {
8395         int end = (start + size > 256) ? 256 : start + size, i;
8396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8397
8398         for (i = start; i < end; i++) {
8399                 intel_crtc->lut_r[i] = red[i] >> 8;
8400                 intel_crtc->lut_g[i] = green[i] >> 8;
8401                 intel_crtc->lut_b[i] = blue[i] >> 8;
8402         }
8403
8404         intel_crtc_load_lut(crtc);
8405 }
8406
8407 /* VESA 640x480x72Hz mode to set on the pipe */
8408 static struct drm_display_mode load_detect_mode = {
8409         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8410                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8411 };
8412
8413 struct drm_framebuffer *
8414 __intel_framebuffer_create(struct drm_device *dev,
8415                            struct drm_mode_fb_cmd2 *mode_cmd,
8416                            struct drm_i915_gem_object *obj)
8417 {
8418         struct intel_framebuffer *intel_fb;
8419         int ret;
8420
8421         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8422         if (!intel_fb) {
8423                 drm_gem_object_unreference_unlocked(&obj->base);
8424                 return ERR_PTR(-ENOMEM);
8425         }
8426
8427         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8428         if (ret)
8429                 goto err;
8430
8431         return &intel_fb->base;
8432 err:
8433         drm_gem_object_unreference_unlocked(&obj->base);
8434         kfree(intel_fb);
8435
8436         return ERR_PTR(ret);
8437 }
8438
8439 static struct drm_framebuffer *
8440 intel_framebuffer_create(struct drm_device *dev,
8441                          struct drm_mode_fb_cmd2 *mode_cmd,
8442                          struct drm_i915_gem_object *obj)
8443 {
8444         struct drm_framebuffer *fb;
8445         int ret;
8446
8447         ret = i915_mutex_lock_interruptible(dev);
8448         if (ret)
8449                 return ERR_PTR(ret);
8450         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8451         mutex_unlock(&dev->struct_mutex);
8452
8453         return fb;
8454 }
8455
8456 static u32
8457 intel_framebuffer_pitch_for_width(int width, int bpp)
8458 {
8459         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8460         return ALIGN(pitch, 64);
8461 }
8462
8463 static u32
8464 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8465 {
8466         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8467         return PAGE_ALIGN(pitch * mode->vdisplay);
8468 }
8469
8470 static struct drm_framebuffer *
8471 intel_framebuffer_create_for_mode(struct drm_device *dev,
8472                                   struct drm_display_mode *mode,
8473                                   int depth, int bpp)
8474 {
8475         struct drm_i915_gem_object *obj;
8476         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8477
8478         obj = i915_gem_alloc_object(dev,
8479                                     intel_framebuffer_size_for_mode(mode, bpp));
8480         if (obj == NULL)
8481                 return ERR_PTR(-ENOMEM);
8482
8483         mode_cmd.width = mode->hdisplay;
8484         mode_cmd.height = mode->vdisplay;
8485         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8486                                                                 bpp);
8487         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8488
8489         return intel_framebuffer_create(dev, &mode_cmd, obj);
8490 }
8491
8492 static struct drm_framebuffer *
8493 mode_fits_in_fbdev(struct drm_device *dev,
8494                    struct drm_display_mode *mode)
8495 {
8496 #ifdef CONFIG_DRM_I915_FBDEV
8497         struct drm_i915_private *dev_priv = dev->dev_private;
8498         struct drm_i915_gem_object *obj;
8499         struct drm_framebuffer *fb;
8500
8501         if (!dev_priv->fbdev)
8502                 return NULL;
8503
8504         if (!dev_priv->fbdev->fb)
8505                 return NULL;
8506
8507         obj = dev_priv->fbdev->fb->obj;
8508         BUG_ON(!obj);
8509
8510         fb = &dev_priv->fbdev->fb->base;
8511         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8512                                                                fb->bits_per_pixel))
8513                 return NULL;
8514
8515         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8516                 return NULL;
8517
8518         return fb;
8519 #else
8520         return NULL;
8521 #endif
8522 }
8523
8524 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8525                                 struct drm_display_mode *mode,
8526                                 struct intel_load_detect_pipe *old,
8527                                 struct drm_modeset_acquire_ctx *ctx)
8528 {
8529         struct intel_crtc *intel_crtc;
8530         struct intel_encoder *intel_encoder =
8531                 intel_attached_encoder(connector);
8532         struct drm_crtc *possible_crtc;
8533         struct drm_encoder *encoder = &intel_encoder->base;
8534         struct drm_crtc *crtc = NULL;
8535         struct drm_device *dev = encoder->dev;
8536         struct drm_framebuffer *fb;
8537         struct drm_mode_config *config = &dev->mode_config;
8538         int ret, i = -1;
8539
8540         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8541                       connector->base.id, connector->name,
8542                       encoder->base.id, encoder->name);
8543
8544 retry:
8545         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8546         if (ret)
8547                 goto fail_unlock;
8548
8549         /*
8550          * Algorithm gets a little messy:
8551          *
8552          *   - if the connector already has an assigned crtc, use it (but make
8553          *     sure it's on first)
8554          *
8555          *   - try to find the first unused crtc that can drive this connector,
8556          *     and use that if we find one
8557          */
8558
8559         /* See if we already have a CRTC for this connector */
8560         if (encoder->crtc) {
8561                 crtc = encoder->crtc;
8562
8563                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8564                 if (ret)
8565                         goto fail_unlock;
8566
8567                 old->dpms_mode = connector->dpms;
8568                 old->load_detect_temp = false;
8569
8570                 /* Make sure the crtc and connector are running */
8571                 if (connector->dpms != DRM_MODE_DPMS_ON)
8572                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8573
8574                 return true;
8575         }
8576
8577         /* Find an unused one (if possible) */
8578         for_each_crtc(dev, possible_crtc) {
8579                 i++;
8580                 if (!(encoder->possible_crtcs & (1 << i)))
8581                         continue;
8582                 if (possible_crtc->enabled)
8583                         continue;
8584                 /* This can occur when applying the pipe A quirk on resume. */
8585                 if (to_intel_crtc(possible_crtc)->new_enabled)
8586                         continue;
8587
8588                 crtc = possible_crtc;
8589                 break;
8590         }
8591
8592         /*
8593          * If we didn't find an unused CRTC, don't use any.
8594          */
8595         if (!crtc) {
8596                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8597                 goto fail_unlock;
8598         }
8599
8600         ret = drm_modeset_lock(&crtc->mutex, ctx);
8601         if (ret)
8602                 goto fail_unlock;
8603         intel_encoder->new_crtc = to_intel_crtc(crtc);
8604         to_intel_connector(connector)->new_encoder = intel_encoder;
8605
8606         intel_crtc = to_intel_crtc(crtc);
8607         intel_crtc->new_enabled = true;
8608         intel_crtc->new_config = &intel_crtc->config;
8609         old->dpms_mode = connector->dpms;
8610         old->load_detect_temp = true;
8611         old->release_fb = NULL;
8612
8613         if (!mode)
8614                 mode = &load_detect_mode;
8615
8616         /* We need a framebuffer large enough to accommodate all accesses
8617          * that the plane may generate whilst we perform load detection.
8618          * We can not rely on the fbcon either being present (we get called
8619          * during its initialisation to detect all boot displays, or it may
8620          * not even exist) or that it is large enough to satisfy the
8621          * requested mode.
8622          */
8623         fb = mode_fits_in_fbdev(dev, mode);
8624         if (fb == NULL) {
8625                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8626                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8627                 old->release_fb = fb;
8628         } else
8629                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8630         if (IS_ERR(fb)) {
8631                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8632                 goto fail;
8633         }
8634
8635         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8636                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8637                 if (old->release_fb)
8638                         old->release_fb->funcs->destroy(old->release_fb);
8639                 goto fail;
8640         }
8641
8642         /* let the connector get through one full cycle before testing */
8643         intel_wait_for_vblank(dev, intel_crtc->pipe);
8644         return true;
8645
8646  fail:
8647         intel_crtc->new_enabled = crtc->enabled;
8648         if (intel_crtc->new_enabled)
8649                 intel_crtc->new_config = &intel_crtc->config;
8650         else
8651                 intel_crtc->new_config = NULL;
8652 fail_unlock:
8653         if (ret == -EDEADLK) {
8654                 drm_modeset_backoff(ctx);
8655                 goto retry;
8656         }
8657
8658         return false;
8659 }
8660
8661 void intel_release_load_detect_pipe(struct drm_connector *connector,
8662                                     struct intel_load_detect_pipe *old)
8663 {
8664         struct intel_encoder *intel_encoder =
8665                 intel_attached_encoder(connector);
8666         struct drm_encoder *encoder = &intel_encoder->base;
8667         struct drm_crtc *crtc = encoder->crtc;
8668         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8669
8670         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8671                       connector->base.id, connector->name,
8672                       encoder->base.id, encoder->name);
8673
8674         if (old->load_detect_temp) {
8675                 to_intel_connector(connector)->new_encoder = NULL;
8676                 intel_encoder->new_crtc = NULL;
8677                 intel_crtc->new_enabled = false;
8678                 intel_crtc->new_config = NULL;
8679                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8680
8681                 if (old->release_fb) {
8682                         drm_framebuffer_unregister_private(old->release_fb);
8683                         drm_framebuffer_unreference(old->release_fb);
8684                 }
8685
8686                 return;
8687         }
8688
8689         /* Switch crtc and encoder back off if necessary */
8690         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8691                 connector->funcs->dpms(connector, old->dpms_mode);
8692 }
8693
8694 static int i9xx_pll_refclk(struct drm_device *dev,
8695                            const struct intel_crtc_config *pipe_config)
8696 {
8697         struct drm_i915_private *dev_priv = dev->dev_private;
8698         u32 dpll = pipe_config->dpll_hw_state.dpll;
8699
8700         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8701                 return dev_priv->vbt.lvds_ssc_freq;
8702         else if (HAS_PCH_SPLIT(dev))
8703                 return 120000;
8704         else if (!IS_GEN2(dev))
8705                 return 96000;
8706         else
8707                 return 48000;
8708 }
8709
8710 /* Returns the clock of the currently programmed mode of the given pipe. */
8711 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8712                                 struct intel_crtc_config *pipe_config)
8713 {
8714         struct drm_device *dev = crtc->base.dev;
8715         struct drm_i915_private *dev_priv = dev->dev_private;
8716         int pipe = pipe_config->cpu_transcoder;
8717         u32 dpll = pipe_config->dpll_hw_state.dpll;
8718         u32 fp;
8719         intel_clock_t clock;
8720         int refclk = i9xx_pll_refclk(dev, pipe_config);
8721
8722         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8723                 fp = pipe_config->dpll_hw_state.fp0;
8724         else
8725                 fp = pipe_config->dpll_hw_state.fp1;
8726
8727         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8728         if (IS_PINEVIEW(dev)) {
8729                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8730                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8731         } else {
8732                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8733                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8734         }
8735
8736         if (!IS_GEN2(dev)) {
8737                 if (IS_PINEVIEW(dev))
8738                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8739                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8740                 else
8741                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8742                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8743
8744                 switch (dpll & DPLL_MODE_MASK) {
8745                 case DPLLB_MODE_DAC_SERIAL:
8746                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8747                                 5 : 10;
8748                         break;
8749                 case DPLLB_MODE_LVDS:
8750                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8751                                 7 : 14;
8752                         break;
8753                 default:
8754                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8755                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8756                         return;
8757                 }
8758
8759                 if (IS_PINEVIEW(dev))
8760                         pineview_clock(refclk, &clock);
8761                 else
8762                         i9xx_clock(refclk, &clock);
8763         } else {
8764                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8765                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8766
8767                 if (is_lvds) {
8768                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8769                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8770
8771                         if (lvds & LVDS_CLKB_POWER_UP)
8772                                 clock.p2 = 7;
8773                         else
8774                                 clock.p2 = 14;
8775                 } else {
8776                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8777                                 clock.p1 = 2;
8778                         else {
8779                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8780                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8781                         }
8782                         if (dpll & PLL_P2_DIVIDE_BY_4)
8783                                 clock.p2 = 4;
8784                         else
8785                                 clock.p2 = 2;
8786                 }
8787
8788                 i9xx_clock(refclk, &clock);
8789         }
8790
8791         /*
8792          * This value includes pixel_multiplier. We will use
8793          * port_clock to compute adjusted_mode.crtc_clock in the
8794          * encoder's get_config() function.
8795          */
8796         pipe_config->port_clock = clock.dot;
8797 }
8798
8799 int intel_dotclock_calculate(int link_freq,
8800                              const struct intel_link_m_n *m_n)
8801 {
8802         /*
8803          * The calculation for the data clock is:
8804          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8805          * But we want to avoid losing precison if possible, so:
8806          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8807          *
8808          * and the link clock is simpler:
8809          * link_clock = (m * link_clock) / n
8810          */
8811
8812         if (!m_n->link_n)
8813                 return 0;
8814
8815         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8816 }
8817
8818 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8819                                    struct intel_crtc_config *pipe_config)
8820 {
8821         struct drm_device *dev = crtc->base.dev;
8822
8823         /* read out port_clock from the DPLL */
8824         i9xx_crtc_clock_get(crtc, pipe_config);
8825
8826         /*
8827          * This value does not include pixel_multiplier.
8828          * We will check that port_clock and adjusted_mode.crtc_clock
8829          * agree once we know their relationship in the encoder's
8830          * get_config() function.
8831          */
8832         pipe_config->adjusted_mode.crtc_clock =
8833                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8834                                          &pipe_config->fdi_m_n);
8835 }
8836
8837 /** Returns the currently programmed mode of the given pipe. */
8838 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8839                                              struct drm_crtc *crtc)
8840 {
8841         struct drm_i915_private *dev_priv = dev->dev_private;
8842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8843         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8844         struct drm_display_mode *mode;
8845         struct intel_crtc_config pipe_config;
8846         int htot = I915_READ(HTOTAL(cpu_transcoder));
8847         int hsync = I915_READ(HSYNC(cpu_transcoder));
8848         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8849         int vsync = I915_READ(VSYNC(cpu_transcoder));
8850         enum pipe pipe = intel_crtc->pipe;
8851
8852         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8853         if (!mode)
8854                 return NULL;
8855
8856         /*
8857          * Construct a pipe_config sufficient for getting the clock info
8858          * back out of crtc_clock_get.
8859          *
8860          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8861          * to use a real value here instead.
8862          */
8863         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8864         pipe_config.pixel_multiplier = 1;
8865         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8866         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8867         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8868         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8869
8870         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8871         mode->hdisplay = (htot & 0xffff) + 1;
8872         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8873         mode->hsync_start = (hsync & 0xffff) + 1;
8874         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8875         mode->vdisplay = (vtot & 0xffff) + 1;
8876         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8877         mode->vsync_start = (vsync & 0xffff) + 1;
8878         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8879
8880         drm_mode_set_name(mode);
8881
8882         return mode;
8883 }
8884
8885 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8886 {
8887         struct drm_device *dev = crtc->dev;
8888         struct drm_i915_private *dev_priv = dev->dev_private;
8889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8890
8891         if (!HAS_GMCH_DISPLAY(dev))
8892                 return;
8893
8894         if (!dev_priv->lvds_downclock_avail)
8895                 return;
8896
8897         /*
8898          * Since this is called by a timer, we should never get here in
8899          * the manual case.
8900          */
8901         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8902                 int pipe = intel_crtc->pipe;
8903                 int dpll_reg = DPLL(pipe);
8904                 int dpll;
8905
8906                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8907
8908                 assert_panel_unlocked(dev_priv, pipe);
8909
8910                 dpll = I915_READ(dpll_reg);
8911                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8912                 I915_WRITE(dpll_reg, dpll);
8913                 intel_wait_for_vblank(dev, pipe);
8914                 dpll = I915_READ(dpll_reg);
8915                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8916                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8917         }
8918
8919 }
8920
8921 void intel_mark_busy(struct drm_device *dev)
8922 {
8923         struct drm_i915_private *dev_priv = dev->dev_private;
8924
8925         if (dev_priv->mm.busy)
8926                 return;
8927
8928         intel_runtime_pm_get(dev_priv);
8929         i915_update_gfx_val(dev_priv);
8930         dev_priv->mm.busy = true;
8931 }
8932
8933 void intel_mark_idle(struct drm_device *dev)
8934 {
8935         struct drm_i915_private *dev_priv = dev->dev_private;
8936         struct drm_crtc *crtc;
8937
8938         if (!dev_priv->mm.busy)
8939                 return;
8940
8941         dev_priv->mm.busy = false;
8942
8943         if (!i915.powersave)
8944                 goto out;
8945
8946         for_each_crtc(dev, crtc) {
8947                 if (!crtc->primary->fb)
8948                         continue;
8949
8950                 intel_decrease_pllclock(crtc);
8951         }
8952
8953         if (INTEL_INFO(dev)->gen >= 6)
8954                 gen6_rps_idle(dev->dev_private);
8955
8956 out:
8957         intel_runtime_pm_put(dev_priv);
8958 }
8959
8960 static void intel_crtc_destroy(struct drm_crtc *crtc)
8961 {
8962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8963         struct drm_device *dev = crtc->dev;
8964         struct intel_unpin_work *work;
8965
8966         spin_lock_irq(&dev->event_lock);
8967         work = intel_crtc->unpin_work;
8968         intel_crtc->unpin_work = NULL;
8969         spin_unlock_irq(&dev->event_lock);
8970
8971         if (work) {
8972                 cancel_work_sync(&work->work);
8973                 kfree(work);
8974         }
8975
8976         drm_crtc_cleanup(crtc);
8977
8978         kfree(intel_crtc);
8979 }
8980
8981 static void intel_unpin_work_fn(struct work_struct *__work)
8982 {
8983         struct intel_unpin_work *work =
8984                 container_of(__work, struct intel_unpin_work, work);
8985         struct drm_device *dev = work->crtc->dev;
8986         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8987
8988         mutex_lock(&dev->struct_mutex);
8989         intel_unpin_fb_obj(work->old_fb_obj);
8990         drm_gem_object_unreference(&work->pending_flip_obj->base);
8991         drm_gem_object_unreference(&work->old_fb_obj->base);
8992
8993         intel_update_fbc(dev);
8994         mutex_unlock(&dev->struct_mutex);
8995
8996         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8997
8998         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8999         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9000
9001         kfree(work);
9002 }
9003
9004 static void do_intel_finish_page_flip(struct drm_device *dev,
9005                                       struct drm_crtc *crtc)
9006 {
9007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9008         struct intel_unpin_work *work;
9009         unsigned long flags;
9010
9011         /* Ignore early vblank irqs */
9012         if (intel_crtc == NULL)
9013                 return;
9014
9015         /*
9016          * This is called both by irq handlers and the reset code (to complete
9017          * lost pageflips) so needs the full irqsave spinlocks.
9018          */
9019         spin_lock_irqsave(&dev->event_lock, flags);
9020         work = intel_crtc->unpin_work;
9021
9022         /* Ensure we don't miss a work->pending update ... */
9023         smp_rmb();
9024
9025         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9026                 spin_unlock_irqrestore(&dev->event_lock, flags);
9027                 return;
9028         }
9029
9030         page_flip_completed(intel_crtc);
9031
9032         spin_unlock_irqrestore(&dev->event_lock, flags);
9033 }
9034
9035 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9036 {
9037         struct drm_i915_private *dev_priv = dev->dev_private;
9038         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9039
9040         do_intel_finish_page_flip(dev, crtc);
9041 }
9042
9043 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9044 {
9045         struct drm_i915_private *dev_priv = dev->dev_private;
9046         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9047
9048         do_intel_finish_page_flip(dev, crtc);
9049 }
9050
9051 /* Is 'a' after or equal to 'b'? */
9052 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9053 {
9054         return !((a - b) & 0x80000000);
9055 }
9056
9057 static bool page_flip_finished(struct intel_crtc *crtc)
9058 {
9059         struct drm_device *dev = crtc->base.dev;
9060         struct drm_i915_private *dev_priv = dev->dev_private;
9061
9062         /*
9063          * The relevant registers doen't exist on pre-ctg.
9064          * As the flip done interrupt doesn't trigger for mmio
9065          * flips on gmch platforms, a flip count check isn't
9066          * really needed there. But since ctg has the registers,
9067          * include it in the check anyway.
9068          */
9069         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9070                 return true;
9071
9072         /*
9073          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9074          * used the same base address. In that case the mmio flip might
9075          * have completed, but the CS hasn't even executed the flip yet.
9076          *
9077          * A flip count check isn't enough as the CS might have updated
9078          * the base address just after start of vblank, but before we
9079          * managed to process the interrupt. This means we'd complete the
9080          * CS flip too soon.
9081          *
9082          * Combining both checks should get us a good enough result. It may
9083          * still happen that the CS flip has been executed, but has not
9084          * yet actually completed. But in case the base address is the same
9085          * anyway, we don't really care.
9086          */
9087         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9088                 crtc->unpin_work->gtt_offset &&
9089                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9090                                     crtc->unpin_work->flip_count);
9091 }
9092
9093 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9094 {
9095         struct drm_i915_private *dev_priv = dev->dev_private;
9096         struct intel_crtc *intel_crtc =
9097                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9098         unsigned long flags;
9099
9100
9101         /*
9102          * This is called both by irq handlers and the reset code (to complete
9103          * lost pageflips) so needs the full irqsave spinlocks.
9104          *
9105          * NB: An MMIO update of the plane base pointer will also
9106          * generate a page-flip completion irq, i.e. every modeset
9107          * is also accompanied by a spurious intel_prepare_page_flip().
9108          */
9109         spin_lock_irqsave(&dev->event_lock, flags);
9110         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9111                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9112         spin_unlock_irqrestore(&dev->event_lock, flags);
9113 }
9114
9115 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9116 {
9117         /* Ensure that the work item is consistent when activating it ... */
9118         smp_wmb();
9119         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9120         /* and that it is marked active as soon as the irq could fire. */
9121         smp_wmb();
9122 }
9123
9124 static int intel_gen2_queue_flip(struct drm_device *dev,
9125                                  struct drm_crtc *crtc,
9126                                  struct drm_framebuffer *fb,
9127                                  struct drm_i915_gem_object *obj,
9128                                  struct intel_engine_cs *ring,
9129                                  uint32_t flags)
9130 {
9131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9132         u32 flip_mask;
9133         int ret;
9134
9135         ret = intel_ring_begin(ring, 6);
9136         if (ret)
9137                 return ret;
9138
9139         /* Can't queue multiple flips, so wait for the previous
9140          * one to finish before executing the next.
9141          */
9142         if (intel_crtc->plane)
9143                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9144         else
9145                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9146         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9147         intel_ring_emit(ring, MI_NOOP);
9148         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9149                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9150         intel_ring_emit(ring, fb->pitches[0]);
9151         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9152         intel_ring_emit(ring, 0); /* aux display base address, unused */
9153
9154         intel_mark_page_flip_active(intel_crtc);
9155         __intel_ring_advance(ring);
9156         return 0;
9157 }
9158
9159 static int intel_gen3_queue_flip(struct drm_device *dev,
9160                                  struct drm_crtc *crtc,
9161                                  struct drm_framebuffer *fb,
9162                                  struct drm_i915_gem_object *obj,
9163                                  struct intel_engine_cs *ring,
9164                                  uint32_t flags)
9165 {
9166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9167         u32 flip_mask;
9168         int ret;
9169
9170         ret = intel_ring_begin(ring, 6);
9171         if (ret)
9172                 return ret;
9173
9174         if (intel_crtc->plane)
9175                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9176         else
9177                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9178         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9179         intel_ring_emit(ring, MI_NOOP);
9180         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9181                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9182         intel_ring_emit(ring, fb->pitches[0]);
9183         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9184         intel_ring_emit(ring, MI_NOOP);
9185
9186         intel_mark_page_flip_active(intel_crtc);
9187         __intel_ring_advance(ring);
9188         return 0;
9189 }
9190
9191 static int intel_gen4_queue_flip(struct drm_device *dev,
9192                                  struct drm_crtc *crtc,
9193                                  struct drm_framebuffer *fb,
9194                                  struct drm_i915_gem_object *obj,
9195                                  struct intel_engine_cs *ring,
9196                                  uint32_t flags)
9197 {
9198         struct drm_i915_private *dev_priv = dev->dev_private;
9199         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9200         uint32_t pf, pipesrc;
9201         int ret;
9202
9203         ret = intel_ring_begin(ring, 4);
9204         if (ret)
9205                 return ret;
9206
9207         /* i965+ uses the linear or tiled offsets from the
9208          * Display Registers (which do not change across a page-flip)
9209          * so we need only reprogram the base address.
9210          */
9211         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9212                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9213         intel_ring_emit(ring, fb->pitches[0]);
9214         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9215                         obj->tiling_mode);
9216
9217         /* XXX Enabling the panel-fitter across page-flip is so far
9218          * untested on non-native modes, so ignore it for now.
9219          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9220          */
9221         pf = 0;
9222         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9223         intel_ring_emit(ring, pf | pipesrc);
9224
9225         intel_mark_page_flip_active(intel_crtc);
9226         __intel_ring_advance(ring);
9227         return 0;
9228 }
9229
9230 static int intel_gen6_queue_flip(struct drm_device *dev,
9231                                  struct drm_crtc *crtc,
9232                                  struct drm_framebuffer *fb,
9233                                  struct drm_i915_gem_object *obj,
9234                                  struct intel_engine_cs *ring,
9235                                  uint32_t flags)
9236 {
9237         struct drm_i915_private *dev_priv = dev->dev_private;
9238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9239         uint32_t pf, pipesrc;
9240         int ret;
9241
9242         ret = intel_ring_begin(ring, 4);
9243         if (ret)
9244                 return ret;
9245
9246         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9247                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9248         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9249         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9250
9251         /* Contrary to the suggestions in the documentation,
9252          * "Enable Panel Fitter" does not seem to be required when page
9253          * flipping with a non-native mode, and worse causes a normal
9254          * modeset to fail.
9255          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9256          */
9257         pf = 0;
9258         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9259         intel_ring_emit(ring, pf | pipesrc);
9260
9261         intel_mark_page_flip_active(intel_crtc);
9262         __intel_ring_advance(ring);
9263         return 0;
9264 }
9265
9266 static int intel_gen7_queue_flip(struct drm_device *dev,
9267                                  struct drm_crtc *crtc,
9268                                  struct drm_framebuffer *fb,
9269                                  struct drm_i915_gem_object *obj,
9270                                  struct intel_engine_cs *ring,
9271                                  uint32_t flags)
9272 {
9273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9274         uint32_t plane_bit = 0;
9275         int len, ret;
9276
9277         switch (intel_crtc->plane) {
9278         case PLANE_A:
9279                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9280                 break;
9281         case PLANE_B:
9282                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9283                 break;
9284         case PLANE_C:
9285                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9286                 break;
9287         default:
9288                 WARN_ONCE(1, "unknown plane in flip command\n");
9289                 return -ENODEV;
9290         }
9291
9292         len = 4;
9293         if (ring->id == RCS) {
9294                 len += 6;
9295                 /*
9296                  * On Gen 8, SRM is now taking an extra dword to accommodate
9297                  * 48bits addresses, and we need a NOOP for the batch size to
9298                  * stay even.
9299                  */
9300                 if (IS_GEN8(dev))
9301                         len += 2;
9302         }
9303
9304         /*
9305          * BSpec MI_DISPLAY_FLIP for IVB:
9306          * "The full packet must be contained within the same cache line."
9307          *
9308          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9309          * cacheline, if we ever start emitting more commands before
9310          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9311          * then do the cacheline alignment, and finally emit the
9312          * MI_DISPLAY_FLIP.
9313          */
9314         ret = intel_ring_cacheline_align(ring);
9315         if (ret)
9316                 return ret;
9317
9318         ret = intel_ring_begin(ring, len);
9319         if (ret)
9320                 return ret;
9321
9322         /* Unmask the flip-done completion message. Note that the bspec says that
9323          * we should do this for both the BCS and RCS, and that we must not unmask
9324          * more than one flip event at any time (or ensure that one flip message
9325          * can be sent by waiting for flip-done prior to queueing new flips).
9326          * Experimentation says that BCS works despite DERRMR masking all
9327          * flip-done completion events and that unmasking all planes at once
9328          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9329          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9330          */
9331         if (ring->id == RCS) {
9332                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9333                 intel_ring_emit(ring, DERRMR);
9334                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9335                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9336                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9337                 if (IS_GEN8(dev))
9338                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9339                                               MI_SRM_LRM_GLOBAL_GTT);
9340                 else
9341                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9342                                               MI_SRM_LRM_GLOBAL_GTT);
9343                 intel_ring_emit(ring, DERRMR);
9344                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9345                 if (IS_GEN8(dev)) {
9346                         intel_ring_emit(ring, 0);
9347                         intel_ring_emit(ring, MI_NOOP);
9348                 }
9349         }
9350
9351         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9352         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9353         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9354         intel_ring_emit(ring, (MI_NOOP));
9355
9356         intel_mark_page_flip_active(intel_crtc);
9357         __intel_ring_advance(ring);
9358         return 0;
9359 }
9360
9361 static bool use_mmio_flip(struct intel_engine_cs *ring,
9362                           struct drm_i915_gem_object *obj)
9363 {
9364         /*
9365          * This is not being used for older platforms, because
9366          * non-availability of flip done interrupt forces us to use
9367          * CS flips. Older platforms derive flip done using some clever
9368          * tricks involving the flip_pending status bits and vblank irqs.
9369          * So using MMIO flips there would disrupt this mechanism.
9370          */
9371
9372         if (ring == NULL)
9373                 return true;
9374
9375         if (INTEL_INFO(ring->dev)->gen < 5)
9376                 return false;
9377
9378         if (i915.use_mmio_flip < 0)
9379                 return false;
9380         else if (i915.use_mmio_flip > 0)
9381                 return true;
9382         else if (i915.enable_execlists)
9383                 return true;
9384         else
9385                 return ring != obj->ring;
9386 }
9387
9388 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9389 {
9390         struct drm_device *dev = intel_crtc->base.dev;
9391         struct drm_i915_private *dev_priv = dev->dev_private;
9392         struct intel_framebuffer *intel_fb =
9393                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9394         struct drm_i915_gem_object *obj = intel_fb->obj;
9395         bool atomic_update;
9396         u32 start_vbl_count;
9397         u32 dspcntr;
9398         u32 reg;
9399
9400         intel_mark_page_flip_active(intel_crtc);
9401
9402         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9403
9404         reg = DSPCNTR(intel_crtc->plane);
9405         dspcntr = I915_READ(reg);
9406
9407         if (obj->tiling_mode != I915_TILING_NONE)
9408                 dspcntr |= DISPPLANE_TILED;
9409         else
9410                 dspcntr &= ~DISPPLANE_TILED;
9411
9412         I915_WRITE(reg, dspcntr);
9413
9414         I915_WRITE(DSPSURF(intel_crtc->plane),
9415                    intel_crtc->unpin_work->gtt_offset);
9416         POSTING_READ(DSPSURF(intel_crtc->plane));
9417
9418         if (atomic_update)
9419                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9420 }
9421
9422 static void intel_mmio_flip_work_func(struct work_struct *work)
9423 {
9424         struct intel_crtc *intel_crtc =
9425                 container_of(work, struct intel_crtc, mmio_flip.work);
9426         struct intel_engine_cs *ring;
9427         uint32_t seqno;
9428
9429         seqno = intel_crtc->mmio_flip.seqno;
9430         ring = intel_crtc->mmio_flip.ring;
9431
9432         if (seqno)
9433                 WARN_ON(__i915_wait_seqno(ring, seqno,
9434                                           intel_crtc->reset_counter,
9435                                           false, NULL, NULL) != 0);
9436
9437         intel_do_mmio_flip(intel_crtc);
9438 }
9439
9440 static int intel_queue_mmio_flip(struct drm_device *dev,
9441                                  struct drm_crtc *crtc,
9442                                  struct drm_framebuffer *fb,
9443                                  struct drm_i915_gem_object *obj,
9444                                  struct intel_engine_cs *ring,
9445                                  uint32_t flags)
9446 {
9447         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9448
9449         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9450         intel_crtc->mmio_flip.ring = obj->ring;
9451
9452         schedule_work(&intel_crtc->mmio_flip.work);
9453
9454         return 0;
9455 }
9456
9457 static int intel_default_queue_flip(struct drm_device *dev,
9458                                     struct drm_crtc *crtc,
9459                                     struct drm_framebuffer *fb,
9460                                     struct drm_i915_gem_object *obj,
9461                                     struct intel_engine_cs *ring,
9462                                     uint32_t flags)
9463 {
9464         return -ENODEV;
9465 }
9466
9467 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9468                                          struct drm_crtc *crtc)
9469 {
9470         struct drm_i915_private *dev_priv = dev->dev_private;
9471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9472         struct intel_unpin_work *work = intel_crtc->unpin_work;
9473         u32 addr;
9474
9475         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9476                 return true;
9477
9478         if (!work->enable_stall_check)
9479                 return false;
9480
9481         if (work->flip_ready_vblank == 0) {
9482                 if (work->flip_queued_ring &&
9483                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9484                                        work->flip_queued_seqno))
9485                         return false;
9486
9487                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9488         }
9489
9490         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9491                 return false;
9492
9493         /* Potential stall - if we see that the flip has happened,
9494          * assume a missed interrupt. */
9495         if (INTEL_INFO(dev)->gen >= 4)
9496                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9497         else
9498                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9499
9500         /* There is a potential issue here with a false positive after a flip
9501          * to the same address. We could address this by checking for a
9502          * non-incrementing frame counter.
9503          */
9504         return addr == work->gtt_offset;
9505 }
9506
9507 void intel_check_page_flip(struct drm_device *dev, int pipe)
9508 {
9509         struct drm_i915_private *dev_priv = dev->dev_private;
9510         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9512
9513         WARN_ON(!in_irq());
9514
9515         if (crtc == NULL)
9516                 return;
9517
9518         spin_lock(&dev->event_lock);
9519         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9520                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9521                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9522                 page_flip_completed(intel_crtc);
9523         }
9524         spin_unlock(&dev->event_lock);
9525 }
9526
9527 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9528                                 struct drm_framebuffer *fb,
9529                                 struct drm_pending_vblank_event *event,
9530                                 uint32_t page_flip_flags)
9531 {
9532         struct drm_device *dev = crtc->dev;
9533         struct drm_i915_private *dev_priv = dev->dev_private;
9534         struct drm_framebuffer *old_fb = crtc->primary->fb;
9535         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9537         enum pipe pipe = intel_crtc->pipe;
9538         struct intel_unpin_work *work;
9539         struct intel_engine_cs *ring;
9540         int ret;
9541
9542         /*
9543          * drm_mode_page_flip_ioctl() should already catch this, but double
9544          * check to be safe.  In the future we may enable pageflipping from
9545          * a disabled primary plane.
9546          */
9547         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9548                 return -EBUSY;
9549
9550         /* Can't change pixel format via MI display flips. */
9551         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9552                 return -EINVAL;
9553
9554         /*
9555          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9556          * Note that pitch changes could also affect these register.
9557          */
9558         if (INTEL_INFO(dev)->gen > 3 &&
9559             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9560              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9561                 return -EINVAL;
9562
9563         if (i915_terminally_wedged(&dev_priv->gpu_error))
9564                 goto out_hang;
9565
9566         work = kzalloc(sizeof(*work), GFP_KERNEL);
9567         if (work == NULL)
9568                 return -ENOMEM;
9569
9570         work->event = event;
9571         work->crtc = crtc;
9572         work->old_fb_obj = intel_fb_obj(old_fb);
9573         INIT_WORK(&work->work, intel_unpin_work_fn);
9574
9575         ret = drm_crtc_vblank_get(crtc);
9576         if (ret)
9577                 goto free_work;
9578
9579         /* We borrow the event spin lock for protecting unpin_work */
9580         spin_lock_irq(&dev->event_lock);
9581         if (intel_crtc->unpin_work) {
9582                 /* Before declaring the flip queue wedged, check if
9583                  * the hardware completed the operation behind our backs.
9584                  */
9585                 if (__intel_pageflip_stall_check(dev, crtc)) {
9586                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9587                         page_flip_completed(intel_crtc);
9588                 } else {
9589                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9590                         spin_unlock_irq(&dev->event_lock);
9591
9592                         drm_crtc_vblank_put(crtc);
9593                         kfree(work);
9594                         return -EBUSY;
9595                 }
9596         }
9597         intel_crtc->unpin_work = work;
9598         spin_unlock_irq(&dev->event_lock);
9599
9600         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9601                 flush_workqueue(dev_priv->wq);
9602
9603         ret = i915_mutex_lock_interruptible(dev);
9604         if (ret)
9605                 goto cleanup;
9606
9607         /* Reference the objects for the scheduled work. */
9608         drm_gem_object_reference(&work->old_fb_obj->base);
9609         drm_gem_object_reference(&obj->base);
9610
9611         crtc->primary->fb = fb;
9612
9613         work->pending_flip_obj = obj;
9614
9615         atomic_inc(&intel_crtc->unpin_work_count);
9616         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9617
9618         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9619                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9620
9621         if (IS_VALLEYVIEW(dev)) {
9622                 ring = &dev_priv->ring[BCS];
9623                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9624                         /* vlv: DISPLAY_FLIP fails to change tiling */
9625                         ring = NULL;
9626         } else if (IS_IVYBRIDGE(dev)) {
9627                 ring = &dev_priv->ring[BCS];
9628         } else if (INTEL_INFO(dev)->gen >= 7) {
9629                 ring = obj->ring;
9630                 if (ring == NULL || ring->id != RCS)
9631                         ring = &dev_priv->ring[BCS];
9632         } else {
9633                 ring = &dev_priv->ring[RCS];
9634         }
9635
9636         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9637         if (ret)
9638                 goto cleanup_pending;
9639
9640         work->gtt_offset =
9641                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9642
9643         if (use_mmio_flip(ring, obj)) {
9644                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9645                                             page_flip_flags);
9646                 if (ret)
9647                         goto cleanup_unpin;
9648
9649                 work->flip_queued_seqno = obj->last_write_seqno;
9650                 work->flip_queued_ring = obj->ring;
9651         } else {
9652                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9653                                                    page_flip_flags);
9654                 if (ret)
9655                         goto cleanup_unpin;
9656
9657                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9658                 work->flip_queued_ring = ring;
9659         }
9660
9661         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9662         work->enable_stall_check = true;
9663
9664         i915_gem_track_fb(work->old_fb_obj, obj,
9665                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9666
9667         intel_disable_fbc(dev);
9668         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9669         mutex_unlock(&dev->struct_mutex);
9670
9671         trace_i915_flip_request(intel_crtc->plane, obj);
9672
9673         return 0;
9674
9675 cleanup_unpin:
9676         intel_unpin_fb_obj(obj);
9677 cleanup_pending:
9678         atomic_dec(&intel_crtc->unpin_work_count);
9679         crtc->primary->fb = old_fb;
9680         drm_gem_object_unreference(&work->old_fb_obj->base);
9681         drm_gem_object_unreference(&obj->base);
9682         mutex_unlock(&dev->struct_mutex);
9683
9684 cleanup:
9685         spin_lock_irq(&dev->event_lock);
9686         intel_crtc->unpin_work = NULL;
9687         spin_unlock_irq(&dev->event_lock);
9688
9689         drm_crtc_vblank_put(crtc);
9690 free_work:
9691         kfree(work);
9692
9693         if (ret == -EIO) {
9694 out_hang:
9695                 intel_crtc_wait_for_pending_flips(crtc);
9696                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9697                 if (ret == 0 && event) {
9698                         spin_lock_irq(&dev->event_lock);
9699                         drm_send_vblank_event(dev, pipe, event);
9700                         spin_unlock_irq(&dev->event_lock);
9701                 }
9702         }
9703         return ret;
9704 }
9705
9706 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9707         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9708         .load_lut = intel_crtc_load_lut,
9709 };
9710
9711 /**
9712  * intel_modeset_update_staged_output_state
9713  *
9714  * Updates the staged output configuration state, e.g. after we've read out the
9715  * current hw state.
9716  */
9717 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9718 {
9719         struct intel_crtc *crtc;
9720         struct intel_encoder *encoder;
9721         struct intel_connector *connector;
9722
9723         list_for_each_entry(connector, &dev->mode_config.connector_list,
9724                             base.head) {
9725                 connector->new_encoder =
9726                         to_intel_encoder(connector->base.encoder);
9727         }
9728
9729         for_each_intel_encoder(dev, encoder) {
9730                 encoder->new_crtc =
9731                         to_intel_crtc(encoder->base.crtc);
9732         }
9733
9734         for_each_intel_crtc(dev, crtc) {
9735                 crtc->new_enabled = crtc->base.enabled;
9736
9737                 if (crtc->new_enabled)
9738                         crtc->new_config = &crtc->config;
9739                 else
9740                         crtc->new_config = NULL;
9741         }
9742 }
9743
9744 /**
9745  * intel_modeset_commit_output_state
9746  *
9747  * This function copies the stage display pipe configuration to the real one.
9748  */
9749 static void intel_modeset_commit_output_state(struct drm_device *dev)
9750 {
9751         struct intel_crtc *crtc;
9752         struct intel_encoder *encoder;
9753         struct intel_connector *connector;
9754
9755         list_for_each_entry(connector, &dev->mode_config.connector_list,
9756                             base.head) {
9757                 connector->base.encoder = &connector->new_encoder->base;
9758         }
9759
9760         for_each_intel_encoder(dev, encoder) {
9761                 encoder->base.crtc = &encoder->new_crtc->base;
9762         }
9763
9764         for_each_intel_crtc(dev, crtc) {
9765                 crtc->base.enabled = crtc->new_enabled;
9766         }
9767 }
9768
9769 static void
9770 connected_sink_compute_bpp(struct intel_connector *connector,
9771                            struct intel_crtc_config *pipe_config)
9772 {
9773         int bpp = pipe_config->pipe_bpp;
9774
9775         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9776                 connector->base.base.id,
9777                 connector->base.name);
9778
9779         /* Don't use an invalid EDID bpc value */
9780         if (connector->base.display_info.bpc &&
9781             connector->base.display_info.bpc * 3 < bpp) {
9782                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9783                               bpp, connector->base.display_info.bpc*3);
9784                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9785         }
9786
9787         /* Clamp bpp to 8 on screens without EDID 1.4 */
9788         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9789                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9790                               bpp);
9791                 pipe_config->pipe_bpp = 24;
9792         }
9793 }
9794
9795 static int
9796 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9797                           struct drm_framebuffer *fb,
9798                           struct intel_crtc_config *pipe_config)
9799 {
9800         struct drm_device *dev = crtc->base.dev;
9801         struct intel_connector *connector;
9802         int bpp;
9803
9804         switch (fb->pixel_format) {
9805         case DRM_FORMAT_C8:
9806                 bpp = 8*3; /* since we go through a colormap */
9807                 break;
9808         case DRM_FORMAT_XRGB1555:
9809         case DRM_FORMAT_ARGB1555:
9810                 /* checked in intel_framebuffer_init already */
9811                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9812                         return -EINVAL;
9813         case DRM_FORMAT_RGB565:
9814                 bpp = 6*3; /* min is 18bpp */
9815                 break;
9816         case DRM_FORMAT_XBGR8888:
9817         case DRM_FORMAT_ABGR8888:
9818                 /* checked in intel_framebuffer_init already */
9819                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9820                         return -EINVAL;
9821         case DRM_FORMAT_XRGB8888:
9822         case DRM_FORMAT_ARGB8888:
9823                 bpp = 8*3;
9824                 break;
9825         case DRM_FORMAT_XRGB2101010:
9826         case DRM_FORMAT_ARGB2101010:
9827         case DRM_FORMAT_XBGR2101010:
9828         case DRM_FORMAT_ABGR2101010:
9829                 /* checked in intel_framebuffer_init already */
9830                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9831                         return -EINVAL;
9832                 bpp = 10*3;
9833                 break;
9834         /* TODO: gen4+ supports 16 bpc floating point, too. */
9835         default:
9836                 DRM_DEBUG_KMS("unsupported depth\n");
9837                 return -EINVAL;
9838         }
9839
9840         pipe_config->pipe_bpp = bpp;
9841
9842         /* Clamp display bpp to EDID value */
9843         list_for_each_entry(connector, &dev->mode_config.connector_list,
9844                             base.head) {
9845                 if (!connector->new_encoder ||
9846                     connector->new_encoder->new_crtc != crtc)
9847                         continue;
9848
9849                 connected_sink_compute_bpp(connector, pipe_config);
9850         }
9851
9852         return bpp;
9853 }
9854
9855 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9856 {
9857         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9858                         "type: 0x%x flags: 0x%x\n",
9859                 mode->crtc_clock,
9860                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9861                 mode->crtc_hsync_end, mode->crtc_htotal,
9862                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9863                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9864 }
9865
9866 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9867                                    struct intel_crtc_config *pipe_config,
9868                                    const char *context)
9869 {
9870         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9871                       context, pipe_name(crtc->pipe));
9872
9873         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9874         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9875                       pipe_config->pipe_bpp, pipe_config->dither);
9876         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9877                       pipe_config->has_pch_encoder,
9878                       pipe_config->fdi_lanes,
9879                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9880                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9881                       pipe_config->fdi_m_n.tu);
9882         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9883                       pipe_config->has_dp_encoder,
9884                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9885                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9886                       pipe_config->dp_m_n.tu);
9887
9888         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9889                       pipe_config->has_dp_encoder,
9890                       pipe_config->dp_m2_n2.gmch_m,
9891                       pipe_config->dp_m2_n2.gmch_n,
9892                       pipe_config->dp_m2_n2.link_m,
9893                       pipe_config->dp_m2_n2.link_n,
9894                       pipe_config->dp_m2_n2.tu);
9895
9896         DRM_DEBUG_KMS("requested mode:\n");
9897         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9898         DRM_DEBUG_KMS("adjusted mode:\n");
9899         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9900         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9901         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9902         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9903                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9904         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9905                       pipe_config->gmch_pfit.control,
9906                       pipe_config->gmch_pfit.pgm_ratios,
9907                       pipe_config->gmch_pfit.lvds_border_bits);
9908         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9909                       pipe_config->pch_pfit.pos,
9910                       pipe_config->pch_pfit.size,
9911                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9912         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9913         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9914 }
9915
9916 static bool encoders_cloneable(const struct intel_encoder *a,
9917                                const struct intel_encoder *b)
9918 {
9919         /* masks could be asymmetric, so check both ways */
9920         return a == b || (a->cloneable & (1 << b->type) &&
9921                           b->cloneable & (1 << a->type));
9922 }
9923
9924 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9925                                          struct intel_encoder *encoder)
9926 {
9927         struct drm_device *dev = crtc->base.dev;
9928         struct intel_encoder *source_encoder;
9929
9930         for_each_intel_encoder(dev, source_encoder) {
9931                 if (source_encoder->new_crtc != crtc)
9932                         continue;
9933
9934                 if (!encoders_cloneable(encoder, source_encoder))
9935                         return false;
9936         }
9937
9938         return true;
9939 }
9940
9941 static bool check_encoder_cloning(struct intel_crtc *crtc)
9942 {
9943         struct drm_device *dev = crtc->base.dev;
9944         struct intel_encoder *encoder;
9945
9946         for_each_intel_encoder(dev, encoder) {
9947                 if (encoder->new_crtc != crtc)
9948                         continue;
9949
9950                 if (!check_single_encoder_cloning(crtc, encoder))
9951                         return false;
9952         }
9953
9954         return true;
9955 }
9956
9957 static struct intel_crtc_config *
9958 intel_modeset_pipe_config(struct drm_crtc *crtc,
9959                           struct drm_framebuffer *fb,
9960                           struct drm_display_mode *mode)
9961 {
9962         struct drm_device *dev = crtc->dev;
9963         struct intel_encoder *encoder;
9964         struct intel_crtc_config *pipe_config;
9965         int plane_bpp, ret = -EINVAL;
9966         bool retry = true;
9967
9968         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9969                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9970                 return ERR_PTR(-EINVAL);
9971         }
9972
9973         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9974         if (!pipe_config)
9975                 return ERR_PTR(-ENOMEM);
9976
9977         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9978         drm_mode_copy(&pipe_config->requested_mode, mode);
9979
9980         pipe_config->cpu_transcoder =
9981                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9982         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9983
9984         /*
9985          * Sanitize sync polarity flags based on requested ones. If neither
9986          * positive or negative polarity is requested, treat this as meaning
9987          * negative polarity.
9988          */
9989         if (!(pipe_config->adjusted_mode.flags &
9990               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9991                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9992
9993         if (!(pipe_config->adjusted_mode.flags &
9994               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9995                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9996
9997         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9998          * plane pixel format and any sink constraints into account. Returns the
9999          * source plane bpp so that dithering can be selected on mismatches
10000          * after encoders and crtc also have had their say. */
10001         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10002                                               fb, pipe_config);
10003         if (plane_bpp < 0)
10004                 goto fail;
10005
10006         /*
10007          * Determine the real pipe dimensions. Note that stereo modes can
10008          * increase the actual pipe size due to the frame doubling and
10009          * insertion of additional space for blanks between the frame. This
10010          * is stored in the crtc timings. We use the requested mode to do this
10011          * computation to clearly distinguish it from the adjusted mode, which
10012          * can be changed by the connectors in the below retry loop.
10013          */
10014         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10015         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10016         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10017
10018 encoder_retry:
10019         /* Ensure the port clock defaults are reset when retrying. */
10020         pipe_config->port_clock = 0;
10021         pipe_config->pixel_multiplier = 1;
10022
10023         /* Fill in default crtc timings, allow encoders to overwrite them. */
10024         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10025
10026         /* Pass our mode to the connectors and the CRTC to give them a chance to
10027          * adjust it according to limitations or connector properties, and also
10028          * a chance to reject the mode entirely.
10029          */
10030         for_each_intel_encoder(dev, encoder) {
10031
10032                 if (&encoder->new_crtc->base != crtc)
10033                         continue;
10034
10035                 if (!(encoder->compute_config(encoder, pipe_config))) {
10036                         DRM_DEBUG_KMS("Encoder config failure\n");
10037                         goto fail;
10038                 }
10039         }
10040
10041         /* Set default port clock if not overwritten by the encoder. Needs to be
10042          * done afterwards in case the encoder adjusts the mode. */
10043         if (!pipe_config->port_clock)
10044                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10045                         * pipe_config->pixel_multiplier;
10046
10047         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10048         if (ret < 0) {
10049                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10050                 goto fail;
10051         }
10052
10053         if (ret == RETRY) {
10054                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10055                         ret = -EINVAL;
10056                         goto fail;
10057                 }
10058
10059                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10060                 retry = false;
10061                 goto encoder_retry;
10062         }
10063
10064         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10065         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10066                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10067
10068         return pipe_config;
10069 fail:
10070         kfree(pipe_config);
10071         return ERR_PTR(ret);
10072 }
10073
10074 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10075  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10076 static void
10077 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10078                              unsigned *prepare_pipes, unsigned *disable_pipes)
10079 {
10080         struct intel_crtc *intel_crtc;
10081         struct drm_device *dev = crtc->dev;
10082         struct intel_encoder *encoder;
10083         struct intel_connector *connector;
10084         struct drm_crtc *tmp_crtc;
10085
10086         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10087
10088         /* Check which crtcs have changed outputs connected to them, these need
10089          * to be part of the prepare_pipes mask. We don't (yet) support global
10090          * modeset across multiple crtcs, so modeset_pipes will only have one
10091          * bit set at most. */
10092         list_for_each_entry(connector, &dev->mode_config.connector_list,
10093                             base.head) {
10094                 if (connector->base.encoder == &connector->new_encoder->base)
10095                         continue;
10096
10097                 if (connector->base.encoder) {
10098                         tmp_crtc = connector->base.encoder->crtc;
10099
10100                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10101                 }
10102
10103                 if (connector->new_encoder)
10104                         *prepare_pipes |=
10105                                 1 << connector->new_encoder->new_crtc->pipe;
10106         }
10107
10108         for_each_intel_encoder(dev, encoder) {
10109                 if (encoder->base.crtc == &encoder->new_crtc->base)
10110                         continue;
10111
10112                 if (encoder->base.crtc) {
10113                         tmp_crtc = encoder->base.crtc;
10114
10115                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10116                 }
10117
10118                 if (encoder->new_crtc)
10119                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10120         }
10121
10122         /* Check for pipes that will be enabled/disabled ... */
10123         for_each_intel_crtc(dev, intel_crtc) {
10124                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10125                         continue;
10126
10127                 if (!intel_crtc->new_enabled)
10128                         *disable_pipes |= 1 << intel_crtc->pipe;
10129                 else
10130                         *prepare_pipes |= 1 << intel_crtc->pipe;
10131         }
10132
10133
10134         /* set_mode is also used to update properties on life display pipes. */
10135         intel_crtc = to_intel_crtc(crtc);
10136         if (intel_crtc->new_enabled)
10137                 *prepare_pipes |= 1 << intel_crtc->pipe;
10138
10139         /*
10140          * For simplicity do a full modeset on any pipe where the output routing
10141          * changed. We could be more clever, but that would require us to be
10142          * more careful with calling the relevant encoder->mode_set functions.
10143          */
10144         if (*prepare_pipes)
10145                 *modeset_pipes = *prepare_pipes;
10146
10147         /* ... and mask these out. */
10148         *modeset_pipes &= ~(*disable_pipes);
10149         *prepare_pipes &= ~(*disable_pipes);
10150
10151         /*
10152          * HACK: We don't (yet) fully support global modesets. intel_set_config
10153          * obies this rule, but the modeset restore mode of
10154          * intel_modeset_setup_hw_state does not.
10155          */
10156         *modeset_pipes &= 1 << intel_crtc->pipe;
10157         *prepare_pipes &= 1 << intel_crtc->pipe;
10158
10159         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10160                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10161 }
10162
10163 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10164 {
10165         struct drm_encoder *encoder;
10166         struct drm_device *dev = crtc->dev;
10167
10168         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10169                 if (encoder->crtc == crtc)
10170                         return true;
10171
10172         return false;
10173 }
10174
10175 static void
10176 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10177 {
10178         struct drm_i915_private *dev_priv = dev->dev_private;
10179         struct intel_encoder *intel_encoder;
10180         struct intel_crtc *intel_crtc;
10181         struct drm_connector *connector;
10182
10183         intel_shared_dpll_commit(dev_priv);
10184
10185         for_each_intel_encoder(dev, intel_encoder) {
10186                 if (!intel_encoder->base.crtc)
10187                         continue;
10188
10189                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10190
10191                 if (prepare_pipes & (1 << intel_crtc->pipe))
10192                         intel_encoder->connectors_active = false;
10193         }
10194
10195         intel_modeset_commit_output_state(dev);
10196
10197         /* Double check state. */
10198         for_each_intel_crtc(dev, intel_crtc) {
10199                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10200                 WARN_ON(intel_crtc->new_config &&
10201                         intel_crtc->new_config != &intel_crtc->config);
10202                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10203         }
10204
10205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10206                 if (!connector->encoder || !connector->encoder->crtc)
10207                         continue;
10208
10209                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10210
10211                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10212                         struct drm_property *dpms_property =
10213                                 dev->mode_config.dpms_property;
10214
10215                         connector->dpms = DRM_MODE_DPMS_ON;
10216                         drm_object_property_set_value(&connector->base,
10217                                                          dpms_property,
10218                                                          DRM_MODE_DPMS_ON);
10219
10220                         intel_encoder = to_intel_encoder(connector->encoder);
10221                         intel_encoder->connectors_active = true;
10222                 }
10223         }
10224
10225 }
10226
10227 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10228 {
10229         int diff;
10230
10231         if (clock1 == clock2)
10232                 return true;
10233
10234         if (!clock1 || !clock2)
10235                 return false;
10236
10237         diff = abs(clock1 - clock2);
10238
10239         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10240                 return true;
10241
10242         return false;
10243 }
10244
10245 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10246         list_for_each_entry((intel_crtc), \
10247                             &(dev)->mode_config.crtc_list, \
10248                             base.head) \
10249                 if (mask & (1 <<(intel_crtc)->pipe))
10250
10251 static bool
10252 intel_pipe_config_compare(struct drm_device *dev,
10253                           struct intel_crtc_config *current_config,
10254                           struct intel_crtc_config *pipe_config)
10255 {
10256 #define PIPE_CONF_CHECK_X(name) \
10257         if (current_config->name != pipe_config->name) { \
10258                 DRM_ERROR("mismatch in " #name " " \
10259                           "(expected 0x%08x, found 0x%08x)\n", \
10260                           current_config->name, \
10261                           pipe_config->name); \
10262                 return false; \
10263         }
10264
10265 #define PIPE_CONF_CHECK_I(name) \
10266         if (current_config->name != pipe_config->name) { \
10267                 DRM_ERROR("mismatch in " #name " " \
10268                           "(expected %i, found %i)\n", \
10269                           current_config->name, \
10270                           pipe_config->name); \
10271                 return false; \
10272         }
10273
10274 /* This is required for BDW+ where there is only one set of registers for
10275  * switching between high and low RR.
10276  * This macro can be used whenever a comparison has to be made between one
10277  * hw state and multiple sw state variables.
10278  */
10279 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10280         if ((current_config->name != pipe_config->name) && \
10281                 (current_config->alt_name != pipe_config->name)) { \
10282                         DRM_ERROR("mismatch in " #name " " \
10283                                   "(expected %i or %i, found %i)\n", \
10284                                   current_config->name, \
10285                                   current_config->alt_name, \
10286                                   pipe_config->name); \
10287                         return false; \
10288         }
10289
10290 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10291         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10292                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10293                           "(expected %i, found %i)\n", \
10294                           current_config->name & (mask), \
10295                           pipe_config->name & (mask)); \
10296                 return false; \
10297         }
10298
10299 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10300         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10301                 DRM_ERROR("mismatch in " #name " " \
10302                           "(expected %i, found %i)\n", \
10303                           current_config->name, \
10304                           pipe_config->name); \
10305                 return false; \
10306         }
10307
10308 #define PIPE_CONF_QUIRK(quirk)  \
10309         ((current_config->quirks | pipe_config->quirks) & (quirk))
10310
10311         PIPE_CONF_CHECK_I(cpu_transcoder);
10312
10313         PIPE_CONF_CHECK_I(has_pch_encoder);
10314         PIPE_CONF_CHECK_I(fdi_lanes);
10315         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10316         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10317         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10318         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10319         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10320
10321         PIPE_CONF_CHECK_I(has_dp_encoder);
10322
10323         if (INTEL_INFO(dev)->gen < 8) {
10324                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10325                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10326                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10327                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10328                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10329
10330                 if (current_config->has_drrs) {
10331                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10332                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10333                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10334                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10335                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10336                 }
10337         } else {
10338                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10339                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10340                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10341                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10342                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10343         }
10344
10345         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10346         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10347         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10348         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10349         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10350         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10351
10352         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10353         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10354         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10355         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10356         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10357         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10358
10359         PIPE_CONF_CHECK_I(pixel_multiplier);
10360         PIPE_CONF_CHECK_I(has_hdmi_sink);
10361         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10362             IS_VALLEYVIEW(dev))
10363                 PIPE_CONF_CHECK_I(limited_color_range);
10364
10365         PIPE_CONF_CHECK_I(has_audio);
10366
10367         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10368                               DRM_MODE_FLAG_INTERLACE);
10369
10370         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10371                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10372                                       DRM_MODE_FLAG_PHSYNC);
10373                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10374                                       DRM_MODE_FLAG_NHSYNC);
10375                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10376                                       DRM_MODE_FLAG_PVSYNC);
10377                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10378                                       DRM_MODE_FLAG_NVSYNC);
10379         }
10380
10381         PIPE_CONF_CHECK_I(pipe_src_w);
10382         PIPE_CONF_CHECK_I(pipe_src_h);
10383
10384         /*
10385          * FIXME: BIOS likes to set up a cloned config with lvds+external
10386          * screen. Since we don't yet re-compute the pipe config when moving
10387          * just the lvds port away to another pipe the sw tracking won't match.
10388          *
10389          * Proper atomic modesets with recomputed global state will fix this.
10390          * Until then just don't check gmch state for inherited modes.
10391          */
10392         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10393                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10394                 /* pfit ratios are autocomputed by the hw on gen4+ */
10395                 if (INTEL_INFO(dev)->gen < 4)
10396                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10397                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10398         }
10399
10400         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10401         if (current_config->pch_pfit.enabled) {
10402                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10403                 PIPE_CONF_CHECK_I(pch_pfit.size);
10404         }
10405
10406         /* BDW+ don't expose a synchronous way to read the state */
10407         if (IS_HASWELL(dev))
10408                 PIPE_CONF_CHECK_I(ips_enabled);
10409
10410         PIPE_CONF_CHECK_I(double_wide);
10411
10412         PIPE_CONF_CHECK_X(ddi_pll_sel);
10413
10414         PIPE_CONF_CHECK_I(shared_dpll);
10415         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10416         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10417         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10418         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10419         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10420
10421         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10422                 PIPE_CONF_CHECK_I(pipe_bpp);
10423
10424         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10425         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10426
10427 #undef PIPE_CONF_CHECK_X
10428 #undef PIPE_CONF_CHECK_I
10429 #undef PIPE_CONF_CHECK_I_ALT
10430 #undef PIPE_CONF_CHECK_FLAGS
10431 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10432 #undef PIPE_CONF_QUIRK
10433
10434         return true;
10435 }
10436
10437 static void check_wm_state(struct drm_device *dev)
10438 {
10439         struct drm_i915_private *dev_priv = dev->dev_private;
10440         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10441         struct intel_crtc *intel_crtc;
10442         int plane;
10443
10444         if (INTEL_INFO(dev)->gen < 9)
10445                 return;
10446
10447         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10448         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10449
10450         for_each_intel_crtc(dev, intel_crtc) {
10451                 struct skl_ddb_entry *hw_entry, *sw_entry;
10452                 const enum pipe pipe = intel_crtc->pipe;
10453
10454                 if (!intel_crtc->active)
10455                         continue;
10456
10457                 /* planes */
10458                 for_each_plane(pipe, plane) {
10459                         hw_entry = &hw_ddb.plane[pipe][plane];
10460                         sw_entry = &sw_ddb->plane[pipe][plane];
10461
10462                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10463                                 continue;
10464
10465                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10466                                   "(expected (%u,%u), found (%u,%u))\n",
10467                                   pipe_name(pipe), plane + 1,
10468                                   sw_entry->start, sw_entry->end,
10469                                   hw_entry->start, hw_entry->end);
10470                 }
10471
10472                 /* cursor */
10473                 hw_entry = &hw_ddb.cursor[pipe];
10474                 sw_entry = &sw_ddb->cursor[pipe];
10475
10476                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10477                         continue;
10478
10479                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10480                           "(expected (%u,%u), found (%u,%u))\n",
10481                           pipe_name(pipe),
10482                           sw_entry->start, sw_entry->end,
10483                           hw_entry->start, hw_entry->end);
10484         }
10485 }
10486
10487 static void
10488 check_connector_state(struct drm_device *dev)
10489 {
10490         struct intel_connector *connector;
10491
10492         list_for_each_entry(connector, &dev->mode_config.connector_list,
10493                             base.head) {
10494                 /* This also checks the encoder/connector hw state with the
10495                  * ->get_hw_state callbacks. */
10496                 intel_connector_check_state(connector);
10497
10498                 WARN(&connector->new_encoder->base != connector->base.encoder,
10499                      "connector's staged encoder doesn't match current encoder\n");
10500         }
10501 }
10502
10503 static void
10504 check_encoder_state(struct drm_device *dev)
10505 {
10506         struct intel_encoder *encoder;
10507         struct intel_connector *connector;
10508
10509         for_each_intel_encoder(dev, encoder) {
10510                 bool enabled = false;
10511                 bool active = false;
10512                 enum pipe pipe, tracked_pipe;
10513
10514                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10515                               encoder->base.base.id,
10516                               encoder->base.name);
10517
10518                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10519                      "encoder's stage crtc doesn't match current crtc\n");
10520                 WARN(encoder->connectors_active && !encoder->base.crtc,
10521                      "encoder's active_connectors set, but no crtc\n");
10522
10523                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10524                                     base.head) {
10525                         if (connector->base.encoder != &encoder->base)
10526                                 continue;
10527                         enabled = true;
10528                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10529                                 active = true;
10530                 }
10531                 /*
10532                  * for MST connectors if we unplug the connector is gone
10533                  * away but the encoder is still connected to a crtc
10534                  * until a modeset happens in response to the hotplug.
10535                  */
10536                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10537                         continue;
10538
10539                 WARN(!!encoder->base.crtc != enabled,
10540                      "encoder's enabled state mismatch "
10541                      "(expected %i, found %i)\n",
10542                      !!encoder->base.crtc, enabled);
10543                 WARN(active && !encoder->base.crtc,
10544                      "active encoder with no crtc\n");
10545
10546                 WARN(encoder->connectors_active != active,
10547                      "encoder's computed active state doesn't match tracked active state "
10548                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10549
10550                 active = encoder->get_hw_state(encoder, &pipe);
10551                 WARN(active != encoder->connectors_active,
10552                      "encoder's hw state doesn't match sw tracking "
10553                      "(expected %i, found %i)\n",
10554                      encoder->connectors_active, active);
10555
10556                 if (!encoder->base.crtc)
10557                         continue;
10558
10559                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10560                 WARN(active && pipe != tracked_pipe,
10561                      "active encoder's pipe doesn't match"
10562                      "(expected %i, found %i)\n",
10563                      tracked_pipe, pipe);
10564
10565         }
10566 }
10567
10568 static void
10569 check_crtc_state(struct drm_device *dev)
10570 {
10571         struct drm_i915_private *dev_priv = dev->dev_private;
10572         struct intel_crtc *crtc;
10573         struct intel_encoder *encoder;
10574         struct intel_crtc_config pipe_config;
10575
10576         for_each_intel_crtc(dev, crtc) {
10577                 bool enabled = false;
10578                 bool active = false;
10579
10580                 memset(&pipe_config, 0, sizeof(pipe_config));
10581
10582                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10583                               crtc->base.base.id);
10584
10585                 WARN(crtc->active && !crtc->base.enabled,
10586                      "active crtc, but not enabled in sw tracking\n");
10587
10588                 for_each_intel_encoder(dev, encoder) {
10589                         if (encoder->base.crtc != &crtc->base)
10590                                 continue;
10591                         enabled = true;
10592                         if (encoder->connectors_active)
10593                                 active = true;
10594                 }
10595
10596                 WARN(active != crtc->active,
10597                      "crtc's computed active state doesn't match tracked active state "
10598                      "(expected %i, found %i)\n", active, crtc->active);
10599                 WARN(enabled != crtc->base.enabled,
10600                      "crtc's computed enabled state doesn't match tracked enabled state "
10601                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10602
10603                 active = dev_priv->display.get_pipe_config(crtc,
10604                                                            &pipe_config);
10605
10606                 /* hw state is inconsistent with the pipe quirk */
10607                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10608                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10609                         active = crtc->active;
10610
10611                 for_each_intel_encoder(dev, encoder) {
10612                         enum pipe pipe;
10613                         if (encoder->base.crtc != &crtc->base)
10614                                 continue;
10615                         if (encoder->get_hw_state(encoder, &pipe))
10616                                 encoder->get_config(encoder, &pipe_config);
10617                 }
10618
10619                 WARN(crtc->active != active,
10620                      "crtc active state doesn't match with hw state "
10621                      "(expected %i, found %i)\n", crtc->active, active);
10622
10623                 if (active &&
10624                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10625                         WARN(1, "pipe state doesn't match!\n");
10626                         intel_dump_pipe_config(crtc, &pipe_config,
10627                                                "[hw state]");
10628                         intel_dump_pipe_config(crtc, &crtc->config,
10629                                                "[sw state]");
10630                 }
10631         }
10632 }
10633
10634 static void
10635 check_shared_dpll_state(struct drm_device *dev)
10636 {
10637         struct drm_i915_private *dev_priv = dev->dev_private;
10638         struct intel_crtc *crtc;
10639         struct intel_dpll_hw_state dpll_hw_state;
10640         int i;
10641
10642         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10643                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10644                 int enabled_crtcs = 0, active_crtcs = 0;
10645                 bool active;
10646
10647                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10648
10649                 DRM_DEBUG_KMS("%s\n", pll->name);
10650
10651                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10652
10653                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10654                      "more active pll users than references: %i vs %i\n",
10655                      pll->active, hweight32(pll->config.crtc_mask));
10656                 WARN(pll->active && !pll->on,
10657                      "pll in active use but not on in sw tracking\n");
10658                 WARN(pll->on && !pll->active,
10659                      "pll in on but not on in use in sw tracking\n");
10660                 WARN(pll->on != active,
10661                      "pll on state mismatch (expected %i, found %i)\n",
10662                      pll->on, active);
10663
10664                 for_each_intel_crtc(dev, crtc) {
10665                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10666                                 enabled_crtcs++;
10667                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10668                                 active_crtcs++;
10669                 }
10670                 WARN(pll->active != active_crtcs,
10671                      "pll active crtcs mismatch (expected %i, found %i)\n",
10672                      pll->active, active_crtcs);
10673                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10674                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10675                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10676
10677                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10678                                        sizeof(dpll_hw_state)),
10679                      "pll hw state mismatch\n");
10680         }
10681 }
10682
10683 void
10684 intel_modeset_check_state(struct drm_device *dev)
10685 {
10686         check_wm_state(dev);
10687         check_connector_state(dev);
10688         check_encoder_state(dev);
10689         check_crtc_state(dev);
10690         check_shared_dpll_state(dev);
10691 }
10692
10693 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10694                                      int dotclock)
10695 {
10696         /*
10697          * FDI already provided one idea for the dotclock.
10698          * Yell if the encoder disagrees.
10699          */
10700         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10701              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10702              pipe_config->adjusted_mode.crtc_clock, dotclock);
10703 }
10704
10705 static void update_scanline_offset(struct intel_crtc *crtc)
10706 {
10707         struct drm_device *dev = crtc->base.dev;
10708
10709         /*
10710          * The scanline counter increments at the leading edge of hsync.
10711          *
10712          * On most platforms it starts counting from vtotal-1 on the
10713          * first active line. That means the scanline counter value is
10714          * always one less than what we would expect. Ie. just after
10715          * start of vblank, which also occurs at start of hsync (on the
10716          * last active line), the scanline counter will read vblank_start-1.
10717          *
10718          * On gen2 the scanline counter starts counting from 1 instead
10719          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10720          * to keep the value positive), instead of adding one.
10721          *
10722          * On HSW+ the behaviour of the scanline counter depends on the output
10723          * type. For DP ports it behaves like most other platforms, but on HDMI
10724          * there's an extra 1 line difference. So we need to add two instead of
10725          * one to the value.
10726          */
10727         if (IS_GEN2(dev)) {
10728                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10729                 int vtotal;
10730
10731                 vtotal = mode->crtc_vtotal;
10732                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10733                         vtotal /= 2;
10734
10735                 crtc->scanline_offset = vtotal - 1;
10736         } else if (HAS_DDI(dev) &&
10737                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10738                 crtc->scanline_offset = 2;
10739         } else
10740                 crtc->scanline_offset = 1;
10741 }
10742
10743 static int __intel_set_mode(struct drm_crtc *crtc,
10744                             struct drm_display_mode *mode,
10745                             int x, int y, struct drm_framebuffer *fb)
10746 {
10747         struct drm_device *dev = crtc->dev;
10748         struct drm_i915_private *dev_priv = dev->dev_private;
10749         struct drm_display_mode *saved_mode;
10750         struct intel_crtc_config *pipe_config = NULL;
10751         struct intel_crtc *intel_crtc;
10752         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10753         int ret = 0;
10754
10755         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10756         if (!saved_mode)
10757                 return -ENOMEM;
10758
10759         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10760                                      &prepare_pipes, &disable_pipes);
10761
10762         *saved_mode = crtc->mode;
10763
10764         /* Hack: Because we don't (yet) support global modeset on multiple
10765          * crtcs, we don't keep track of the new mode for more than one crtc.
10766          * Hence simply check whether any bit is set in modeset_pipes in all the
10767          * pieces of code that are not yet converted to deal with mutliple crtcs
10768          * changing their mode at the same time. */
10769         if (modeset_pipes) {
10770                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10771                 if (IS_ERR(pipe_config)) {
10772                         ret = PTR_ERR(pipe_config);
10773                         pipe_config = NULL;
10774
10775                         goto out;
10776                 }
10777                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10778                                        "[modeset]");
10779                 to_intel_crtc(crtc)->new_config = pipe_config;
10780         }
10781
10782         /*
10783          * See if the config requires any additional preparation, e.g.
10784          * to adjust global state with pipes off.  We need to do this
10785          * here so we can get the modeset_pipe updated config for the new
10786          * mode set on this crtc.  For other crtcs we need to use the
10787          * adjusted_mode bits in the crtc directly.
10788          */
10789         if (IS_VALLEYVIEW(dev)) {
10790                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10791
10792                 /* may have added more to prepare_pipes than we should */
10793                 prepare_pipes &= ~disable_pipes;
10794         }
10795
10796         if (dev_priv->display.crtc_compute_clock) {
10797                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10798
10799                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10800                 if (ret)
10801                         goto done;
10802
10803                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10804                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10805                         if (ret) {
10806                                 intel_shared_dpll_abort_config(dev_priv);
10807                                 goto done;
10808                         }
10809                 }
10810         }
10811
10812         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10813                 intel_crtc_disable(&intel_crtc->base);
10814
10815         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10816                 if (intel_crtc->base.enabled)
10817                         dev_priv->display.crtc_disable(&intel_crtc->base);
10818         }
10819
10820         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10821          * to set it here already despite that we pass it down the callchain.
10822          */
10823         if (modeset_pipes) {
10824                 crtc->mode = *mode;
10825                 /* mode_set/enable/disable functions rely on a correct pipe
10826                  * config. */
10827                 to_intel_crtc(crtc)->config = *pipe_config;
10828                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10829
10830                 /*
10831                  * Calculate and store various constants which
10832                  * are later needed by vblank and swap-completion
10833                  * timestamping. They are derived from true hwmode.
10834                  */
10835                 drm_calc_timestamping_constants(crtc,
10836                                                 &pipe_config->adjusted_mode);
10837         }
10838
10839         /* Only after disabling all output pipelines that will be changed can we
10840          * update the the output configuration. */
10841         intel_modeset_update_state(dev, prepare_pipes);
10842
10843         modeset_update_crtc_power_domains(dev);
10844
10845         /* Set up the DPLL and any encoders state that needs to adjust or depend
10846          * on the DPLL.
10847          */
10848         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10849                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10850                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10851                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10852
10853                 mutex_lock(&dev->struct_mutex);
10854                 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10855                 if (ret != 0) {
10856                         DRM_ERROR("pin & fence failed\n");
10857                         mutex_unlock(&dev->struct_mutex);
10858                         goto done;
10859                 }
10860                 if (old_fb)
10861                         intel_unpin_fb_obj(old_obj);
10862                 i915_gem_track_fb(old_obj, obj,
10863                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10864                 mutex_unlock(&dev->struct_mutex);
10865
10866                 crtc->primary->fb = fb;
10867                 crtc->x = x;
10868                 crtc->y = y;
10869         }
10870
10871         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10872         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10873                 update_scanline_offset(intel_crtc);
10874
10875                 dev_priv->display.crtc_enable(&intel_crtc->base);
10876         }
10877
10878         /* FIXME: add subpixel order */
10879 done:
10880         if (ret && crtc->enabled)
10881                 crtc->mode = *saved_mode;
10882
10883 out:
10884         kfree(pipe_config);
10885         kfree(saved_mode);
10886         return ret;
10887 }
10888
10889 static int intel_set_mode(struct drm_crtc *crtc,
10890                           struct drm_display_mode *mode,
10891                           int x, int y, struct drm_framebuffer *fb)
10892 {
10893         int ret;
10894
10895         ret = __intel_set_mode(crtc, mode, x, y, fb);
10896
10897         if (ret == 0)
10898                 intel_modeset_check_state(crtc->dev);
10899
10900         return ret;
10901 }
10902
10903 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10904 {
10905         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10906 }
10907
10908 #undef for_each_intel_crtc_masked
10909
10910 static void intel_set_config_free(struct intel_set_config *config)
10911 {
10912         if (!config)
10913                 return;
10914
10915         kfree(config->save_connector_encoders);
10916         kfree(config->save_encoder_crtcs);
10917         kfree(config->save_crtc_enabled);
10918         kfree(config);
10919 }
10920
10921 static int intel_set_config_save_state(struct drm_device *dev,
10922                                        struct intel_set_config *config)
10923 {
10924         struct drm_crtc *crtc;
10925         struct drm_encoder *encoder;
10926         struct drm_connector *connector;
10927         int count;
10928
10929         config->save_crtc_enabled =
10930                 kcalloc(dev->mode_config.num_crtc,
10931                         sizeof(bool), GFP_KERNEL);
10932         if (!config->save_crtc_enabled)
10933                 return -ENOMEM;
10934
10935         config->save_encoder_crtcs =
10936                 kcalloc(dev->mode_config.num_encoder,
10937                         sizeof(struct drm_crtc *), GFP_KERNEL);
10938         if (!config->save_encoder_crtcs)
10939                 return -ENOMEM;
10940
10941         config->save_connector_encoders =
10942                 kcalloc(dev->mode_config.num_connector,
10943                         sizeof(struct drm_encoder *), GFP_KERNEL);
10944         if (!config->save_connector_encoders)
10945                 return -ENOMEM;
10946
10947         /* Copy data. Note that driver private data is not affected.
10948          * Should anything bad happen only the expected state is
10949          * restored, not the drivers personal bookkeeping.
10950          */
10951         count = 0;
10952         for_each_crtc(dev, crtc) {
10953                 config->save_crtc_enabled[count++] = crtc->enabled;
10954         }
10955
10956         count = 0;
10957         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10958                 config->save_encoder_crtcs[count++] = encoder->crtc;
10959         }
10960
10961         count = 0;
10962         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10963                 config->save_connector_encoders[count++] = connector->encoder;
10964         }
10965
10966         return 0;
10967 }
10968
10969 static void intel_set_config_restore_state(struct drm_device *dev,
10970                                            struct intel_set_config *config)
10971 {
10972         struct intel_crtc *crtc;
10973         struct intel_encoder *encoder;
10974         struct intel_connector *connector;
10975         int count;
10976
10977         count = 0;
10978         for_each_intel_crtc(dev, crtc) {
10979                 crtc->new_enabled = config->save_crtc_enabled[count++];
10980
10981                 if (crtc->new_enabled)
10982                         crtc->new_config = &crtc->config;
10983                 else
10984                         crtc->new_config = NULL;
10985         }
10986
10987         count = 0;
10988         for_each_intel_encoder(dev, encoder) {
10989                 encoder->new_crtc =
10990                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10991         }
10992
10993         count = 0;
10994         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10995                 connector->new_encoder =
10996                         to_intel_encoder(config->save_connector_encoders[count++]);
10997         }
10998 }
10999
11000 static bool
11001 is_crtc_connector_off(struct drm_mode_set *set)
11002 {
11003         int i;
11004
11005         if (set->num_connectors == 0)
11006                 return false;
11007
11008         if (WARN_ON(set->connectors == NULL))
11009                 return false;
11010
11011         for (i = 0; i < set->num_connectors; i++)
11012                 if (set->connectors[i]->encoder &&
11013                     set->connectors[i]->encoder->crtc == set->crtc &&
11014                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11015                         return true;
11016
11017         return false;
11018 }
11019
11020 static void
11021 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11022                                       struct intel_set_config *config)
11023 {
11024
11025         /* We should be able to check here if the fb has the same properties
11026          * and then just flip_or_move it */
11027         if (is_crtc_connector_off(set)) {
11028                 config->mode_changed = true;
11029         } else if (set->crtc->primary->fb != set->fb) {
11030                 /*
11031                  * If we have no fb, we can only flip as long as the crtc is
11032                  * active, otherwise we need a full mode set.  The crtc may
11033                  * be active if we've only disabled the primary plane, or
11034                  * in fastboot situations.
11035                  */
11036                 if (set->crtc->primary->fb == NULL) {
11037                         struct intel_crtc *intel_crtc =
11038                                 to_intel_crtc(set->crtc);
11039
11040                         if (intel_crtc->active) {
11041                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11042                                 config->fb_changed = true;
11043                         } else {
11044                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11045                                 config->mode_changed = true;
11046                         }
11047                 } else if (set->fb == NULL) {
11048                         config->mode_changed = true;
11049                 } else if (set->fb->pixel_format !=
11050                            set->crtc->primary->fb->pixel_format) {
11051                         config->mode_changed = true;
11052                 } else {
11053                         config->fb_changed = true;
11054                 }
11055         }
11056
11057         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11058                 config->fb_changed = true;
11059
11060         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11061                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11062                 drm_mode_debug_printmodeline(&set->crtc->mode);
11063                 drm_mode_debug_printmodeline(set->mode);
11064                 config->mode_changed = true;
11065         }
11066
11067         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11068                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11069 }
11070
11071 static int
11072 intel_modeset_stage_output_state(struct drm_device *dev,
11073                                  struct drm_mode_set *set,
11074                                  struct intel_set_config *config)
11075 {
11076         struct intel_connector *connector;
11077         struct intel_encoder *encoder;
11078         struct intel_crtc *crtc;
11079         int ro;
11080
11081         /* The upper layers ensure that we either disable a crtc or have a list
11082          * of connectors. For paranoia, double-check this. */
11083         WARN_ON(!set->fb && (set->num_connectors != 0));
11084         WARN_ON(set->fb && (set->num_connectors == 0));
11085
11086         list_for_each_entry(connector, &dev->mode_config.connector_list,
11087                             base.head) {
11088                 /* Otherwise traverse passed in connector list and get encoders
11089                  * for them. */
11090                 for (ro = 0; ro < set->num_connectors; ro++) {
11091                         if (set->connectors[ro] == &connector->base) {
11092                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11093                                 break;
11094                         }
11095                 }
11096
11097                 /* If we disable the crtc, disable all its connectors. Also, if
11098                  * the connector is on the changing crtc but not on the new
11099                  * connector list, disable it. */
11100                 if ((!set->fb || ro == set->num_connectors) &&
11101                     connector->base.encoder &&
11102                     connector->base.encoder->crtc == set->crtc) {
11103                         connector->new_encoder = NULL;
11104
11105                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11106                                 connector->base.base.id,
11107                                 connector->base.name);
11108                 }
11109
11110
11111                 if (&connector->new_encoder->base != connector->base.encoder) {
11112                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11113                         config->mode_changed = true;
11114                 }
11115         }
11116         /* connector->new_encoder is now updated for all connectors. */
11117
11118         /* Update crtc of enabled connectors. */
11119         list_for_each_entry(connector, &dev->mode_config.connector_list,
11120                             base.head) {
11121                 struct drm_crtc *new_crtc;
11122
11123                 if (!connector->new_encoder)
11124                         continue;
11125
11126                 new_crtc = connector->new_encoder->base.crtc;
11127
11128                 for (ro = 0; ro < set->num_connectors; ro++) {
11129                         if (set->connectors[ro] == &connector->base)
11130                                 new_crtc = set->crtc;
11131                 }
11132
11133                 /* Make sure the new CRTC will work with the encoder */
11134                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11135                                          new_crtc)) {
11136                         return -EINVAL;
11137                 }
11138                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11139
11140                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11141                         connector->base.base.id,
11142                         connector->base.name,
11143                         new_crtc->base.id);
11144         }
11145
11146         /* Check for any encoders that needs to be disabled. */
11147         for_each_intel_encoder(dev, encoder) {
11148                 int num_connectors = 0;
11149                 list_for_each_entry(connector,
11150                                     &dev->mode_config.connector_list,
11151                                     base.head) {
11152                         if (connector->new_encoder == encoder) {
11153                                 WARN_ON(!connector->new_encoder->new_crtc);
11154                                 num_connectors++;
11155                         }
11156                 }
11157
11158                 if (num_connectors == 0)
11159                         encoder->new_crtc = NULL;
11160                 else if (num_connectors > 1)
11161                         return -EINVAL;
11162
11163                 /* Only now check for crtc changes so we don't miss encoders
11164                  * that will be disabled. */
11165                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11166                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11167                         config->mode_changed = true;
11168                 }
11169         }
11170         /* Now we've also updated encoder->new_crtc for all encoders. */
11171         list_for_each_entry(connector, &dev->mode_config.connector_list,
11172                             base.head) {
11173                 if (connector->new_encoder)
11174                         if (connector->new_encoder != connector->encoder)
11175                                 connector->encoder = connector->new_encoder;
11176         }
11177         for_each_intel_crtc(dev, crtc) {
11178                 crtc->new_enabled = false;
11179
11180                 for_each_intel_encoder(dev, encoder) {
11181                         if (encoder->new_crtc == crtc) {
11182                                 crtc->new_enabled = true;
11183                                 break;
11184                         }
11185                 }
11186
11187                 if (crtc->new_enabled != crtc->base.enabled) {
11188                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11189                                       crtc->new_enabled ? "en" : "dis");
11190                         config->mode_changed = true;
11191                 }
11192
11193                 if (crtc->new_enabled)
11194                         crtc->new_config = &crtc->config;
11195                 else
11196                         crtc->new_config = NULL;
11197         }
11198
11199         return 0;
11200 }
11201
11202 static void disable_crtc_nofb(struct intel_crtc *crtc)
11203 {
11204         struct drm_device *dev = crtc->base.dev;
11205         struct intel_encoder *encoder;
11206         struct intel_connector *connector;
11207
11208         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11209                       pipe_name(crtc->pipe));
11210
11211         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11212                 if (connector->new_encoder &&
11213                     connector->new_encoder->new_crtc == crtc)
11214                         connector->new_encoder = NULL;
11215         }
11216
11217         for_each_intel_encoder(dev, encoder) {
11218                 if (encoder->new_crtc == crtc)
11219                         encoder->new_crtc = NULL;
11220         }
11221
11222         crtc->new_enabled = false;
11223         crtc->new_config = NULL;
11224 }
11225
11226 static int intel_crtc_set_config(struct drm_mode_set *set)
11227 {
11228         struct drm_device *dev;
11229         struct drm_mode_set save_set;
11230         struct intel_set_config *config;
11231         int ret;
11232
11233         BUG_ON(!set);
11234         BUG_ON(!set->crtc);
11235         BUG_ON(!set->crtc->helper_private);
11236
11237         /* Enforce sane interface api - has been abused by the fb helper. */
11238         BUG_ON(!set->mode && set->fb);
11239         BUG_ON(set->fb && set->num_connectors == 0);
11240
11241         if (set->fb) {
11242                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11243                                 set->crtc->base.id, set->fb->base.id,
11244                                 (int)set->num_connectors, set->x, set->y);
11245         } else {
11246                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11247         }
11248
11249         dev = set->crtc->dev;
11250
11251         ret = -ENOMEM;
11252         config = kzalloc(sizeof(*config), GFP_KERNEL);
11253         if (!config)
11254                 goto out_config;
11255
11256         ret = intel_set_config_save_state(dev, config);
11257         if (ret)
11258                 goto out_config;
11259
11260         save_set.crtc = set->crtc;
11261         save_set.mode = &set->crtc->mode;
11262         save_set.x = set->crtc->x;
11263         save_set.y = set->crtc->y;
11264         save_set.fb = set->crtc->primary->fb;
11265
11266         /* Compute whether we need a full modeset, only an fb base update or no
11267          * change at all. In the future we might also check whether only the
11268          * mode changed, e.g. for LVDS where we only change the panel fitter in
11269          * such cases. */
11270         intel_set_config_compute_mode_changes(set, config);
11271
11272         ret = intel_modeset_stage_output_state(dev, set, config);
11273         if (ret)
11274                 goto fail;
11275
11276         if (config->mode_changed) {
11277                 ret = intel_set_mode(set->crtc, set->mode,
11278                                      set->x, set->y, set->fb);
11279         } else if (config->fb_changed) {
11280                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11281
11282                 intel_crtc_wait_for_pending_flips(set->crtc);
11283
11284                 ret = intel_pipe_set_base(set->crtc,
11285                                           set->x, set->y, set->fb);
11286
11287                 /*
11288                  * We need to make sure the primary plane is re-enabled if it
11289                  * has previously been turned off.
11290                  */
11291                 if (!intel_crtc->primary_enabled && ret == 0) {
11292                         WARN_ON(!intel_crtc->active);
11293                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11294                 }
11295
11296                 /*
11297                  * In the fastboot case this may be our only check of the
11298                  * state after boot.  It would be better to only do it on
11299                  * the first update, but we don't have a nice way of doing that
11300                  * (and really, set_config isn't used much for high freq page
11301                  * flipping, so increasing its cost here shouldn't be a big
11302                  * deal).
11303                  */
11304                 if (i915.fastboot && ret == 0)
11305                         intel_modeset_check_state(set->crtc->dev);
11306         }
11307
11308         if (ret) {
11309                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11310                               set->crtc->base.id, ret);
11311 fail:
11312                 intel_set_config_restore_state(dev, config);
11313
11314                 /*
11315                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11316                  * force the pipe off to avoid oopsing in the modeset code
11317                  * due to fb==NULL. This should only happen during boot since
11318                  * we don't yet reconstruct the FB from the hardware state.
11319                  */
11320                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11321                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11322
11323                 /* Try to restore the config */
11324                 if (config->mode_changed &&
11325                     intel_set_mode(save_set.crtc, save_set.mode,
11326                                    save_set.x, save_set.y, save_set.fb))
11327                         DRM_ERROR("failed to restore config after modeset failure\n");
11328         }
11329
11330 out_config:
11331         intel_set_config_free(config);
11332         return ret;
11333 }
11334
11335 static const struct drm_crtc_funcs intel_crtc_funcs = {
11336         .gamma_set = intel_crtc_gamma_set,
11337         .set_config = intel_crtc_set_config,
11338         .destroy = intel_crtc_destroy,
11339         .page_flip = intel_crtc_page_flip,
11340 };
11341
11342 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11343                                       struct intel_shared_dpll *pll,
11344                                       struct intel_dpll_hw_state *hw_state)
11345 {
11346         uint32_t val;
11347
11348         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11349                 return false;
11350
11351         val = I915_READ(PCH_DPLL(pll->id));
11352         hw_state->dpll = val;
11353         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11354         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11355
11356         return val & DPLL_VCO_ENABLE;
11357 }
11358
11359 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11360                                   struct intel_shared_dpll *pll)
11361 {
11362         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11363         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11364 }
11365
11366 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11367                                 struct intel_shared_dpll *pll)
11368 {
11369         /* PCH refclock must be enabled first */
11370         ibx_assert_pch_refclk_enabled(dev_priv);
11371
11372         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11373
11374         /* Wait for the clocks to stabilize. */
11375         POSTING_READ(PCH_DPLL(pll->id));
11376         udelay(150);
11377
11378         /* The pixel multiplier can only be updated once the
11379          * DPLL is enabled and the clocks are stable.
11380          *
11381          * So write it again.
11382          */
11383         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11384         POSTING_READ(PCH_DPLL(pll->id));
11385         udelay(200);
11386 }
11387
11388 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11389                                  struct intel_shared_dpll *pll)
11390 {
11391         struct drm_device *dev = dev_priv->dev;
11392         struct intel_crtc *crtc;
11393
11394         /* Make sure no transcoder isn't still depending on us. */
11395         for_each_intel_crtc(dev, crtc) {
11396                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11397                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11398         }
11399
11400         I915_WRITE(PCH_DPLL(pll->id), 0);
11401         POSTING_READ(PCH_DPLL(pll->id));
11402         udelay(200);
11403 }
11404
11405 static char *ibx_pch_dpll_names[] = {
11406         "PCH DPLL A",
11407         "PCH DPLL B",
11408 };
11409
11410 static void ibx_pch_dpll_init(struct drm_device *dev)
11411 {
11412         struct drm_i915_private *dev_priv = dev->dev_private;
11413         int i;
11414
11415         dev_priv->num_shared_dpll = 2;
11416
11417         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11418                 dev_priv->shared_dplls[i].id = i;
11419                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11420                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11421                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11422                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11423                 dev_priv->shared_dplls[i].get_hw_state =
11424                         ibx_pch_dpll_get_hw_state;
11425         }
11426 }
11427
11428 static void intel_shared_dpll_init(struct drm_device *dev)
11429 {
11430         struct drm_i915_private *dev_priv = dev->dev_private;
11431
11432         if (HAS_DDI(dev))
11433                 intel_ddi_pll_init(dev);
11434         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11435                 ibx_pch_dpll_init(dev);
11436         else
11437                 dev_priv->num_shared_dpll = 0;
11438
11439         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11440 }
11441
11442 static int
11443 intel_primary_plane_disable(struct drm_plane *plane)
11444 {
11445         struct drm_device *dev = plane->dev;
11446         struct intel_crtc *intel_crtc;
11447
11448         if (!plane->fb)
11449                 return 0;
11450
11451         BUG_ON(!plane->crtc);
11452
11453         intel_crtc = to_intel_crtc(plane->crtc);
11454
11455         /*
11456          * Even though we checked plane->fb above, it's still possible that
11457          * the primary plane has been implicitly disabled because the crtc
11458          * coordinates given weren't visible, or because we detected
11459          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11460          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11461          * In either case, we need to unpin the FB and let the fb pointer get
11462          * updated, but otherwise we don't need to touch the hardware.
11463          */
11464         if (!intel_crtc->primary_enabled)
11465                 goto disable_unpin;
11466
11467         intel_crtc_wait_for_pending_flips(plane->crtc);
11468         intel_disable_primary_hw_plane(plane, plane->crtc);
11469
11470 disable_unpin:
11471         mutex_lock(&dev->struct_mutex);
11472         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11473                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11474         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11475         mutex_unlock(&dev->struct_mutex);
11476         plane->fb = NULL;
11477
11478         return 0;
11479 }
11480
11481 static int
11482 intel_check_primary_plane(struct drm_plane *plane,
11483                           struct intel_plane_state *state)
11484 {
11485         struct drm_crtc *crtc = state->crtc;
11486         struct drm_framebuffer *fb = state->fb;
11487         struct drm_rect *dest = &state->dst;
11488         struct drm_rect *src = &state->src;
11489         const struct drm_rect *clip = &state->clip;
11490
11491         return drm_plane_helper_check_update(plane, crtc, fb,
11492                                              src, dest, clip,
11493                                              DRM_PLANE_HELPER_NO_SCALING,
11494                                              DRM_PLANE_HELPER_NO_SCALING,
11495                                              false, true, &state->visible);
11496 }
11497
11498 static int
11499 intel_prepare_primary_plane(struct drm_plane *plane,
11500                             struct intel_plane_state *state)
11501 {
11502         struct drm_crtc *crtc = state->crtc;
11503         struct drm_framebuffer *fb = state->fb;
11504         struct drm_device *dev = crtc->dev;
11505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11506         enum pipe pipe = intel_crtc->pipe;
11507         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11508         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11509         int ret;
11510
11511         intel_crtc_wait_for_pending_flips(crtc);
11512
11513         if (intel_crtc_has_pending_flip(crtc)) {
11514                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11515                 return -EBUSY;
11516         }
11517
11518         if (old_obj != obj) {
11519                 mutex_lock(&dev->struct_mutex);
11520                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11521                 if (ret == 0)
11522                         i915_gem_track_fb(old_obj, obj,
11523                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11524                 mutex_unlock(&dev->struct_mutex);
11525                 if (ret != 0) {
11526                         DRM_DEBUG_KMS("pin & fence failed\n");
11527                         return ret;
11528                 }
11529         }
11530
11531         return 0;
11532 }
11533
11534 static void
11535 intel_commit_primary_plane(struct drm_plane *plane,
11536                            struct intel_plane_state *state)
11537 {
11538         struct drm_crtc *crtc = state->crtc;
11539         struct drm_framebuffer *fb = state->fb;
11540         struct drm_device *dev = crtc->dev;
11541         struct drm_i915_private *dev_priv = dev->dev_private;
11542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11543         enum pipe pipe = intel_crtc->pipe;
11544         struct drm_framebuffer *old_fb = plane->fb;
11545         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11546         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11547         struct intel_plane *intel_plane = to_intel_plane(plane);
11548         struct drm_rect *src = &state->src;
11549
11550         crtc->primary->fb = fb;
11551         crtc->x = src->x1;
11552         crtc->y = src->y1;
11553
11554         intel_plane->crtc_x = state->orig_dst.x1;
11555         intel_plane->crtc_y = state->orig_dst.y1;
11556         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11557         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11558         intel_plane->src_x = state->orig_src.x1;
11559         intel_plane->src_y = state->orig_src.y1;
11560         intel_plane->src_w = drm_rect_width(&state->orig_src);
11561         intel_plane->src_h = drm_rect_height(&state->orig_src);
11562         intel_plane->obj = obj;
11563
11564         if (intel_crtc->active) {
11565                 /*
11566                  * FBC does not work on some platforms for rotated
11567                  * planes, so disable it when rotation is not 0 and
11568                  * update it when rotation is set back to 0.
11569                  *
11570                  * FIXME: This is redundant with the fbc update done in
11571                  * the primary plane enable function except that that
11572                  * one is done too late. We eventually need to unify
11573                  * this.
11574                  */
11575                 if (intel_crtc->primary_enabled &&
11576                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11577                     dev_priv->fbc.plane == intel_crtc->plane &&
11578                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11579                         intel_disable_fbc(dev);
11580                 }
11581
11582                 if (state->visible) {
11583                         bool was_enabled = intel_crtc->primary_enabled;
11584
11585                         /* FIXME: kill this fastboot hack */
11586                         intel_update_pipe_size(intel_crtc);
11587
11588                         intel_crtc->primary_enabled = true;
11589
11590                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11591                                         crtc->x, crtc->y);
11592
11593                         /*
11594                          * BDW signals flip done immediately if the plane
11595                          * is disabled, even if the plane enable is already
11596                          * armed to occur at the next vblank :(
11597                          */
11598                         if (IS_BROADWELL(dev) && !was_enabled)
11599                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11600                 } else {
11601                         /*
11602                          * If clipping results in a non-visible primary plane,
11603                          * we'll disable the primary plane.  Note that this is
11604                          * a bit different than what happens if userspace
11605                          * explicitly disables the plane by passing fb=0
11606                          * because plane->fb still gets set and pinned.
11607                          */
11608                         intel_disable_primary_hw_plane(plane, crtc);
11609                 }
11610
11611                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11612
11613                 mutex_lock(&dev->struct_mutex);
11614                 intel_update_fbc(dev);
11615                 mutex_unlock(&dev->struct_mutex);
11616         }
11617
11618         if (old_fb && old_fb != fb) {
11619                 if (intel_crtc->active)
11620                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11621
11622                 mutex_lock(&dev->struct_mutex);
11623                 intel_unpin_fb_obj(old_obj);
11624                 mutex_unlock(&dev->struct_mutex);
11625         }
11626 }
11627
11628 static int
11629 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11630                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11631                              unsigned int crtc_w, unsigned int crtc_h,
11632                              uint32_t src_x, uint32_t src_y,
11633                              uint32_t src_w, uint32_t src_h)
11634 {
11635         struct intel_plane_state state;
11636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11637         int ret;
11638
11639         state.crtc = crtc;
11640         state.fb = fb;
11641
11642         /* sample coordinates in 16.16 fixed point */
11643         state.src.x1 = src_x;
11644         state.src.x2 = src_x + src_w;
11645         state.src.y1 = src_y;
11646         state.src.y2 = src_y + src_h;
11647
11648         /* integer pixels */
11649         state.dst.x1 = crtc_x;
11650         state.dst.x2 = crtc_x + crtc_w;
11651         state.dst.y1 = crtc_y;
11652         state.dst.y2 = crtc_y + crtc_h;
11653
11654         state.clip.x1 = 0;
11655         state.clip.y1 = 0;
11656         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11657         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11658
11659         state.orig_src = state.src;
11660         state.orig_dst = state.dst;
11661
11662         ret = intel_check_primary_plane(plane, &state);
11663         if (ret)
11664                 return ret;
11665
11666         ret = intel_prepare_primary_plane(plane, &state);
11667         if (ret)
11668                 return ret;
11669
11670         intel_commit_primary_plane(plane, &state);
11671
11672         return 0;
11673 }
11674
11675 /* Common destruction function for both primary and cursor planes */
11676 static void intel_plane_destroy(struct drm_plane *plane)
11677 {
11678         struct intel_plane *intel_plane = to_intel_plane(plane);
11679         drm_plane_cleanup(plane);
11680         kfree(intel_plane);
11681 }
11682
11683 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11684         .update_plane = intel_primary_plane_setplane,
11685         .disable_plane = intel_primary_plane_disable,
11686         .destroy = intel_plane_destroy,
11687         .set_property = intel_plane_set_property
11688 };
11689
11690 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11691                                                     int pipe)
11692 {
11693         struct intel_plane *primary;
11694         const uint32_t *intel_primary_formats;
11695         int num_formats;
11696
11697         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11698         if (primary == NULL)
11699                 return NULL;
11700
11701         primary->can_scale = false;
11702         primary->max_downscale = 1;
11703         primary->pipe = pipe;
11704         primary->plane = pipe;
11705         primary->rotation = BIT(DRM_ROTATE_0);
11706         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11707                 primary->plane = !pipe;
11708
11709         if (INTEL_INFO(dev)->gen <= 3) {
11710                 intel_primary_formats = intel_primary_formats_gen2;
11711                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11712         } else {
11713                 intel_primary_formats = intel_primary_formats_gen4;
11714                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11715         }
11716
11717         drm_universal_plane_init(dev, &primary->base, 0,
11718                                  &intel_primary_plane_funcs,
11719                                  intel_primary_formats, num_formats,
11720                                  DRM_PLANE_TYPE_PRIMARY);
11721
11722         if (INTEL_INFO(dev)->gen >= 4) {
11723                 if (!dev->mode_config.rotation_property)
11724                         dev->mode_config.rotation_property =
11725                                 drm_mode_create_rotation_property(dev,
11726                                                         BIT(DRM_ROTATE_0) |
11727                                                         BIT(DRM_ROTATE_180));
11728                 if (dev->mode_config.rotation_property)
11729                         drm_object_attach_property(&primary->base.base,
11730                                 dev->mode_config.rotation_property,
11731                                 primary->rotation);
11732         }
11733
11734         return &primary->base;
11735 }
11736
11737 static int
11738 intel_cursor_plane_disable(struct drm_plane *plane)
11739 {
11740         if (!plane->fb)
11741                 return 0;
11742
11743         BUG_ON(!plane->crtc);
11744
11745         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11746 }
11747
11748 static int
11749 intel_check_cursor_plane(struct drm_plane *plane,
11750                          struct intel_plane_state *state)
11751 {
11752         struct drm_crtc *crtc = state->crtc;
11753         struct drm_device *dev = crtc->dev;
11754         struct drm_framebuffer *fb = state->fb;
11755         struct drm_rect *dest = &state->dst;
11756         struct drm_rect *src = &state->src;
11757         const struct drm_rect *clip = &state->clip;
11758         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11759         int crtc_w, crtc_h;
11760         unsigned stride;
11761         int ret;
11762
11763         ret = drm_plane_helper_check_update(plane, crtc, fb,
11764                                             src, dest, clip,
11765                                             DRM_PLANE_HELPER_NO_SCALING,
11766                                             DRM_PLANE_HELPER_NO_SCALING,
11767                                             true, true, &state->visible);
11768         if (ret)
11769                 return ret;
11770
11771
11772         /* if we want to turn off the cursor ignore width and height */
11773         if (!obj)
11774                 return 0;
11775
11776         /* Check for which cursor types we support */
11777         crtc_w = drm_rect_width(&state->orig_dst);
11778         crtc_h = drm_rect_height(&state->orig_dst);
11779         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11780                 DRM_DEBUG("Cursor dimension not supported\n");
11781                 return -EINVAL;
11782         }
11783
11784         stride = roundup_pow_of_two(crtc_w) * 4;
11785         if (obj->base.size < stride * crtc_h) {
11786                 DRM_DEBUG_KMS("buffer is too small\n");
11787                 return -ENOMEM;
11788         }
11789
11790         if (fb == crtc->cursor->fb)
11791                 return 0;
11792
11793         /* we only need to pin inside GTT if cursor is non-phy */
11794         mutex_lock(&dev->struct_mutex);
11795         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11796                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11797                 ret = -EINVAL;
11798         }
11799         mutex_unlock(&dev->struct_mutex);
11800
11801         return ret;
11802 }
11803
11804 static int
11805 intel_commit_cursor_plane(struct drm_plane *plane,
11806                           struct intel_plane_state *state)
11807 {
11808         struct drm_crtc *crtc = state->crtc;
11809         struct drm_framebuffer *fb = state->fb;
11810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11811         struct intel_plane *intel_plane = to_intel_plane(plane);
11812         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11813         struct drm_i915_gem_object *obj = intel_fb->obj;
11814         int crtc_w, crtc_h;
11815
11816         crtc->cursor_x = state->orig_dst.x1;
11817         crtc->cursor_y = state->orig_dst.y1;
11818
11819         intel_plane->crtc_x = state->orig_dst.x1;
11820         intel_plane->crtc_y = state->orig_dst.y1;
11821         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11822         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11823         intel_plane->src_x = state->orig_src.x1;
11824         intel_plane->src_y = state->orig_src.y1;
11825         intel_plane->src_w = drm_rect_width(&state->orig_src);
11826         intel_plane->src_h = drm_rect_height(&state->orig_src);
11827         intel_plane->obj = obj;
11828
11829         if (fb != crtc->cursor->fb) {
11830                 crtc_w = drm_rect_width(&state->orig_dst);
11831                 crtc_h = drm_rect_height(&state->orig_dst);
11832                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11833         } else {
11834                 intel_crtc_update_cursor(crtc, state->visible);
11835
11836                 intel_frontbuffer_flip(crtc->dev,
11837                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11838
11839                 return 0;
11840         }
11841 }
11842
11843 static int
11844 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11845                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11846                           unsigned int crtc_w, unsigned int crtc_h,
11847                           uint32_t src_x, uint32_t src_y,
11848                           uint32_t src_w, uint32_t src_h)
11849 {
11850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11851         struct intel_plane_state state;
11852         int ret;
11853
11854         state.crtc = crtc;
11855         state.fb = fb;
11856
11857         /* sample coordinates in 16.16 fixed point */
11858         state.src.x1 = src_x;
11859         state.src.x2 = src_x + src_w;
11860         state.src.y1 = src_y;
11861         state.src.y2 = src_y + src_h;
11862
11863         /* integer pixels */
11864         state.dst.x1 = crtc_x;
11865         state.dst.x2 = crtc_x + crtc_w;
11866         state.dst.y1 = crtc_y;
11867         state.dst.y2 = crtc_y + crtc_h;
11868
11869         state.clip.x1 = 0;
11870         state.clip.y1 = 0;
11871         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11872         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11873
11874         state.orig_src = state.src;
11875         state.orig_dst = state.dst;
11876
11877         ret = intel_check_cursor_plane(plane, &state);
11878         if (ret)
11879                 return ret;
11880
11881         return intel_commit_cursor_plane(plane, &state);
11882 }
11883
11884 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11885         .update_plane = intel_cursor_plane_update,
11886         .disable_plane = intel_cursor_plane_disable,
11887         .destroy = intel_plane_destroy,
11888         .set_property = intel_plane_set_property,
11889 };
11890
11891 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11892                                                    int pipe)
11893 {
11894         struct intel_plane *cursor;
11895
11896         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11897         if (cursor == NULL)
11898                 return NULL;
11899
11900         cursor->can_scale = false;
11901         cursor->max_downscale = 1;
11902         cursor->pipe = pipe;
11903         cursor->plane = pipe;
11904         cursor->rotation = BIT(DRM_ROTATE_0);
11905
11906         drm_universal_plane_init(dev, &cursor->base, 0,
11907                                  &intel_cursor_plane_funcs,
11908                                  intel_cursor_formats,
11909                                  ARRAY_SIZE(intel_cursor_formats),
11910                                  DRM_PLANE_TYPE_CURSOR);
11911
11912         if (INTEL_INFO(dev)->gen >= 4) {
11913                 if (!dev->mode_config.rotation_property)
11914                         dev->mode_config.rotation_property =
11915                                 drm_mode_create_rotation_property(dev,
11916                                                         BIT(DRM_ROTATE_0) |
11917                                                         BIT(DRM_ROTATE_180));
11918                 if (dev->mode_config.rotation_property)
11919                         drm_object_attach_property(&cursor->base.base,
11920                                 dev->mode_config.rotation_property,
11921                                 cursor->rotation);
11922         }
11923
11924         return &cursor->base;
11925 }
11926
11927 static void intel_crtc_init(struct drm_device *dev, int pipe)
11928 {
11929         struct drm_i915_private *dev_priv = dev->dev_private;
11930         struct intel_crtc *intel_crtc;
11931         struct drm_plane *primary = NULL;
11932         struct drm_plane *cursor = NULL;
11933         int i, ret;
11934
11935         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11936         if (intel_crtc == NULL)
11937                 return;
11938
11939         primary = intel_primary_plane_create(dev, pipe);
11940         if (!primary)
11941                 goto fail;
11942
11943         cursor = intel_cursor_plane_create(dev, pipe);
11944         if (!cursor)
11945                 goto fail;
11946
11947         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11948                                         cursor, &intel_crtc_funcs);
11949         if (ret)
11950                 goto fail;
11951
11952         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11953         for (i = 0; i < 256; i++) {
11954                 intel_crtc->lut_r[i] = i;
11955                 intel_crtc->lut_g[i] = i;
11956                 intel_crtc->lut_b[i] = i;
11957         }
11958
11959         /*
11960          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11961          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11962          */
11963         intel_crtc->pipe = pipe;
11964         intel_crtc->plane = pipe;
11965         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11966                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11967                 intel_crtc->plane = !pipe;
11968         }
11969
11970         intel_crtc->cursor_base = ~0;
11971         intel_crtc->cursor_cntl = ~0;
11972         intel_crtc->cursor_size = ~0;
11973
11974         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11975                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11976         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11977         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11978
11979         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
11980
11981         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11982
11983         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11984         return;
11985
11986 fail:
11987         if (primary)
11988                 drm_plane_cleanup(primary);
11989         if (cursor)
11990                 drm_plane_cleanup(cursor);
11991         kfree(intel_crtc);
11992 }
11993
11994 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11995 {
11996         struct drm_encoder *encoder = connector->base.encoder;
11997         struct drm_device *dev = connector->base.dev;
11998
11999         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12000
12001         if (!encoder)
12002                 return INVALID_PIPE;
12003
12004         return to_intel_crtc(encoder->crtc)->pipe;
12005 }
12006
12007 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12008                                 struct drm_file *file)
12009 {
12010         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12011         struct drm_crtc *drmmode_crtc;
12012         struct intel_crtc *crtc;
12013
12014         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12015                 return -ENODEV;
12016
12017         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12018
12019         if (!drmmode_crtc) {
12020                 DRM_ERROR("no such CRTC id\n");
12021                 return -ENOENT;
12022         }
12023
12024         crtc = to_intel_crtc(drmmode_crtc);
12025         pipe_from_crtc_id->pipe = crtc->pipe;
12026
12027         return 0;
12028 }
12029
12030 static int intel_encoder_clones(struct intel_encoder *encoder)
12031 {
12032         struct drm_device *dev = encoder->base.dev;
12033         struct intel_encoder *source_encoder;
12034         int index_mask = 0;
12035         int entry = 0;
12036
12037         for_each_intel_encoder(dev, source_encoder) {
12038                 if (encoders_cloneable(encoder, source_encoder))
12039                         index_mask |= (1 << entry);
12040
12041                 entry++;
12042         }
12043
12044         return index_mask;
12045 }
12046
12047 static bool has_edp_a(struct drm_device *dev)
12048 {
12049         struct drm_i915_private *dev_priv = dev->dev_private;
12050
12051         if (!IS_MOBILE(dev))
12052                 return false;
12053
12054         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12055                 return false;
12056
12057         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12058                 return false;
12059
12060         return true;
12061 }
12062
12063 const char *intel_output_name(int output)
12064 {
12065         static const char *names[] = {
12066                 [INTEL_OUTPUT_UNUSED] = "Unused",
12067                 [INTEL_OUTPUT_ANALOG] = "Analog",
12068                 [INTEL_OUTPUT_DVO] = "DVO",
12069                 [INTEL_OUTPUT_SDVO] = "SDVO",
12070                 [INTEL_OUTPUT_LVDS] = "LVDS",
12071                 [INTEL_OUTPUT_TVOUT] = "TV",
12072                 [INTEL_OUTPUT_HDMI] = "HDMI",
12073                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12074                 [INTEL_OUTPUT_EDP] = "eDP",
12075                 [INTEL_OUTPUT_DSI] = "DSI",
12076                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12077         };
12078
12079         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12080                 return "Invalid";
12081
12082         return names[output];
12083 }
12084
12085 static bool intel_crt_present(struct drm_device *dev)
12086 {
12087         struct drm_i915_private *dev_priv = dev->dev_private;
12088
12089         if (INTEL_INFO(dev)->gen >= 9)
12090                 return false;
12091
12092         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12093                 return false;
12094
12095         if (IS_CHERRYVIEW(dev))
12096                 return false;
12097
12098         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12099                 return false;
12100
12101         return true;
12102 }
12103
12104 static void intel_setup_outputs(struct drm_device *dev)
12105 {
12106         struct drm_i915_private *dev_priv = dev->dev_private;
12107         struct intel_encoder *encoder;
12108         bool dpd_is_edp = false;
12109
12110         intel_lvds_init(dev);
12111
12112         if (intel_crt_present(dev))
12113                 intel_crt_init(dev);
12114
12115         if (HAS_DDI(dev)) {
12116                 int found;
12117
12118                 /* Haswell uses DDI functions to detect digital outputs */
12119                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12120                 /* DDI A only supports eDP */
12121                 if (found)
12122                         intel_ddi_init(dev, PORT_A);
12123
12124                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12125                  * register */
12126                 found = I915_READ(SFUSE_STRAP);
12127
12128                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12129                         intel_ddi_init(dev, PORT_B);
12130                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12131                         intel_ddi_init(dev, PORT_C);
12132                 if (found & SFUSE_STRAP_DDID_DETECTED)
12133                         intel_ddi_init(dev, PORT_D);
12134         } else if (HAS_PCH_SPLIT(dev)) {
12135                 int found;
12136                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12137
12138                 if (has_edp_a(dev))
12139                         intel_dp_init(dev, DP_A, PORT_A);
12140
12141                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12142                         /* PCH SDVOB multiplex with HDMIB */
12143                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12144                         if (!found)
12145                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12146                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12147                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12148                 }
12149
12150                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12151                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12152
12153                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12154                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12155
12156                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12157                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12158
12159                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12160                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12161         } else if (IS_VALLEYVIEW(dev)) {
12162                 /*
12163                  * The DP_DETECTED bit is the latched state of the DDC
12164                  * SDA pin at boot. However since eDP doesn't require DDC
12165                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12166                  * eDP ports may have been muxed to an alternate function.
12167                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12168                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12169                  * detect eDP ports.
12170                  */
12171                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12172                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12173                                         PORT_B);
12174                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12175                     intel_dp_is_edp(dev, PORT_B))
12176                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12177
12178                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12179                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12180                                         PORT_C);
12181                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12182                     intel_dp_is_edp(dev, PORT_C))
12183                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12184
12185                 if (IS_CHERRYVIEW(dev)) {
12186                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12187                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12188                                                 PORT_D);
12189                         /* eDP not supported on port D, so don't check VBT */
12190                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12191                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12192                 }
12193
12194                 intel_dsi_init(dev);
12195         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12196                 bool found = false;
12197
12198                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12199                         DRM_DEBUG_KMS("probing SDVOB\n");
12200                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12201                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12202                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12203                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12204                         }
12205
12206                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12207                                 intel_dp_init(dev, DP_B, PORT_B);
12208                 }
12209
12210                 /* Before G4X SDVOC doesn't have its own detect register */
12211
12212                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12213                         DRM_DEBUG_KMS("probing SDVOC\n");
12214                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12215                 }
12216
12217                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12218
12219                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12220                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12221                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12222                         }
12223                         if (SUPPORTS_INTEGRATED_DP(dev))
12224                                 intel_dp_init(dev, DP_C, PORT_C);
12225                 }
12226
12227                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12228                     (I915_READ(DP_D) & DP_DETECTED))
12229                         intel_dp_init(dev, DP_D, PORT_D);
12230         } else if (IS_GEN2(dev))
12231                 intel_dvo_init(dev);
12232
12233         if (SUPPORTS_TV(dev))
12234                 intel_tv_init(dev);
12235
12236         intel_edp_psr_init(dev);
12237
12238         for_each_intel_encoder(dev, encoder) {
12239                 encoder->base.possible_crtcs = encoder->crtc_mask;
12240                 encoder->base.possible_clones =
12241                         intel_encoder_clones(encoder);
12242         }
12243
12244         intel_init_pch_refclk(dev);
12245
12246         drm_helper_move_panel_connectors_to_head(dev);
12247 }
12248
12249 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12250 {
12251         struct drm_device *dev = fb->dev;
12252         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12253
12254         drm_framebuffer_cleanup(fb);
12255         mutex_lock(&dev->struct_mutex);
12256         WARN_ON(!intel_fb->obj->framebuffer_references--);
12257         drm_gem_object_unreference(&intel_fb->obj->base);
12258         mutex_unlock(&dev->struct_mutex);
12259         kfree(intel_fb);
12260 }
12261
12262 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12263                                                 struct drm_file *file,
12264                                                 unsigned int *handle)
12265 {
12266         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12267         struct drm_i915_gem_object *obj = intel_fb->obj;
12268
12269         return drm_gem_handle_create(file, &obj->base, handle);
12270 }
12271
12272 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12273         .destroy = intel_user_framebuffer_destroy,
12274         .create_handle = intel_user_framebuffer_create_handle,
12275 };
12276
12277 static int intel_framebuffer_init(struct drm_device *dev,
12278                                   struct intel_framebuffer *intel_fb,
12279                                   struct drm_mode_fb_cmd2 *mode_cmd,
12280                                   struct drm_i915_gem_object *obj)
12281 {
12282         int aligned_height;
12283         int pitch_limit;
12284         int ret;
12285
12286         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12287
12288         if (obj->tiling_mode == I915_TILING_Y) {
12289                 DRM_DEBUG("hardware does not support tiling Y\n");
12290                 return -EINVAL;
12291         }
12292
12293         if (mode_cmd->pitches[0] & 63) {
12294                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12295                           mode_cmd->pitches[0]);
12296                 return -EINVAL;
12297         }
12298
12299         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12300                 pitch_limit = 32*1024;
12301         } else if (INTEL_INFO(dev)->gen >= 4) {
12302                 if (obj->tiling_mode)
12303                         pitch_limit = 16*1024;
12304                 else
12305                         pitch_limit = 32*1024;
12306         } else if (INTEL_INFO(dev)->gen >= 3) {
12307                 if (obj->tiling_mode)
12308                         pitch_limit = 8*1024;
12309                 else
12310                         pitch_limit = 16*1024;
12311         } else
12312                 /* XXX DSPC is limited to 4k tiled */
12313                 pitch_limit = 8*1024;
12314
12315         if (mode_cmd->pitches[0] > pitch_limit) {
12316                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12317                           obj->tiling_mode ? "tiled" : "linear",
12318                           mode_cmd->pitches[0], pitch_limit);
12319                 return -EINVAL;
12320         }
12321
12322         if (obj->tiling_mode != I915_TILING_NONE &&
12323             mode_cmd->pitches[0] != obj->stride) {
12324                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12325                           mode_cmd->pitches[0], obj->stride);
12326                 return -EINVAL;
12327         }
12328
12329         /* Reject formats not supported by any plane early. */
12330         switch (mode_cmd->pixel_format) {
12331         case DRM_FORMAT_C8:
12332         case DRM_FORMAT_RGB565:
12333         case DRM_FORMAT_XRGB8888:
12334         case DRM_FORMAT_ARGB8888:
12335                 break;
12336         case DRM_FORMAT_XRGB1555:
12337         case DRM_FORMAT_ARGB1555:
12338                 if (INTEL_INFO(dev)->gen > 3) {
12339                         DRM_DEBUG("unsupported pixel format: %s\n",
12340                                   drm_get_format_name(mode_cmd->pixel_format));
12341                         return -EINVAL;
12342                 }
12343                 break;
12344         case DRM_FORMAT_XBGR8888:
12345         case DRM_FORMAT_ABGR8888:
12346         case DRM_FORMAT_XRGB2101010:
12347         case DRM_FORMAT_ARGB2101010:
12348         case DRM_FORMAT_XBGR2101010:
12349         case DRM_FORMAT_ABGR2101010:
12350                 if (INTEL_INFO(dev)->gen < 4) {
12351                         DRM_DEBUG("unsupported pixel format: %s\n",
12352                                   drm_get_format_name(mode_cmd->pixel_format));
12353                         return -EINVAL;
12354                 }
12355                 break;
12356         case DRM_FORMAT_YUYV:
12357         case DRM_FORMAT_UYVY:
12358         case DRM_FORMAT_YVYU:
12359         case DRM_FORMAT_VYUY:
12360                 if (INTEL_INFO(dev)->gen < 5) {
12361                         DRM_DEBUG("unsupported pixel format: %s\n",
12362                                   drm_get_format_name(mode_cmd->pixel_format));
12363                         return -EINVAL;
12364                 }
12365                 break;
12366         default:
12367                 DRM_DEBUG("unsupported pixel format: %s\n",
12368                           drm_get_format_name(mode_cmd->pixel_format));
12369                 return -EINVAL;
12370         }
12371
12372         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12373         if (mode_cmd->offsets[0] != 0)
12374                 return -EINVAL;
12375
12376         aligned_height = intel_align_height(dev, mode_cmd->height,
12377                                             obj->tiling_mode);
12378         /* FIXME drm helper for size checks (especially planar formats)? */
12379         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12380                 return -EINVAL;
12381
12382         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12383         intel_fb->obj = obj;
12384         intel_fb->obj->framebuffer_references++;
12385
12386         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12387         if (ret) {
12388                 DRM_ERROR("framebuffer init failed %d\n", ret);
12389                 return ret;
12390         }
12391
12392         return 0;
12393 }
12394
12395 static struct drm_framebuffer *
12396 intel_user_framebuffer_create(struct drm_device *dev,
12397                               struct drm_file *filp,
12398                               struct drm_mode_fb_cmd2 *mode_cmd)
12399 {
12400         struct drm_i915_gem_object *obj;
12401
12402         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12403                                                 mode_cmd->handles[0]));
12404         if (&obj->base == NULL)
12405                 return ERR_PTR(-ENOENT);
12406
12407         return intel_framebuffer_create(dev, mode_cmd, obj);
12408 }
12409
12410 #ifndef CONFIG_DRM_I915_FBDEV
12411 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12412 {
12413 }
12414 #endif
12415
12416 static const struct drm_mode_config_funcs intel_mode_funcs = {
12417         .fb_create = intel_user_framebuffer_create,
12418         .output_poll_changed = intel_fbdev_output_poll_changed,
12419 };
12420
12421 /* Set up chip specific display functions */
12422 static void intel_init_display(struct drm_device *dev)
12423 {
12424         struct drm_i915_private *dev_priv = dev->dev_private;
12425
12426         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12427                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12428         else if (IS_CHERRYVIEW(dev))
12429                 dev_priv->display.find_dpll = chv_find_best_dpll;
12430         else if (IS_VALLEYVIEW(dev))
12431                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12432         else if (IS_PINEVIEW(dev))
12433                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12434         else
12435                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12436
12437         if (HAS_DDI(dev)) {
12438                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12439                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12440                 dev_priv->display.crtc_compute_clock =
12441                         haswell_crtc_compute_clock;
12442                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12443                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12444                 dev_priv->display.off = ironlake_crtc_off;
12445                 if (INTEL_INFO(dev)->gen >= 9)
12446                         dev_priv->display.update_primary_plane =
12447                                 skylake_update_primary_plane;
12448                 else
12449                         dev_priv->display.update_primary_plane =
12450                                 ironlake_update_primary_plane;
12451         } else if (HAS_PCH_SPLIT(dev)) {
12452                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12453                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12454                 dev_priv->display.crtc_compute_clock =
12455                         ironlake_crtc_compute_clock;
12456                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12457                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12458                 dev_priv->display.off = ironlake_crtc_off;
12459                 dev_priv->display.update_primary_plane =
12460                         ironlake_update_primary_plane;
12461         } else if (IS_VALLEYVIEW(dev)) {
12462                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12463                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12464                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12465                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12466                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12467                 dev_priv->display.off = i9xx_crtc_off;
12468                 dev_priv->display.update_primary_plane =
12469                         i9xx_update_primary_plane;
12470         } else {
12471                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12472                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12473                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12474                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12475                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12476                 dev_priv->display.off = i9xx_crtc_off;
12477                 dev_priv->display.update_primary_plane =
12478                         i9xx_update_primary_plane;
12479         }
12480
12481         /* Returns the core display clock speed */
12482         if (IS_VALLEYVIEW(dev))
12483                 dev_priv->display.get_display_clock_speed =
12484                         valleyview_get_display_clock_speed;
12485         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12486                 dev_priv->display.get_display_clock_speed =
12487                         i945_get_display_clock_speed;
12488         else if (IS_I915G(dev))
12489                 dev_priv->display.get_display_clock_speed =
12490                         i915_get_display_clock_speed;
12491         else if (IS_I945GM(dev) || IS_845G(dev))
12492                 dev_priv->display.get_display_clock_speed =
12493                         i9xx_misc_get_display_clock_speed;
12494         else if (IS_PINEVIEW(dev))
12495                 dev_priv->display.get_display_clock_speed =
12496                         pnv_get_display_clock_speed;
12497         else if (IS_I915GM(dev))
12498                 dev_priv->display.get_display_clock_speed =
12499                         i915gm_get_display_clock_speed;
12500         else if (IS_I865G(dev))
12501                 dev_priv->display.get_display_clock_speed =
12502                         i865_get_display_clock_speed;
12503         else if (IS_I85X(dev))
12504                 dev_priv->display.get_display_clock_speed =
12505                         i855_get_display_clock_speed;
12506         else /* 852, 830 */
12507                 dev_priv->display.get_display_clock_speed =
12508                         i830_get_display_clock_speed;
12509
12510         if (IS_GEN5(dev)) {
12511                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12512         } else if (IS_GEN6(dev)) {
12513                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12514         } else if (IS_IVYBRIDGE(dev)) {
12515                 /* FIXME: detect B0+ stepping and use auto training */
12516                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12517                 dev_priv->display.modeset_global_resources =
12518                         ivb_modeset_global_resources;
12519         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12520                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12521         } else if (IS_VALLEYVIEW(dev)) {
12522                 dev_priv->display.modeset_global_resources =
12523                         valleyview_modeset_global_resources;
12524         }
12525
12526         /* Default just returns -ENODEV to indicate unsupported */
12527         dev_priv->display.queue_flip = intel_default_queue_flip;
12528
12529         switch (INTEL_INFO(dev)->gen) {
12530         case 2:
12531                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12532                 break;
12533
12534         case 3:
12535                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12536                 break;
12537
12538         case 4:
12539         case 5:
12540                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12541                 break;
12542
12543         case 6:
12544                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12545                 break;
12546         case 7:
12547         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12548                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12549                 break;
12550         }
12551
12552         intel_panel_init_backlight_funcs(dev);
12553
12554         mutex_init(&dev_priv->pps_mutex);
12555 }
12556
12557 /*
12558  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12559  * resume, or other times.  This quirk makes sure that's the case for
12560  * affected systems.
12561  */
12562 static void quirk_pipea_force(struct drm_device *dev)
12563 {
12564         struct drm_i915_private *dev_priv = dev->dev_private;
12565
12566         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12567         DRM_INFO("applying pipe a force quirk\n");
12568 }
12569
12570 static void quirk_pipeb_force(struct drm_device *dev)
12571 {
12572         struct drm_i915_private *dev_priv = dev->dev_private;
12573
12574         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12575         DRM_INFO("applying pipe b force quirk\n");
12576 }
12577
12578 /*
12579  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12580  */
12581 static void quirk_ssc_force_disable(struct drm_device *dev)
12582 {
12583         struct drm_i915_private *dev_priv = dev->dev_private;
12584         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12585         DRM_INFO("applying lvds SSC disable quirk\n");
12586 }
12587
12588 /*
12589  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12590  * brightness value
12591  */
12592 static void quirk_invert_brightness(struct drm_device *dev)
12593 {
12594         struct drm_i915_private *dev_priv = dev->dev_private;
12595         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12596         DRM_INFO("applying inverted panel brightness quirk\n");
12597 }
12598
12599 /* Some VBT's incorrectly indicate no backlight is present */
12600 static void quirk_backlight_present(struct drm_device *dev)
12601 {
12602         struct drm_i915_private *dev_priv = dev->dev_private;
12603         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12604         DRM_INFO("applying backlight present quirk\n");
12605 }
12606
12607 struct intel_quirk {
12608         int device;
12609         int subsystem_vendor;
12610         int subsystem_device;
12611         void (*hook)(struct drm_device *dev);
12612 };
12613
12614 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12615 struct intel_dmi_quirk {
12616         void (*hook)(struct drm_device *dev);
12617         const struct dmi_system_id (*dmi_id_list)[];
12618 };
12619
12620 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12621 {
12622         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12623         return 1;
12624 }
12625
12626 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12627         {
12628                 .dmi_id_list = &(const struct dmi_system_id[]) {
12629                         {
12630                                 .callback = intel_dmi_reverse_brightness,
12631                                 .ident = "NCR Corporation",
12632                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12633                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12634                                 },
12635                         },
12636                         { }  /* terminating entry */
12637                 },
12638                 .hook = quirk_invert_brightness,
12639         },
12640 };
12641
12642 static struct intel_quirk intel_quirks[] = {
12643         /* HP Mini needs pipe A force quirk (LP: #322104) */
12644         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12645
12646         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12647         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12648
12649         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12650         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12651
12652         /* 830 needs to leave pipe A & dpll A up */
12653         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12654
12655         /* 830 needs to leave pipe B & dpll B up */
12656         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12657
12658         /* Lenovo U160 cannot use SSC on LVDS */
12659         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12660
12661         /* Sony Vaio Y cannot use SSC on LVDS */
12662         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12663
12664         /* Acer Aspire 5734Z must invert backlight brightness */
12665         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12666
12667         /* Acer/eMachines G725 */
12668         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12669
12670         /* Acer/eMachines e725 */
12671         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12672
12673         /* Acer/Packard Bell NCL20 */
12674         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12675
12676         /* Acer Aspire 4736Z */
12677         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12678
12679         /* Acer Aspire 5336 */
12680         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12681
12682         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12683         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12684
12685         /* Acer C720 Chromebook (Core i3 4005U) */
12686         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12687
12688         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12689         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12690
12691         /* HP Chromebook 14 (Celeron 2955U) */
12692         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12693 };
12694
12695 static void intel_init_quirks(struct drm_device *dev)
12696 {
12697         struct pci_dev *d = dev->pdev;
12698         int i;
12699
12700         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12701                 struct intel_quirk *q = &intel_quirks[i];
12702
12703                 if (d->device == q->device &&
12704                     (d->subsystem_vendor == q->subsystem_vendor ||
12705                      q->subsystem_vendor == PCI_ANY_ID) &&
12706                     (d->subsystem_device == q->subsystem_device ||
12707                      q->subsystem_device == PCI_ANY_ID))
12708                         q->hook(dev);
12709         }
12710         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12711                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12712                         intel_dmi_quirks[i].hook(dev);
12713         }
12714 }
12715
12716 /* Disable the VGA plane that we never use */
12717 static void i915_disable_vga(struct drm_device *dev)
12718 {
12719         struct drm_i915_private *dev_priv = dev->dev_private;
12720         u8 sr1;
12721         u32 vga_reg = i915_vgacntrl_reg(dev);
12722
12723         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12724         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12725         outb(SR01, VGA_SR_INDEX);
12726         sr1 = inb(VGA_SR_DATA);
12727         outb(sr1 | 1<<5, VGA_SR_DATA);
12728         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12729         udelay(300);
12730
12731         /*
12732          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12733          * from S3 without preserving (some of?) the other bits.
12734          */
12735         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12736         POSTING_READ(vga_reg);
12737 }
12738
12739 void intel_modeset_init_hw(struct drm_device *dev)
12740 {
12741         intel_prepare_ddi(dev);
12742
12743         if (IS_VALLEYVIEW(dev))
12744                 vlv_update_cdclk(dev);
12745
12746         intel_init_clock_gating(dev);
12747
12748         intel_enable_gt_powersave(dev);
12749 }
12750
12751 void intel_modeset_init(struct drm_device *dev)
12752 {
12753         struct drm_i915_private *dev_priv = dev->dev_private;
12754         int sprite, ret;
12755         enum pipe pipe;
12756         struct intel_crtc *crtc;
12757
12758         drm_mode_config_init(dev);
12759
12760         dev->mode_config.min_width = 0;
12761         dev->mode_config.min_height = 0;
12762
12763         dev->mode_config.preferred_depth = 24;
12764         dev->mode_config.prefer_shadow = 1;
12765
12766         dev->mode_config.funcs = &intel_mode_funcs;
12767
12768         intel_init_quirks(dev);
12769
12770         intel_init_pm(dev);
12771
12772         if (INTEL_INFO(dev)->num_pipes == 0)
12773                 return;
12774
12775         intel_init_display(dev);
12776         intel_init_audio(dev);
12777
12778         if (IS_GEN2(dev)) {
12779                 dev->mode_config.max_width = 2048;
12780                 dev->mode_config.max_height = 2048;
12781         } else if (IS_GEN3(dev)) {
12782                 dev->mode_config.max_width = 4096;
12783                 dev->mode_config.max_height = 4096;
12784         } else {
12785                 dev->mode_config.max_width = 8192;
12786                 dev->mode_config.max_height = 8192;
12787         }
12788
12789         if (IS_845G(dev) || IS_I865G(dev)) {
12790                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12791                 dev->mode_config.cursor_height = 1023;
12792         } else if (IS_GEN2(dev)) {
12793                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12794                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12795         } else {
12796                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12797                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12798         }
12799
12800         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12801
12802         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12803                       INTEL_INFO(dev)->num_pipes,
12804                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12805
12806         for_each_pipe(dev_priv, pipe) {
12807                 intel_crtc_init(dev, pipe);
12808                 for_each_sprite(pipe, sprite) {
12809                         ret = intel_plane_init(dev, pipe, sprite);
12810                         if (ret)
12811                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12812                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12813                 }
12814         }
12815
12816         intel_init_dpio(dev);
12817
12818         intel_shared_dpll_init(dev);
12819
12820         /* save the BIOS value before clobbering it */
12821         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12822         /* Just disable it once at startup */
12823         i915_disable_vga(dev);
12824         intel_setup_outputs(dev);
12825
12826         /* Just in case the BIOS is doing something questionable. */
12827         intel_disable_fbc(dev);
12828
12829         drm_modeset_lock_all(dev);
12830         intel_modeset_setup_hw_state(dev, false);
12831         drm_modeset_unlock_all(dev);
12832
12833         for_each_intel_crtc(dev, crtc) {
12834                 if (!crtc->active)
12835                         continue;
12836
12837                 /*
12838                  * Note that reserving the BIOS fb up front prevents us
12839                  * from stuffing other stolen allocations like the ring
12840                  * on top.  This prevents some ugliness at boot time, and
12841                  * can even allow for smooth boot transitions if the BIOS
12842                  * fb is large enough for the active pipe configuration.
12843                  */
12844                 if (dev_priv->display.get_plane_config) {
12845                         dev_priv->display.get_plane_config(crtc,
12846                                                            &crtc->plane_config);
12847                         /*
12848                          * If the fb is shared between multiple heads, we'll
12849                          * just get the first one.
12850                          */
12851                         intel_find_plane_obj(crtc, &crtc->plane_config);
12852                 }
12853         }
12854 }
12855
12856 static void intel_enable_pipe_a(struct drm_device *dev)
12857 {
12858         struct intel_connector *connector;
12859         struct drm_connector *crt = NULL;
12860         struct intel_load_detect_pipe load_detect_temp;
12861         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12862
12863         /* We can't just switch on the pipe A, we need to set things up with a
12864          * proper mode and output configuration. As a gross hack, enable pipe A
12865          * by enabling the load detect pipe once. */
12866         list_for_each_entry(connector,
12867                             &dev->mode_config.connector_list,
12868                             base.head) {
12869                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12870                         crt = &connector->base;
12871                         break;
12872                 }
12873         }
12874
12875         if (!crt)
12876                 return;
12877
12878         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12879                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12880 }
12881
12882 static bool
12883 intel_check_plane_mapping(struct intel_crtc *crtc)
12884 {
12885         struct drm_device *dev = crtc->base.dev;
12886         struct drm_i915_private *dev_priv = dev->dev_private;
12887         u32 reg, val;
12888
12889         if (INTEL_INFO(dev)->num_pipes == 1)
12890                 return true;
12891
12892         reg = DSPCNTR(!crtc->plane);
12893         val = I915_READ(reg);
12894
12895         if ((val & DISPLAY_PLANE_ENABLE) &&
12896             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12897                 return false;
12898
12899         return true;
12900 }
12901
12902 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12903 {
12904         struct drm_device *dev = crtc->base.dev;
12905         struct drm_i915_private *dev_priv = dev->dev_private;
12906         u32 reg;
12907
12908         /* Clear any frame start delays used for debugging left by the BIOS */
12909         reg = PIPECONF(crtc->config.cpu_transcoder);
12910         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12911
12912         /* restore vblank interrupts to correct state */
12913         if (crtc->active) {
12914                 update_scanline_offset(crtc);
12915                 drm_vblank_on(dev, crtc->pipe);
12916         } else
12917                 drm_vblank_off(dev, crtc->pipe);
12918
12919         /* We need to sanitize the plane -> pipe mapping first because this will
12920          * disable the crtc (and hence change the state) if it is wrong. Note
12921          * that gen4+ has a fixed plane -> pipe mapping.  */
12922         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12923                 struct intel_connector *connector;
12924                 bool plane;
12925
12926                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12927                               crtc->base.base.id);
12928
12929                 /* Pipe has the wrong plane attached and the plane is active.
12930                  * Temporarily change the plane mapping and disable everything
12931                  * ...  */
12932                 plane = crtc->plane;
12933                 crtc->plane = !plane;
12934                 crtc->primary_enabled = true;
12935                 dev_priv->display.crtc_disable(&crtc->base);
12936                 crtc->plane = plane;
12937
12938                 /* ... and break all links. */
12939                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12940                                     base.head) {
12941                         if (connector->encoder->base.crtc != &crtc->base)
12942                                 continue;
12943
12944                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12945                         connector->base.encoder = NULL;
12946                 }
12947                 /* multiple connectors may have the same encoder:
12948                  *  handle them and break crtc link separately */
12949                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12950                                     base.head)
12951                         if (connector->encoder->base.crtc == &crtc->base) {
12952                                 connector->encoder->base.crtc = NULL;
12953                                 connector->encoder->connectors_active = false;
12954                         }
12955
12956                 WARN_ON(crtc->active);
12957                 crtc->base.enabled = false;
12958         }
12959
12960         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12961             crtc->pipe == PIPE_A && !crtc->active) {
12962                 /* BIOS forgot to enable pipe A, this mostly happens after
12963                  * resume. Force-enable the pipe to fix this, the update_dpms
12964                  * call below we restore the pipe to the right state, but leave
12965                  * the required bits on. */
12966                 intel_enable_pipe_a(dev);
12967         }
12968
12969         /* Adjust the state of the output pipe according to whether we
12970          * have active connectors/encoders. */
12971         intel_crtc_update_dpms(&crtc->base);
12972
12973         if (crtc->active != crtc->base.enabled) {
12974                 struct intel_encoder *encoder;
12975
12976                 /* This can happen either due to bugs in the get_hw_state
12977                  * functions or because the pipe is force-enabled due to the
12978                  * pipe A quirk. */
12979                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12980                               crtc->base.base.id,
12981                               crtc->base.enabled ? "enabled" : "disabled",
12982                               crtc->active ? "enabled" : "disabled");
12983
12984                 crtc->base.enabled = crtc->active;
12985
12986                 /* Because we only establish the connector -> encoder ->
12987                  * crtc links if something is active, this means the
12988                  * crtc is now deactivated. Break the links. connector
12989                  * -> encoder links are only establish when things are
12990                  *  actually up, hence no need to break them. */
12991                 WARN_ON(crtc->active);
12992
12993                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12994                         WARN_ON(encoder->connectors_active);
12995                         encoder->base.crtc = NULL;
12996                 }
12997         }
12998
12999         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13000                 /*
13001                  * We start out with underrun reporting disabled to avoid races.
13002                  * For correct bookkeeping mark this on active crtcs.
13003                  *
13004                  * Also on gmch platforms we dont have any hardware bits to
13005                  * disable the underrun reporting. Which means we need to start
13006                  * out with underrun reporting disabled also on inactive pipes,
13007                  * since otherwise we'll complain about the garbage we read when
13008                  * e.g. coming up after runtime pm.
13009                  *
13010                  * No protection against concurrent access is required - at
13011                  * worst a fifo underrun happens which also sets this to false.
13012                  */
13013                 crtc->cpu_fifo_underrun_disabled = true;
13014                 crtc->pch_fifo_underrun_disabled = true;
13015         }
13016 }
13017
13018 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13019 {
13020         struct intel_connector *connector;
13021         struct drm_device *dev = encoder->base.dev;
13022
13023         /* We need to check both for a crtc link (meaning that the
13024          * encoder is active and trying to read from a pipe) and the
13025          * pipe itself being active. */
13026         bool has_active_crtc = encoder->base.crtc &&
13027                 to_intel_crtc(encoder->base.crtc)->active;
13028
13029         if (encoder->connectors_active && !has_active_crtc) {
13030                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13031                               encoder->base.base.id,
13032                               encoder->base.name);
13033
13034                 /* Connector is active, but has no active pipe. This is
13035                  * fallout from our resume register restoring. Disable
13036                  * the encoder manually again. */
13037                 if (encoder->base.crtc) {
13038                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13039                                       encoder->base.base.id,
13040                                       encoder->base.name);
13041                         encoder->disable(encoder);
13042                         if (encoder->post_disable)
13043                                 encoder->post_disable(encoder);
13044                 }
13045                 encoder->base.crtc = NULL;
13046                 encoder->connectors_active = false;
13047
13048                 /* Inconsistent output/port/pipe state happens presumably due to
13049                  * a bug in one of the get_hw_state functions. Or someplace else
13050                  * in our code, like the register restore mess on resume. Clamp
13051                  * things to off as a safer default. */
13052                 list_for_each_entry(connector,
13053                                     &dev->mode_config.connector_list,
13054                                     base.head) {
13055                         if (connector->encoder != encoder)
13056                                 continue;
13057                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13058                         connector->base.encoder = NULL;
13059                 }
13060         }
13061         /* Enabled encoders without active connectors will be fixed in
13062          * the crtc fixup. */
13063 }
13064
13065 void i915_redisable_vga_power_on(struct drm_device *dev)
13066 {
13067         struct drm_i915_private *dev_priv = dev->dev_private;
13068         u32 vga_reg = i915_vgacntrl_reg(dev);
13069
13070         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13071                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13072                 i915_disable_vga(dev);
13073         }
13074 }
13075
13076 void i915_redisable_vga(struct drm_device *dev)
13077 {
13078         struct drm_i915_private *dev_priv = dev->dev_private;
13079
13080         /* This function can be called both from intel_modeset_setup_hw_state or
13081          * at a very early point in our resume sequence, where the power well
13082          * structures are not yet restored. Since this function is at a very
13083          * paranoid "someone might have enabled VGA while we were not looking"
13084          * level, just check if the power well is enabled instead of trying to
13085          * follow the "don't touch the power well if we don't need it" policy
13086          * the rest of the driver uses. */
13087         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13088                 return;
13089
13090         i915_redisable_vga_power_on(dev);
13091 }
13092
13093 static bool primary_get_hw_state(struct intel_crtc *crtc)
13094 {
13095         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13096
13097         if (!crtc->active)
13098                 return false;
13099
13100         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13101 }
13102
13103 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13104 {
13105         struct drm_i915_private *dev_priv = dev->dev_private;
13106         enum pipe pipe;
13107         struct intel_crtc *crtc;
13108         struct intel_encoder *encoder;
13109         struct intel_connector *connector;
13110         int i;
13111
13112         for_each_intel_crtc(dev, crtc) {
13113                 memset(&crtc->config, 0, sizeof(crtc->config));
13114
13115                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13116
13117                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13118                                                                  &crtc->config);
13119
13120                 crtc->base.enabled = crtc->active;
13121                 crtc->primary_enabled = primary_get_hw_state(crtc);
13122
13123                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13124                               crtc->base.base.id,
13125                               crtc->active ? "enabled" : "disabled");
13126         }
13127
13128         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13129                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13130
13131                 pll->on = pll->get_hw_state(dev_priv, pll,
13132                                             &pll->config.hw_state);
13133                 pll->active = 0;
13134                 pll->config.crtc_mask = 0;
13135                 for_each_intel_crtc(dev, crtc) {
13136                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13137                                 pll->active++;
13138                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13139                         }
13140                 }
13141
13142                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13143                               pll->name, pll->config.crtc_mask, pll->on);
13144
13145                 if (pll->config.crtc_mask)
13146                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13147         }
13148
13149         for_each_intel_encoder(dev, encoder) {
13150                 pipe = 0;
13151
13152                 if (encoder->get_hw_state(encoder, &pipe)) {
13153                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13154                         encoder->base.crtc = &crtc->base;
13155                         encoder->get_config(encoder, &crtc->config);
13156                 } else {
13157                         encoder->base.crtc = NULL;
13158                 }
13159
13160                 encoder->connectors_active = false;
13161                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13162                               encoder->base.base.id,
13163                               encoder->base.name,
13164                               encoder->base.crtc ? "enabled" : "disabled",
13165                               pipe_name(pipe));
13166         }
13167
13168         list_for_each_entry(connector, &dev->mode_config.connector_list,
13169                             base.head) {
13170                 if (connector->get_hw_state(connector)) {
13171                         connector->base.dpms = DRM_MODE_DPMS_ON;
13172                         connector->encoder->connectors_active = true;
13173                         connector->base.encoder = &connector->encoder->base;
13174                 } else {
13175                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13176                         connector->base.encoder = NULL;
13177                 }
13178                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13179                               connector->base.base.id,
13180                               connector->base.name,
13181                               connector->base.encoder ? "enabled" : "disabled");
13182         }
13183 }
13184
13185 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13186  * and i915 state tracking structures. */
13187 void intel_modeset_setup_hw_state(struct drm_device *dev,
13188                                   bool force_restore)
13189 {
13190         struct drm_i915_private *dev_priv = dev->dev_private;
13191         enum pipe pipe;
13192         struct intel_crtc *crtc;
13193         struct intel_encoder *encoder;
13194         int i;
13195
13196         intel_modeset_readout_hw_state(dev);
13197
13198         /*
13199          * Now that we have the config, copy it to each CRTC struct
13200          * Note that this could go away if we move to using crtc_config
13201          * checking everywhere.
13202          */
13203         for_each_intel_crtc(dev, crtc) {
13204                 if (crtc->active && i915.fastboot) {
13205                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13206                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13207                                       crtc->base.base.id);
13208                         drm_mode_debug_printmodeline(&crtc->base.mode);
13209                 }
13210         }
13211
13212         /* HW state is read out, now we need to sanitize this mess. */
13213         for_each_intel_encoder(dev, encoder) {
13214                 intel_sanitize_encoder(encoder);
13215         }
13216
13217         for_each_pipe(dev_priv, pipe) {
13218                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13219                 intel_sanitize_crtc(crtc);
13220                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13221         }
13222
13223         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13224                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13225
13226                 if (!pll->on || pll->active)
13227                         continue;
13228
13229                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13230
13231                 pll->disable(dev_priv, pll);
13232                 pll->on = false;
13233         }
13234
13235         if (IS_GEN9(dev))
13236                 skl_wm_get_hw_state(dev);
13237         else if (HAS_PCH_SPLIT(dev))
13238                 ilk_wm_get_hw_state(dev);
13239
13240         if (force_restore) {
13241                 i915_redisable_vga(dev);
13242
13243                 /*
13244                  * We need to use raw interfaces for restoring state to avoid
13245                  * checking (bogus) intermediate states.
13246                  */
13247                 for_each_pipe(dev_priv, pipe) {
13248                         struct drm_crtc *crtc =
13249                                 dev_priv->pipe_to_crtc_mapping[pipe];
13250
13251                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13252                                          crtc->primary->fb);
13253                 }
13254         } else {
13255                 intel_modeset_update_staged_output_state(dev);
13256         }
13257
13258         intel_modeset_check_state(dev);
13259 }
13260
13261 void intel_modeset_gem_init(struct drm_device *dev)
13262 {
13263         struct drm_crtc *c;
13264         struct drm_i915_gem_object *obj;
13265
13266         mutex_lock(&dev->struct_mutex);
13267         intel_init_gt_powersave(dev);
13268         mutex_unlock(&dev->struct_mutex);
13269
13270         intel_modeset_init_hw(dev);
13271
13272         intel_setup_overlay(dev);
13273
13274         /*
13275          * Make sure any fbs we allocated at startup are properly
13276          * pinned & fenced.  When we do the allocation it's too early
13277          * for this.
13278          */
13279         mutex_lock(&dev->struct_mutex);
13280         for_each_crtc(dev, c) {
13281                 obj = intel_fb_obj(c->primary->fb);
13282                 if (obj == NULL)
13283                         continue;
13284
13285                 if (intel_pin_and_fence_fb_obj(c->primary,
13286                                                c->primary->fb,
13287                                                NULL)) {
13288                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13289                                   to_intel_crtc(c)->pipe);
13290                         drm_framebuffer_unreference(c->primary->fb);
13291                         c->primary->fb = NULL;
13292                 }
13293         }
13294         mutex_unlock(&dev->struct_mutex);
13295 }
13296
13297 void intel_connector_unregister(struct intel_connector *intel_connector)
13298 {
13299         struct drm_connector *connector = &intel_connector->base;
13300
13301         intel_panel_destroy_backlight(connector);
13302         drm_connector_unregister(connector);
13303 }
13304
13305 void intel_modeset_cleanup(struct drm_device *dev)
13306 {
13307         struct drm_i915_private *dev_priv = dev->dev_private;
13308         struct drm_connector *connector;
13309
13310         /*
13311          * Interrupts and polling as the first thing to avoid creating havoc.
13312          * Too much stuff here (turning of rps, connectors, ...) would
13313          * experience fancy races otherwise.
13314          */
13315         intel_irq_uninstall(dev_priv);
13316
13317         /*
13318          * Due to the hpd irq storm handling the hotplug work can re-arm the
13319          * poll handlers. Hence disable polling after hpd handling is shut down.
13320          */
13321         drm_kms_helper_poll_fini(dev);
13322
13323         mutex_lock(&dev->struct_mutex);
13324
13325         intel_unregister_dsm_handler();
13326
13327         intel_disable_fbc(dev);
13328
13329         intel_disable_gt_powersave(dev);
13330
13331         ironlake_teardown_rc6(dev);
13332
13333         mutex_unlock(&dev->struct_mutex);
13334
13335         /* flush any delayed tasks or pending work */
13336         flush_scheduled_work();
13337
13338         /* destroy the backlight and sysfs files before encoders/connectors */
13339         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13340                 struct intel_connector *intel_connector;
13341
13342                 intel_connector = to_intel_connector(connector);
13343                 intel_connector->unregister(intel_connector);
13344         }
13345
13346         drm_mode_config_cleanup(dev);
13347
13348         intel_cleanup_overlay(dev);
13349
13350         mutex_lock(&dev->struct_mutex);
13351         intel_cleanup_gt_powersave(dev);
13352         mutex_unlock(&dev->struct_mutex);
13353 }
13354
13355 /*
13356  * Return which encoder is currently attached for connector.
13357  */
13358 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13359 {
13360         return &intel_attached_encoder(connector)->base;
13361 }
13362
13363 void intel_connector_attach_encoder(struct intel_connector *connector,
13364                                     struct intel_encoder *encoder)
13365 {
13366         connector->encoder = encoder;
13367         drm_mode_connector_attach_encoder(&connector->base,
13368                                           &encoder->base);
13369 }
13370
13371 /*
13372  * set vga decode state - true == enable VGA decode
13373  */
13374 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13375 {
13376         struct drm_i915_private *dev_priv = dev->dev_private;
13377         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13378         u16 gmch_ctrl;
13379
13380         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13381                 DRM_ERROR("failed to read control word\n");
13382                 return -EIO;
13383         }
13384
13385         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13386                 return 0;
13387
13388         if (state)
13389                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13390         else
13391                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13392
13393         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13394                 DRM_ERROR("failed to write control word\n");
13395                 return -EIO;
13396         }
13397
13398         return 0;
13399 }
13400
13401 struct intel_display_error_state {
13402
13403         u32 power_well_driver;
13404
13405         int num_transcoders;
13406
13407         struct intel_cursor_error_state {
13408                 u32 control;
13409                 u32 position;
13410                 u32 base;
13411                 u32 size;
13412         } cursor[I915_MAX_PIPES];
13413
13414         struct intel_pipe_error_state {
13415                 bool power_domain_on;
13416                 u32 source;
13417                 u32 stat;
13418         } pipe[I915_MAX_PIPES];
13419
13420         struct intel_plane_error_state {
13421                 u32 control;
13422                 u32 stride;
13423                 u32 size;
13424                 u32 pos;
13425                 u32 addr;
13426                 u32 surface;
13427                 u32 tile_offset;
13428         } plane[I915_MAX_PIPES];
13429
13430         struct intel_transcoder_error_state {
13431                 bool power_domain_on;
13432                 enum transcoder cpu_transcoder;
13433
13434                 u32 conf;
13435
13436                 u32 htotal;
13437                 u32 hblank;
13438                 u32 hsync;
13439                 u32 vtotal;
13440                 u32 vblank;
13441                 u32 vsync;
13442         } transcoder[4];
13443 };
13444
13445 struct intel_display_error_state *
13446 intel_display_capture_error_state(struct drm_device *dev)
13447 {
13448         struct drm_i915_private *dev_priv = dev->dev_private;
13449         struct intel_display_error_state *error;
13450         int transcoders[] = {
13451                 TRANSCODER_A,
13452                 TRANSCODER_B,
13453                 TRANSCODER_C,
13454                 TRANSCODER_EDP,
13455         };
13456         int i;
13457
13458         if (INTEL_INFO(dev)->num_pipes == 0)
13459                 return NULL;
13460
13461         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13462         if (error == NULL)
13463                 return NULL;
13464
13465         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13466                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13467
13468         for_each_pipe(dev_priv, i) {
13469                 error->pipe[i].power_domain_on =
13470                         __intel_display_power_is_enabled(dev_priv,
13471                                                          POWER_DOMAIN_PIPE(i));
13472                 if (!error->pipe[i].power_domain_on)
13473                         continue;
13474
13475                 error->cursor[i].control = I915_READ(CURCNTR(i));
13476                 error->cursor[i].position = I915_READ(CURPOS(i));
13477                 error->cursor[i].base = I915_READ(CURBASE(i));
13478
13479                 error->plane[i].control = I915_READ(DSPCNTR(i));
13480                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13481                 if (INTEL_INFO(dev)->gen <= 3) {
13482                         error->plane[i].size = I915_READ(DSPSIZE(i));
13483                         error->plane[i].pos = I915_READ(DSPPOS(i));
13484                 }
13485                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13486                         error->plane[i].addr = I915_READ(DSPADDR(i));
13487                 if (INTEL_INFO(dev)->gen >= 4) {
13488                         error->plane[i].surface = I915_READ(DSPSURF(i));
13489                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13490                 }
13491
13492                 error->pipe[i].source = I915_READ(PIPESRC(i));
13493
13494                 if (HAS_GMCH_DISPLAY(dev))
13495                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13496         }
13497
13498         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13499         if (HAS_DDI(dev_priv->dev))
13500                 error->num_transcoders++; /* Account for eDP. */
13501
13502         for (i = 0; i < error->num_transcoders; i++) {
13503                 enum transcoder cpu_transcoder = transcoders[i];
13504
13505                 error->transcoder[i].power_domain_on =
13506                         __intel_display_power_is_enabled(dev_priv,
13507                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13508                 if (!error->transcoder[i].power_domain_on)
13509                         continue;
13510
13511                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13512
13513                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13514                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13515                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13516                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13517                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13518                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13519                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13520         }
13521
13522         return error;
13523 }
13524
13525 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13526
13527 void
13528 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13529                                 struct drm_device *dev,
13530                                 struct intel_display_error_state *error)
13531 {
13532         struct drm_i915_private *dev_priv = dev->dev_private;
13533         int i;
13534
13535         if (!error)
13536                 return;
13537
13538         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13539         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13540                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13541                            error->power_well_driver);
13542         for_each_pipe(dev_priv, i) {
13543                 err_printf(m, "Pipe [%d]:\n", i);
13544                 err_printf(m, "  Power: %s\n",
13545                            error->pipe[i].power_domain_on ? "on" : "off");
13546                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13547                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13548
13549                 err_printf(m, "Plane [%d]:\n", i);
13550                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13551                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13552                 if (INTEL_INFO(dev)->gen <= 3) {
13553                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13554                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13555                 }
13556                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13557                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13558                 if (INTEL_INFO(dev)->gen >= 4) {
13559                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13560                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13561                 }
13562
13563                 err_printf(m, "Cursor [%d]:\n", i);
13564                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13565                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13566                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13567         }
13568
13569         for (i = 0; i < error->num_transcoders; i++) {
13570                 err_printf(m, "CPU transcoder: %c\n",
13571                            transcoder_name(error->transcoder[i].cpu_transcoder));
13572                 err_printf(m, "  Power: %s\n",
13573                            error->transcoder[i].power_domain_on ? "on" : "off");
13574                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13575                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13576                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13577                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13578                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13579                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13580                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13581         }
13582 }
13583
13584 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13585 {
13586         struct intel_crtc *crtc;
13587
13588         for_each_intel_crtc(dev, crtc) {
13589                 struct intel_unpin_work *work;
13590
13591                 spin_lock_irq(&dev->event_lock);
13592
13593                 work = crtc->unpin_work;
13594
13595                 if (work && work->event &&
13596                     work->event->base.file_priv == file) {
13597                         kfree(work->event);
13598                         work->event = NULL;
13599                 }
13600
13601                 spin_unlock_irq(&dev->event_lock);
13602         }
13603 }