drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74         intel_p2_t          p2;
  75 };
  76
  77 int
  78 intel_pch_rawclk(struct drm_device *dev)
  79 {
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81
  82         WARN_ON(!HAS_PCH_SPLIT(dev));
  83
  84         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  85 }
  86
  87 static inline u32 /* units of 100MHz */
  88 intel_fdi_link_freq(struct drm_device *dev)
  89 {
  90         if (IS_GEN5(dev)) {
  91                 struct drm_i915_private *dev_priv = dev->dev_private;
  92                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  93         } else
  94                 return 27;
  95 }
  96
  97 static const intel_limit_t intel_limits_i8xx_dac = {
  98         .dot = { .min = 25000, .max = 350000 },
  99         .vco = { .min = 908000, .max = 1512000 },
 100         .n = { .min = 2, .max = 16 },
 101         .m = { .min = 96, .max = 140 },
 102         .m1 = { .min = 18, .max = 26 },
 103         .m2 = { .min = 6, .max = 16 },
 104         .p = { .min = 4, .max = 128 },
 105         .p1 = { .min = 2, .max = 33 },
 106         .p2 = { .dot_limit = 165000,
 107                 .p2_slow = 4, .p2_fast = 2 },
 108 };
 109
 110 static const intel_limit_t intel_limits_i8xx_dvo = {
 111         .dot = { .min = 25000, .max = 350000 },
 112         .vco = { .min = 908000, .max = 1512000 },
 113         .n = { .min = 2, .max = 16 },
 114         .m = { .min = 96, .max = 140 },
 115         .m1 = { .min = 18, .max = 26 },
 116         .m2 = { .min = 6, .max = 16 },
 117         .p = { .min = 4, .max = 128 },
 118         .p1 = { .min = 2, .max = 33 },
 119         .p2 = { .dot_limit = 165000,
 120                 .p2_slow = 4, .p2_fast = 4 },
 121 };
 122
 123 static const intel_limit_t intel_limits_i8xx_lvds = {
 124         .dot = { .min = 25000, .max = 350000 },
 125         .vco = { .min = 908000, .max = 1512000 },
 126         .n = { .min = 2, .max = 16 },
 127         .m = { .min = 96, .max = 140 },
 128         .m1 = { .min = 18, .max = 26 },
 129         .m2 = { .min = 6, .max = 16 },
 130         .p = { .min = 4, .max = 128 },
 131         .p1 = { .min = 1, .max = 6 },
 132         .p2 = { .dot_limit = 165000,
 133                 .p2_slow = 14, .p2_fast = 7 },
 134 };
 135
 136 static const intel_limit_t intel_limits_i9xx_sdvo = {
 137         .dot = { .min = 20000, .max = 400000 },
 138         .vco = { .min = 1400000, .max = 2800000 },
 139         .n = { .min = 1, .max = 6 },
 140         .m = { .min = 70, .max = 120 },
 141         .m1 = { .min = 8, .max = 18 },
 142         .m2 = { .min = 3, .max = 7 },
 143         .p = { .min = 5, .max = 80 },
 144         .p1 = { .min = 1, .max = 8 },
 145         .p2 = { .dot_limit = 200000,
 146                 .p2_slow = 10, .p2_fast = 5 },
 147 };
 148
 149 static const intel_limit_t intel_limits_i9xx_lvds = {
 150         .dot = { .min = 20000, .max = 400000 },
 151         .vco = { .min = 1400000, .max = 2800000 },
 152         .n = { .min = 1, .max = 6 },
 153         .m = { .min = 70, .max = 120 },
 154         .m1 = { .min = 8, .max = 18 },
 155         .m2 = { .min = 3, .max = 7 },
 156         .p = { .min = 7, .max = 98 },
 157         .p1 = { .min = 1, .max = 8 },
 158         .p2 = { .dot_limit = 112000,
 159                 .p2_slow = 14, .p2_fast = 7 },
 160 };
 161
 162
 163 static const intel_limit_t intel_limits_g4x_sdvo = {
 164         .dot = { .min = 25000, .max = 270000 },
 165         .vco = { .min = 1750000, .max = 3500000},
 166         .n = { .min = 1, .max = 4 },
 167         .m = { .min = 104, .max = 138 },
 168         .m1 = { .min = 17, .max = 23 },
 169         .m2 = { .min = 5, .max = 11 },
 170         .p = { .min = 10, .max = 30 },
 171         .p1 = { .min = 1, .max = 3},
 172         .p2 = { .dot_limit = 270000,
 173                 .p2_slow = 10,
 174                 .p2_fast = 10
 175         },
 176 };
 177
 178 static const intel_limit_t intel_limits_g4x_hdmi = {
 179         .dot = { .min = 22000, .max = 400000 },
 180         .vco = { .min = 1750000, .max = 3500000},
 181         .n = { .min = 1, .max = 4 },
 182         .m = { .min = 104, .max = 138 },
 183         .m1 = { .min = 16, .max = 23 },
 184         .m2 = { .min = 5, .max = 11 },
 185         .p = { .min = 5, .max = 80 },
 186         .p1 = { .min = 1, .max = 8},
 187         .p2 = { .dot_limit = 165000,
 188                 .p2_slow = 10, .p2_fast = 5 },
 189 };
 190
 191 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 192         .dot = { .min = 20000, .max = 115000 },
 193         .vco = { .min = 1750000, .max = 3500000 },
 194         .n = { .min = 1, .max = 3 },
 195         .m = { .min = 104, .max = 138 },
 196         .m1 = { .min = 17, .max = 23 },
 197         .m2 = { .min = 5, .max = 11 },
 198         .p = { .min = 28, .max = 112 },
 199         .p1 = { .min = 2, .max = 8 },
 200         .p2 = { .dot_limit = 0,
 201                 .p2_slow = 14, .p2_fast = 14
 202         },
 203 };
 204
 205 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 206         .dot = { .min = 80000, .max = 224000 },
 207         .vco = { .min = 1750000, .max = 3500000 },
 208         .n = { .min = 1, .max = 3 },
 209         .m = { .min = 104, .max = 138 },
 210         .m1 = { .min = 17, .max = 23 },
 211         .m2 = { .min = 5, .max = 11 },
 212         .p = { .min = 14, .max = 42 },
 213         .p1 = { .min = 2, .max = 6 },
 214         .p2 = { .dot_limit = 0,
 215                 .p2_slow = 7, .p2_fast = 7
 216         },
 217 };
 218
 219 static const intel_limit_t intel_limits_pineview_sdvo = {
 220         .dot = { .min = 20000, .max = 400000},
 221         .vco = { .min = 1700000, .max = 3500000 },
 222         /* Pineview's Ncounter is a ring counter */
 223         .n = { .min = 3, .max = 6 },
 224         .m = { .min = 2, .max = 256 },
 225         /* Pineview only has one combined m divider, which we treat as m2. */
 226         .m1 = { .min = 0, .max = 0 },
 227         .m2 = { .min = 0, .max = 254 },
 228         .p = { .min = 5, .max = 80 },
 229         .p1 = { .min = 1, .max = 8 },
 230         .p2 = { .dot_limit = 200000,
 231                 .p2_slow = 10, .p2_fast = 5 },
 232 };
 233
 234 static const intel_limit_t intel_limits_pineview_lvds = {
 235         .dot = { .min = 20000, .max = 400000 },
 236         .vco = { .min = 1700000, .max = 3500000 },
 237         .n = { .min = 3, .max = 6 },
 238         .m = { .min = 2, .max = 256 },
 239         .m1 = { .min = 0, .max = 0 },
 240         .m2 = { .min = 0, .max = 254 },
 241         .p = { .min = 7, .max = 112 },
 242         .p1 = { .min = 1, .max = 8 },
 243         .p2 = { .dot_limit = 112000,
 244                 .p2_slow = 14, .p2_fast = 14 },
 245 };
 246
 247 /* Ironlake / Sandybridge
 248  *
 249  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 250  * the range value for them is (actual_value - 2).
 251  */
 252 static const intel_limit_t intel_limits_ironlake_dac = {
 253         .dot = { .min = 25000, .max = 350000 },
 254         .vco = { .min = 1760000, .max = 3510000 },
 255         .n = { .min = 1, .max = 5 },
 256         .m = { .min = 79, .max = 127 },
 257         .m1 = { .min = 12, .max = 22 },
 258         .m2 = { .min = 5, .max = 9 },
 259         .p = { .min = 5, .max = 80 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 225000,
 262                 .p2_slow = 10, .p2_fast = 5 },
 263 };
 264
 265 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 266         .dot = { .min = 25000, .max = 350000 },
 267         .vco = { .min = 1760000, .max = 3510000 },
 268         .n = { .min = 1, .max = 3 },
 269         .m = { .min = 79, .max = 118 },
 270         .m1 = { .min = 12, .max = 22 },
 271         .m2 = { .min = 5, .max = 9 },
 272         .p = { .min = 28, .max = 112 },
 273         .p1 = { .min = 2, .max = 8 },
 274         .p2 = { .dot_limit = 225000,
 275                 .p2_slow = 14, .p2_fast = 14 },
 276 };
 277
 278 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 279         .dot = { .min = 25000, .max = 350000 },
 280         .vco = { .min = 1760000, .max = 3510000 },
 281         .n = { .min = 1, .max = 3 },
 282         .m = { .min = 79, .max = 127 },
 283         .m1 = { .min = 12, .max = 22 },
 284         .m2 = { .min = 5, .max = 9 },
 285         .p = { .min = 14, .max = 56 },
 286         .p1 = { .min = 2, .max = 8 },
 287         .p2 = { .dot_limit = 225000,
 288                 .p2_slow = 7, .p2_fast = 7 },
 289 };
 290
 291 /* LVDS 100mhz refclk limits. */
 292 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 2 },
 296         .m = { .min = 79, .max = 126 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 28, .max = 112 },
 300         .p1 = { .min = 2, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 14, .p2_fast = 14 },
 303 };
 304
 305 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 306         .dot = { .min = 25000, .max = 350000 },
 307         .vco = { .min = 1760000, .max = 3510000 },
 308         .n = { .min = 1, .max = 3 },
 309         .m = { .min = 79, .max = 126 },
 310         .m1 = { .min = 12, .max = 22 },
 311         .m2 = { .min = 5, .max = 9 },
 312         .p = { .min = 14, .max = 42 },
 313         .p1 = { .min = 2, .max = 6 },
 314         .p2 = { .dot_limit = 225000,
 315                 .p2_slow = 7, .p2_fast = 7 },
 316 };
 317
 318 static const intel_limit_t intel_limits_vlv = {
 319          /*
 320           * These are the data rate limits (measured in fast clocks)
 321           * since those are the strictest limits we have. The fast
 322           * clock and actual rate limits are more relaxed, so checking
 323           * them would make no difference.
 324           */
 325         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 326         .vco = { .min = 4000000, .max = 6000000 },
 327         .n = { .min = 1, .max = 7 },
 328         .m1 = { .min = 2, .max = 3 },
 329         .m2 = { .min = 11, .max = 156 },
 330         .p1 = { .min = 2, .max = 3 },
 331         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 332 };
 333
 334 static const intel_limit_t intel_limits_chv = {
 335         /*
 336          * These are the data rate limits (measured in fast clocks)
 337          * since those are the strictest limits we have.  The fast
 338          * clock and actual rate limits are more relaxed, so checking
 339          * them would make no difference.
 340          */
 341         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 342         .vco = { .min = 4860000, .max = 6700000 },
 343         .n = { .min = 1, .max = 1 },
 344         .m1 = { .min = 2, .max = 2 },
 345         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 346         .p1 = { .min = 2, .max = 4 },
 347         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 348 };
 349
 350 static void vlv_clock(int refclk, intel_clock_t *clock)
 351 {
 352         clock->m = clock->m1 * clock->m2;
 353         clock->p = clock->p1 * clock->p2;
 354         if (WARN_ON(clock->n == 0 || clock->p == 0))
 355                 return;
 356         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 357         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 358 }
 359
 360 /**
 361  * Returns whether any output on the specified pipe is of the specified type
 362  */
 363 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         struct intel_encoder *encoder;
 367
 368         for_each_encoder_on_crtc(dev, crtc, encoder)
 369                 if (encoder->type == type)
 370                         return true;
 371
 372         return false;
 373 }
 374
 375 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 376                                                 int refclk)
 377 {
 378         struct drm_device *dev = crtc->dev;
 379         const intel_limit_t *limit;
 380
 381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 382                 if (intel_is_dual_link_lvds(dev)) {
 383                         if (refclk == 100000)
 384                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 385                         else
 386                                 limit = &intel_limits_ironlake_dual_lvds;
 387                 } else {
 388                         if (refclk == 100000)
 389                                 limit = &intel_limits_ironlake_single_lvds_100m;
 390                         else
 391                                 limit = &intel_limits_ironlake_single_lvds;
 392                 }
 393         } else
 394                 limit = &intel_limits_ironlake_dac;
 395
 396         return limit;
 397 }
 398
 399 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 400 {
 401         struct drm_device *dev = crtc->dev;
 402         const intel_limit_t *limit;
 403
 404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 405                 if (intel_is_dual_link_lvds(dev))
 406                         limit = &intel_limits_g4x_dual_channel_lvds;
 407                 else
 408                         limit = &intel_limits_g4x_single_channel_lvds;
 409         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 410                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 411                 limit = &intel_limits_g4x_hdmi;
 412         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 413                 limit = &intel_limits_g4x_sdvo;
 414         } else /* The option is for other outputs */
 415                 limit = &intel_limits_i9xx_sdvo;
 416
 417         return limit;
 418 }
 419
 420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 421 {
 422         struct drm_device *dev = crtc->dev;
 423         const intel_limit_t *limit;
 424
 425         if (HAS_PCH_SPLIT(dev))
 426                 limit = intel_ironlake_limit(crtc, refclk);
 427         else if (IS_G4X(dev)) {
 428                 limit = intel_g4x_limit(crtc);
 429         } else if (IS_PINEVIEW(dev)) {
 430                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 431                         limit = &intel_limits_pineview_lvds;
 432                 else
 433                         limit = &intel_limits_pineview_sdvo;
 434         } else if (IS_CHERRYVIEW(dev)) {
 435                 limit = &intel_limits_chv;
 436         } else if (IS_VALLEYVIEW(dev)) {
 437                 limit = &intel_limits_vlv;
 438         } else if (!IS_GEN2(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_i9xx_lvds;
 441                 else
 442                         limit = &intel_limits_i9xx_sdvo;
 443         } else {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 445                         limit = &intel_limits_i8xx_lvds;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 447                         limit = &intel_limits_i8xx_dvo;
 448                 else
 449                         limit = &intel_limits_i8xx_dac;
 450         }
 451         return limit;
 452 }
 453
 454 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 455 static void pineview_clock(int refclk, intel_clock_t *clock)
 456 {
 457         clock->m = clock->m2 + 2;
 458         clock->p = clock->p1 * clock->p2;
 459         if (WARN_ON(clock->n == 0 || clock->p == 0))
 460                 return;
 461         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 462         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 463 }
 464
 465 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 466 {
 467         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 468 }
 469
 470 static void i9xx_clock(int refclk, intel_clock_t *clock)
 471 {
 472         clock->m = i9xx_dpll_compute_m(clock);
 473         clock->p = clock->p1 * clock->p2;
 474         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 475                 return;
 476         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 477         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 478 }
 479
 480 static void chv_clock(int refclk, intel_clock_t *clock)
 481 {
 482         clock->m = clock->m1 * clock->m2;
 483         clock->p = clock->p1 * clock->p2;
 484         if (WARN_ON(clock->n == 0 || clock->p == 0))
 485                 return;
 486         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 487                         clock->n << 22);
 488         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 489 }
 490
 491 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 492 /**
 493  * Returns whether the given set of divisors are valid for a given refclk with
 494  * the given connectors.
 495  */
 496
 497 static bool intel_PLL_is_valid(struct drm_device *dev,
 498                                const intel_limit_t *limit,
 499                                const intel_clock_t *clock)
 500 {
 501         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 502                 INTELPllInvalid("n out of range\n");
 503         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 504                 INTELPllInvalid("p1 out of range\n");
 505         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 506                 INTELPllInvalid("m2 out of range\n");
 507         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 508                 INTELPllInvalid("m1 out of range\n");
 509
 510         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 511                 if (clock->m1 <= clock->m2)
 512                         INTELPllInvalid("m1 <= m2\n");
 513
 514         if (!IS_VALLEYVIEW(dev)) {
 515                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 516                         INTELPllInvalid("p out of range\n");
 517                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 518                         INTELPllInvalid("m out of range\n");
 519         }
 520
 521         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 522                 INTELPllInvalid("vco out of range\n");
 523         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 524          * connector, etc., rather than just a single range.
 525          */
 526         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 527                 INTELPllInvalid("dot out of range\n");
 528
 529         return true;
 530 }
 531
 532 static bool
 533 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 534                     int target, int refclk, intel_clock_t *match_clock,
 535                     intel_clock_t *best_clock)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         intel_clock_t clock;
 539         int err = target;
 540
 541         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 542                 /*
 543                  * For LVDS just rely on its current settings for dual-channel.
 544                  * We haven't figured out how to reliably set up different
 545                  * single/dual channel state, if we even can.
 546                  */
 547                 if (intel_is_dual_link_lvds(dev))
 548                         clock.p2 = limit->p2.p2_fast;
 549                 else
 550                         clock.p2 = limit->p2.p2_slow;
 551         } else {
 552                 if (target < limit->p2.dot_limit)
 553                         clock.p2 = limit->p2.p2_slow;
 554                 else
 555                         clock.p2 = limit->p2.p2_fast;
 556         }
 557
 558         memset(best_clock, 0, sizeof(*best_clock));
 559
 560         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 561              clock.m1++) {
 562                 for (clock.m2 = limit->m2.min;
 563                      clock.m2 <= limit->m2.max; clock.m2++) {
 564                         if (clock.m2 >= clock.m1)
 565                                 break;
 566                         for (clock.n = limit->n.min;
 567                              clock.n <= limit->n.max; clock.n++) {
 568                                 for (clock.p1 = limit->p1.min;
 569                                         clock.p1 <= limit->p1.max; clock.p1++) {
 570                                         int this_err;
 571
 572                                         i9xx_clock(refclk, &clock);
 573                                         if (!intel_PLL_is_valid(dev, limit,
 574                                                                 &clock))
 575                                                 continue;
 576                                         if (match_clock &&
 577                                             clock.p != match_clock->p)
 578                                                 continue;
 579
 580                                         this_err = abs(clock.dot - target);
 581                                         if (this_err < err) {
 582                                                 *best_clock = clock;
 583                                                 err = this_err;
 584                                         }
 585                                 }
 586                         }
 587                 }
 588         }
 589
 590         return (err != target);
 591 }
 592
 593 static bool
 594 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 595                    int target, int refclk, intel_clock_t *match_clock,
 596                    intel_clock_t *best_clock)
 597 {
 598         struct drm_device *dev = crtc->dev;
 599         intel_clock_t clock;
 600         int err = target;
 601
 602         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 603                 /*
 604                  * For LVDS just rely on its current settings for dual-channel.
 605                  * We haven't figured out how to reliably set up different
 606                  * single/dual channel state, if we even can.
 607                  */
 608                 if (intel_is_dual_link_lvds(dev))
 609                         clock.p2 = limit->p2.p2_fast;
 610                 else
 611                         clock.p2 = limit->p2.p2_slow;
 612         } else {
 613                 if (target < limit->p2.dot_limit)
 614                         clock.p2 = limit->p2.p2_slow;
 615                 else
 616                         clock.p2 = limit->p2.p2_fast;
 617         }
 618
 619         memset(best_clock, 0, sizeof(*best_clock));
 620
 621         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 622              clock.m1++) {
 623                 for (clock.m2 = limit->m2.min;
 624                      clock.m2 <= limit->m2.max; clock.m2++) {
 625                         for (clock.n = limit->n.min;
 626                              clock.n <= limit->n.max; clock.n++) {
 627                                 for (clock.p1 = limit->p1.min;
 628                                         clock.p1 <= limit->p1.max; clock.p1++) {
 629                                         int this_err;
 630
 631                                         pineview_clock(refclk, &clock);
 632                                         if (!intel_PLL_is_valid(dev, limit,
 633                                                                 &clock))
 634                                                 continue;
 635                                         if (match_clock &&
 636                                             clock.p != match_clock->p)
 637                                                 continue;
 638
 639                                         this_err = abs(clock.dot - target);
 640                                         if (this_err < err) {
 641                                                 *best_clock = clock;
 642                                                 err = this_err;
 643                                         }
 644                                 }
 645                         }
 646                 }
 647         }
 648
 649         return (err != target);
 650 }
 651
 652 static bool
 653 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 654                    int target, int refclk, intel_clock_t *match_clock,
 655                    intel_clock_t *best_clock)
 656 {
 657         struct drm_device *dev = crtc->dev;
 658         intel_clock_t clock;
 659         int max_n;
 660         bool found;
 661         /* approximately equals target * 0.00585 */
 662         int err_most = (target >> 8) + (target >> 9);
 663         found = false;
 664
 665         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 666                 if (intel_is_dual_link_lvds(dev))
 667                         clock.p2 = limit->p2.p2_fast;
 668                 else
 669                         clock.p2 = limit->p2.p2_slow;
 670         } else {
 671                 if (target < limit->p2.dot_limit)
 672                         clock.p2 = limit->p2.p2_slow;
 673                 else
 674                         clock.p2 = limit->p2.p2_fast;
 675         }
 676
 677         memset(best_clock, 0, sizeof(*best_clock));
 678         max_n = limit->n.max;
 679         /* based on hardware requirement, prefer smaller n to precision */
 680         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 681                 /* based on hardware requirement, prefere larger m1,m2 */
 682                 for (clock.m1 = limit->m1.max;
 683                      clock.m1 >= limit->m1.min; clock.m1--) {
 684                         for (clock.m2 = limit->m2.max;
 685                              clock.m2 >= limit->m2.min; clock.m2--) {
 686                                 for (clock.p1 = limit->p1.max;
 687                                      clock.p1 >= limit->p1.min; clock.p1--) {
 688                                         int this_err;
 689
 690                                         i9xx_clock(refclk, &clock);
 691                                         if (!intel_PLL_is_valid(dev, limit,
 692                                                                 &clock))
 693                                                 continue;
 694
 695                                         this_err = abs(clock.dot - target);
 696                                         if (this_err < err_most) {
 697                                                 *best_clock = clock;
 698                                                 err_most = this_err;
 699                                                 max_n = clock.n;
 700                                                 found = true;
 701                                         }
 702                                 }
 703                         }
 704                 }
 705         }
 706         return found;
 707 }
 708
 709 static bool
 710 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 711                    int target, int refclk, intel_clock_t *match_clock,
 712                    intel_clock_t *best_clock)
 713 {
 714         struct drm_device *dev = crtc->dev;
 715         intel_clock_t clock;
 716         unsigned int bestppm = 1000000;
 717         /* min update 19.2 MHz */
 718         int max_n = min(limit->n.max, refclk / 19200);
 719         bool found = false;
 720
 721         target *= 5; /* fast clock */
 722
 723         memset(best_clock, 0, sizeof(*best_clock));
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 727                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 728                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 729                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 730                                 clock.p = clock.p1 * clock.p2;
 731                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 732                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 733                                         unsigned int ppm, diff;
 734
 735                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 736                                                                      refclk * clock.m1);
 737
 738                                         vlv_clock(refclk, &clock);
 739
 740                                         if (!intel_PLL_is_valid(dev, limit,
 741                                                                 &clock))
 742                                                 continue;
 743
 744                                         diff = abs(clock.dot - target);
 745                                         ppm = div_u64(1000000ULL * diff, target);
 746
 747                                         if (ppm < 100 && clock.p > best_clock->p) {
 748                                                 bestppm = 0;
 749                                                 *best_clock = clock;
 750                                                 found = true;
 751                                         }
 752
 753                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 754                                                 bestppm = ppm;
 755                                                 *best_clock = clock;
 756                                                 found = true;
 757                                         }
 758                                 }
 759                         }
 760                 }
 761         }
 762
 763         return found;
 764 }
 765
 766 static bool
 767 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 768                    int target, int refclk, intel_clock_t *match_clock,
 769                    intel_clock_t *best_clock)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         intel_clock_t clock;
 773         uint64_t m2;
 774         int found = false;
 775
 776         memset(best_clock, 0, sizeof(*best_clock));
 777
 778         /*
 779          * Based on hardware doc, the n always set to 1, and m1 always
 780          * set to 2.  If requires to support 200Mhz refclk, we need to
 781          * revisit this because n may not 1 anymore.
 782          */
 783         clock.n = 1, clock.m1 = 2;
 784         target *= 5;    /* fast clock */
 785
 786         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 787                 for (clock.p2 = limit->p2.p2_fast;
 788                                 clock.p2 >= limit->p2.p2_slow;
 789                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 790
 791                         clock.p = clock.p1 * clock.p2;
 792
 793                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 794                                         clock.n) << 22, refclk * clock.m1);
 795
 796                         if (m2 > INT_MAX/clock.m1)
 797                                 continue;
 798
 799                         clock.m2 = m2;
 800
 801                         chv_clock(refclk, &clock);
 802
 803                         if (!intel_PLL_is_valid(dev, limit, &clock))
 804                                 continue;
 805
 806                         /* based on hardware requirement, prefer bigger p
 807                          */
 808                         if (clock.p > best_clock->p) {
 809                                 *best_clock = clock;
 810                                 found = true;
 811                         }
 812                 }
 813         }
 814
 815         return found;
 816 }
 817
 818 bool intel_crtc_active(struct drm_crtc *crtc)
 819 {
 820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 821
 822         /* Be paranoid as we can arrive here with only partial
 823          * state retrieved from the hardware during setup.
 824          *
 825          * We can ditch the adjusted_mode.crtc_clock check as soon
 826          * as Haswell has gained clock readout/fastboot support.
 827          *
 828          * We can ditch the crtc->primary->fb check as soon as we can
 829          * properly reconstruct framebuffers.
 830          */
 831         return intel_crtc->active && crtc->primary->fb &&
 832                 intel_crtc->config.adjusted_mode.crtc_clock;
 833 }
 834
 835 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 836                                              enum pipe pipe)
 837 {
 838         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 840
 841         return intel_crtc->config.cpu_transcoder;
 842 }
 843
 844 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 845 {
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 848
 849         frame = I915_READ(frame_reg);
 850
 851         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 852                 WARN(1, "vblank wait timed out\n");
 853 }
 854
 855 /**
 856  * intel_wait_for_vblank - wait for vblank on a given pipe
 857  * @dev: drm device
 858  * @pipe: pipe to wait for
 859  *
 860  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 861  * mode setting code.
 862  */
 863 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int pipestat_reg = PIPESTAT(pipe);
 867
 868         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 869                 g4x_wait_for_vblank(dev, pipe);
 870                 return;
 871         }
 872
 873         /* Clear existing vblank status. Note this will clear any other
 874          * sticky status fields as well.
 875          *
 876          * This races with i915_driver_irq_handler() with the result
 877          * that either function could miss a vblank event.  Here it is not
 878          * fatal, as we will either wait upon the next vblank interrupt or
 879          * timeout.  Generally speaking intel_wait_for_vblank() is only
 880          * called during modeset at which time the GPU should be idle and
 881          * should *not* be performing page flips and thus not waiting on
 882          * vblanks...
 883          * Currently, the result of us stealing a vblank from the irq
 884          * handler is that a single frame will be skipped during swapbuffers.
 885          */
 886         I915_WRITE(pipestat_reg,
 887                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 888
 889         /* Wait for vblank interrupt bit to set */
 890         if (wait_for(I915_READ(pipestat_reg) &
 891                      PIPE_VBLANK_INTERRUPT_STATUS,
 892                      50))
 893                 DRM_DEBUG_KMS("vblank wait timed out\n");
 894 }
 895
 896 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 897 {
 898         struct drm_i915_private *dev_priv = dev->dev_private;
 899         u32 reg = PIPEDSL(pipe);
 900         u32 line1, line2;
 901         u32 line_mask;
 902
 903         if (IS_GEN2(dev))
 904                 line_mask = DSL_LINEMASK_GEN2;
 905         else
 906                 line_mask = DSL_LINEMASK_GEN3;
 907
 908         line1 = I915_READ(reg) & line_mask;
 909         mdelay(5);
 910         line2 = I915_READ(reg) & line_mask;
 911
 912         return line1 == line2;
 913 }
 914
 915 /*
 916  * intel_wait_for_pipe_off - wait for pipe to turn off
 917  * @dev: drm device
 918  * @pipe: pipe to wait for
 919  *
 920  * After disabling a pipe, we can't wait for vblank in the usual way,
 921  * spinning on the vblank interrupt status bit, since we won't actually
 922  * see an interrupt when the pipe is disabled.
 923  *
 924  * On Gen4 and above:
 925  *   wait for the pipe register state bit to turn off
 926  *
 927  * Otherwise:
 928  *   wait for the display line value to settle (it usually
 929  *   ends up stopping at the start of the next frame).
 930  *
 931  */
 932 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 936                                                                       pipe);
 937
 938         if (INTEL_INFO(dev)->gen >= 4) {
 939                 int reg = PIPECONF(cpu_transcoder);
 940
 941                 /* Wait for the Pipe State to go off */
 942                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 943                              100))
 944                         WARN(1, "pipe_off wait timed out\n");
 945         } else {
 946                 /* Wait for the display line to settle */
 947                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 948                         WARN(1, "pipe_off wait timed out\n");
 949         }
 950 }
 951
 952 /*
 953  * ibx_digital_port_connected - is the specified port connected?
 954  * @dev_priv: i915 private structure
 955  * @port: the port to test
 956  *
 957  * Returns true if @port is connected, false otherwise.
 958  */
 959 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 960                                 struct intel_digital_port *port)
 961 {
 962         u32 bit;
 963
 964         if (HAS_PCH_IBX(dev_priv->dev)) {
 965                 switch(port->port) {
 966                 case PORT_B:
 967                         bit = SDE_PORTB_HOTPLUG;
 968                         break;
 969                 case PORT_C:
 970                         bit = SDE_PORTC_HOTPLUG;
 971                         break;
 972                 case PORT_D:
 973                         bit = SDE_PORTD_HOTPLUG;
 974                         break;
 975                 default:
 976                         return true;
 977                 }
 978         } else {
 979                 switch(port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG_CPT;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG_CPT;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG_CPT;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         }
 993
 994         return I915_READ(SDEISR) & bit;
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 void assert_pll(struct drm_i915_private *dev_priv,
1004                 enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017
1018 /* XXX: the dsi pll is shared between MIPI DSI ports */
1019 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1020 {
1021         u32 val;
1022         bool cur_state;
1023
1024         mutex_lock(&dev_priv->dpio_lock);
1025         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1026         mutex_unlock(&dev_priv->dpio_lock);
1027
1028         cur_state = val & DSI_PLL_VCO_EN;
1029         WARN(cur_state != state,
1030              "DSI PLL state assertion failure (expected %s, current %s)\n",
1031              state_string(state), state_string(cur_state));
1032 }
1033 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1034 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1035
1036 struct intel_shared_dpll *
1037 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1038 {
1039         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1040
1041         if (crtc->config.shared_dpll < 0)
1042                 return NULL;
1043
1044         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1045 }
1046
1047 /* For ILK+ */
1048 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1049                         struct intel_shared_dpll *pll,
1050                         bool state)
1051 {
1052         bool cur_state;
1053         struct intel_dpll_hw_state hw_state;
1054
1055         if (HAS_PCH_LPT(dev_priv->dev)) {
1056                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1057                 return;
1058         }
1059
1060         if (WARN (!pll,
1061                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1062                 return;
1063
1064         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1065         WARN(cur_state != state,
1066              "%s assertion failure (expected %s, current %s)\n",
1067              pll->name, state_string(state), state_string(cur_state));
1068 }
1069
1070 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1071                           enum pipe pipe, bool state)
1072 {
1073         int reg;
1074         u32 val;
1075         bool cur_state;
1076         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077                                                                       pipe);
1078
1079         if (HAS_DDI(dev_priv->dev)) {
1080                 /* DDI does not have a specific FDI_TX register */
1081                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1084         } else {
1085                 reg = FDI_TX_CTL(pipe);
1086                 val = I915_READ(reg);
1087                 cur_state = !!(val & FDI_TX_ENABLE);
1088         }
1089         WARN(cur_state != state,
1090              "FDI TX state assertion failure (expected %s, current %s)\n",
1091              state_string(state), state_string(cur_state));
1092 }
1093 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1094 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1095
1096 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1097                           enum pipe pipe, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = FDI_RX_CTL(pipe);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & FDI_RX_ENABLE);
1106         WARN(cur_state != state,
1107              "FDI RX state assertion failure (expected %s, current %s)\n",
1108              state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1111 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1112
1113 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1114                                       enum pipe pipe)
1115 {
1116         int reg;
1117         u32 val;
1118
1119         /* ILK FDI PLL is always enabled */
1120         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1121                 return;
1122
1123         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1124         if (HAS_DDI(dev_priv->dev))
1125                 return;
1126
1127         reg = FDI_TX_CTL(pipe);
1128         val = I915_READ(reg);
1129         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1130 }
1131
1132 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1133                        enum pipe pipe, bool state)
1134 {
1135         int reg;
1136         u32 val;
1137         bool cur_state;
1138
1139         reg = FDI_RX_CTL(pipe);
1140         val = I915_READ(reg);
1141         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1142         WARN(cur_state != state,
1143              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1144              state_string(state), state_string(cur_state));
1145 }
1146
1147 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1148                                   enum pipe pipe)
1149 {
1150         int pp_reg, lvds_reg;
1151         u32 val;
1152         enum pipe panel_pipe = PIPE_A;
1153         bool locked = true;
1154
1155         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1156                 pp_reg = PCH_PP_CONTROL;
1157                 lvds_reg = PCH_LVDS;
1158         } else {
1159                 pp_reg = PP_CONTROL;
1160                 lvds_reg = LVDS;
1161         }
1162
1163         val = I915_READ(pp_reg);
1164         if (!(val & PANEL_POWER_ON) ||
1165             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1166                 locked = false;
1167
1168         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1169                 panel_pipe = PIPE_B;
1170
1171         WARN(panel_pipe == pipe && locked,
1172              "panel assertion failure, pipe %c regs locked\n",
1173              pipe_name(pipe));
1174 }
1175
1176 static void assert_cursor(struct drm_i915_private *dev_priv,
1177                           enum pipe pipe, bool state)
1178 {
1179         struct drm_device *dev = dev_priv->dev;
1180         bool cur_state;
1181
1182         if (IS_845G(dev) || IS_I865G(dev))
1183                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1184         else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1185                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1186         else
1187                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1188
1189         WARN(cur_state != state,
1190              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1191              pipe_name(pipe), state_string(state), state_string(cur_state));
1192 }
1193 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1194 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1195
1196 void assert_pipe(struct drm_i915_private *dev_priv,
1197                  enum pipe pipe, bool state)
1198 {
1199         int reg;
1200         u32 val;
1201         bool cur_state;
1202         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1203                                                                       pipe);
1204
1205         /* if we need the pipe A quirk it must be always on */
1206         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1207                 state = true;
1208
1209         if (!intel_display_power_enabled(dev_priv,
1210                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1211                 cur_state = false;
1212         } else {
1213                 reg = PIPECONF(cpu_transcoder);
1214                 val = I915_READ(reg);
1215                 cur_state = !!(val & PIPECONF_ENABLE);
1216         }
1217
1218         WARN(cur_state != state,
1219              "pipe %c assertion failure (expected %s, current %s)\n",
1220              pipe_name(pipe), state_string(state), state_string(cur_state));
1221 }
1222
1223 static void assert_plane(struct drm_i915_private *dev_priv,
1224                          enum plane plane, bool state)
1225 {
1226         int reg;
1227         u32 val;
1228         bool cur_state;
1229
1230         reg = DSPCNTR(plane);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1233         WARN(cur_state != state,
1234              "plane %c assertion failure (expected %s, current %s)\n",
1235              plane_name(plane), state_string(state), state_string(cur_state));
1236 }
1237
1238 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1239 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1240
1241 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1242                                    enum pipe pipe)
1243 {
1244         struct drm_device *dev = dev_priv->dev;
1245         int reg, i;
1246         u32 val;
1247         int cur_pipe;
1248
1249         /* Primary planes are fixed to pipes on gen4+ */
1250         if (INTEL_INFO(dev)->gen >= 4) {
1251                 reg = DSPCNTR(pipe);
1252                 val = I915_READ(reg);
1253                 WARN(val & DISPLAY_PLANE_ENABLE,
1254                      "plane %c assertion failure, should be disabled but not\n",
1255                      plane_name(pipe));
1256                 return;
1257         }
1258
1259         /* Need to check both planes against the pipe */
1260         for_each_pipe(i) {
1261                 reg = DSPCNTR(i);
1262                 val = I915_READ(reg);
1263                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1264                         DISPPLANE_SEL_PIPE_SHIFT;
1265                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1266                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1267                      plane_name(i), pipe_name(pipe));
1268         }
1269 }
1270
1271 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1272                                     enum pipe pipe)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         int reg, sprite;
1276         u32 val;
1277
1278         if (IS_VALLEYVIEW(dev)) {
1279                 for_each_sprite(pipe, sprite) {
1280                         reg = SPCNTR(pipe, sprite);
1281                         val = I915_READ(reg);
1282                         WARN(val & SP_ENABLE,
1283                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                              sprite_name(pipe, sprite), pipe_name(pipe));
1285                 }
1286         } else if (INTEL_INFO(dev)->gen >= 7) {
1287                 reg = SPRCTL(pipe);
1288                 val = I915_READ(reg);
1289                 WARN(val & SPRITE_ENABLE,
1290                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                      plane_name(pipe), pipe_name(pipe));
1292         } else if (INTEL_INFO(dev)->gen >= 5) {
1293                 reg = DVSCNTR(pipe);
1294                 val = I915_READ(reg);
1295                 WARN(val & DVS_ENABLE,
1296                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1297                      plane_name(pipe), pipe_name(pipe));
1298         }
1299 }
1300
1301 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1302 {
1303         u32 val;
1304         bool enabled;
1305
1306         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1307
1308         val = I915_READ(PCH_DREF_CONTROL);
1309         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310                             DREF_SUPERSPREAD_SOURCE_MASK));
1311         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1315                                            enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319         bool enabled;
1320
1321         reg = PCH_TRANSCONF(pipe);
1322         val = I915_READ(reg);
1323         enabled = !!(val & TRANS_ENABLE);
1324         WARN(enabled,
1325              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326              pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330                             enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332         if ((val & DP_PORT_EN) == 0)
1333                 return false;
1334
1335         if (HAS_PCH_CPT(dev_priv->dev)) {
1336                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339                         return false;
1340         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1341                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & SDVO_ENABLE) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1358                         return false;
1359         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1360                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1361                         return false;
1362         } else {
1363                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1364                         return false;
1365         }
1366         return true;
1367 }
1368
1369 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1370                               enum pipe pipe, u32 val)
1371 {
1372         if ((val & LVDS_PORT_EN) == 0)
1373                 return false;
1374
1375         if (HAS_PCH_CPT(dev_priv->dev)) {
1376                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1377                         return false;
1378         } else {
1379                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1380                         return false;
1381         }
1382         return true;
1383 }
1384
1385 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1386                               enum pipe pipe, u32 val)
1387 {
1388         if ((val & ADPA_DAC_ENABLE) == 0)
1389                 return false;
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1392                         return false;
1393         } else {
1394                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1395                         return false;
1396         }
1397         return true;
1398 }
1399
1400 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1401                                    enum pipe pipe, int reg, u32 port_sel)
1402 {
1403         u32 val = I915_READ(reg);
1404         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1405              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1406              reg, pipe_name(pipe));
1407
1408         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1409              && (val & DP_PIPEB_SELECT),
1410              "IBX PCH dp port still using transcoder B\n");
1411 }
1412
1413 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1414                                      enum pipe pipe, int reg)
1415 {
1416         u32 val = I915_READ(reg);
1417         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1418              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1419              reg, pipe_name(pipe));
1420
1421         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1422              && (val & SDVO_PIPE_B_SELECT),
1423              "IBX PCH hdmi port still using transcoder B\n");
1424 }
1425
1426 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1427                                       enum pipe pipe)
1428 {
1429         int reg;
1430         u32 val;
1431
1432         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1433         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1434         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1435
1436         reg = PCH_ADPA;
1437         val = I915_READ(reg);
1438         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1439              "PCH VGA enabled on transcoder %c, should be disabled\n",
1440              pipe_name(pipe));
1441
1442         reg = PCH_LVDS;
1443         val = I915_READ(reg);
1444         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1445              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1446              pipe_name(pipe));
1447
1448         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1449         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1450         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1451 }
1452
1453 static void intel_init_dpio(struct drm_device *dev)
1454 {
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!IS_VALLEYVIEW(dev))
1458                 return;
1459
1460         /*
1461          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1462          * CHV x1 PHY (DP/HDMI D)
1463          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1464          */
1465         if (IS_CHERRYVIEW(dev)) {
1466                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1467                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1468         } else {
1469                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1470         }
1471 }
1472
1473 static void intel_reset_dpio(struct drm_device *dev)
1474 {
1475         struct drm_i915_private *dev_priv = dev->dev_private;
1476
1477         if (!IS_VALLEYVIEW(dev))
1478                 return;
1479
1480         /*
1481          * Enable the CRI clock source so we can get at the display and the
1482          * reference clock for VGA hotplug / manual detection.
1483          */
1484         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1485                    DPLL_REFA_CLK_ENABLE_VLV |
1486                    DPLL_INTEGRATED_CRI_CLK_VLV);
1487
1488         if (IS_CHERRYVIEW(dev)) {
1489                 enum dpio_phy phy;
1490                 u32 val;
1491
1492                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1493                         /* Poll for phypwrgood signal */
1494                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1495                                                 PHY_POWERGOOD(phy), 1))
1496                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1497
1498                         /*
1499                          * Deassert common lane reset for PHY.
1500                          *
1501                          * This should only be done on init and resume from S3
1502                          * with both PLLs disabled, or we risk losing DPIO and
1503                          * PLL synchronization.
1504                          */
1505                         val = I915_READ(DISPLAY_PHY_CONTROL);
1506                         I915_WRITE(DISPLAY_PHY_CONTROL,
1507                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1508                 }
1509
1510         } else {
1511                 /*
1512                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1513                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1514                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1515                  *   b. The other bits such as sfr settings / modesel may all
1516                  *      be set to 0.
1517                  *
1518                  * This should only be done on init and resume from S3 with
1519                  * both PLLs disabled, or we risk losing DPIO and PLL
1520                  * synchronization.
1521                  */
1522                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1523         }
1524 }
1525
1526 static void vlv_enable_pll(struct intel_crtc *crtc)
1527 {
1528         struct drm_device *dev = crtc->base.dev;
1529         struct drm_i915_private *dev_priv = dev->dev_private;
1530         int reg = DPLL(crtc->pipe);
1531         u32 dpll = crtc->config.dpll_hw_state.dpll;
1532
1533         assert_pipe_disabled(dev_priv, crtc->pipe);
1534
1535         /* No really, not for ILK+ */
1536         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1537
1538         /* PLL is protected by panel, make sure we can write it */
1539         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1540                 assert_panel_unlocked(dev_priv, crtc->pipe);
1541
1542         I915_WRITE(reg, dpll);
1543         POSTING_READ(reg);
1544         udelay(150);
1545
1546         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1547                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1548
1549         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1550         POSTING_READ(DPLL_MD(crtc->pipe));
1551
1552         /* We do this three times for luck */
1553         I915_WRITE(reg, dpll);
1554         POSTING_READ(reg);
1555         udelay(150); /* wait for warmup */
1556         I915_WRITE(reg, dpll);
1557         POSTING_READ(reg);
1558         udelay(150); /* wait for warmup */
1559         I915_WRITE(reg, dpll);
1560         POSTING_READ(reg);
1561         udelay(150); /* wait for warmup */
1562 }
1563
1564 static void chv_enable_pll(struct intel_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->base.dev;
1567         struct drm_i915_private *dev_priv = dev->dev_private;
1568         int pipe = crtc->pipe;
1569         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1570         int dpll = DPLL(crtc->pipe);
1571         u32 tmp;
1572
1573         assert_pipe_disabled(dev_priv, crtc->pipe);
1574
1575         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1576
1577         mutex_lock(&dev_priv->dpio_lock);
1578
1579         /* Enable back the 10bit clock to display controller */
1580         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1581         tmp |= DPIO_DCLKP_EN;
1582         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1583
1584         /*
1585          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1586          */
1587         udelay(1);
1588
1589         /* Enable PLL */
1590         tmp = I915_READ(dpll);
1591         tmp |= DPLL_VCO_ENABLE;
1592         I915_WRITE(dpll, tmp);
1593
1594         /* Check PLL is locked */
1595         if (wait_for(((I915_READ(dpll) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1596                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1597
1598         /* Deassert soft data lane reset*/
1599         tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
1600         tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
1602
1603
1604         mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609         struct drm_device *dev = crtc->base.dev;
1610         struct drm_i915_private *dev_priv = dev->dev_private;
1611         int reg = DPLL(crtc->pipe);
1612         u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614         assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616         /* No really, not for ILK+ */
1617         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619         /* PLL is protected by panel, make sure we can write it */
1620         if (IS_MOBILE(dev) && !IS_I830(dev))
1621                 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623         I915_WRITE(reg, dpll);
1624
1625         /* Wait for the clocks to stabilize. */
1626         POSTING_READ(reg);
1627         udelay(150);
1628
1629         if (INTEL_INFO(dev)->gen >= 4) {
1630                 I915_WRITE(DPLL_MD(crtc->pipe),
1631                            crtc->config.dpll_hw_state.dpll_md);
1632         } else {
1633                 /* The pixel multiplier can only be updated once the
1634                  * DPLL is enabled and the clocks are stable.
1635                  *
1636                  * So write it again.
1637                  */
1638                 I915_WRITE(reg, dpll);
1639         }
1640
1641         /* We do this three times for luck */
1642         I915_WRITE(reg, dpll);
1643         POSTING_READ(reg);
1644         udelay(150); /* wait for warmup */
1645         I915_WRITE(reg, dpll);
1646         POSTING_READ(reg);
1647         udelay(150); /* wait for warmup */
1648         I915_WRITE(reg, dpll);
1649         POSTING_READ(reg);
1650         udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654  * i9xx_disable_pll - disable a PLL
1655  * @dev_priv: i915 private structure
1656  * @pipe: pipe PLL to disable
1657  *
1658  * Disable the PLL for @pipe, making sure the pipe is off first.
1659  *
1660  * Note!  This is for pre-ILK only.
1661  */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664         /* Don't disable pipe A or pipe A PLLs if needed */
1665         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666                 return;
1667
1668         /* Make sure the pipe isn't still relying on us */
1669         assert_pipe_disabled(dev_priv, pipe);
1670
1671         I915_WRITE(DPLL(pipe), 0);
1672         POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677         u32 val = 0;
1678
1679         /* Make sure the pipe isn't still relying on us */
1680         assert_pipe_disabled(dev_priv, pipe);
1681
1682         /*
1683          * Leave integrated clock source and reference clock enabled for pipe B.
1684          * The latter is needed for VGA hotplug / manual detection.
1685          */
1686         if (pipe == PIPE_B)
1687                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688         I915_WRITE(DPLL(pipe), val);
1689         POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695         int dpll = DPLL(pipe);
1696         u32 val;
1697
1698         /* Set PLL en = 0 */
1699         val = I915_READ(dpll);
1700         val &= ~DPLL_VCO_ENABLE;
1701         I915_WRITE(dpll, val);
1702
1703 }
1704
1705 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1706                 struct intel_digital_port *dport)
1707 {
1708         u32 port_mask;
1709         int dpll_reg;
1710
1711         switch (dport->port) {
1712         case PORT_B:
1713                 port_mask = DPLL_PORTB_READY_MASK;
1714                 dpll_reg = DPLL(0);
1715                 break;
1716         case PORT_C:
1717                 port_mask = DPLL_PORTC_READY_MASK;
1718                 dpll_reg = DPLL(0);
1719                 break;
1720         case PORT_D:
1721                 port_mask = DPLL_PORTD_READY_MASK;
1722                 dpll_reg = DPIO_PHY_STATUS;
1723                 break;
1724         default:
1725                 BUG();
1726         }
1727
1728         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1729                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1730                      port_name(dport->port), I915_READ(dpll_reg));
1731 }
1732
1733 /**
1734  * ironlake_enable_shared_dpll - enable PCH PLL
1735  * @dev_priv: i915 private structure
1736  * @pipe: pipe PLL to enable
1737  *
1738  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1739  * drives the transcoder clock.
1740  */
1741 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1742 {
1743         struct drm_device *dev = crtc->base.dev;
1744         struct drm_i915_private *dev_priv = dev->dev_private;
1745         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1746
1747         /* PCH PLLs only available on ILK, SNB and IVB */
1748         BUG_ON(INTEL_INFO(dev)->gen < 5);
1749         if (WARN_ON(pll == NULL))
1750                 return;
1751
1752         if (WARN_ON(pll->refcount == 0))
1753                 return;
1754
1755         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1756                       pll->name, pll->active, pll->on,
1757                       crtc->base.base.id);
1758
1759         if (pll->active++) {
1760                 WARN_ON(!pll->on);
1761                 assert_shared_dpll_enabled(dev_priv, pll);
1762                 return;
1763         }
1764         WARN_ON(pll->on);
1765
1766         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1767         pll->enable(dev_priv, pll);
1768         pll->on = true;
1769 }
1770
1771 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1772 {
1773         struct drm_device *dev = crtc->base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1776
1777         /* PCH only available on ILK+ */
1778         BUG_ON(INTEL_INFO(dev)->gen < 5);
1779         if (WARN_ON(pll == NULL))
1780                return;
1781
1782         if (WARN_ON(pll->refcount == 0))
1783                 return;
1784
1785         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1786                       pll->name, pll->active, pll->on,
1787                       crtc->base.base.id);
1788
1789         if (WARN_ON(pll->active == 0)) {
1790                 assert_shared_dpll_disabled(dev_priv, pll);
1791                 return;
1792         }
1793
1794         assert_shared_dpll_enabled(dev_priv, pll);
1795         WARN_ON(!pll->on);
1796         if (--pll->active)
1797                 return;
1798
1799         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1800         pll->disable(dev_priv, pll);
1801         pll->on = false;
1802 }
1803
1804 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1805                                            enum pipe pipe)
1806 {
1807         struct drm_device *dev = dev_priv->dev;
1808         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1810         uint32_t reg, val, pipeconf_val;
1811
1812         /* PCH only available on ILK+ */
1813         BUG_ON(INTEL_INFO(dev)->gen < 5);
1814
1815         /* Make sure PCH DPLL is enabled */
1816         assert_shared_dpll_enabled(dev_priv,
1817                                    intel_crtc_to_shared_dpll(intel_crtc));
1818
1819         /* FDI must be feeding us bits for PCH ports */
1820         assert_fdi_tx_enabled(dev_priv, pipe);
1821         assert_fdi_rx_enabled(dev_priv, pipe);
1822
1823         if (HAS_PCH_CPT(dev)) {
1824                 /* Workaround: Set the timing override bit before enabling the
1825                  * pch transcoder. */
1826                 reg = TRANS_CHICKEN2(pipe);
1827                 val = I915_READ(reg);
1828                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1829                 I915_WRITE(reg, val);
1830         }
1831
1832         reg = PCH_TRANSCONF(pipe);
1833         val = I915_READ(reg);
1834         pipeconf_val = I915_READ(PIPECONF(pipe));
1835
1836         if (HAS_PCH_IBX(dev_priv->dev)) {
1837                 /*
1838                  * make the BPC in transcoder be consistent with
1839                  * that in pipeconf reg.
1840                  */
1841                 val &= ~PIPECONF_BPC_MASK;
1842                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1843         }
1844
1845         val &= ~TRANS_INTERLACE_MASK;
1846         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1847                 if (HAS_PCH_IBX(dev_priv->dev) &&
1848                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1849                         val |= TRANS_LEGACY_INTERLACED_ILK;
1850                 else
1851                         val |= TRANS_INTERLACED;
1852         else
1853                 val |= TRANS_PROGRESSIVE;
1854
1855         I915_WRITE(reg, val | TRANS_ENABLE);
1856         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1857                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1858 }
1859
1860 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1861                                       enum transcoder cpu_transcoder)
1862 {
1863         u32 val, pipeconf_val;
1864
1865         /* PCH only available on ILK+ */
1866         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1867
1868         /* FDI must be feeding us bits for PCH ports */
1869         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1870         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1871
1872         /* Workaround: set timing override bit. */
1873         val = I915_READ(_TRANSA_CHICKEN2);
1874         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875         I915_WRITE(_TRANSA_CHICKEN2, val);
1876
1877         val = TRANS_ENABLE;
1878         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1879
1880         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1881             PIPECONF_INTERLACED_ILK)
1882                 val |= TRANS_INTERLACED;
1883         else
1884                 val |= TRANS_PROGRESSIVE;
1885
1886         I915_WRITE(LPT_TRANSCONF, val);
1887         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1888                 DRM_ERROR("Failed to enable PCH transcoder\n");
1889 }
1890
1891 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1892                                             enum pipe pipe)
1893 {
1894         struct drm_device *dev = dev_priv->dev;
1895         uint32_t reg, val;
1896
1897         /* FDI relies on the transcoder */
1898         assert_fdi_tx_disabled(dev_priv, pipe);
1899         assert_fdi_rx_disabled(dev_priv, pipe);
1900
1901         /* Ports must be off as well */
1902         assert_pch_ports_disabled(dev_priv, pipe);
1903
1904         reg = PCH_TRANSCONF(pipe);
1905         val = I915_READ(reg);
1906         val &= ~TRANS_ENABLE;
1907         I915_WRITE(reg, val);
1908         /* wait for PCH transcoder off, transcoder state */
1909         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1910                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1911
1912         if (!HAS_PCH_IBX(dev)) {
1913                 /* Workaround: Clear the timing override chicken bit again. */
1914                 reg = TRANS_CHICKEN2(pipe);
1915                 val = I915_READ(reg);
1916                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1917                 I915_WRITE(reg, val);
1918         }
1919 }
1920
1921 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1922 {
1923         u32 val;
1924
1925         val = I915_READ(LPT_TRANSCONF);
1926         val &= ~TRANS_ENABLE;
1927         I915_WRITE(LPT_TRANSCONF, val);
1928         /* wait for PCH transcoder off, transcoder state */
1929         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1930                 DRM_ERROR("Failed to disable PCH transcoder\n");
1931
1932         /* Workaround: clear timing override bit. */
1933         val = I915_READ(_TRANSA_CHICKEN2);
1934         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1935         I915_WRITE(_TRANSA_CHICKEN2, val);
1936 }
1937
1938 /**
1939  * intel_enable_pipe - enable a pipe, asserting requirements
1940  * @crtc: crtc responsible for the pipe
1941  *
1942  * Enable @crtc's pipe, making sure that various hardware specific requirements
1943  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1944  */
1945 static void intel_enable_pipe(struct intel_crtc *crtc)
1946 {
1947         struct drm_device *dev = crtc->base.dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         enum pipe pipe = crtc->pipe;
1950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1951                                                                       pipe);
1952         enum pipe pch_transcoder;
1953         int reg;
1954         u32 val;
1955
1956         assert_planes_disabled(dev_priv, pipe);
1957         assert_cursor_disabled(dev_priv, pipe);
1958         assert_sprites_disabled(dev_priv, pipe);
1959
1960         if (HAS_PCH_LPT(dev_priv->dev))
1961                 pch_transcoder = TRANSCODER_A;
1962         else
1963                 pch_transcoder = pipe;
1964
1965         /*
1966          * A pipe without a PLL won't actually be able to drive bits from
1967          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1968          * need the check.
1969          */
1970         if (!HAS_PCH_SPLIT(dev_priv->dev))
1971                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1972                         assert_dsi_pll_enabled(dev_priv);
1973                 else
1974                         assert_pll_enabled(dev_priv, pipe);
1975         else {
1976                 if (crtc->config.has_pch_encoder) {
1977                         /* if driving the PCH, we need FDI enabled */
1978                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1979                         assert_fdi_tx_pll_enabled(dev_priv,
1980                                                   (enum pipe) cpu_transcoder);
1981                 }
1982                 /* FIXME: assert CPU port conditions for SNB+ */
1983         }
1984
1985         reg = PIPECONF(cpu_transcoder);
1986         val = I915_READ(reg);
1987         if (val & PIPECONF_ENABLE) {
1988                 WARN_ON(!(pipe == PIPE_A &&
1989                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
1990                 return;
1991         }
1992
1993         I915_WRITE(reg, val | PIPECONF_ENABLE);
1994         POSTING_READ(reg);
1995 }
1996
1997 /**
1998  * intel_disable_pipe - disable a pipe, asserting requirements
1999  * @dev_priv: i915 private structure
2000  * @pipe: pipe to disable
2001  *
2002  * Disable @pipe, making sure that various hardware specific requirements
2003  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2004  *
2005  * @pipe should be %PIPE_A or %PIPE_B.
2006  *
2007  * Will wait until the pipe has shut down before returning.
2008  */
2009 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2010                                enum pipe pipe)
2011 {
2012         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2013                                                                       pipe);
2014         int reg;
2015         u32 val;
2016
2017         /*
2018          * Make sure planes won't keep trying to pump pixels to us,
2019          * or we might hang the display.
2020          */
2021         assert_planes_disabled(dev_priv, pipe);
2022         assert_cursor_disabled(dev_priv, pipe);
2023         assert_sprites_disabled(dev_priv, pipe);
2024
2025         /* Don't disable pipe A or pipe A PLLs if needed */
2026         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2027                 return;
2028
2029         reg = PIPECONF(cpu_transcoder);
2030         val = I915_READ(reg);
2031         if ((val & PIPECONF_ENABLE) == 0)
2032                 return;
2033
2034         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2035         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2036 }
2037
2038 /*
2039  * Plane regs are double buffered, going from enabled->disabled needs a
2040  * trigger in order to latch.  The display address reg provides this.
2041  */
2042 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2043                                enum plane plane)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2047
2048         I915_WRITE(reg, I915_READ(reg));
2049         POSTING_READ(reg);
2050 }
2051
2052 /**
2053  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2054  * @dev_priv: i915 private structure
2055  * @plane: plane to enable
2056  * @pipe: pipe being fed
2057  *
2058  * Enable @plane on @pipe, making sure that @pipe is running first.
2059  */
2060 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2061                                           enum plane plane, enum pipe pipe)
2062 {
2063         struct intel_crtc *intel_crtc =
2064                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2065         int reg;
2066         u32 val;
2067
2068         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2069         assert_pipe_enabled(dev_priv, pipe);
2070
2071         if (intel_crtc->primary_enabled)
2072                 return;
2073
2074         intel_crtc->primary_enabled = true;
2075
2076         reg = DSPCNTR(plane);
2077         val = I915_READ(reg);
2078         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2079
2080         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2081         intel_flush_primary_plane(dev_priv, plane);
2082         intel_wait_for_vblank(dev_priv->dev, pipe);
2083 }
2084
2085 /**
2086  * intel_disable_primary_hw_plane - disable the primary hardware plane
2087  * @dev_priv: i915 private structure
2088  * @plane: plane to disable
2089  * @pipe: pipe consuming the data
2090  *
2091  * Disable @plane; should be an independent operation.
2092  */
2093 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2094                                            enum plane plane, enum pipe pipe)
2095 {
2096         struct intel_crtc *intel_crtc =
2097                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2098         int reg;
2099         u32 val;
2100
2101         if (!intel_crtc->primary_enabled)
2102                 return;
2103
2104         intel_crtc->primary_enabled = false;
2105
2106         reg = DSPCNTR(plane);
2107         val = I915_READ(reg);
2108         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2109
2110         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2111         intel_flush_primary_plane(dev_priv, plane);
2112         intel_wait_for_vblank(dev_priv->dev, pipe);
2113 }
2114
2115 static bool need_vtd_wa(struct drm_device *dev)
2116 {
2117 #ifdef CONFIG_INTEL_IOMMU
2118         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2119                 return true;
2120 #endif
2121         return false;
2122 }
2123
2124 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2125 {
2126         int tile_height;
2127
2128         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2129         return ALIGN(height, tile_height);
2130 }
2131
2132 int
2133 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2134                            struct drm_i915_gem_object *obj,
2135                            struct intel_ring_buffer *pipelined)
2136 {
2137         struct drm_i915_private *dev_priv = dev->dev_private;
2138         u32 alignment;
2139         int ret;
2140
2141         switch (obj->tiling_mode) {
2142         case I915_TILING_NONE:
2143                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2144                         alignment = 128 * 1024;
2145                 else if (INTEL_INFO(dev)->gen >= 4)
2146                         alignment = 4 * 1024;
2147                 else
2148                         alignment = 64 * 1024;
2149                 break;
2150         case I915_TILING_X:
2151                 /* pin() will align the object as required by fence */
2152                 alignment = 0;
2153                 break;
2154         case I915_TILING_Y:
2155                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2156                 return -EINVAL;
2157         default:
2158                 BUG();
2159         }
2160
2161         /* Note that the w/a also requires 64 PTE of padding following the
2162          * bo. We currently fill all unused PTE with the shadow page and so
2163          * we should always have valid PTE following the scanout preventing
2164          * the VT-d warning.
2165          */
2166         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2167                 alignment = 256 * 1024;
2168
2169         dev_priv->mm.interruptible = false;
2170         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2171         if (ret)
2172                 goto err_interruptible;
2173
2174         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2175          * fence, whereas 965+ only requires a fence if using
2176          * framebuffer compression.  For simplicity, we always install
2177          * a fence as the cost is not that onerous.
2178          */
2179         ret = i915_gem_object_get_fence(obj);
2180         if (ret)
2181                 goto err_unpin;
2182
2183         i915_gem_object_pin_fence(obj);
2184
2185         dev_priv->mm.interruptible = true;
2186         return 0;
2187
2188 err_unpin:
2189         i915_gem_object_unpin_from_display_plane(obj);
2190 err_interruptible:
2191         dev_priv->mm.interruptible = true;
2192         return ret;
2193 }
2194
2195 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2196 {
2197         i915_gem_object_unpin_fence(obj);
2198         i915_gem_object_unpin_from_display_plane(obj);
2199 }
2200
2201 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2202  * is assumed to be a power-of-two. */
2203 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2204                                              unsigned int tiling_mode,
2205                                              unsigned int cpp,
2206                                              unsigned int pitch)
2207 {
2208         if (tiling_mode != I915_TILING_NONE) {
2209                 unsigned int tile_rows, tiles;
2210
2211                 tile_rows = *y / 8;
2212                 *y %= 8;
2213
2214                 tiles = *x / (512/cpp);
2215                 *x %= 512/cpp;
2216
2217                 return tile_rows * pitch * 8 + tiles * 4096;
2218         } else {
2219                 unsigned int offset;
2220
2221                 offset = *y * pitch + *x * cpp;
2222                 *y = 0;
2223                 *x = (offset & 4095) / cpp;
2224                 return offset & -4096;
2225         }
2226 }
2227
2228 int intel_format_to_fourcc(int format)
2229 {
2230         switch (format) {
2231         case DISPPLANE_8BPP:
2232                 return DRM_FORMAT_C8;
2233         case DISPPLANE_BGRX555:
2234                 return DRM_FORMAT_XRGB1555;
2235         case DISPPLANE_BGRX565:
2236                 return DRM_FORMAT_RGB565;
2237         default:
2238         case DISPPLANE_BGRX888:
2239                 return DRM_FORMAT_XRGB8888;
2240         case DISPPLANE_RGBX888:
2241                 return DRM_FORMAT_XBGR8888;
2242         case DISPPLANE_BGRX101010:
2243                 return DRM_FORMAT_XRGB2101010;
2244         case DISPPLANE_RGBX101010:
2245                 return DRM_FORMAT_XBGR2101010;
2246         }
2247 }
2248
2249 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2250                                   struct intel_plane_config *plane_config)
2251 {
2252         struct drm_device *dev = crtc->base.dev;
2253         struct drm_i915_gem_object *obj = NULL;
2254         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2255         u32 base = plane_config->base;
2256
2257         if (plane_config->size == 0)
2258                 return false;
2259
2260         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2261                                                              plane_config->size);
2262         if (!obj)
2263                 return false;
2264
2265         if (plane_config->tiled) {
2266                 obj->tiling_mode = I915_TILING_X;
2267                 obj->stride = crtc->base.primary->fb->pitches[0];
2268         }
2269
2270         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2271         mode_cmd.width = crtc->base.primary->fb->width;
2272         mode_cmd.height = crtc->base.primary->fb->height;
2273         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2274
2275         mutex_lock(&dev->struct_mutex);
2276
2277         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2278                                    &mode_cmd, obj)) {
2279                 DRM_DEBUG_KMS("intel fb init failed\n");
2280                 goto out_unref_obj;
2281         }
2282
2283         mutex_unlock(&dev->struct_mutex);
2284
2285         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2286         return true;
2287
2288 out_unref_obj:
2289         drm_gem_object_unreference(&obj->base);
2290         mutex_unlock(&dev->struct_mutex);
2291         return false;
2292 }
2293
2294 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2295                                  struct intel_plane_config *plane_config)
2296 {
2297         struct drm_device *dev = intel_crtc->base.dev;
2298         struct drm_crtc *c;
2299         struct intel_crtc *i;
2300         struct intel_framebuffer *fb;
2301
2302         if (!intel_crtc->base.primary->fb)
2303                 return;
2304
2305         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2306                 return;
2307
2308         kfree(intel_crtc->base.primary->fb);
2309         intel_crtc->base.primary->fb = NULL;
2310
2311         /*
2312          * Failed to alloc the obj, check to see if we should share
2313          * an fb with another CRTC instead
2314          */
2315         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2316                 i = to_intel_crtc(c);
2317
2318                 if (c == &intel_crtc->base)
2319                         continue;
2320
2321                 if (!i->active || !c->primary->fb)
2322                         continue;
2323
2324                 fb = to_intel_framebuffer(c->primary->fb);
2325                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2326                         drm_framebuffer_reference(c->primary->fb);
2327                         intel_crtc->base.primary->fb = c->primary->fb;
2328                         break;
2329                 }
2330         }
2331 }
2332
2333 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2334                                      struct drm_framebuffer *fb,
2335                                      int x, int y)
2336 {
2337         struct drm_device *dev = crtc->dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2340         struct intel_framebuffer *intel_fb;
2341         struct drm_i915_gem_object *obj;
2342         int plane = intel_crtc->plane;
2343         unsigned long linear_offset;
2344         u32 dspcntr;
2345         u32 reg;
2346
2347         intel_fb = to_intel_framebuffer(fb);
2348         obj = intel_fb->obj;
2349
2350         reg = DSPCNTR(plane);
2351         dspcntr = I915_READ(reg);
2352         /* Mask out pixel format bits in case we change it */
2353         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2354         switch (fb->pixel_format) {
2355         case DRM_FORMAT_C8:
2356                 dspcntr |= DISPPLANE_8BPP;
2357                 break;
2358         case DRM_FORMAT_XRGB1555:
2359         case DRM_FORMAT_ARGB1555:
2360                 dspcntr |= DISPPLANE_BGRX555;
2361                 break;
2362         case DRM_FORMAT_RGB565:
2363                 dspcntr |= DISPPLANE_BGRX565;
2364                 break;
2365         case DRM_FORMAT_XRGB8888:
2366         case DRM_FORMAT_ARGB8888:
2367                 dspcntr |= DISPPLANE_BGRX888;
2368                 break;
2369         case DRM_FORMAT_XBGR8888:
2370         case DRM_FORMAT_ABGR8888:
2371                 dspcntr |= DISPPLANE_RGBX888;
2372                 break;
2373         case DRM_FORMAT_XRGB2101010:
2374         case DRM_FORMAT_ARGB2101010:
2375                 dspcntr |= DISPPLANE_BGRX101010;
2376                 break;
2377         case DRM_FORMAT_XBGR2101010:
2378         case DRM_FORMAT_ABGR2101010:
2379                 dspcntr |= DISPPLANE_RGBX101010;
2380                 break;
2381         default:
2382                 BUG();
2383         }
2384
2385         if (INTEL_INFO(dev)->gen >= 4) {
2386                 if (obj->tiling_mode != I915_TILING_NONE)
2387                         dspcntr |= DISPPLANE_TILED;
2388                 else
2389                         dspcntr &= ~DISPPLANE_TILED;
2390         }
2391
2392         if (IS_G4X(dev))
2393                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2394
2395         I915_WRITE(reg, dspcntr);
2396
2397         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2398
2399         if (INTEL_INFO(dev)->gen >= 4) {
2400                 intel_crtc->dspaddr_offset =
2401                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2402                                                        fb->bits_per_pixel / 8,
2403                                                        fb->pitches[0]);
2404                 linear_offset -= intel_crtc->dspaddr_offset;
2405         } else {
2406                 intel_crtc->dspaddr_offset = linear_offset;
2407         }
2408
2409         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2410                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2411                       fb->pitches[0]);
2412         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2413         if (INTEL_INFO(dev)->gen >= 4) {
2414                 I915_WRITE(DSPSURF(plane),
2415                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2416                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2417                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2418         } else
2419                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2420         POSTING_READ(reg);
2421
2422         return 0;
2423 }
2424
2425 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2426                                          struct drm_framebuffer *fb,
2427                                          int x, int y)
2428 {
2429         struct drm_device *dev = crtc->dev;
2430         struct drm_i915_private *dev_priv = dev->dev_private;
2431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432         struct intel_framebuffer *intel_fb;
2433         struct drm_i915_gem_object *obj;
2434         int plane = intel_crtc->plane;
2435         unsigned long linear_offset;
2436         u32 dspcntr;
2437         u32 reg;
2438
2439         intel_fb = to_intel_framebuffer(fb);
2440         obj = intel_fb->obj;
2441
2442         reg = DSPCNTR(plane);
2443         dspcntr = I915_READ(reg);
2444         /* Mask out pixel format bits in case we change it */
2445         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2446         switch (fb->pixel_format) {
2447         case DRM_FORMAT_C8:
2448                 dspcntr |= DISPPLANE_8BPP;
2449                 break;
2450         case DRM_FORMAT_RGB565:
2451                 dspcntr |= DISPPLANE_BGRX565;
2452                 break;
2453         case DRM_FORMAT_XRGB8888:
2454         case DRM_FORMAT_ARGB8888:
2455                 dspcntr |= DISPPLANE_BGRX888;
2456                 break;
2457         case DRM_FORMAT_XBGR8888:
2458         case DRM_FORMAT_ABGR8888:
2459                 dspcntr |= DISPPLANE_RGBX888;
2460                 break;
2461         case DRM_FORMAT_XRGB2101010:
2462         case DRM_FORMAT_ARGB2101010:
2463                 dspcntr |= DISPPLANE_BGRX101010;
2464                 break;
2465         case DRM_FORMAT_XBGR2101010:
2466         case DRM_FORMAT_ABGR2101010:
2467                 dspcntr |= DISPPLANE_RGBX101010;
2468                 break;
2469         default:
2470                 BUG();
2471         }
2472
2473         if (obj->tiling_mode != I915_TILING_NONE)
2474                 dspcntr |= DISPPLANE_TILED;
2475         else
2476                 dspcntr &= ~DISPPLANE_TILED;
2477
2478         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2479                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2480         else
2481                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2482
2483         I915_WRITE(reg, dspcntr);
2484
2485         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2486         intel_crtc->dspaddr_offset =
2487                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2488                                                fb->bits_per_pixel / 8,
2489                                                fb->pitches[0]);
2490         linear_offset -= intel_crtc->dspaddr_offset;
2491
2492         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2493                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2494                       fb->pitches[0]);
2495         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2496         I915_WRITE(DSPSURF(plane),
2497                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2498         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2499                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2500         } else {
2501                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2502                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2503         }
2504         POSTING_READ(reg);
2505
2506         return 0;
2507 }
2508
2509 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2510 static int
2511 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2512                            int x, int y, enum mode_set_atomic state)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516
2517         if (dev_priv->display.disable_fbc)
2518                 dev_priv->display.disable_fbc(dev);
2519         intel_increase_pllclock(crtc);
2520
2521         return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2522 }
2523
2524 void intel_display_handle_reset(struct drm_device *dev)
2525 {
2526         struct drm_i915_private *dev_priv = dev->dev_private;
2527         struct drm_crtc *crtc;
2528
2529         /*
2530          * Flips in the rings have been nuked by the reset,
2531          * so complete all pending flips so that user space
2532          * will get its events and not get stuck.
2533          *
2534          * Also update the base address of all primary
2535          * planes to the the last fb to make sure we're
2536          * showing the correct fb after a reset.
2537          *
2538          * Need to make two loops over the crtcs so that we
2539          * don't try to grab a crtc mutex before the
2540          * pending_flip_queue really got woken up.
2541          */
2542
2543         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2544                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545                 enum plane plane = intel_crtc->plane;
2546
2547                 intel_prepare_page_flip(dev, plane);
2548                 intel_finish_page_flip_plane(dev, plane);
2549         }
2550
2551         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2552                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2553
2554                 mutex_lock(&crtc->mutex);
2555                 /*
2556                  * FIXME: Once we have proper support for primary planes (and
2557                  * disabling them without disabling the entire crtc) allow again
2558                  * a NULL crtc->primary->fb.
2559                  */
2560                 if (intel_crtc->active && crtc->primary->fb)
2561                         dev_priv->display.update_primary_plane(crtc,
2562                                                                crtc->primary->fb,
2563                                                                crtc->x,
2564                                                                crtc->y);
2565                 mutex_unlock(&crtc->mutex);
2566         }
2567 }
2568
2569 static int
2570 intel_finish_fb(struct drm_framebuffer *old_fb)
2571 {
2572         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2573         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2574         bool was_interruptible = dev_priv->mm.interruptible;
2575         int ret;
2576
2577         /* Big Hammer, we also need to ensure that any pending
2578          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2579          * current scanout is retired before unpinning the old
2580          * framebuffer.
2581          *
2582          * This should only fail upon a hung GPU, in which case we
2583          * can safely continue.
2584          */
2585         dev_priv->mm.interruptible = false;
2586         ret = i915_gem_object_finish_gpu(obj);
2587         dev_priv->mm.interruptible = was_interruptible;
2588
2589         return ret;
2590 }
2591
2592 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2593 {
2594         struct drm_device *dev = crtc->dev;
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597         unsigned long flags;
2598         bool pending;
2599
2600         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2601             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2602                 return false;
2603
2604         spin_lock_irqsave(&dev->event_lock, flags);
2605         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2606         spin_unlock_irqrestore(&dev->event_lock, flags);
2607
2608         return pending;
2609 }
2610
2611 static int
2612 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2613                     struct drm_framebuffer *fb)
2614 {
2615         struct drm_device *dev = crtc->dev;
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618         struct drm_framebuffer *old_fb;
2619         int ret;
2620
2621         if (intel_crtc_has_pending_flip(crtc)) {
2622                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2623                 return -EBUSY;
2624         }
2625
2626         /* no fb bound */
2627         if (!fb) {
2628                 DRM_ERROR("No FB bound\n");
2629                 return 0;
2630         }
2631
2632         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2633                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2634                           plane_name(intel_crtc->plane),
2635                           INTEL_INFO(dev)->num_pipes);
2636                 return -EINVAL;
2637         }
2638
2639         mutex_lock(&dev->struct_mutex);
2640         ret = intel_pin_and_fence_fb_obj(dev,
2641                                          to_intel_framebuffer(fb)->obj,
2642                                          NULL);
2643         mutex_unlock(&dev->struct_mutex);
2644         if (ret != 0) {
2645                 DRM_ERROR("pin & fence failed\n");
2646                 return ret;
2647         }
2648
2649         /*
2650          * Update pipe size and adjust fitter if needed: the reason for this is
2651          * that in compute_mode_changes we check the native mode (not the pfit
2652          * mode) to see if we can flip rather than do a full mode set. In the
2653          * fastboot case, we'll flip, but if we don't update the pipesrc and
2654          * pfit state, we'll end up with a big fb scanned out into the wrong
2655          * sized surface.
2656          *
2657          * To fix this properly, we need to hoist the checks up into
2658          * compute_mode_changes (or above), check the actual pfit state and
2659          * whether the platform allows pfit disable with pipe active, and only
2660          * then update the pipesrc and pfit state, even on the flip path.
2661          */
2662         if (i915.fastboot) {
2663                 const struct drm_display_mode *adjusted_mode =
2664                         &intel_crtc->config.adjusted_mode;
2665
2666                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2667                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2668                            (adjusted_mode->crtc_vdisplay - 1));
2669                 if (!intel_crtc->config.pch_pfit.enabled &&
2670                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2671                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2672                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2673                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2674                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2675                 }
2676                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2677                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2678         }
2679
2680         ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2681         if (ret) {
2682                 mutex_lock(&dev->struct_mutex);
2683                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2684                 mutex_unlock(&dev->struct_mutex);
2685                 DRM_ERROR("failed to update base address\n");
2686                 return ret;
2687         }
2688
2689         old_fb = crtc->primary->fb;
2690         crtc->primary->fb = fb;
2691         crtc->x = x;
2692         crtc->y = y;
2693
2694         if (old_fb) {
2695                 if (intel_crtc->active && old_fb != fb)
2696                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2697                 mutex_lock(&dev->struct_mutex);
2698                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2699                 mutex_unlock(&dev->struct_mutex);
2700         }
2701
2702         mutex_lock(&dev->struct_mutex);
2703         intel_update_fbc(dev);
2704         intel_edp_psr_update(dev);
2705         mutex_unlock(&dev->struct_mutex);
2706
2707         return 0;
2708 }
2709
2710 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2711 {
2712         struct drm_device *dev = crtc->dev;
2713         struct drm_i915_private *dev_priv = dev->dev_private;
2714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715         int pipe = intel_crtc->pipe;
2716         u32 reg, temp;
2717
2718         /* enable normal train */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         if (IS_IVYBRIDGE(dev)) {
2722                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2723                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2724         } else {
2725                 temp &= ~FDI_LINK_TRAIN_NONE;
2726                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2727         }
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         if (HAS_PCH_CPT(dev)) {
2733                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2734                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2735         } else {
2736                 temp &= ~FDI_LINK_TRAIN_NONE;
2737                 temp |= FDI_LINK_TRAIN_NONE;
2738         }
2739         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2740
2741         /* wait one idle pattern time */
2742         POSTING_READ(reg);
2743         udelay(1000);
2744
2745         /* IVB wants error correction enabled */
2746         if (IS_IVYBRIDGE(dev))
2747                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2748                            FDI_FE_ERRC_ENABLE);
2749 }
2750
2751 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2752 {
2753         return crtc->base.enabled && crtc->active &&
2754                 crtc->config.has_pch_encoder;
2755 }
2756
2757 static void ivb_modeset_global_resources(struct drm_device *dev)
2758 {
2759         struct drm_i915_private *dev_priv = dev->dev_private;
2760         struct intel_crtc *pipe_B_crtc =
2761                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2762         struct intel_crtc *pipe_C_crtc =
2763                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2764         uint32_t temp;
2765
2766         /*
2767          * When everything is off disable fdi C so that we could enable fdi B
2768          * with all lanes. Note that we don't care about enabled pipes without
2769          * an enabled pch encoder.
2770          */
2771         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2772             !pipe_has_enabled_pch(pipe_C_crtc)) {
2773                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2774                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2775
2776                 temp = I915_READ(SOUTH_CHICKEN1);
2777                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2778                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2779                 I915_WRITE(SOUTH_CHICKEN1, temp);
2780         }
2781 }
2782
2783 /* The FDI link training functions for ILK/Ibexpeak. */
2784 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2785 {
2786         struct drm_device *dev = crtc->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789         int pipe = intel_crtc->pipe;
2790         u32 reg, temp, tries;
2791
2792         /* FDI needs bits from pipe first */
2793         assert_pipe_enabled(dev_priv, pipe);
2794
2795         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2796            for train result */
2797         reg = FDI_RX_IMR(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~FDI_RX_SYMBOL_LOCK;
2800         temp &= ~FDI_RX_BIT_LOCK;
2801         I915_WRITE(reg, temp);
2802         I915_READ(reg);
2803         udelay(150);
2804
2805         /* enable CPU FDI TX and PCH FDI RX */
2806         reg = FDI_TX_CTL(pipe);
2807         temp = I915_READ(reg);
2808         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2809         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2810         temp &= ~FDI_LINK_TRAIN_NONE;
2811         temp |= FDI_LINK_TRAIN_PATTERN_1;
2812         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2813
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         temp &= ~FDI_LINK_TRAIN_NONE;
2817         temp |= FDI_LINK_TRAIN_PATTERN_1;
2818         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2819
2820         POSTING_READ(reg);
2821         udelay(150);
2822
2823         /* Ironlake workaround, enable clock pointer after FDI enable*/
2824         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2825         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2826                    FDI_RX_PHASE_SYNC_POINTER_EN);
2827
2828         reg = FDI_RX_IIR(pipe);
2829         for (tries = 0; tries < 5; tries++) {
2830                 temp = I915_READ(reg);
2831                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2832
2833                 if ((temp & FDI_RX_BIT_LOCK)) {
2834                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2835                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2836                         break;
2837                 }
2838         }
2839         if (tries == 5)
2840                 DRM_ERROR("FDI train 1 fail!\n");
2841
2842         /* Train 2 */
2843         reg = FDI_TX_CTL(pipe);
2844         temp = I915_READ(reg);
2845         temp &= ~FDI_LINK_TRAIN_NONE;
2846         temp |= FDI_LINK_TRAIN_PATTERN_2;
2847         I915_WRITE(reg, temp);
2848
2849         reg = FDI_RX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_2;
2853         I915_WRITE(reg, temp);
2854
2855         POSTING_READ(reg);
2856         udelay(150);
2857
2858         reg = FDI_RX_IIR(pipe);
2859         for (tries = 0; tries < 5; tries++) {
2860                 temp = I915_READ(reg);
2861                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2862
2863                 if (temp & FDI_RX_SYMBOL_LOCK) {
2864                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2865                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2866                         break;
2867                 }
2868         }
2869         if (tries == 5)
2870                 DRM_ERROR("FDI train 2 fail!\n");
2871
2872         DRM_DEBUG_KMS("FDI train done\n");
2873
2874 }
2875
2876 static const int snb_b_fdi_train_param[] = {
2877         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2878         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2879         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2880         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2881 };
2882
2883 /* The FDI link training functions for SNB/Cougarpoint. */
2884 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2885 {
2886         struct drm_device *dev = crtc->dev;
2887         struct drm_i915_private *dev_priv = dev->dev_private;
2888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889         int pipe = intel_crtc->pipe;
2890         u32 reg, temp, i, retry;
2891
2892         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2893            for train result */
2894         reg = FDI_RX_IMR(pipe);
2895         temp = I915_READ(reg);
2896         temp &= ~FDI_RX_SYMBOL_LOCK;
2897         temp &= ~FDI_RX_BIT_LOCK;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(150);
2902
2903         /* enable CPU FDI TX and PCH FDI RX */
2904         reg = FDI_TX_CTL(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2907         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2908         temp &= ~FDI_LINK_TRAIN_NONE;
2909         temp |= FDI_LINK_TRAIN_PATTERN_1;
2910         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2911         /* SNB-B */
2912         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2913         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2914
2915         I915_WRITE(FDI_RX_MISC(pipe),
2916                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2917
2918         reg = FDI_RX_CTL(pipe);
2919         temp = I915_READ(reg);
2920         if (HAS_PCH_CPT(dev)) {
2921                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2922                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2923         } else {
2924                 temp &= ~FDI_LINK_TRAIN_NONE;
2925                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926         }
2927         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2928
2929         POSTING_READ(reg);
2930         udelay(150);
2931
2932         for (i = 0; i < 4; i++) {
2933                 reg = FDI_TX_CTL(pipe);
2934                 temp = I915_READ(reg);
2935                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2936                 temp |= snb_b_fdi_train_param[i];
2937                 I915_WRITE(reg, temp);
2938
2939                 POSTING_READ(reg);
2940                 udelay(500);
2941
2942                 for (retry = 0; retry < 5; retry++) {
2943                         reg = FDI_RX_IIR(pipe);
2944                         temp = I915_READ(reg);
2945                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2946                         if (temp & FDI_RX_BIT_LOCK) {
2947                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2948                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2949                                 break;
2950                         }
2951                         udelay(50);
2952                 }
2953                 if (retry < 5)
2954                         break;
2955         }
2956         if (i == 4)
2957                 DRM_ERROR("FDI train 1 fail!\n");
2958
2959         /* Train 2 */
2960         reg = FDI_TX_CTL(pipe);
2961         temp = I915_READ(reg);
2962         temp &= ~FDI_LINK_TRAIN_NONE;
2963         temp |= FDI_LINK_TRAIN_PATTERN_2;
2964         if (IS_GEN6(dev)) {
2965                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2966                 /* SNB-B */
2967                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2968         }
2969         I915_WRITE(reg, temp);
2970
2971         reg = FDI_RX_CTL(pipe);
2972         temp = I915_READ(reg);
2973         if (HAS_PCH_CPT(dev)) {
2974                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2975                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2976         } else {
2977                 temp &= ~FDI_LINK_TRAIN_NONE;
2978                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2979         }
2980         I915_WRITE(reg, temp);
2981
2982         POSTING_READ(reg);
2983         udelay(150);
2984
2985         for (i = 0; i < 4; i++) {
2986                 reg = FDI_TX_CTL(pipe);
2987                 temp = I915_READ(reg);
2988                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2989                 temp |= snb_b_fdi_train_param[i];
2990                 I915_WRITE(reg, temp);
2991
2992                 POSTING_READ(reg);
2993                 udelay(500);
2994
2995                 for (retry = 0; retry < 5; retry++) {
2996                         reg = FDI_RX_IIR(pipe);
2997                         temp = I915_READ(reg);
2998                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2999                         if (temp & FDI_RX_SYMBOL_LOCK) {
3000                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3001                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3002                                 break;
3003                         }
3004                         udelay(50);
3005                 }
3006                 if (retry < 5)
3007                         break;
3008         }
3009         if (i == 4)
3010                 DRM_ERROR("FDI train 2 fail!\n");
3011
3012         DRM_DEBUG_KMS("FDI train done.\n");
3013 }
3014
3015 /* Manual link training for Ivy Bridge A0 parts */
3016 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3017 {
3018         struct drm_device *dev = crtc->dev;
3019         struct drm_i915_private *dev_priv = dev->dev_private;
3020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3021         int pipe = intel_crtc->pipe;
3022         u32 reg, temp, i, j;
3023
3024         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025            for train result */
3026         reg = FDI_RX_IMR(pipe);
3027         temp = I915_READ(reg);
3028         temp &= ~FDI_RX_SYMBOL_LOCK;
3029         temp &= ~FDI_RX_BIT_LOCK;
3030         I915_WRITE(reg, temp);
3031
3032         POSTING_READ(reg);
3033         udelay(150);
3034
3035         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3036                       I915_READ(FDI_RX_IIR(pipe)));
3037
3038         /* Try each vswing and preemphasis setting twice before moving on */
3039         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3040                 /* disable first in case we need to retry */
3041                 reg = FDI_TX_CTL(pipe);
3042                 temp = I915_READ(reg);
3043                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3044                 temp &= ~FDI_TX_ENABLE;
3045                 I915_WRITE(reg, temp);
3046
3047                 reg = FDI_RX_CTL(pipe);
3048                 temp = I915_READ(reg);
3049                 temp &= ~FDI_LINK_TRAIN_AUTO;
3050                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3051                 temp &= ~FDI_RX_ENABLE;
3052                 I915_WRITE(reg, temp);
3053
3054                 /* enable CPU FDI TX and PCH FDI RX */
3055                 reg = FDI_TX_CTL(pipe);
3056                 temp = I915_READ(reg);
3057                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3060                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3061                 temp |= snb_b_fdi_train_param[j/2];
3062                 temp |= FDI_COMPOSITE_SYNC;
3063                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3064
3065                 I915_WRITE(FDI_RX_MISC(pipe),
3066                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3067
3068                 reg = FDI_RX_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3071                 temp |= FDI_COMPOSITE_SYNC;
3072                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3073
3074                 POSTING_READ(reg);
3075                 udelay(1); /* should be 0.5us */
3076
3077                 for (i = 0; i < 4; i++) {
3078                         reg = FDI_RX_IIR(pipe);
3079                         temp = I915_READ(reg);
3080                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                         if (temp & FDI_RX_BIT_LOCK ||
3083                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3084                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3086                                               i);
3087                                 break;
3088                         }
3089                         udelay(1); /* should be 0.5us */
3090                 }
3091                 if (i == 4) {
3092                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3093                         continue;
3094                 }
3095
3096                 /* Train 2 */
3097                 reg = FDI_TX_CTL(pipe);
3098                 temp = I915_READ(reg);
3099                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3100                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3101                 I915_WRITE(reg, temp);
3102
3103                 reg = FDI_RX_CTL(pipe);
3104                 temp = I915_READ(reg);
3105                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3106                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3107                 I915_WRITE(reg, temp);
3108
3109                 POSTING_READ(reg);
3110                 udelay(2); /* should be 1.5us */
3111
3112                 for (i = 0; i < 4; i++) {
3113                         reg = FDI_RX_IIR(pipe);
3114                         temp = I915_READ(reg);
3115                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3116
3117                         if (temp & FDI_RX_SYMBOL_LOCK ||
3118                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3119                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3120                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3121                                               i);
3122                                 goto train_done;
3123                         }
3124                         udelay(2); /* should be 1.5us */
3125                 }
3126                 if (i == 4)
3127                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3128         }
3129
3130 train_done:
3131         DRM_DEBUG_KMS("FDI train done.\n");
3132 }
3133
3134 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3135 {
3136         struct drm_device *dev = intel_crtc->base.dev;
3137         struct drm_i915_private *dev_priv = dev->dev_private;
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp;
3140
3141
3142         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3143         reg = FDI_RX_CTL(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3146         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3147         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3148         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3149
3150         POSTING_READ(reg);
3151         udelay(200);
3152
3153         /* Switch from Rawclk to PCDclk */
3154         temp = I915_READ(reg);
3155         I915_WRITE(reg, temp | FDI_PCDCLK);
3156
3157         POSTING_READ(reg);
3158         udelay(200);
3159
3160         /* Enable CPU FDI TX PLL, always on for Ironlake */
3161         reg = FDI_TX_CTL(pipe);
3162         temp = I915_READ(reg);
3163         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3164                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3165
3166                 POSTING_READ(reg);
3167                 udelay(100);
3168         }
3169 }
3170
3171 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3172 {
3173         struct drm_device *dev = intel_crtc->base.dev;
3174         struct drm_i915_private *dev_priv = dev->dev_private;
3175         int pipe = intel_crtc->pipe;
3176         u32 reg, temp;
3177
3178         /* Switch from PCDclk to Rawclk */
3179         reg = FDI_RX_CTL(pipe);
3180         temp = I915_READ(reg);
3181         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3182
3183         /* Disable CPU FDI TX PLL */
3184         reg = FDI_TX_CTL(pipe);
3185         temp = I915_READ(reg);
3186         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3187
3188         POSTING_READ(reg);
3189         udelay(100);
3190
3191         reg = FDI_RX_CTL(pipe);
3192         temp = I915_READ(reg);
3193         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3194
3195         /* Wait for the clocks to turn off. */
3196         POSTING_READ(reg);
3197         udelay(100);
3198 }
3199
3200 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3201 {
3202         struct drm_device *dev = crtc->dev;
3203         struct drm_i915_private *dev_priv = dev->dev_private;
3204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3205         int pipe = intel_crtc->pipe;
3206         u32 reg, temp;
3207
3208         /* disable CPU FDI tx and PCH FDI rx */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3212         POSTING_READ(reg);
3213
3214         reg = FDI_RX_CTL(pipe);
3215         temp = I915_READ(reg);
3216         temp &= ~(0x7 << 16);
3217         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3218         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3219
3220         POSTING_READ(reg);
3221         udelay(100);
3222
3223         /* Ironlake workaround, disable clock pointer after downing FDI */
3224         if (HAS_PCH_IBX(dev)) {
3225                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3226         }
3227
3228         /* still set train pattern 1 */
3229         reg = FDI_TX_CTL(pipe);
3230         temp = I915_READ(reg);
3231         temp &= ~FDI_LINK_TRAIN_NONE;
3232         temp |= FDI_LINK_TRAIN_PATTERN_1;
3233         I915_WRITE(reg, temp);
3234
3235         reg = FDI_RX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (HAS_PCH_CPT(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3239                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3243         }
3244         /* BPC in FDI rx is consistent with that in PIPECONF */
3245         temp &= ~(0x07 << 16);
3246         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3247         I915_WRITE(reg, temp);
3248
3249         POSTING_READ(reg);
3250         udelay(100);
3251 }
3252
3253 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3254 {
3255         struct intel_crtc *crtc;
3256
3257         /* Note that we don't need to be called with mode_config.lock here
3258          * as our list of CRTC objects is static for the lifetime of the
3259          * device and so cannot disappear as we iterate. Similarly, we can
3260          * happily treat the predicates as racy, atomic checks as userspace
3261          * cannot claim and pin a new fb without at least acquring the
3262          * struct_mutex and so serialising with us.
3263          */
3264         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3265                 if (atomic_read(&crtc->unpin_work_count) == 0)
3266                         continue;
3267
3268                 if (crtc->unpin_work)
3269                         intel_wait_for_vblank(dev, crtc->pipe);
3270
3271                 return true;
3272         }
3273
3274         return false;
3275 }
3276
3277 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282         if (crtc->primary->fb == NULL)
3283                 return;
3284
3285         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3286
3287         wait_event(dev_priv->pending_flip_queue,
3288                    !intel_crtc_has_pending_flip(crtc));
3289
3290         mutex_lock(&dev->struct_mutex);
3291         intel_finish_fb(crtc->primary->fb);
3292         mutex_unlock(&dev->struct_mutex);
3293 }
3294
3295 /* Program iCLKIP clock to the desired frequency */
3296 static void lpt_program_iclkip(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3301         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3302         u32 temp;
3303
3304         mutex_lock(&dev_priv->dpio_lock);
3305
3306         /* It is necessary to ungate the pixclk gate prior to programming
3307          * the divisors, and gate it back when it is done.
3308          */
3309         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3310
3311         /* Disable SSCCTL */
3312         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3313                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3314                                 SBI_SSCCTL_DISABLE,
3315                         SBI_ICLK);
3316
3317         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3318         if (clock == 20000) {
3319                 auxdiv = 1;
3320                 divsel = 0x41;
3321                 phaseinc = 0x20;
3322         } else {
3323                 /* The iCLK virtual clock root frequency is in MHz,
3324                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3325                  * divisors, it is necessary to divide one by another, so we
3326                  * convert the virtual clock precision to KHz here for higher
3327                  * precision.
3328                  */
3329                 u32 iclk_virtual_root_freq = 172800 * 1000;
3330                 u32 iclk_pi_range = 64;
3331                 u32 desired_divisor, msb_divisor_value, pi_value;
3332
3333                 desired_divisor = (iclk_virtual_root_freq / clock);
3334                 msb_divisor_value = desired_divisor / iclk_pi_range;
3335                 pi_value = desired_divisor % iclk_pi_range;
3336
3337                 auxdiv = 0;
3338                 divsel = msb_divisor_value - 2;
3339                 phaseinc = pi_value;
3340         }
3341
3342         /* This should not happen with any sane values */
3343         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3344                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3345         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3346                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3347
3348         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3349                         clock,
3350                         auxdiv,
3351                         divsel,
3352                         phasedir,
3353                         phaseinc);
3354
3355         /* Program SSCDIVINTPHASE6 */
3356         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3357         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3358         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3359         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3360         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3361         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3362         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3363         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3364
3365         /* Program SSCAUXDIV */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3367         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3368         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3369         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3370
3371         /* Enable modulator and associated divider */
3372         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3373         temp &= ~SBI_SSCCTL_DISABLE;
3374         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3375
3376         /* Wait for initialization time */
3377         udelay(24);
3378
3379         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3380
3381         mutex_unlock(&dev_priv->dpio_lock);
3382 }
3383
3384 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3385                                                 enum pipe pch_transcoder)
3386 {
3387         struct drm_device *dev = crtc->base.dev;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3390
3391         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3392                    I915_READ(HTOTAL(cpu_transcoder)));
3393         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3394                    I915_READ(HBLANK(cpu_transcoder)));
3395         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3396                    I915_READ(HSYNC(cpu_transcoder)));
3397
3398         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3399                    I915_READ(VTOTAL(cpu_transcoder)));
3400         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3401                    I915_READ(VBLANK(cpu_transcoder)));
3402         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3403                    I915_READ(VSYNC(cpu_transcoder)));
3404         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3405                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3406 }
3407
3408 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3409 {
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411         uint32_t temp;
3412
3413         temp = I915_READ(SOUTH_CHICKEN1);
3414         if (temp & FDI_BC_BIFURCATION_SELECT)
3415                 return;
3416
3417         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3418         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3419
3420         temp |= FDI_BC_BIFURCATION_SELECT;
3421         DRM_DEBUG_KMS("enabling fdi C rx\n");
3422         I915_WRITE(SOUTH_CHICKEN1, temp);
3423         POSTING_READ(SOUTH_CHICKEN1);
3424 }
3425
3426 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3427 {
3428         struct drm_device *dev = intel_crtc->base.dev;
3429         struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431         switch (intel_crtc->pipe) {
3432         case PIPE_A:
3433                 break;
3434         case PIPE_B:
3435                 if (intel_crtc->config.fdi_lanes > 2)
3436                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3437                 else
3438                         cpt_enable_fdi_bc_bifurcation(dev);
3439
3440                 break;
3441         case PIPE_C:
3442                 cpt_enable_fdi_bc_bifurcation(dev);
3443
3444                 break;
3445         default:
3446                 BUG();
3447         }
3448 }
3449
3450 /*
3451  * Enable PCH resources required for PCH ports:
3452  *   - PCH PLLs
3453  *   - FDI training & RX/TX
3454  *   - update transcoder timings
3455  *   - DP transcoding bits
3456  *   - transcoder
3457  */
3458 static void ironlake_pch_enable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         int pipe = intel_crtc->pipe;
3464         u32 reg, temp;
3465
3466         assert_pch_transcoder_disabled(dev_priv, pipe);
3467
3468         if (IS_IVYBRIDGE(dev))
3469                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3470
3471         /* Write the TU size bits before fdi link training, so that error
3472          * detection works. */
3473         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3474                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3475
3476         /* For PCH output, training FDI link */
3477         dev_priv->display.fdi_link_train(crtc);
3478
3479         /* We need to program the right clock selection before writing the pixel
3480          * mutliplier into the DPLL. */
3481         if (HAS_PCH_CPT(dev)) {
3482                 u32 sel;
3483
3484                 temp = I915_READ(PCH_DPLL_SEL);
3485                 temp |= TRANS_DPLL_ENABLE(pipe);
3486                 sel = TRANS_DPLLB_SEL(pipe);
3487                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3488                         temp |= sel;
3489                 else
3490                         temp &= ~sel;
3491                 I915_WRITE(PCH_DPLL_SEL, temp);
3492         }
3493
3494         /* XXX: pch pll's can be enabled any time before we enable the PCH
3495          * transcoder, and we actually should do this to not upset any PCH
3496          * transcoder that already use the clock when we share it.
3497          *
3498          * Note that enable_shared_dpll tries to do the right thing, but
3499          * get_shared_dpll unconditionally resets the pll - we need that to have
3500          * the right LVDS enable sequence. */
3501         ironlake_enable_shared_dpll(intel_crtc);
3502
3503         /* set transcoder timing, panel must allow it */
3504         assert_panel_unlocked(dev_priv, pipe);
3505         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3506
3507         intel_fdi_normal_train(crtc);
3508
3509         /* For PCH DP, enable TRANS_DP_CTL */
3510         if (HAS_PCH_CPT(dev) &&
3511             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3512              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3513                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3514                 reg = TRANS_DP_CTL(pipe);
3515                 temp = I915_READ(reg);
3516                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3517                           TRANS_DP_SYNC_MASK |
3518                           TRANS_DP_BPC_MASK);
3519                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3520                          TRANS_DP_ENH_FRAMING);
3521                 temp |= bpc << 9; /* same format but at 11:9 */
3522
3523                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3524                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3525                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3526                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3527
3528                 switch (intel_trans_dp_port_sel(crtc)) {
3529                 case PCH_DP_B:
3530                         temp |= TRANS_DP_PORT_SEL_B;
3531                         break;
3532                 case PCH_DP_C:
3533                         temp |= TRANS_DP_PORT_SEL_C;
3534                         break;
3535                 case PCH_DP_D:
3536                         temp |= TRANS_DP_PORT_SEL_D;
3537                         break;
3538                 default:
3539                         BUG();
3540                 }
3541
3542                 I915_WRITE(reg, temp);
3543         }
3544
3545         ironlake_enable_pch_transcoder(dev_priv, pipe);
3546 }
3547
3548 static void lpt_pch_enable(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3554
3555         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3556
3557         lpt_program_iclkip(crtc);
3558
3559         /* Set transcoder timing. */
3560         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3561
3562         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3563 }
3564
3565 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3566 {
3567         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3568
3569         if (pll == NULL)
3570                 return;
3571
3572         if (pll->refcount == 0) {
3573                 WARN(1, "bad %s refcount\n", pll->name);
3574                 return;
3575         }
3576
3577         if (--pll->refcount == 0) {
3578                 WARN_ON(pll->on);
3579                 WARN_ON(pll->active);
3580         }
3581
3582         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3583 }
3584
3585 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3586 {
3587         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3588         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3589         enum intel_dpll_id i;
3590
3591         if (pll) {
3592                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3593                               crtc->base.base.id, pll->name);
3594                 intel_put_shared_dpll(crtc);
3595         }
3596
3597         if (HAS_PCH_IBX(dev_priv->dev)) {
3598                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3599                 i = (enum intel_dpll_id) crtc->pipe;
3600                 pll = &dev_priv->shared_dplls[i];
3601
3602                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3603                               crtc->base.base.id, pll->name);
3604
3605                 goto found;
3606         }
3607
3608         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3609                 pll = &dev_priv->shared_dplls[i];
3610
3611                 /* Only want to check enabled timings first */
3612                 if (pll->refcount == 0)
3613                         continue;
3614
3615                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3616                            sizeof(pll->hw_state)) == 0) {
3617                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3618                                       crtc->base.base.id,
3619                                       pll->name, pll->refcount, pll->active);
3620
3621                         goto found;
3622                 }
3623         }
3624
3625         /* Ok no matching timings, maybe there's a free one? */
3626         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627                 pll = &dev_priv->shared_dplls[i];
3628                 if (pll->refcount == 0) {
3629                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3630                                       crtc->base.base.id, pll->name);
3631                         goto found;
3632                 }
3633         }
3634
3635         return NULL;
3636
3637 found:
3638         crtc->config.shared_dpll = i;
3639         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3640                          pipe_name(crtc->pipe));
3641
3642         if (pll->active == 0) {
3643                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3644                        sizeof(pll->hw_state));
3645
3646                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3647                 WARN_ON(pll->on);
3648                 assert_shared_dpll_disabled(dev_priv, pll);
3649
3650                 pll->mode_set(dev_priv, pll);
3651         }
3652         pll->refcount++;
3653
3654         return pll;
3655 }
3656
3657 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3658 {
3659         struct drm_i915_private *dev_priv = dev->dev_private;
3660         int dslreg = PIPEDSL(pipe);
3661         u32 temp;
3662
3663         temp = I915_READ(dslreg);
3664         udelay(500);
3665         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3666                 if (wait_for(I915_READ(dslreg) != temp, 5))
3667                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3668         }
3669 }
3670
3671 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3672 {
3673         struct drm_device *dev = crtc->base.dev;
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         int pipe = crtc->pipe;
3676
3677         if (crtc->config.pch_pfit.enabled) {
3678                 /* Force use of hard-coded filter coefficients
3679                  * as some pre-programmed values are broken,
3680                  * e.g. x201.
3681                  */
3682                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3683                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3684                                                  PF_PIPE_SEL_IVB(pipe));
3685                 else
3686                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3687                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3688                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3689         }
3690 }
3691
3692 static void intel_enable_planes(struct drm_crtc *crtc)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3696         struct drm_plane *plane;
3697         struct intel_plane *intel_plane;
3698
3699         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3700                 intel_plane = to_intel_plane(plane);
3701                 if (intel_plane->pipe == pipe)
3702                         intel_plane_restore(&intel_plane->base);
3703         }
3704 }
3705
3706 static void intel_disable_planes(struct drm_crtc *crtc)
3707 {
3708         struct drm_device *dev = crtc->dev;
3709         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3710         struct drm_plane *plane;
3711         struct intel_plane *intel_plane;
3712
3713         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3714                 intel_plane = to_intel_plane(plane);
3715                 if (intel_plane->pipe == pipe)
3716                         intel_plane_disable(&intel_plane->base);
3717         }
3718 }
3719
3720 void hsw_enable_ips(struct intel_crtc *crtc)
3721 {
3722         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3723
3724         if (!crtc->config.ips_enabled)
3725                 return;
3726
3727         /* We can only enable IPS after we enable a plane and wait for a vblank.
3728          * We guarantee that the plane is enabled by calling intel_enable_ips
3729          * only after intel_enable_plane. And intel_enable_plane already waits
3730          * for a vblank, so all we need to do here is to enable the IPS bit. */
3731         assert_plane_enabled(dev_priv, crtc->plane);
3732         if (IS_BROADWELL(crtc->base.dev)) {
3733                 mutex_lock(&dev_priv->rps.hw_lock);
3734                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3735                 mutex_unlock(&dev_priv->rps.hw_lock);
3736                 /* Quoting Art Runyan: "its not safe to expect any particular
3737                  * value in IPS_CTL bit 31 after enabling IPS through the
3738                  * mailbox." Moreover, the mailbox may return a bogus state,
3739                  * so we need to just enable it and continue on.
3740                  */
3741         } else {
3742                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3743                 /* The bit only becomes 1 in the next vblank, so this wait here
3744                  * is essentially intel_wait_for_vblank. If we don't have this
3745                  * and don't wait for vblanks until the end of crtc_enable, then
3746                  * the HW state readout code will complain that the expected
3747                  * IPS_CTL value is not the one we read. */
3748                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3749                         DRM_ERROR("Timed out waiting for IPS enable\n");
3750         }
3751 }
3752
3753 void hsw_disable_ips(struct intel_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->base.dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757
3758         if (!crtc->config.ips_enabled)
3759                 return;
3760
3761         assert_plane_enabled(dev_priv, crtc->plane);
3762         if (IS_BROADWELL(dev)) {
3763                 mutex_lock(&dev_priv->rps.hw_lock);
3764                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3765                 mutex_unlock(&dev_priv->rps.hw_lock);
3766                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3767                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3768                         DRM_ERROR("Timed out waiting for IPS disable\n");
3769         } else {
3770                 I915_WRITE(IPS_CTL, 0);
3771                 POSTING_READ(IPS_CTL);
3772         }
3773
3774         /* We need to wait for a vblank before we can disable the plane. */
3775         intel_wait_for_vblank(dev, crtc->pipe);
3776 }
3777
3778 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3779 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3780 {
3781         struct drm_device *dev = crtc->dev;
3782         struct drm_i915_private *dev_priv = dev->dev_private;
3783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784         enum pipe pipe = intel_crtc->pipe;
3785         int palreg = PALETTE(pipe);
3786         int i;
3787         bool reenable_ips = false;
3788
3789         /* The clocks have to be on to load the palette. */
3790         if (!crtc->enabled || !intel_crtc->active)
3791                 return;
3792
3793         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3794                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3795                         assert_dsi_pll_enabled(dev_priv);
3796                 else
3797                         assert_pll_enabled(dev_priv, pipe);
3798         }
3799
3800         /* use legacy palette for Ironlake */
3801         if (HAS_PCH_SPLIT(dev))
3802                 palreg = LGC_PALETTE(pipe);
3803
3804         /* Workaround : Do not read or write the pipe palette/gamma data while
3805          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3806          */
3807         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3808             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3809              GAMMA_MODE_MODE_SPLIT)) {
3810                 hsw_disable_ips(intel_crtc);
3811                 reenable_ips = true;
3812         }
3813
3814         for (i = 0; i < 256; i++) {
3815                 I915_WRITE(palreg + 4 * i,
3816                            (intel_crtc->lut_r[i] << 16) |
3817                            (intel_crtc->lut_g[i] << 8) |
3818                            intel_crtc->lut_b[i]);
3819         }
3820
3821         if (reenable_ips)
3822                 hsw_enable_ips(intel_crtc);
3823 }
3824
3825 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3826 {
3827         if (!enable && intel_crtc->overlay) {
3828                 struct drm_device *dev = intel_crtc->base.dev;
3829                 struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831                 mutex_lock(&dev->struct_mutex);
3832                 dev_priv->mm.interruptible = false;
3833                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3834                 dev_priv->mm.interruptible = true;
3835                 mutex_unlock(&dev->struct_mutex);
3836         }
3837
3838         /* Let userspace switch the overlay on again. In most cases userspace
3839          * has to recompute where to put it anyway.
3840          */
3841 }
3842
3843 /**
3844  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3845  * cursor plane briefly if not already running after enabling the display
3846  * plane.
3847  * This workaround avoids occasional blank screens when self refresh is
3848  * enabled.
3849  */
3850 static void
3851 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3852 {
3853         u32 cntl = I915_READ(CURCNTR(pipe));
3854
3855         if ((cntl & CURSOR_MODE) == 0) {
3856                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3857
3858                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3859                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3860                 intel_wait_for_vblank(dev_priv->dev, pipe);
3861                 I915_WRITE(CURCNTR(pipe), cntl);
3862                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3863                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3864         }
3865 }
3866
3867 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3868 {
3869         struct drm_device *dev = crtc->dev;
3870         struct drm_i915_private *dev_priv = dev->dev_private;
3871         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3872         int pipe = intel_crtc->pipe;
3873         int plane = intel_crtc->plane;
3874
3875         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3876         intel_enable_planes(crtc);
3877         /* The fixup needs to happen before cursor is enabled */
3878         if (IS_G4X(dev))
3879                 g4x_fixup_plane(dev_priv, pipe);
3880         intel_crtc_update_cursor(crtc, true);
3881         intel_crtc_dpms_overlay(intel_crtc, true);
3882
3883         hsw_enable_ips(intel_crtc);
3884
3885         mutex_lock(&dev->struct_mutex);
3886         intel_update_fbc(dev);
3887         mutex_unlock(&dev->struct_mutex);
3888 }
3889
3890 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3891 {
3892         struct drm_device *dev = crtc->dev;
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3895         int pipe = intel_crtc->pipe;
3896         int plane = intel_crtc->plane;
3897
3898         intel_crtc_wait_for_pending_flips(crtc);
3899         drm_vblank_off(dev, pipe);
3900
3901         if (dev_priv->fbc.plane == plane)
3902                 intel_disable_fbc(dev);
3903
3904         hsw_disable_ips(intel_crtc);
3905
3906         intel_crtc_dpms_overlay(intel_crtc, false);
3907         intel_crtc_update_cursor(crtc, false);
3908         intel_disable_planes(crtc);
3909         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3910 }
3911
3912 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3913 {
3914         struct drm_device *dev = crtc->dev;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3917         struct intel_encoder *encoder;
3918         int pipe = intel_crtc->pipe;
3919
3920         WARN_ON(!crtc->enabled);
3921
3922         if (intel_crtc->active)
3923                 return;
3924
3925         intel_crtc->active = true;
3926
3927         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3928         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3929
3930         for_each_encoder_on_crtc(dev, crtc, encoder)
3931                 if (encoder->pre_enable)
3932                         encoder->pre_enable(encoder);
3933
3934         if (intel_crtc->config.has_pch_encoder) {
3935                 /* Note: FDI PLL enabling _must_ be done before we enable the
3936                  * cpu pipes, hence this is separate from all the other fdi/pch
3937                  * enabling. */
3938                 ironlake_fdi_pll_enable(intel_crtc);
3939         } else {
3940                 assert_fdi_tx_disabled(dev_priv, pipe);
3941                 assert_fdi_rx_disabled(dev_priv, pipe);
3942         }
3943
3944         ironlake_pfit_enable(intel_crtc);
3945
3946         /*
3947          * On ILK+ LUT must be loaded before the pipe is running but with
3948          * clocks enabled
3949          */
3950         intel_crtc_load_lut(crtc);
3951
3952         intel_update_watermarks(crtc);
3953         intel_enable_pipe(intel_crtc);
3954
3955         if (intel_crtc->config.has_pch_encoder)
3956                 ironlake_pch_enable(crtc);
3957
3958         for_each_encoder_on_crtc(dev, crtc, encoder)
3959                 encoder->enable(encoder);
3960
3961         if (HAS_PCH_CPT(dev))
3962                 cpt_verify_modeset(dev, intel_crtc->pipe);
3963
3964         intel_crtc_enable_planes(crtc);
3965
3966         /*
3967          * There seems to be a race in PCH platform hw (at least on some
3968          * outputs) where an enabled pipe still completes any pageflip right
3969          * away (as if the pipe is off) instead of waiting for vblank. As soon
3970          * as the first vblank happend, everything works as expected. Hence just
3971          * wait for one vblank before returning to avoid strange things
3972          * happening.
3973          */
3974         intel_wait_for_vblank(dev, intel_crtc->pipe);
3975 }
3976
3977 /* IPS only exists on ULT machines and is tied to pipe A. */
3978 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3979 {
3980         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3981 }
3982
3983 /*
3984  * This implements the workaround described in the "notes" section of the mode
3985  * set sequence documentation. When going from no pipes or single pipe to
3986  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3987  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3988  */
3989 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3990 {
3991         struct drm_device *dev = crtc->base.dev;
3992         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3993
3994         /* We want to get the other_active_crtc only if there's only 1 other
3995          * active crtc. */
3996         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3997                 if (!crtc_it->active || crtc_it == crtc)
3998                         continue;
3999
4000                 if (other_active_crtc)
4001                         return;
4002
4003                 other_active_crtc = crtc_it;
4004         }
4005         if (!other_active_crtc)
4006                 return;
4007
4008         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4009         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4010 }
4011
4012 static void haswell_crtc_enable(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017         struct intel_encoder *encoder;
4018         int pipe = intel_crtc->pipe;
4019
4020         WARN_ON(!crtc->enabled);
4021
4022         if (intel_crtc->active)
4023                 return;
4024
4025         intel_crtc->active = true;
4026
4027         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4028         if (intel_crtc->config.has_pch_encoder)
4029                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4030
4031         if (intel_crtc->config.has_pch_encoder)
4032                 dev_priv->display.fdi_link_train(crtc);
4033
4034         for_each_encoder_on_crtc(dev, crtc, encoder)
4035                 if (encoder->pre_enable)
4036                         encoder->pre_enable(encoder);
4037
4038         intel_ddi_enable_pipe_clock(intel_crtc);
4039
4040         ironlake_pfit_enable(intel_crtc);
4041
4042         /*
4043          * On ILK+ LUT must be loaded before the pipe is running but with
4044          * clocks enabled
4045          */
4046         intel_crtc_load_lut(crtc);
4047
4048         intel_ddi_set_pipe_settings(crtc);
4049         intel_ddi_enable_transcoder_func(crtc);
4050
4051         intel_update_watermarks(crtc);
4052         intel_enable_pipe(intel_crtc);
4053
4054         if (intel_crtc->config.has_pch_encoder)
4055                 lpt_pch_enable(crtc);
4056
4057         for_each_encoder_on_crtc(dev, crtc, encoder) {
4058                 encoder->enable(encoder);
4059                 intel_opregion_notify_encoder(encoder, true);
4060         }
4061
4062         /* If we change the relative order between pipe/planes enabling, we need
4063          * to change the workaround. */
4064         haswell_mode_set_planes_workaround(intel_crtc);
4065         intel_crtc_enable_planes(crtc);
4066 }
4067
4068 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4069 {
4070         struct drm_device *dev = crtc->base.dev;
4071         struct drm_i915_private *dev_priv = dev->dev_private;
4072         int pipe = crtc->pipe;
4073
4074         /* To avoid upsetting the power well on haswell only disable the pfit if
4075          * it's in use. The hw state code will make sure we get this right. */
4076         if (crtc->config.pch_pfit.enabled) {
4077                 I915_WRITE(PF_CTL(pipe), 0);
4078                 I915_WRITE(PF_WIN_POS(pipe), 0);
4079                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4080         }
4081 }
4082
4083 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4088         struct intel_encoder *encoder;
4089         int pipe = intel_crtc->pipe;
4090         u32 reg, temp;
4091
4092         if (!intel_crtc->active)
4093                 return;
4094
4095         intel_crtc_disable_planes(crtc);
4096
4097         for_each_encoder_on_crtc(dev, crtc, encoder)
4098                 encoder->disable(encoder);
4099
4100         if (intel_crtc->config.has_pch_encoder)
4101                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4102
4103         intel_disable_pipe(dev_priv, pipe);
4104
4105         ironlake_pfit_disable(intel_crtc);
4106
4107         for_each_encoder_on_crtc(dev, crtc, encoder)
4108                 if (encoder->post_disable)
4109                         encoder->post_disable(encoder);
4110
4111         if (intel_crtc->config.has_pch_encoder) {
4112                 ironlake_fdi_disable(crtc);
4113
4114                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4115                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4116
4117                 if (HAS_PCH_CPT(dev)) {
4118                         /* disable TRANS_DP_CTL */
4119                         reg = TRANS_DP_CTL(pipe);
4120                         temp = I915_READ(reg);
4121                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4122                                   TRANS_DP_PORT_SEL_MASK);
4123                         temp |= TRANS_DP_PORT_SEL_NONE;
4124                         I915_WRITE(reg, temp);
4125
4126                         /* disable DPLL_SEL */
4127                         temp = I915_READ(PCH_DPLL_SEL);
4128                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4129                         I915_WRITE(PCH_DPLL_SEL, temp);
4130                 }
4131
4132                 /* disable PCH DPLL */
4133                 intel_disable_shared_dpll(intel_crtc);
4134
4135                 ironlake_fdi_pll_disable(intel_crtc);
4136         }
4137
4138         intel_crtc->active = false;
4139         intel_update_watermarks(crtc);
4140
4141         mutex_lock(&dev->struct_mutex);
4142         intel_update_fbc(dev);
4143         mutex_unlock(&dev->struct_mutex);
4144 }
4145
4146 static void haswell_crtc_disable(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         struct intel_encoder *encoder;
4152         int pipe = intel_crtc->pipe;
4153         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4154
4155         if (!intel_crtc->active)
4156                 return;
4157
4158         intel_crtc_disable_planes(crtc);
4159
4160         for_each_encoder_on_crtc(dev, crtc, encoder) {
4161                 intel_opregion_notify_encoder(encoder, false);
4162                 encoder->disable(encoder);
4163         }
4164
4165         if (intel_crtc->config.has_pch_encoder)
4166                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4167         intel_disable_pipe(dev_priv, pipe);
4168
4169         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4170
4171         ironlake_pfit_disable(intel_crtc);
4172
4173         intel_ddi_disable_pipe_clock(intel_crtc);
4174
4175         for_each_encoder_on_crtc(dev, crtc, encoder)
4176                 if (encoder->post_disable)
4177                         encoder->post_disable(encoder);
4178
4179         if (intel_crtc->config.has_pch_encoder) {
4180                 lpt_disable_pch_transcoder(dev_priv);
4181                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4182                 intel_ddi_fdi_disable(crtc);
4183         }
4184
4185         intel_crtc->active = false;
4186         intel_update_watermarks(crtc);
4187
4188         mutex_lock(&dev->struct_mutex);
4189         intel_update_fbc(dev);
4190         mutex_unlock(&dev->struct_mutex);
4191 }
4192
4193 static void ironlake_crtc_off(struct drm_crtc *crtc)
4194 {
4195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4196         intel_put_shared_dpll(intel_crtc);
4197 }
4198
4199 static void haswell_crtc_off(struct drm_crtc *crtc)
4200 {
4201         intel_ddi_put_crtc_pll(crtc);
4202 }
4203
4204 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4205 {
4206         struct drm_device *dev = crtc->base.dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc_config *pipe_config = &crtc->config;
4209
4210         if (!crtc->config.gmch_pfit.control)
4211                 return;
4212
4213         /*
4214          * The panel fitter should only be adjusted whilst the pipe is disabled,
4215          * according to register description and PRM.
4216          */
4217         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4218         assert_pipe_disabled(dev_priv, crtc->pipe);
4219
4220         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4221         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4222
4223         /* Border color in case we don't scale up to the full screen. Black by
4224          * default, change to something else for debugging. */
4225         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4226 }
4227
4228 #define for_each_power_domain(domain, mask)                             \
4229         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4230                 if ((1 << (domain)) & (mask))
4231
4232 enum intel_display_power_domain
4233 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4234 {
4235         struct drm_device *dev = intel_encoder->base.dev;
4236         struct intel_digital_port *intel_dig_port;
4237
4238         switch (intel_encoder->type) {
4239         case INTEL_OUTPUT_UNKNOWN:
4240                 /* Only DDI platforms should ever use this output type */
4241                 WARN_ON_ONCE(!HAS_DDI(dev));
4242         case INTEL_OUTPUT_DISPLAYPORT:
4243         case INTEL_OUTPUT_HDMI:
4244         case INTEL_OUTPUT_EDP:
4245                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4246                 switch (intel_dig_port->port) {
4247                 case PORT_A:
4248                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4249                 case PORT_B:
4250                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4251                 case PORT_C:
4252                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4253                 case PORT_D:
4254                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4255                 default:
4256                         WARN_ON_ONCE(1);
4257                         return POWER_DOMAIN_PORT_OTHER;
4258                 }
4259         case INTEL_OUTPUT_ANALOG:
4260                 return POWER_DOMAIN_PORT_CRT;
4261         case INTEL_OUTPUT_DSI:
4262                 return POWER_DOMAIN_PORT_DSI;
4263         default:
4264                 return POWER_DOMAIN_PORT_OTHER;
4265         }
4266 }
4267
4268 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct intel_encoder *intel_encoder;
4272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273         enum pipe pipe = intel_crtc->pipe;
4274         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4275         unsigned long mask;
4276         enum transcoder transcoder;
4277
4278         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4279
4280         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4281         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4282         if (pfit_enabled)
4283                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4284
4285         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4286                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4287
4288         return mask;
4289 }
4290
4291 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4292                                   bool enable)
4293 {
4294         if (dev_priv->power_domains.init_power_on == enable)
4295                 return;
4296
4297         if (enable)
4298                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4299         else
4300                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4301
4302         dev_priv->power_domains.init_power_on = enable;
4303 }
4304
4305 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4306 {
4307         struct drm_i915_private *dev_priv = dev->dev_private;
4308         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4309         struct intel_crtc *crtc;
4310
4311         /*
4312          * First get all needed power domains, then put all unneeded, to avoid
4313          * any unnecessary toggling of the power wells.
4314          */
4315         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4316                 enum intel_display_power_domain domain;
4317
4318                 if (!crtc->base.enabled)
4319                         continue;
4320
4321                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4322
4323                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4324                         intel_display_power_get(dev_priv, domain);
4325         }
4326
4327         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4328                 enum intel_display_power_domain domain;
4329
4330                 for_each_power_domain(domain, crtc->enabled_power_domains)
4331                         intel_display_power_put(dev_priv, domain);
4332
4333                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4334         }
4335
4336         intel_display_set_init_power(dev_priv, false);
4337 }
4338
4339 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4340 {
4341         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4342
4343         /* Obtain SKU information */
4344         mutex_lock(&dev_priv->dpio_lock);
4345         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4346                 CCK_FUSE_HPLL_FREQ_MASK;
4347         mutex_unlock(&dev_priv->dpio_lock);
4348
4349         return vco_freq[hpll_freq];
4350 }
4351
4352 /* Adjust CDclk dividers to allow high res or save power if possible */
4353 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4354 {
4355         struct drm_i915_private *dev_priv = dev->dev_private;
4356         u32 val, cmd;
4357
4358         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4359         dev_priv->vlv_cdclk_freq = cdclk;
4360
4361         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4362                 cmd = 2;
4363         else if (cdclk == 266)
4364                 cmd = 1;
4365         else
4366                 cmd = 0;
4367
4368         mutex_lock(&dev_priv->rps.hw_lock);
4369         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4370         val &= ~DSPFREQGUAR_MASK;
4371         val |= (cmd << DSPFREQGUAR_SHIFT);
4372         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4373         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4374                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4375                      50)) {
4376                 DRM_ERROR("timed out waiting for CDclk change\n");
4377         }
4378         mutex_unlock(&dev_priv->rps.hw_lock);
4379
4380         if (cdclk == 400) {
4381                 u32 divider, vco;
4382
4383                 vco = valleyview_get_vco(dev_priv);
4384                 divider = ((vco << 1) / cdclk) - 1;
4385
4386                 mutex_lock(&dev_priv->dpio_lock);
4387                 /* adjust cdclk divider */
4388                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4389                 val &= ~0xf;
4390                 val |= divider;
4391                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4392                 mutex_unlock(&dev_priv->dpio_lock);
4393         }
4394
4395         mutex_lock(&dev_priv->dpio_lock);
4396         /* adjust self-refresh exit latency value */
4397         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4398         val &= ~0x7f;
4399
4400         /*
4401          * For high bandwidth configs, we set a higher latency in the bunit
4402          * so that the core display fetch happens in time to avoid underruns.
4403          */
4404         if (cdclk == 400)
4405                 val |= 4500 / 250; /* 4.5 usec */
4406         else
4407                 val |= 3000 / 250; /* 3.0 usec */
4408         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4409         mutex_unlock(&dev_priv->dpio_lock);
4410
4411         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4412         intel_i2c_reset(dev);
4413 }
4414
4415 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4416 {
4417         int cur_cdclk, vco;
4418         int divider;
4419
4420         vco = valleyview_get_vco(dev_priv);
4421
4422         mutex_lock(&dev_priv->dpio_lock);
4423         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4424         mutex_unlock(&dev_priv->dpio_lock);
4425
4426         divider &= 0xf;
4427
4428         cur_cdclk = (vco << 1) / (divider + 1);
4429
4430         return cur_cdclk;
4431 }
4432
4433 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4434                                  int max_pixclk)
4435 {
4436         /*
4437          * Really only a few cases to deal with, as only 4 CDclks are supported:
4438          *   200MHz
4439          *   267MHz
4440          *   320MHz
4441          *   400MHz
4442          * So we check to see whether we're above 90% of the lower bin and
4443          * adjust if needed.
4444          */
4445         if (max_pixclk > 288000) {
4446                 return 400;
4447         } else if (max_pixclk > 240000) {
4448                 return 320;
4449         } else
4450                 return 266;
4451         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4452 }
4453
4454 /* compute the max pixel clock for new configuration */
4455 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4456 {
4457         struct drm_device *dev = dev_priv->dev;
4458         struct intel_crtc *intel_crtc;
4459         int max_pixclk = 0;
4460
4461         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4462                             base.head) {
4463                 if (intel_crtc->new_enabled)
4464                         max_pixclk = max(max_pixclk,
4465                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4466         }
4467
4468         return max_pixclk;
4469 }
4470
4471 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4472                                             unsigned *prepare_pipes)
4473 {
4474         struct drm_i915_private *dev_priv = dev->dev_private;
4475         struct intel_crtc *intel_crtc;
4476         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4477
4478         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4479             dev_priv->vlv_cdclk_freq)
4480                 return;
4481
4482         /* disable/enable all currently active pipes while we change cdclk */
4483         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4484                             base.head)
4485                 if (intel_crtc->base.enabled)
4486                         *prepare_pipes |= (1 << intel_crtc->pipe);
4487 }
4488
4489 static void valleyview_modeset_global_resources(struct drm_device *dev)
4490 {
4491         struct drm_i915_private *dev_priv = dev->dev_private;
4492         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4493         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4494
4495         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4496                 valleyview_set_cdclk(dev, req_cdclk);
4497         modeset_update_crtc_power_domains(dev);
4498 }
4499
4500 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4501 {
4502         struct drm_device *dev = crtc->dev;
4503         struct drm_i915_private *dev_priv = dev->dev_private;
4504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4505         struct intel_encoder *encoder;
4506         int pipe = intel_crtc->pipe;
4507         bool is_dsi;
4508
4509         WARN_ON(!crtc->enabled);
4510
4511         if (intel_crtc->active)
4512                 return;
4513
4514         intel_crtc->active = true;
4515
4516         for_each_encoder_on_crtc(dev, crtc, encoder)
4517                 if (encoder->pre_pll_enable)
4518                         encoder->pre_pll_enable(encoder);
4519
4520         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4521
4522         if (!is_dsi) {
4523                 if (IS_CHERRYVIEW(dev))
4524                         chv_enable_pll(intel_crtc);
4525                 else
4526                         vlv_enable_pll(intel_crtc);
4527         }
4528
4529         for_each_encoder_on_crtc(dev, crtc, encoder)
4530                 if (encoder->pre_enable)
4531                         encoder->pre_enable(encoder);
4532
4533         i9xx_pfit_enable(intel_crtc);
4534
4535         intel_crtc_load_lut(crtc);
4536
4537         intel_update_watermarks(crtc);
4538         intel_enable_pipe(intel_crtc);
4539         intel_wait_for_vblank(dev_priv->dev, pipe);
4540         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4541
4542         intel_crtc_enable_planes(crtc);
4543
4544         for_each_encoder_on_crtc(dev, crtc, encoder)
4545                 encoder->enable(encoder);
4546 }
4547
4548 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4549 {
4550         struct drm_device *dev = crtc->dev;
4551         struct drm_i915_private *dev_priv = dev->dev_private;
4552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4553         struct intel_encoder *encoder;
4554         int pipe = intel_crtc->pipe;
4555
4556         WARN_ON(!crtc->enabled);
4557
4558         if (intel_crtc->active)
4559                 return;
4560
4561         intel_crtc->active = true;
4562
4563         for_each_encoder_on_crtc(dev, crtc, encoder)
4564                 if (encoder->pre_enable)
4565                         encoder->pre_enable(encoder);
4566
4567         i9xx_enable_pll(intel_crtc);
4568
4569         i9xx_pfit_enable(intel_crtc);
4570
4571         intel_crtc_load_lut(crtc);
4572
4573         intel_update_watermarks(crtc);
4574         intel_enable_pipe(intel_crtc);
4575         intel_wait_for_vblank(dev_priv->dev, pipe);
4576         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4577
4578         intel_crtc_enable_planes(crtc);
4579
4580         for_each_encoder_on_crtc(dev, crtc, encoder)
4581                 encoder->enable(encoder);
4582 }
4583
4584 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4585 {
4586         struct drm_device *dev = crtc->base.dev;
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588
4589         if (!crtc->config.gmch_pfit.control)
4590                 return;
4591
4592         assert_pipe_disabled(dev_priv, crtc->pipe);
4593
4594         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4595                          I915_READ(PFIT_CONTROL));
4596         I915_WRITE(PFIT_CONTROL, 0);
4597 }
4598
4599 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4600 {
4601         struct drm_device *dev = crtc->dev;
4602         struct drm_i915_private *dev_priv = dev->dev_private;
4603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4604         struct intel_encoder *encoder;
4605         int pipe = intel_crtc->pipe;
4606
4607         if (!intel_crtc->active)
4608                 return;
4609
4610         for_each_encoder_on_crtc(dev, crtc, encoder)
4611                 encoder->disable(encoder);
4612
4613         intel_crtc_disable_planes(crtc);
4614
4615         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4616         intel_disable_pipe(dev_priv, pipe);
4617
4618         i9xx_pfit_disable(intel_crtc);
4619
4620         for_each_encoder_on_crtc(dev, crtc, encoder)
4621                 if (encoder->post_disable)
4622                         encoder->post_disable(encoder);
4623
4624         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4625                 if (IS_CHERRYVIEW(dev))
4626                         chv_disable_pll(dev_priv, pipe);
4627                 else if (IS_VALLEYVIEW(dev))
4628                         vlv_disable_pll(dev_priv, pipe);
4629                 else
4630                         i9xx_disable_pll(dev_priv, pipe);
4631         }
4632
4633         intel_crtc->active = false;
4634         intel_update_watermarks(crtc);
4635
4636         intel_update_fbc(dev);
4637 }
4638
4639 static void i9xx_crtc_off(struct drm_crtc *crtc)
4640 {
4641 }
4642
4643 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4644                                     bool enabled)
4645 {
4646         struct drm_device *dev = crtc->dev;
4647         struct drm_i915_master_private *master_priv;
4648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649         int pipe = intel_crtc->pipe;
4650
4651         if (!dev->primary->master)
4652                 return;
4653
4654         master_priv = dev->primary->master->driver_priv;
4655         if (!master_priv->sarea_priv)
4656                 return;
4657
4658         switch (pipe) {
4659         case 0:
4660                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4661                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4662                 break;
4663         case 1:
4664                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4665                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4666                 break;
4667         default:
4668                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4669                 break;
4670         }
4671 }
4672
4673 /**
4674  * Sets the power management mode of the pipe and plane.
4675  */
4676 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4677 {
4678         struct drm_device *dev = crtc->dev;
4679         struct drm_i915_private *dev_priv = dev->dev_private;
4680         struct intel_encoder *intel_encoder;
4681         bool enable = false;
4682
4683         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4684                 enable |= intel_encoder->connectors_active;
4685
4686         if (enable)
4687                 dev_priv->display.crtc_enable(crtc);
4688         else
4689                 dev_priv->display.crtc_disable(crtc);
4690
4691         intel_crtc_update_sarea(crtc, enable);
4692 }
4693
4694 static void intel_crtc_disable(struct drm_crtc *crtc)
4695 {
4696         struct drm_device *dev = crtc->dev;
4697         struct drm_connector *connector;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4700
4701         /* crtc should still be enabled when we disable it. */
4702         WARN_ON(!crtc->enabled);
4703
4704         dev_priv->display.crtc_disable(crtc);
4705         intel_crtc->eld_vld = false;
4706         intel_crtc_update_sarea(crtc, false);
4707         dev_priv->display.off(crtc);
4708
4709         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4710         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4711         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4712
4713         if (crtc->primary->fb) {
4714                 mutex_lock(&dev->struct_mutex);
4715                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4716                 mutex_unlock(&dev->struct_mutex);
4717                 crtc->primary->fb = NULL;
4718         }
4719
4720         /* Update computed state. */
4721         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4722                 if (!connector->encoder || !connector->encoder->crtc)
4723                         continue;
4724
4725                 if (connector->encoder->crtc != crtc)
4726                         continue;
4727
4728                 connector->dpms = DRM_MODE_DPMS_OFF;
4729                 to_intel_encoder(connector->encoder)->connectors_active = false;
4730         }
4731 }
4732
4733 void intel_encoder_destroy(struct drm_encoder *encoder)
4734 {
4735         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4736
4737         drm_encoder_cleanup(encoder);
4738         kfree(intel_encoder);
4739 }
4740
4741 /* Simple dpms helper for encoders with just one connector, no cloning and only
4742  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4743  * state of the entire output pipe. */
4744 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4745 {
4746         if (mode == DRM_MODE_DPMS_ON) {
4747                 encoder->connectors_active = true;
4748
4749                 intel_crtc_update_dpms(encoder->base.crtc);
4750         } else {
4751                 encoder->connectors_active = false;
4752
4753                 intel_crtc_update_dpms(encoder->base.crtc);
4754         }
4755 }
4756
4757 /* Cross check the actual hw state with our own modeset state tracking (and it's
4758  * internal consistency). */
4759 static void intel_connector_check_state(struct intel_connector *connector)
4760 {
4761         if (connector->get_hw_state(connector)) {
4762                 struct intel_encoder *encoder = connector->encoder;
4763                 struct drm_crtc *crtc;
4764                 bool encoder_enabled;
4765                 enum pipe pipe;
4766
4767                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4768                               connector->base.base.id,
4769                               drm_get_connector_name(&connector->base));
4770
4771                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4772                      "wrong connector dpms state\n");
4773                 WARN(connector->base.encoder != &encoder->base,
4774                      "active connector not linked to encoder\n");
4775                 WARN(!encoder->connectors_active,
4776                      "encoder->connectors_active not set\n");
4777
4778                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4779                 WARN(!encoder_enabled, "encoder not enabled\n");
4780                 if (WARN_ON(!encoder->base.crtc))
4781                         return;
4782
4783                 crtc = encoder->base.crtc;
4784
4785                 WARN(!crtc->enabled, "crtc not enabled\n");
4786                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4787                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4788                      "encoder active on the wrong pipe\n");
4789         }
4790 }
4791
4792 /* Even simpler default implementation, if there's really no special case to
4793  * consider. */
4794 void intel_connector_dpms(struct drm_connector *connector, int mode)
4795 {
4796         /* All the simple cases only support two dpms states. */
4797         if (mode != DRM_MODE_DPMS_ON)
4798                 mode = DRM_MODE_DPMS_OFF;
4799
4800         if (mode == connector->dpms)
4801                 return;
4802
4803         connector->dpms = mode;
4804
4805         /* Only need to change hw state when actually enabled */
4806         if (connector->encoder)
4807                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4808
4809         intel_modeset_check_state(connector->dev);
4810 }
4811
4812 /* Simple connector->get_hw_state implementation for encoders that support only
4813  * one connector and no cloning and hence the encoder state determines the state
4814  * of the connector. */
4815 bool intel_connector_get_hw_state(struct intel_connector *connector)
4816 {
4817         enum pipe pipe = 0;
4818         struct intel_encoder *encoder = connector->encoder;
4819
4820         return encoder->get_hw_state(encoder, &pipe);
4821 }
4822
4823 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4824                                      struct intel_crtc_config *pipe_config)
4825 {
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827         struct intel_crtc *pipe_B_crtc =
4828                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4829
4830         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4831                       pipe_name(pipe), pipe_config->fdi_lanes);
4832         if (pipe_config->fdi_lanes > 4) {
4833                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4834                               pipe_name(pipe), pipe_config->fdi_lanes);
4835                 return false;
4836         }
4837
4838         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4839                 if (pipe_config->fdi_lanes > 2) {
4840                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4841                                       pipe_config->fdi_lanes);
4842                         return false;
4843                 } else {
4844                         return true;
4845                 }
4846         }
4847
4848         if (INTEL_INFO(dev)->num_pipes == 2)
4849                 return true;
4850
4851         /* Ivybridge 3 pipe is really complicated */
4852         switch (pipe) {
4853         case PIPE_A:
4854                 return true;
4855         case PIPE_B:
4856                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4857                     pipe_config->fdi_lanes > 2) {
4858                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4859                                       pipe_name(pipe), pipe_config->fdi_lanes);
4860                         return false;
4861                 }
4862                 return true;
4863         case PIPE_C:
4864                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4865                     pipe_B_crtc->config.fdi_lanes <= 2) {
4866                         if (pipe_config->fdi_lanes > 2) {
4867                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4868                                               pipe_name(pipe), pipe_config->fdi_lanes);
4869                                 return false;
4870                         }
4871                 } else {
4872                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4873                         return false;
4874                 }
4875                 return true;
4876         default:
4877                 BUG();
4878         }
4879 }
4880
4881 #define RETRY 1
4882 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4883                                        struct intel_crtc_config *pipe_config)
4884 {
4885         struct drm_device *dev = intel_crtc->base.dev;
4886         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4887         int lane, link_bw, fdi_dotclock;
4888         bool setup_ok, needs_recompute = false;
4889
4890 retry:
4891         /* FDI is a binary signal running at ~2.7GHz, encoding
4892          * each output octet as 10 bits. The actual frequency
4893          * is stored as a divider into a 100MHz clock, and the
4894          * mode pixel clock is stored in units of 1KHz.
4895          * Hence the bw of each lane in terms of the mode signal
4896          * is:
4897          */
4898         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4899
4900         fdi_dotclock = adjusted_mode->crtc_clock;
4901
4902         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4903                                            pipe_config->pipe_bpp);
4904
4905         pipe_config->fdi_lanes = lane;
4906
4907         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4908                                link_bw, &pipe_config->fdi_m_n);
4909
4910         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4911                                             intel_crtc->pipe, pipe_config);
4912         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4913                 pipe_config->pipe_bpp -= 2*3;
4914                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4915                               pipe_config->pipe_bpp);
4916                 needs_recompute = true;
4917                 pipe_config->bw_constrained = true;
4918
4919                 goto retry;
4920         }
4921
4922         if (needs_recompute)
4923                 return RETRY;
4924
4925         return setup_ok ? 0 : -EINVAL;
4926 }
4927
4928 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4929                                    struct intel_crtc_config *pipe_config)
4930 {
4931         pipe_config->ips_enabled = i915.enable_ips &&
4932                                    hsw_crtc_supports_ips(crtc) &&
4933                                    pipe_config->pipe_bpp <= 24;
4934 }
4935
4936 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4937                                      struct intel_crtc_config *pipe_config)
4938 {
4939         struct drm_device *dev = crtc->base.dev;
4940         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4941
4942         /* FIXME should check pixel clock limits on all platforms */
4943         if (INTEL_INFO(dev)->gen < 4) {
4944                 struct drm_i915_private *dev_priv = dev->dev_private;
4945                 int clock_limit =
4946                         dev_priv->display.get_display_clock_speed(dev);
4947
4948                 /*
4949                  * Enable pixel doubling when the dot clock
4950                  * is > 90% of the (display) core speed.
4951                  *
4952                  * GDG double wide on either pipe,
4953                  * otherwise pipe A only.
4954                  */
4955                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4956                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4957                         clock_limit *= 2;
4958                         pipe_config->double_wide = true;
4959                 }
4960
4961                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4962                         return -EINVAL;
4963         }
4964
4965         /*
4966          * Pipe horizontal size must be even in:
4967          * - DVO ganged mode
4968          * - LVDS dual channel mode
4969          * - Double wide pipe
4970          */
4971         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4972              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4973                 pipe_config->pipe_src_w &= ~1;
4974
4975         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4976          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4977          */
4978         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4979                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4980                 return -EINVAL;
4981
4982         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4983                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4984         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4985                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4986                  * for lvds. */
4987                 pipe_config->pipe_bpp = 8*3;
4988         }
4989
4990         if (HAS_IPS(dev))
4991                 hsw_compute_ips_config(crtc, pipe_config);
4992
4993         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4994          * clock survives for now. */
4995         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4996                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4997
4998         if (pipe_config->has_pch_encoder)
4999                 return ironlake_fdi_compute_config(crtc, pipe_config);
5000
5001         return 0;
5002 }
5003
5004 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5005 {
5006         return 400000; /* FIXME */
5007 }
5008
5009 static int i945_get_display_clock_speed(struct drm_device *dev)
5010 {
5011         return 400000;
5012 }
5013
5014 static int i915_get_display_clock_speed(struct drm_device *dev)
5015 {
5016         return 333000;
5017 }
5018
5019 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5020 {
5021         return 200000;
5022 }
5023
5024 static int pnv_get_display_clock_speed(struct drm_device *dev)
5025 {
5026         u16 gcfgc = 0;
5027
5028         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5029
5030         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5031         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5032                 return 267000;
5033         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5034                 return 333000;
5035         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5036                 return 444000;
5037         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5038                 return 200000;
5039         default:
5040                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5041         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5042                 return 133000;
5043         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5044                 return 167000;
5045         }
5046 }
5047
5048 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5049 {
5050         u16 gcfgc = 0;
5051
5052         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5053
5054         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5055                 return 133000;
5056         else {
5057                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5058                 case GC_DISPLAY_CLOCK_333_MHZ:
5059                         return 333000;
5060                 default:
5061                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5062                         return 190000;
5063                 }
5064         }
5065 }
5066
5067 static int i865_get_display_clock_speed(struct drm_device *dev)
5068 {
5069         return 266000;
5070 }
5071
5072 static int i855_get_display_clock_speed(struct drm_device *dev)
5073 {
5074         u16 hpllcc = 0;
5075         /* Assume that the hardware is in the high speed state.  This
5076          * should be the default.
5077          */
5078         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5079         case GC_CLOCK_133_200:
5080         case GC_CLOCK_100_200:
5081                 return 200000;
5082         case GC_CLOCK_166_250:
5083                 return 250000;
5084         case GC_CLOCK_100_133:
5085                 return 133000;
5086         }
5087
5088         /* Shouldn't happen */
5089         return 0;
5090 }
5091
5092 static int i830_get_display_clock_speed(struct drm_device *dev)
5093 {
5094         return 133000;
5095 }
5096
5097 static void
5098 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5099 {
5100         while (*num > DATA_LINK_M_N_MASK ||
5101                *den > DATA_LINK_M_N_MASK) {
5102                 *num >>= 1;
5103                 *den >>= 1;
5104         }
5105 }
5106
5107 static void compute_m_n(unsigned int m, unsigned int n,
5108                         uint32_t *ret_m, uint32_t *ret_n)
5109 {
5110         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5111         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5112         intel_reduce_m_n_ratio(ret_m, ret_n);
5113 }
5114
5115 void
5116 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5117                        int pixel_clock, int link_clock,
5118                        struct intel_link_m_n *m_n)
5119 {
5120         m_n->tu = 64;
5121
5122         compute_m_n(bits_per_pixel * pixel_clock,
5123                     link_clock * nlanes * 8,
5124                     &m_n->gmch_m, &m_n->gmch_n);
5125
5126         compute_m_n(pixel_clock, link_clock,
5127                     &m_n->link_m, &m_n->link_n);
5128 }
5129
5130 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5131 {
5132         if (i915.panel_use_ssc >= 0)
5133                 return i915.panel_use_ssc != 0;
5134         return dev_priv->vbt.lvds_use_ssc
5135                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5136 }
5137
5138 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5139 {
5140         struct drm_device *dev = crtc->dev;
5141         struct drm_i915_private *dev_priv = dev->dev_private;
5142         int refclk;
5143
5144         if (IS_VALLEYVIEW(dev)) {
5145                 refclk = 100000;
5146         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5147             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5148                 refclk = dev_priv->vbt.lvds_ssc_freq;
5149                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5150         } else if (!IS_GEN2(dev)) {
5151                 refclk = 96000;
5152         } else {
5153                 refclk = 48000;
5154         }
5155
5156         return refclk;
5157 }
5158
5159 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5160 {
5161         return (1 << dpll->n) << 16 | dpll->m2;
5162 }
5163
5164 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5165 {
5166         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5167 }
5168
5169 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5170                                      intel_clock_t *reduced_clock)
5171 {
5172         struct drm_device *dev = crtc->base.dev;
5173         struct drm_i915_private *dev_priv = dev->dev_private;
5174         int pipe = crtc->pipe;
5175         u32 fp, fp2 = 0;
5176
5177         if (IS_PINEVIEW(dev)) {
5178                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5179                 if (reduced_clock)
5180                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5181         } else {
5182                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5183                 if (reduced_clock)
5184                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5185         }
5186
5187         I915_WRITE(FP0(pipe), fp);
5188         crtc->config.dpll_hw_state.fp0 = fp;
5189
5190         crtc->lowfreq_avail = false;
5191         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5192             reduced_clock && i915.powersave) {
5193                 I915_WRITE(FP1(pipe), fp2);
5194                 crtc->config.dpll_hw_state.fp1 = fp2;
5195                 crtc->lowfreq_avail = true;
5196         } else {
5197                 I915_WRITE(FP1(pipe), fp);
5198                 crtc->config.dpll_hw_state.fp1 = fp;
5199         }
5200 }
5201
5202 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5203                 pipe)
5204 {
5205         u32 reg_val;
5206
5207         /*
5208          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5209          * and set it to a reasonable value instead.
5210          */
5211         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5212         reg_val &= 0xffffff00;
5213         reg_val |= 0x00000030;
5214         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5215
5216         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5217         reg_val &= 0x8cffffff;
5218         reg_val = 0x8c000000;
5219         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5220
5221         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5222         reg_val &= 0xffffff00;
5223         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5224
5225         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5226         reg_val &= 0x00ffffff;
5227         reg_val |= 0xb0000000;
5228         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5229 }
5230
5231 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5232                                          struct intel_link_m_n *m_n)
5233 {
5234         struct drm_device *dev = crtc->base.dev;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         int pipe = crtc->pipe;
5237
5238         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5239         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5240         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5241         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5242 }
5243
5244 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5245                                          struct intel_link_m_n *m_n)
5246 {
5247         struct drm_device *dev = crtc->base.dev;
5248         struct drm_i915_private *dev_priv = dev->dev_private;
5249         int pipe = crtc->pipe;
5250         enum transcoder transcoder = crtc->config.cpu_transcoder;
5251
5252         if (INTEL_INFO(dev)->gen >= 5) {
5253                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5254                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5255                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5256                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5257         } else {
5258                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5259                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5260                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5261                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5262         }
5263 }
5264
5265 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5266 {
5267         if (crtc->config.has_pch_encoder)
5268                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5269         else
5270                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5271 }
5272
5273 static void vlv_update_pll(struct intel_crtc *crtc)
5274 {
5275         struct drm_device *dev = crtc->base.dev;
5276         struct drm_i915_private *dev_priv = dev->dev_private;
5277         int pipe = crtc->pipe;
5278         u32 dpll, mdiv;
5279         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5280         u32 coreclk, reg_val, dpll_md;
5281
5282         mutex_lock(&dev_priv->dpio_lock);
5283
5284         bestn = crtc->config.dpll.n;
5285         bestm1 = crtc->config.dpll.m1;
5286         bestm2 = crtc->config.dpll.m2;
5287         bestp1 = crtc->config.dpll.p1;
5288         bestp2 = crtc->config.dpll.p2;
5289
5290         /* See eDP HDMI DPIO driver vbios notes doc */
5291
5292         /* PLL B needs special handling */
5293         if (pipe)
5294                 vlv_pllb_recal_opamp(dev_priv, pipe);
5295
5296         /* Set up Tx target for periodic Rcomp update */
5297         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5298
5299         /* Disable target IRef on PLL */
5300         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5301         reg_val &= 0x00ffffff;
5302         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5303
5304         /* Disable fast lock */
5305         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5306
5307         /* Set idtafcrecal before PLL is enabled */
5308         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5309         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5310         mdiv |= ((bestn << DPIO_N_SHIFT));
5311         mdiv |= (1 << DPIO_K_SHIFT);
5312
5313         /*
5314          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5315          * but we don't support that).
5316          * Note: don't use the DAC post divider as it seems unstable.
5317          */
5318         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5319         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5320
5321         mdiv |= DPIO_ENABLE_CALIBRATION;
5322         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5323
5324         /* Set HBR and RBR LPF coefficients */
5325         if (crtc->config.port_clock == 162000 ||
5326             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5327             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5328                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5329                                  0x009f0003);
5330         else
5331                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5332                                  0x00d0000f);
5333
5334         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5335             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5336                 /* Use SSC source */
5337                 if (!pipe)
5338                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5339                                          0x0df40000);
5340                 else
5341                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5342                                          0x0df70000);
5343         } else { /* HDMI or VGA */
5344                 /* Use bend source */
5345                 if (!pipe)
5346                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5347                                          0x0df70000);
5348                 else
5349                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5350                                          0x0df40000);
5351         }
5352
5353         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5354         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5355         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5356             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5357                 coreclk |= 0x01000000;
5358         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5359
5360         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5361
5362         /*
5363          * Enable DPIO clock input. We should never disable the reference
5364          * clock for pipe B, since VGA hotplug / manual detection depends
5365          * on it.
5366          */
5367         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5368                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5369         /* We should never disable this, set it here for state tracking */
5370         if (pipe == PIPE_B)
5371                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5372         dpll |= DPLL_VCO_ENABLE;
5373         crtc->config.dpll_hw_state.dpll = dpll;
5374
5375         dpll_md = (crtc->config.pixel_multiplier - 1)
5376                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5377         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5378
5379         mutex_unlock(&dev_priv->dpio_lock);
5380 }
5381
5382 static void chv_update_pll(struct intel_crtc *crtc)
5383 {
5384         struct drm_device *dev = crtc->base.dev;
5385         struct drm_i915_private *dev_priv = dev->dev_private;
5386         int pipe = crtc->pipe;
5387         int dpll_reg = DPLL(crtc->pipe);
5388         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5389         u32 val, loopfilter, intcoeff;
5390         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5391         int refclk;
5392
5393         mutex_lock(&dev_priv->dpio_lock);
5394
5395         bestn = crtc->config.dpll.n;
5396         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5397         bestm1 = crtc->config.dpll.m1;
5398         bestm2 = crtc->config.dpll.m2 >> 22;
5399         bestp1 = crtc->config.dpll.p1;
5400         bestp2 = crtc->config.dpll.p2;
5401
5402         /*
5403          * Enable Refclk and SSC
5404          */
5405         val = I915_READ(dpll_reg);
5406         val |= (DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV);
5407         I915_WRITE(dpll_reg, val);
5408
5409         /* Propagate soft reset to data lane reset */
5410         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5411         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5412         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5413
5414         /* Disable 10bit clock to display controller */
5415         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5416         val &= ~DPIO_DCLKP_EN;
5417         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5418
5419         /* p1 and p2 divider */
5420         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5421                         5 << DPIO_CHV_S1_DIV_SHIFT |
5422                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5423                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5424                         1 << DPIO_CHV_K_DIV_SHIFT);
5425
5426         /* Feedback post-divider - m2 */
5427         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5428
5429         /* Feedback refclk divider - n and m1 */
5430         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5431                         DPIO_CHV_M1_DIV_BY_2 |
5432                         1 << DPIO_CHV_N_DIV_SHIFT);
5433
5434         /* M2 fraction division */
5435         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5436
5437         /* M2 fraction division enable */
5438         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5439                        DPIO_CHV_FRAC_DIV_EN |
5440                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5441
5442         /* Loop filter */
5443         refclk = i9xx_get_refclk(&crtc->base, 0);
5444         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5445                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5446         if (refclk == 100000)
5447                 intcoeff = 11;
5448         else if (refclk == 38400)
5449                 intcoeff = 10;
5450         else
5451                 intcoeff = 9;
5452         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5453         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5454
5455         /* AFC Recal */
5456         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5457                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5458                         DPIO_AFC_RECAL);
5459
5460         mutex_unlock(&dev_priv->dpio_lock);
5461 }
5462
5463 static void i9xx_update_pll(struct intel_crtc *crtc,
5464                             intel_clock_t *reduced_clock,
5465                             int num_connectors)
5466 {
5467         struct drm_device *dev = crtc->base.dev;
5468         struct drm_i915_private *dev_priv = dev->dev_private;
5469         u32 dpll;
5470         bool is_sdvo;
5471         struct dpll *clock = &crtc->config.dpll;
5472
5473         i9xx_update_pll_dividers(crtc, reduced_clock);
5474
5475         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5476                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5477
5478         dpll = DPLL_VGA_MODE_DIS;
5479
5480         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5481                 dpll |= DPLLB_MODE_LVDS;
5482         else
5483                 dpll |= DPLLB_MODE_DAC_SERIAL;
5484
5485         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5486                 dpll |= (crtc->config.pixel_multiplier - 1)
5487                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5488         }
5489
5490         if (is_sdvo)
5491                 dpll |= DPLL_SDVO_HIGH_SPEED;
5492
5493         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5494                 dpll |= DPLL_SDVO_HIGH_SPEED;
5495
5496         /* compute bitmask from p1 value */
5497         if (IS_PINEVIEW(dev))
5498                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5499         else {
5500                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5501                 if (IS_G4X(dev) && reduced_clock)
5502                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5503         }
5504         switch (clock->p2) {
5505         case 5:
5506                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5507                 break;
5508         case 7:
5509                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5510                 break;
5511         case 10:
5512                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5513                 break;
5514         case 14:
5515                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5516                 break;
5517         }
5518         if (INTEL_INFO(dev)->gen >= 4)
5519                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5520
5521         if (crtc->config.sdvo_tv_clock)
5522                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5523         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5524                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5525                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5526         else
5527                 dpll |= PLL_REF_INPUT_DREFCLK;
5528
5529         dpll |= DPLL_VCO_ENABLE;
5530         crtc->config.dpll_hw_state.dpll = dpll;
5531
5532         if (INTEL_INFO(dev)->gen >= 4) {
5533                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5534                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5535                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5536         }
5537 }
5538
5539 static void i8xx_update_pll(struct intel_crtc *crtc,
5540                             intel_clock_t *reduced_clock,
5541                             int num_connectors)
5542 {
5543         struct drm_device *dev = crtc->base.dev;
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         u32 dpll;
5546         struct dpll *clock = &crtc->config.dpll;
5547
5548         i9xx_update_pll_dividers(crtc, reduced_clock);
5549
5550         dpll = DPLL_VGA_MODE_DIS;
5551
5552         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5553                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5554         } else {
5555                 if (clock->p1 == 2)
5556                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5557                 else
5558                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5559                 if (clock->p2 == 4)
5560                         dpll |= PLL_P2_DIVIDE_BY_4;
5561         }
5562
5563         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5564                 dpll |= DPLL_DVO_2X_MODE;
5565
5566         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5567                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5568                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5569         else
5570                 dpll |= PLL_REF_INPUT_DREFCLK;
5571
5572         dpll |= DPLL_VCO_ENABLE;
5573         crtc->config.dpll_hw_state.dpll = dpll;
5574 }
5575
5576 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5577 {
5578         struct drm_device *dev = intel_crtc->base.dev;
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         enum pipe pipe = intel_crtc->pipe;
5581         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5582         struct drm_display_mode *adjusted_mode =
5583                 &intel_crtc->config.adjusted_mode;
5584         uint32_t crtc_vtotal, crtc_vblank_end;
5585         int vsyncshift = 0;
5586
5587         /* We need to be careful not to changed the adjusted mode, for otherwise
5588          * the hw state checker will get angry at the mismatch. */
5589         crtc_vtotal = adjusted_mode->crtc_vtotal;
5590         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5591
5592         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5593                 /* the chip adds 2 halflines automatically */
5594                 crtc_vtotal -= 1;
5595                 crtc_vblank_end -= 1;
5596
5597                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5598                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5599                 else
5600                         vsyncshift = adjusted_mode->crtc_hsync_start -
5601                                 adjusted_mode->crtc_htotal / 2;
5602                 if (vsyncshift < 0)
5603                         vsyncshift += adjusted_mode->crtc_htotal;
5604         }
5605
5606         if (INTEL_INFO(dev)->gen > 3)
5607                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5608
5609         I915_WRITE(HTOTAL(cpu_transcoder),
5610                    (adjusted_mode->crtc_hdisplay - 1) |
5611                    ((adjusted_mode->crtc_htotal - 1) << 16));
5612         I915_WRITE(HBLANK(cpu_transcoder),
5613                    (adjusted_mode->crtc_hblank_start - 1) |
5614                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5615         I915_WRITE(HSYNC(cpu_transcoder),
5616                    (adjusted_mode->crtc_hsync_start - 1) |
5617                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5618
5619         I915_WRITE(VTOTAL(cpu_transcoder),
5620                    (adjusted_mode->crtc_vdisplay - 1) |
5621                    ((crtc_vtotal - 1) << 16));
5622         I915_WRITE(VBLANK(cpu_transcoder),
5623                    (adjusted_mode->crtc_vblank_start - 1) |
5624                    ((crtc_vblank_end - 1) << 16));
5625         I915_WRITE(VSYNC(cpu_transcoder),
5626                    (adjusted_mode->crtc_vsync_start - 1) |
5627                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5628
5629         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5630          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5631          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5632          * bits. */
5633         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5634             (pipe == PIPE_B || pipe == PIPE_C))
5635                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5636
5637         /* pipesrc controls the size that is scaled from, which should
5638          * always be the user's requested size.
5639          */
5640         I915_WRITE(PIPESRC(pipe),
5641                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5642                    (intel_crtc->config.pipe_src_h - 1));
5643 }
5644
5645 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5646                                    struct intel_crtc_config *pipe_config)
5647 {
5648         struct drm_device *dev = crtc->base.dev;
5649         struct drm_i915_private *dev_priv = dev->dev_private;
5650         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5651         uint32_t tmp;
5652
5653         tmp = I915_READ(HTOTAL(cpu_transcoder));
5654         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5655         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5656         tmp = I915_READ(HBLANK(cpu_transcoder));
5657         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5658         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5659         tmp = I915_READ(HSYNC(cpu_transcoder));
5660         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5661         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5662
5663         tmp = I915_READ(VTOTAL(cpu_transcoder));
5664         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5665         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5666         tmp = I915_READ(VBLANK(cpu_transcoder));
5667         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5668         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5669         tmp = I915_READ(VSYNC(cpu_transcoder));
5670         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5671         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5672
5673         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5674                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5675                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5676                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5677         }
5678
5679         tmp = I915_READ(PIPESRC(crtc->pipe));
5680         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5681         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5682
5683         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5684         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5685 }
5686
5687 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5688                                  struct intel_crtc_config *pipe_config)
5689 {
5690         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5691         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5692         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5693         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5694
5695         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5696         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5697         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5698         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5699
5700         mode->flags = pipe_config->adjusted_mode.flags;
5701
5702         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5703         mode->flags |= pipe_config->adjusted_mode.flags;
5704 }
5705
5706 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5707 {
5708         struct drm_device *dev = intel_crtc->base.dev;
5709         struct drm_i915_private *dev_priv = dev->dev_private;
5710         uint32_t pipeconf;
5711
5712         pipeconf = 0;
5713
5714         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5715             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5716                 pipeconf |= PIPECONF_ENABLE;
5717
5718         if (intel_crtc->config.double_wide)
5719                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5720
5721         /* only g4x and later have fancy bpc/dither controls */
5722         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5723                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5724                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5725                         pipeconf |= PIPECONF_DITHER_EN |
5726                                     PIPECONF_DITHER_TYPE_SP;
5727
5728                 switch (intel_crtc->config.pipe_bpp) {
5729                 case 18:
5730                         pipeconf |= PIPECONF_6BPC;
5731                         break;
5732                 case 24:
5733                         pipeconf |= PIPECONF_8BPC;
5734                         break;
5735                 case 30:
5736                         pipeconf |= PIPECONF_10BPC;
5737                         break;
5738                 default:
5739                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5740                         BUG();
5741                 }
5742         }
5743
5744         if (HAS_PIPE_CXSR(dev)) {
5745                 if (intel_crtc->lowfreq_avail) {
5746                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5747                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5748                 } else {
5749                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5750                 }
5751         }
5752
5753         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5754                 if (INTEL_INFO(dev)->gen < 4 ||
5755                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5756                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5757                 else
5758                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5759         } else
5760                 pipeconf |= PIPECONF_PROGRESSIVE;
5761
5762         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5763                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5764
5765         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5766         POSTING_READ(PIPECONF(intel_crtc->pipe));
5767 }
5768
5769 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5770                               int x, int y,
5771                               struct drm_framebuffer *fb)
5772 {
5773         struct drm_device *dev = crtc->dev;
5774         struct drm_i915_private *dev_priv = dev->dev_private;
5775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776         int pipe = intel_crtc->pipe;
5777         int plane = intel_crtc->plane;
5778         int refclk, num_connectors = 0;
5779         intel_clock_t clock, reduced_clock;
5780         u32 dspcntr;
5781         bool ok, has_reduced_clock = false;
5782         bool is_lvds = false, is_dsi = false;
5783         struct intel_encoder *encoder;
5784         const intel_limit_t *limit;
5785         int ret;
5786
5787         for_each_encoder_on_crtc(dev, crtc, encoder) {
5788                 switch (encoder->type) {
5789                 case INTEL_OUTPUT_LVDS:
5790                         is_lvds = true;
5791                         break;
5792                 case INTEL_OUTPUT_DSI:
5793                         is_dsi = true;
5794                         break;
5795                 }
5796
5797                 num_connectors++;
5798         }
5799
5800         if (is_dsi)
5801                 goto skip_dpll;
5802
5803         if (!intel_crtc->config.clock_set) {
5804                 refclk = i9xx_get_refclk(crtc, num_connectors);
5805
5806                 /*
5807                  * Returns a set of divisors for the desired target clock with
5808                  * the given refclk, or FALSE.  The returned values represent
5809                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5810                  * 2) / p1 / p2.
5811                  */
5812                 limit = intel_limit(crtc, refclk);
5813                 ok = dev_priv->display.find_dpll(limit, crtc,
5814                                                  intel_crtc->config.port_clock,
5815                                                  refclk, NULL, &clock);
5816                 if (!ok) {
5817                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5818                         return -EINVAL;
5819                 }
5820
5821                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5822                         /*
5823                          * Ensure we match the reduced clock's P to the target
5824                          * clock.  If the clocks don't match, we can't switch
5825                          * the display clock by using the FP0/FP1. In such case
5826                          * we will disable the LVDS downclock feature.
5827                          */
5828                         has_reduced_clock =
5829                                 dev_priv->display.find_dpll(limit, crtc,
5830                                                             dev_priv->lvds_downclock,
5831                                                             refclk, &clock,
5832                                                             &reduced_clock);
5833                 }
5834                 /* Compat-code for transition, will disappear. */
5835                 intel_crtc->config.dpll.n = clock.n;
5836                 intel_crtc->config.dpll.m1 = clock.m1;
5837                 intel_crtc->config.dpll.m2 = clock.m2;
5838                 intel_crtc->config.dpll.p1 = clock.p1;
5839                 intel_crtc->config.dpll.p2 = clock.p2;
5840         }
5841
5842         if (IS_GEN2(dev)) {
5843                 i8xx_update_pll(intel_crtc,
5844                                 has_reduced_clock ? &reduced_clock : NULL,
5845                                 num_connectors);
5846         } else if (IS_CHERRYVIEW(dev)) {
5847                 chv_update_pll(intel_crtc);
5848         } else if (IS_VALLEYVIEW(dev)) {
5849                 vlv_update_pll(intel_crtc);
5850         } else {
5851                 i9xx_update_pll(intel_crtc,
5852                                 has_reduced_clock ? &reduced_clock : NULL,
5853                                 num_connectors);
5854         }
5855
5856 skip_dpll:
5857         /* Set up the display plane register */
5858         dspcntr = DISPPLANE_GAMMA_ENABLE;
5859
5860         if (!IS_VALLEYVIEW(dev)) {
5861                 if (pipe == 0)
5862                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5863                 else
5864                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5865         }
5866
5867         if (intel_crtc->config.has_dp_encoder)
5868                 intel_dp_set_m_n(intel_crtc);
5869
5870         intel_set_pipe_timings(intel_crtc);
5871
5872         /* pipesrc and dspsize control the size that is scaled from,
5873          * which should always be the user's requested size.
5874          */
5875         I915_WRITE(DSPSIZE(plane),
5876                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5877                    (intel_crtc->config.pipe_src_w - 1));
5878         I915_WRITE(DSPPOS(plane), 0);
5879
5880         i9xx_set_pipeconf(intel_crtc);
5881
5882         I915_WRITE(DSPCNTR(plane), dspcntr);
5883         POSTING_READ(DSPCNTR(plane));
5884
5885         ret = intel_pipe_set_base(crtc, x, y, fb);
5886
5887         return ret;
5888 }
5889
5890 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5891                                  struct intel_crtc_config *pipe_config)
5892 {
5893         struct drm_device *dev = crtc->base.dev;
5894         struct drm_i915_private *dev_priv = dev->dev_private;
5895         uint32_t tmp;
5896
5897         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5898                 return;
5899
5900         tmp = I915_READ(PFIT_CONTROL);
5901         if (!(tmp & PFIT_ENABLE))
5902                 return;
5903
5904         /* Check whether the pfit is attached to our pipe. */
5905         if (INTEL_INFO(dev)->gen < 4) {
5906                 if (crtc->pipe != PIPE_B)
5907                         return;
5908         } else {
5909                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5910                         return;
5911         }
5912
5913         pipe_config->gmch_pfit.control = tmp;
5914         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5915         if (INTEL_INFO(dev)->gen < 5)
5916                 pipe_config->gmch_pfit.lvds_border_bits =
5917                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5918 }
5919
5920 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5921                                struct intel_crtc_config *pipe_config)
5922 {
5923         struct drm_device *dev = crtc->base.dev;
5924         struct drm_i915_private *dev_priv = dev->dev_private;
5925         int pipe = pipe_config->cpu_transcoder;
5926         intel_clock_t clock;
5927         u32 mdiv;
5928         int refclk = 100000;
5929
5930         mutex_lock(&dev_priv->dpio_lock);
5931         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5932         mutex_unlock(&dev_priv->dpio_lock);
5933
5934         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5935         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5936         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5937         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5938         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5939
5940         vlv_clock(refclk, &clock);
5941
5942         /* clock.dot is the fast clock */
5943         pipe_config->port_clock = clock.dot / 5;
5944 }
5945
5946 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5947                                   struct intel_plane_config *plane_config)
5948 {
5949         struct drm_device *dev = crtc->base.dev;
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951         u32 val, base, offset;
5952         int pipe = crtc->pipe, plane = crtc->plane;
5953         int fourcc, pixel_format;
5954         int aligned_height;
5955
5956         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5957         if (!crtc->base.primary->fb) {
5958                 DRM_DEBUG_KMS("failed to alloc fb\n");
5959                 return;
5960         }
5961
5962         val = I915_READ(DSPCNTR(plane));
5963
5964         if (INTEL_INFO(dev)->gen >= 4)
5965                 if (val & DISPPLANE_TILED)
5966                         plane_config->tiled = true;
5967
5968         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5969         fourcc = intel_format_to_fourcc(pixel_format);
5970         crtc->base.primary->fb->pixel_format = fourcc;
5971         crtc->base.primary->fb->bits_per_pixel =
5972                 drm_format_plane_cpp(fourcc, 0) * 8;
5973
5974         if (INTEL_INFO(dev)->gen >= 4) {
5975                 if (plane_config->tiled)
5976                         offset = I915_READ(DSPTILEOFF(plane));
5977                 else
5978                         offset = I915_READ(DSPLINOFF(plane));
5979                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5980         } else {
5981                 base = I915_READ(DSPADDR(plane));
5982         }
5983         plane_config->base = base;
5984
5985         val = I915_READ(PIPESRC(pipe));
5986         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5987         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5988
5989         val = I915_READ(DSPSTRIDE(pipe));
5990         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5991
5992         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5993                                             plane_config->tiled);
5994
5995         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5996                                    aligned_height, PAGE_SIZE);
5997
5998         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5999                       pipe, plane, crtc->base.primary->fb->width,
6000                       crtc->base.primary->fb->height,
6001                       crtc->base.primary->fb->bits_per_pixel, base,
6002                       crtc->base.primary->fb->pitches[0],
6003                       plane_config->size);
6004
6005 }
6006
6007 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6008                                struct intel_crtc_config *pipe_config)
6009 {
6010         struct drm_device *dev = crtc->base.dev;
6011         struct drm_i915_private *dev_priv = dev->dev_private;
6012         int pipe = pipe_config->cpu_transcoder;
6013         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6014         intel_clock_t clock;
6015         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6016         int refclk = 100000;
6017
6018         mutex_lock(&dev_priv->dpio_lock);
6019         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6020         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6021         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6022         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6023         mutex_unlock(&dev_priv->dpio_lock);
6024
6025         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6026         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6027         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6028         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6029         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6030
6031         chv_clock(refclk, &clock);
6032
6033         /* clock.dot is the fast clock */
6034         pipe_config->port_clock = clock.dot / 5;
6035 }
6036
6037 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6038                                  struct intel_crtc_config *pipe_config)
6039 {
6040         struct drm_device *dev = crtc->base.dev;
6041         struct drm_i915_private *dev_priv = dev->dev_private;
6042         uint32_t tmp;
6043
6044         if (!intel_display_power_enabled(dev_priv,
6045                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6046                 return false;
6047
6048         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6049         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6050
6051         tmp = I915_READ(PIPECONF(crtc->pipe));
6052         if (!(tmp & PIPECONF_ENABLE))
6053                 return false;
6054
6055         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6056                 switch (tmp & PIPECONF_BPC_MASK) {
6057                 case PIPECONF_6BPC:
6058                         pipe_config->pipe_bpp = 18;
6059                         break;
6060                 case PIPECONF_8BPC:
6061                         pipe_config->pipe_bpp = 24;
6062                         break;
6063                 case PIPECONF_10BPC:
6064                         pipe_config->pipe_bpp = 30;
6065                         break;
6066                 default:
6067                         break;
6068                 }
6069         }
6070
6071         if (INTEL_INFO(dev)->gen < 4)
6072                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6073
6074         intel_get_pipe_timings(crtc, pipe_config);
6075
6076         i9xx_get_pfit_config(crtc, pipe_config);
6077
6078         if (INTEL_INFO(dev)->gen >= 4) {
6079                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6080                 pipe_config->pixel_multiplier =
6081                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6082                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6083                 pipe_config->dpll_hw_state.dpll_md = tmp;
6084         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6085                 tmp = I915_READ(DPLL(crtc->pipe));
6086                 pipe_config->pixel_multiplier =
6087                         ((tmp & SDVO_MULTIPLIER_MASK)
6088                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6089         } else {
6090                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6091                  * port and will be fixed up in the encoder->get_config
6092                  * function. */
6093                 pipe_config->pixel_multiplier = 1;
6094         }
6095         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6096         if (!IS_VALLEYVIEW(dev)) {
6097                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6098                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6099         } else {
6100                 /* Mask out read-only status bits. */
6101                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6102                                                      DPLL_PORTC_READY_MASK |
6103                                                      DPLL_PORTB_READY_MASK);
6104         }
6105
6106         if (IS_CHERRYVIEW(dev))
6107                 chv_crtc_clock_get(crtc, pipe_config);
6108         else if (IS_VALLEYVIEW(dev))
6109                 vlv_crtc_clock_get(crtc, pipe_config);
6110         else
6111                 i9xx_crtc_clock_get(crtc, pipe_config);
6112
6113         return true;
6114 }
6115
6116 static void ironlake_init_pch_refclk(struct drm_device *dev)
6117 {
6118         struct drm_i915_private *dev_priv = dev->dev_private;
6119         struct drm_mode_config *mode_config = &dev->mode_config;
6120         struct intel_encoder *encoder;
6121         u32 val, final;
6122         bool has_lvds = false;
6123         bool has_cpu_edp = false;
6124         bool has_panel = false;
6125         bool has_ck505 = false;
6126         bool can_ssc = false;
6127
6128         /* We need to take the global config into account */
6129         list_for_each_entry(encoder, &mode_config->encoder_list,
6130                             base.head) {
6131                 switch (encoder->type) {
6132                 case INTEL_OUTPUT_LVDS:
6133                         has_panel = true;
6134                         has_lvds = true;
6135                         break;
6136                 case INTEL_OUTPUT_EDP:
6137                         has_panel = true;
6138                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6139                                 has_cpu_edp = true;
6140                         break;
6141                 }
6142         }
6143
6144         if (HAS_PCH_IBX(dev)) {
6145                 has_ck505 = dev_priv->vbt.display_clock_mode;
6146                 can_ssc = has_ck505;
6147         } else {
6148                 has_ck505 = false;
6149                 can_ssc = true;
6150         }
6151
6152         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6153                       has_panel, has_lvds, has_ck505);
6154
6155         /* Ironlake: try to setup display ref clock before DPLL
6156          * enabling. This is only under driver's control after
6157          * PCH B stepping, previous chipset stepping should be
6158          * ignoring this setting.
6159          */
6160         val = I915_READ(PCH_DREF_CONTROL);
6161
6162         /* As we must carefully and slowly disable/enable each source in turn,
6163          * compute the final state we want first and check if we need to
6164          * make any changes at all.
6165          */
6166         final = val;
6167         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6168         if (has_ck505)
6169                 final |= DREF_NONSPREAD_CK505_ENABLE;
6170         else
6171                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6172
6173         final &= ~DREF_SSC_SOURCE_MASK;
6174         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6175         final &= ~DREF_SSC1_ENABLE;
6176
6177         if (has_panel) {
6178                 final |= DREF_SSC_SOURCE_ENABLE;
6179
6180                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6181                         final |= DREF_SSC1_ENABLE;
6182
6183                 if (has_cpu_edp) {
6184                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6185                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6186                         else
6187                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6188                 } else
6189                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6190         } else {
6191                 final |= DREF_SSC_SOURCE_DISABLE;
6192                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6193         }
6194
6195         if (final == val)
6196                 return;
6197
6198         /* Always enable nonspread source */
6199         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6200
6201         if (has_ck505)
6202                 val |= DREF_NONSPREAD_CK505_ENABLE;
6203         else
6204                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6205
6206         if (has_panel) {
6207                 val &= ~DREF_SSC_SOURCE_MASK;
6208                 val |= DREF_SSC_SOURCE_ENABLE;
6209
6210                 /* SSC must be turned on before enabling the CPU output  */
6211                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6212                         DRM_DEBUG_KMS("Using SSC on panel\n");
6213                         val |= DREF_SSC1_ENABLE;
6214                 } else
6215                         val &= ~DREF_SSC1_ENABLE;
6216
6217                 /* Get SSC going before enabling the outputs */
6218                 I915_WRITE(PCH_DREF_CONTROL, val);
6219                 POSTING_READ(PCH_DREF_CONTROL);
6220                 udelay(200);
6221
6222                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6223
6224                 /* Enable CPU source on CPU attached eDP */
6225                 if (has_cpu_edp) {
6226                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6227                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6228                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6229                         }
6230                         else
6231                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6232                 } else
6233                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6234
6235                 I915_WRITE(PCH_DREF_CONTROL, val);
6236                 POSTING_READ(PCH_DREF_CONTROL);
6237                 udelay(200);
6238         } else {
6239                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6240
6241                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6242
6243                 /* Turn off CPU output */
6244                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6245
6246                 I915_WRITE(PCH_DREF_CONTROL, val);
6247                 POSTING_READ(PCH_DREF_CONTROL);
6248                 udelay(200);
6249
6250                 /* Turn off the SSC source */
6251                 val &= ~DREF_SSC_SOURCE_MASK;
6252                 val |= DREF_SSC_SOURCE_DISABLE;
6253
6254                 /* Turn off SSC1 */
6255                 val &= ~DREF_SSC1_ENABLE;
6256
6257                 I915_WRITE(PCH_DREF_CONTROL, val);
6258                 POSTING_READ(PCH_DREF_CONTROL);
6259                 udelay(200);
6260         }
6261
6262         BUG_ON(val != final);
6263 }
6264
6265 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6266 {
6267         uint32_t tmp;
6268
6269         tmp = I915_READ(SOUTH_CHICKEN2);
6270         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6271         I915_WRITE(SOUTH_CHICKEN2, tmp);
6272
6273         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6274                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6275                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6276
6277         tmp = I915_READ(SOUTH_CHICKEN2);
6278         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6279         I915_WRITE(SOUTH_CHICKEN2, tmp);
6280
6281         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6282                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6283                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6284 }
6285
6286 /* WaMPhyProgramming:hsw */
6287 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6288 {
6289         uint32_t tmp;
6290
6291         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6292         tmp &= ~(0xFF << 24);
6293         tmp |= (0x12 << 24);
6294         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6295
6296         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6297         tmp |= (1 << 11);
6298         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6299
6300         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6301         tmp |= (1 << 11);
6302         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6303
6304         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6305         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6306         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6307
6308         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6309         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6310         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6311
6312         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6313         tmp &= ~(7 << 13);
6314         tmp |= (5 << 13);
6315         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6316
6317         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6318         tmp &= ~(7 << 13);
6319         tmp |= (5 << 13);
6320         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6321
6322         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6323         tmp &= ~0xFF;
6324         tmp |= 0x1C;
6325         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6326
6327         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6328         tmp &= ~0xFF;
6329         tmp |= 0x1C;
6330         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6331
6332         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6333         tmp &= ~(0xFF << 16);
6334         tmp |= (0x1C << 16);
6335         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6336
6337         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6338         tmp &= ~(0xFF << 16);
6339         tmp |= (0x1C << 16);
6340         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6341
6342         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6343         tmp |= (1 << 27);
6344         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6345
6346         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6347         tmp |= (1 << 27);
6348         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6349
6350         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6351         tmp &= ~(0xF << 28);
6352         tmp |= (4 << 28);
6353         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6354
6355         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6356         tmp &= ~(0xF << 28);
6357         tmp |= (4 << 28);
6358         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6359 }
6360
6361 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6362  * Programming" based on the parameters passed:
6363  * - Sequence to enable CLKOUT_DP
6364  * - Sequence to enable CLKOUT_DP without spread
6365  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6366  */
6367 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6368                                  bool with_fdi)
6369 {
6370         struct drm_i915_private *dev_priv = dev->dev_private;
6371         uint32_t reg, tmp;
6372
6373         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6374                 with_spread = true;
6375         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6376                  with_fdi, "LP PCH doesn't have FDI\n"))
6377                 with_fdi = false;
6378
6379         mutex_lock(&dev_priv->dpio_lock);
6380
6381         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6382         tmp &= ~SBI_SSCCTL_DISABLE;
6383         tmp |= SBI_SSCCTL_PATHALT;
6384         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6385
6386         udelay(24);
6387
6388         if (with_spread) {
6389                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6390                 tmp &= ~SBI_SSCCTL_PATHALT;
6391                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6392
6393                 if (with_fdi) {
6394                         lpt_reset_fdi_mphy(dev_priv);
6395                         lpt_program_fdi_mphy(dev_priv);
6396                 }
6397         }
6398
6399         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6400                SBI_GEN0 : SBI_DBUFF0;
6401         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6402         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6403         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6404
6405         mutex_unlock(&dev_priv->dpio_lock);
6406 }
6407
6408 /* Sequence to disable CLKOUT_DP */
6409 static void lpt_disable_clkout_dp(struct drm_device *dev)
6410 {
6411         struct drm_i915_private *dev_priv = dev->dev_private;
6412         uint32_t reg, tmp;
6413
6414         mutex_lock(&dev_priv->dpio_lock);
6415
6416         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6417                SBI_GEN0 : SBI_DBUFF0;
6418         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6419         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6420         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6421
6422         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6423         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6424                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6425                         tmp |= SBI_SSCCTL_PATHALT;
6426                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6427                         udelay(32);
6428                 }
6429                 tmp |= SBI_SSCCTL_DISABLE;
6430                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6431         }
6432
6433         mutex_unlock(&dev_priv->dpio_lock);
6434 }
6435
6436 static void lpt_init_pch_refclk(struct drm_device *dev)
6437 {
6438         struct drm_mode_config *mode_config = &dev->mode_config;
6439         struct intel_encoder *encoder;
6440         bool has_vga = false;
6441
6442         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6443                 switch (encoder->type) {
6444                 case INTEL_OUTPUT_ANALOG:
6445                         has_vga = true;
6446                         break;
6447                 }
6448         }
6449
6450         if (has_vga)
6451                 lpt_enable_clkout_dp(dev, true, true);
6452         else
6453                 lpt_disable_clkout_dp(dev);
6454 }
6455
6456 /*
6457  * Initialize reference clocks when the driver loads
6458  */
6459 void intel_init_pch_refclk(struct drm_device *dev)
6460 {
6461         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6462                 ironlake_init_pch_refclk(dev);
6463         else if (HAS_PCH_LPT(dev))
6464                 lpt_init_pch_refclk(dev);
6465 }
6466
6467 static int ironlake_get_refclk(struct drm_crtc *crtc)
6468 {
6469         struct drm_device *dev = crtc->dev;
6470         struct drm_i915_private *dev_priv = dev->dev_private;
6471         struct intel_encoder *encoder;
6472         int num_connectors = 0;
6473         bool is_lvds = false;
6474
6475         for_each_encoder_on_crtc(dev, crtc, encoder) {
6476                 switch (encoder->type) {
6477                 case INTEL_OUTPUT_LVDS:
6478                         is_lvds = true;
6479                         break;
6480                 }
6481                 num_connectors++;
6482         }
6483
6484         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6485                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6486                               dev_priv->vbt.lvds_ssc_freq);
6487                 return dev_priv->vbt.lvds_ssc_freq;
6488         }
6489
6490         return 120000;
6491 }
6492
6493 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6494 {
6495         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497         int pipe = intel_crtc->pipe;
6498         uint32_t val;
6499
6500         val = 0;
6501
6502         switch (intel_crtc->config.pipe_bpp) {
6503         case 18:
6504                 val |= PIPECONF_6BPC;
6505                 break;
6506         case 24:
6507                 val |= PIPECONF_8BPC;
6508                 break;
6509         case 30:
6510                 val |= PIPECONF_10BPC;
6511                 break;
6512         case 36:
6513                 val |= PIPECONF_12BPC;
6514                 break;
6515         default:
6516                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6517                 BUG();
6518         }
6519
6520         if (intel_crtc->config.dither)
6521                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6522
6523         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6524                 val |= PIPECONF_INTERLACED_ILK;
6525         else
6526                 val |= PIPECONF_PROGRESSIVE;
6527
6528         if (intel_crtc->config.limited_color_range)
6529                 val |= PIPECONF_COLOR_RANGE_SELECT;
6530
6531         I915_WRITE(PIPECONF(pipe), val);
6532         POSTING_READ(PIPECONF(pipe));
6533 }
6534
6535 /*
6536  * Set up the pipe CSC unit.
6537  *
6538  * Currently only full range RGB to limited range RGB conversion
6539  * is supported, but eventually this should handle various
6540  * RGB<->YCbCr scenarios as well.
6541  */
6542 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6543 {
6544         struct drm_device *dev = crtc->dev;
6545         struct drm_i915_private *dev_priv = dev->dev_private;
6546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547         int pipe = intel_crtc->pipe;
6548         uint16_t coeff = 0x7800; /* 1.0 */
6549
6550         /*
6551          * TODO: Check what kind of values actually come out of the pipe
6552          * with these coeff/postoff values and adjust to get the best
6553          * accuracy. Perhaps we even need to take the bpc value into
6554          * consideration.
6555          */
6556
6557         if (intel_crtc->config.limited_color_range)
6558                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6559
6560         /*
6561          * GY/GU and RY/RU should be the other way around according
6562          * to BSpec, but reality doesn't agree. Just set them up in
6563          * a way that results in the correct picture.
6564          */
6565         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6566         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6567
6568         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6569         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6570
6571         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6572         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6573
6574         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6575         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6576         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6577
6578         if (INTEL_INFO(dev)->gen > 6) {
6579                 uint16_t postoff = 0;
6580
6581                 if (intel_crtc->config.limited_color_range)
6582                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6583
6584                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6585                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6586                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6587
6588                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6589         } else {
6590                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6591
6592                 if (intel_crtc->config.limited_color_range)
6593                         mode |= CSC_BLACK_SCREEN_OFFSET;
6594
6595                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6596         }
6597 }
6598
6599 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6600 {
6601         struct drm_device *dev = crtc->dev;
6602         struct drm_i915_private *dev_priv = dev->dev_private;
6603         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6604         enum pipe pipe = intel_crtc->pipe;
6605         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6606         uint32_t val;
6607
6608         val = 0;
6609
6610         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6611                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6612
6613         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6614                 val |= PIPECONF_INTERLACED_ILK;
6615         else
6616                 val |= PIPECONF_PROGRESSIVE;
6617
6618         I915_WRITE(PIPECONF(cpu_transcoder), val);
6619         POSTING_READ(PIPECONF(cpu_transcoder));
6620
6621         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6622         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6623
6624         if (IS_BROADWELL(dev)) {
6625                 val = 0;
6626
6627                 switch (intel_crtc->config.pipe_bpp) {
6628                 case 18:
6629                         val |= PIPEMISC_DITHER_6_BPC;
6630                         break;
6631                 case 24:
6632                         val |= PIPEMISC_DITHER_8_BPC;
6633                         break;
6634                 case 30:
6635                         val |= PIPEMISC_DITHER_10_BPC;
6636                         break;
6637                 case 36:
6638                         val |= PIPEMISC_DITHER_12_BPC;
6639                         break;
6640                 default:
6641                         /* Case prevented by pipe_config_set_bpp. */
6642                         BUG();
6643                 }
6644
6645                 if (intel_crtc->config.dither)
6646                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6647
6648                 I915_WRITE(PIPEMISC(pipe), val);
6649         }
6650 }
6651
6652 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6653                                     intel_clock_t *clock,
6654                                     bool *has_reduced_clock,
6655                                     intel_clock_t *reduced_clock)
6656 {
6657         struct drm_device *dev = crtc->dev;
6658         struct drm_i915_private *dev_priv = dev->dev_private;
6659         struct intel_encoder *intel_encoder;
6660         int refclk;
6661         const intel_limit_t *limit;
6662         bool ret, is_lvds = false;
6663
6664         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6665                 switch (intel_encoder->type) {
6666                 case INTEL_OUTPUT_LVDS:
6667                         is_lvds = true;
6668                         break;
6669                 }
6670         }
6671
6672         refclk = ironlake_get_refclk(crtc);
6673
6674         /*
6675          * Returns a set of divisors for the desired target clock with the given
6676          * refclk, or FALSE.  The returned values represent the clock equation:
6677          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6678          */
6679         limit = intel_limit(crtc, refclk);
6680         ret = dev_priv->display.find_dpll(limit, crtc,
6681                                           to_intel_crtc(crtc)->config.port_clock,
6682                                           refclk, NULL, clock);
6683         if (!ret)
6684                 return false;
6685
6686         if (is_lvds && dev_priv->lvds_downclock_avail) {
6687                 /*
6688                  * Ensure we match the reduced clock's P to the target clock.
6689                  * If the clocks don't match, we can't switch the display clock
6690                  * by using the FP0/FP1. In such case we will disable the LVDS
6691                  * downclock feature.
6692                 */
6693                 *has_reduced_clock =
6694                         dev_priv->display.find_dpll(limit, crtc,
6695                                                     dev_priv->lvds_downclock,
6696                                                     refclk, clock,
6697                                                     reduced_clock);
6698         }
6699
6700         return true;
6701 }
6702
6703 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6704 {
6705         /*
6706          * Account for spread spectrum to avoid
6707          * oversubscribing the link. Max center spread
6708          * is 2.5%; use 5% for safety's sake.
6709          */
6710         u32 bps = target_clock * bpp * 21 / 20;
6711         return DIV_ROUND_UP(bps, link_bw * 8);
6712 }
6713
6714 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6715 {
6716         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6717 }
6718
6719 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6720                                       u32 *fp,
6721                                       intel_clock_t *reduced_clock, u32 *fp2)
6722 {
6723         struct drm_crtc *crtc = &intel_crtc->base;
6724         struct drm_device *dev = crtc->dev;
6725         struct drm_i915_private *dev_priv = dev->dev_private;
6726         struct intel_encoder *intel_encoder;
6727         uint32_t dpll;
6728         int factor, num_connectors = 0;
6729         bool is_lvds = false, is_sdvo = false;
6730
6731         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6732                 switch (intel_encoder->type) {
6733                 case INTEL_OUTPUT_LVDS:
6734                         is_lvds = true;
6735                         break;
6736                 case INTEL_OUTPUT_SDVO:
6737                 case INTEL_OUTPUT_HDMI:
6738                         is_sdvo = true;
6739                         break;
6740                 }
6741
6742                 num_connectors++;
6743         }
6744
6745         /* Enable autotuning of the PLL clock (if permissible) */
6746         factor = 21;
6747         if (is_lvds) {
6748                 if ((intel_panel_use_ssc(dev_priv) &&
6749                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6750                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6751                         factor = 25;
6752         } else if (intel_crtc->config.sdvo_tv_clock)
6753                 factor = 20;
6754
6755         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6756                 *fp |= FP_CB_TUNE;
6757
6758         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6759                 *fp2 |= FP_CB_TUNE;
6760
6761         dpll = 0;
6762
6763         if (is_lvds)
6764                 dpll |= DPLLB_MODE_LVDS;
6765         else
6766                 dpll |= DPLLB_MODE_DAC_SERIAL;
6767
6768         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6769                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6770
6771         if (is_sdvo)
6772                 dpll |= DPLL_SDVO_HIGH_SPEED;
6773         if (intel_crtc->config.has_dp_encoder)
6774                 dpll |= DPLL_SDVO_HIGH_SPEED;
6775
6776         /* compute bitmask from p1 value */
6777         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6778         /* also FPA1 */
6779         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6780
6781         switch (intel_crtc->config.dpll.p2) {
6782         case 5:
6783                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6784                 break;
6785         case 7:
6786                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6787                 break;
6788         case 10:
6789                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6790                 break;
6791         case 14:
6792                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6793                 break;
6794         }
6795
6796         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6797                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6798         else
6799                 dpll |= PLL_REF_INPUT_DREFCLK;
6800
6801         return dpll | DPLL_VCO_ENABLE;
6802 }
6803
6804 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6805                                   int x, int y,
6806                                   struct drm_framebuffer *fb)
6807 {
6808         struct drm_device *dev = crtc->dev;
6809         struct drm_i915_private *dev_priv = dev->dev_private;
6810         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811         int pipe = intel_crtc->pipe;
6812         int plane = intel_crtc->plane;
6813         int num_connectors = 0;
6814         intel_clock_t clock, reduced_clock;
6815         u32 dpll = 0, fp = 0, fp2 = 0;
6816         bool ok, has_reduced_clock = false;
6817         bool is_lvds = false;
6818         struct intel_encoder *encoder;
6819         struct intel_shared_dpll *pll;
6820         int ret;
6821
6822         for_each_encoder_on_crtc(dev, crtc, encoder) {
6823                 switch (encoder->type) {
6824                 case INTEL_OUTPUT_LVDS:
6825                         is_lvds = true;
6826                         break;
6827                 }
6828
6829                 num_connectors++;
6830         }
6831
6832         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6833              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6834
6835         ok = ironlake_compute_clocks(crtc, &clock,
6836                                      &has_reduced_clock, &reduced_clock);
6837         if (!ok && !intel_crtc->config.clock_set) {
6838                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6839                 return -EINVAL;
6840         }
6841         /* Compat-code for transition, will disappear. */
6842         if (!intel_crtc->config.clock_set) {
6843                 intel_crtc->config.dpll.n = clock.n;
6844                 intel_crtc->config.dpll.m1 = clock.m1;
6845                 intel_crtc->config.dpll.m2 = clock.m2;
6846                 intel_crtc->config.dpll.p1 = clock.p1;
6847                 intel_crtc->config.dpll.p2 = clock.p2;
6848         }
6849
6850         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6851         if (intel_crtc->config.has_pch_encoder) {
6852                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6853                 if (has_reduced_clock)
6854                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6855
6856                 dpll = ironlake_compute_dpll(intel_crtc,
6857                                              &fp, &reduced_clock,
6858                                              has_reduced_clock ? &fp2 : NULL);
6859
6860                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6861                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6862                 if (has_reduced_clock)
6863                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6864                 else
6865                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6866
6867                 pll = intel_get_shared_dpll(intel_crtc);
6868                 if (pll == NULL) {
6869                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6870                                          pipe_name(pipe));
6871                         return -EINVAL;
6872                 }
6873         } else
6874                 intel_put_shared_dpll(intel_crtc);
6875
6876         if (intel_crtc->config.has_dp_encoder)
6877                 intel_dp_set_m_n(intel_crtc);
6878
6879         if (is_lvds && has_reduced_clock && i915.powersave)
6880                 intel_crtc->lowfreq_avail = true;
6881         else
6882                 intel_crtc->lowfreq_avail = false;
6883
6884         intel_set_pipe_timings(intel_crtc);
6885
6886         if (intel_crtc->config.has_pch_encoder) {
6887                 intel_cpu_transcoder_set_m_n(intel_crtc,
6888                                              &intel_crtc->config.fdi_m_n);
6889         }
6890
6891         ironlake_set_pipeconf(crtc);
6892
6893         /* Set up the display plane register */
6894         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6895         POSTING_READ(DSPCNTR(plane));
6896
6897         ret = intel_pipe_set_base(crtc, x, y, fb);
6898
6899         return ret;
6900 }
6901
6902 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6903                                          struct intel_link_m_n *m_n)
6904 {
6905         struct drm_device *dev = crtc->base.dev;
6906         struct drm_i915_private *dev_priv = dev->dev_private;
6907         enum pipe pipe = crtc->pipe;
6908
6909         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6910         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6911         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6912                 & ~TU_SIZE_MASK;
6913         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6914         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6915                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6916 }
6917
6918 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6919                                          enum transcoder transcoder,
6920                                          struct intel_link_m_n *m_n)
6921 {
6922         struct drm_device *dev = crtc->base.dev;
6923         struct drm_i915_private *dev_priv = dev->dev_private;
6924         enum pipe pipe = crtc->pipe;
6925
6926         if (INTEL_INFO(dev)->gen >= 5) {
6927                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6928                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6929                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6930                         & ~TU_SIZE_MASK;
6931                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6932                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6933                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6934         } else {
6935                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6936                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6937                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6938                         & ~TU_SIZE_MASK;
6939                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6940                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6941                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6942         }
6943 }
6944
6945 void intel_dp_get_m_n(struct intel_crtc *crtc,
6946                       struct intel_crtc_config *pipe_config)
6947 {
6948         if (crtc->config.has_pch_encoder)
6949                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6950         else
6951                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6952                                              &pipe_config->dp_m_n);
6953 }
6954
6955 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6956                                         struct intel_crtc_config *pipe_config)
6957 {
6958         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6959                                      &pipe_config->fdi_m_n);
6960 }
6961
6962 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6963                                      struct intel_crtc_config *pipe_config)
6964 {
6965         struct drm_device *dev = crtc->base.dev;
6966         struct drm_i915_private *dev_priv = dev->dev_private;
6967         uint32_t tmp;
6968
6969         tmp = I915_READ(PF_CTL(crtc->pipe));
6970
6971         if (tmp & PF_ENABLE) {
6972                 pipe_config->pch_pfit.enabled = true;
6973                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6974                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6975
6976                 /* We currently do not free assignements of panel fitters on
6977                  * ivb/hsw (since we don't use the higher upscaling modes which
6978                  * differentiates them) so just WARN about this case for now. */
6979                 if (IS_GEN7(dev)) {
6980                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6981                                 PF_PIPE_SEL_IVB(crtc->pipe));
6982                 }
6983         }
6984 }
6985
6986 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6987                                       struct intel_plane_config *plane_config)
6988 {
6989         struct drm_device *dev = crtc->base.dev;
6990         struct drm_i915_private *dev_priv = dev->dev_private;
6991         u32 val, base, offset;
6992         int pipe = crtc->pipe, plane = crtc->plane;
6993         int fourcc, pixel_format;
6994         int aligned_height;
6995
6996         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6997         if (!crtc->base.primary->fb) {
6998                 DRM_DEBUG_KMS("failed to alloc fb\n");
6999                 return;
7000         }
7001
7002         val = I915_READ(DSPCNTR(plane));
7003
7004         if (INTEL_INFO(dev)->gen >= 4)
7005                 if (val & DISPPLANE_TILED)
7006                         plane_config->tiled = true;
7007
7008         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7009         fourcc = intel_format_to_fourcc(pixel_format);
7010         crtc->base.primary->fb->pixel_format = fourcc;
7011         crtc->base.primary->fb->bits_per_pixel =
7012                 drm_format_plane_cpp(fourcc, 0) * 8;
7013
7014         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7015         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7016                 offset = I915_READ(DSPOFFSET(plane));
7017         } else {
7018                 if (plane_config->tiled)
7019                         offset = I915_READ(DSPTILEOFF(plane));
7020                 else
7021                         offset = I915_READ(DSPLINOFF(plane));
7022         }
7023         plane_config->base = base;
7024
7025         val = I915_READ(PIPESRC(pipe));
7026         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7027         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7028
7029         val = I915_READ(DSPSTRIDE(pipe));
7030         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7031
7032         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7033                                             plane_config->tiled);
7034
7035         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7036                                    aligned_height, PAGE_SIZE);
7037
7038         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7039                       pipe, plane, crtc->base.primary->fb->width,
7040                       crtc->base.primary->fb->height,
7041                       crtc->base.primary->fb->bits_per_pixel, base,
7042                       crtc->base.primary->fb->pitches[0],
7043                       plane_config->size);
7044 }
7045
7046 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7047                                      struct intel_crtc_config *pipe_config)
7048 {
7049         struct drm_device *dev = crtc->base.dev;
7050         struct drm_i915_private *dev_priv = dev->dev_private;
7051         uint32_t tmp;
7052
7053         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7054         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7055
7056         tmp = I915_READ(PIPECONF(crtc->pipe));
7057         if (!(tmp & PIPECONF_ENABLE))
7058                 return false;
7059
7060         switch (tmp & PIPECONF_BPC_MASK) {
7061         case PIPECONF_6BPC:
7062                 pipe_config->pipe_bpp = 18;
7063                 break;
7064         case PIPECONF_8BPC:
7065                 pipe_config->pipe_bpp = 24;
7066                 break;
7067         case PIPECONF_10BPC:
7068                 pipe_config->pipe_bpp = 30;
7069                 break;
7070         case PIPECONF_12BPC:
7071                 pipe_config->pipe_bpp = 36;
7072                 break;
7073         default:
7074                 break;
7075         }
7076
7077         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7078                 struct intel_shared_dpll *pll;
7079
7080                 pipe_config->has_pch_encoder = true;
7081
7082                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7083                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7084                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7085
7086                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7087
7088                 if (HAS_PCH_IBX(dev_priv->dev)) {
7089                         pipe_config->shared_dpll =
7090                                 (enum intel_dpll_id) crtc->pipe;
7091                 } else {
7092                         tmp = I915_READ(PCH_DPLL_SEL);
7093                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7094                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7095                         else
7096                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7097                 }
7098
7099                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7100
7101                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7102                                            &pipe_config->dpll_hw_state));
7103
7104                 tmp = pipe_config->dpll_hw_state.dpll;
7105                 pipe_config->pixel_multiplier =
7106                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7107                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7108
7109                 ironlake_pch_clock_get(crtc, pipe_config);
7110         } else {
7111                 pipe_config->pixel_multiplier = 1;
7112         }
7113
7114         intel_get_pipe_timings(crtc, pipe_config);
7115
7116         ironlake_get_pfit_config(crtc, pipe_config);
7117
7118         return true;
7119 }
7120
7121 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7122 {
7123         struct drm_device *dev = dev_priv->dev;
7124         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7125         struct intel_crtc *crtc;
7126
7127         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
7128                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7129                      pipe_name(crtc->pipe));
7130
7131         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7132         WARN(plls->spll_refcount, "SPLL enabled\n");
7133         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7134         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7135         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7136         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7137              "CPU PWM1 enabled\n");
7138         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7139              "CPU PWM2 enabled\n");
7140         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7141              "PCH PWM1 enabled\n");
7142         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7143              "Utility pin enabled\n");
7144         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7145
7146         /*
7147          * In theory we can still leave IRQs enabled, as long as only the HPD
7148          * interrupts remain enabled. We used to check for that, but since it's
7149          * gen-specific and since we only disable LCPLL after we fully disable
7150          * the interrupts, the check below should be enough.
7151          */
7152         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7153 }
7154
7155 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7156 {
7157         struct drm_device *dev = dev_priv->dev;
7158
7159         if (IS_HASWELL(dev)) {
7160                 mutex_lock(&dev_priv->rps.hw_lock);
7161                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7162                                             val))
7163                         DRM_ERROR("Failed to disable D_COMP\n");
7164                 mutex_unlock(&dev_priv->rps.hw_lock);
7165         } else {
7166                 I915_WRITE(D_COMP, val);
7167         }
7168         POSTING_READ(D_COMP);
7169 }
7170
7171 /*
7172  * This function implements pieces of two sequences from BSpec:
7173  * - Sequence for display software to disable LCPLL
7174  * - Sequence for display software to allow package C8+
7175  * The steps implemented here are just the steps that actually touch the LCPLL
7176  * register. Callers should take care of disabling all the display engine
7177  * functions, doing the mode unset, fixing interrupts, etc.
7178  */
7179 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7180                               bool switch_to_fclk, bool allow_power_down)
7181 {
7182         uint32_t val;
7183
7184         assert_can_disable_lcpll(dev_priv);
7185
7186         val = I915_READ(LCPLL_CTL);
7187
7188         if (switch_to_fclk) {
7189                 val |= LCPLL_CD_SOURCE_FCLK;
7190                 I915_WRITE(LCPLL_CTL, val);
7191
7192                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7193                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7194                         DRM_ERROR("Switching to FCLK failed\n");
7195
7196                 val = I915_READ(LCPLL_CTL);
7197         }
7198
7199         val |= LCPLL_PLL_DISABLE;
7200         I915_WRITE(LCPLL_CTL, val);
7201         POSTING_READ(LCPLL_CTL);
7202
7203         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7204                 DRM_ERROR("LCPLL still locked\n");
7205
7206         val = I915_READ(D_COMP);
7207         val |= D_COMP_COMP_DISABLE;
7208         hsw_write_dcomp(dev_priv, val);
7209         ndelay(100);
7210
7211         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7212                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7213
7214         if (allow_power_down) {
7215                 val = I915_READ(LCPLL_CTL);
7216                 val |= LCPLL_POWER_DOWN_ALLOW;
7217                 I915_WRITE(LCPLL_CTL, val);
7218                 POSTING_READ(LCPLL_CTL);
7219         }
7220 }
7221
7222 /*
7223  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7224  * source.
7225  */
7226 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7227 {
7228         uint32_t val;
7229         unsigned long irqflags;
7230
7231         val = I915_READ(LCPLL_CTL);
7232
7233         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7234                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7235                 return;
7236
7237         /*
7238          * Make sure we're not on PC8 state before disabling PC8, otherwise
7239          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7240          *
7241          * The other problem is that hsw_restore_lcpll() is called as part of
7242          * the runtime PM resume sequence, so we can't just call
7243          * gen6_gt_force_wake_get() because that function calls
7244          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7245          * while we are on the resume sequence. So to solve this problem we have
7246          * to call special forcewake code that doesn't touch runtime PM and
7247          * doesn't enable the forcewake delayed work.
7248          */
7249         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7250         if (dev_priv->uncore.forcewake_count++ == 0)
7251                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7252         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7253
7254         if (val & LCPLL_POWER_DOWN_ALLOW) {
7255                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7256                 I915_WRITE(LCPLL_CTL, val);
7257                 POSTING_READ(LCPLL_CTL);
7258         }
7259
7260         val = I915_READ(D_COMP);
7261         val |= D_COMP_COMP_FORCE;
7262         val &= ~D_COMP_COMP_DISABLE;
7263         hsw_write_dcomp(dev_priv, val);
7264
7265         val = I915_READ(LCPLL_CTL);
7266         val &= ~LCPLL_PLL_DISABLE;
7267         I915_WRITE(LCPLL_CTL, val);
7268
7269         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7270                 DRM_ERROR("LCPLL not locked yet\n");
7271
7272         if (val & LCPLL_CD_SOURCE_FCLK) {
7273                 val = I915_READ(LCPLL_CTL);
7274                 val &= ~LCPLL_CD_SOURCE_FCLK;
7275                 I915_WRITE(LCPLL_CTL, val);
7276
7277                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7278                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7279                         DRM_ERROR("Switching back to LCPLL failed\n");
7280         }
7281
7282         /* See the big comment above. */
7283         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7284         if (--dev_priv->uncore.forcewake_count == 0)
7285                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7286         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7287 }
7288
7289 /*
7290  * Package states C8 and deeper are really deep PC states that can only be
7291  * reached when all the devices on the system allow it, so even if the graphics
7292  * device allows PC8+, it doesn't mean the system will actually get to these
7293  * states. Our driver only allows PC8+ when going into runtime PM.
7294  *
7295  * The requirements for PC8+ are that all the outputs are disabled, the power
7296  * well is disabled and most interrupts are disabled, and these are also
7297  * requirements for runtime PM. When these conditions are met, we manually do
7298  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7299  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7300  * hang the machine.
7301  *
7302  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7303  * the state of some registers, so when we come back from PC8+ we need to
7304  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7305  * need to take care of the registers kept by RC6. Notice that this happens even
7306  * if we don't put the device in PCI D3 state (which is what currently happens
7307  * because of the runtime PM support).
7308  *
7309  * For more, read "Display Sequences for Package C8" on the hardware
7310  * documentation.
7311  */
7312 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7313 {
7314         struct drm_device *dev = dev_priv->dev;
7315         uint32_t val;
7316
7317         DRM_DEBUG_KMS("Enabling package C8+\n");
7318
7319         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7320                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7321                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7322                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7323         }
7324
7325         lpt_disable_clkout_dp(dev);
7326         hsw_disable_lcpll(dev_priv, true, true);
7327 }
7328
7329 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7330 {
7331         struct drm_device *dev = dev_priv->dev;
7332         uint32_t val;
7333
7334         DRM_DEBUG_KMS("Disabling package C8+\n");
7335
7336         hsw_restore_lcpll(dev_priv);
7337         lpt_init_pch_refclk(dev);
7338
7339         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7340                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7341                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7342                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7343         }
7344
7345         intel_prepare_ddi(dev);
7346 }
7347
7348 static void snb_modeset_global_resources(struct drm_device *dev)
7349 {
7350         modeset_update_crtc_power_domains(dev);
7351 }
7352
7353 static void haswell_modeset_global_resources(struct drm_device *dev)
7354 {
7355         modeset_update_crtc_power_domains(dev);
7356 }
7357
7358 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7359                                  int x, int y,
7360                                  struct drm_framebuffer *fb)
7361 {
7362         struct drm_device *dev = crtc->dev;
7363         struct drm_i915_private *dev_priv = dev->dev_private;
7364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7365         int plane = intel_crtc->plane;
7366         int ret;
7367
7368         if (!intel_ddi_pll_select(intel_crtc))
7369                 return -EINVAL;
7370         intel_ddi_pll_enable(intel_crtc);
7371
7372         if (intel_crtc->config.has_dp_encoder)
7373                 intel_dp_set_m_n(intel_crtc);
7374
7375         intel_crtc->lowfreq_avail = false;
7376
7377         intel_set_pipe_timings(intel_crtc);
7378
7379         if (intel_crtc->config.has_pch_encoder) {
7380                 intel_cpu_transcoder_set_m_n(intel_crtc,
7381                                              &intel_crtc->config.fdi_m_n);
7382         }
7383
7384         haswell_set_pipeconf(crtc);
7385
7386         intel_set_pipe_csc(crtc);
7387
7388         /* Set up the display plane register */
7389         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7390         POSTING_READ(DSPCNTR(plane));
7391
7392         ret = intel_pipe_set_base(crtc, x, y, fb);
7393
7394         return ret;
7395 }
7396
7397 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7398                                     struct intel_crtc_config *pipe_config)
7399 {
7400         struct drm_device *dev = crtc->base.dev;
7401         struct drm_i915_private *dev_priv = dev->dev_private;
7402         enum intel_display_power_domain pfit_domain;
7403         uint32_t tmp;
7404
7405         if (!intel_display_power_enabled(dev_priv,
7406                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7407                 return false;
7408
7409         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7410         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7411
7412         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7413         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7414                 enum pipe trans_edp_pipe;
7415                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7416                 default:
7417                         WARN(1, "unknown pipe linked to edp transcoder\n");
7418                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7419                 case TRANS_DDI_EDP_INPUT_A_ON:
7420                         trans_edp_pipe = PIPE_A;
7421                         break;
7422                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7423                         trans_edp_pipe = PIPE_B;
7424                         break;
7425                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7426                         trans_edp_pipe = PIPE_C;
7427                         break;
7428                 }
7429
7430                 if (trans_edp_pipe == crtc->pipe)
7431                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7432         }
7433
7434         if (!intel_display_power_enabled(dev_priv,
7435                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7436                 return false;
7437
7438         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7439         if (!(tmp & PIPECONF_ENABLE))
7440                 return false;
7441
7442         /*
7443          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7444          * DDI E. So just check whether this pipe is wired to DDI E and whether
7445          * the PCH transcoder is on.
7446          */
7447         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7448         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7449             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7450                 pipe_config->has_pch_encoder = true;
7451
7452                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7453                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7454                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7455
7456                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7457         }
7458
7459         intel_get_pipe_timings(crtc, pipe_config);
7460
7461         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7462         if (intel_display_power_enabled(dev_priv, pfit_domain))
7463                 ironlake_get_pfit_config(crtc, pipe_config);
7464
7465         if (IS_HASWELL(dev))
7466                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7467                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7468
7469         pipe_config->pixel_multiplier = 1;
7470
7471         return true;
7472 }
7473
7474 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7475                                int x, int y,
7476                                struct drm_framebuffer *fb)
7477 {
7478         struct drm_device *dev = crtc->dev;
7479         struct drm_i915_private *dev_priv = dev->dev_private;
7480         struct intel_encoder *encoder;
7481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7482         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7483         int pipe = intel_crtc->pipe;
7484         int ret;
7485
7486         drm_vblank_pre_modeset(dev, pipe);
7487
7488         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7489
7490         drm_vblank_post_modeset(dev, pipe);
7491
7492         if (ret != 0)
7493                 return ret;
7494
7495         for_each_encoder_on_crtc(dev, crtc, encoder) {
7496                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7497                         encoder->base.base.id,
7498                         drm_get_encoder_name(&encoder->base),
7499                         mode->base.id, mode->name);
7500
7501                 if (encoder->mode_set)
7502                         encoder->mode_set(encoder);
7503         }
7504
7505         return 0;
7506 }
7507
7508 static struct {
7509         int clock;
7510         u32 config;
7511 } hdmi_audio_clock[] = {
7512         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7513         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7514         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7515         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7516         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7517         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7518         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7519         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7520         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7521         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7522 };
7523
7524 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7525 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7526 {
7527         int i;
7528
7529         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7530                 if (mode->clock == hdmi_audio_clock[i].clock)
7531                         break;
7532         }
7533
7534         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7535                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7536                 i = 1;
7537         }
7538
7539         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7540                       hdmi_audio_clock[i].clock,
7541                       hdmi_audio_clock[i].config);
7542
7543         return hdmi_audio_clock[i].config;
7544 }
7545
7546 static bool intel_eld_uptodate(struct drm_connector *connector,
7547                                int reg_eldv, uint32_t bits_eldv,
7548                                int reg_elda, uint32_t bits_elda,
7549                                int reg_edid)
7550 {
7551         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7552         uint8_t *eld = connector->eld;
7553         uint32_t i;
7554
7555         i = I915_READ(reg_eldv);
7556         i &= bits_eldv;
7557
7558         if (!eld[0])
7559                 return !i;
7560
7561         if (!i)
7562                 return false;
7563
7564         i = I915_READ(reg_elda);
7565         i &= ~bits_elda;
7566         I915_WRITE(reg_elda, i);
7567
7568         for (i = 0; i < eld[2]; i++)
7569                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7570                         return false;
7571
7572         return true;
7573 }
7574
7575 static void g4x_write_eld(struct drm_connector *connector,
7576                           struct drm_crtc *crtc,
7577                           struct drm_display_mode *mode)
7578 {
7579         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7580         uint8_t *eld = connector->eld;
7581         uint32_t eldv;
7582         uint32_t len;
7583         uint32_t i;
7584
7585         i = I915_READ(G4X_AUD_VID_DID);
7586
7587         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7588                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7589         else
7590                 eldv = G4X_ELDV_DEVCTG;
7591
7592         if (intel_eld_uptodate(connector,
7593                                G4X_AUD_CNTL_ST, eldv,
7594                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7595                                G4X_HDMIW_HDMIEDID))
7596                 return;
7597
7598         i = I915_READ(G4X_AUD_CNTL_ST);
7599         i &= ~(eldv | G4X_ELD_ADDR);
7600         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7601         I915_WRITE(G4X_AUD_CNTL_ST, i);
7602
7603         if (!eld[0])
7604                 return;
7605
7606         len = min_t(uint8_t, eld[2], len);
7607         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7608         for (i = 0; i < len; i++)
7609                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7610
7611         i = I915_READ(G4X_AUD_CNTL_ST);
7612         i |= eldv;
7613         I915_WRITE(G4X_AUD_CNTL_ST, i);
7614 }
7615
7616 static void haswell_write_eld(struct drm_connector *connector,
7617                               struct drm_crtc *crtc,
7618                               struct drm_display_mode *mode)
7619 {
7620         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7621         uint8_t *eld = connector->eld;
7622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7623         uint32_t eldv;
7624         uint32_t i;
7625         int len;
7626         int pipe = to_intel_crtc(crtc)->pipe;
7627         int tmp;
7628
7629         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7630         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7631         int aud_config = HSW_AUD_CFG(pipe);
7632         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7633
7634         /* Audio output enable */
7635         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7636         tmp = I915_READ(aud_cntrl_st2);
7637         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7638         I915_WRITE(aud_cntrl_st2, tmp);
7639         POSTING_READ(aud_cntrl_st2);
7640
7641         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7642
7643         /* Set ELD valid state */
7644         tmp = I915_READ(aud_cntrl_st2);
7645         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7646         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7647         I915_WRITE(aud_cntrl_st2, tmp);
7648         tmp = I915_READ(aud_cntrl_st2);
7649         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7650
7651         /* Enable HDMI mode */
7652         tmp = I915_READ(aud_config);
7653         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7654         /* clear N_programing_enable and N_value_index */
7655         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7656         I915_WRITE(aud_config, tmp);
7657
7658         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7659
7660         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7661         intel_crtc->eld_vld = true;
7662
7663         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7664                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7665                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7666                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7667         } else {
7668                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7669         }
7670
7671         if (intel_eld_uptodate(connector,
7672                                aud_cntrl_st2, eldv,
7673                                aud_cntl_st, IBX_ELD_ADDRESS,
7674                                hdmiw_hdmiedid))
7675                 return;
7676
7677         i = I915_READ(aud_cntrl_st2);
7678         i &= ~eldv;
7679         I915_WRITE(aud_cntrl_st2, i);
7680
7681         if (!eld[0])
7682                 return;
7683
7684         i = I915_READ(aud_cntl_st);
7685         i &= ~IBX_ELD_ADDRESS;
7686         I915_WRITE(aud_cntl_st, i);
7687         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7688         DRM_DEBUG_DRIVER("port num:%d\n", i);
7689
7690         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7691         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7692         for (i = 0; i < len; i++)
7693                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7694
7695         i = I915_READ(aud_cntrl_st2);
7696         i |= eldv;
7697         I915_WRITE(aud_cntrl_st2, i);
7698
7699 }
7700
7701 static void ironlake_write_eld(struct drm_connector *connector,
7702                                struct drm_crtc *crtc,
7703                                struct drm_display_mode *mode)
7704 {
7705         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7706         uint8_t *eld = connector->eld;
7707         uint32_t eldv;
7708         uint32_t i;
7709         int len;
7710         int hdmiw_hdmiedid;
7711         int aud_config;
7712         int aud_cntl_st;
7713         int aud_cntrl_st2;
7714         int pipe = to_intel_crtc(crtc)->pipe;
7715
7716         if (HAS_PCH_IBX(connector->dev)) {
7717                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7718                 aud_config = IBX_AUD_CFG(pipe);
7719                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7720                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7721         } else if (IS_VALLEYVIEW(connector->dev)) {
7722                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7723                 aud_config = VLV_AUD_CFG(pipe);
7724                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7725                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7726         } else {
7727                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7728                 aud_config = CPT_AUD_CFG(pipe);
7729                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7730                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7731         }
7732
7733         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7734
7735         if (IS_VALLEYVIEW(connector->dev))  {
7736                 struct intel_encoder *intel_encoder;
7737                 struct intel_digital_port *intel_dig_port;
7738
7739                 intel_encoder = intel_attached_encoder(connector);
7740                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7741                 i = intel_dig_port->port;
7742         } else {
7743                 i = I915_READ(aud_cntl_st);
7744                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7745                 /* DIP_Port_Select, 0x1 = PortB */
7746         }
7747
7748         if (!i) {
7749                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7750                 /* operate blindly on all ports */
7751                 eldv = IBX_ELD_VALIDB;
7752                 eldv |= IBX_ELD_VALIDB << 4;
7753                 eldv |= IBX_ELD_VALIDB << 8;
7754         } else {
7755                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7756                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7757         }
7758
7759         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7760                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7761                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7762                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7763         } else {
7764                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7765         }
7766
7767         if (intel_eld_uptodate(connector,
7768                                aud_cntrl_st2, eldv,
7769                                aud_cntl_st, IBX_ELD_ADDRESS,
7770                                hdmiw_hdmiedid))
7771                 return;
7772
7773         i = I915_READ(aud_cntrl_st2);
7774         i &= ~eldv;
7775         I915_WRITE(aud_cntrl_st2, i);
7776
7777         if (!eld[0])
7778                 return;
7779
7780         i = I915_READ(aud_cntl_st);
7781         i &= ~IBX_ELD_ADDRESS;
7782         I915_WRITE(aud_cntl_st, i);
7783
7784         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7785         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7786         for (i = 0; i < len; i++)
7787                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7788
7789         i = I915_READ(aud_cntrl_st2);
7790         i |= eldv;
7791         I915_WRITE(aud_cntrl_st2, i);
7792 }
7793
7794 void intel_write_eld(struct drm_encoder *encoder,
7795                      struct drm_display_mode *mode)
7796 {
7797         struct drm_crtc *crtc = encoder->crtc;
7798         struct drm_connector *connector;
7799         struct drm_device *dev = encoder->dev;
7800         struct drm_i915_private *dev_priv = dev->dev_private;
7801
7802         connector = drm_select_eld(encoder, mode);
7803         if (!connector)
7804                 return;
7805
7806         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7807                          connector->base.id,
7808                          drm_get_connector_name(connector),
7809                          connector->encoder->base.id,
7810                          drm_get_encoder_name(connector->encoder));
7811
7812         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7813
7814         if (dev_priv->display.write_eld)
7815                 dev_priv->display.write_eld(connector, crtc, mode);
7816 }
7817
7818 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7819 {
7820         struct drm_device *dev = crtc->dev;
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7823         bool visible = base != 0;
7824         u32 cntl;
7825
7826         if (intel_crtc->cursor_visible == visible)
7827                 return;
7828
7829         cntl = I915_READ(_CURACNTR);
7830         if (visible) {
7831                 /* On these chipsets we can only modify the base whilst
7832                  * the cursor is disabled.
7833                  */
7834                 I915_WRITE(_CURABASE, base);
7835
7836                 cntl &= ~(CURSOR_FORMAT_MASK);
7837                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7838                 cntl |= CURSOR_ENABLE |
7839                         CURSOR_GAMMA_ENABLE |
7840                         CURSOR_FORMAT_ARGB;
7841         } else
7842                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7843         I915_WRITE(_CURACNTR, cntl);
7844
7845         intel_crtc->cursor_visible = visible;
7846 }
7847
7848 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7849 {
7850         struct drm_device *dev = crtc->dev;
7851         struct drm_i915_private *dev_priv = dev->dev_private;
7852         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7853         int pipe = intel_crtc->pipe;
7854         bool visible = base != 0;
7855
7856         if (intel_crtc->cursor_visible != visible) {
7857                 int16_t width = intel_crtc->cursor_width;
7858                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7859                 if (base) {
7860                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7861                         cntl |= MCURSOR_GAMMA_ENABLE;
7862
7863                         switch (width) {
7864                         case 64:
7865                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7866                                 break;
7867                         case 128:
7868                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7869                                 break;
7870                         case 256:
7871                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7872                                 break;
7873                         default:
7874                                 WARN_ON(1);
7875                                 return;
7876                         }
7877                         cntl |= pipe << 28; /* Connect to correct pipe */
7878                 } else {
7879                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7880                         cntl |= CURSOR_MODE_DISABLE;
7881                 }
7882                 I915_WRITE(CURCNTR(pipe), cntl);
7883
7884                 intel_crtc->cursor_visible = visible;
7885         }
7886         /* and commit changes on next vblank */
7887         POSTING_READ(CURCNTR(pipe));
7888         I915_WRITE(CURBASE(pipe), base);
7889         POSTING_READ(CURBASE(pipe));
7890 }
7891
7892 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7893 {
7894         struct drm_device *dev = crtc->dev;
7895         struct drm_i915_private *dev_priv = dev->dev_private;
7896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7897         int pipe = intel_crtc->pipe;
7898         bool visible = base != 0;
7899
7900         if (intel_crtc->cursor_visible != visible) {
7901                 int16_t width = intel_crtc->cursor_width;
7902                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7903                 if (base) {
7904                         cntl &= ~CURSOR_MODE;
7905                         cntl |= MCURSOR_GAMMA_ENABLE;
7906                         switch (width) {
7907                         case 64:
7908                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7909                                 break;
7910                         case 128:
7911                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7912                                 break;
7913                         case 256:
7914                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7915                                 break;
7916                         default:
7917                                 WARN_ON(1);
7918                                 return;
7919                         }
7920                 } else {
7921                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7922                         cntl |= CURSOR_MODE_DISABLE;
7923                 }
7924                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7925                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7926                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7927                 }
7928                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7929
7930                 intel_crtc->cursor_visible = visible;
7931         }
7932         /* and commit changes on next vblank */
7933         POSTING_READ(CURCNTR_IVB(pipe));
7934         I915_WRITE(CURBASE_IVB(pipe), base);
7935         POSTING_READ(CURBASE_IVB(pipe));
7936 }
7937
7938 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7939 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7940                                      bool on)
7941 {
7942         struct drm_device *dev = crtc->dev;
7943         struct drm_i915_private *dev_priv = dev->dev_private;
7944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945         int pipe = intel_crtc->pipe;
7946         int x = intel_crtc->cursor_x;
7947         int y = intel_crtc->cursor_y;
7948         u32 base = 0, pos = 0;
7949         bool visible;
7950
7951         if (on)
7952                 base = intel_crtc->cursor_addr;
7953
7954         if (x >= intel_crtc->config.pipe_src_w)
7955                 base = 0;
7956
7957         if (y >= intel_crtc->config.pipe_src_h)
7958                 base = 0;
7959
7960         if (x < 0) {
7961                 if (x + intel_crtc->cursor_width <= 0)
7962                         base = 0;
7963
7964                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7965                 x = -x;
7966         }
7967         pos |= x << CURSOR_X_SHIFT;
7968
7969         if (y < 0) {
7970                 if (y + intel_crtc->cursor_height <= 0)
7971                         base = 0;
7972
7973                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7974                 y = -y;
7975         }
7976         pos |= y << CURSOR_Y_SHIFT;
7977
7978         visible = base != 0;
7979         if (!visible && !intel_crtc->cursor_visible)
7980                 return;
7981
7982         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7983                 I915_WRITE(CURPOS_IVB(pipe), pos);
7984                 ivb_update_cursor(crtc, base);
7985         } else {
7986                 I915_WRITE(CURPOS(pipe), pos);
7987                 if (IS_845G(dev) || IS_I865G(dev))
7988                         i845_update_cursor(crtc, base);
7989                 else
7990                         i9xx_update_cursor(crtc, base);
7991         }
7992 }
7993
7994 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7995                                  struct drm_file *file,
7996                                  uint32_t handle,
7997                                  uint32_t width, uint32_t height)
7998 {
7999         struct drm_device *dev = crtc->dev;
8000         struct drm_i915_private *dev_priv = dev->dev_private;
8001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8002         struct drm_i915_gem_object *obj;
8003         unsigned old_width;
8004         uint32_t addr;
8005         int ret;
8006
8007         /* if we want to turn off the cursor ignore width and height */
8008         if (!handle) {
8009                 DRM_DEBUG_KMS("cursor off\n");
8010                 addr = 0;
8011                 obj = NULL;
8012                 mutex_lock(&dev->struct_mutex);
8013                 goto finish;
8014         }
8015
8016         /* Check for which cursor types we support */
8017         if (!((width == 64 && height == 64) ||
8018                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8019                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8020                 DRM_DEBUG("Cursor dimension not supported\n");
8021                 return -EINVAL;
8022         }
8023
8024         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8025         if (&obj->base == NULL)
8026                 return -ENOENT;
8027
8028         if (obj->base.size < width * height * 4) {
8029                 DRM_DEBUG_KMS("buffer is to small\n");
8030                 ret = -ENOMEM;
8031                 goto fail;
8032         }
8033
8034         /* we only need to pin inside GTT if cursor is non-phy */
8035         mutex_lock(&dev->struct_mutex);
8036         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8037                 unsigned alignment;
8038
8039                 if (obj->tiling_mode) {
8040                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8041                         ret = -EINVAL;
8042                         goto fail_locked;
8043                 }
8044
8045                 /* Note that the w/a also requires 2 PTE of padding following
8046                  * the bo. We currently fill all unused PTE with the shadow
8047                  * page and so we should always have valid PTE following the
8048                  * cursor preventing the VT-d warning.
8049                  */
8050                 alignment = 0;
8051                 if (need_vtd_wa(dev))
8052                         alignment = 64*1024;
8053
8054                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8055                 if (ret) {
8056                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8057                         goto fail_locked;
8058                 }
8059
8060                 ret = i915_gem_object_put_fence(obj);
8061                 if (ret) {
8062                         DRM_DEBUG_KMS("failed to release fence for cursor");
8063                         goto fail_unpin;
8064                 }
8065
8066                 addr = i915_gem_obj_ggtt_offset(obj);
8067         } else {
8068                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8069                 ret = i915_gem_attach_phys_object(dev, obj,
8070                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8071                                                   align);
8072                 if (ret) {
8073                         DRM_DEBUG_KMS("failed to attach phys object\n");
8074                         goto fail_locked;
8075                 }
8076                 addr = obj->phys_obj->handle->busaddr;
8077         }
8078
8079         if (IS_GEN2(dev))
8080                 I915_WRITE(CURSIZE, (height << 12) | width);
8081
8082  finish:
8083         if (intel_crtc->cursor_bo) {
8084                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8085                         if (intel_crtc->cursor_bo != obj)
8086                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8087                 } else
8088                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8089                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8090         }
8091
8092         mutex_unlock(&dev->struct_mutex);
8093
8094         old_width = intel_crtc->cursor_width;
8095
8096         intel_crtc->cursor_addr = addr;
8097         intel_crtc->cursor_bo = obj;
8098         intel_crtc->cursor_width = width;
8099         intel_crtc->cursor_height = height;
8100
8101         if (intel_crtc->active) {
8102                 if (old_width != width)
8103                         intel_update_watermarks(crtc);
8104                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8105         }
8106
8107         return 0;
8108 fail_unpin:
8109         i915_gem_object_unpin_from_display_plane(obj);
8110 fail_locked:
8111         mutex_unlock(&dev->struct_mutex);
8112 fail:
8113         drm_gem_object_unreference_unlocked(&obj->base);
8114         return ret;
8115 }
8116
8117 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8118 {
8119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8120
8121         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8122         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8123
8124         if (intel_crtc->active)
8125                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8126
8127         return 0;
8128 }
8129
8130 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8131                                  u16 *blue, uint32_t start, uint32_t size)
8132 {
8133         int end = (start + size > 256) ? 256 : start + size, i;
8134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8135
8136         for (i = start; i < end; i++) {
8137                 intel_crtc->lut_r[i] = red[i] >> 8;
8138                 intel_crtc->lut_g[i] = green[i] >> 8;
8139                 intel_crtc->lut_b[i] = blue[i] >> 8;
8140         }
8141
8142         intel_crtc_load_lut(crtc);
8143 }
8144
8145 /* VESA 640x480x72Hz mode to set on the pipe */
8146 static struct drm_display_mode load_detect_mode = {
8147         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8148                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8149 };
8150
8151 struct drm_framebuffer *
8152 __intel_framebuffer_create(struct drm_device *dev,
8153                            struct drm_mode_fb_cmd2 *mode_cmd,
8154                            struct drm_i915_gem_object *obj)
8155 {
8156         struct intel_framebuffer *intel_fb;
8157         int ret;
8158
8159         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8160         if (!intel_fb) {
8161                 drm_gem_object_unreference_unlocked(&obj->base);
8162                 return ERR_PTR(-ENOMEM);
8163         }
8164
8165         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8166         if (ret)
8167                 goto err;
8168
8169         return &intel_fb->base;
8170 err:
8171         drm_gem_object_unreference_unlocked(&obj->base);
8172         kfree(intel_fb);
8173
8174         return ERR_PTR(ret);
8175 }
8176
8177 static struct drm_framebuffer *
8178 intel_framebuffer_create(struct drm_device *dev,
8179                          struct drm_mode_fb_cmd2 *mode_cmd,
8180                          struct drm_i915_gem_object *obj)
8181 {
8182         struct drm_framebuffer *fb;
8183         int ret;
8184
8185         ret = i915_mutex_lock_interruptible(dev);
8186         if (ret)
8187                 return ERR_PTR(ret);
8188         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8189         mutex_unlock(&dev->struct_mutex);
8190
8191         return fb;
8192 }
8193
8194 static u32
8195 intel_framebuffer_pitch_for_width(int width, int bpp)
8196 {
8197         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8198         return ALIGN(pitch, 64);
8199 }
8200
8201 static u32
8202 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8203 {
8204         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8205         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8206 }
8207
8208 static struct drm_framebuffer *
8209 intel_framebuffer_create_for_mode(struct drm_device *dev,
8210                                   struct drm_display_mode *mode,
8211                                   int depth, int bpp)
8212 {
8213         struct drm_i915_gem_object *obj;
8214         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8215
8216         obj = i915_gem_alloc_object(dev,
8217                                     intel_framebuffer_size_for_mode(mode, bpp));
8218         if (obj == NULL)
8219                 return ERR_PTR(-ENOMEM);
8220
8221         mode_cmd.width = mode->hdisplay;
8222         mode_cmd.height = mode->vdisplay;
8223         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8224                                                                 bpp);
8225         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8226
8227         return intel_framebuffer_create(dev, &mode_cmd, obj);
8228 }
8229
8230 static struct drm_framebuffer *
8231 mode_fits_in_fbdev(struct drm_device *dev,
8232                    struct drm_display_mode *mode)
8233 {
8234 #ifdef CONFIG_DRM_I915_FBDEV
8235         struct drm_i915_private *dev_priv = dev->dev_private;
8236         struct drm_i915_gem_object *obj;
8237         struct drm_framebuffer *fb;
8238
8239         if (!dev_priv->fbdev)
8240                 return NULL;
8241
8242         if (!dev_priv->fbdev->fb)
8243                 return NULL;
8244
8245         obj = dev_priv->fbdev->fb->obj;
8246         BUG_ON(!obj);
8247
8248         fb = &dev_priv->fbdev->fb->base;
8249         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8250                                                                fb->bits_per_pixel))
8251                 return NULL;
8252
8253         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8254                 return NULL;
8255
8256         return fb;
8257 #else
8258         return NULL;
8259 #endif
8260 }
8261
8262 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8263                                 struct drm_display_mode *mode,
8264                                 struct intel_load_detect_pipe *old)
8265 {
8266         struct intel_crtc *intel_crtc;
8267         struct intel_encoder *intel_encoder =
8268                 intel_attached_encoder(connector);
8269         struct drm_crtc *possible_crtc;
8270         struct drm_encoder *encoder = &intel_encoder->base;
8271         struct drm_crtc *crtc = NULL;
8272         struct drm_device *dev = encoder->dev;
8273         struct drm_framebuffer *fb;
8274         int i = -1;
8275
8276         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8277                       connector->base.id, drm_get_connector_name(connector),
8278                       encoder->base.id, drm_get_encoder_name(encoder));
8279
8280         /*
8281          * Algorithm gets a little messy:
8282          *
8283          *   - if the connector already has an assigned crtc, use it (but make
8284          *     sure it's on first)
8285          *
8286          *   - try to find the first unused crtc that can drive this connector,
8287          *     and use that if we find one
8288          */
8289
8290         /* See if we already have a CRTC for this connector */
8291         if (encoder->crtc) {
8292                 crtc = encoder->crtc;
8293
8294                 mutex_lock(&crtc->mutex);
8295
8296                 old->dpms_mode = connector->dpms;
8297                 old->load_detect_temp = false;
8298
8299                 /* Make sure the crtc and connector are running */
8300                 if (connector->dpms != DRM_MODE_DPMS_ON)
8301                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8302
8303                 return true;
8304         }
8305
8306         /* Find an unused one (if possible) */
8307         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8308                 i++;
8309                 if (!(encoder->possible_crtcs & (1 << i)))
8310                         continue;
8311                 if (!possible_crtc->enabled) {
8312                         crtc = possible_crtc;
8313                         break;
8314                 }
8315         }
8316
8317         /*
8318          * If we didn't find an unused CRTC, don't use any.
8319          */
8320         if (!crtc) {
8321                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8322                 return false;
8323         }
8324
8325         mutex_lock(&crtc->mutex);
8326         intel_encoder->new_crtc = to_intel_crtc(crtc);
8327         to_intel_connector(connector)->new_encoder = intel_encoder;
8328
8329         intel_crtc = to_intel_crtc(crtc);
8330         intel_crtc->new_enabled = true;
8331         intel_crtc->new_config = &intel_crtc->config;
8332         old->dpms_mode = connector->dpms;
8333         old->load_detect_temp = true;
8334         old->release_fb = NULL;
8335
8336         if (!mode)
8337                 mode = &load_detect_mode;
8338
8339         /* We need a framebuffer large enough to accommodate all accesses
8340          * that the plane may generate whilst we perform load detection.
8341          * We can not rely on the fbcon either being present (we get called
8342          * during its initialisation to detect all boot displays, or it may
8343          * not even exist) or that it is large enough to satisfy the
8344          * requested mode.
8345          */
8346         fb = mode_fits_in_fbdev(dev, mode);
8347         if (fb == NULL) {
8348                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8349                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8350                 old->release_fb = fb;
8351         } else
8352                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8353         if (IS_ERR(fb)) {
8354                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8355                 goto fail;
8356         }
8357
8358         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8359                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8360                 if (old->release_fb)
8361                         old->release_fb->funcs->destroy(old->release_fb);
8362                 goto fail;
8363         }
8364
8365         /* let the connector get through one full cycle before testing */
8366         intel_wait_for_vblank(dev, intel_crtc->pipe);
8367         return true;
8368
8369  fail:
8370         intel_crtc->new_enabled = crtc->enabled;
8371         if (intel_crtc->new_enabled)
8372                 intel_crtc->new_config = &intel_crtc->config;
8373         else
8374                 intel_crtc->new_config = NULL;
8375         mutex_unlock(&crtc->mutex);
8376         return false;
8377 }
8378
8379 void intel_release_load_detect_pipe(struct drm_connector *connector,
8380                                     struct intel_load_detect_pipe *old)
8381 {
8382         struct intel_encoder *intel_encoder =
8383                 intel_attached_encoder(connector);
8384         struct drm_encoder *encoder = &intel_encoder->base;
8385         struct drm_crtc *crtc = encoder->crtc;
8386         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8387
8388         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8389                       connector->base.id, drm_get_connector_name(connector),
8390                       encoder->base.id, drm_get_encoder_name(encoder));
8391
8392         if (old->load_detect_temp) {
8393                 to_intel_connector(connector)->new_encoder = NULL;
8394                 intel_encoder->new_crtc = NULL;
8395                 intel_crtc->new_enabled = false;
8396                 intel_crtc->new_config = NULL;
8397                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8398
8399                 if (old->release_fb) {
8400                         drm_framebuffer_unregister_private(old->release_fb);
8401                         drm_framebuffer_unreference(old->release_fb);
8402                 }
8403
8404                 mutex_unlock(&crtc->mutex);
8405                 return;
8406         }
8407
8408         /* Switch crtc and encoder back off if necessary */
8409         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8410                 connector->funcs->dpms(connector, old->dpms_mode);
8411
8412         mutex_unlock(&crtc->mutex);
8413 }
8414
8415 static int i9xx_pll_refclk(struct drm_device *dev,
8416                            const struct intel_crtc_config *pipe_config)
8417 {
8418         struct drm_i915_private *dev_priv = dev->dev_private;
8419         u32 dpll = pipe_config->dpll_hw_state.dpll;
8420
8421         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8422                 return dev_priv->vbt.lvds_ssc_freq;
8423         else if (HAS_PCH_SPLIT(dev))
8424                 return 120000;
8425         else if (!IS_GEN2(dev))
8426                 return 96000;
8427         else
8428                 return 48000;
8429 }
8430
8431 /* Returns the clock of the currently programmed mode of the given pipe. */
8432 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8433                                 struct intel_crtc_config *pipe_config)
8434 {
8435         struct drm_device *dev = crtc->base.dev;
8436         struct drm_i915_private *dev_priv = dev->dev_private;
8437         int pipe = pipe_config->cpu_transcoder;
8438         u32 dpll = pipe_config->dpll_hw_state.dpll;
8439         u32 fp;
8440         intel_clock_t clock;
8441         int refclk = i9xx_pll_refclk(dev, pipe_config);
8442
8443         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8444                 fp = pipe_config->dpll_hw_state.fp0;
8445         else
8446                 fp = pipe_config->dpll_hw_state.fp1;
8447
8448         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8449         if (IS_PINEVIEW(dev)) {
8450                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8451                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8452         } else {
8453                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8454                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8455         }
8456
8457         if (!IS_GEN2(dev)) {
8458                 if (IS_PINEVIEW(dev))
8459                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8460                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8461                 else
8462                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8463                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8464
8465                 switch (dpll & DPLL_MODE_MASK) {
8466                 case DPLLB_MODE_DAC_SERIAL:
8467                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8468                                 5 : 10;
8469                         break;
8470                 case DPLLB_MODE_LVDS:
8471                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8472                                 7 : 14;
8473                         break;
8474                 default:
8475                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8476                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8477                         return;
8478                 }
8479
8480                 if (IS_PINEVIEW(dev))
8481                         pineview_clock(refclk, &clock);
8482                 else
8483                         i9xx_clock(refclk, &clock);
8484         } else {
8485                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8486                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8487
8488                 if (is_lvds) {
8489                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8490                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8491
8492                         if (lvds & LVDS_CLKB_POWER_UP)
8493                                 clock.p2 = 7;
8494                         else
8495                                 clock.p2 = 14;
8496                 } else {
8497                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8498                                 clock.p1 = 2;
8499                         else {
8500                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8501                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8502                         }
8503                         if (dpll & PLL_P2_DIVIDE_BY_4)
8504                                 clock.p2 = 4;
8505                         else
8506                                 clock.p2 = 2;
8507                 }
8508
8509                 i9xx_clock(refclk, &clock);
8510         }
8511
8512         /*
8513          * This value includes pixel_multiplier. We will use
8514          * port_clock to compute adjusted_mode.crtc_clock in the
8515          * encoder's get_config() function.
8516          */
8517         pipe_config->port_clock = clock.dot;
8518 }
8519
8520 int intel_dotclock_calculate(int link_freq,
8521                              const struct intel_link_m_n *m_n)
8522 {
8523         /*
8524          * The calculation for the data clock is:
8525          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8526          * But we want to avoid losing precison if possible, so:
8527          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8528          *
8529          * and the link clock is simpler:
8530          * link_clock = (m * link_clock) / n
8531          */
8532
8533         if (!m_n->link_n)
8534                 return 0;
8535
8536         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8537 }
8538
8539 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8540                                    struct intel_crtc_config *pipe_config)
8541 {
8542         struct drm_device *dev = crtc->base.dev;
8543
8544         /* read out port_clock from the DPLL */
8545         i9xx_crtc_clock_get(crtc, pipe_config);
8546
8547         /*
8548          * This value does not include pixel_multiplier.
8549          * We will check that port_clock and adjusted_mode.crtc_clock
8550          * agree once we know their relationship in the encoder's
8551          * get_config() function.
8552          */
8553         pipe_config->adjusted_mode.crtc_clock =
8554                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8555                                          &pipe_config->fdi_m_n);
8556 }
8557
8558 /** Returns the currently programmed mode of the given pipe. */
8559 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8560                                              struct drm_crtc *crtc)
8561 {
8562         struct drm_i915_private *dev_priv = dev->dev_private;
8563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8564         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8565         struct drm_display_mode *mode;
8566         struct intel_crtc_config pipe_config;
8567         int htot = I915_READ(HTOTAL(cpu_transcoder));
8568         int hsync = I915_READ(HSYNC(cpu_transcoder));
8569         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8570         int vsync = I915_READ(VSYNC(cpu_transcoder));
8571         enum pipe pipe = intel_crtc->pipe;
8572
8573         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8574         if (!mode)
8575                 return NULL;
8576
8577         /*
8578          * Construct a pipe_config sufficient for getting the clock info
8579          * back out of crtc_clock_get.
8580          *
8581          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8582          * to use a real value here instead.
8583          */
8584         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8585         pipe_config.pixel_multiplier = 1;
8586         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8587         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8588         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8589         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8590
8591         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8592         mode->hdisplay = (htot & 0xffff) + 1;
8593         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8594         mode->hsync_start = (hsync & 0xffff) + 1;
8595         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8596         mode->vdisplay = (vtot & 0xffff) + 1;
8597         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8598         mode->vsync_start = (vsync & 0xffff) + 1;
8599         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8600
8601         drm_mode_set_name(mode);
8602
8603         return mode;
8604 }
8605
8606 static void intel_increase_pllclock(struct drm_crtc *crtc)
8607 {
8608         struct drm_device *dev = crtc->dev;
8609         struct drm_i915_private *dev_priv = dev->dev_private;
8610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8611         int pipe = intel_crtc->pipe;
8612         int dpll_reg = DPLL(pipe);
8613         int dpll;
8614
8615         if (HAS_PCH_SPLIT(dev))
8616                 return;
8617
8618         if (!dev_priv->lvds_downclock_avail)
8619                 return;
8620
8621         dpll = I915_READ(dpll_reg);
8622         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8623                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8624
8625                 assert_panel_unlocked(dev_priv, pipe);
8626
8627                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8628                 I915_WRITE(dpll_reg, dpll);
8629                 intel_wait_for_vblank(dev, pipe);
8630
8631                 dpll = I915_READ(dpll_reg);
8632                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8633                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8634         }
8635 }
8636
8637 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8638 {
8639         struct drm_device *dev = crtc->dev;
8640         struct drm_i915_private *dev_priv = dev->dev_private;
8641         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8642
8643         if (HAS_PCH_SPLIT(dev))
8644                 return;
8645
8646         if (!dev_priv->lvds_downclock_avail)
8647                 return;
8648
8649         /*
8650          * Since this is called by a timer, we should never get here in
8651          * the manual case.
8652          */
8653         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8654                 int pipe = intel_crtc->pipe;
8655                 int dpll_reg = DPLL(pipe);
8656                 int dpll;
8657
8658                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8659
8660                 assert_panel_unlocked(dev_priv, pipe);
8661
8662                 dpll = I915_READ(dpll_reg);
8663                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8664                 I915_WRITE(dpll_reg, dpll);
8665                 intel_wait_for_vblank(dev, pipe);
8666                 dpll = I915_READ(dpll_reg);
8667                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8668                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8669         }
8670
8671 }
8672
8673 void intel_mark_busy(struct drm_device *dev)
8674 {
8675         struct drm_i915_private *dev_priv = dev->dev_private;
8676
8677         if (dev_priv->mm.busy)
8678                 return;
8679
8680         intel_runtime_pm_get(dev_priv);
8681         i915_update_gfx_val(dev_priv);
8682         dev_priv->mm.busy = true;
8683 }
8684
8685 void intel_mark_idle(struct drm_device *dev)
8686 {
8687         struct drm_i915_private *dev_priv = dev->dev_private;
8688         struct drm_crtc *crtc;
8689
8690         if (!dev_priv->mm.busy)
8691                 return;
8692
8693         dev_priv->mm.busy = false;
8694
8695         if (!i915.powersave)
8696                 goto out;
8697
8698         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8699                 if (!crtc->primary->fb)
8700                         continue;
8701
8702                 intel_decrease_pllclock(crtc);
8703         }
8704
8705         if (INTEL_INFO(dev)->gen >= 6)
8706                 gen6_rps_idle(dev->dev_private);
8707
8708 out:
8709         intel_runtime_pm_put(dev_priv);
8710 }
8711
8712 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8713                         struct intel_ring_buffer *ring)
8714 {
8715         struct drm_device *dev = obj->base.dev;
8716         struct drm_crtc *crtc;
8717
8718         if (!i915.powersave)
8719                 return;
8720
8721         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8722                 if (!crtc->primary->fb)
8723                         continue;
8724
8725                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8726                         continue;
8727
8728                 intel_increase_pllclock(crtc);
8729                 if (ring && intel_fbc_enabled(dev))
8730                         ring->fbc_dirty = true;
8731         }
8732 }
8733
8734 static void intel_crtc_destroy(struct drm_crtc *crtc)
8735 {
8736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8737         struct drm_device *dev = crtc->dev;
8738         struct intel_unpin_work *work;
8739         unsigned long flags;
8740
8741         spin_lock_irqsave(&dev->event_lock, flags);
8742         work = intel_crtc->unpin_work;
8743         intel_crtc->unpin_work = NULL;
8744         spin_unlock_irqrestore(&dev->event_lock, flags);
8745
8746         if (work) {
8747                 cancel_work_sync(&work->work);
8748                 kfree(work);
8749         }
8750
8751         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8752
8753         drm_crtc_cleanup(crtc);
8754
8755         kfree(intel_crtc);
8756 }
8757
8758 static void intel_unpin_work_fn(struct work_struct *__work)
8759 {
8760         struct intel_unpin_work *work =
8761                 container_of(__work, struct intel_unpin_work, work);
8762         struct drm_device *dev = work->crtc->dev;
8763
8764         mutex_lock(&dev->struct_mutex);
8765         intel_unpin_fb_obj(work->old_fb_obj);
8766         drm_gem_object_unreference(&work->pending_flip_obj->base);
8767         drm_gem_object_unreference(&work->old_fb_obj->base);
8768
8769         intel_update_fbc(dev);
8770         mutex_unlock(&dev->struct_mutex);
8771
8772         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8773         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8774
8775         kfree(work);
8776 }
8777
8778 static void do_intel_finish_page_flip(struct drm_device *dev,
8779                                       struct drm_crtc *crtc)
8780 {
8781         struct drm_i915_private *dev_priv = dev->dev_private;
8782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8783         struct intel_unpin_work *work;
8784         unsigned long flags;
8785
8786         /* Ignore early vblank irqs */
8787         if (intel_crtc == NULL)
8788                 return;
8789
8790         spin_lock_irqsave(&dev->event_lock, flags);
8791         work = intel_crtc->unpin_work;
8792
8793         /* Ensure we don't miss a work->pending update ... */
8794         smp_rmb();
8795
8796         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8797                 spin_unlock_irqrestore(&dev->event_lock, flags);
8798                 return;
8799         }
8800
8801         /* and that the unpin work is consistent wrt ->pending. */
8802         smp_rmb();
8803
8804         intel_crtc->unpin_work = NULL;
8805
8806         if (work->event)
8807                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8808
8809         drm_vblank_put(dev, intel_crtc->pipe);
8810
8811         spin_unlock_irqrestore(&dev->event_lock, flags);
8812
8813         wake_up_all(&dev_priv->pending_flip_queue);
8814
8815         queue_work(dev_priv->wq, &work->work);
8816
8817         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8818 }
8819
8820 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8821 {
8822         struct drm_i915_private *dev_priv = dev->dev_private;
8823         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8824
8825         do_intel_finish_page_flip(dev, crtc);
8826 }
8827
8828 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8829 {
8830         struct drm_i915_private *dev_priv = dev->dev_private;
8831         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8832
8833         do_intel_finish_page_flip(dev, crtc);
8834 }
8835
8836 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8837 {
8838         struct drm_i915_private *dev_priv = dev->dev_private;
8839         struct intel_crtc *intel_crtc =
8840                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8841         unsigned long flags;
8842
8843         /* NB: An MMIO update of the plane base pointer will also
8844          * generate a page-flip completion irq, i.e. every modeset
8845          * is also accompanied by a spurious intel_prepare_page_flip().
8846          */
8847         spin_lock_irqsave(&dev->event_lock, flags);
8848         if (intel_crtc->unpin_work)
8849                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8850         spin_unlock_irqrestore(&dev->event_lock, flags);
8851 }
8852
8853 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8854 {
8855         /* Ensure that the work item is consistent when activating it ... */
8856         smp_wmb();
8857         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8858         /* and that it is marked active as soon as the irq could fire. */
8859         smp_wmb();
8860 }
8861
8862 static int intel_gen2_queue_flip(struct drm_device *dev,
8863                                  struct drm_crtc *crtc,
8864                                  struct drm_framebuffer *fb,
8865                                  struct drm_i915_gem_object *obj,
8866                                  uint32_t flags)
8867 {
8868         struct drm_i915_private *dev_priv = dev->dev_private;
8869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8870         u32 flip_mask;
8871         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8872         int ret;
8873
8874         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8875         if (ret)
8876                 goto err;
8877
8878         ret = intel_ring_begin(ring, 6);
8879         if (ret)
8880                 goto err_unpin;
8881
8882         /* Can't queue multiple flips, so wait for the previous
8883          * one to finish before executing the next.
8884          */
8885         if (intel_crtc->plane)
8886                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8887         else
8888                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8889         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8890         intel_ring_emit(ring, MI_NOOP);
8891         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8892                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8893         intel_ring_emit(ring, fb->pitches[0]);
8894         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8895         intel_ring_emit(ring, 0); /* aux display base address, unused */
8896
8897         intel_mark_page_flip_active(intel_crtc);
8898         __intel_ring_advance(ring);
8899         return 0;
8900
8901 err_unpin:
8902         intel_unpin_fb_obj(obj);
8903 err:
8904         return ret;
8905 }
8906
8907 static int intel_gen3_queue_flip(struct drm_device *dev,
8908                                  struct drm_crtc *crtc,
8909                                  struct drm_framebuffer *fb,
8910                                  struct drm_i915_gem_object *obj,
8911                                  uint32_t flags)
8912 {
8913         struct drm_i915_private *dev_priv = dev->dev_private;
8914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8915         u32 flip_mask;
8916         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8917         int ret;
8918
8919         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8920         if (ret)
8921                 goto err;
8922
8923         ret = intel_ring_begin(ring, 6);
8924         if (ret)
8925                 goto err_unpin;
8926
8927         if (intel_crtc->plane)
8928                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8929         else
8930                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8931         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8932         intel_ring_emit(ring, MI_NOOP);
8933         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8934                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8935         intel_ring_emit(ring, fb->pitches[0]);
8936         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8937         intel_ring_emit(ring, MI_NOOP);
8938
8939         intel_mark_page_flip_active(intel_crtc);
8940         __intel_ring_advance(ring);
8941         return 0;
8942
8943 err_unpin:
8944         intel_unpin_fb_obj(obj);
8945 err:
8946         return ret;
8947 }
8948
8949 static int intel_gen4_queue_flip(struct drm_device *dev,
8950                                  struct drm_crtc *crtc,
8951                                  struct drm_framebuffer *fb,
8952                                  struct drm_i915_gem_object *obj,
8953                                  uint32_t flags)
8954 {
8955         struct drm_i915_private *dev_priv = dev->dev_private;
8956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8957         uint32_t pf, pipesrc;
8958         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8959         int ret;
8960
8961         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8962         if (ret)
8963                 goto err;
8964
8965         ret = intel_ring_begin(ring, 4);
8966         if (ret)
8967                 goto err_unpin;
8968
8969         /* i965+ uses the linear or tiled offsets from the
8970          * Display Registers (which do not change across a page-flip)
8971          * so we need only reprogram the base address.
8972          */
8973         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8974                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8975         intel_ring_emit(ring, fb->pitches[0]);
8976         intel_ring_emit(ring,
8977                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8978                         obj->tiling_mode);
8979
8980         /* XXX Enabling the panel-fitter across page-flip is so far
8981          * untested on non-native modes, so ignore it for now.
8982          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8983          */
8984         pf = 0;
8985         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8986         intel_ring_emit(ring, pf | pipesrc);
8987
8988         intel_mark_page_flip_active(intel_crtc);
8989         __intel_ring_advance(ring);
8990         return 0;
8991
8992 err_unpin:
8993         intel_unpin_fb_obj(obj);
8994 err:
8995         return ret;
8996 }
8997
8998 static int intel_gen6_queue_flip(struct drm_device *dev,
8999                                  struct drm_crtc *crtc,
9000                                  struct drm_framebuffer *fb,
9001                                  struct drm_i915_gem_object *obj,
9002                                  uint32_t flags)
9003 {
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9006         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9007         uint32_t pf, pipesrc;
9008         int ret;
9009
9010         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9011         if (ret)
9012                 goto err;
9013
9014         ret = intel_ring_begin(ring, 4);
9015         if (ret)
9016                 goto err_unpin;
9017
9018         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9019                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9020         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9021         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9022
9023         /* Contrary to the suggestions in the documentation,
9024          * "Enable Panel Fitter" does not seem to be required when page
9025          * flipping with a non-native mode, and worse causes a normal
9026          * modeset to fail.
9027          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9028          */
9029         pf = 0;
9030         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9031         intel_ring_emit(ring, pf | pipesrc);
9032
9033         intel_mark_page_flip_active(intel_crtc);
9034         __intel_ring_advance(ring);
9035         return 0;
9036
9037 err_unpin:
9038         intel_unpin_fb_obj(obj);
9039 err:
9040         return ret;
9041 }
9042
9043 static int intel_gen7_queue_flip(struct drm_device *dev,
9044                                  struct drm_crtc *crtc,
9045                                  struct drm_framebuffer *fb,
9046                                  struct drm_i915_gem_object *obj,
9047                                  uint32_t flags)
9048 {
9049         struct drm_i915_private *dev_priv = dev->dev_private;
9050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9051         struct intel_ring_buffer *ring;
9052         uint32_t plane_bit = 0;
9053         int len, ret;
9054
9055         ring = obj->ring;
9056         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9057                 ring = &dev_priv->ring[BCS];
9058
9059         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9060         if (ret)
9061                 goto err;
9062
9063         switch(intel_crtc->plane) {
9064         case PLANE_A:
9065                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9066                 break;
9067         case PLANE_B:
9068                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9069                 break;
9070         case PLANE_C:
9071                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9072                 break;
9073         default:
9074                 WARN_ONCE(1, "unknown plane in flip command\n");
9075                 ret = -ENODEV;
9076                 goto err_unpin;
9077         }
9078
9079         len = 4;
9080         if (ring->id == RCS) {
9081                 len += 6;
9082                 /*
9083                  * On Gen 8, SRM is now taking an extra dword to accommodate
9084                  * 48bits addresses, and we need a NOOP for the batch size to
9085                  * stay even.
9086                  */
9087                 if (IS_GEN8(dev))
9088                         len += 2;
9089         }
9090
9091         /*
9092          * BSpec MI_DISPLAY_FLIP for IVB:
9093          * "The full packet must be contained within the same cache line."
9094          *
9095          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9096          * cacheline, if we ever start emitting more commands before
9097          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9098          * then do the cacheline alignment, and finally emit the
9099          * MI_DISPLAY_FLIP.
9100          */
9101         ret = intel_ring_cacheline_align(ring);
9102         if (ret)
9103                 goto err_unpin;
9104
9105         ret = intel_ring_begin(ring, len);
9106         if (ret)
9107                 goto err_unpin;
9108
9109         /* Unmask the flip-done completion message. Note that the bspec says that
9110          * we should do this for both the BCS and RCS, and that we must not unmask
9111          * more than one flip event at any time (or ensure that one flip message
9112          * can be sent by waiting for flip-done prior to queueing new flips).
9113          * Experimentation says that BCS works despite DERRMR masking all
9114          * flip-done completion events and that unmasking all planes at once
9115          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9116          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9117          */
9118         if (ring->id == RCS) {
9119                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9120                 intel_ring_emit(ring, DERRMR);
9121                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9122                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9123                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9124                 if (IS_GEN8(dev))
9125                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9126                                               MI_SRM_LRM_GLOBAL_GTT);
9127                 else
9128                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9129                                               MI_SRM_LRM_GLOBAL_GTT);
9130                 intel_ring_emit(ring, DERRMR);
9131                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9132                 if (IS_GEN8(dev)) {
9133                         intel_ring_emit(ring, 0);
9134                         intel_ring_emit(ring, MI_NOOP);
9135                 }
9136         }
9137
9138         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9139         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9140         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9141         intel_ring_emit(ring, (MI_NOOP));
9142
9143         intel_mark_page_flip_active(intel_crtc);
9144         __intel_ring_advance(ring);
9145         return 0;
9146
9147 err_unpin:
9148         intel_unpin_fb_obj(obj);
9149 err:
9150         return ret;
9151 }
9152
9153 static int intel_default_queue_flip(struct drm_device *dev,
9154                                     struct drm_crtc *crtc,
9155                                     struct drm_framebuffer *fb,
9156                                     struct drm_i915_gem_object *obj,
9157                                     uint32_t flags)
9158 {
9159         return -ENODEV;
9160 }
9161
9162 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9163                                 struct drm_framebuffer *fb,
9164                                 struct drm_pending_vblank_event *event,
9165                                 uint32_t page_flip_flags)
9166 {
9167         struct drm_device *dev = crtc->dev;
9168         struct drm_i915_private *dev_priv = dev->dev_private;
9169         struct drm_framebuffer *old_fb = crtc->primary->fb;
9170         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9172         struct intel_unpin_work *work;
9173         unsigned long flags;
9174         int ret;
9175
9176         /* Can't change pixel format via MI display flips. */
9177         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9178                 return -EINVAL;
9179
9180         /*
9181          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9182          * Note that pitch changes could also affect these register.
9183          */
9184         if (INTEL_INFO(dev)->gen > 3 &&
9185             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9186              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9187                 return -EINVAL;
9188
9189         if (i915_terminally_wedged(&dev_priv->gpu_error))
9190                 goto out_hang;
9191
9192         work = kzalloc(sizeof(*work), GFP_KERNEL);
9193         if (work == NULL)
9194                 return -ENOMEM;
9195
9196         work->event = event;
9197         work->crtc = crtc;
9198         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9199         INIT_WORK(&work->work, intel_unpin_work_fn);
9200
9201         ret = drm_vblank_get(dev, intel_crtc->pipe);
9202         if (ret)
9203                 goto free_work;
9204
9205         /* We borrow the event spin lock for protecting unpin_work */
9206         spin_lock_irqsave(&dev->event_lock, flags);
9207         if (intel_crtc->unpin_work) {
9208                 spin_unlock_irqrestore(&dev->event_lock, flags);
9209                 kfree(work);
9210                 drm_vblank_put(dev, intel_crtc->pipe);
9211
9212                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9213                 return -EBUSY;
9214         }
9215         intel_crtc->unpin_work = work;
9216         spin_unlock_irqrestore(&dev->event_lock, flags);
9217
9218         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9219                 flush_workqueue(dev_priv->wq);
9220
9221         ret = i915_mutex_lock_interruptible(dev);
9222         if (ret)
9223                 goto cleanup;
9224
9225         /* Reference the objects for the scheduled work. */
9226         drm_gem_object_reference(&work->old_fb_obj->base);
9227         drm_gem_object_reference(&obj->base);
9228
9229         crtc->primary->fb = fb;
9230
9231         work->pending_flip_obj = obj;
9232
9233         work->enable_stall_check = true;
9234
9235         atomic_inc(&intel_crtc->unpin_work_count);
9236         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9237
9238         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9239         if (ret)
9240                 goto cleanup_pending;
9241
9242         intel_disable_fbc(dev);
9243         intel_mark_fb_busy(obj, NULL);
9244         mutex_unlock(&dev->struct_mutex);
9245
9246         trace_i915_flip_request(intel_crtc->plane, obj);
9247
9248         return 0;
9249
9250 cleanup_pending:
9251         atomic_dec(&intel_crtc->unpin_work_count);
9252         crtc->primary->fb = old_fb;
9253         drm_gem_object_unreference(&work->old_fb_obj->base);
9254         drm_gem_object_unreference(&obj->base);
9255         mutex_unlock(&dev->struct_mutex);
9256
9257 cleanup:
9258         spin_lock_irqsave(&dev->event_lock, flags);
9259         intel_crtc->unpin_work = NULL;
9260         spin_unlock_irqrestore(&dev->event_lock, flags);
9261
9262         drm_vblank_put(dev, intel_crtc->pipe);
9263 free_work:
9264         kfree(work);
9265
9266         if (ret == -EIO) {
9267 out_hang:
9268                 intel_crtc_wait_for_pending_flips(crtc);
9269                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9270                 if (ret == 0 && event)
9271                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9272         }
9273         return ret;
9274 }
9275
9276 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9277         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9278         .load_lut = intel_crtc_load_lut,
9279 };
9280
9281 /**
9282  * intel_modeset_update_staged_output_state
9283  *
9284  * Updates the staged output configuration state, e.g. after we've read out the
9285  * current hw state.
9286  */
9287 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9288 {
9289         struct intel_crtc *crtc;
9290         struct intel_encoder *encoder;
9291         struct intel_connector *connector;
9292
9293         list_for_each_entry(connector, &dev->mode_config.connector_list,
9294                             base.head) {
9295                 connector->new_encoder =
9296                         to_intel_encoder(connector->base.encoder);
9297         }
9298
9299         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9300                             base.head) {
9301                 encoder->new_crtc =
9302                         to_intel_crtc(encoder->base.crtc);
9303         }
9304
9305         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9306                             base.head) {
9307                 crtc->new_enabled = crtc->base.enabled;
9308
9309                 if (crtc->new_enabled)
9310                         crtc->new_config = &crtc->config;
9311                 else
9312                         crtc->new_config = NULL;
9313         }
9314 }
9315
9316 /**
9317  * intel_modeset_commit_output_state
9318  *
9319  * This function copies the stage display pipe configuration to the real one.
9320  */
9321 static void intel_modeset_commit_output_state(struct drm_device *dev)
9322 {
9323         struct intel_crtc *crtc;
9324         struct intel_encoder *encoder;
9325         struct intel_connector *connector;
9326
9327         list_for_each_entry(connector, &dev->mode_config.connector_list,
9328                             base.head) {
9329                 connector->base.encoder = &connector->new_encoder->base;
9330         }
9331
9332         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9333                             base.head) {
9334                 encoder->base.crtc = &encoder->new_crtc->base;
9335         }
9336
9337         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9338                             base.head) {
9339                 crtc->base.enabled = crtc->new_enabled;
9340         }
9341 }
9342
9343 static void
9344 connected_sink_compute_bpp(struct intel_connector * connector,
9345                            struct intel_crtc_config *pipe_config)
9346 {
9347         int bpp = pipe_config->pipe_bpp;
9348
9349         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9350                 connector->base.base.id,
9351                 drm_get_connector_name(&connector->base));
9352
9353         /* Don't use an invalid EDID bpc value */
9354         if (connector->base.display_info.bpc &&
9355             connector->base.display_info.bpc * 3 < bpp) {
9356                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9357                               bpp, connector->base.display_info.bpc*3);
9358                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9359         }
9360
9361         /* Clamp bpp to 8 on screens without EDID 1.4 */
9362         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9363                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9364                               bpp);
9365                 pipe_config->pipe_bpp = 24;
9366         }
9367 }
9368
9369 static int
9370 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9371                           struct drm_framebuffer *fb,
9372                           struct intel_crtc_config *pipe_config)
9373 {
9374         struct drm_device *dev = crtc->base.dev;
9375         struct intel_connector *connector;
9376         int bpp;
9377
9378         switch (fb->pixel_format) {
9379         case DRM_FORMAT_C8:
9380                 bpp = 8*3; /* since we go through a colormap */
9381                 break;
9382         case DRM_FORMAT_XRGB1555:
9383         case DRM_FORMAT_ARGB1555:
9384                 /* checked in intel_framebuffer_init already */
9385                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9386                         return -EINVAL;
9387         case DRM_FORMAT_RGB565:
9388                 bpp = 6*3; /* min is 18bpp */
9389                 break;
9390         case DRM_FORMAT_XBGR8888:
9391         case DRM_FORMAT_ABGR8888:
9392                 /* checked in intel_framebuffer_init already */
9393                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9394                         return -EINVAL;
9395         case DRM_FORMAT_XRGB8888:
9396         case DRM_FORMAT_ARGB8888:
9397                 bpp = 8*3;
9398                 break;
9399         case DRM_FORMAT_XRGB2101010:
9400         case DRM_FORMAT_ARGB2101010:
9401         case DRM_FORMAT_XBGR2101010:
9402         case DRM_FORMAT_ABGR2101010:
9403                 /* checked in intel_framebuffer_init already */
9404                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9405                         return -EINVAL;
9406                 bpp = 10*3;
9407                 break;
9408         /* TODO: gen4+ supports 16 bpc floating point, too. */
9409         default:
9410                 DRM_DEBUG_KMS("unsupported depth\n");
9411                 return -EINVAL;
9412         }
9413
9414         pipe_config->pipe_bpp = bpp;
9415
9416         /* Clamp display bpp to EDID value */
9417         list_for_each_entry(connector, &dev->mode_config.connector_list,
9418                             base.head) {
9419                 if (!connector->new_encoder ||
9420                     connector->new_encoder->new_crtc != crtc)
9421                         continue;
9422
9423                 connected_sink_compute_bpp(connector, pipe_config);
9424         }
9425
9426         return bpp;
9427 }
9428
9429 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9430 {
9431         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9432                         "type: 0x%x flags: 0x%x\n",
9433                 mode->crtc_clock,
9434                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9435                 mode->crtc_hsync_end, mode->crtc_htotal,
9436                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9437                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9438 }
9439
9440 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9441                                    struct intel_crtc_config *pipe_config,
9442                                    const char *context)
9443 {
9444         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9445                       context, pipe_name(crtc->pipe));
9446
9447         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9448         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9449                       pipe_config->pipe_bpp, pipe_config->dither);
9450         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9451                       pipe_config->has_pch_encoder,
9452                       pipe_config->fdi_lanes,
9453                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9454                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9455                       pipe_config->fdi_m_n.tu);
9456         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9457                       pipe_config->has_dp_encoder,
9458                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9459                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9460                       pipe_config->dp_m_n.tu);
9461         DRM_DEBUG_KMS("requested mode:\n");
9462         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9463         DRM_DEBUG_KMS("adjusted mode:\n");
9464         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9465         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9466         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9467         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9468                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9469         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9470                       pipe_config->gmch_pfit.control,
9471                       pipe_config->gmch_pfit.pgm_ratios,
9472                       pipe_config->gmch_pfit.lvds_border_bits);
9473         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9474                       pipe_config->pch_pfit.pos,
9475                       pipe_config->pch_pfit.size,
9476                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9477         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9478         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9479 }
9480
9481 static bool encoders_cloneable(const struct intel_encoder *a,
9482                                const struct intel_encoder *b)
9483 {
9484         /* masks could be asymmetric, so check both ways */
9485         return a == b || (a->cloneable & (1 << b->type) &&
9486                           b->cloneable & (1 << a->type));
9487 }
9488
9489 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9490                                          struct intel_encoder *encoder)
9491 {
9492         struct drm_device *dev = crtc->base.dev;
9493         struct intel_encoder *source_encoder;
9494
9495         list_for_each_entry(source_encoder,
9496                             &dev->mode_config.encoder_list, base.head) {
9497                 if (source_encoder->new_crtc != crtc)
9498                         continue;
9499
9500                 if (!encoders_cloneable(encoder, source_encoder))
9501                         return false;
9502         }
9503
9504         return true;
9505 }
9506
9507 static bool check_encoder_cloning(struct intel_crtc *crtc)
9508 {
9509         struct drm_device *dev = crtc->base.dev;
9510         struct intel_encoder *encoder;
9511
9512         list_for_each_entry(encoder,
9513                             &dev->mode_config.encoder_list, base.head) {
9514                 if (encoder->new_crtc != crtc)
9515                         continue;
9516
9517                 if (!check_single_encoder_cloning(crtc, encoder))
9518                         return false;
9519         }
9520
9521         return true;
9522 }
9523
9524 static struct intel_crtc_config *
9525 intel_modeset_pipe_config(struct drm_crtc *crtc,
9526                           struct drm_framebuffer *fb,
9527                           struct drm_display_mode *mode)
9528 {
9529         struct drm_device *dev = crtc->dev;
9530         struct intel_encoder *encoder;
9531         struct intel_crtc_config *pipe_config;
9532         int plane_bpp, ret = -EINVAL;
9533         bool retry = true;
9534
9535         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9536                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9537                 return ERR_PTR(-EINVAL);
9538         }
9539
9540         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9541         if (!pipe_config)
9542                 return ERR_PTR(-ENOMEM);
9543
9544         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9545         drm_mode_copy(&pipe_config->requested_mode, mode);
9546
9547         pipe_config->cpu_transcoder =
9548                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9549         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9550
9551         /*
9552          * Sanitize sync polarity flags based on requested ones. If neither
9553          * positive or negative polarity is requested, treat this as meaning
9554          * negative polarity.
9555          */
9556         if (!(pipe_config->adjusted_mode.flags &
9557               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9558                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9559
9560         if (!(pipe_config->adjusted_mode.flags &
9561               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9562                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9563
9564         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9565          * plane pixel format and any sink constraints into account. Returns the
9566          * source plane bpp so that dithering can be selected on mismatches
9567          * after encoders and crtc also have had their say. */
9568         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9569                                               fb, pipe_config);
9570         if (plane_bpp < 0)
9571                 goto fail;
9572
9573         /*
9574          * Determine the real pipe dimensions. Note that stereo modes can
9575          * increase the actual pipe size due to the frame doubling and
9576          * insertion of additional space for blanks between the frame. This
9577          * is stored in the crtc timings. We use the requested mode to do this
9578          * computation to clearly distinguish it from the adjusted mode, which
9579          * can be changed by the connectors in the below retry loop.
9580          */
9581         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9582         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9583         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9584
9585 encoder_retry:
9586         /* Ensure the port clock defaults are reset when retrying. */
9587         pipe_config->port_clock = 0;
9588         pipe_config->pixel_multiplier = 1;
9589
9590         /* Fill in default crtc timings, allow encoders to overwrite them. */
9591         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9592
9593         /* Pass our mode to the connectors and the CRTC to give them a chance to
9594          * adjust it according to limitations or connector properties, and also
9595          * a chance to reject the mode entirely.
9596          */
9597         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9598                             base.head) {
9599
9600                 if (&encoder->new_crtc->base != crtc)
9601                         continue;
9602
9603                 if (!(encoder->compute_config(encoder, pipe_config))) {
9604                         DRM_DEBUG_KMS("Encoder config failure\n");
9605                         goto fail;
9606                 }
9607         }
9608
9609         /* Set default port clock if not overwritten by the encoder. Needs to be
9610          * done afterwards in case the encoder adjusts the mode. */
9611         if (!pipe_config->port_clock)
9612                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9613                         * pipe_config->pixel_multiplier;
9614
9615         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9616         if (ret < 0) {
9617                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9618                 goto fail;
9619         }
9620
9621         if (ret == RETRY) {
9622                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9623                         ret = -EINVAL;
9624                         goto fail;
9625                 }
9626
9627                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9628                 retry = false;
9629                 goto encoder_retry;
9630         }
9631
9632         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9633         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9634                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9635
9636         return pipe_config;
9637 fail:
9638         kfree(pipe_config);
9639         return ERR_PTR(ret);
9640 }
9641
9642 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9643  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9644 static void
9645 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9646                              unsigned *prepare_pipes, unsigned *disable_pipes)
9647 {
9648         struct intel_crtc *intel_crtc;
9649         struct drm_device *dev = crtc->dev;
9650         struct intel_encoder *encoder;
9651         struct intel_connector *connector;
9652         struct drm_crtc *tmp_crtc;
9653
9654         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9655
9656         /* Check which crtcs have changed outputs connected to them, these need
9657          * to be part of the prepare_pipes mask. We don't (yet) support global
9658          * modeset across multiple crtcs, so modeset_pipes will only have one
9659          * bit set at most. */
9660         list_for_each_entry(connector, &dev->mode_config.connector_list,
9661                             base.head) {
9662                 if (connector->base.encoder == &connector->new_encoder->base)
9663                         continue;
9664
9665                 if (connector->base.encoder) {
9666                         tmp_crtc = connector->base.encoder->crtc;
9667
9668                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9669                 }
9670
9671                 if (connector->new_encoder)
9672                         *prepare_pipes |=
9673                                 1 << connector->new_encoder->new_crtc->pipe;
9674         }
9675
9676         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9677                             base.head) {
9678                 if (encoder->base.crtc == &encoder->new_crtc->base)
9679                         continue;
9680
9681                 if (encoder->base.crtc) {
9682                         tmp_crtc = encoder->base.crtc;
9683
9684                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9685                 }
9686
9687                 if (encoder->new_crtc)
9688                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9689         }
9690
9691         /* Check for pipes that will be enabled/disabled ... */
9692         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9693                             base.head) {
9694                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9695                         continue;
9696
9697                 if (!intel_crtc->new_enabled)
9698                         *disable_pipes |= 1 << intel_crtc->pipe;
9699                 else
9700                         *prepare_pipes |= 1 << intel_crtc->pipe;
9701         }
9702
9703
9704         /* set_mode is also used to update properties on life display pipes. */
9705         intel_crtc = to_intel_crtc(crtc);
9706         if (intel_crtc->new_enabled)
9707                 *prepare_pipes |= 1 << intel_crtc->pipe;
9708
9709         /*
9710          * For simplicity do a full modeset on any pipe where the output routing
9711          * changed. We could be more clever, but that would require us to be
9712          * more careful with calling the relevant encoder->mode_set functions.
9713          */
9714         if (*prepare_pipes)
9715                 *modeset_pipes = *prepare_pipes;
9716
9717         /* ... and mask these out. */
9718         *modeset_pipes &= ~(*disable_pipes);
9719         *prepare_pipes &= ~(*disable_pipes);
9720
9721         /*
9722          * HACK: We don't (yet) fully support global modesets. intel_set_config
9723          * obies this rule, but the modeset restore mode of
9724          * intel_modeset_setup_hw_state does not.
9725          */
9726         *modeset_pipes &= 1 << intel_crtc->pipe;
9727         *prepare_pipes &= 1 << intel_crtc->pipe;
9728
9729         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9730                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9731 }
9732
9733 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9734 {
9735         struct drm_encoder *encoder;
9736         struct drm_device *dev = crtc->dev;
9737
9738         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9739                 if (encoder->crtc == crtc)
9740                         return true;
9741
9742         return false;
9743 }
9744
9745 static void
9746 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9747 {
9748         struct intel_encoder *intel_encoder;
9749         struct intel_crtc *intel_crtc;
9750         struct drm_connector *connector;
9751
9752         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9753                             base.head) {
9754                 if (!intel_encoder->base.crtc)
9755                         continue;
9756
9757                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9758
9759                 if (prepare_pipes & (1 << intel_crtc->pipe))
9760                         intel_encoder->connectors_active = false;
9761         }
9762
9763         intel_modeset_commit_output_state(dev);
9764
9765         /* Double check state. */
9766         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9767                             base.head) {
9768                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9769                 WARN_ON(intel_crtc->new_config &&
9770                         intel_crtc->new_config != &intel_crtc->config);
9771                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9772         }
9773
9774         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9775                 if (!connector->encoder || !connector->encoder->crtc)
9776                         continue;
9777
9778                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9779
9780                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9781                         struct drm_property *dpms_property =
9782                                 dev->mode_config.dpms_property;
9783
9784                         connector->dpms = DRM_MODE_DPMS_ON;
9785                         drm_object_property_set_value(&connector->base,
9786                                                          dpms_property,
9787                                                          DRM_MODE_DPMS_ON);
9788
9789                         intel_encoder = to_intel_encoder(connector->encoder);
9790                         intel_encoder->connectors_active = true;
9791                 }
9792         }
9793
9794 }
9795
9796 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9797 {
9798         int diff;
9799
9800         if (clock1 == clock2)
9801                 return true;
9802
9803         if (!clock1 || !clock2)
9804                 return false;
9805
9806         diff = abs(clock1 - clock2);
9807
9808         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9809                 return true;
9810
9811         return false;
9812 }
9813
9814 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9815         list_for_each_entry((intel_crtc), \
9816                             &(dev)->mode_config.crtc_list, \
9817                             base.head) \
9818                 if (mask & (1 <<(intel_crtc)->pipe))
9819
9820 static bool
9821 intel_pipe_config_compare(struct drm_device *dev,
9822                           struct intel_crtc_config *current_config,
9823                           struct intel_crtc_config *pipe_config)
9824 {
9825 #define PIPE_CONF_CHECK_X(name) \
9826         if (current_config->name != pipe_config->name) { \
9827                 DRM_ERROR("mismatch in " #name " " \
9828                           "(expected 0x%08x, found 0x%08x)\n", \
9829                           current_config->name, \
9830                           pipe_config->name); \
9831                 return false; \
9832         }
9833
9834 #define PIPE_CONF_CHECK_I(name) \
9835         if (current_config->name != pipe_config->name) { \
9836                 DRM_ERROR("mismatch in " #name " " \
9837                           "(expected %i, found %i)\n", \
9838                           current_config->name, \
9839                           pipe_config->name); \
9840                 return false; \
9841         }
9842
9843 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9844         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9845                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9846                           "(expected %i, found %i)\n", \
9847                           current_config->name & (mask), \
9848                           pipe_config->name & (mask)); \
9849                 return false; \
9850         }
9851
9852 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9853         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9854                 DRM_ERROR("mismatch in " #name " " \
9855                           "(expected %i, found %i)\n", \
9856                           current_config->name, \
9857                           pipe_config->name); \
9858                 return false; \
9859         }
9860
9861 #define PIPE_CONF_QUIRK(quirk)  \
9862         ((current_config->quirks | pipe_config->quirks) & (quirk))
9863
9864         PIPE_CONF_CHECK_I(cpu_transcoder);
9865
9866         PIPE_CONF_CHECK_I(has_pch_encoder);
9867         PIPE_CONF_CHECK_I(fdi_lanes);
9868         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9869         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9870         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9871         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9872         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9873
9874         PIPE_CONF_CHECK_I(has_dp_encoder);
9875         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9876         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9877         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9878         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9879         PIPE_CONF_CHECK_I(dp_m_n.tu);
9880
9881         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9882         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9883         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9884         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9885         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9886         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9887
9888         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9889         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9894
9895         PIPE_CONF_CHECK_I(pixel_multiplier);
9896
9897         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9898                               DRM_MODE_FLAG_INTERLACE);
9899
9900         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9901                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9902                                       DRM_MODE_FLAG_PHSYNC);
9903                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9904                                       DRM_MODE_FLAG_NHSYNC);
9905                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9906                                       DRM_MODE_FLAG_PVSYNC);
9907                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9908                                       DRM_MODE_FLAG_NVSYNC);
9909         }
9910
9911         PIPE_CONF_CHECK_I(pipe_src_w);
9912         PIPE_CONF_CHECK_I(pipe_src_h);
9913
9914         /*
9915          * FIXME: BIOS likes to set up a cloned config with lvds+external
9916          * screen. Since we don't yet re-compute the pipe config when moving
9917          * just the lvds port away to another pipe the sw tracking won't match.
9918          *
9919          * Proper atomic modesets with recomputed global state will fix this.
9920          * Until then just don't check gmch state for inherited modes.
9921          */
9922         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9923                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9924                 /* pfit ratios are autocomputed by the hw on gen4+ */
9925                 if (INTEL_INFO(dev)->gen < 4)
9926                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9927                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9928         }
9929
9930         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9931         if (current_config->pch_pfit.enabled) {
9932                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9933                 PIPE_CONF_CHECK_I(pch_pfit.size);
9934         }
9935
9936         /* BDW+ don't expose a synchronous way to read the state */
9937         if (IS_HASWELL(dev))
9938                 PIPE_CONF_CHECK_I(ips_enabled);
9939
9940         PIPE_CONF_CHECK_I(double_wide);
9941
9942         PIPE_CONF_CHECK_I(shared_dpll);
9943         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9944         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9945         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9946         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9947
9948         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9949                 PIPE_CONF_CHECK_I(pipe_bpp);
9950
9951         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9952         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9953
9954 #undef PIPE_CONF_CHECK_X
9955 #undef PIPE_CONF_CHECK_I
9956 #undef PIPE_CONF_CHECK_FLAGS
9957 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9958 #undef PIPE_CONF_QUIRK
9959
9960         return true;
9961 }
9962
9963 static void
9964 check_connector_state(struct drm_device *dev)
9965 {
9966         struct intel_connector *connector;
9967
9968         list_for_each_entry(connector, &dev->mode_config.connector_list,
9969                             base.head) {
9970                 /* This also checks the encoder/connector hw state with the
9971                  * ->get_hw_state callbacks. */
9972                 intel_connector_check_state(connector);
9973
9974                 WARN(&connector->new_encoder->base != connector->base.encoder,
9975                      "connector's staged encoder doesn't match current encoder\n");
9976         }
9977 }
9978
9979 static void
9980 check_encoder_state(struct drm_device *dev)
9981 {
9982         struct intel_encoder *encoder;
9983         struct intel_connector *connector;
9984
9985         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9986                             base.head) {
9987                 bool enabled = false;
9988                 bool active = false;
9989                 enum pipe pipe, tracked_pipe;
9990
9991                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9992                               encoder->base.base.id,
9993                               drm_get_encoder_name(&encoder->base));
9994
9995                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9996                      "encoder's stage crtc doesn't match current crtc\n");
9997                 WARN(encoder->connectors_active && !encoder->base.crtc,
9998                      "encoder's active_connectors set, but no crtc\n");
9999
10000                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10001                                     base.head) {
10002                         if (connector->base.encoder != &encoder->base)
10003                                 continue;
10004                         enabled = true;
10005                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10006                                 active = true;
10007                 }
10008                 WARN(!!encoder->base.crtc != enabled,
10009                      "encoder's enabled state mismatch "
10010                      "(expected %i, found %i)\n",
10011                      !!encoder->base.crtc, enabled);
10012                 WARN(active && !encoder->base.crtc,
10013                      "active encoder with no crtc\n");
10014
10015                 WARN(encoder->connectors_active != active,
10016                      "encoder's computed active state doesn't match tracked active state "
10017                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10018
10019                 active = encoder->get_hw_state(encoder, &pipe);
10020                 WARN(active != encoder->connectors_active,
10021                      "encoder's hw state doesn't match sw tracking "
10022                      "(expected %i, found %i)\n",
10023                      encoder->connectors_active, active);
10024
10025                 if (!encoder->base.crtc)
10026                         continue;
10027
10028                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10029                 WARN(active && pipe != tracked_pipe,
10030                      "active encoder's pipe doesn't match"
10031                      "(expected %i, found %i)\n",
10032                      tracked_pipe, pipe);
10033
10034         }
10035 }
10036
10037 static void
10038 check_crtc_state(struct drm_device *dev)
10039 {
10040         struct drm_i915_private *dev_priv = dev->dev_private;
10041         struct intel_crtc *crtc;
10042         struct intel_encoder *encoder;
10043         struct intel_crtc_config pipe_config;
10044
10045         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10046                             base.head) {
10047                 bool enabled = false;
10048                 bool active = false;
10049
10050                 memset(&pipe_config, 0, sizeof(pipe_config));
10051
10052                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10053                               crtc->base.base.id);
10054
10055                 WARN(crtc->active && !crtc->base.enabled,
10056                      "active crtc, but not enabled in sw tracking\n");
10057
10058                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10059                                     base.head) {
10060                         if (encoder->base.crtc != &crtc->base)
10061                                 continue;
10062                         enabled = true;
10063                         if (encoder->connectors_active)
10064                                 active = true;
10065                 }
10066
10067                 WARN(active != crtc->active,
10068                      "crtc's computed active state doesn't match tracked active state "
10069                      "(expected %i, found %i)\n", active, crtc->active);
10070                 WARN(enabled != crtc->base.enabled,
10071                      "crtc's computed enabled state doesn't match tracked enabled state "
10072                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10073
10074                 active = dev_priv->display.get_pipe_config(crtc,
10075                                                            &pipe_config);
10076
10077                 /* hw state is inconsistent with the pipe A quirk */
10078                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10079                         active = crtc->active;
10080
10081                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10082                                     base.head) {
10083                         enum pipe pipe;
10084                         if (encoder->base.crtc != &crtc->base)
10085                                 continue;
10086                         if (encoder->get_hw_state(encoder, &pipe))
10087                                 encoder->get_config(encoder, &pipe_config);
10088                 }
10089
10090                 WARN(crtc->active != active,
10091                      "crtc active state doesn't match with hw state "
10092                      "(expected %i, found %i)\n", crtc->active, active);
10093
10094                 if (active &&
10095                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10096                         WARN(1, "pipe state doesn't match!\n");
10097                         intel_dump_pipe_config(crtc, &pipe_config,
10098                                                "[hw state]");
10099                         intel_dump_pipe_config(crtc, &crtc->config,
10100                                                "[sw state]");
10101                 }
10102         }
10103 }
10104
10105 static void
10106 check_shared_dpll_state(struct drm_device *dev)
10107 {
10108         struct drm_i915_private *dev_priv = dev->dev_private;
10109         struct intel_crtc *crtc;
10110         struct intel_dpll_hw_state dpll_hw_state;
10111         int i;
10112
10113         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10114                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10115                 int enabled_crtcs = 0, active_crtcs = 0;
10116                 bool active;
10117
10118                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10119
10120                 DRM_DEBUG_KMS("%s\n", pll->name);
10121
10122                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10123
10124                 WARN(pll->active > pll->refcount,
10125                      "more active pll users than references: %i vs %i\n",
10126                      pll->active, pll->refcount);
10127                 WARN(pll->active && !pll->on,
10128                      "pll in active use but not on in sw tracking\n");
10129                 WARN(pll->on && !pll->active,
10130                      "pll in on but not on in use in sw tracking\n");
10131                 WARN(pll->on != active,
10132                      "pll on state mismatch (expected %i, found %i)\n",
10133                      pll->on, active);
10134
10135                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10136                                     base.head) {
10137                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10138                                 enabled_crtcs++;
10139                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10140                                 active_crtcs++;
10141                 }
10142                 WARN(pll->active != active_crtcs,
10143                      "pll active crtcs mismatch (expected %i, found %i)\n",
10144                      pll->active, active_crtcs);
10145                 WARN(pll->refcount != enabled_crtcs,
10146                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10147                      pll->refcount, enabled_crtcs);
10148
10149                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10150                                        sizeof(dpll_hw_state)),
10151                      "pll hw state mismatch\n");
10152         }
10153 }
10154
10155 void
10156 intel_modeset_check_state(struct drm_device *dev)
10157 {
10158         check_connector_state(dev);
10159         check_encoder_state(dev);
10160         check_crtc_state(dev);
10161         check_shared_dpll_state(dev);
10162 }
10163
10164 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10165                                      int dotclock)
10166 {
10167         /*
10168          * FDI already provided one idea for the dotclock.
10169          * Yell if the encoder disagrees.
10170          */
10171         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10172              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10173              pipe_config->adjusted_mode.crtc_clock, dotclock);
10174 }
10175
10176 static int __intel_set_mode(struct drm_crtc *crtc,
10177                             struct drm_display_mode *mode,
10178                             int x, int y, struct drm_framebuffer *fb)
10179 {
10180         struct drm_device *dev = crtc->dev;
10181         struct drm_i915_private *dev_priv = dev->dev_private;
10182         struct drm_display_mode *saved_mode;
10183         struct intel_crtc_config *pipe_config = NULL;
10184         struct intel_crtc *intel_crtc;
10185         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10186         int ret = 0;
10187
10188         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10189         if (!saved_mode)
10190                 return -ENOMEM;
10191
10192         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10193                                      &prepare_pipes, &disable_pipes);
10194
10195         *saved_mode = crtc->mode;
10196
10197         /* Hack: Because we don't (yet) support global modeset on multiple
10198          * crtcs, we don't keep track of the new mode for more than one crtc.
10199          * Hence simply check whether any bit is set in modeset_pipes in all the
10200          * pieces of code that are not yet converted to deal with mutliple crtcs
10201          * changing their mode at the same time. */
10202         if (modeset_pipes) {
10203                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10204                 if (IS_ERR(pipe_config)) {
10205                         ret = PTR_ERR(pipe_config);
10206                         pipe_config = NULL;
10207
10208                         goto out;
10209                 }
10210                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10211                                        "[modeset]");
10212                 to_intel_crtc(crtc)->new_config = pipe_config;
10213         }
10214
10215         /*
10216          * See if the config requires any additional preparation, e.g.
10217          * to adjust global state with pipes off.  We need to do this
10218          * here so we can get the modeset_pipe updated config for the new
10219          * mode set on this crtc.  For other crtcs we need to use the
10220          * adjusted_mode bits in the crtc directly.
10221          */
10222         if (IS_VALLEYVIEW(dev)) {
10223                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10224
10225                 /* may have added more to prepare_pipes than we should */
10226                 prepare_pipes &= ~disable_pipes;
10227         }
10228
10229         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10230                 intel_crtc_disable(&intel_crtc->base);
10231
10232         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10233                 if (intel_crtc->base.enabled)
10234                         dev_priv->display.crtc_disable(&intel_crtc->base);
10235         }
10236
10237         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10238          * to set it here already despite that we pass it down the callchain.
10239          */
10240         if (modeset_pipes) {
10241                 crtc->mode = *mode;
10242                 /* mode_set/enable/disable functions rely on a correct pipe
10243                  * config. */
10244                 to_intel_crtc(crtc)->config = *pipe_config;
10245                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10246
10247                 /*
10248                  * Calculate and store various constants which
10249                  * are later needed by vblank and swap-completion
10250                  * timestamping. They are derived from true hwmode.
10251                  */
10252                 drm_calc_timestamping_constants(crtc,
10253                                                 &pipe_config->adjusted_mode);
10254         }
10255
10256         /* Only after disabling all output pipelines that will be changed can we
10257          * update the the output configuration. */
10258         intel_modeset_update_state(dev, prepare_pipes);
10259
10260         if (dev_priv->display.modeset_global_resources)
10261                 dev_priv->display.modeset_global_resources(dev);
10262
10263         /* Set up the DPLL and any encoders state that needs to adjust or depend
10264          * on the DPLL.
10265          */
10266         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10267                 ret = intel_crtc_mode_set(&intel_crtc->base,
10268                                           x, y, fb);
10269                 if (ret)
10270                         goto done;
10271         }
10272
10273         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10274         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10275                 dev_priv->display.crtc_enable(&intel_crtc->base);
10276
10277         /* FIXME: add subpixel order */
10278 done:
10279         if (ret && crtc->enabled)
10280                 crtc->mode = *saved_mode;
10281
10282 out:
10283         kfree(pipe_config);
10284         kfree(saved_mode);
10285         return ret;
10286 }
10287
10288 static int intel_set_mode(struct drm_crtc *crtc,
10289                           struct drm_display_mode *mode,
10290                           int x, int y, struct drm_framebuffer *fb)
10291 {
10292         int ret;
10293
10294         ret = __intel_set_mode(crtc, mode, x, y, fb);
10295
10296         if (ret == 0)
10297                 intel_modeset_check_state(crtc->dev);
10298
10299         return ret;
10300 }
10301
10302 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10303 {
10304         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10305 }
10306
10307 #undef for_each_intel_crtc_masked
10308
10309 static void intel_set_config_free(struct intel_set_config *config)
10310 {
10311         if (!config)
10312                 return;
10313
10314         kfree(config->save_connector_encoders);
10315         kfree(config->save_encoder_crtcs);
10316         kfree(config->save_crtc_enabled);
10317         kfree(config);
10318 }
10319
10320 static int intel_set_config_save_state(struct drm_device *dev,
10321                                        struct intel_set_config *config)
10322 {
10323         struct drm_crtc *crtc;
10324         struct drm_encoder *encoder;
10325         struct drm_connector *connector;
10326         int count;
10327
10328         config->save_crtc_enabled =
10329                 kcalloc(dev->mode_config.num_crtc,
10330                         sizeof(bool), GFP_KERNEL);
10331         if (!config->save_crtc_enabled)
10332                 return -ENOMEM;
10333
10334         config->save_encoder_crtcs =
10335                 kcalloc(dev->mode_config.num_encoder,
10336                         sizeof(struct drm_crtc *), GFP_KERNEL);
10337         if (!config->save_encoder_crtcs)
10338                 return -ENOMEM;
10339
10340         config->save_connector_encoders =
10341                 kcalloc(dev->mode_config.num_connector,
10342                         sizeof(struct drm_encoder *), GFP_KERNEL);
10343         if (!config->save_connector_encoders)
10344                 return -ENOMEM;
10345
10346         /* Copy data. Note that driver private data is not affected.
10347          * Should anything bad happen only the expected state is
10348          * restored, not the drivers personal bookkeeping.
10349          */
10350         count = 0;
10351         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10352                 config->save_crtc_enabled[count++] = crtc->enabled;
10353         }
10354
10355         count = 0;
10356         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10357                 config->save_encoder_crtcs[count++] = encoder->crtc;
10358         }
10359
10360         count = 0;
10361         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10362                 config->save_connector_encoders[count++] = connector->encoder;
10363         }
10364
10365         return 0;
10366 }
10367
10368 static void intel_set_config_restore_state(struct drm_device *dev,
10369                                            struct intel_set_config *config)
10370 {
10371         struct intel_crtc *crtc;
10372         struct intel_encoder *encoder;
10373         struct intel_connector *connector;
10374         int count;
10375
10376         count = 0;
10377         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10378                 crtc->new_enabled = config->save_crtc_enabled[count++];
10379
10380                 if (crtc->new_enabled)
10381                         crtc->new_config = &crtc->config;
10382                 else
10383                         crtc->new_config = NULL;
10384         }
10385
10386         count = 0;
10387         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10388                 encoder->new_crtc =
10389                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10390         }
10391
10392         count = 0;
10393         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10394                 connector->new_encoder =
10395                         to_intel_encoder(config->save_connector_encoders[count++]);
10396         }
10397 }
10398
10399 static bool
10400 is_crtc_connector_off(struct drm_mode_set *set)
10401 {
10402         int i;
10403
10404         if (set->num_connectors == 0)
10405                 return false;
10406
10407         if (WARN_ON(set->connectors == NULL))
10408                 return false;
10409
10410         for (i = 0; i < set->num_connectors; i++)
10411                 if (set->connectors[i]->encoder &&
10412                     set->connectors[i]->encoder->crtc == set->crtc &&
10413                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10414                         return true;
10415
10416         return false;
10417 }
10418
10419 static void
10420 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10421                                       struct intel_set_config *config)
10422 {
10423
10424         /* We should be able to check here if the fb has the same properties
10425          * and then just flip_or_move it */
10426         if (is_crtc_connector_off(set)) {
10427                 config->mode_changed = true;
10428         } else if (set->crtc->primary->fb != set->fb) {
10429                 /* If we have no fb then treat it as a full mode set */
10430                 if (set->crtc->primary->fb == NULL) {
10431                         struct intel_crtc *intel_crtc =
10432                                 to_intel_crtc(set->crtc);
10433
10434                         if (intel_crtc->active && i915.fastboot) {
10435                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10436                                 config->fb_changed = true;
10437                         } else {
10438                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10439                                 config->mode_changed = true;
10440                         }
10441                 } else if (set->fb == NULL) {
10442                         config->mode_changed = true;
10443                 } else if (set->fb->pixel_format !=
10444                            set->crtc->primary->fb->pixel_format) {
10445                         config->mode_changed = true;
10446                 } else {
10447                         config->fb_changed = true;
10448                 }
10449         }
10450
10451         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10452                 config->fb_changed = true;
10453
10454         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10455                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10456                 drm_mode_debug_printmodeline(&set->crtc->mode);
10457                 drm_mode_debug_printmodeline(set->mode);
10458                 config->mode_changed = true;
10459         }
10460
10461         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10462                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10463 }
10464
10465 static int
10466 intel_modeset_stage_output_state(struct drm_device *dev,
10467                                  struct drm_mode_set *set,
10468                                  struct intel_set_config *config)
10469 {
10470         struct intel_connector *connector;
10471         struct intel_encoder *encoder;
10472         struct intel_crtc *crtc;
10473         int ro;
10474
10475         /* The upper layers ensure that we either disable a crtc or have a list
10476          * of connectors. For paranoia, double-check this. */
10477         WARN_ON(!set->fb && (set->num_connectors != 0));
10478         WARN_ON(set->fb && (set->num_connectors == 0));
10479
10480         list_for_each_entry(connector, &dev->mode_config.connector_list,
10481                             base.head) {
10482                 /* Otherwise traverse passed in connector list and get encoders
10483                  * for them. */
10484                 for (ro = 0; ro < set->num_connectors; ro++) {
10485                         if (set->connectors[ro] == &connector->base) {
10486                                 connector->new_encoder = connector->encoder;
10487                                 break;
10488                         }
10489                 }
10490
10491                 /* If we disable the crtc, disable all its connectors. Also, if
10492                  * the connector is on the changing crtc but not on the new
10493                  * connector list, disable it. */
10494                 if ((!set->fb || ro == set->num_connectors) &&
10495                     connector->base.encoder &&
10496                     connector->base.encoder->crtc == set->crtc) {
10497                         connector->new_encoder = NULL;
10498
10499                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10500                                 connector->base.base.id,
10501                                 drm_get_connector_name(&connector->base));
10502                 }
10503
10504
10505                 if (&connector->new_encoder->base != connector->base.encoder) {
10506                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10507                         config->mode_changed = true;
10508                 }
10509         }
10510         /* connector->new_encoder is now updated for all connectors. */
10511
10512         /* Update crtc of enabled connectors. */
10513         list_for_each_entry(connector, &dev->mode_config.connector_list,
10514                             base.head) {
10515                 struct drm_crtc *new_crtc;
10516
10517                 if (!connector->new_encoder)
10518                         continue;
10519
10520                 new_crtc = connector->new_encoder->base.crtc;
10521
10522                 for (ro = 0; ro < set->num_connectors; ro++) {
10523                         if (set->connectors[ro] == &connector->base)
10524                                 new_crtc = set->crtc;
10525                 }
10526
10527                 /* Make sure the new CRTC will work with the encoder */
10528                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10529                                          new_crtc)) {
10530                         return -EINVAL;
10531                 }
10532                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10533
10534                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10535                         connector->base.base.id,
10536                         drm_get_connector_name(&connector->base),
10537                         new_crtc->base.id);
10538         }
10539
10540         /* Check for any encoders that needs to be disabled. */
10541         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10542                             base.head) {
10543                 int num_connectors = 0;
10544                 list_for_each_entry(connector,
10545                                     &dev->mode_config.connector_list,
10546                                     base.head) {
10547                         if (connector->new_encoder == encoder) {
10548                                 WARN_ON(!connector->new_encoder->new_crtc);
10549                                 num_connectors++;
10550                         }
10551                 }
10552
10553                 if (num_connectors == 0)
10554                         encoder->new_crtc = NULL;
10555                 else if (num_connectors > 1)
10556                         return -EINVAL;
10557
10558                 /* Only now check for crtc changes so we don't miss encoders
10559                  * that will be disabled. */
10560                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10561                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10562                         config->mode_changed = true;
10563                 }
10564         }
10565         /* Now we've also updated encoder->new_crtc for all encoders. */
10566
10567         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10568                             base.head) {
10569                 crtc->new_enabled = false;
10570
10571                 list_for_each_entry(encoder,
10572                                     &dev->mode_config.encoder_list,
10573                                     base.head) {
10574                         if (encoder->new_crtc == crtc) {
10575                                 crtc->new_enabled = true;
10576                                 break;
10577                         }
10578                 }
10579
10580                 if (crtc->new_enabled != crtc->base.enabled) {
10581                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10582                                       crtc->new_enabled ? "en" : "dis");
10583                         config->mode_changed = true;
10584                 }
10585
10586                 if (crtc->new_enabled)
10587                         crtc->new_config = &crtc->config;
10588                 else
10589                         crtc->new_config = NULL;
10590         }
10591
10592         return 0;
10593 }
10594
10595 static void disable_crtc_nofb(struct intel_crtc *crtc)
10596 {
10597         struct drm_device *dev = crtc->base.dev;
10598         struct intel_encoder *encoder;
10599         struct intel_connector *connector;
10600
10601         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10602                       pipe_name(crtc->pipe));
10603
10604         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10605                 if (connector->new_encoder &&
10606                     connector->new_encoder->new_crtc == crtc)
10607                         connector->new_encoder = NULL;
10608         }
10609
10610         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10611                 if (encoder->new_crtc == crtc)
10612                         encoder->new_crtc = NULL;
10613         }
10614
10615         crtc->new_enabled = false;
10616         crtc->new_config = NULL;
10617 }
10618
10619 static int intel_crtc_set_config(struct drm_mode_set *set)
10620 {
10621         struct drm_device *dev;
10622         struct drm_mode_set save_set;
10623         struct intel_set_config *config;
10624         int ret;
10625
10626         BUG_ON(!set);
10627         BUG_ON(!set->crtc);
10628         BUG_ON(!set->crtc->helper_private);
10629
10630         /* Enforce sane interface api - has been abused by the fb helper. */
10631         BUG_ON(!set->mode && set->fb);
10632         BUG_ON(set->fb && set->num_connectors == 0);
10633
10634         if (set->fb) {
10635                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10636                                 set->crtc->base.id, set->fb->base.id,
10637                                 (int)set->num_connectors, set->x, set->y);
10638         } else {
10639                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10640         }
10641
10642         dev = set->crtc->dev;
10643
10644         ret = -ENOMEM;
10645         config = kzalloc(sizeof(*config), GFP_KERNEL);
10646         if (!config)
10647                 goto out_config;
10648
10649         ret = intel_set_config_save_state(dev, config);
10650         if (ret)
10651                 goto out_config;
10652
10653         save_set.crtc = set->crtc;
10654         save_set.mode = &set->crtc->mode;
10655         save_set.x = set->crtc->x;
10656         save_set.y = set->crtc->y;
10657         save_set.fb = set->crtc->primary->fb;
10658
10659         /* Compute whether we need a full modeset, only an fb base update or no
10660          * change at all. In the future we might also check whether only the
10661          * mode changed, e.g. for LVDS where we only change the panel fitter in
10662          * such cases. */
10663         intel_set_config_compute_mode_changes(set, config);
10664
10665         ret = intel_modeset_stage_output_state(dev, set, config);
10666         if (ret)
10667                 goto fail;
10668
10669         if (config->mode_changed) {
10670                 ret = intel_set_mode(set->crtc, set->mode,
10671                                      set->x, set->y, set->fb);
10672         } else if (config->fb_changed) {
10673                 intel_crtc_wait_for_pending_flips(set->crtc);
10674
10675                 ret = intel_pipe_set_base(set->crtc,
10676                                           set->x, set->y, set->fb);
10677                 /*
10678                  * In the fastboot case this may be our only check of the
10679                  * state after boot.  It would be better to only do it on
10680                  * the first update, but we don't have a nice way of doing that
10681                  * (and really, set_config isn't used much for high freq page
10682                  * flipping, so increasing its cost here shouldn't be a big
10683                  * deal).
10684                  */
10685                 if (i915.fastboot && ret == 0)
10686                         intel_modeset_check_state(set->crtc->dev);
10687         }
10688
10689         if (ret) {
10690                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10691                               set->crtc->base.id, ret);
10692 fail:
10693                 intel_set_config_restore_state(dev, config);
10694
10695                 /*
10696                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10697                  * force the pipe off to avoid oopsing in the modeset code
10698                  * due to fb==NULL. This should only happen during boot since
10699                  * we don't yet reconstruct the FB from the hardware state.
10700                  */
10701                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10702                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10703
10704                 /* Try to restore the config */
10705                 if (config->mode_changed &&
10706                     intel_set_mode(save_set.crtc, save_set.mode,
10707                                    save_set.x, save_set.y, save_set.fb))
10708                         DRM_ERROR("failed to restore config after modeset failure\n");
10709         }
10710
10711 out_config:
10712         intel_set_config_free(config);
10713         return ret;
10714 }
10715
10716 static const struct drm_crtc_funcs intel_crtc_funcs = {
10717         .cursor_set = intel_crtc_cursor_set,
10718         .cursor_move = intel_crtc_cursor_move,
10719         .gamma_set = intel_crtc_gamma_set,
10720         .set_config = intel_crtc_set_config,
10721         .destroy = intel_crtc_destroy,
10722         .page_flip = intel_crtc_page_flip,
10723 };
10724
10725 static void intel_cpu_pll_init(struct drm_device *dev)
10726 {
10727         if (HAS_DDI(dev))
10728                 intel_ddi_pll_init(dev);
10729 }
10730
10731 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10732                                       struct intel_shared_dpll *pll,
10733                                       struct intel_dpll_hw_state *hw_state)
10734 {
10735         uint32_t val;
10736
10737         val = I915_READ(PCH_DPLL(pll->id));
10738         hw_state->dpll = val;
10739         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10740         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10741
10742         return val & DPLL_VCO_ENABLE;
10743 }
10744
10745 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10746                                   struct intel_shared_dpll *pll)
10747 {
10748         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10749         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10750 }
10751
10752 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10753                                 struct intel_shared_dpll *pll)
10754 {
10755         /* PCH refclock must be enabled first */
10756         ibx_assert_pch_refclk_enabled(dev_priv);
10757
10758         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10759
10760         /* Wait for the clocks to stabilize. */
10761         POSTING_READ(PCH_DPLL(pll->id));
10762         udelay(150);
10763
10764         /* The pixel multiplier can only be updated once the
10765          * DPLL is enabled and the clocks are stable.
10766          *
10767          * So write it again.
10768          */
10769         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10770         POSTING_READ(PCH_DPLL(pll->id));
10771         udelay(200);
10772 }
10773
10774 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10775                                  struct intel_shared_dpll *pll)
10776 {
10777         struct drm_device *dev = dev_priv->dev;
10778         struct intel_crtc *crtc;
10779
10780         /* Make sure no transcoder isn't still depending on us. */
10781         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10782                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10783                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10784         }
10785
10786         I915_WRITE(PCH_DPLL(pll->id), 0);
10787         POSTING_READ(PCH_DPLL(pll->id));
10788         udelay(200);
10789 }
10790
10791 static char *ibx_pch_dpll_names[] = {
10792         "PCH DPLL A",
10793         "PCH DPLL B",
10794 };
10795
10796 static void ibx_pch_dpll_init(struct drm_device *dev)
10797 {
10798         struct drm_i915_private *dev_priv = dev->dev_private;
10799         int i;
10800
10801         dev_priv->num_shared_dpll = 2;
10802
10803         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10804                 dev_priv->shared_dplls[i].id = i;
10805                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10806                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10807                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10808                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10809                 dev_priv->shared_dplls[i].get_hw_state =
10810                         ibx_pch_dpll_get_hw_state;
10811         }
10812 }
10813
10814 static void intel_shared_dpll_init(struct drm_device *dev)
10815 {
10816         struct drm_i915_private *dev_priv = dev->dev_private;
10817
10818         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10819                 ibx_pch_dpll_init(dev);
10820         else
10821                 dev_priv->num_shared_dpll = 0;
10822
10823         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10824 }
10825
10826 static void intel_crtc_init(struct drm_device *dev, int pipe)
10827 {
10828         struct drm_i915_private *dev_priv = dev->dev_private;
10829         struct intel_crtc *intel_crtc;
10830         int i;
10831
10832         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10833         if (intel_crtc == NULL)
10834                 return;
10835
10836         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10837
10838         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10839         for (i = 0; i < 256; i++) {
10840                 intel_crtc->lut_r[i] = i;
10841                 intel_crtc->lut_g[i] = i;
10842                 intel_crtc->lut_b[i] = i;
10843         }
10844
10845         /*
10846          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10847          * is hooked to plane B. Hence we want plane A feeding pipe B.
10848          */
10849         intel_crtc->pipe = pipe;
10850         intel_crtc->plane = pipe;
10851         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10852                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10853                 intel_crtc->plane = !pipe;
10854         }
10855
10856         init_waitqueue_head(&intel_crtc->vbl_wait);
10857
10858         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10859                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10860         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10861         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10862
10863         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10864 }
10865
10866 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10867 {
10868         struct drm_encoder *encoder = connector->base.encoder;
10869
10870         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10871
10872         if (!encoder)
10873                 return INVALID_PIPE;
10874
10875         return to_intel_crtc(encoder->crtc)->pipe;
10876 }
10877
10878 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10879                                 struct drm_file *file)
10880 {
10881         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10882         struct drm_mode_object *drmmode_obj;
10883         struct intel_crtc *crtc;
10884
10885         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10886                 return -ENODEV;
10887
10888         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10889                         DRM_MODE_OBJECT_CRTC);
10890
10891         if (!drmmode_obj) {
10892                 DRM_ERROR("no such CRTC id\n");
10893                 return -ENOENT;
10894         }
10895
10896         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10897         pipe_from_crtc_id->pipe = crtc->pipe;
10898
10899         return 0;
10900 }
10901
10902 static int intel_encoder_clones(struct intel_encoder *encoder)
10903 {
10904         struct drm_device *dev = encoder->base.dev;
10905         struct intel_encoder *source_encoder;
10906         int index_mask = 0;
10907         int entry = 0;
10908
10909         list_for_each_entry(source_encoder,
10910                             &dev->mode_config.encoder_list, base.head) {
10911                 if (encoders_cloneable(encoder, source_encoder))
10912                         index_mask |= (1 << entry);
10913
10914                 entry++;
10915         }
10916
10917         return index_mask;
10918 }
10919
10920 static bool has_edp_a(struct drm_device *dev)
10921 {
10922         struct drm_i915_private *dev_priv = dev->dev_private;
10923
10924         if (!IS_MOBILE(dev))
10925                 return false;
10926
10927         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10928                 return false;
10929
10930         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10931                 return false;
10932
10933         return true;
10934 }
10935
10936 const char *intel_output_name(int output)
10937 {
10938         static const char *names[] = {
10939                 [INTEL_OUTPUT_UNUSED] = "Unused",
10940                 [INTEL_OUTPUT_ANALOG] = "Analog",
10941                 [INTEL_OUTPUT_DVO] = "DVO",
10942                 [INTEL_OUTPUT_SDVO] = "SDVO",
10943                 [INTEL_OUTPUT_LVDS] = "LVDS",
10944                 [INTEL_OUTPUT_TVOUT] = "TV",
10945                 [INTEL_OUTPUT_HDMI] = "HDMI",
10946                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10947                 [INTEL_OUTPUT_EDP] = "eDP",
10948                 [INTEL_OUTPUT_DSI] = "DSI",
10949                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10950         };
10951
10952         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10953                 return "Invalid";
10954
10955         return names[output];
10956 }
10957
10958 static void intel_setup_outputs(struct drm_device *dev)
10959 {
10960         struct drm_i915_private *dev_priv = dev->dev_private;
10961         struct intel_encoder *encoder;
10962         bool dpd_is_edp = false;
10963
10964         intel_lvds_init(dev);
10965
10966         if (!IS_ULT(dev))
10967                 intel_crt_init(dev);
10968
10969         if (HAS_DDI(dev)) {
10970                 int found;
10971
10972                 /* Haswell uses DDI functions to detect digital outputs */
10973                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10974                 /* DDI A only supports eDP */
10975                 if (found)
10976                         intel_ddi_init(dev, PORT_A);
10977
10978                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10979                  * register */
10980                 found = I915_READ(SFUSE_STRAP);
10981
10982                 if (found & SFUSE_STRAP_DDIB_DETECTED)
10983                         intel_ddi_init(dev, PORT_B);
10984                 if (found & SFUSE_STRAP_DDIC_DETECTED)
10985                         intel_ddi_init(dev, PORT_C);
10986                 if (found & SFUSE_STRAP_DDID_DETECTED)
10987                         intel_ddi_init(dev, PORT_D);
10988         } else if (HAS_PCH_SPLIT(dev)) {
10989                 int found;
10990                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10991
10992                 if (has_edp_a(dev))
10993                         intel_dp_init(dev, DP_A, PORT_A);
10994
10995                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10996                         /* PCH SDVOB multiplex with HDMIB */
10997                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
10998                         if (!found)
10999                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11000                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11001                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11002                 }
11003
11004                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11005                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11006
11007                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11008                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11009
11010                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11011                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11012
11013                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11014                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11015         } else if (IS_VALLEYVIEW(dev)) {
11016                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11017                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11018                                         PORT_B);
11019                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11020                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11021                 }
11022
11023                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11024                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11025                                         PORT_C);
11026                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11027                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11028                 }
11029
11030                 intel_dsi_init(dev);
11031         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11032                 bool found = false;
11033
11034                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11035                         DRM_DEBUG_KMS("probing SDVOB\n");
11036                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11037                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11038                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11039                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11040                         }
11041
11042                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11043                                 intel_dp_init(dev, DP_B, PORT_B);
11044                 }
11045
11046                 /* Before G4X SDVOC doesn't have its own detect register */
11047
11048                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11049                         DRM_DEBUG_KMS("probing SDVOC\n");
11050                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11051                 }
11052
11053                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11054
11055                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11056                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11057                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11058                         }
11059                         if (SUPPORTS_INTEGRATED_DP(dev))
11060                                 intel_dp_init(dev, DP_C, PORT_C);
11061                 }
11062
11063                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11064                     (I915_READ(DP_D) & DP_DETECTED))
11065                         intel_dp_init(dev, DP_D, PORT_D);
11066         } else if (IS_GEN2(dev))
11067                 intel_dvo_init(dev);
11068
11069         if (SUPPORTS_TV(dev))
11070                 intel_tv_init(dev);
11071
11072         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11073                 encoder->base.possible_crtcs = encoder->crtc_mask;
11074                 encoder->base.possible_clones =
11075                         intel_encoder_clones(encoder);
11076         }
11077
11078         intel_init_pch_refclk(dev);
11079
11080         drm_helper_move_panel_connectors_to_head(dev);
11081 }
11082
11083 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11084 {
11085         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11086
11087         drm_framebuffer_cleanup(fb);
11088         WARN_ON(!intel_fb->obj->framebuffer_references--);
11089         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11090         kfree(intel_fb);
11091 }
11092
11093 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11094                                                 struct drm_file *file,
11095                                                 unsigned int *handle)
11096 {
11097         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11098         struct drm_i915_gem_object *obj = intel_fb->obj;
11099
11100         return drm_gem_handle_create(file, &obj->base, handle);
11101 }
11102
11103 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11104         .destroy = intel_user_framebuffer_destroy,
11105         .create_handle = intel_user_framebuffer_create_handle,
11106 };
11107
11108 static int intel_framebuffer_init(struct drm_device *dev,
11109                                   struct intel_framebuffer *intel_fb,
11110                                   struct drm_mode_fb_cmd2 *mode_cmd,
11111                                   struct drm_i915_gem_object *obj)
11112 {
11113         int aligned_height;
11114         int pitch_limit;
11115         int ret;
11116
11117         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11118
11119         if (obj->tiling_mode == I915_TILING_Y) {
11120                 DRM_DEBUG("hardware does not support tiling Y\n");
11121                 return -EINVAL;
11122         }
11123
11124         if (mode_cmd->pitches[0] & 63) {
11125                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11126                           mode_cmd->pitches[0]);
11127                 return -EINVAL;
11128         }
11129
11130         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11131                 pitch_limit = 32*1024;
11132         } else if (INTEL_INFO(dev)->gen >= 4) {
11133                 if (obj->tiling_mode)
11134                         pitch_limit = 16*1024;
11135                 else
11136                         pitch_limit = 32*1024;
11137         } else if (INTEL_INFO(dev)->gen >= 3) {
11138                 if (obj->tiling_mode)
11139                         pitch_limit = 8*1024;
11140                 else
11141                         pitch_limit = 16*1024;
11142         } else
11143                 /* XXX DSPC is limited to 4k tiled */
11144                 pitch_limit = 8*1024;
11145
11146         if (mode_cmd->pitches[0] > pitch_limit) {
11147                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11148                           obj->tiling_mode ? "tiled" : "linear",
11149                           mode_cmd->pitches[0], pitch_limit);
11150                 return -EINVAL;
11151         }
11152
11153         if (obj->tiling_mode != I915_TILING_NONE &&
11154             mode_cmd->pitches[0] != obj->stride) {
11155                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11156                           mode_cmd->pitches[0], obj->stride);
11157                 return -EINVAL;
11158         }
11159
11160         /* Reject formats not supported by any plane early. */
11161         switch (mode_cmd->pixel_format) {
11162         case DRM_FORMAT_C8:
11163         case DRM_FORMAT_RGB565:
11164         case DRM_FORMAT_XRGB8888:
11165         case DRM_FORMAT_ARGB8888:
11166                 break;
11167         case DRM_FORMAT_XRGB1555:
11168         case DRM_FORMAT_ARGB1555:
11169                 if (INTEL_INFO(dev)->gen > 3) {
11170                         DRM_DEBUG("unsupported pixel format: %s\n",
11171                                   drm_get_format_name(mode_cmd->pixel_format));
11172                         return -EINVAL;
11173                 }
11174                 break;
11175         case DRM_FORMAT_XBGR8888:
11176         case DRM_FORMAT_ABGR8888:
11177         case DRM_FORMAT_XRGB2101010:
11178         case DRM_FORMAT_ARGB2101010:
11179         case DRM_FORMAT_XBGR2101010:
11180         case DRM_FORMAT_ABGR2101010:
11181                 if (INTEL_INFO(dev)->gen < 4) {
11182                         DRM_DEBUG("unsupported pixel format: %s\n",
11183                                   drm_get_format_name(mode_cmd->pixel_format));
11184                         return -EINVAL;
11185                 }
11186                 break;
11187         case DRM_FORMAT_YUYV:
11188         case DRM_FORMAT_UYVY:
11189         case DRM_FORMAT_YVYU:
11190         case DRM_FORMAT_VYUY:
11191                 if (INTEL_INFO(dev)->gen < 5) {
11192                         DRM_DEBUG("unsupported pixel format: %s\n",
11193                                   drm_get_format_name(mode_cmd->pixel_format));
11194                         return -EINVAL;
11195                 }
11196                 break;
11197         default:
11198                 DRM_DEBUG("unsupported pixel format: %s\n",
11199                           drm_get_format_name(mode_cmd->pixel_format));
11200                 return -EINVAL;
11201         }
11202
11203         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11204         if (mode_cmd->offsets[0] != 0)
11205                 return -EINVAL;
11206
11207         aligned_height = intel_align_height(dev, mode_cmd->height,
11208                                             obj->tiling_mode);
11209         /* FIXME drm helper for size checks (especially planar formats)? */
11210         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11211                 return -EINVAL;
11212
11213         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11214         intel_fb->obj = obj;
11215         intel_fb->obj->framebuffer_references++;
11216
11217         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11218         if (ret) {
11219                 DRM_ERROR("framebuffer init failed %d\n", ret);
11220                 return ret;
11221         }
11222
11223         return 0;
11224 }
11225
11226 static struct drm_framebuffer *
11227 intel_user_framebuffer_create(struct drm_device *dev,
11228                               struct drm_file *filp,
11229                               struct drm_mode_fb_cmd2 *mode_cmd)
11230 {
11231         struct drm_i915_gem_object *obj;
11232
11233         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11234                                                 mode_cmd->handles[0]));
11235         if (&obj->base == NULL)
11236                 return ERR_PTR(-ENOENT);
11237
11238         return intel_framebuffer_create(dev, mode_cmd, obj);
11239 }
11240
11241 #ifndef CONFIG_DRM_I915_FBDEV
11242 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11243 {
11244 }
11245 #endif
11246
11247 static const struct drm_mode_config_funcs intel_mode_funcs = {
11248         .fb_create = intel_user_framebuffer_create,
11249         .output_poll_changed = intel_fbdev_output_poll_changed,
11250 };
11251
11252 /* Set up chip specific display functions */
11253 static void intel_init_display(struct drm_device *dev)
11254 {
11255         struct drm_i915_private *dev_priv = dev->dev_private;
11256
11257         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11258                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11259         else if (IS_CHERRYVIEW(dev))
11260                 dev_priv->display.find_dpll = chv_find_best_dpll;
11261         else if (IS_VALLEYVIEW(dev))
11262                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11263         else if (IS_PINEVIEW(dev))
11264                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11265         else
11266                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11267
11268         if (HAS_DDI(dev)) {
11269                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11270                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11271                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11272                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11273                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11274                 dev_priv->display.off = haswell_crtc_off;
11275                 dev_priv->display.update_primary_plane =
11276                         ironlake_update_primary_plane;
11277         } else if (HAS_PCH_SPLIT(dev)) {
11278                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11279                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11280                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11281                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11282                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11283                 dev_priv->display.off = ironlake_crtc_off;
11284                 dev_priv->display.update_primary_plane =
11285                         ironlake_update_primary_plane;
11286         } else if (IS_VALLEYVIEW(dev)) {
11287                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11288                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11289                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11290                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11291                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11292                 dev_priv->display.off = i9xx_crtc_off;
11293                 dev_priv->display.update_primary_plane =
11294                         i9xx_update_primary_plane;
11295         } else {
11296                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11297                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11298                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11299                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11300                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11301                 dev_priv->display.off = i9xx_crtc_off;
11302                 dev_priv->display.update_primary_plane =
11303                         i9xx_update_primary_plane;
11304         }
11305
11306         /* Returns the core display clock speed */
11307         if (IS_VALLEYVIEW(dev))
11308                 dev_priv->display.get_display_clock_speed =
11309                         valleyview_get_display_clock_speed;
11310         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11311                 dev_priv->display.get_display_clock_speed =
11312                         i945_get_display_clock_speed;
11313         else if (IS_I915G(dev))
11314                 dev_priv->display.get_display_clock_speed =
11315                         i915_get_display_clock_speed;
11316         else if (IS_I945GM(dev) || IS_845G(dev))
11317                 dev_priv->display.get_display_clock_speed =
11318                         i9xx_misc_get_display_clock_speed;
11319         else if (IS_PINEVIEW(dev))
11320                 dev_priv->display.get_display_clock_speed =
11321                         pnv_get_display_clock_speed;
11322         else if (IS_I915GM(dev))
11323                 dev_priv->display.get_display_clock_speed =
11324                         i915gm_get_display_clock_speed;
11325         else if (IS_I865G(dev))
11326                 dev_priv->display.get_display_clock_speed =
11327                         i865_get_display_clock_speed;
11328         else if (IS_I85X(dev))
11329                 dev_priv->display.get_display_clock_speed =
11330                         i855_get_display_clock_speed;
11331         else /* 852, 830 */
11332                 dev_priv->display.get_display_clock_speed =
11333                         i830_get_display_clock_speed;
11334
11335         if (HAS_PCH_SPLIT(dev)) {
11336                 if (IS_GEN5(dev)) {
11337                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11338                         dev_priv->display.write_eld = ironlake_write_eld;
11339                 } else if (IS_GEN6(dev)) {
11340                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11341                         dev_priv->display.write_eld = ironlake_write_eld;
11342                         dev_priv->display.modeset_global_resources =
11343                                 snb_modeset_global_resources;
11344                 } else if (IS_IVYBRIDGE(dev)) {
11345                         /* FIXME: detect B0+ stepping and use auto training */
11346                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11347                         dev_priv->display.write_eld = ironlake_write_eld;
11348                         dev_priv->display.modeset_global_resources =
11349                                 ivb_modeset_global_resources;
11350                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11351                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11352                         dev_priv->display.write_eld = haswell_write_eld;
11353                         dev_priv->display.modeset_global_resources =
11354                                 haswell_modeset_global_resources;
11355                 }
11356         } else if (IS_G4X(dev)) {
11357                 dev_priv->display.write_eld = g4x_write_eld;
11358         } else if (IS_VALLEYVIEW(dev)) {
11359                 dev_priv->display.modeset_global_resources =
11360                         valleyview_modeset_global_resources;
11361                 dev_priv->display.write_eld = ironlake_write_eld;
11362         }
11363
11364         /* Default just returns -ENODEV to indicate unsupported */
11365         dev_priv->display.queue_flip = intel_default_queue_flip;
11366
11367         switch (INTEL_INFO(dev)->gen) {
11368         case 2:
11369                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11370                 break;
11371
11372         case 3:
11373                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11374                 break;
11375
11376         case 4:
11377         case 5:
11378                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11379                 break;
11380
11381         case 6:
11382                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11383                 break;
11384         case 7:
11385         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11386                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11387                 break;
11388         }
11389
11390         intel_panel_init_backlight_funcs(dev);
11391 }
11392
11393 /*
11394  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11395  * resume, or other times.  This quirk makes sure that's the case for
11396  * affected systems.
11397  */
11398 static void quirk_pipea_force(struct drm_device *dev)
11399 {
11400         struct drm_i915_private *dev_priv = dev->dev_private;
11401
11402         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11403         DRM_INFO("applying pipe a force quirk\n");
11404 }
11405
11406 /*
11407  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11408  */
11409 static void quirk_ssc_force_disable(struct drm_device *dev)
11410 {
11411         struct drm_i915_private *dev_priv = dev->dev_private;
11412         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11413         DRM_INFO("applying lvds SSC disable quirk\n");
11414 }
11415
11416 /*
11417  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11418  * brightness value
11419  */
11420 static void quirk_invert_brightness(struct drm_device *dev)
11421 {
11422         struct drm_i915_private *dev_priv = dev->dev_private;
11423         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11424         DRM_INFO("applying inverted panel brightness quirk\n");
11425 }
11426
11427 struct intel_quirk {
11428         int device;
11429         int subsystem_vendor;
11430         int subsystem_device;
11431         void (*hook)(struct drm_device *dev);
11432 };
11433
11434 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11435 struct intel_dmi_quirk {
11436         void (*hook)(struct drm_device *dev);
11437         const struct dmi_system_id (*dmi_id_list)[];
11438 };
11439
11440 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11441 {
11442         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11443         return 1;
11444 }
11445
11446 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11447         {
11448                 .dmi_id_list = &(const struct dmi_system_id[]) {
11449                         {
11450                                 .callback = intel_dmi_reverse_brightness,
11451                                 .ident = "NCR Corporation",
11452                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11453                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11454                                 },
11455                         },
11456                         { }  /* terminating entry */
11457                 },
11458                 .hook = quirk_invert_brightness,
11459         },
11460 };
11461
11462 static struct intel_quirk intel_quirks[] = {
11463         /* HP Mini needs pipe A force quirk (LP: #322104) */
11464         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11465
11466         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11467         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11468
11469         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11470         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11471
11472         /* 830 needs to leave pipe A & dpll A up */
11473         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11474
11475         /* Lenovo U160 cannot use SSC on LVDS */
11476         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11477
11478         /* Sony Vaio Y cannot use SSC on LVDS */
11479         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11480
11481         /* Acer Aspire 5734Z must invert backlight brightness */
11482         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11483
11484         /* Acer/eMachines G725 */
11485         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11486
11487         /* Acer/eMachines e725 */
11488         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11489
11490         /* Acer/Packard Bell NCL20 */
11491         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11492
11493         /* Acer Aspire 4736Z */
11494         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11495
11496         /* Acer Aspire 5336 */
11497         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11498 };
11499
11500 static void intel_init_quirks(struct drm_device *dev)
11501 {
11502         struct pci_dev *d = dev->pdev;
11503         int i;
11504
11505         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11506                 struct intel_quirk *q = &intel_quirks[i];
11507
11508                 if (d->device == q->device &&
11509                     (d->subsystem_vendor == q->subsystem_vendor ||
11510                      q->subsystem_vendor == PCI_ANY_ID) &&
11511                     (d->subsystem_device == q->subsystem_device ||
11512                      q->subsystem_device == PCI_ANY_ID))
11513                         q->hook(dev);
11514         }
11515         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11516                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11517                         intel_dmi_quirks[i].hook(dev);
11518         }
11519 }
11520
11521 /* Disable the VGA plane that we never use */
11522 static void i915_disable_vga(struct drm_device *dev)
11523 {
11524         struct drm_i915_private *dev_priv = dev->dev_private;
11525         u8 sr1;
11526         u32 vga_reg = i915_vgacntrl_reg(dev);
11527
11528         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11529         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11530         outb(SR01, VGA_SR_INDEX);
11531         sr1 = inb(VGA_SR_DATA);
11532         outb(sr1 | 1<<5, VGA_SR_DATA);
11533         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11534         udelay(300);
11535
11536         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11537         POSTING_READ(vga_reg);
11538 }
11539
11540 void intel_modeset_init_hw(struct drm_device *dev)
11541 {
11542         intel_prepare_ddi(dev);
11543
11544         intel_init_clock_gating(dev);
11545
11546         intel_reset_dpio(dev);
11547
11548         intel_enable_gt_powersave(dev);
11549 }
11550
11551 void intel_modeset_suspend_hw(struct drm_device *dev)
11552 {
11553         intel_suspend_hw(dev);
11554 }
11555
11556 void intel_modeset_init(struct drm_device *dev)
11557 {
11558         struct drm_i915_private *dev_priv = dev->dev_private;
11559         int sprite, ret;
11560         enum pipe pipe;
11561         struct intel_crtc *crtc;
11562
11563         drm_mode_config_init(dev);
11564
11565         dev->mode_config.min_width = 0;
11566         dev->mode_config.min_height = 0;
11567
11568         dev->mode_config.preferred_depth = 24;
11569         dev->mode_config.prefer_shadow = 1;
11570
11571         dev->mode_config.funcs = &intel_mode_funcs;
11572
11573         intel_init_quirks(dev);
11574
11575         intel_init_pm(dev);
11576
11577         if (INTEL_INFO(dev)->num_pipes == 0)
11578                 return;
11579
11580         intel_init_display(dev);
11581
11582         if (IS_GEN2(dev)) {
11583                 dev->mode_config.max_width = 2048;
11584                 dev->mode_config.max_height = 2048;
11585         } else if (IS_GEN3(dev)) {
11586                 dev->mode_config.max_width = 4096;
11587                 dev->mode_config.max_height = 4096;
11588         } else {
11589                 dev->mode_config.max_width = 8192;
11590                 dev->mode_config.max_height = 8192;
11591         }
11592
11593         if (IS_GEN2(dev)) {
11594                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11595                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11596         } else {
11597                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11598                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11599         }
11600
11601         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11602
11603         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11604                       INTEL_INFO(dev)->num_pipes,
11605                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11606
11607         for_each_pipe(pipe) {
11608                 intel_crtc_init(dev, pipe);
11609                 for_each_sprite(pipe, sprite) {
11610                         ret = intel_plane_init(dev, pipe, sprite);
11611                         if (ret)
11612                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11613                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11614                 }
11615         }
11616
11617         intel_init_dpio(dev);
11618         intel_reset_dpio(dev);
11619
11620         intel_cpu_pll_init(dev);
11621         intel_shared_dpll_init(dev);
11622
11623         /* Just disable it once at startup */
11624         i915_disable_vga(dev);
11625         intel_setup_outputs(dev);
11626
11627         /* Just in case the BIOS is doing something questionable. */
11628         intel_disable_fbc(dev);
11629
11630         mutex_lock(&dev->mode_config.mutex);
11631         intel_modeset_setup_hw_state(dev, false);
11632         mutex_unlock(&dev->mode_config.mutex);
11633
11634         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11635                             base.head) {
11636                 if (!crtc->active)
11637                         continue;
11638
11639                 /*
11640                  * Note that reserving the BIOS fb up front prevents us
11641                  * from stuffing other stolen allocations like the ring
11642                  * on top.  This prevents some ugliness at boot time, and
11643                  * can even allow for smooth boot transitions if the BIOS
11644                  * fb is large enough for the active pipe configuration.
11645                  */
11646                 if (dev_priv->display.get_plane_config) {
11647                         dev_priv->display.get_plane_config(crtc,
11648                                                            &crtc->plane_config);
11649                         /*
11650                          * If the fb is shared between multiple heads, we'll
11651                          * just get the first one.
11652                          */
11653                         intel_find_plane_obj(crtc, &crtc->plane_config);
11654                 }
11655         }
11656 }
11657
11658 static void
11659 intel_connector_break_all_links(struct intel_connector *connector)
11660 {
11661         connector->base.dpms = DRM_MODE_DPMS_OFF;
11662         connector->base.encoder = NULL;
11663         connector->encoder->connectors_active = false;
11664         connector->encoder->base.crtc = NULL;
11665 }
11666
11667 static void intel_enable_pipe_a(struct drm_device *dev)
11668 {
11669         struct intel_connector *connector;
11670         struct drm_connector *crt = NULL;
11671         struct intel_load_detect_pipe load_detect_temp;
11672
11673         /* We can't just switch on the pipe A, we need to set things up with a
11674          * proper mode and output configuration. As a gross hack, enable pipe A
11675          * by enabling the load detect pipe once. */
11676         list_for_each_entry(connector,
11677                             &dev->mode_config.connector_list,
11678                             base.head) {
11679                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11680                         crt = &connector->base;
11681                         break;
11682                 }
11683         }
11684
11685         if (!crt)
11686                 return;
11687
11688         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11689                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11690
11691
11692 }
11693
11694 static bool
11695 intel_check_plane_mapping(struct intel_crtc *crtc)
11696 {
11697         struct drm_device *dev = crtc->base.dev;
11698         struct drm_i915_private *dev_priv = dev->dev_private;
11699         u32 reg, val;
11700
11701         if (INTEL_INFO(dev)->num_pipes == 1)
11702                 return true;
11703
11704         reg = DSPCNTR(!crtc->plane);
11705         val = I915_READ(reg);
11706
11707         if ((val & DISPLAY_PLANE_ENABLE) &&
11708             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11709                 return false;
11710
11711         return true;
11712 }
11713
11714 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11715 {
11716         struct drm_device *dev = crtc->base.dev;
11717         struct drm_i915_private *dev_priv = dev->dev_private;
11718         u32 reg;
11719
11720         /* Clear any frame start delays used for debugging left by the BIOS */
11721         reg = PIPECONF(crtc->config.cpu_transcoder);
11722         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11723
11724         /* We need to sanitize the plane -> pipe mapping first because this will
11725          * disable the crtc (and hence change the state) if it is wrong. Note
11726          * that gen4+ has a fixed plane -> pipe mapping.  */
11727         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11728                 struct intel_connector *connector;
11729                 bool plane;
11730
11731                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11732                               crtc->base.base.id);
11733
11734                 /* Pipe has the wrong plane attached and the plane is active.
11735                  * Temporarily change the plane mapping and disable everything
11736                  * ...  */
11737                 plane = crtc->plane;
11738                 crtc->plane = !plane;
11739                 dev_priv->display.crtc_disable(&crtc->base);
11740                 crtc->plane = plane;
11741
11742                 /* ... and break all links. */
11743                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11744                                     base.head) {
11745                         if (connector->encoder->base.crtc != &crtc->base)
11746                                 continue;
11747
11748                         intel_connector_break_all_links(connector);
11749                 }
11750
11751                 WARN_ON(crtc->active);
11752                 crtc->base.enabled = false;
11753         }
11754
11755         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11756             crtc->pipe == PIPE_A && !crtc->active) {
11757                 /* BIOS forgot to enable pipe A, this mostly happens after
11758                  * resume. Force-enable the pipe to fix this, the update_dpms
11759                  * call below we restore the pipe to the right state, but leave
11760                  * the required bits on. */
11761                 intel_enable_pipe_a(dev);
11762         }
11763
11764         /* Adjust the state of the output pipe according to whether we
11765          * have active connectors/encoders. */
11766         intel_crtc_update_dpms(&crtc->base);
11767
11768         if (crtc->active != crtc->base.enabled) {
11769                 struct intel_encoder *encoder;
11770
11771                 /* This can happen either due to bugs in the get_hw_state
11772                  * functions or because the pipe is force-enabled due to the
11773                  * pipe A quirk. */
11774                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11775                               crtc->base.base.id,
11776                               crtc->base.enabled ? "enabled" : "disabled",
11777                               crtc->active ? "enabled" : "disabled");
11778
11779                 crtc->base.enabled = crtc->active;
11780
11781                 /* Because we only establish the connector -> encoder ->
11782                  * crtc links if something is active, this means the
11783                  * crtc is now deactivated. Break the links. connector
11784                  * -> encoder links are only establish when things are
11785                  *  actually up, hence no need to break them. */
11786                 WARN_ON(crtc->active);
11787
11788                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11789                         WARN_ON(encoder->connectors_active);
11790                         encoder->base.crtc = NULL;
11791                 }
11792         }
11793         if (crtc->active) {
11794                 /*
11795                  * We start out with underrun reporting disabled to avoid races.
11796                  * For correct bookkeeping mark this on active crtcs.
11797                  *
11798                  * No protection against concurrent access is required - at
11799                  * worst a fifo underrun happens which also sets this to false.
11800                  */
11801                 crtc->cpu_fifo_underrun_disabled = true;
11802                 crtc->pch_fifo_underrun_disabled = true;
11803         }
11804 }
11805
11806 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11807 {
11808         struct intel_connector *connector;
11809         struct drm_device *dev = encoder->base.dev;
11810
11811         /* We need to check both for a crtc link (meaning that the
11812          * encoder is active and trying to read from a pipe) and the
11813          * pipe itself being active. */
11814         bool has_active_crtc = encoder->base.crtc &&
11815                 to_intel_crtc(encoder->base.crtc)->active;
11816
11817         if (encoder->connectors_active && !has_active_crtc) {
11818                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11819                               encoder->base.base.id,
11820                               drm_get_encoder_name(&encoder->base));
11821
11822                 /* Connector is active, but has no active pipe. This is
11823                  * fallout from our resume register restoring. Disable
11824                  * the encoder manually again. */
11825                 if (encoder->base.crtc) {
11826                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11827                                       encoder->base.base.id,
11828                                       drm_get_encoder_name(&encoder->base));
11829                         encoder->disable(encoder);
11830                 }
11831
11832                 /* Inconsistent output/port/pipe state happens presumably due to
11833                  * a bug in one of the get_hw_state functions. Or someplace else
11834                  * in our code, like the register restore mess on resume. Clamp
11835                  * things to off as a safer default. */
11836                 list_for_each_entry(connector,
11837                                     &dev->mode_config.connector_list,
11838                                     base.head) {
11839                         if (connector->encoder != encoder)
11840                                 continue;
11841
11842                         intel_connector_break_all_links(connector);
11843                 }
11844         }
11845         /* Enabled encoders without active connectors will be fixed in
11846          * the crtc fixup. */
11847 }
11848
11849 void i915_redisable_vga_power_on(struct drm_device *dev)
11850 {
11851         struct drm_i915_private *dev_priv = dev->dev_private;
11852         u32 vga_reg = i915_vgacntrl_reg(dev);
11853
11854         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11855                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11856                 i915_disable_vga(dev);
11857         }
11858 }
11859
11860 void i915_redisable_vga(struct drm_device *dev)
11861 {
11862         struct drm_i915_private *dev_priv = dev->dev_private;
11863
11864         /* This function can be called both from intel_modeset_setup_hw_state or
11865          * at a very early point in our resume sequence, where the power well
11866          * structures are not yet restored. Since this function is at a very
11867          * paranoid "someone might have enabled VGA while we were not looking"
11868          * level, just check if the power well is enabled instead of trying to
11869          * follow the "don't touch the power well if we don't need it" policy
11870          * the rest of the driver uses. */
11871         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11872                 return;
11873
11874         i915_redisable_vga_power_on(dev);
11875 }
11876
11877 static bool primary_get_hw_state(struct intel_crtc *crtc)
11878 {
11879         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11880
11881         if (!crtc->active)
11882                 return false;
11883
11884         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11885 }
11886
11887 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11888 {
11889         struct drm_i915_private *dev_priv = dev->dev_private;
11890         enum pipe pipe;
11891         struct intel_crtc *crtc;
11892         struct intel_encoder *encoder;
11893         struct intel_connector *connector;
11894         int i;
11895
11896         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11897                             base.head) {
11898                 memset(&crtc->config, 0, sizeof(crtc->config));
11899
11900                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11901
11902                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11903                                                                  &crtc->config);
11904
11905                 crtc->base.enabled = crtc->active;
11906                 crtc->primary_enabled = primary_get_hw_state(crtc);
11907
11908                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11909                               crtc->base.base.id,
11910                               crtc->active ? "enabled" : "disabled");
11911         }
11912
11913         /* FIXME: Smash this into the new shared dpll infrastructure. */
11914         if (HAS_DDI(dev))
11915                 intel_ddi_setup_hw_pll_state(dev);
11916
11917         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11918                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11919
11920                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11921                 pll->active = 0;
11922                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11923                                     base.head) {
11924                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11925                                 pll->active++;
11926                 }
11927                 pll->refcount = pll->active;
11928
11929                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11930                               pll->name, pll->refcount, pll->on);
11931         }
11932
11933         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11934                             base.head) {
11935                 pipe = 0;
11936
11937                 if (encoder->get_hw_state(encoder, &pipe)) {
11938                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11939                         encoder->base.crtc = &crtc->base;
11940                         encoder->get_config(encoder, &crtc->config);
11941                 } else {
11942                         encoder->base.crtc = NULL;
11943                 }
11944
11945                 encoder->connectors_active = false;
11946                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11947                               encoder->base.base.id,
11948                               drm_get_encoder_name(&encoder->base),
11949                               encoder->base.crtc ? "enabled" : "disabled",
11950                               pipe_name(pipe));
11951         }
11952
11953         list_for_each_entry(connector, &dev->mode_config.connector_list,
11954                             base.head) {
11955                 if (connector->get_hw_state(connector)) {
11956                         connector->base.dpms = DRM_MODE_DPMS_ON;
11957                         connector->encoder->connectors_active = true;
11958                         connector->base.encoder = &connector->encoder->base;
11959                 } else {
11960                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11961                         connector->base.encoder = NULL;
11962                 }
11963                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11964                               connector->base.base.id,
11965                               drm_get_connector_name(&connector->base),
11966                               connector->base.encoder ? "enabled" : "disabled");
11967         }
11968 }
11969
11970 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11971  * and i915 state tracking structures. */
11972 void intel_modeset_setup_hw_state(struct drm_device *dev,
11973                                   bool force_restore)
11974 {
11975         struct drm_i915_private *dev_priv = dev->dev_private;
11976         enum pipe pipe;
11977         struct intel_crtc *crtc;
11978         struct intel_encoder *encoder;
11979         int i;
11980
11981         intel_modeset_readout_hw_state(dev);
11982
11983         /*
11984          * Now that we have the config, copy it to each CRTC struct
11985          * Note that this could go away if we move to using crtc_config
11986          * checking everywhere.
11987          */
11988         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11989                             base.head) {
11990                 if (crtc->active && i915.fastboot) {
11991                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11992                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11993                                       crtc->base.base.id);
11994                         drm_mode_debug_printmodeline(&crtc->base.mode);
11995                 }
11996         }
11997
11998         /* HW state is read out, now we need to sanitize this mess. */
11999         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12000                             base.head) {
12001                 intel_sanitize_encoder(encoder);
12002         }
12003
12004         for_each_pipe(pipe) {
12005                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12006                 intel_sanitize_crtc(crtc);
12007                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12008         }
12009
12010         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12011                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12012
12013                 if (!pll->on || pll->active)
12014                         continue;
12015
12016                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12017
12018                 pll->disable(dev_priv, pll);
12019                 pll->on = false;
12020         }
12021
12022         if (HAS_PCH_SPLIT(dev))
12023                 ilk_wm_get_hw_state(dev);
12024
12025         if (force_restore) {
12026                 i915_redisable_vga(dev);
12027
12028                 /*
12029                  * We need to use raw interfaces for restoring state to avoid
12030                  * checking (bogus) intermediate states.
12031                  */
12032                 for_each_pipe(pipe) {
12033                         struct drm_crtc *crtc =
12034                                 dev_priv->pipe_to_crtc_mapping[pipe];
12035
12036                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12037                                          crtc->primary->fb);
12038                 }
12039         } else {
12040                 intel_modeset_update_staged_output_state(dev);
12041         }
12042
12043         intel_modeset_check_state(dev);
12044 }
12045
12046 void intel_modeset_gem_init(struct drm_device *dev)
12047 {
12048         struct drm_crtc *c;
12049         struct intel_framebuffer *fb;
12050
12051         mutex_lock(&dev->struct_mutex);
12052         intel_init_gt_powersave(dev);
12053         mutex_unlock(&dev->struct_mutex);
12054
12055         intel_modeset_init_hw(dev);
12056
12057         intel_setup_overlay(dev);
12058
12059         /*
12060          * Make sure any fbs we allocated at startup are properly
12061          * pinned & fenced.  When we do the allocation it's too early
12062          * for this.
12063          */
12064         mutex_lock(&dev->struct_mutex);
12065         list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
12066                 if (!c->primary->fb)
12067                         continue;
12068
12069                 fb = to_intel_framebuffer(c->primary->fb);
12070                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12071                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12072                                   to_intel_crtc(c)->pipe);
12073                         drm_framebuffer_unreference(c->primary->fb);
12074                         c->primary->fb = NULL;
12075                 }
12076         }
12077         mutex_unlock(&dev->struct_mutex);
12078 }
12079
12080 void intel_connector_unregister(struct intel_connector *intel_connector)
12081 {
12082         struct drm_connector *connector = &intel_connector->base;
12083
12084         intel_panel_destroy_backlight(connector);
12085         drm_sysfs_connector_remove(connector);
12086 }
12087
12088 void intel_modeset_cleanup(struct drm_device *dev)
12089 {
12090         struct drm_i915_private *dev_priv = dev->dev_private;
12091         struct drm_crtc *crtc;
12092         struct drm_connector *connector;
12093
12094         /*
12095          * Interrupts and polling as the first thing to avoid creating havoc.
12096          * Too much stuff here (turning of rps, connectors, ...) would
12097          * experience fancy races otherwise.
12098          */
12099         drm_irq_uninstall(dev);
12100         cancel_work_sync(&dev_priv->hotplug_work);
12101         /*
12102          * Due to the hpd irq storm handling the hotplug work can re-arm the
12103          * poll handlers. Hence disable polling after hpd handling is shut down.
12104          */
12105         drm_kms_helper_poll_fini(dev);
12106
12107         mutex_lock(&dev->struct_mutex);
12108
12109         intel_unregister_dsm_handler();
12110
12111         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
12112                 /* Skip inactive CRTCs */
12113                 if (!crtc->primary->fb)
12114                         continue;
12115
12116                 intel_increase_pllclock(crtc);
12117         }
12118
12119         intel_disable_fbc(dev);
12120
12121         intel_disable_gt_powersave(dev);
12122
12123         ironlake_teardown_rc6(dev);
12124
12125         mutex_unlock(&dev->struct_mutex);
12126
12127         /* flush any delayed tasks or pending work */
12128         flush_scheduled_work();
12129
12130         /* destroy the backlight and sysfs files before encoders/connectors */
12131         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12132                 struct intel_connector *intel_connector;
12133
12134                 intel_connector = to_intel_connector(connector);
12135                 intel_connector->unregister(intel_connector);
12136         }
12137
12138         drm_mode_config_cleanup(dev);
12139
12140         intel_cleanup_overlay(dev);
12141
12142         mutex_lock(&dev->struct_mutex);
12143         intel_cleanup_gt_powersave(dev);
12144         mutex_unlock(&dev->struct_mutex);
12145 }
12146
12147 /*
12148  * Return which encoder is currently attached for connector.
12149  */
12150 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12151 {
12152         return &intel_attached_encoder(connector)->base;
12153 }
12154
12155 void intel_connector_attach_encoder(struct intel_connector *connector,
12156                                     struct intel_encoder *encoder)
12157 {
12158         connector->encoder = encoder;
12159         drm_mode_connector_attach_encoder(&connector->base,
12160                                           &encoder->base);
12161 }
12162
12163 /*
12164  * set vga decode state - true == enable VGA decode
12165  */
12166 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12167 {
12168         struct drm_i915_private *dev_priv = dev->dev_private;
12169         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12170         u16 gmch_ctrl;
12171
12172         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12173                 DRM_ERROR("failed to read control word\n");
12174                 return -EIO;
12175         }
12176
12177         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12178                 return 0;
12179
12180         if (state)
12181                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12182         else
12183                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12184
12185         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12186                 DRM_ERROR("failed to write control word\n");
12187                 return -EIO;
12188         }
12189
12190         return 0;
12191 }
12192
12193 struct intel_display_error_state {
12194
12195         u32 power_well_driver;
12196
12197         int num_transcoders;
12198
12199         struct intel_cursor_error_state {
12200                 u32 control;
12201                 u32 position;
12202                 u32 base;
12203                 u32 size;
12204         } cursor[I915_MAX_PIPES];
12205
12206         struct intel_pipe_error_state {
12207                 bool power_domain_on;
12208                 u32 source;
12209                 u32 stat;
12210         } pipe[I915_MAX_PIPES];
12211
12212         struct intel_plane_error_state {
12213                 u32 control;
12214                 u32 stride;
12215                 u32 size;
12216                 u32 pos;
12217                 u32 addr;
12218                 u32 surface;
12219                 u32 tile_offset;
12220         } plane[I915_MAX_PIPES];
12221
12222         struct intel_transcoder_error_state {
12223                 bool power_domain_on;
12224                 enum transcoder cpu_transcoder;
12225
12226                 u32 conf;
12227
12228                 u32 htotal;
12229                 u32 hblank;
12230                 u32 hsync;
12231                 u32 vtotal;
12232                 u32 vblank;
12233                 u32 vsync;
12234         } transcoder[4];
12235 };
12236
12237 struct intel_display_error_state *
12238 intel_display_capture_error_state(struct drm_device *dev)
12239 {
12240         struct drm_i915_private *dev_priv = dev->dev_private;
12241         struct intel_display_error_state *error;
12242         int transcoders[] = {
12243                 TRANSCODER_A,
12244                 TRANSCODER_B,
12245                 TRANSCODER_C,
12246                 TRANSCODER_EDP,
12247         };
12248         int i;
12249
12250         if (INTEL_INFO(dev)->num_pipes == 0)
12251                 return NULL;
12252
12253         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12254         if (error == NULL)
12255                 return NULL;
12256
12257         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12258                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12259
12260         for_each_pipe(i) {
12261                 error->pipe[i].power_domain_on =
12262                         intel_display_power_enabled_sw(dev_priv,
12263                                                        POWER_DOMAIN_PIPE(i));
12264                 if (!error->pipe[i].power_domain_on)
12265                         continue;
12266
12267                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
12268                         error->cursor[i].control = I915_READ(CURCNTR(i));
12269                         error->cursor[i].position = I915_READ(CURPOS(i));
12270                         error->cursor[i].base = I915_READ(CURBASE(i));
12271                 } else {
12272                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
12273                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
12274                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
12275                 }
12276
12277                 error->plane[i].control = I915_READ(DSPCNTR(i));
12278                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12279                 if (INTEL_INFO(dev)->gen <= 3) {
12280                         error->plane[i].size = I915_READ(DSPSIZE(i));
12281                         error->plane[i].pos = I915_READ(DSPPOS(i));
12282                 }
12283                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12284                         error->plane[i].addr = I915_READ(DSPADDR(i));
12285                 if (INTEL_INFO(dev)->gen >= 4) {
12286                         error->plane[i].surface = I915_READ(DSPSURF(i));
12287                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12288                 }
12289
12290                 error->pipe[i].source = I915_READ(PIPESRC(i));
12291
12292                 if (!HAS_PCH_SPLIT(dev))
12293                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12294         }
12295
12296         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12297         if (HAS_DDI(dev_priv->dev))
12298                 error->num_transcoders++; /* Account for eDP. */
12299
12300         for (i = 0; i < error->num_transcoders; i++) {
12301                 enum transcoder cpu_transcoder = transcoders[i];
12302
12303                 error->transcoder[i].power_domain_on =
12304                         intel_display_power_enabled_sw(dev_priv,
12305                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12306                 if (!error->transcoder[i].power_domain_on)
12307                         continue;
12308
12309                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12310
12311                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12312                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12313                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12314                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12315                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12316                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12317                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12318         }
12319
12320         return error;
12321 }
12322
12323 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12324
12325 void
12326 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12327                                 struct drm_device *dev,
12328                                 struct intel_display_error_state *error)
12329 {
12330         int i;
12331
12332         if (!error)
12333                 return;
12334
12335         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12336         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12337                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12338                            error->power_well_driver);
12339         for_each_pipe(i) {
12340                 err_printf(m, "Pipe [%d]:\n", i);
12341                 err_printf(m, "  Power: %s\n",
12342                            error->pipe[i].power_domain_on ? "on" : "off");
12343                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12344                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12345
12346                 err_printf(m, "Plane [%d]:\n", i);
12347                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12348                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12349                 if (INTEL_INFO(dev)->gen <= 3) {
12350                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12351                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12352                 }
12353                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12354                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12355                 if (INTEL_INFO(dev)->gen >= 4) {
12356                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12357                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12358                 }
12359
12360                 err_printf(m, "Cursor [%d]:\n", i);
12361                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12362                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12363                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12364         }
12365
12366         for (i = 0; i < error->num_transcoders; i++) {
12367                 err_printf(m, "CPU transcoder: %c\n",
12368                            transcoder_name(error->transcoder[i].cpu_transcoder));
12369                 err_printf(m, "  Power: %s\n",
12370                            error->transcoder[i].power_domain_on ? "on" : "off");
12371                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12372                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12373                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12374                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12375                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12376                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12377                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12378         }
12379 }