2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
82 static const uint32_t intel_cursor_formats[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
126 int p2_slow, p2_fast;
129 typedef struct intel_limit intel_limit_t;
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_pch_rawclk(struct drm_device *dev)
138 struct drm_i915_private *dev_priv = dev->dev_private;
140 WARN_ON(!HAS_PCH_SPLIT(dev));
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
145 /* hrawclock is 1/4 the FSB frequency */
146 int intel_hrawclk(struct drm_device *dev)
148 struct drm_i915_private *dev_priv = dev->dev_private;
151 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
152 if (IS_VALLEYVIEW(dev))
155 clkcfg = I915_READ(CLKCFG);
156 switch (clkcfg & CLKCFG_FSB_MASK) {
165 case CLKCFG_FSB_1067:
167 case CLKCFG_FSB_1333:
169 /* these two are just a guess; one of them might be right */
170 case CLKCFG_FSB_1600:
171 case CLKCFG_FSB_1600_ALT:
178 static inline u32 /* units of 100MHz */
179 intel_fdi_link_freq(struct drm_device *dev)
182 struct drm_i915_private *dev_priv = dev->dev_private;
183 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
188 static const intel_limit_t intel_limits_i8xx_dac = {
189 .dot = { .min = 25000, .max = 350000 },
190 .vco = { .min = 908000, .max = 1512000 },
191 .n = { .min = 2, .max = 16 },
192 .m = { .min = 96, .max = 140 },
193 .m1 = { .min = 18, .max = 26 },
194 .m2 = { .min = 6, .max = 16 },
195 .p = { .min = 4, .max = 128 },
196 .p1 = { .min = 2, .max = 33 },
197 .p2 = { .dot_limit = 165000,
198 .p2_slow = 4, .p2_fast = 2 },
201 static const intel_limit_t intel_limits_i8xx_dvo = {
202 .dot = { .min = 25000, .max = 350000 },
203 .vco = { .min = 908000, .max = 1512000 },
204 .n = { .min = 2, .max = 16 },
205 .m = { .min = 96, .max = 140 },
206 .m1 = { .min = 18, .max = 26 },
207 .m2 = { .min = 6, .max = 16 },
208 .p = { .min = 4, .max = 128 },
209 .p1 = { .min = 2, .max = 33 },
210 .p2 = { .dot_limit = 165000,
211 .p2_slow = 4, .p2_fast = 4 },
214 static const intel_limit_t intel_limits_i8xx_lvds = {
215 .dot = { .min = 25000, .max = 350000 },
216 .vco = { .min = 908000, .max = 1512000 },
217 .n = { .min = 2, .max = 16 },
218 .m = { .min = 96, .max = 140 },
219 .m1 = { .min = 18, .max = 26 },
220 .m2 = { .min = 6, .max = 16 },
221 .p = { .min = 4, .max = 128 },
222 .p1 = { .min = 1, .max = 6 },
223 .p2 = { .dot_limit = 165000,
224 .p2_slow = 14, .p2_fast = 7 },
227 static const intel_limit_t intel_limits_i9xx_sdvo = {
228 .dot = { .min = 20000, .max = 400000 },
229 .vco = { .min = 1400000, .max = 2800000 },
230 .n = { .min = 1, .max = 6 },
231 .m = { .min = 70, .max = 120 },
232 .m1 = { .min = 8, .max = 18 },
233 .m2 = { .min = 3, .max = 7 },
234 .p = { .min = 5, .max = 80 },
235 .p1 = { .min = 1, .max = 8 },
236 .p2 = { .dot_limit = 200000,
237 .p2_slow = 10, .p2_fast = 5 },
240 static const intel_limit_t intel_limits_i9xx_lvds = {
241 .dot = { .min = 20000, .max = 400000 },
242 .vco = { .min = 1400000, .max = 2800000 },
243 .n = { .min = 1, .max = 6 },
244 .m = { .min = 70, .max = 120 },
245 .m1 = { .min = 8, .max = 18 },
246 .m2 = { .min = 3, .max = 7 },
247 .p = { .min = 7, .max = 98 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 112000,
250 .p2_slow = 14, .p2_fast = 7 },
254 static const intel_limit_t intel_limits_g4x_sdvo = {
255 .dot = { .min = 25000, .max = 270000 },
256 .vco = { .min = 1750000, .max = 3500000},
257 .n = { .min = 1, .max = 4 },
258 .m = { .min = 104, .max = 138 },
259 .m1 = { .min = 17, .max = 23 },
260 .m2 = { .min = 5, .max = 11 },
261 .p = { .min = 10, .max = 30 },
262 .p1 = { .min = 1, .max = 3},
263 .p2 = { .dot_limit = 270000,
269 static const intel_limit_t intel_limits_g4x_hdmi = {
270 .dot = { .min = 22000, .max = 400000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 16, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8},
278 .p2 = { .dot_limit = 165000,
279 .p2_slow = 10, .p2_fast = 5 },
282 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
283 .dot = { .min = 20000, .max = 115000 },
284 .vco = { .min = 1750000, .max = 3500000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 104, .max = 138 },
287 .m1 = { .min = 17, .max = 23 },
288 .m2 = { .min = 5, .max = 11 },
289 .p = { .min = 28, .max = 112 },
290 .p1 = { .min = 2, .max = 8 },
291 .p2 = { .dot_limit = 0,
292 .p2_slow = 14, .p2_fast = 14
296 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
297 .dot = { .min = 80000, .max = 224000 },
298 .vco = { .min = 1750000, .max = 3500000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 104, .max = 138 },
301 .m1 = { .min = 17, .max = 23 },
302 .m2 = { .min = 5, .max = 11 },
303 .p = { .min = 14, .max = 42 },
304 .p1 = { .min = 2, .max = 6 },
305 .p2 = { .dot_limit = 0,
306 .p2_slow = 7, .p2_fast = 7
310 static const intel_limit_t intel_limits_pineview_sdvo = {
311 .dot = { .min = 20000, .max = 400000},
312 .vco = { .min = 1700000, .max = 3500000 },
313 /* Pineview's Ncounter is a ring counter */
314 .n = { .min = 3, .max = 6 },
315 .m = { .min = 2, .max = 256 },
316 /* Pineview only has one combined m divider, which we treat as m2. */
317 .m1 = { .min = 0, .max = 0 },
318 .m2 = { .min = 0, .max = 254 },
319 .p = { .min = 5, .max = 80 },
320 .p1 = { .min = 1, .max = 8 },
321 .p2 = { .dot_limit = 200000,
322 .p2_slow = 10, .p2_fast = 5 },
325 static const intel_limit_t intel_limits_pineview_lvds = {
326 .dot = { .min = 20000, .max = 400000 },
327 .vco = { .min = 1700000, .max = 3500000 },
328 .n = { .min = 3, .max = 6 },
329 .m = { .min = 2, .max = 256 },
330 .m1 = { .min = 0, .max = 0 },
331 .m2 = { .min = 0, .max = 254 },
332 .p = { .min = 7, .max = 112 },
333 .p1 = { .min = 1, .max = 8 },
334 .p2 = { .dot_limit = 112000,
335 .p2_slow = 14, .p2_fast = 14 },
338 /* Ironlake / Sandybridge
340 * We calculate clock using (register_value + 2) for N/M1/M2, so here
341 * the range value for them is (actual_value - 2).
343 static const intel_limit_t intel_limits_ironlake_dac = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 5 },
347 .m = { .min = 79, .max = 127 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 5, .max = 80 },
351 .p1 = { .min = 1, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 10, .p2_fast = 5 },
356 static const intel_limit_t intel_limits_ironlake_single_lvds = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 118 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 28, .max = 112 },
364 .p1 = { .min = 2, .max = 8 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 14, .p2_fast = 14 },
369 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
370 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = 1760000, .max = 3510000 },
372 .n = { .min = 1, .max = 3 },
373 .m = { .min = 79, .max = 127 },
374 .m1 = { .min = 12, .max = 22 },
375 .m2 = { .min = 5, .max = 9 },
376 .p = { .min = 14, .max = 56 },
377 .p1 = { .min = 2, .max = 8 },
378 .p2 = { .dot_limit = 225000,
379 .p2_slow = 7, .p2_fast = 7 },
382 /* LVDS 100mhz refclk limits. */
383 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
384 .dot = { .min = 25000, .max = 350000 },
385 .vco = { .min = 1760000, .max = 3510000 },
386 .n = { .min = 1, .max = 2 },
387 .m = { .min = 79, .max = 126 },
388 .m1 = { .min = 12, .max = 22 },
389 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = 28, .max = 112 },
391 .p1 = { .min = 2, .max = 8 },
392 .p2 = { .dot_limit = 225000,
393 .p2_slow = 14, .p2_fast = 14 },
396 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
397 .dot = { .min = 25000, .max = 350000 },
398 .vco = { .min = 1760000, .max = 3510000 },
399 .n = { .min = 1, .max = 3 },
400 .m = { .min = 79, .max = 126 },
401 .m1 = { .min = 12, .max = 22 },
402 .m2 = { .min = 5, .max = 9 },
403 .p = { .min = 14, .max = 42 },
404 .p1 = { .min = 2, .max = 6 },
405 .p2 = { .dot_limit = 225000,
406 .p2_slow = 7, .p2_fast = 7 },
409 static const intel_limit_t intel_limits_vlv = {
411 * These are the data rate limits (measured in fast clocks)
412 * since those are the strictest limits we have. The fast
413 * clock and actual rate limits are more relaxed, so checking
414 * them would make no difference.
416 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
417 .vco = { .min = 4000000, .max = 6000000 },
418 .n = { .min = 1, .max = 7 },
419 .m1 = { .min = 2, .max = 3 },
420 .m2 = { .min = 11, .max = 156 },
421 .p1 = { .min = 2, .max = 3 },
422 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
425 static const intel_limit_t intel_limits_chv = {
427 * These are the data rate limits (measured in fast clocks)
428 * since those are the strictest limits we have. The fast
429 * clock and actual rate limits are more relaxed, so checking
430 * them would make no difference.
432 .dot = { .min = 25000 * 5, .max = 540000 * 5},
433 .vco = { .min = 4800000, .max = 6480000 },
434 .n = { .min = 1, .max = 1 },
435 .m1 = { .min = 2, .max = 2 },
436 .m2 = { .min = 24 << 22, .max = 175 << 22 },
437 .p1 = { .min = 2, .max = 4 },
438 .p2 = { .p2_slow = 1, .p2_fast = 14 },
441 static const intel_limit_t intel_limits_bxt = {
442 /* FIXME: find real dot limits */
443 .dot = { .min = 0, .max = INT_MAX },
444 .vco = { .min = 4800000, .max = 6700000 },
445 .n = { .min = 1, .max = 1 },
446 .m1 = { .min = 2, .max = 2 },
447 /* FIXME: find real m2 limits */
448 .m2 = { .min = 2 << 22, .max = 255 << 22 },
449 .p1 = { .min = 2, .max = 4 },
450 .p2 = { .p2_slow = 1, .p2_fast = 20 },
454 needs_modeset(struct drm_crtc_state *state)
456 return drm_atomic_crtc_needs_modeset(state);
460 * Returns whether any output on the specified pipe is of the specified type
462 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
464 struct drm_device *dev = crtc->base.dev;
465 struct intel_encoder *encoder;
467 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
468 if (encoder->type == type)
475 * Returns whether any output on the specified pipe will have the specified
476 * type after a staged modeset is complete, i.e., the same as
477 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
480 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
483 struct drm_atomic_state *state = crtc_state->base.state;
484 struct drm_connector *connector;
485 struct drm_connector_state *connector_state;
486 struct intel_encoder *encoder;
487 int i, num_connectors = 0;
489 for_each_connector_in_state(state, connector, connector_state, i) {
490 if (connector_state->crtc != crtc_state->base.crtc)
495 encoder = to_intel_encoder(connector_state->best_encoder);
496 if (encoder->type == type)
500 WARN_ON(num_connectors == 0);
505 static const intel_limit_t *
506 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
508 struct drm_device *dev = crtc_state->base.crtc->dev;
509 const intel_limit_t *limit;
511 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
512 if (intel_is_dual_link_lvds(dev)) {
513 if (refclk == 100000)
514 limit = &intel_limits_ironlake_dual_lvds_100m;
516 limit = &intel_limits_ironlake_dual_lvds;
518 if (refclk == 100000)
519 limit = &intel_limits_ironlake_single_lvds_100m;
521 limit = &intel_limits_ironlake_single_lvds;
524 limit = &intel_limits_ironlake_dac;
529 static const intel_limit_t *
530 intel_g4x_limit(struct intel_crtc_state *crtc_state)
532 struct drm_device *dev = crtc_state->base.crtc->dev;
533 const intel_limit_t *limit;
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
536 if (intel_is_dual_link_lvds(dev))
537 limit = &intel_limits_g4x_dual_channel_lvds;
539 limit = &intel_limits_g4x_single_channel_lvds;
540 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
541 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
542 limit = &intel_limits_g4x_hdmi;
543 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
544 limit = &intel_limits_g4x_sdvo;
545 } else /* The option is for other outputs */
546 limit = &intel_limits_i9xx_sdvo;
551 static const intel_limit_t *
552 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
554 struct drm_device *dev = crtc_state->base.crtc->dev;
555 const intel_limit_t *limit;
558 limit = &intel_limits_bxt;
559 else if (HAS_PCH_SPLIT(dev))
560 limit = intel_ironlake_limit(crtc_state, refclk);
561 else if (IS_G4X(dev)) {
562 limit = intel_g4x_limit(crtc_state);
563 } else if (IS_PINEVIEW(dev)) {
564 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
565 limit = &intel_limits_pineview_lvds;
567 limit = &intel_limits_pineview_sdvo;
568 } else if (IS_CHERRYVIEW(dev)) {
569 limit = &intel_limits_chv;
570 } else if (IS_VALLEYVIEW(dev)) {
571 limit = &intel_limits_vlv;
572 } else if (!IS_GEN2(dev)) {
573 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
574 limit = &intel_limits_i9xx_lvds;
576 limit = &intel_limits_i9xx_sdvo;
578 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_i8xx_lvds;
580 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
581 limit = &intel_limits_i8xx_dvo;
583 limit = &intel_limits_i8xx_dac;
589 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
590 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
591 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
592 * The helpers' return value is the rate of the clock that is fed to the
593 * display engine's pipe which can be the above fast dot clock rate or a
594 * divided-down version of it.
596 /* m1 is reserved as 0 in Pineview, n is a ring counter */
597 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
599 clock->m = clock->m2 + 2;
600 clock->p = clock->p1 * clock->p2;
601 if (WARN_ON(clock->n == 0 || clock->p == 0))
603 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
604 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
611 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
614 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
616 clock->m = i9xx_dpll_compute_m(clock);
617 clock->p = clock->p1 * clock->p2;
618 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
620 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
621 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
626 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
628 clock->m = clock->m1 * clock->m2;
629 clock->p = clock->p1 * clock->p2;
630 if (WARN_ON(clock->n == 0 || clock->p == 0))
632 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
635 return clock->dot / 5;
638 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
640 clock->m = clock->m1 * clock->m2;
641 clock->p = clock->p1 * clock->p2;
642 if (WARN_ON(clock->n == 0 || clock->p == 0))
644 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
646 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
648 return clock->dot / 5;
651 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
653 * Returns whether the given set of divisors are valid for a given refclk with
654 * the given connectors.
657 static bool intel_PLL_is_valid(struct drm_device *dev,
658 const intel_limit_t *limit,
659 const intel_clock_t *clock)
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
664 INTELPllInvalid("p1 out of range\n");
665 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
666 INTELPllInvalid("m2 out of range\n");
667 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
668 INTELPllInvalid("m1 out of range\n");
670 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
671 if (clock->m1 <= clock->m2)
672 INTELPllInvalid("m1 <= m2\n");
674 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
675 if (clock->p < limit->p.min || limit->p.max < clock->p)
676 INTELPllInvalid("p out of range\n");
677 if (clock->m < limit->m.min || limit->m.max < clock->m)
678 INTELPllInvalid("m out of range\n");
681 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
682 INTELPllInvalid("vco out of range\n");
683 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
684 * connector, etc., rather than just a single range.
686 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
687 INTELPllInvalid("dot out of range\n");
693 i9xx_select_p2_div(const intel_limit_t *limit,
694 const struct intel_crtc_state *crtc_state,
697 struct drm_device *dev = crtc_state->base.crtc->dev;
699 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
701 * For LVDS just rely on its current settings for dual-channel.
702 * We haven't figured out how to reliably set up different
703 * single/dual channel state, if we even can.
705 if (intel_is_dual_link_lvds(dev))
706 return limit->p2.p2_fast;
708 return limit->p2.p2_slow;
710 if (target < limit->p2.dot_limit)
711 return limit->p2.p2_slow;
713 return limit->p2.p2_fast;
718 i9xx_find_best_dpll(const intel_limit_t *limit,
719 struct intel_crtc_state *crtc_state,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
723 struct drm_device *dev = crtc_state->base.crtc->dev;
727 memset(best_clock, 0, sizeof(*best_clock));
729 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
731 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
733 for (clock.m2 = limit->m2.min;
734 clock.m2 <= limit->m2.max; clock.m2++) {
735 if (clock.m2 >= clock.m1)
737 for (clock.n = limit->n.min;
738 clock.n <= limit->n.max; clock.n++) {
739 for (clock.p1 = limit->p1.min;
740 clock.p1 <= limit->p1.max; clock.p1++) {
743 i9xx_calc_dpll_params(refclk, &clock);
744 if (!intel_PLL_is_valid(dev, limit,
748 clock.p != match_clock->p)
751 this_err = abs(clock.dot - target);
752 if (this_err < err) {
761 return (err != target);
765 pnv_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
770 struct drm_device *dev = crtc_state->base.crtc->dev;
774 memset(best_clock, 0, sizeof(*best_clock));
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 for (clock.n = limit->n.min;
783 clock.n <= limit->n.max; clock.n++) {
784 for (clock.p1 = limit->p1.min;
785 clock.p1 <= limit->p1.max; clock.p1++) {
788 pnv_calc_dpll_params(refclk, &clock);
789 if (!intel_PLL_is_valid(dev, limit,
793 clock.p != match_clock->p)
796 this_err = abs(clock.dot - target);
797 if (this_err < err) {
806 return (err != target);
810 g4x_find_best_dpll(const intel_limit_t *limit,
811 struct intel_crtc_state *crtc_state,
812 int target, int refclk, intel_clock_t *match_clock,
813 intel_clock_t *best_clock)
815 struct drm_device *dev = crtc_state->base.crtc->dev;
819 /* approximately equals target * 0.00585 */
820 int err_most = (target >> 8) + (target >> 9);
822 memset(best_clock, 0, sizeof(*best_clock));
824 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826 max_n = limit->n.max;
827 /* based on hardware requirement, prefer smaller n to precision */
828 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
829 /* based on hardware requirement, prefere larger m1,m2 */
830 for (clock.m1 = limit->m1.max;
831 clock.m1 >= limit->m1.min; clock.m1--) {
832 for (clock.m2 = limit->m2.max;
833 clock.m2 >= limit->m2.min; clock.m2--) {
834 for (clock.p1 = limit->p1.max;
835 clock.p1 >= limit->p1.min; clock.p1--) {
838 i9xx_calc_dpll_params(refclk, &clock);
839 if (!intel_PLL_is_valid(dev, limit,
843 this_err = abs(clock.dot - target);
844 if (this_err < err_most) {
858 * Check if the calculated PLL configuration is more optimal compared to the
859 * best configuration and error found so far. Return the calculated error.
861 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
862 const intel_clock_t *calculated_clock,
863 const intel_clock_t *best_clock,
864 unsigned int best_error_ppm,
865 unsigned int *error_ppm)
868 * For CHV ignore the error and consider only the P value.
869 * Prefer a bigger P value based on HW requirements.
871 if (IS_CHERRYVIEW(dev)) {
874 return calculated_clock->p > best_clock->p;
877 if (WARN_ON_ONCE(!target_freq))
880 *error_ppm = div_u64(1000000ULL *
881 abs(target_freq - calculated_clock->dot),
884 * Prefer a better P value over a better (smaller) error if the error
885 * is small. Ensure this preference for future configurations too by
886 * setting the error to 0.
888 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
894 return *error_ppm + 10 < best_error_ppm;
898 vlv_find_best_dpll(const intel_limit_t *limit,
899 struct intel_crtc_state *crtc_state,
900 int target, int refclk, intel_clock_t *match_clock,
901 intel_clock_t *best_clock)
903 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
904 struct drm_device *dev = crtc->base.dev;
906 unsigned int bestppm = 1000000;
907 /* min update 19.2 MHz */
908 int max_n = min(limit->n.max, refclk / 19200);
911 target *= 5; /* fast clock */
913 memset(best_clock, 0, sizeof(*best_clock));
915 /* based on hardware requirement, prefer smaller n to precision */
916 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
917 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
918 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
919 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
920 clock.p = clock.p1 * clock.p2;
921 /* based on hardware requirement, prefer bigger m1,m2 values */
922 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
925 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
928 vlv_calc_dpll_params(refclk, &clock);
930 if (!intel_PLL_is_valid(dev, limit,
934 if (!vlv_PLL_is_optimal(dev, target,
952 chv_find_best_dpll(const intel_limit_t *limit,
953 struct intel_crtc_state *crtc_state,
954 int target, int refclk, intel_clock_t *match_clock,
955 intel_clock_t *best_clock)
957 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
958 struct drm_device *dev = crtc->base.dev;
959 unsigned int best_error_ppm;
964 memset(best_clock, 0, sizeof(*best_clock));
965 best_error_ppm = 1000000;
968 * Based on hardware doc, the n always set to 1, and m1 always
969 * set to 2. If requires to support 200Mhz refclk, we need to
970 * revisit this because n may not 1 anymore.
972 clock.n = 1, clock.m1 = 2;
973 target *= 5; /* fast clock */
975 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
976 for (clock.p2 = limit->p2.p2_fast;
977 clock.p2 >= limit->p2.p2_slow;
978 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
979 unsigned int error_ppm;
981 clock.p = clock.p1 * clock.p2;
983 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
984 clock.n) << 22, refclk * clock.m1);
986 if (m2 > INT_MAX/clock.m1)
991 chv_calc_dpll_params(refclk, &clock);
993 if (!intel_PLL_is_valid(dev, limit, &clock))
996 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
997 best_error_ppm, &error_ppm))
1000 *best_clock = clock;
1001 best_error_ppm = error_ppm;
1009 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1010 intel_clock_t *best_clock)
1012 int refclk = i9xx_get_refclk(crtc_state, 0);
1014 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1015 target_clock, refclk, NULL, best_clock);
1018 bool intel_crtc_active(struct drm_crtc *crtc)
1020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1022 /* Be paranoid as we can arrive here with only partial
1023 * state retrieved from the hardware during setup.
1025 * We can ditch the adjusted_mode.crtc_clock check as soon
1026 * as Haswell has gained clock readout/fastboot support.
1028 * We can ditch the crtc->primary->fb check as soon as we can
1029 * properly reconstruct framebuffers.
1031 * FIXME: The intel_crtc->active here should be switched to
1032 * crtc->state->active once we have proper CRTC states wired up
1035 return intel_crtc->active && crtc->primary->state->fb &&
1036 intel_crtc->config->base.adjusted_mode.crtc_clock;
1039 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1042 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1045 return intel_crtc->config->cpu_transcoder;
1048 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 u32 reg = PIPEDSL(pipe);
1056 line_mask = DSL_LINEMASK_GEN2;
1058 line_mask = DSL_LINEMASK_GEN3;
1060 line1 = I915_READ(reg) & line_mask;
1062 line2 = I915_READ(reg) & line_mask;
1064 return line1 == line2;
1068 * intel_wait_for_pipe_off - wait for pipe to turn off
1069 * @crtc: crtc whose pipe to wait for
1071 * After disabling a pipe, we can't wait for vblank in the usual way,
1072 * spinning on the vblank interrupt status bit, since we won't actually
1073 * see an interrupt when the pipe is disabled.
1075 * On Gen4 and above:
1076 * wait for the pipe register state bit to turn off
1079 * wait for the display line value to settle (it usually
1080 * ends up stopping at the start of the next frame).
1083 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1085 struct drm_device *dev = crtc->base.dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1088 enum pipe pipe = crtc->pipe;
1090 if (INTEL_INFO(dev)->gen >= 4) {
1091 int reg = PIPECONF(cpu_transcoder);
1093 /* Wait for the Pipe State to go off */
1094 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1096 WARN(1, "pipe_off wait timed out\n");
1098 /* Wait for the display line to settle */
1099 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1100 WARN(1, "pipe_off wait timed out\n");
1104 static const char *state_string(bool enabled)
1106 return enabled ? "on" : "off";
1109 /* Only for pre-ILK configs */
1110 void assert_pll(struct drm_i915_private *dev_priv,
1111 enum pipe pipe, bool state)
1118 val = I915_READ(reg);
1119 cur_state = !!(val & DPLL_VCO_ENABLE);
1120 I915_STATE_WARN(cur_state != state,
1121 "PLL state assertion failure (expected %s, current %s)\n",
1122 state_string(state), state_string(cur_state));
1125 /* XXX: the dsi pll is shared between MIPI DSI ports */
1126 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1131 mutex_lock(&dev_priv->sb_lock);
1132 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1133 mutex_unlock(&dev_priv->sb_lock);
1135 cur_state = val & DSI_PLL_VCO_EN;
1136 I915_STATE_WARN(cur_state != state,
1137 "DSI PLL state assertion failure (expected %s, current %s)\n",
1138 state_string(state), state_string(cur_state));
1140 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1141 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1143 struct intel_shared_dpll *
1144 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1148 if (crtc->config->shared_dpll < 0)
1151 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1155 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1156 struct intel_shared_dpll *pll,
1160 struct intel_dpll_hw_state hw_state;
1163 "asserting DPLL %s with no DPLL\n", state_string(state)))
1166 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1167 I915_STATE_WARN(cur_state != state,
1168 "%s assertion failure (expected %s, current %s)\n",
1169 pll->name, state_string(state), state_string(cur_state));
1172 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1173 enum pipe pipe, bool state)
1178 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1181 if (HAS_DDI(dev_priv->dev)) {
1182 /* DDI does not have a specific FDI_TX register */
1183 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1184 val = I915_READ(reg);
1185 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1187 reg = FDI_TX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_TX_ENABLE);
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI TX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1195 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1196 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1198 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1205 reg = FDI_RX_CTL(pipe);
1206 val = I915_READ(reg);
1207 cur_state = !!(val & FDI_RX_ENABLE);
1208 I915_STATE_WARN(cur_state != state,
1209 "FDI RX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1212 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1213 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1215 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 /* ILK FDI PLL is always enabled */
1222 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1225 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1226 if (HAS_DDI(dev_priv->dev))
1229 reg = FDI_TX_CTL(pipe);
1230 val = I915_READ(reg);
1231 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1234 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, bool state)
1241 reg = FDI_RX_CTL(pipe);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1244 I915_STATE_WARN(cur_state != state,
1245 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1246 state_string(state), state_string(cur_state));
1249 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1252 struct drm_device *dev = dev_priv->dev;
1255 enum pipe panel_pipe = PIPE_A;
1258 if (WARN_ON(HAS_DDI(dev)))
1261 if (HAS_PCH_SPLIT(dev)) {
1264 pp_reg = PCH_PP_CONTROL;
1265 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1267 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1268 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1269 panel_pipe = PIPE_B;
1270 /* XXX: else fix for eDP */
1271 } else if (IS_VALLEYVIEW(dev)) {
1272 /* presumably write lock depends on pipe, not port select */
1273 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1276 pp_reg = PP_CONTROL;
1277 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1278 panel_pipe = PIPE_B;
1281 val = I915_READ(pp_reg);
1282 if (!(val & PANEL_POWER_ON) ||
1283 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1286 I915_STATE_WARN(panel_pipe == pipe && locked,
1287 "panel assertion failure, pipe %c regs locked\n",
1291 static void assert_cursor(struct drm_i915_private *dev_priv,
1292 enum pipe pipe, bool state)
1294 struct drm_device *dev = dev_priv->dev;
1297 if (IS_845G(dev) || IS_I865G(dev))
1298 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1300 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1302 I915_STATE_WARN(cur_state != state,
1303 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1304 pipe_name(pipe), state_string(state), state_string(cur_state));
1306 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1307 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1309 void assert_pipe(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, bool state)
1315 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1318 /* if we need the pipe quirk it must be always on */
1319 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1320 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1323 if (!intel_display_power_is_enabled(dev_priv,
1324 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1327 reg = PIPECONF(cpu_transcoder);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & PIPECONF_ENABLE);
1332 I915_STATE_WARN(cur_state != state,
1333 "pipe %c assertion failure (expected %s, current %s)\n",
1334 pipe_name(pipe), state_string(state), state_string(cur_state));
1337 static void assert_plane(struct drm_i915_private *dev_priv,
1338 enum plane plane, bool state)
1344 reg = DSPCNTR(plane);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1347 I915_STATE_WARN(cur_state != state,
1348 "plane %c assertion failure (expected %s, current %s)\n",
1349 plane_name(plane), state_string(state), state_string(cur_state));
1352 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1353 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1355 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1358 struct drm_device *dev = dev_priv->dev;
1363 /* Primary planes are fixed to pipes on gen4+ */
1364 if (INTEL_INFO(dev)->gen >= 4) {
1365 reg = DSPCNTR(pipe);
1366 val = I915_READ(reg);
1367 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1368 "plane %c assertion failure, should be disabled but not\n",
1373 /* Need to check both planes against the pipe */
1374 for_each_pipe(dev_priv, i) {
1376 val = I915_READ(reg);
1377 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1378 DISPPLANE_SEL_PIPE_SHIFT;
1379 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1380 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1381 plane_name(i), pipe_name(pipe));
1385 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1388 struct drm_device *dev = dev_priv->dev;
1392 if (INTEL_INFO(dev)->gen >= 9) {
1393 for_each_sprite(dev_priv, pipe, sprite) {
1394 val = I915_READ(PLANE_CTL(pipe, sprite));
1395 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1396 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1397 sprite, pipe_name(pipe));
1399 } else if (IS_VALLEYVIEW(dev)) {
1400 for_each_sprite(dev_priv, pipe, sprite) {
1401 reg = SPCNTR(pipe, sprite);
1402 val = I915_READ(reg);
1403 I915_STATE_WARN(val & SP_ENABLE,
1404 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1405 sprite_name(pipe, sprite), pipe_name(pipe));
1407 } else if (INTEL_INFO(dev)->gen >= 7) {
1409 val = I915_READ(reg);
1410 I915_STATE_WARN(val & SPRITE_ENABLE,
1411 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1412 plane_name(pipe), pipe_name(pipe));
1413 } else if (INTEL_INFO(dev)->gen >= 5) {
1414 reg = DVSCNTR(pipe);
1415 val = I915_READ(reg);
1416 I915_STATE_WARN(val & DVS_ENABLE,
1417 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1418 plane_name(pipe), pipe_name(pipe));
1422 static void assert_vblank_disabled(struct drm_crtc *crtc)
1424 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1425 drm_crtc_vblank_put(crtc);
1428 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1433 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1435 val = I915_READ(PCH_DREF_CONTROL);
1436 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1437 DREF_SUPERSPREAD_SOURCE_MASK));
1438 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1441 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1448 reg = PCH_TRANSCONF(pipe);
1449 val = I915_READ(reg);
1450 enabled = !!(val & TRANS_ENABLE);
1451 I915_STATE_WARN(enabled,
1452 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1456 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 port_sel, u32 val)
1459 if ((val & DP_PORT_EN) == 0)
1462 if (HAS_PCH_CPT(dev_priv->dev)) {
1463 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1464 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1465 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1467 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1468 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1471 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1478 enum pipe pipe, u32 val)
1480 if ((val & SDVO_ENABLE) == 0)
1483 if (HAS_PCH_CPT(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1486 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1490 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1496 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, u32 val)
1499 if ((val & LVDS_PORT_EN) == 0)
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1506 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1513 enum pipe pipe, u32 val)
1515 if ((val & ADPA_DAC_ENABLE) == 0)
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, int reg, u32 port_sel)
1530 u32 val = I915_READ(reg);
1531 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1532 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1533 reg, pipe_name(pipe));
1535 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1536 && (val & DP_PIPEB_SELECT),
1537 "IBX PCH dp port still using transcoder B\n");
1540 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1541 enum pipe pipe, int reg)
1543 u32 val = I915_READ(reg);
1544 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1545 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1546 reg, pipe_name(pipe));
1548 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1549 && (val & SDVO_PIPE_B_SELECT),
1550 "IBX PCH hdmi port still using transcoder B\n");
1553 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1560 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1561 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1564 val = I915_READ(reg);
1565 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1566 "PCH VGA enabled on transcoder %c, should be disabled\n",
1570 val = I915_READ(reg);
1571 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1572 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1575 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1576 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1577 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1580 static void vlv_enable_pll(struct intel_crtc *crtc,
1581 const struct intel_crtc_state *pipe_config)
1583 struct drm_device *dev = crtc->base.dev;
1584 struct drm_i915_private *dev_priv = dev->dev_private;
1585 int reg = DPLL(crtc->pipe);
1586 u32 dpll = pipe_config->dpll_hw_state.dpll;
1588 assert_pipe_disabled(dev_priv, crtc->pipe);
1590 /* No really, not for ILK+ */
1591 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1593 /* PLL is protected by panel, make sure we can write it */
1594 if (IS_MOBILE(dev_priv->dev))
1595 assert_panel_unlocked(dev_priv, crtc->pipe);
1597 I915_WRITE(reg, dpll);
1601 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1602 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1604 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1605 POSTING_READ(DPLL_MD(crtc->pipe));
1607 /* We do this three times for luck */
1608 I915_WRITE(reg, dpll);
1610 udelay(150); /* wait for warmup */
1611 I915_WRITE(reg, dpll);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg, dpll);
1616 udelay(150); /* wait for warmup */
1619 static void chv_enable_pll(struct intel_crtc *crtc,
1620 const struct intel_crtc_state *pipe_config)
1622 struct drm_device *dev = crtc->base.dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 int pipe = crtc->pipe;
1625 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1628 assert_pipe_disabled(dev_priv, crtc->pipe);
1630 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1632 mutex_lock(&dev_priv->sb_lock);
1634 /* Enable back the 10bit clock to display controller */
1635 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1636 tmp |= DPIO_DCLKP_EN;
1637 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1639 mutex_unlock(&dev_priv->sb_lock);
1642 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1647 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1649 /* Check PLL is locked */
1650 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1651 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653 /* not sure when this should be written */
1654 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1655 POSTING_READ(DPLL_MD(pipe));
1658 static int intel_num_dvo_pipes(struct drm_device *dev)
1660 struct intel_crtc *crtc;
1663 for_each_intel_crtc(dev, crtc)
1664 count += crtc->base.state->active &&
1665 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1670 static void i9xx_enable_pll(struct intel_crtc *crtc)
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 int reg = DPLL(crtc->pipe);
1675 u32 dpll = crtc->config->dpll_hw_state.dpll;
1677 assert_pipe_disabled(dev_priv, crtc->pipe);
1679 /* No really, not for ILK+ */
1680 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1682 /* PLL is protected by panel, make sure we can write it */
1683 if (IS_MOBILE(dev) && !IS_I830(dev))
1684 assert_panel_unlocked(dev_priv, crtc->pipe);
1686 /* Enable DVO 2x clock on both PLLs if necessary */
1687 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1689 * It appears to be important that we don't enable this
1690 * for the current pipe before otherwise configuring the
1691 * PLL. No idea how this should be handled if multiple
1692 * DVO outputs are enabled simultaneosly.
1694 dpll |= DPLL_DVO_2X_MODE;
1695 I915_WRITE(DPLL(!crtc->pipe),
1696 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1699 /* Wait for the clocks to stabilize. */
1703 if (INTEL_INFO(dev)->gen >= 4) {
1704 I915_WRITE(DPLL_MD(crtc->pipe),
1705 crtc->config->dpll_hw_state.dpll_md);
1707 /* The pixel multiplier can only be updated once the
1708 * DPLL is enabled and the clocks are stable.
1710 * So write it again.
1712 I915_WRITE(reg, dpll);
1715 /* We do this three times for luck */
1716 I915_WRITE(reg, dpll);
1718 udelay(150); /* wait for warmup */
1719 I915_WRITE(reg, dpll);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg, dpll);
1724 udelay(150); /* wait for warmup */
1728 * i9xx_disable_pll - disable a PLL
1729 * @dev_priv: i915 private structure
1730 * @pipe: pipe PLL to disable
1732 * Disable the PLL for @pipe, making sure the pipe is off first.
1734 * Note! This is for pre-ILK only.
1736 static void i9xx_disable_pll(struct intel_crtc *crtc)
1738 struct drm_device *dev = crtc->base.dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1740 enum pipe pipe = crtc->pipe;
1742 /* Disable DVO 2x clock on both PLLs if necessary */
1744 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1745 !intel_num_dvo_pipes(dev)) {
1746 I915_WRITE(DPLL(PIPE_B),
1747 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1748 I915_WRITE(DPLL(PIPE_A),
1749 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1752 /* Don't disable pipe or pipe PLLs if needed */
1753 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1754 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1757 /* Make sure the pipe isn't still relying on us */
1758 assert_pipe_disabled(dev_priv, pipe);
1760 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1761 POSTING_READ(DPLL(pipe));
1764 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768 /* Make sure the pipe isn't still relying on us */
1769 assert_pipe_disabled(dev_priv, pipe);
1772 * Leave integrated clock source and reference clock enabled for pipe B.
1773 * The latter is needed for VGA hotplug / manual detection.
1775 val = DPLL_VGA_MODE_DIS;
1777 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1778 I915_WRITE(DPLL(pipe), val);
1779 POSTING_READ(DPLL(pipe));
1783 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1785 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1788 /* Make sure the pipe isn't still relying on us */
1789 assert_pipe_disabled(dev_priv, pipe);
1791 /* Set PLL en = 0 */
1792 val = DPLL_SSC_REF_CLK_CHV |
1793 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1795 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1796 I915_WRITE(DPLL(pipe), val);
1797 POSTING_READ(DPLL(pipe));
1799 mutex_lock(&dev_priv->sb_lock);
1801 /* Disable 10bit clock to display controller */
1802 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1803 val &= ~DPIO_DCLKP_EN;
1804 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806 mutex_unlock(&dev_priv->sb_lock);
1809 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1810 struct intel_digital_port *dport,
1811 unsigned int expected_mask)
1816 switch (dport->port) {
1818 port_mask = DPLL_PORTB_READY_MASK;
1822 port_mask = DPLL_PORTC_READY_MASK;
1824 expected_mask <<= 4;
1827 port_mask = DPLL_PORTD_READY_MASK;
1828 dpll_reg = DPIO_PHY_STATUS;
1834 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1835 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1836 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1839 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1841 struct drm_device *dev = crtc->base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1845 if (WARN_ON(pll == NULL))
1848 WARN_ON(!pll->config.crtc_mask);
1849 if (pll->active == 0) {
1850 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1852 assert_shared_dpll_disabled(dev_priv, pll);
1854 pll->mode_set(dev_priv, pll);
1859 * intel_enable_shared_dpll - enable PCH PLL
1860 * @dev_priv: i915 private structure
1861 * @pipe: pipe PLL to enable
1863 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1864 * drives the transcoder clock.
1866 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1868 struct drm_device *dev = crtc->base.dev;
1869 struct drm_i915_private *dev_priv = dev->dev_private;
1870 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1872 if (WARN_ON(pll == NULL))
1875 if (WARN_ON(pll->config.crtc_mask == 0))
1878 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1879 pll->name, pll->active, pll->on,
1880 crtc->base.base.id);
1882 if (pll->active++) {
1884 assert_shared_dpll_enabled(dev_priv, pll);
1889 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1891 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1892 pll->enable(dev_priv, pll);
1896 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1898 struct drm_device *dev = crtc->base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1902 /* PCH only available on ILK+ */
1903 if (INTEL_INFO(dev)->gen < 5)
1909 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1912 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1913 pll->name, pll->active, pll->on,
1914 crtc->base.base.id);
1916 if (WARN_ON(pll->active == 0)) {
1917 assert_shared_dpll_disabled(dev_priv, pll);
1921 assert_shared_dpll_enabled(dev_priv, pll);
1926 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1927 pll->disable(dev_priv, pll);
1930 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1933 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1936 struct drm_device *dev = dev_priv->dev;
1937 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1939 uint32_t reg, val, pipeconf_val;
1941 /* PCH only available on ILK+ */
1942 BUG_ON(!HAS_PCH_SPLIT(dev));
1944 /* Make sure PCH DPLL is enabled */
1945 assert_shared_dpll_enabled(dev_priv,
1946 intel_crtc_to_shared_dpll(intel_crtc));
1948 /* FDI must be feeding us bits for PCH ports */
1949 assert_fdi_tx_enabled(dev_priv, pipe);
1950 assert_fdi_rx_enabled(dev_priv, pipe);
1952 if (HAS_PCH_CPT(dev)) {
1953 /* Workaround: Set the timing override bit before enabling the
1954 * pch transcoder. */
1955 reg = TRANS_CHICKEN2(pipe);
1956 val = I915_READ(reg);
1957 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1958 I915_WRITE(reg, val);
1961 reg = PCH_TRANSCONF(pipe);
1962 val = I915_READ(reg);
1963 pipeconf_val = I915_READ(PIPECONF(pipe));
1965 if (HAS_PCH_IBX(dev_priv->dev)) {
1967 * Make the BPC in transcoder be consistent with
1968 * that in pipeconf reg. For HDMI we must use 8bpc
1969 * here for both 8bpc and 12bpc.
1971 val &= ~PIPECONF_BPC_MASK;
1972 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1973 val |= PIPECONF_8BPC;
1975 val |= pipeconf_val & PIPECONF_BPC_MASK;
1978 val &= ~TRANS_INTERLACE_MASK;
1979 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1980 if (HAS_PCH_IBX(dev_priv->dev) &&
1981 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1982 val |= TRANS_LEGACY_INTERLACED_ILK;
1984 val |= TRANS_INTERLACED;
1986 val |= TRANS_PROGRESSIVE;
1988 I915_WRITE(reg, val | TRANS_ENABLE);
1989 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1990 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1993 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1994 enum transcoder cpu_transcoder)
1996 u32 val, pipeconf_val;
1998 /* PCH only available on ILK+ */
1999 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2001 /* FDI must be feeding us bits for PCH ports */
2002 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2003 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2005 /* Workaround: set timing override bit. */
2006 val = I915_READ(_TRANSA_CHICKEN2);
2007 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(_TRANSA_CHICKEN2, val);
2011 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2014 PIPECONF_INTERLACED_ILK)
2015 val |= TRANS_INTERLACED;
2017 val |= TRANS_PROGRESSIVE;
2019 I915_WRITE(LPT_TRANSCONF, val);
2020 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2021 DRM_ERROR("Failed to enable PCH transcoder\n");
2024 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2027 struct drm_device *dev = dev_priv->dev;
2030 /* FDI relies on the transcoder */
2031 assert_fdi_tx_disabled(dev_priv, pipe);
2032 assert_fdi_rx_disabled(dev_priv, pipe);
2034 /* Ports must be off as well */
2035 assert_pch_ports_disabled(dev_priv, pipe);
2037 reg = PCH_TRANSCONF(pipe);
2038 val = I915_READ(reg);
2039 val &= ~TRANS_ENABLE;
2040 I915_WRITE(reg, val);
2041 /* wait for PCH transcoder off, transcoder state */
2042 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2043 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2045 if (!HAS_PCH_IBX(dev)) {
2046 /* Workaround: Clear the timing override chicken bit again. */
2047 reg = TRANS_CHICKEN2(pipe);
2048 val = I915_READ(reg);
2049 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2050 I915_WRITE(reg, val);
2054 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2058 val = I915_READ(LPT_TRANSCONF);
2059 val &= ~TRANS_ENABLE;
2060 I915_WRITE(LPT_TRANSCONF, val);
2061 /* wait for PCH transcoder off, transcoder state */
2062 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2063 DRM_ERROR("Failed to disable PCH transcoder\n");
2065 /* Workaround: clear timing override bit. */
2066 val = I915_READ(_TRANSA_CHICKEN2);
2067 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2068 I915_WRITE(_TRANSA_CHICKEN2, val);
2072 * intel_enable_pipe - enable a pipe, asserting requirements
2073 * @crtc: crtc responsible for the pipe
2075 * Enable @crtc's pipe, making sure that various hardware specific requirements
2076 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2078 static void intel_enable_pipe(struct intel_crtc *crtc)
2080 struct drm_device *dev = crtc->base.dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 enum pipe pipe = crtc->pipe;
2083 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2085 enum pipe pch_transcoder;
2089 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2091 assert_planes_disabled(dev_priv, pipe);
2092 assert_cursor_disabled(dev_priv, pipe);
2093 assert_sprites_disabled(dev_priv, pipe);
2095 if (HAS_PCH_LPT(dev_priv->dev))
2096 pch_transcoder = TRANSCODER_A;
2098 pch_transcoder = pipe;
2101 * A pipe without a PLL won't actually be able to drive bits from
2102 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2106 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2107 assert_dsi_pll_enabled(dev_priv);
2109 assert_pll_enabled(dev_priv, pipe);
2111 if (crtc->config->has_pch_encoder) {
2112 /* if driving the PCH, we need FDI enabled */
2113 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2114 assert_fdi_tx_pll_enabled(dev_priv,
2115 (enum pipe) cpu_transcoder);
2117 /* FIXME: assert CPU port conditions for SNB+ */
2120 reg = PIPECONF(cpu_transcoder);
2121 val = I915_READ(reg);
2122 if (val & PIPECONF_ENABLE) {
2123 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2124 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2128 I915_WRITE(reg, val | PIPECONF_ENABLE);
2133 * intel_disable_pipe - disable a pipe, asserting requirements
2134 * @crtc: crtc whose pipes is to be disabled
2136 * Disable the pipe of @crtc, making sure that various hardware
2137 * specific requirements are met, if applicable, e.g. plane
2138 * disabled, panel fitter off, etc.
2140 * Will wait until the pipe has shut down before returning.
2142 static void intel_disable_pipe(struct intel_crtc *crtc)
2144 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2145 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2146 enum pipe pipe = crtc->pipe;
2150 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2156 assert_planes_disabled(dev_priv, pipe);
2157 assert_cursor_disabled(dev_priv, pipe);
2158 assert_sprites_disabled(dev_priv, pipe);
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if ((val & PIPECONF_ENABLE) == 0)
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2169 if (crtc->config->double_wide)
2170 val &= ~PIPECONF_DOUBLE_WIDE;
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175 val &= ~PIPECONF_ENABLE;
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
2182 static bool need_vtd_wa(struct drm_device *dev)
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2192 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2193 uint64_t fb_format_modifier, unsigned int plane)
2195 unsigned int tile_height;
2196 uint32_t pixel_bytes;
2198 switch (fb_format_modifier) {
2199 case DRM_FORMAT_MOD_NONE:
2202 case I915_FORMAT_MOD_X_TILED:
2203 tile_height = IS_GEN2(dev) ? 16 : 8;
2205 case I915_FORMAT_MOD_Y_TILED:
2208 case I915_FORMAT_MOD_Yf_TILED:
2209 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2210 switch (pixel_bytes) {
2224 "128-bit pixels are not supported for display!");
2230 MISSING_CASE(fb_format_modifier);
2239 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2240 uint32_t pixel_format, uint64_t fb_format_modifier)
2242 return ALIGN(height, intel_tile_height(dev, pixel_format,
2243 fb_format_modifier, 0));
2247 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2248 const struct drm_plane_state *plane_state)
2250 struct intel_rotation_info *info = &view->rotation_info;
2251 unsigned int tile_height, tile_pitch;
2253 *view = i915_ggtt_view_normal;
2258 if (!intel_rotation_90_or_270(plane_state->rotation))
2261 *view = i915_ggtt_view_rotated;
2263 info->height = fb->height;
2264 info->pixel_format = fb->pixel_format;
2265 info->pitch = fb->pitches[0];
2266 info->uv_offset = fb->offsets[1];
2267 info->fb_modifier = fb->modifier[0];
2269 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2270 fb->modifier[0], 0);
2271 tile_pitch = PAGE_SIZE / tile_height;
2272 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2273 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2274 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2276 if (info->pixel_format == DRM_FORMAT_NV12) {
2277 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2278 fb->modifier[0], 1);
2279 tile_pitch = PAGE_SIZE / tile_height;
2280 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2281 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2283 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2290 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2292 if (INTEL_INFO(dev_priv)->gen >= 9)
2294 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2295 IS_VALLEYVIEW(dev_priv))
2297 else if (INTEL_INFO(dev_priv)->gen >= 4)
2304 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2305 struct drm_framebuffer *fb,
2306 const struct drm_plane_state *plane_state,
2307 struct intel_engine_cs *pipelined,
2308 struct drm_i915_gem_request **pipelined_request)
2310 struct drm_device *dev = fb->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2313 struct i915_ggtt_view view;
2317 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2319 switch (fb->modifier[0]) {
2320 case DRM_FORMAT_MOD_NONE:
2321 alignment = intel_linear_alignment(dev_priv);
2323 case I915_FORMAT_MOD_X_TILED:
2324 if (INTEL_INFO(dev)->gen >= 9)
2325 alignment = 256 * 1024;
2327 /* pin() will align the object as required by fence */
2331 case I915_FORMAT_MOD_Y_TILED:
2332 case I915_FORMAT_MOD_Yf_TILED:
2333 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2334 "Y tiling bo slipped through, driver bug!\n"))
2336 alignment = 1 * 1024 * 1024;
2339 MISSING_CASE(fb->modifier[0]);
2343 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2347 /* Note that the w/a also requires 64 PTE of padding following the
2348 * bo. We currently fill all unused PTE with the shadow page and so
2349 * we should always have valid PTE following the scanout preventing
2352 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2353 alignment = 256 * 1024;
2356 * Global gtt pte registers are special registers which actually forward
2357 * writes to a chunk of system memory. Which means that there is no risk
2358 * that the register values disappear as soon as we call
2359 * intel_runtime_pm_put(), so it is correct to wrap only the
2360 * pin/unpin/fence and not more.
2362 intel_runtime_pm_get(dev_priv);
2364 dev_priv->mm.interruptible = false;
2365 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2366 pipelined_request, &view);
2368 goto err_interruptible;
2370 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2371 * fence, whereas 965+ only requires a fence if using
2372 * framebuffer compression. For simplicity, we always install
2373 * a fence as the cost is not that onerous.
2375 ret = i915_gem_object_get_fence(obj);
2376 if (ret == -EDEADLK) {
2378 * -EDEADLK means there are no free fences
2381 * This is propagated to atomic, but it uses
2382 * -EDEADLK to force a locking recovery, so
2383 * change the returned error to -EBUSY.
2390 i915_gem_object_pin_fence(obj);
2392 dev_priv->mm.interruptible = true;
2393 intel_runtime_pm_put(dev_priv);
2397 i915_gem_object_unpin_from_display_plane(obj, &view);
2399 dev_priv->mm.interruptible = true;
2400 intel_runtime_pm_put(dev_priv);
2404 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2405 const struct drm_plane_state *plane_state)
2407 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2408 struct i915_ggtt_view view;
2411 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2413 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2414 WARN_ONCE(ret, "Couldn't get view from plane state!");
2416 i915_gem_object_unpin_fence(obj);
2417 i915_gem_object_unpin_from_display_plane(obj, &view);
2420 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2421 * is assumed to be a power-of-two. */
2422 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2424 unsigned int tiling_mode,
2428 if (tiling_mode != I915_TILING_NONE) {
2429 unsigned int tile_rows, tiles;
2434 tiles = *x / (512/cpp);
2437 return tile_rows * pitch * 8 + tiles * 4096;
2439 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2440 unsigned int offset;
2442 offset = *y * pitch + *x * cpp;
2443 *y = (offset & alignment) / pitch;
2444 *x = ((offset & alignment) - *y * pitch) / cpp;
2445 return offset & ~alignment;
2449 static int i9xx_format_to_fourcc(int format)
2452 case DISPPLANE_8BPP:
2453 return DRM_FORMAT_C8;
2454 case DISPPLANE_BGRX555:
2455 return DRM_FORMAT_XRGB1555;
2456 case DISPPLANE_BGRX565:
2457 return DRM_FORMAT_RGB565;
2459 case DISPPLANE_BGRX888:
2460 return DRM_FORMAT_XRGB8888;
2461 case DISPPLANE_RGBX888:
2462 return DRM_FORMAT_XBGR8888;
2463 case DISPPLANE_BGRX101010:
2464 return DRM_FORMAT_XRGB2101010;
2465 case DISPPLANE_RGBX101010:
2466 return DRM_FORMAT_XBGR2101010;
2470 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2473 case PLANE_CTL_FORMAT_RGB_565:
2474 return DRM_FORMAT_RGB565;
2476 case PLANE_CTL_FORMAT_XRGB_8888:
2479 return DRM_FORMAT_ABGR8888;
2481 return DRM_FORMAT_XBGR8888;
2484 return DRM_FORMAT_ARGB8888;
2486 return DRM_FORMAT_XRGB8888;
2488 case PLANE_CTL_FORMAT_XRGB_2101010:
2490 return DRM_FORMAT_XBGR2101010;
2492 return DRM_FORMAT_XRGB2101010;
2497 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2498 struct intel_initial_plane_config *plane_config)
2500 struct drm_device *dev = crtc->base.dev;
2501 struct drm_i915_gem_object *obj = NULL;
2502 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2503 struct drm_framebuffer *fb = &plane_config->fb->base;
2504 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2505 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2508 size_aligned -= base_aligned;
2510 if (plane_config->size == 0)
2513 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2520 obj->tiling_mode = plane_config->tiling;
2521 if (obj->tiling_mode == I915_TILING_X)
2522 obj->stride = fb->pitches[0];
2524 mode_cmd.pixel_format = fb->pixel_format;
2525 mode_cmd.width = fb->width;
2526 mode_cmd.height = fb->height;
2527 mode_cmd.pitches[0] = fb->pitches[0];
2528 mode_cmd.modifier[0] = fb->modifier[0];
2529 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2531 mutex_lock(&dev->struct_mutex);
2532 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2534 DRM_DEBUG_KMS("intel fb init failed\n");
2537 mutex_unlock(&dev->struct_mutex);
2539 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2543 drm_gem_object_unreference(&obj->base);
2544 mutex_unlock(&dev->struct_mutex);
2548 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2550 update_state_fb(struct drm_plane *plane)
2552 if (plane->fb == plane->state->fb)
2555 if (plane->state->fb)
2556 drm_framebuffer_unreference(plane->state->fb);
2557 plane->state->fb = plane->fb;
2558 if (plane->state->fb)
2559 drm_framebuffer_reference(plane->state->fb);
2563 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2564 struct intel_initial_plane_config *plane_config)
2566 struct drm_device *dev = intel_crtc->base.dev;
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2569 struct intel_crtc *i;
2570 struct drm_i915_gem_object *obj;
2571 struct drm_plane *primary = intel_crtc->base.primary;
2572 struct drm_plane_state *plane_state = primary->state;
2573 struct drm_framebuffer *fb;
2575 if (!plane_config->fb)
2578 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2579 fb = &plane_config->fb->base;
2583 kfree(plane_config->fb);
2586 * Failed to alloc the obj, check to see if we should share
2587 * an fb with another CRTC instead
2589 for_each_crtc(dev, c) {
2590 i = to_intel_crtc(c);
2592 if (c == &intel_crtc->base)
2598 fb = c->primary->fb;
2602 obj = intel_fb_obj(fb);
2603 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2604 drm_framebuffer_reference(fb);
2612 plane_state->src_x = plane_state->src_y = 0;
2613 plane_state->src_w = fb->width << 16;
2614 plane_state->src_h = fb->height << 16;
2616 plane_state->crtc_x = plane_state->src_y = 0;
2617 plane_state->crtc_w = fb->width;
2618 plane_state->crtc_h = fb->height;
2620 obj = intel_fb_obj(fb);
2621 if (obj->tiling_mode != I915_TILING_NONE)
2622 dev_priv->preserve_bios_swizzle = true;
2624 drm_framebuffer_reference(fb);
2625 primary->fb = primary->state->fb = fb;
2626 primary->crtc = primary->state->crtc = &intel_crtc->base;
2627 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2628 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2631 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2632 struct drm_framebuffer *fb,
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 struct drm_plane *primary = crtc->primary;
2639 bool visible = to_intel_plane_state(primary->state)->visible;
2640 struct drm_i915_gem_object *obj;
2641 int plane = intel_crtc->plane;
2642 unsigned long linear_offset;
2644 u32 reg = DSPCNTR(plane);
2647 if (!visible || !fb) {
2649 if (INTEL_INFO(dev)->gen >= 4)
2650 I915_WRITE(DSPSURF(plane), 0);
2652 I915_WRITE(DSPADDR(plane), 0);
2657 obj = intel_fb_obj(fb);
2658 if (WARN_ON(obj == NULL))
2661 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2663 dspcntr = DISPPLANE_GAMMA_ENABLE;
2665 dspcntr |= DISPLAY_PLANE_ENABLE;
2667 if (INTEL_INFO(dev)->gen < 4) {
2668 if (intel_crtc->pipe == PIPE_B)
2669 dspcntr |= DISPPLANE_SEL_PIPE_B;
2671 /* pipesrc and dspsize control the size that is scaled from,
2672 * which should always be the user's requested size.
2674 I915_WRITE(DSPSIZE(plane),
2675 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2676 (intel_crtc->config->pipe_src_w - 1));
2677 I915_WRITE(DSPPOS(plane), 0);
2678 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2679 I915_WRITE(PRIMSIZE(plane),
2680 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2681 (intel_crtc->config->pipe_src_w - 1));
2682 I915_WRITE(PRIMPOS(plane), 0);
2683 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2686 switch (fb->pixel_format) {
2688 dspcntr |= DISPPLANE_8BPP;
2690 case DRM_FORMAT_XRGB1555:
2691 dspcntr |= DISPPLANE_BGRX555;
2693 case DRM_FORMAT_RGB565:
2694 dspcntr |= DISPPLANE_BGRX565;
2696 case DRM_FORMAT_XRGB8888:
2697 dspcntr |= DISPPLANE_BGRX888;
2699 case DRM_FORMAT_XBGR8888:
2700 dspcntr |= DISPPLANE_RGBX888;
2702 case DRM_FORMAT_XRGB2101010:
2703 dspcntr |= DISPPLANE_BGRX101010;
2705 case DRM_FORMAT_XBGR2101010:
2706 dspcntr |= DISPPLANE_RGBX101010;
2712 if (INTEL_INFO(dev)->gen >= 4 &&
2713 obj->tiling_mode != I915_TILING_NONE)
2714 dspcntr |= DISPPLANE_TILED;
2717 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2719 linear_offset = y * fb->pitches[0] + x * pixel_size;
2721 if (INTEL_INFO(dev)->gen >= 4) {
2722 intel_crtc->dspaddr_offset =
2723 intel_gen4_compute_page_offset(dev_priv,
2724 &x, &y, obj->tiling_mode,
2727 linear_offset -= intel_crtc->dspaddr_offset;
2729 intel_crtc->dspaddr_offset = linear_offset;
2732 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2733 dspcntr |= DISPPLANE_ROTATE_180;
2735 x += (intel_crtc->config->pipe_src_w - 1);
2736 y += (intel_crtc->config->pipe_src_h - 1);
2738 /* Finding the last pixel of the last line of the display
2739 data and adding to linear_offset*/
2741 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2742 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2745 intel_crtc->adjusted_x = x;
2746 intel_crtc->adjusted_y = y;
2748 I915_WRITE(reg, dspcntr);
2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2761 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
2770 struct drm_i915_gem_object *obj;
2771 int plane = intel_crtc->plane;
2772 unsigned long linear_offset;
2774 u32 reg = DSPCNTR(plane);
2777 if (!visible || !fb) {
2779 I915_WRITE(DSPSURF(plane), 0);
2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2792 dspcntr |= DISPLAY_PLANE_ENABLE;
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2797 switch (fb->pixel_format) {
2799 dspcntr |= DISPPLANE_8BPP;
2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
2804 case DRM_FORMAT_XRGB8888:
2805 dspcntr |= DISPPLANE_BGRX888;
2807 case DRM_FORMAT_XBGR8888:
2808 dspcntr |= DISPPLANE_RGBX888;
2810 case DRM_FORMAT_XRGB2101010:
2811 dspcntr |= DISPPLANE_BGRX101010;
2813 case DRM_FORMAT_XBGR2101010:
2814 dspcntr |= DISPPLANE_RGBX101010;
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
2827 intel_crtc->dspaddr_offset =
2828 intel_gen4_compute_page_offset(dev_priv,
2829 &x, &y, obj->tiling_mode,
2832 linear_offset -= intel_crtc->dspaddr_offset;
2833 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2834 dspcntr |= DISPPLANE_ROTATE_180;
2836 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2837 x += (intel_crtc->config->pipe_src_w - 1);
2838 y += (intel_crtc->config->pipe_src_h - 1);
2840 /* Finding the last pixel of the last line of the display
2841 data and adding to linear_offset*/
2843 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2844 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2848 intel_crtc->adjusted_x = x;
2849 intel_crtc->adjusted_y = y;
2851 I915_WRITE(reg, dspcntr);
2853 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2854 I915_WRITE(DSPSURF(plane),
2855 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2856 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2857 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2859 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2860 I915_WRITE(DSPLINOFF(plane), linear_offset);
2865 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2866 uint32_t pixel_format)
2868 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2871 * The stride is either expressed as a multiple of 64 bytes
2872 * chunks for linear buffers or in number of tiles for tiled
2875 switch (fb_modifier) {
2876 case DRM_FORMAT_MOD_NONE:
2878 case I915_FORMAT_MOD_X_TILED:
2879 if (INTEL_INFO(dev)->gen == 2)
2882 case I915_FORMAT_MOD_Y_TILED:
2883 /* No need to check for old gens and Y tiling since this is
2884 * about the display engine and those will be blocked before
2888 case I915_FORMAT_MOD_Yf_TILED:
2889 if (bits_per_pixel == 8)
2894 MISSING_CASE(fb_modifier);
2899 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2900 struct drm_i915_gem_object *obj,
2903 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2904 struct i915_vma *vma;
2905 unsigned char *offset;
2907 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908 view = &i915_ggtt_view_rotated;
2910 vma = i915_gem_obj_to_ggtt_view(obj, view);
2911 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2915 offset = (unsigned char *)vma->node.start;
2918 offset += vma->ggtt_view.rotation_info.uv_start_page *
2922 return (unsigned long)offset;
2925 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2927 struct drm_device *dev = intel_crtc->base.dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2930 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2931 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2932 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2936 * This function detaches (aka. unbinds) unused scalers in hardware
2938 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2940 struct intel_crtc_scaler_state *scaler_state;
2943 scaler_state = &intel_crtc->config->scaler_state;
2945 /* loop through and disable scalers that aren't in use */
2946 for (i = 0; i < intel_crtc->num_scalers; i++) {
2947 if (!scaler_state->scalers[i].in_use)
2948 skl_detach_scaler(intel_crtc, i);
2952 u32 skl_plane_ctl_format(uint32_t pixel_format)
2954 switch (pixel_format) {
2956 return PLANE_CTL_FORMAT_INDEXED;
2957 case DRM_FORMAT_RGB565:
2958 return PLANE_CTL_FORMAT_RGB_565;
2959 case DRM_FORMAT_XBGR8888:
2960 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2961 case DRM_FORMAT_XRGB8888:
2962 return PLANE_CTL_FORMAT_XRGB_8888;
2964 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2965 * to be already pre-multiplied. We need to add a knob (or a different
2966 * DRM_FORMAT) for user-space to configure that.
2968 case DRM_FORMAT_ABGR8888:
2969 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971 case DRM_FORMAT_ARGB8888:
2972 return PLANE_CTL_FORMAT_XRGB_8888 |
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 case DRM_FORMAT_XRGB2101010:
2975 return PLANE_CTL_FORMAT_XRGB_2101010;
2976 case DRM_FORMAT_XBGR2101010:
2977 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2978 case DRM_FORMAT_YUYV:
2979 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2980 case DRM_FORMAT_YVYU:
2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2982 case DRM_FORMAT_UYVY:
2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2984 case DRM_FORMAT_VYUY:
2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2987 MISSING_CASE(pixel_format);
2993 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2995 switch (fb_modifier) {
2996 case DRM_FORMAT_MOD_NONE:
2998 case I915_FORMAT_MOD_X_TILED:
2999 return PLANE_CTL_TILED_X;
3000 case I915_FORMAT_MOD_Y_TILED:
3001 return PLANE_CTL_TILED_Y;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 return PLANE_CTL_TILED_YF;
3005 MISSING_CASE(fb_modifier);
3011 u32 skl_plane_ctl_rotation(unsigned int rotation)
3014 case BIT(DRM_ROTATE_0):
3017 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3018 * while i915 HW rotation is clockwise, thats why this swapping.
3020 case BIT(DRM_ROTATE_90):
3021 return PLANE_CTL_ROTATE_270;
3022 case BIT(DRM_ROTATE_180):
3023 return PLANE_CTL_ROTATE_180;
3024 case BIT(DRM_ROTATE_270):
3025 return PLANE_CTL_ROTATE_90;
3027 MISSING_CASE(rotation);
3033 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3034 struct drm_framebuffer *fb,
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040 struct drm_plane *plane = crtc->primary;
3041 bool visible = to_intel_plane_state(plane->state)->visible;
3042 struct drm_i915_gem_object *obj;
3043 int pipe = intel_crtc->pipe;
3044 u32 plane_ctl, stride_div, stride;
3045 u32 tile_height, plane_offset, plane_size;
3046 unsigned int rotation;
3047 int x_offset, y_offset;
3048 unsigned long surf_addr;
3049 struct intel_crtc_state *crtc_state = intel_crtc->config;
3050 struct intel_plane_state *plane_state;
3051 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3052 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3055 plane_state = to_intel_plane_state(plane->state);
3057 if (!visible || !fb) {
3058 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3059 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3060 POSTING_READ(PLANE_CTL(pipe, 0));
3064 plane_ctl = PLANE_CTL_ENABLE |
3065 PLANE_CTL_PIPE_GAMMA_ENABLE |
3066 PLANE_CTL_PIPE_CSC_ENABLE;
3068 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3069 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3070 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3072 rotation = plane->state->rotation;
3073 plane_ctl |= skl_plane_ctl_rotation(rotation);
3075 obj = intel_fb_obj(fb);
3076 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3078 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3081 * FIXME: intel_plane_state->src, dst aren't set when transitional
3082 * update_plane helpers are called from legacy paths.
3083 * Once full atomic crtc is available, below check can be avoided.
3085 if (drm_rect_width(&plane_state->src)) {
3086 scaler_id = plane_state->scaler_id;
3087 src_x = plane_state->src.x1 >> 16;
3088 src_y = plane_state->src.y1 >> 16;
3089 src_w = drm_rect_width(&plane_state->src) >> 16;
3090 src_h = drm_rect_height(&plane_state->src) >> 16;
3091 dst_x = plane_state->dst.x1;
3092 dst_y = plane_state->dst.y1;
3093 dst_w = drm_rect_width(&plane_state->dst);
3094 dst_h = drm_rect_height(&plane_state->dst);
3096 WARN_ON(x != src_x || y != src_y);
3098 src_w = intel_crtc->config->pipe_src_w;
3099 src_h = intel_crtc->config->pipe_src_h;
3102 if (intel_rotation_90_or_270(rotation)) {
3103 /* stride = Surface height in tiles */
3104 tile_height = intel_tile_height(dev, fb->pixel_format,
3105 fb->modifier[0], 0);
3106 stride = DIV_ROUND_UP(fb->height, tile_height);
3107 x_offset = stride * tile_height - y - src_h;
3109 plane_size = (src_w - 1) << 16 | (src_h - 1);
3111 stride = fb->pitches[0] / stride_div;
3114 plane_size = (src_h - 1) << 16 | (src_w - 1);
3116 plane_offset = y_offset << 16 | x_offset;
3118 intel_crtc->adjusted_x = x_offset;
3119 intel_crtc->adjusted_y = y_offset;
3121 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3122 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3126 if (scaler_id >= 0) {
3127 uint32_t ps_ctrl = 0;
3129 WARN_ON(!dst_w || !dst_h);
3130 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131 crtc_state->scaler_state.scalers[scaler_id].mode;
3132 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136 I915_WRITE(PLANE_POS(pipe, 0), 0);
3138 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3141 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3143 POSTING_READ(PLANE_SURF(pipe, 0));
3146 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3148 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149 int x, int y, enum mode_set_atomic state)
3151 struct drm_device *dev = crtc->dev;
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3154 if (dev_priv->fbc.disable_fbc)
3155 dev_priv->fbc.disable_fbc(dev_priv);
3157 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3162 static void intel_complete_page_flips(struct drm_device *dev)
3164 struct drm_crtc *crtc;
3166 for_each_crtc(dev, crtc) {
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168 enum plane plane = intel_crtc->plane;
3170 intel_prepare_page_flip(dev, plane);
3171 intel_finish_page_flip_plane(dev, plane);
3175 static void intel_update_primary_planes(struct drm_device *dev)
3177 struct drm_crtc *crtc;
3179 for_each_crtc(dev, crtc) {
3180 struct intel_plane *plane = to_intel_plane(crtc->primary);
3181 struct intel_plane_state *plane_state;
3183 drm_modeset_lock_crtc(crtc, &plane->base);
3185 plane_state = to_intel_plane_state(plane->base.state);
3187 if (plane_state->base.fb)
3188 plane->commit_plane(&plane->base, plane_state);
3190 drm_modeset_unlock_crtc(crtc);
3194 void intel_prepare_reset(struct drm_device *dev)
3196 /* no reset support for gen2 */
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3204 drm_modeset_lock_all(dev);
3206 * Disabling the crtcs gracefully seems nicer. Also the
3207 * g33 docs say we should at least disable all the planes.
3209 intel_display_suspend(dev);
3212 void intel_finish_reset(struct drm_device *dev)
3214 struct drm_i915_private *dev_priv = to_i915(dev);
3217 * Flips in the rings will be nuked by the reset,
3218 * so complete all pending flips so that user space
3219 * will get its events and not get stuck.
3221 intel_complete_page_flips(dev);
3223 /* no reset support for gen2 */
3227 /* reset doesn't touch the display */
3228 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3230 * Flips in the rings have been nuked by the reset,
3231 * so update the base address of all primary
3232 * planes to the the last fb to make sure we're
3233 * showing the correct fb after a reset.
3235 * FIXME: Atomic will make this obsolete since we won't schedule
3236 * CS-based flips (which might get lost in gpu resets) any more.
3238 intel_update_primary_planes(dev);
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3246 intel_runtime_pm_disable_interrupts(dev_priv);
3247 intel_runtime_pm_enable_interrupts(dev_priv);
3249 intel_modeset_init_hw(dev);
3251 spin_lock_irq(&dev_priv->irq_lock);
3252 if (dev_priv->display.hpd_irq_setup)
3253 dev_priv->display.hpd_irq_setup(dev);
3254 spin_unlock_irq(&dev_priv->irq_lock);
3256 intel_display_resume(dev);
3258 intel_hpd_init(dev_priv);
3260 drm_modeset_unlock_all(dev);
3264 intel_finish_fb(struct drm_framebuffer *old_fb)
3266 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3267 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3268 bool was_interruptible = dev_priv->mm.interruptible;
3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3282 dev_priv->mm.interruptible = false;
3283 ret = i915_gem_object_wait_rendering(obj, true);
3284 dev_priv->mm.interruptible = was_interruptible;
3289 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3300 spin_lock_irq(&dev->event_lock);
3301 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3302 spin_unlock_irq(&dev->event_lock);
3307 static void intel_update_pipe_config(struct intel_crtc *crtc,
3308 struct intel_crtc_state *old_crtc_state)
3310 struct drm_device *dev = crtc->base.dev;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 struct intel_crtc_state *pipe_config =
3313 to_intel_crtc_state(crtc->base.state);
3315 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3316 crtc->base.mode = crtc->base.state->mode;
3318 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3319 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3320 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3323 intel_set_pipe_csc(&crtc->base);
3326 * Update pipe size and adjust fitter if needed: the reason for this is
3327 * that in compute_mode_changes we check the native mode (not the pfit
3328 * mode) to see if we can flip rather than do a full mode set. In the
3329 * fastboot case, we'll flip, but if we don't update the pipesrc and
3330 * pfit state, we'll end up with a big fb scanned out into the wrong
3334 I915_WRITE(PIPESRC(crtc->pipe),
3335 ((pipe_config->pipe_src_w - 1) << 16) |
3336 (pipe_config->pipe_src_h - 1));
3338 /* on skylake this is done by detaching scalers */
3339 if (INTEL_INFO(dev)->gen >= 9) {
3340 skl_detach_scalers(crtc);
3342 if (pipe_config->pch_pfit.enabled)
3343 skylake_pfit_enable(crtc);
3344 } else if (HAS_PCH_SPLIT(dev)) {
3345 if (pipe_config->pch_pfit.enabled)
3346 ironlake_pfit_enable(crtc);
3347 else if (old_crtc_state->pch_pfit.enabled)
3348 ironlake_pfit_disable(crtc, true);
3352 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3360 /* enable normal train */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 if (IS_IVYBRIDGE(dev)) {
3364 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3370 I915_WRITE(reg, temp);
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 if (HAS_PCH_CPT(dev)) {
3375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_NONE;
3381 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3383 /* wait one idle pattern time */
3387 /* IVB wants error correction enabled */
3388 if (IS_IVYBRIDGE(dev))
3389 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390 FDI_FE_ERRC_ENABLE);
3393 /* The FDI link training functions for ILK/Ibexpeak. */
3394 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 int pipe = intel_crtc->pipe;
3400 u32 reg, temp, tries;
3402 /* FDI needs bits from pipe first */
3403 assert_pipe_enabled(dev_priv, pipe);
3405 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3407 reg = FDI_RX_IMR(pipe);
3408 temp = I915_READ(reg);
3409 temp &= ~FDI_RX_SYMBOL_LOCK;
3410 temp &= ~FDI_RX_BIT_LOCK;
3411 I915_WRITE(reg, temp);
3415 /* enable CPU FDI TX and PCH FDI RX */
3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
3418 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
3422 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3424 reg = FDI_RX_CTL(pipe);
3425 temp = I915_READ(reg);
3426 temp &= ~FDI_LINK_TRAIN_NONE;
3427 temp |= FDI_LINK_TRAIN_PATTERN_1;
3428 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3433 /* Ironlake workaround, enable clock pointer after FDI enable*/
3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436 FDI_RX_PHASE_SYNC_POINTER_EN);
3438 reg = FDI_RX_IIR(pipe);
3439 for (tries = 0; tries < 5; tries++) {
3440 temp = I915_READ(reg);
3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3443 if ((temp & FDI_RX_BIT_LOCK)) {
3444 DRM_DEBUG_KMS("FDI train 1 done.\n");
3445 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3450 DRM_ERROR("FDI train 1 fail!\n");
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 I915_WRITE(reg, temp);
3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_2;
3463 I915_WRITE(reg, temp);
3468 reg = FDI_RX_IIR(pipe);
3469 for (tries = 0; tries < 5; tries++) {
3470 temp = I915_READ(reg);
3471 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3473 if (temp & FDI_RX_SYMBOL_LOCK) {
3474 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3475 DRM_DEBUG_KMS("FDI train 2 done.\n");
3480 DRM_ERROR("FDI train 2 fail!\n");
3482 DRM_DEBUG_KMS("FDI train done\n");
3486 static const int snb_b_fdi_train_param[] = {
3487 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3493 /* The FDI link training functions for SNB/Cougarpoint. */
3494 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 int pipe = intel_crtc->pipe;
3500 u32 reg, temp, i, retry;
3502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3504 reg = FDI_RX_IMR(pipe);
3505 temp = I915_READ(reg);
3506 temp &= ~FDI_RX_SYMBOL_LOCK;
3507 temp &= ~FDI_RX_BIT_LOCK;
3508 I915_WRITE(reg, temp);
3513 /* enable CPU FDI TX and PCH FDI RX */
3514 reg = FDI_TX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3517 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3523 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3525 I915_WRITE(FDI_RX_MISC(pipe),
3526 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
3530 if (HAS_PCH_CPT(dev)) {
3531 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3542 for (i = 0; i < 4; i++) {
3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 temp |= snb_b_fdi_train_param[i];
3547 I915_WRITE(reg, temp);
3552 for (retry = 0; retry < 5; retry++) {
3553 reg = FDI_RX_IIR(pipe);
3554 temp = I915_READ(reg);
3555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556 if (temp & FDI_RX_BIT_LOCK) {
3557 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558 DRM_DEBUG_KMS("FDI train 1 done.\n");
3567 DRM_ERROR("FDI train 1 fail!\n");
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3577 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3579 I915_WRITE(reg, temp);
3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
3583 if (HAS_PCH_CPT(dev)) {
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3587 temp &= ~FDI_LINK_TRAIN_NONE;
3588 temp |= FDI_LINK_TRAIN_PATTERN_2;
3590 I915_WRITE(reg, temp);
3595 for (i = 0; i < 4; i++) {
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599 temp |= snb_b_fdi_train_param[i];
3600 I915_WRITE(reg, temp);
3605 for (retry = 0; retry < 5; retry++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609 if (temp & FDI_RX_SYMBOL_LOCK) {
3610 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611 DRM_DEBUG_KMS("FDI train 2 done.\n");
3620 DRM_ERROR("FDI train 2 fail!\n");
3622 DRM_DEBUG_KMS("FDI train done.\n");
3625 /* Manual link training for Ivy Bridge A0 parts */
3626 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp, i, j;
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3678 reg = FDI_RX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3685 udelay(1); /* should be 0.5us */
3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3699 udelay(1); /* should be 0.5us */
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717 I915_WRITE(reg, temp);
3720 udelay(2); /* should be 1.5us */
3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3734 udelay(2); /* should be 1.5us */
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3741 DRM_DEBUG_KMS("FDI train done.\n");
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3746 struct drm_device *dev = intel_crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = intel_crtc->pipe;
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3763 /* Switch from Rawclk to PCDclk */
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3788 /* Switch from PCDclk to Rawclk */
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793 /* Disable CPU FDI TX PLL */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805 /* Wait for the clocks to turn off. */
3810 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 int pipe = intel_crtc->pipe;
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(0x7 << 16);
3827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
3834 if (HAS_PCH_IBX(dev))
3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3837 /* still set train pattern 1 */
3838 reg = FDI_TX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1;
3842 I915_WRITE(reg, temp);
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp &= ~(0x07 << 16);
3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3856 I915_WRITE(reg, temp);
3862 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3864 struct intel_crtc *crtc;
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3873 for_each_intel_crtc(dev, crtc) {
3874 if (atomic_read(&crtc->unpin_work_count) == 0)
3877 if (crtc->unpin_work)
3878 intel_wait_for_vblank(dev, crtc->pipe);
3886 static void page_flip_completed(struct intel_crtc *intel_crtc)
3888 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889 struct intel_unpin_work *work = intel_crtc->unpin_work;
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3893 intel_crtc->unpin_work = NULL;
3896 drm_send_vblank_event(intel_crtc->base.dev,
3900 drm_crtc_vblank_put(&intel_crtc->base);
3902 wake_up_all(&dev_priv->pending_flip_queue);
3903 queue_work(dev_priv->wq, &work->work);
3905 trace_i915_flip_complete(intel_crtc->plane,
3906 work->pending_flip_obj);
3909 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3914 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3915 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916 !intel_crtc_has_pending_flip(crtc),
3918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920 spin_lock_irq(&dev->event_lock);
3921 if (intel_crtc->unpin_work) {
3922 WARN_ONCE(1, "Removing stuck page flip\n");
3923 page_flip_completed(intel_crtc);
3925 spin_unlock_irq(&dev->event_lock);
3928 if (crtc->primary->fb) {
3929 mutex_lock(&dev->struct_mutex);
3930 intel_finish_fb(crtc->primary->fb);
3931 mutex_unlock(&dev->struct_mutex);
3935 /* Program iCLKIP clock to the desired frequency */
3936 static void lpt_program_iclkip(struct drm_crtc *crtc)
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3941 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3944 mutex_lock(&dev_priv->sb_lock);
3946 /* It is necessary to ungate the pixclk gate prior to programming
3947 * the divisors, and gate it back when it is done.
3949 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3951 /* Disable SSCCTL */
3952 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3953 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3957 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3958 if (clock == 20000) {
3963 /* The iCLK virtual clock root frequency is in MHz,
3964 * but the adjusted_mode->crtc_clock in in KHz. To get the
3965 * divisors, it is necessary to divide one by another, so we
3966 * convert the virtual clock precision to KHz here for higher
3969 u32 iclk_virtual_root_freq = 172800 * 1000;
3970 u32 iclk_pi_range = 64;
3971 u32 desired_divisor, msb_divisor_value, pi_value;
3973 desired_divisor = (iclk_virtual_root_freq / clock);
3974 msb_divisor_value = desired_divisor / iclk_pi_range;
3975 pi_value = desired_divisor % iclk_pi_range;
3978 divsel = msb_divisor_value - 2;
3979 phaseinc = pi_value;
3982 /* This should not happen with any sane values */
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3988 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995 /* Program SSCDIVINTPHASE6 */
3996 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3997 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4003 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4005 /* Program SSCAUXDIV */
4006 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4007 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4009 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4011 /* Enable modulator and associated divider */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4013 temp &= ~SBI_SSCCTL_DISABLE;
4014 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4016 /* Wait for initialization time */
4019 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4021 mutex_unlock(&dev_priv->sb_lock);
4024 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025 enum pipe pch_transcoder)
4027 struct drm_device *dev = crtc->base.dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4031 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032 I915_READ(HTOTAL(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034 I915_READ(HBLANK(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036 I915_READ(HSYNC(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039 I915_READ(VTOTAL(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041 I915_READ(VBLANK(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043 I915_READ(VSYNC(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4048 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4053 temp = I915_READ(SOUTH_CHICKEN1);
4054 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4060 temp &= ~FDI_BC_BIFURCATION_SELECT;
4062 temp |= FDI_BC_BIFURCATION_SELECT;
4064 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4065 I915_WRITE(SOUTH_CHICKEN1, temp);
4066 POSTING_READ(SOUTH_CHICKEN1);
4069 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4071 struct drm_device *dev = intel_crtc->base.dev;
4073 switch (intel_crtc->pipe) {
4077 if (intel_crtc->config->fdi_lanes > 2)
4078 cpt_set_fdi_bc_bifurcation(dev, false);
4080 cpt_set_fdi_bc_bifurcation(dev, true);
4084 cpt_set_fdi_bc_bifurcation(dev, true);
4093 * Enable PCH resources required for PCH ports:
4095 * - FDI training & RX/TX
4096 * - update transcoder timings
4097 * - DP transcoding bits
4100 static void ironlake_pch_enable(struct drm_crtc *crtc)
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 int pipe = intel_crtc->pipe;
4108 assert_pch_transcoder_disabled(dev_priv, pipe);
4110 if (IS_IVYBRIDGE(dev))
4111 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4113 /* Write the TU size bits before fdi link training, so that error
4114 * detection works. */
4115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4118 /* For PCH output, training FDI link */
4119 dev_priv->display.fdi_link_train(crtc);
4121 /* We need to program the right clock selection before writing the pixel
4122 * mutliplier into the DPLL. */
4123 if (HAS_PCH_CPT(dev)) {
4126 temp = I915_READ(PCH_DPLL_SEL);
4127 temp |= TRANS_DPLL_ENABLE(pipe);
4128 sel = TRANS_DPLLB_SEL(pipe);
4129 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4133 I915_WRITE(PCH_DPLL_SEL, temp);
4136 /* XXX: pch pll's can be enabled any time before we enable the PCH
4137 * transcoder, and we actually should do this to not upset any PCH
4138 * transcoder that already use the clock when we share it.
4140 * Note that enable_shared_dpll tries to do the right thing, but
4141 * get_shared_dpll unconditionally resets the pll - we need that to have
4142 * the right LVDS enable sequence. */
4143 intel_enable_shared_dpll(intel_crtc);
4145 /* set transcoder timing, panel must allow it */
4146 assert_panel_unlocked(dev_priv, pipe);
4147 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4149 intel_fdi_normal_train(crtc);
4151 /* For PCH DP, enable TRANS_DP_CTL */
4152 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4153 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4154 reg = TRANS_DP_CTL(pipe);
4155 temp = I915_READ(reg);
4156 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4157 TRANS_DP_SYNC_MASK |
4159 temp |= TRANS_DP_OUTPUT_ENABLE;
4160 temp |= bpc << 9; /* same format but at 11:9 */
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4163 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4164 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4165 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4167 switch (intel_trans_dp_port_sel(crtc)) {
4169 temp |= TRANS_DP_PORT_SEL_B;
4172 temp |= TRANS_DP_PORT_SEL_C;
4175 temp |= TRANS_DP_PORT_SEL_D;
4181 I915_WRITE(reg, temp);
4184 ironlake_enable_pch_transcoder(dev_priv, pipe);
4187 static void lpt_pch_enable(struct drm_crtc *crtc)
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4192 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4194 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4196 lpt_program_iclkip(crtc);
4198 /* Set transcoder timing. */
4199 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4201 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4204 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205 struct intel_crtc_state *crtc_state)
4207 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4208 struct intel_shared_dpll *pll;
4209 struct intel_shared_dpll_config *shared_dpll;
4210 enum intel_dpll_id i;
4212 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4214 if (HAS_PCH_IBX(dev_priv->dev)) {
4215 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4216 i = (enum intel_dpll_id) crtc->pipe;
4217 pll = &dev_priv->shared_dplls[i];
4219 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220 crtc->base.base.id, pll->name);
4222 WARN_ON(shared_dpll[i].crtc_mask);
4227 if (IS_BROXTON(dev_priv->dev)) {
4228 /* PLL is attached to port in bxt */
4229 struct intel_encoder *encoder;
4230 struct intel_digital_port *intel_dig_port;
4232 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233 if (WARN_ON(!encoder))
4236 intel_dig_port = enc_to_dig_port(&encoder->base);
4237 /* 1:1 mapping between ports and PLLs */
4238 i = (enum intel_dpll_id)intel_dig_port->port;
4239 pll = &dev_priv->shared_dplls[i];
4240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241 crtc->base.base.id, pll->name);
4242 WARN_ON(shared_dpll[i].crtc_mask);
4247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248 pll = &dev_priv->shared_dplls[i];
4250 /* Only want to check enabled timings first */
4251 if (shared_dpll[i].crtc_mask == 0)
4254 if (memcmp(&crtc_state->dpll_hw_state,
4255 &shared_dpll[i].hw_state,
4256 sizeof(crtc_state->dpll_hw_state)) == 0) {
4257 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4258 crtc->base.base.id, pll->name,
4259 shared_dpll[i].crtc_mask,
4265 /* Ok no matching timings, maybe there's a free one? */
4266 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267 pll = &dev_priv->shared_dplls[i];
4268 if (shared_dpll[i].crtc_mask == 0) {
4269 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270 crtc->base.base.id, pll->name);
4278 if (shared_dpll[i].crtc_mask == 0)
4279 shared_dpll[i].hw_state =
4280 crtc_state->dpll_hw_state;
4282 crtc_state->shared_dpll = i;
4283 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284 pipe_name(crtc->pipe));
4286 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4291 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4293 struct drm_i915_private *dev_priv = to_i915(state->dev);
4294 struct intel_shared_dpll_config *shared_dpll;
4295 struct intel_shared_dpll *pll;
4296 enum intel_dpll_id i;
4298 if (!to_intel_atomic_state(state)->dpll_set)
4301 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303 pll = &dev_priv->shared_dplls[i];
4304 pll->config = shared_dpll[i];
4308 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311 int dslreg = PIPEDSL(pipe);
4314 temp = I915_READ(dslreg);
4316 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4317 if (wait_for(I915_READ(dslreg) != temp, 5))
4318 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4323 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325 int src_w, int src_h, int dst_w, int dst_h)
4327 struct intel_crtc_scaler_state *scaler_state =
4328 &crtc_state->scaler_state;
4329 struct intel_crtc *intel_crtc =
4330 to_intel_crtc(crtc_state->base.crtc);
4333 need_scaling = intel_rotation_90_or_270(rotation) ?
4334 (src_h != dst_w || src_w != dst_h):
4335 (src_w != dst_w || src_h != dst_h);
4338 * if plane is being disabled or scaler is no more required or force detach
4339 * - free scaler binded to this plane/crtc
4340 * - in order to do this, update crtc->scaler_usage
4342 * Here scaler state in crtc_state is set free so that
4343 * scaler can be assigned to other user. Actual register
4344 * update to free the scaler is done in plane/panel-fit programming.
4345 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4347 if (force_detach || !need_scaling) {
4348 if (*scaler_id >= 0) {
4349 scaler_state->scaler_users &= ~(1 << scaler_user);
4350 scaler_state->scalers[*scaler_id].in_use = 0;
4352 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354 intel_crtc->pipe, scaler_user, *scaler_id,
4355 scaler_state->scaler_users);
4362 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4365 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4367 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4368 "size is out of scaler range\n",
4369 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4373 /* mark this plane as a scaler user in crtc_state */
4374 scaler_state->scaler_users |= (1 << scaler_user);
4375 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378 scaler_state->scaler_users);
4384 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4386 * @state: crtc's scaler state
4389 * 0 - scaler_usage updated successfully
4390 * error - requested scaling cannot be supported or other error condition
4392 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4394 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4397 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4398 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4400 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4401 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4402 state->pipe_src_w, state->pipe_src_h,
4403 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4407 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4409 * @state: crtc's scaler state
4410 * @plane_state: atomic plane state to update
4413 * 0 - scaler_usage updated successfully
4414 * error - requested scaling cannot be supported or other error condition
4416 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4417 struct intel_plane_state *plane_state)
4420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4421 struct intel_plane *intel_plane =
4422 to_intel_plane(plane_state->base.plane);
4423 struct drm_framebuffer *fb = plane_state->base.fb;
4426 bool force_detach = !fb || !plane_state->visible;
4428 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4429 intel_plane->base.base.id, intel_crtc->pipe,
4430 drm_plane_index(&intel_plane->base));
4432 ret = skl_update_scaler(crtc_state, force_detach,
4433 drm_plane_index(&intel_plane->base),
4434 &plane_state->scaler_id,
4435 plane_state->base.rotation,
4436 drm_rect_width(&plane_state->src) >> 16,
4437 drm_rect_height(&plane_state->src) >> 16,
4438 drm_rect_width(&plane_state->dst),
4439 drm_rect_height(&plane_state->dst));
4441 if (ret || plane_state->scaler_id < 0)
4444 /* check colorkey */
4445 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4446 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4447 intel_plane->base.base.id);
4451 /* Check src format */
4452 switch (fb->pixel_format) {
4453 case DRM_FORMAT_RGB565:
4454 case DRM_FORMAT_XBGR8888:
4455 case DRM_FORMAT_XRGB8888:
4456 case DRM_FORMAT_ABGR8888:
4457 case DRM_FORMAT_ARGB8888:
4458 case DRM_FORMAT_XRGB2101010:
4459 case DRM_FORMAT_XBGR2101010:
4460 case DRM_FORMAT_YUYV:
4461 case DRM_FORMAT_YVYU:
4462 case DRM_FORMAT_UYVY:
4463 case DRM_FORMAT_VYUY:
4466 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4467 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4474 static void skylake_scaler_disable(struct intel_crtc *crtc)
4478 for (i = 0; i < crtc->num_scalers; i++)
4479 skl_detach_scaler(crtc, i);
4482 static void skylake_pfit_enable(struct intel_crtc *crtc)
4484 struct drm_device *dev = crtc->base.dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 int pipe = crtc->pipe;
4487 struct intel_crtc_scaler_state *scaler_state =
4488 &crtc->config->scaler_state;
4490 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4492 if (crtc->config->pch_pfit.enabled) {
4495 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4496 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4500 id = scaler_state->scaler_id;
4501 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4502 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4503 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4504 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4506 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4510 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4512 struct drm_device *dev = crtc->base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 int pipe = crtc->pipe;
4516 if (crtc->config->pch_pfit.enabled) {
4517 /* Force use of hard-coded filter coefficients
4518 * as some pre-programmed values are broken,
4521 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4522 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4523 PF_PIPE_SEL_IVB(pipe));
4525 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4526 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4527 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4531 void hsw_enable_ips(struct intel_crtc *crtc)
4533 struct drm_device *dev = crtc->base.dev;
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4536 if (!crtc->config->ips_enabled)
4539 /* We can only enable IPS after we enable a plane and wait for a vblank */
4540 intel_wait_for_vblank(dev, crtc->pipe);
4542 assert_plane_enabled(dev_priv, crtc->plane);
4543 if (IS_BROADWELL(dev)) {
4544 mutex_lock(&dev_priv->rps.hw_lock);
4545 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4546 mutex_unlock(&dev_priv->rps.hw_lock);
4547 /* Quoting Art Runyan: "its not safe to expect any particular
4548 * value in IPS_CTL bit 31 after enabling IPS through the
4549 * mailbox." Moreover, the mailbox may return a bogus state,
4550 * so we need to just enable it and continue on.
4553 I915_WRITE(IPS_CTL, IPS_ENABLE);
4554 /* The bit only becomes 1 in the next vblank, so this wait here
4555 * is essentially intel_wait_for_vblank. If we don't have this
4556 * and don't wait for vblanks until the end of crtc_enable, then
4557 * the HW state readout code will complain that the expected
4558 * IPS_CTL value is not the one we read. */
4559 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4560 DRM_ERROR("Timed out waiting for IPS enable\n");
4564 void hsw_disable_ips(struct intel_crtc *crtc)
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4569 if (!crtc->config->ips_enabled)
4572 assert_plane_enabled(dev_priv, crtc->plane);
4573 if (IS_BROADWELL(dev)) {
4574 mutex_lock(&dev_priv->rps.hw_lock);
4575 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4576 mutex_unlock(&dev_priv->rps.hw_lock);
4577 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4578 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4579 DRM_ERROR("Timed out waiting for IPS disable\n");
4581 I915_WRITE(IPS_CTL, 0);
4582 POSTING_READ(IPS_CTL);
4585 /* We need to wait for a vblank before we can disable the plane. */
4586 intel_wait_for_vblank(dev, crtc->pipe);
4589 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4590 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4592 struct drm_device *dev = crtc->dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4595 enum pipe pipe = intel_crtc->pipe;
4597 bool reenable_ips = false;
4599 /* The clocks have to be on to load the palette. */
4600 if (!crtc->state->active)
4603 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4604 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4605 assert_dsi_pll_enabled(dev_priv);
4607 assert_pll_enabled(dev_priv, pipe);
4610 /* Workaround : Do not read or write the pipe palette/gamma data while
4611 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4613 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4614 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4615 GAMMA_MODE_MODE_SPLIT)) {
4616 hsw_disable_ips(intel_crtc);
4617 reenable_ips = true;
4620 for (i = 0; i < 256; i++) {
4623 if (HAS_GMCH_DISPLAY(dev))
4624 palreg = PALETTE(pipe, i);
4626 palreg = LGC_PALETTE(pipe, i);
4629 (intel_crtc->lut_r[i] << 16) |
4630 (intel_crtc->lut_g[i] << 8) |
4631 intel_crtc->lut_b[i]);
4635 hsw_enable_ips(intel_crtc);
4638 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4640 if (intel_crtc->overlay) {
4641 struct drm_device *dev = intel_crtc->base.dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4644 mutex_lock(&dev->struct_mutex);
4645 dev_priv->mm.interruptible = false;
4646 (void) intel_overlay_switch_off(intel_crtc->overlay);
4647 dev_priv->mm.interruptible = true;
4648 mutex_unlock(&dev->struct_mutex);
4651 /* Let userspace switch the overlay on again. In most cases userspace
4652 * has to recompute where to put it anyway.
4657 * intel_post_enable_primary - Perform operations after enabling primary plane
4658 * @crtc: the CRTC whose primary plane was just enabled
4660 * Performs potentially sleeping operations that must be done after the primary
4661 * plane is enabled, such as updating FBC and IPS. Note that this may be
4662 * called due to an explicit primary plane update, or due to an implicit
4663 * re-enable that is caused when a sprite plane is updated to no longer
4664 * completely hide the primary plane.
4667 intel_post_enable_primary(struct drm_crtc *crtc)
4669 struct drm_device *dev = crtc->dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672 int pipe = intel_crtc->pipe;
4675 * BDW signals flip done immediately if the plane
4676 * is disabled, even if the plane enable is already
4677 * armed to occur at the next vblank :(
4679 if (IS_BROADWELL(dev))
4680 intel_wait_for_vblank(dev, pipe);
4683 * FIXME IPS should be fine as long as one plane is
4684 * enabled, but in practice it seems to have problems
4685 * when going from primary only to sprite only and vice
4688 hsw_enable_ips(intel_crtc);
4691 * Gen2 reports pipe underruns whenever all planes are disabled.
4692 * So don't enable underrun reporting before at least some planes
4694 * FIXME: Need to fix the logic to work when we turn off all planes
4695 * but leave the pipe running.
4698 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4700 /* Underruns don't raise interrupts, so check manually. */
4701 if (HAS_GMCH_DISPLAY(dev))
4702 i9xx_check_fifo_underruns(dev_priv);
4706 * intel_pre_disable_primary - Perform operations before disabling primary plane
4707 * @crtc: the CRTC whose primary plane is to be disabled
4709 * Performs potentially sleeping operations that must be done before the
4710 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4711 * be called due to an explicit primary plane update, or due to an implicit
4712 * disable that is caused when a sprite plane completely hides the primary
4716 intel_pre_disable_primary(struct drm_crtc *crtc)
4718 struct drm_device *dev = crtc->dev;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4721 int pipe = intel_crtc->pipe;
4724 * Gen2 reports pipe underruns whenever all planes are disabled.
4725 * So diasble underrun reporting before all the planes get disabled.
4726 * FIXME: Need to fix the logic to work when we turn off all planes
4727 * but leave the pipe running.
4730 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4733 * Vblank time updates from the shadow to live plane control register
4734 * are blocked if the memory self-refresh mode is active at that
4735 * moment. So to make sure the plane gets truly disabled, disable
4736 * first the self-refresh mode. The self-refresh enable bit in turn
4737 * will be checked/applied by the HW only at the next frame start
4738 * event which is after the vblank start event, so we need to have a
4739 * wait-for-vblank between disabling the plane and the pipe.
4741 if (HAS_GMCH_DISPLAY(dev)) {
4742 intel_set_memory_cxsr(dev_priv, false);
4743 dev_priv->wm.vlv.cxsr = false;
4744 intel_wait_for_vblank(dev, pipe);
4748 * FIXME IPS should be fine as long as one plane is
4749 * enabled, but in practice it seems to have problems
4750 * when going from primary only to sprite only and vice
4753 hsw_disable_ips(intel_crtc);
4756 static void intel_post_plane_update(struct intel_crtc *crtc)
4758 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4759 struct drm_device *dev = crtc->base.dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 struct drm_plane *plane;
4763 if (atomic->wait_vblank)
4764 intel_wait_for_vblank(dev, crtc->pipe);
4766 intel_frontbuffer_flip(dev, atomic->fb_bits);
4768 if (atomic->disable_cxsr)
4769 crtc->wm.cxsr_allowed = true;
4771 if (crtc->atomic.update_wm_post)
4772 intel_update_watermarks(&crtc->base);
4774 if (atomic->update_fbc)
4775 intel_fbc_update(dev_priv);
4777 if (atomic->post_enable_primary)
4778 intel_post_enable_primary(&crtc->base);
4780 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4781 intel_update_sprite_watermarks(plane, &crtc->base,
4782 0, 0, 0, false, false);
4784 memset(atomic, 0, sizeof(*atomic));
4787 static void intel_pre_plane_update(struct intel_crtc *crtc)
4789 struct drm_device *dev = crtc->base.dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4792 struct drm_plane *p;
4794 /* Track fb's for any planes being disabled */
4795 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4796 struct intel_plane *plane = to_intel_plane(p);
4798 mutex_lock(&dev->struct_mutex);
4799 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4800 plane->frontbuffer_bit);
4801 mutex_unlock(&dev->struct_mutex);
4804 if (atomic->wait_for_flips)
4805 intel_crtc_wait_for_pending_flips(&crtc->base);
4807 if (atomic->disable_fbc)
4808 intel_fbc_disable_crtc(crtc);
4810 if (crtc->atomic.disable_ips)
4811 hsw_disable_ips(crtc);
4813 if (atomic->pre_disable_primary)
4814 intel_pre_disable_primary(&crtc->base);
4816 if (atomic->disable_cxsr) {
4817 crtc->wm.cxsr_allowed = false;
4818 intel_set_memory_cxsr(dev_priv, false);
4822 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4824 struct drm_device *dev = crtc->dev;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826 struct drm_plane *p;
4827 int pipe = intel_crtc->pipe;
4829 intel_crtc_dpms_overlay_disable(intel_crtc);
4831 drm_for_each_plane_mask(p, dev, plane_mask)
4832 to_intel_plane(p)->disable_plane(p, crtc);
4835 * FIXME: Once we grow proper nuclear flip support out of this we need
4836 * to compute the mask of flip planes precisely. For the time being
4837 * consider this a flip to a NULL plane.
4839 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4842 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4844 struct drm_device *dev = crtc->dev;
4845 struct drm_i915_private *dev_priv = dev->dev_private;
4846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4847 struct intel_encoder *encoder;
4848 int pipe = intel_crtc->pipe;
4850 if (WARN_ON(intel_crtc->active))
4853 if (intel_crtc->config->has_pch_encoder)
4854 intel_prepare_shared_dpll(intel_crtc);
4856 if (intel_crtc->config->has_dp_encoder)
4857 intel_dp_set_m_n(intel_crtc, M1_N1);
4859 intel_set_pipe_timings(intel_crtc);
4861 if (intel_crtc->config->has_pch_encoder) {
4862 intel_cpu_transcoder_set_m_n(intel_crtc,
4863 &intel_crtc->config->fdi_m_n, NULL);
4866 ironlake_set_pipeconf(crtc);
4868 intel_crtc->active = true;
4870 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4871 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4873 for_each_encoder_on_crtc(dev, crtc, encoder)
4874 if (encoder->pre_enable)
4875 encoder->pre_enable(encoder);
4877 if (intel_crtc->config->has_pch_encoder) {
4878 /* Note: FDI PLL enabling _must_ be done before we enable the
4879 * cpu pipes, hence this is separate from all the other fdi/pch
4881 ironlake_fdi_pll_enable(intel_crtc);
4883 assert_fdi_tx_disabled(dev_priv, pipe);
4884 assert_fdi_rx_disabled(dev_priv, pipe);
4887 ironlake_pfit_enable(intel_crtc);
4890 * On ILK+ LUT must be loaded before the pipe is running but with
4893 intel_crtc_load_lut(crtc);
4895 intel_update_watermarks(crtc);
4896 intel_enable_pipe(intel_crtc);
4898 if (intel_crtc->config->has_pch_encoder)
4899 ironlake_pch_enable(crtc);
4901 assert_vblank_disabled(crtc);
4902 drm_crtc_vblank_on(crtc);
4904 for_each_encoder_on_crtc(dev, crtc, encoder)
4905 encoder->enable(encoder);
4907 if (HAS_PCH_CPT(dev))
4908 cpt_verify_modeset(dev, intel_crtc->pipe);
4911 /* IPS only exists on ULT machines and is tied to pipe A. */
4912 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4914 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4917 static void haswell_crtc_enable(struct drm_crtc *crtc)
4919 struct drm_device *dev = crtc->dev;
4920 struct drm_i915_private *dev_priv = dev->dev_private;
4921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922 struct intel_encoder *encoder;
4923 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4924 struct intel_crtc_state *pipe_config =
4925 to_intel_crtc_state(crtc->state);
4927 if (WARN_ON(intel_crtc->active))
4930 if (intel_crtc_to_shared_dpll(intel_crtc))
4931 intel_enable_shared_dpll(intel_crtc);
4933 if (intel_crtc->config->has_dp_encoder)
4934 intel_dp_set_m_n(intel_crtc, M1_N1);
4936 intel_set_pipe_timings(intel_crtc);
4938 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4939 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4940 intel_crtc->config->pixel_multiplier - 1);
4943 if (intel_crtc->config->has_pch_encoder) {
4944 intel_cpu_transcoder_set_m_n(intel_crtc,
4945 &intel_crtc->config->fdi_m_n, NULL);
4948 haswell_set_pipeconf(crtc);
4950 intel_set_pipe_csc(crtc);
4952 intel_crtc->active = true;
4954 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4955 for_each_encoder_on_crtc(dev, crtc, encoder)
4956 if (encoder->pre_enable)
4957 encoder->pre_enable(encoder);
4959 if (intel_crtc->config->has_pch_encoder) {
4960 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4962 dev_priv->display.fdi_link_train(crtc);
4965 intel_ddi_enable_pipe_clock(intel_crtc);
4967 if (INTEL_INFO(dev)->gen >= 9)
4968 skylake_pfit_enable(intel_crtc);
4970 ironlake_pfit_enable(intel_crtc);
4973 * On ILK+ LUT must be loaded before the pipe is running but with
4976 intel_crtc_load_lut(crtc);
4978 intel_ddi_set_pipe_settings(crtc);
4979 intel_ddi_enable_transcoder_func(crtc);
4981 intel_update_watermarks(crtc);
4982 intel_enable_pipe(intel_crtc);
4984 if (intel_crtc->config->has_pch_encoder)
4985 lpt_pch_enable(crtc);
4987 if (intel_crtc->config->dp_encoder_is_mst)
4988 intel_ddi_set_vc_payload_alloc(crtc, true);
4990 assert_vblank_disabled(crtc);
4991 drm_crtc_vblank_on(crtc);
4993 for_each_encoder_on_crtc(dev, crtc, encoder) {
4994 encoder->enable(encoder);
4995 intel_opregion_notify_encoder(encoder, true);
4998 /* If we change the relative order between pipe/planes enabling, we need
4999 * to change the workaround. */
5000 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5001 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5002 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5003 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5007 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5009 struct drm_device *dev = crtc->base.dev;
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011 int pipe = crtc->pipe;
5013 /* To avoid upsetting the power well on haswell only disable the pfit if
5014 * it's in use. The hw state code will make sure we get this right. */
5015 if (force || crtc->config->pch_pfit.enabled) {
5016 I915_WRITE(PF_CTL(pipe), 0);
5017 I915_WRITE(PF_WIN_POS(pipe), 0);
5018 I915_WRITE(PF_WIN_SZ(pipe), 0);
5022 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5024 struct drm_device *dev = crtc->dev;
5025 struct drm_i915_private *dev_priv = dev->dev_private;
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 struct intel_encoder *encoder;
5028 int pipe = intel_crtc->pipe;
5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 encoder->disable(encoder);
5034 drm_crtc_vblank_off(crtc);
5035 assert_vblank_disabled(crtc);
5037 if (intel_crtc->config->has_pch_encoder)
5038 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5040 intel_disable_pipe(intel_crtc);
5042 ironlake_pfit_disable(intel_crtc, false);
5044 if (intel_crtc->config->has_pch_encoder)
5045 ironlake_fdi_disable(crtc);
5047 for_each_encoder_on_crtc(dev, crtc, encoder)
5048 if (encoder->post_disable)
5049 encoder->post_disable(encoder);
5051 if (intel_crtc->config->has_pch_encoder) {
5052 ironlake_disable_pch_transcoder(dev_priv, pipe);
5054 if (HAS_PCH_CPT(dev)) {
5055 /* disable TRANS_DP_CTL */
5056 reg = TRANS_DP_CTL(pipe);
5057 temp = I915_READ(reg);
5058 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5059 TRANS_DP_PORT_SEL_MASK);
5060 temp |= TRANS_DP_PORT_SEL_NONE;
5061 I915_WRITE(reg, temp);
5063 /* disable DPLL_SEL */
5064 temp = I915_READ(PCH_DPLL_SEL);
5065 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5066 I915_WRITE(PCH_DPLL_SEL, temp);
5069 ironlake_fdi_pll_disable(intel_crtc);
5072 intel_crtc->active = false;
5073 intel_update_watermarks(crtc);
5076 static void haswell_crtc_disable(struct drm_crtc *crtc)
5078 struct drm_device *dev = crtc->dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5081 struct intel_encoder *encoder;
5082 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5084 for_each_encoder_on_crtc(dev, crtc, encoder) {
5085 intel_opregion_notify_encoder(encoder, false);
5086 encoder->disable(encoder);
5089 drm_crtc_vblank_off(crtc);
5090 assert_vblank_disabled(crtc);
5092 if (intel_crtc->config->has_pch_encoder)
5093 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5095 intel_disable_pipe(intel_crtc);
5097 if (intel_crtc->config->dp_encoder_is_mst)
5098 intel_ddi_set_vc_payload_alloc(crtc, false);
5100 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5102 if (INTEL_INFO(dev)->gen >= 9)
5103 skylake_scaler_disable(intel_crtc);
5105 ironlake_pfit_disable(intel_crtc, false);
5107 intel_ddi_disable_pipe_clock(intel_crtc);
5109 if (intel_crtc->config->has_pch_encoder) {
5110 lpt_disable_pch_transcoder(dev_priv);
5111 intel_ddi_fdi_disable(crtc);
5114 for_each_encoder_on_crtc(dev, crtc, encoder)
5115 if (encoder->post_disable)
5116 encoder->post_disable(encoder);
5118 intel_crtc->active = false;
5119 intel_update_watermarks(crtc);
5122 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5124 struct drm_device *dev = crtc->base.dev;
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 struct intel_crtc_state *pipe_config = crtc->config;
5128 if (!pipe_config->gmch_pfit.control)
5132 * The panel fitter should only be adjusted whilst the pipe is disabled,
5133 * according to register description and PRM.
5135 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5136 assert_pipe_disabled(dev_priv, crtc->pipe);
5138 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5139 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5141 /* Border color in case we don't scale up to the full screen. Black by
5142 * default, change to something else for debugging. */
5143 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5146 static enum intel_display_power_domain port_to_power_domain(enum port port)
5150 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5152 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5154 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5156 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5158 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5161 return POWER_DOMAIN_PORT_OTHER;
5165 #define for_each_power_domain(domain, mask) \
5166 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5167 if ((1 << (domain)) & (mask))
5169 enum intel_display_power_domain
5170 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5172 struct drm_device *dev = intel_encoder->base.dev;
5173 struct intel_digital_port *intel_dig_port;
5175 switch (intel_encoder->type) {
5176 case INTEL_OUTPUT_UNKNOWN:
5177 /* Only DDI platforms should ever use this output type */
5178 WARN_ON_ONCE(!HAS_DDI(dev));
5179 case INTEL_OUTPUT_DISPLAYPORT:
5180 case INTEL_OUTPUT_HDMI:
5181 case INTEL_OUTPUT_EDP:
5182 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5183 return port_to_power_domain(intel_dig_port->port);
5184 case INTEL_OUTPUT_DP_MST:
5185 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5186 return port_to_power_domain(intel_dig_port->port);
5187 case INTEL_OUTPUT_ANALOG:
5188 return POWER_DOMAIN_PORT_CRT;
5189 case INTEL_OUTPUT_DSI:
5190 return POWER_DOMAIN_PORT_DSI;
5192 return POWER_DOMAIN_PORT_OTHER;
5196 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5198 struct drm_device *dev = crtc->dev;
5199 struct intel_encoder *intel_encoder;
5200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5201 enum pipe pipe = intel_crtc->pipe;
5203 enum transcoder transcoder;
5205 if (!crtc->state->active)
5208 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5210 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5211 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5212 if (intel_crtc->config->pch_pfit.enabled ||
5213 intel_crtc->config->pch_pfit.force_thru)
5214 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5216 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5217 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5222 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5224 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226 enum intel_display_power_domain domain;
5227 unsigned long domains, new_domains, old_domains;
5229 old_domains = intel_crtc->enabled_power_domains;
5230 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5232 domains = new_domains & ~old_domains;
5234 for_each_power_domain(domain, domains)
5235 intel_display_power_get(dev_priv, domain);
5237 return old_domains & ~new_domains;
5240 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5241 unsigned long domains)
5243 enum intel_display_power_domain domain;
5245 for_each_power_domain(domain, domains)
5246 intel_display_power_put(dev_priv, domain);
5249 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5251 struct drm_device *dev = state->dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 unsigned long put_domains[I915_MAX_PIPES] = {};
5254 struct drm_crtc_state *crtc_state;
5255 struct drm_crtc *crtc;
5258 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5259 if (needs_modeset(crtc->state))
5260 put_domains[to_intel_crtc(crtc)->pipe] =
5261 modeset_get_crtc_power_domains(crtc);
5264 if (dev_priv->display.modeset_commit_cdclk) {
5265 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5267 if (cdclk != dev_priv->cdclk_freq &&
5268 !WARN_ON(!state->allow_modeset))
5269 dev_priv->display.modeset_commit_cdclk(state);
5272 for (i = 0; i < I915_MAX_PIPES; i++)
5274 modeset_put_power_domains(dev_priv, put_domains[i]);
5277 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5279 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5281 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5282 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5283 return max_cdclk_freq;
5284 else if (IS_CHERRYVIEW(dev_priv))
5285 return max_cdclk_freq*95/100;
5286 else if (INTEL_INFO(dev_priv)->gen < 4)
5287 return 2*max_cdclk_freq*90/100;
5289 return max_cdclk_freq*90/100;
5292 static void intel_update_max_cdclk(struct drm_device *dev)
5294 struct drm_i915_private *dev_priv = dev->dev_private;
5296 if (IS_SKYLAKE(dev)) {
5297 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5299 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5300 dev_priv->max_cdclk_freq = 675000;
5301 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5302 dev_priv->max_cdclk_freq = 540000;
5303 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5304 dev_priv->max_cdclk_freq = 450000;
5306 dev_priv->max_cdclk_freq = 337500;
5307 } else if (IS_BROADWELL(dev)) {
5309 * FIXME with extra cooling we can allow
5310 * 540 MHz for ULX and 675 Mhz for ULT.
5311 * How can we know if extra cooling is
5312 * available? PCI ID, VTB, something else?
5314 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5315 dev_priv->max_cdclk_freq = 450000;
5316 else if (IS_BDW_ULX(dev))
5317 dev_priv->max_cdclk_freq = 450000;
5318 else if (IS_BDW_ULT(dev))
5319 dev_priv->max_cdclk_freq = 540000;
5321 dev_priv->max_cdclk_freq = 675000;
5322 } else if (IS_CHERRYVIEW(dev)) {
5323 dev_priv->max_cdclk_freq = 320000;
5324 } else if (IS_VALLEYVIEW(dev)) {
5325 dev_priv->max_cdclk_freq = 400000;
5327 /* otherwise assume cdclk is fixed */
5328 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5331 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5333 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5334 dev_priv->max_cdclk_freq);
5336 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5337 dev_priv->max_dotclk_freq);
5340 static void intel_update_cdclk(struct drm_device *dev)
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5344 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5345 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5346 dev_priv->cdclk_freq);
5349 * Program the gmbus_freq based on the cdclk frequency.
5350 * BSpec erroneously claims we should aim for 4MHz, but
5351 * in fact 1MHz is the correct frequency.
5353 if (IS_VALLEYVIEW(dev)) {
5355 * Program the gmbus_freq based on the cdclk frequency.
5356 * BSpec erroneously claims we should aim for 4MHz, but
5357 * in fact 1MHz is the correct frequency.
5359 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5362 if (dev_priv->max_cdclk_freq == 0)
5363 intel_update_max_cdclk(dev);
5366 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5371 uint32_t current_freq;
5374 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375 switch (frequency) {
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5378 ratio = BXT_DE_PLL_RATIO(60);
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5382 ratio = BXT_DE_PLL_RATIO(60);
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5386 ratio = BXT_DE_PLL_RATIO(60);
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5390 ratio = BXT_DE_PLL_RATIO(60);
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(65);
5398 * Bypass frequency with DE PLL disabled. Init ratio, divider
5399 * to suppress GCC warning.
5405 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5410 mutex_lock(&dev_priv->rps.hw_lock);
5411 /* Inform power controller of upcoming frequency change */
5412 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5417 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5423 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424 current_freq = current_freq * 500 + 1000;
5427 * DE PLL has to be disabled when
5428 * - setting to 19.2MHz (bypass, PLL isn't used)
5429 * - before setting to 624MHz (PLL needs toggling)
5430 * - before setting to any frequency from 624MHz (PLL needs toggling)
5432 if (frequency == 19200 || frequency == 624000 ||
5433 current_freq == 624000) {
5434 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5436 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5438 DRM_ERROR("timout waiting for DE PLL unlock\n");
5441 if (frequency != 19200) {
5444 val = I915_READ(BXT_DE_PLL_CTL);
5445 val &= ~BXT_DE_PLL_RATIO_MASK;
5447 I915_WRITE(BXT_DE_PLL_CTL, val);
5449 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5451 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5452 DRM_ERROR("timeout waiting for DE PLL lock\n");
5454 val = I915_READ(CDCLK_CTL);
5455 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5458 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5461 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462 if (frequency >= 500000)
5463 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5465 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5466 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467 val |= (frequency - 1000) / 500;
5468 I915_WRITE(CDCLK_CTL, val);
5471 mutex_lock(&dev_priv->rps.hw_lock);
5472 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5473 DIV_ROUND_UP(frequency, 25000));
5474 mutex_unlock(&dev_priv->rps.hw_lock);
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 intel_update_cdclk(dev);
5485 void broxton_init_cdclk(struct drm_device *dev)
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492 * or else the reset will hang because there is no PCH to respond.
5493 * Move the handshake programming to initialization sequence.
5494 * Previously was left up to BIOS.
5496 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5497 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5498 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5500 /* Enable PG1 for cdclk */
5501 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5503 /* check if cd clock is enabled */
5504 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5505 DRM_DEBUG_KMS("Display already initialized\n");
5511 * - The initial CDCLK needs to be read from VBT.
5512 * Need to make this change after VBT has changes for BXT.
5513 * - check if setting the max (or any) cdclk freq is really necessary
5514 * here, it belongs to modeset time
5516 broxton_set_cdclk(dev, 624000);
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5519 POSTING_READ(DBUF_CTL);
5523 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5524 DRM_ERROR("DBuf power enable timeout!\n");
5527 void broxton_uninit_cdclk(struct drm_device *dev)
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5531 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5532 POSTING_READ(DBUF_CTL);
5536 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5537 DRM_ERROR("DBuf power disable timeout!\n");
5539 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540 broxton_set_cdclk(dev, 19200);
5542 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5545 static const struct skl_cdclk_entry {
5548 } skl_cdclk_frequencies[] = {
5549 { .freq = 308570, .vco = 8640 },
5550 { .freq = 337500, .vco = 8100 },
5551 { .freq = 432000, .vco = 8640 },
5552 { .freq = 450000, .vco = 8100 },
5553 { .freq = 540000, .vco = 8100 },
5554 { .freq = 617140, .vco = 8640 },
5555 { .freq = 675000, .vco = 8100 },
5558 static unsigned int skl_cdclk_decimal(unsigned int freq)
5560 return (freq - 1000) / 500;
5563 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5567 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5568 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5570 if (e->freq == freq)
5578 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5580 unsigned int min_freq;
5583 /* select the minimum CDCLK before enabling DPLL 0 */
5584 val = I915_READ(CDCLK_CTL);
5585 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5586 val |= CDCLK_FREQ_337_308;
5588 if (required_vco == 8640)
5593 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5595 I915_WRITE(CDCLK_CTL, val);
5596 POSTING_READ(CDCLK_CTL);
5599 * We always enable DPLL0 with the lowest link rate possible, but still
5600 * taking into account the VCO required to operate the eDP panel at the
5601 * desired frequency. The usual DP link rates operate with a VCO of
5602 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5603 * The modeset code is responsible for the selection of the exact link
5604 * rate later on, with the constraint of choosing a frequency that
5605 * works with required_vco.
5607 val = I915_READ(DPLL_CTRL1);
5609 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5610 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5611 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5612 if (required_vco == 8640)
5613 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5616 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5619 I915_WRITE(DPLL_CTRL1, val);
5620 POSTING_READ(DPLL_CTRL1);
5622 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5624 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5625 DRM_ERROR("DPLL0 not locked\n");
5628 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5633 /* inform PCU we want to change CDCLK */
5634 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5635 mutex_lock(&dev_priv->rps.hw_lock);
5636 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5637 mutex_unlock(&dev_priv->rps.hw_lock);
5639 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5642 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5646 for (i = 0; i < 15; i++) {
5647 if (skl_cdclk_pcu_ready(dev_priv))
5655 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5657 struct drm_device *dev = dev_priv->dev;
5658 u32 freq_select, pcu_ack;
5660 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5662 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5663 DRM_ERROR("failed to inform PCU about cdclk change\n");
5671 freq_select = CDCLK_FREQ_450_432;
5675 freq_select = CDCLK_FREQ_540;
5681 freq_select = CDCLK_FREQ_337_308;
5686 freq_select = CDCLK_FREQ_675_617;
5691 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5692 POSTING_READ(CDCLK_CTL);
5694 /* inform PCU of the change */
5695 mutex_lock(&dev_priv->rps.hw_lock);
5696 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5697 mutex_unlock(&dev_priv->rps.hw_lock);
5699 intel_update_cdclk(dev);
5702 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5704 /* disable DBUF power */
5705 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5706 POSTING_READ(DBUF_CTL);
5710 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5711 DRM_ERROR("DBuf power disable timeout\n");
5714 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5716 if (dev_priv->csr.dmc_payload) {
5718 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5720 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5721 DRM_ERROR("Couldn't disable DPLL0\n");
5724 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5727 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5730 unsigned int required_vco;
5732 /* enable PCH reset handshake */
5733 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5734 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5736 /* enable PG1 and Misc I/O */
5737 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5739 /* DPLL0 not enabled (happens on early BIOS versions) */
5740 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5742 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5743 skl_dpll0_enable(dev_priv, required_vco);
5746 /* set CDCLK to the frequency the BIOS chose */
5747 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5749 /* enable DBUF power */
5750 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5751 POSTING_READ(DBUF_CTL);
5755 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5756 DRM_ERROR("DBuf power enable timeout\n");
5759 /* returns HPLL frequency in kHz */
5760 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5762 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5764 /* Obtain SKU information */
5765 mutex_lock(&dev_priv->sb_lock);
5766 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5767 CCK_FUSE_HPLL_FREQ_MASK;
5768 mutex_unlock(&dev_priv->sb_lock);
5770 return vco_freq[hpll_freq] * 1000;
5773 /* Adjust CDclk dividers to allow high res or save power if possible */
5774 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5776 struct drm_i915_private *dev_priv = dev->dev_private;
5779 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5780 != dev_priv->cdclk_freq);
5782 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5784 else if (cdclk == 266667)
5789 mutex_lock(&dev_priv->rps.hw_lock);
5790 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5791 val &= ~DSPFREQGUAR_MASK;
5792 val |= (cmd << DSPFREQGUAR_SHIFT);
5793 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5794 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5795 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5797 DRM_ERROR("timed out waiting for CDclk change\n");
5799 mutex_unlock(&dev_priv->rps.hw_lock);
5801 mutex_lock(&dev_priv->sb_lock);
5803 if (cdclk == 400000) {
5806 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5808 /* adjust cdclk divider */
5809 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5810 val &= ~DISPLAY_FREQUENCY_VALUES;
5812 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5814 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5815 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5817 DRM_ERROR("timed out waiting for CDclk change\n");
5820 /* adjust self-refresh exit latency value */
5821 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5825 * For high bandwidth configs, we set a higher latency in the bunit
5826 * so that the core display fetch happens in time to avoid underruns.
5828 if (cdclk == 400000)
5829 val |= 4500 / 250; /* 4.5 usec */
5831 val |= 3000 / 250; /* 3.0 usec */
5832 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5834 mutex_unlock(&dev_priv->sb_lock);
5836 intel_update_cdclk(dev);
5839 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5844 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5845 != dev_priv->cdclk_freq);
5854 MISSING_CASE(cdclk);
5859 * Specs are full of misinformation, but testing on actual
5860 * hardware has shown that we just need to write the desired
5861 * CCK divider into the Punit register.
5863 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5865 mutex_lock(&dev_priv->rps.hw_lock);
5866 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5867 val &= ~DSPFREQGUAR_MASK_CHV;
5868 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5869 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5870 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5871 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5873 DRM_ERROR("timed out waiting for CDclk change\n");
5875 mutex_unlock(&dev_priv->rps.hw_lock);
5877 intel_update_cdclk(dev);
5880 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5883 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5884 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5887 * Really only a few cases to deal with, as only 4 CDclks are supported:
5890 * 320/333MHz (depends on HPLL freq)
5892 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5893 * of the lower bin and adjust if needed.
5895 * We seem to get an unstable or solid color picture at 200MHz.
5896 * Not sure what's wrong. For now use 200MHz only when all pipes
5899 if (!IS_CHERRYVIEW(dev_priv) &&
5900 max_pixclk > freq_320*limit/100)
5902 else if (max_pixclk > 266667*limit/100)
5904 else if (max_pixclk > 0)
5910 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5915 * - remove the guardband, it's not needed on BXT
5916 * - set 19.2MHz bypass frequency if there are no active pipes
5918 if (max_pixclk > 576000*9/10)
5920 else if (max_pixclk > 384000*9/10)
5922 else if (max_pixclk > 288000*9/10)
5924 else if (max_pixclk > 144000*9/10)
5930 /* Compute the max pixel clock for new configuration. Uses atomic state if
5931 * that's non-NULL, look at current state otherwise. */
5932 static int intel_mode_max_pixclk(struct drm_device *dev,
5933 struct drm_atomic_state *state)
5935 struct intel_crtc *intel_crtc;
5936 struct intel_crtc_state *crtc_state;
5939 for_each_intel_crtc(dev, intel_crtc) {
5940 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5941 if (IS_ERR(crtc_state))
5942 return PTR_ERR(crtc_state);
5944 if (!crtc_state->base.enable)
5947 max_pixclk = max(max_pixclk,
5948 crtc_state->base.adjusted_mode.crtc_clock);
5954 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5956 struct drm_device *dev = state->dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958 int max_pixclk = intel_mode_max_pixclk(dev, state);
5963 to_intel_atomic_state(state)->cdclk =
5964 valleyview_calc_cdclk(dev_priv, max_pixclk);
5969 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5971 struct drm_device *dev = state->dev;
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 int max_pixclk = intel_mode_max_pixclk(dev, state);
5978 to_intel_atomic_state(state)->cdclk =
5979 broxton_calc_cdclk(dev_priv, max_pixclk);
5984 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5986 unsigned int credits, default_credits;
5988 if (IS_CHERRYVIEW(dev_priv))
5989 default_credits = PFI_CREDIT(12);
5991 default_credits = PFI_CREDIT(8);
5993 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5994 /* CHV suggested value is 31 or 63 */
5995 if (IS_CHERRYVIEW(dev_priv))
5996 credits = PFI_CREDIT_63;
5998 credits = PFI_CREDIT(15);
6000 credits = default_credits;
6004 * WA - write default credits before re-programming
6005 * FIXME: should we also set the resend bit here?
6007 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6010 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6011 credits | PFI_CREDIT_RESEND);
6014 * FIXME is this guaranteed to clear
6015 * immediately or should we poll for it?
6017 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6020 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6022 struct drm_device *dev = old_state->dev;
6023 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6027 * FIXME: We can end up here with all power domains off, yet
6028 * with a CDCLK frequency other than the minimum. To account
6029 * for this take the PIPE-A power domain, which covers the HW
6030 * blocks needed for the following programming. This can be
6031 * removed once it's guaranteed that we get here either with
6032 * the minimum CDCLK set, or the required power domains
6035 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6037 if (IS_CHERRYVIEW(dev))
6038 cherryview_set_cdclk(dev, req_cdclk);
6040 valleyview_set_cdclk(dev, req_cdclk);
6042 vlv_program_pfi_credits(dev_priv);
6044 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6047 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6049 struct drm_device *dev = crtc->dev;
6050 struct drm_i915_private *dev_priv = to_i915(dev);
6051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052 struct intel_encoder *encoder;
6053 int pipe = intel_crtc->pipe;
6056 if (WARN_ON(intel_crtc->active))
6059 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6061 if (intel_crtc->config->has_dp_encoder)
6062 intel_dp_set_m_n(intel_crtc, M1_N1);
6064 intel_set_pipe_timings(intel_crtc);
6066 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6067 struct drm_i915_private *dev_priv = dev->dev_private;
6069 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6070 I915_WRITE(CHV_CANVAS(pipe), 0);
6073 i9xx_set_pipeconf(intel_crtc);
6075 intel_crtc->active = true;
6077 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6079 for_each_encoder_on_crtc(dev, crtc, encoder)
6080 if (encoder->pre_pll_enable)
6081 encoder->pre_pll_enable(encoder);
6084 if (IS_CHERRYVIEW(dev)) {
6085 chv_prepare_pll(intel_crtc, intel_crtc->config);
6086 chv_enable_pll(intel_crtc, intel_crtc->config);
6088 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6089 vlv_enable_pll(intel_crtc, intel_crtc->config);
6093 for_each_encoder_on_crtc(dev, crtc, encoder)
6094 if (encoder->pre_enable)
6095 encoder->pre_enable(encoder);
6097 i9xx_pfit_enable(intel_crtc);
6099 intel_crtc_load_lut(crtc);
6101 intel_enable_pipe(intel_crtc);
6103 assert_vblank_disabled(crtc);
6104 drm_crtc_vblank_on(crtc);
6106 for_each_encoder_on_crtc(dev, crtc, encoder)
6107 encoder->enable(encoder);
6110 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6112 struct drm_device *dev = crtc->base.dev;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6115 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6116 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6119 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6121 struct drm_device *dev = crtc->dev;
6122 struct drm_i915_private *dev_priv = to_i915(dev);
6123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6124 struct intel_encoder *encoder;
6125 int pipe = intel_crtc->pipe;
6127 if (WARN_ON(intel_crtc->active))
6130 i9xx_set_pll_dividers(intel_crtc);
6132 if (intel_crtc->config->has_dp_encoder)
6133 intel_dp_set_m_n(intel_crtc, M1_N1);
6135 intel_set_pipe_timings(intel_crtc);
6137 i9xx_set_pipeconf(intel_crtc);
6139 intel_crtc->active = true;
6142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6144 for_each_encoder_on_crtc(dev, crtc, encoder)
6145 if (encoder->pre_enable)
6146 encoder->pre_enable(encoder);
6148 i9xx_enable_pll(intel_crtc);
6150 i9xx_pfit_enable(intel_crtc);
6152 intel_crtc_load_lut(crtc);
6154 intel_update_watermarks(crtc);
6155 intel_enable_pipe(intel_crtc);
6157 assert_vblank_disabled(crtc);
6158 drm_crtc_vblank_on(crtc);
6160 for_each_encoder_on_crtc(dev, crtc, encoder)
6161 encoder->enable(encoder);
6164 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6166 struct drm_device *dev = crtc->base.dev;
6167 struct drm_i915_private *dev_priv = dev->dev_private;
6169 if (!crtc->config->gmch_pfit.control)
6172 assert_pipe_disabled(dev_priv, crtc->pipe);
6174 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6175 I915_READ(PFIT_CONTROL));
6176 I915_WRITE(PFIT_CONTROL, 0);
6179 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6181 struct drm_device *dev = crtc->dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6184 struct intel_encoder *encoder;
6185 int pipe = intel_crtc->pipe;
6188 * On gen2 planes are double buffered but the pipe isn't, so we must
6189 * wait for planes to fully turn off before disabling the pipe.
6190 * We also need to wait on all gmch platforms because of the
6191 * self-refresh mode constraint explained above.
6193 intel_wait_for_vblank(dev, pipe);
6195 for_each_encoder_on_crtc(dev, crtc, encoder)
6196 encoder->disable(encoder);
6198 drm_crtc_vblank_off(crtc);
6199 assert_vblank_disabled(crtc);
6201 intel_disable_pipe(intel_crtc);
6203 i9xx_pfit_disable(intel_crtc);
6205 for_each_encoder_on_crtc(dev, crtc, encoder)
6206 if (encoder->post_disable)
6207 encoder->post_disable(encoder);
6209 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6210 if (IS_CHERRYVIEW(dev))
6211 chv_disable_pll(dev_priv, pipe);
6212 else if (IS_VALLEYVIEW(dev))
6213 vlv_disable_pll(dev_priv, pipe);
6215 i9xx_disable_pll(intel_crtc);
6218 for_each_encoder_on_crtc(dev, crtc, encoder)
6219 if (encoder->post_pll_disable)
6220 encoder->post_pll_disable(encoder);
6223 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6225 intel_crtc->active = false;
6226 intel_update_watermarks(crtc);
6229 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6232 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6233 enum intel_display_power_domain domain;
6234 unsigned long domains;
6236 if (!intel_crtc->active)
6239 if (to_intel_plane_state(crtc->primary->state)->visible) {
6240 intel_crtc_wait_for_pending_flips(crtc);
6241 intel_pre_disable_primary(crtc);
6244 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6245 dev_priv->display.crtc_disable(crtc);
6246 intel_disable_shared_dpll(intel_crtc);
6248 domains = intel_crtc->enabled_power_domains;
6249 for_each_power_domain(domain, domains)
6250 intel_display_power_put(dev_priv, domain);
6251 intel_crtc->enabled_power_domains = 0;
6255 * turn all crtc's off, but do not adjust state
6256 * This has to be paired with a call to intel_modeset_setup_hw_state.
6258 int intel_display_suspend(struct drm_device *dev)
6260 struct drm_mode_config *config = &dev->mode_config;
6261 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6262 struct drm_atomic_state *state;
6263 struct drm_crtc *crtc;
6264 unsigned crtc_mask = 0;
6270 lockdep_assert_held(&ctx->ww_ctx);
6271 state = drm_atomic_state_alloc(dev);
6272 if (WARN_ON(!state))
6275 state->acquire_ctx = ctx;
6276 state->allow_modeset = true;
6278 for_each_crtc(dev, crtc) {
6279 struct drm_crtc_state *crtc_state =
6280 drm_atomic_get_crtc_state(state, crtc);
6282 ret = PTR_ERR_OR_ZERO(crtc_state);
6286 if (!crtc_state->active)
6289 crtc_state->active = false;
6290 crtc_mask |= 1 << drm_crtc_index(crtc);
6294 ret = drm_atomic_commit(state);
6297 for_each_crtc(dev, crtc)
6298 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6299 crtc->state->active = true;
6307 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6308 drm_atomic_state_free(state);
6312 void intel_encoder_destroy(struct drm_encoder *encoder)
6314 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6316 drm_encoder_cleanup(encoder);
6317 kfree(intel_encoder);
6320 /* Cross check the actual hw state with our own modeset state tracking (and it's
6321 * internal consistency). */
6322 static void intel_connector_check_state(struct intel_connector *connector)
6324 struct drm_crtc *crtc = connector->base.state->crtc;
6326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6327 connector->base.base.id,
6328 connector->base.name);
6330 if (connector->get_hw_state(connector)) {
6331 struct intel_encoder *encoder = connector->encoder;
6332 struct drm_connector_state *conn_state = connector->base.state;
6334 I915_STATE_WARN(!crtc,
6335 "connector enabled without attached crtc\n");
6340 I915_STATE_WARN(!crtc->state->active,
6341 "connector is active, but attached crtc isn't\n");
6343 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6346 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6347 "atomic encoder doesn't match attached encoder\n");
6349 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6350 "attached encoder crtc differs from connector crtc\n");
6352 I915_STATE_WARN(crtc && crtc->state->active,
6353 "attached crtc is active, but connector isn't\n");
6354 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6355 "best encoder set without crtc!\n");
6359 int intel_connector_init(struct intel_connector *connector)
6361 struct drm_connector_state *connector_state;
6363 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6364 if (!connector_state)
6367 connector->base.state = connector_state;
6371 struct intel_connector *intel_connector_alloc(void)
6373 struct intel_connector *connector;
6375 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6379 if (intel_connector_init(connector) < 0) {
6387 /* Simple connector->get_hw_state implementation for encoders that support only
6388 * one connector and no cloning and hence the encoder state determines the state
6389 * of the connector. */
6390 bool intel_connector_get_hw_state(struct intel_connector *connector)
6393 struct intel_encoder *encoder = connector->encoder;
6395 return encoder->get_hw_state(encoder, &pipe);
6398 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6400 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6401 return crtc_state->fdi_lanes;
6406 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6407 struct intel_crtc_state *pipe_config)
6409 struct drm_atomic_state *state = pipe_config->base.state;
6410 struct intel_crtc *other_crtc;
6411 struct intel_crtc_state *other_crtc_state;
6413 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6414 pipe_name(pipe), pipe_config->fdi_lanes);
6415 if (pipe_config->fdi_lanes > 4) {
6416 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6417 pipe_name(pipe), pipe_config->fdi_lanes);
6421 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6422 if (pipe_config->fdi_lanes > 2) {
6423 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6424 pipe_config->fdi_lanes);
6431 if (INTEL_INFO(dev)->num_pipes == 2)
6434 /* Ivybridge 3 pipe is really complicated */
6439 if (pipe_config->fdi_lanes <= 2)
6442 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6444 intel_atomic_get_crtc_state(state, other_crtc);
6445 if (IS_ERR(other_crtc_state))
6446 return PTR_ERR(other_crtc_state);
6448 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6449 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6450 pipe_name(pipe), pipe_config->fdi_lanes);
6455 if (pipe_config->fdi_lanes > 2) {
6456 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6457 pipe_name(pipe), pipe_config->fdi_lanes);
6461 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6463 intel_atomic_get_crtc_state(state, other_crtc);
6464 if (IS_ERR(other_crtc_state))
6465 return PTR_ERR(other_crtc_state);
6467 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6468 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6478 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6479 struct intel_crtc_state *pipe_config)
6481 struct drm_device *dev = intel_crtc->base.dev;
6482 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6483 int lane, link_bw, fdi_dotclock, ret;
6484 bool needs_recompute = false;
6487 /* FDI is a binary signal running at ~2.7GHz, encoding
6488 * each output octet as 10 bits. The actual frequency
6489 * is stored as a divider into a 100MHz clock, and the
6490 * mode pixel clock is stored in units of 1KHz.
6491 * Hence the bw of each lane in terms of the mode signal
6494 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6496 fdi_dotclock = adjusted_mode->crtc_clock;
6498 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6499 pipe_config->pipe_bpp);
6501 pipe_config->fdi_lanes = lane;
6503 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6504 link_bw, &pipe_config->fdi_m_n);
6506 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6507 intel_crtc->pipe, pipe_config);
6508 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6509 pipe_config->pipe_bpp -= 2*3;
6510 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6511 pipe_config->pipe_bpp);
6512 needs_recompute = true;
6513 pipe_config->bw_constrained = true;
6518 if (needs_recompute)
6524 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6525 struct intel_crtc_state *pipe_config)
6527 if (pipe_config->pipe_bpp > 24)
6530 /* HSW can handle pixel rate up to cdclk? */
6531 if (IS_HASWELL(dev_priv->dev))
6535 * We compare against max which means we must take
6536 * the increased cdclk requirement into account when
6537 * calculating the new cdclk.
6539 * Should measure whether using a lower cdclk w/o IPS
6541 return ilk_pipe_pixel_rate(pipe_config) <=
6542 dev_priv->max_cdclk_freq * 95 / 100;
6545 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6546 struct intel_crtc_state *pipe_config)
6548 struct drm_device *dev = crtc->base.dev;
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6551 pipe_config->ips_enabled = i915.enable_ips &&
6552 hsw_crtc_supports_ips(crtc) &&
6553 pipe_config_supports_ips(dev_priv, pipe_config);
6556 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6557 struct intel_crtc_state *pipe_config)
6559 struct drm_device *dev = crtc->base.dev;
6560 struct drm_i915_private *dev_priv = dev->dev_private;
6561 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6563 /* FIXME should check pixel clock limits on all platforms */
6564 if (INTEL_INFO(dev)->gen < 4) {
6565 int clock_limit = dev_priv->max_cdclk_freq;
6568 * Enable pixel doubling when the dot clock
6569 * is > 90% of the (display) core speed.
6571 * GDG double wide on either pipe,
6572 * otherwise pipe A only.
6574 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6575 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6577 pipe_config->double_wide = true;
6580 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6585 * Pipe horizontal size must be even in:
6587 * - LVDS dual channel mode
6588 * - Double wide pipe
6590 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6591 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6592 pipe_config->pipe_src_w &= ~1;
6594 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6595 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6597 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6598 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6602 hsw_compute_ips_config(crtc, pipe_config);
6604 if (pipe_config->has_pch_encoder)
6605 return ironlake_fdi_compute_config(crtc, pipe_config);
6610 static int skylake_get_display_clock_speed(struct drm_device *dev)
6612 struct drm_i915_private *dev_priv = to_i915(dev);
6613 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6614 uint32_t cdctl = I915_READ(CDCLK_CTL);
6617 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6618 return 24000; /* 24MHz is the cd freq with NSSC ref */
6620 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6623 linkrate = (I915_READ(DPLL_CTRL1) &
6624 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6626 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6627 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6629 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6630 case CDCLK_FREQ_450_432:
6632 case CDCLK_FREQ_337_308:
6634 case CDCLK_FREQ_675_617:
6637 WARN(1, "Unknown cd freq selection\n");
6641 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6642 case CDCLK_FREQ_450_432:
6644 case CDCLK_FREQ_337_308:
6646 case CDCLK_FREQ_675_617:
6649 WARN(1, "Unknown cd freq selection\n");
6653 /* error case, do as if DPLL0 isn't enabled */
6657 static int broxton_get_display_clock_speed(struct drm_device *dev)
6659 struct drm_i915_private *dev_priv = to_i915(dev);
6660 uint32_t cdctl = I915_READ(CDCLK_CTL);
6661 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6662 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6665 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6668 cdclk = 19200 * pll_ratio / 2;
6670 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6671 case BXT_CDCLK_CD2X_DIV_SEL_1:
6672 return cdclk; /* 576MHz or 624MHz */
6673 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6674 return cdclk * 2 / 3; /* 384MHz */
6675 case BXT_CDCLK_CD2X_DIV_SEL_2:
6676 return cdclk / 2; /* 288MHz */
6677 case BXT_CDCLK_CD2X_DIV_SEL_4:
6678 return cdclk / 4; /* 144MHz */
6681 /* error case, do as if DE PLL isn't enabled */
6685 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6687 struct drm_i915_private *dev_priv = dev->dev_private;
6688 uint32_t lcpll = I915_READ(LCPLL_CTL);
6689 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6691 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6693 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6695 else if (freq == LCPLL_CLK_FREQ_450)
6697 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6699 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6705 static int haswell_get_display_clock_speed(struct drm_device *dev)
6707 struct drm_i915_private *dev_priv = dev->dev_private;
6708 uint32_t lcpll = I915_READ(LCPLL_CTL);
6709 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6711 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6713 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6715 else if (freq == LCPLL_CLK_FREQ_450)
6717 else if (IS_HSW_ULT(dev))
6723 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6729 if (dev_priv->hpll_freq == 0)
6730 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6732 mutex_lock(&dev_priv->sb_lock);
6733 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6734 mutex_unlock(&dev_priv->sb_lock);
6736 divider = val & DISPLAY_FREQUENCY_VALUES;
6738 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6739 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6740 "cdclk change in progress\n");
6742 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6745 static int ilk_get_display_clock_speed(struct drm_device *dev)
6750 static int i945_get_display_clock_speed(struct drm_device *dev)
6755 static int i915_get_display_clock_speed(struct drm_device *dev)
6760 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6765 static int pnv_get_display_clock_speed(struct drm_device *dev)
6769 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6772 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6774 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6776 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6778 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6781 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6782 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6784 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6789 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6793 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6795 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6798 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6799 case GC_DISPLAY_CLOCK_333_MHZ:
6802 case GC_DISPLAY_CLOCK_190_200_MHZ:
6808 static int i865_get_display_clock_speed(struct drm_device *dev)
6813 static int i85x_get_display_clock_speed(struct drm_device *dev)
6818 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6819 * encoding is different :(
6820 * FIXME is this the right way to detect 852GM/852GMV?
6822 if (dev->pdev->revision == 0x1)
6825 pci_bus_read_config_word(dev->pdev->bus,
6826 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6828 /* Assume that the hardware is in the high speed state. This
6829 * should be the default.
6831 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6832 case GC_CLOCK_133_200:
6833 case GC_CLOCK_133_200_2:
6834 case GC_CLOCK_100_200:
6836 case GC_CLOCK_166_250:
6838 case GC_CLOCK_100_133:
6840 case GC_CLOCK_133_266:
6841 case GC_CLOCK_133_266_2:
6842 case GC_CLOCK_166_266:
6846 /* Shouldn't happen */
6850 static int i830_get_display_clock_speed(struct drm_device *dev)
6855 static unsigned int intel_hpll_vco(struct drm_device *dev)
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 static const unsigned int blb_vco[8] = {
6865 static const unsigned int pnv_vco[8] = {
6872 static const unsigned int cl_vco[8] = {
6881 static const unsigned int elk_vco[8] = {
6887 static const unsigned int ctg_vco[8] = {
6895 const unsigned int *vco_table;
6899 /* FIXME other chipsets? */
6901 vco_table = ctg_vco;
6902 else if (IS_G4X(dev))
6903 vco_table = elk_vco;
6904 else if (IS_CRESTLINE(dev))
6906 else if (IS_PINEVIEW(dev))
6907 vco_table = pnv_vco;
6908 else if (IS_G33(dev))
6909 vco_table = blb_vco;
6913 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6915 vco = vco_table[tmp & 0x7];
6917 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6919 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6924 static int gm45_get_display_clock_speed(struct drm_device *dev)
6926 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6929 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6931 cdclk_sel = (tmp >> 12) & 0x1;
6937 return cdclk_sel ? 333333 : 222222;
6939 return cdclk_sel ? 320000 : 228571;
6941 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6946 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6948 static const uint8_t div_3200[] = { 16, 10, 8 };
6949 static const uint8_t div_4000[] = { 20, 12, 10 };
6950 static const uint8_t div_5333[] = { 24, 16, 14 };
6951 const uint8_t *div_table;
6952 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6955 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6957 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6959 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6964 div_table = div_3200;
6967 div_table = div_4000;
6970 div_table = div_5333;
6976 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6979 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6983 static int g33_get_display_clock_speed(struct drm_device *dev)
6985 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6986 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6987 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6988 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6989 const uint8_t *div_table;
6990 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6993 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6995 cdclk_sel = (tmp >> 4) & 0x7;
6997 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7002 div_table = div_3200;
7005 div_table = div_4000;
7008 div_table = div_4800;
7011 div_table = div_5333;
7017 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7020 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7025 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7027 while (*num > DATA_LINK_M_N_MASK ||
7028 *den > DATA_LINK_M_N_MASK) {
7034 static void compute_m_n(unsigned int m, unsigned int n,
7035 uint32_t *ret_m, uint32_t *ret_n)
7037 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7038 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7039 intel_reduce_m_n_ratio(ret_m, ret_n);
7043 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7044 int pixel_clock, int link_clock,
7045 struct intel_link_m_n *m_n)
7049 compute_m_n(bits_per_pixel * pixel_clock,
7050 link_clock * nlanes * 8,
7051 &m_n->gmch_m, &m_n->gmch_n);
7053 compute_m_n(pixel_clock, link_clock,
7054 &m_n->link_m, &m_n->link_n);
7057 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7059 if (i915.panel_use_ssc >= 0)
7060 return i915.panel_use_ssc != 0;
7061 return dev_priv->vbt.lvds_use_ssc
7062 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7065 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7068 struct drm_device *dev = crtc_state->base.crtc->dev;
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7072 WARN_ON(!crtc_state->base.state);
7074 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7076 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7077 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7078 refclk = dev_priv->vbt.lvds_ssc_freq;
7079 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7080 } else if (!IS_GEN2(dev)) {
7089 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7091 return (1 << dpll->n) << 16 | dpll->m2;
7094 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7096 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7099 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7100 struct intel_crtc_state *crtc_state,
7101 intel_clock_t *reduced_clock)
7103 struct drm_device *dev = crtc->base.dev;
7106 if (IS_PINEVIEW(dev)) {
7107 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7109 fp2 = pnv_dpll_compute_fp(reduced_clock);
7111 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7113 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7116 crtc_state->dpll_hw_state.fp0 = fp;
7118 crtc->lowfreq_avail = false;
7119 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7121 crtc_state->dpll_hw_state.fp1 = fp2;
7122 crtc->lowfreq_avail = true;
7124 crtc_state->dpll_hw_state.fp1 = fp;
7128 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7134 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7135 * and set it to a reasonable value instead.
7137 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7138 reg_val &= 0xffffff00;
7139 reg_val |= 0x00000030;
7140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7142 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7143 reg_val &= 0x8cffffff;
7144 reg_val = 0x8c000000;
7145 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7147 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7148 reg_val &= 0xffffff00;
7149 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7151 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7152 reg_val &= 0x00ffffff;
7153 reg_val |= 0xb0000000;
7154 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7157 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7158 struct intel_link_m_n *m_n)
7160 struct drm_device *dev = crtc->base.dev;
7161 struct drm_i915_private *dev_priv = dev->dev_private;
7162 int pipe = crtc->pipe;
7164 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7165 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7166 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7167 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7170 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7171 struct intel_link_m_n *m_n,
7172 struct intel_link_m_n *m2_n2)
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 int pipe = crtc->pipe;
7177 enum transcoder transcoder = crtc->config->cpu_transcoder;
7179 if (INTEL_INFO(dev)->gen >= 5) {
7180 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7181 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7182 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7183 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7184 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7185 * for gen < 8) and if DRRS is supported (to make sure the
7186 * registers are not unnecessarily accessed).
7188 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7189 crtc->config->has_drrs) {
7190 I915_WRITE(PIPE_DATA_M2(transcoder),
7191 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7192 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7193 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7194 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7197 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7198 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7199 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7200 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7204 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7206 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7209 dp_m_n = &crtc->config->dp_m_n;
7210 dp_m2_n2 = &crtc->config->dp_m2_n2;
7211 } else if (m_n == M2_N2) {
7214 * M2_N2 registers are not supported. Hence m2_n2 divider value
7215 * needs to be programmed into M1_N1.
7217 dp_m_n = &crtc->config->dp_m2_n2;
7219 DRM_ERROR("Unsupported divider value\n");
7223 if (crtc->config->has_pch_encoder)
7224 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7226 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7229 static void vlv_compute_dpll(struct intel_crtc *crtc,
7230 struct intel_crtc_state *pipe_config)
7235 * Enable DPIO clock input. We should never disable the reference
7236 * clock for pipe B, since VGA hotplug / manual detection depends
7239 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7240 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7241 /* We should never disable this, set it here for state tracking */
7242 if (crtc->pipe == PIPE_B)
7243 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7244 dpll |= DPLL_VCO_ENABLE;
7245 pipe_config->dpll_hw_state.dpll = dpll;
7247 dpll_md = (pipe_config->pixel_multiplier - 1)
7248 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7249 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7252 static void vlv_prepare_pll(struct intel_crtc *crtc,
7253 const struct intel_crtc_state *pipe_config)
7255 struct drm_device *dev = crtc->base.dev;
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 int pipe = crtc->pipe;
7259 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7260 u32 coreclk, reg_val;
7262 mutex_lock(&dev_priv->sb_lock);
7264 bestn = pipe_config->dpll.n;
7265 bestm1 = pipe_config->dpll.m1;
7266 bestm2 = pipe_config->dpll.m2;
7267 bestp1 = pipe_config->dpll.p1;
7268 bestp2 = pipe_config->dpll.p2;
7270 /* See eDP HDMI DPIO driver vbios notes doc */
7272 /* PLL B needs special handling */
7274 vlv_pllb_recal_opamp(dev_priv, pipe);
7276 /* Set up Tx target for periodic Rcomp update */
7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7279 /* Disable target IRef on PLL */
7280 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7281 reg_val &= 0x00ffffff;
7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7284 /* Disable fast lock */
7285 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7287 /* Set idtafcrecal before PLL is enabled */
7288 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7289 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7290 mdiv |= ((bestn << DPIO_N_SHIFT));
7291 mdiv |= (1 << DPIO_K_SHIFT);
7294 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7295 * but we don't support that).
7296 * Note: don't use the DAC post divider as it seems unstable.
7298 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7301 mdiv |= DPIO_ENABLE_CALIBRATION;
7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7304 /* Set HBR and RBR LPF coefficients */
7305 if (pipe_config->port_clock == 162000 ||
7306 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7307 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7308 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7314 if (pipe_config->has_dp_encoder) {
7315 /* Use SSC source */
7317 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7322 } else { /* HDMI or VGA */
7323 /* Use bend source */
7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7328 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7332 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7333 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7334 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7335 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7336 coreclk |= 0x01000000;
7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7339 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7340 mutex_unlock(&dev_priv->sb_lock);
7343 static void chv_compute_dpll(struct intel_crtc *crtc,
7344 struct intel_crtc_state *pipe_config)
7346 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7347 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7349 if (crtc->pipe != PIPE_A)
7350 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7352 pipe_config->dpll_hw_state.dpll_md =
7353 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7356 static void chv_prepare_pll(struct intel_crtc *crtc,
7357 const struct intel_crtc_state *pipe_config)
7359 struct drm_device *dev = crtc->base.dev;
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 int pipe = crtc->pipe;
7362 int dpll_reg = DPLL(crtc->pipe);
7363 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7364 u32 loopfilter, tribuf_calcntr;
7365 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7369 bestn = pipe_config->dpll.n;
7370 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7371 bestm1 = pipe_config->dpll.m1;
7372 bestm2 = pipe_config->dpll.m2 >> 22;
7373 bestp1 = pipe_config->dpll.p1;
7374 bestp2 = pipe_config->dpll.p2;
7375 vco = pipe_config->dpll.vco;
7380 * Enable Refclk and SSC
7382 I915_WRITE(dpll_reg,
7383 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7385 mutex_lock(&dev_priv->sb_lock);
7387 /* p1 and p2 divider */
7388 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7389 5 << DPIO_CHV_S1_DIV_SHIFT |
7390 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7391 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7392 1 << DPIO_CHV_K_DIV_SHIFT);
7394 /* Feedback post-divider - m2 */
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7397 /* Feedback refclk divider - n and m1 */
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7399 DPIO_CHV_M1_DIV_BY_2 |
7400 1 << DPIO_CHV_N_DIV_SHIFT);
7402 /* M2 fraction division */
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7405 /* M2 fraction division enable */
7406 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7407 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7408 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7410 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7411 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7413 /* Program digital lock detect threshold */
7414 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7415 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7416 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7417 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7419 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7423 if (vco == 5400000) {
7424 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7425 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7426 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7427 tribuf_calcntr = 0x9;
7428 } else if (vco <= 6200000) {
7429 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7430 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7431 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7432 tribuf_calcntr = 0x9;
7433 } else if (vco <= 6480000) {
7434 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7435 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7436 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437 tribuf_calcntr = 0x8;
7439 /* Not supported. Apply the same limits as in the max case */
7440 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7441 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7442 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7447 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7448 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7449 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7450 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7453 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7454 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7457 mutex_unlock(&dev_priv->sb_lock);
7461 * vlv_force_pll_on - forcibly enable just the PLL
7462 * @dev_priv: i915 private structure
7463 * @pipe: pipe PLL to enable
7464 * @dpll: PLL configuration
7466 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7467 * in cases where we need the PLL enabled even when @pipe is not going to
7470 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7471 const struct dpll *dpll)
7473 struct intel_crtc *crtc =
7474 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7475 struct intel_crtc_state pipe_config = {
7476 .base.crtc = &crtc->base,
7477 .pixel_multiplier = 1,
7481 if (IS_CHERRYVIEW(dev)) {
7482 chv_compute_dpll(crtc, &pipe_config);
7483 chv_prepare_pll(crtc, &pipe_config);
7484 chv_enable_pll(crtc, &pipe_config);
7486 vlv_compute_dpll(crtc, &pipe_config);
7487 vlv_prepare_pll(crtc, &pipe_config);
7488 vlv_enable_pll(crtc, &pipe_config);
7493 * vlv_force_pll_off - forcibly disable just the PLL
7494 * @dev_priv: i915 private structure
7495 * @pipe: pipe PLL to disable
7497 * Disable the PLL for @pipe. To be used in cases where we need
7498 * the PLL enabled even when @pipe is not going to be enabled.
7500 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7502 if (IS_CHERRYVIEW(dev))
7503 chv_disable_pll(to_i915(dev), pipe);
7505 vlv_disable_pll(to_i915(dev), pipe);
7508 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7509 struct intel_crtc_state *crtc_state,
7510 intel_clock_t *reduced_clock,
7513 struct drm_device *dev = crtc->base.dev;
7514 struct drm_i915_private *dev_priv = dev->dev_private;
7517 struct dpll *clock = &crtc_state->dpll;
7519 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7521 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7522 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7524 dpll = DPLL_VGA_MODE_DIS;
7526 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7527 dpll |= DPLLB_MODE_LVDS;
7529 dpll |= DPLLB_MODE_DAC_SERIAL;
7531 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7532 dpll |= (crtc_state->pixel_multiplier - 1)
7533 << SDVO_MULTIPLIER_SHIFT_HIRES;
7537 dpll |= DPLL_SDVO_HIGH_SPEED;
7539 if (crtc_state->has_dp_encoder)
7540 dpll |= DPLL_SDVO_HIGH_SPEED;
7542 /* compute bitmask from p1 value */
7543 if (IS_PINEVIEW(dev))
7544 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7546 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7547 if (IS_G4X(dev) && reduced_clock)
7548 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7550 switch (clock->p2) {
7552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7564 if (INTEL_INFO(dev)->gen >= 4)
7565 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7567 if (crtc_state->sdvo_tv_clock)
7568 dpll |= PLL_REF_INPUT_TVCLKINBC;
7569 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7570 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7571 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7573 dpll |= PLL_REF_INPUT_DREFCLK;
7575 dpll |= DPLL_VCO_ENABLE;
7576 crtc_state->dpll_hw_state.dpll = dpll;
7578 if (INTEL_INFO(dev)->gen >= 4) {
7579 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7580 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7581 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7585 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7586 struct intel_crtc_state *crtc_state,
7587 intel_clock_t *reduced_clock,
7590 struct drm_device *dev = crtc->base.dev;
7591 struct drm_i915_private *dev_priv = dev->dev_private;
7593 struct dpll *clock = &crtc_state->dpll;
7595 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7597 dpll = DPLL_VGA_MODE_DIS;
7599 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7600 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7603 dpll |= PLL_P1_DIVIDE_BY_TWO;
7605 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7607 dpll |= PLL_P2_DIVIDE_BY_4;
7610 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7611 dpll |= DPLL_DVO_2X_MODE;
7613 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7614 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7615 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7617 dpll |= PLL_REF_INPUT_DREFCLK;
7619 dpll |= DPLL_VCO_ENABLE;
7620 crtc_state->dpll_hw_state.dpll = dpll;
7623 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7625 struct drm_device *dev = intel_crtc->base.dev;
7626 struct drm_i915_private *dev_priv = dev->dev_private;
7627 enum pipe pipe = intel_crtc->pipe;
7628 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7629 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7630 uint32_t crtc_vtotal, crtc_vblank_end;
7633 /* We need to be careful not to changed the adjusted mode, for otherwise
7634 * the hw state checker will get angry at the mismatch. */
7635 crtc_vtotal = adjusted_mode->crtc_vtotal;
7636 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7638 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7639 /* the chip adds 2 halflines automatically */
7641 crtc_vblank_end -= 1;
7643 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7644 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7646 vsyncshift = adjusted_mode->crtc_hsync_start -
7647 adjusted_mode->crtc_htotal / 2;
7649 vsyncshift += adjusted_mode->crtc_htotal;
7652 if (INTEL_INFO(dev)->gen > 3)
7653 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7655 I915_WRITE(HTOTAL(cpu_transcoder),
7656 (adjusted_mode->crtc_hdisplay - 1) |
7657 ((adjusted_mode->crtc_htotal - 1) << 16));
7658 I915_WRITE(HBLANK(cpu_transcoder),
7659 (adjusted_mode->crtc_hblank_start - 1) |
7660 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7661 I915_WRITE(HSYNC(cpu_transcoder),
7662 (adjusted_mode->crtc_hsync_start - 1) |
7663 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7665 I915_WRITE(VTOTAL(cpu_transcoder),
7666 (adjusted_mode->crtc_vdisplay - 1) |
7667 ((crtc_vtotal - 1) << 16));
7668 I915_WRITE(VBLANK(cpu_transcoder),
7669 (adjusted_mode->crtc_vblank_start - 1) |
7670 ((crtc_vblank_end - 1) << 16));
7671 I915_WRITE(VSYNC(cpu_transcoder),
7672 (adjusted_mode->crtc_vsync_start - 1) |
7673 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7675 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7676 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7677 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7679 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7680 (pipe == PIPE_B || pipe == PIPE_C))
7681 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7683 /* pipesrc controls the size that is scaled from, which should
7684 * always be the user's requested size.
7686 I915_WRITE(PIPESRC(pipe),
7687 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7688 (intel_crtc->config->pipe_src_h - 1));
7691 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7692 struct intel_crtc_state *pipe_config)
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7699 tmp = I915_READ(HTOTAL(cpu_transcoder));
7700 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7701 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7702 tmp = I915_READ(HBLANK(cpu_transcoder));
7703 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7704 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7705 tmp = I915_READ(HSYNC(cpu_transcoder));
7706 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7707 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7709 tmp = I915_READ(VTOTAL(cpu_transcoder));
7710 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7711 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7712 tmp = I915_READ(VBLANK(cpu_transcoder));
7713 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7714 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7715 tmp = I915_READ(VSYNC(cpu_transcoder));
7716 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7717 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7720 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7721 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7722 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7725 tmp = I915_READ(PIPESRC(crtc->pipe));
7726 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7727 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7729 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7730 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7733 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7734 struct intel_crtc_state *pipe_config)
7736 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7737 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7738 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7739 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7741 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7742 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7743 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7744 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7746 mode->flags = pipe_config->base.adjusted_mode.flags;
7747 mode->type = DRM_MODE_TYPE_DRIVER;
7749 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7750 mode->flags |= pipe_config->base.adjusted_mode.flags;
7752 mode->hsync = drm_mode_hsync(mode);
7753 mode->vrefresh = drm_mode_vrefresh(mode);
7754 drm_mode_set_name(mode);
7757 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7759 struct drm_device *dev = intel_crtc->base.dev;
7760 struct drm_i915_private *dev_priv = dev->dev_private;
7765 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7766 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7767 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7769 if (intel_crtc->config->double_wide)
7770 pipeconf |= PIPECONF_DOUBLE_WIDE;
7772 /* only g4x and later have fancy bpc/dither controls */
7773 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7774 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7775 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7776 pipeconf |= PIPECONF_DITHER_EN |
7777 PIPECONF_DITHER_TYPE_SP;
7779 switch (intel_crtc->config->pipe_bpp) {
7781 pipeconf |= PIPECONF_6BPC;
7784 pipeconf |= PIPECONF_8BPC;
7787 pipeconf |= PIPECONF_10BPC;
7790 /* Case prevented by intel_choose_pipe_bpp_dither. */
7795 if (HAS_PIPE_CXSR(dev)) {
7796 if (intel_crtc->lowfreq_avail) {
7797 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7798 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7800 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7804 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7805 if (INTEL_INFO(dev)->gen < 4 ||
7806 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7807 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7809 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7811 pipeconf |= PIPECONF_PROGRESSIVE;
7813 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7814 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7816 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7817 POSTING_READ(PIPECONF(intel_crtc->pipe));
7820 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7821 struct intel_crtc_state *crtc_state)
7823 struct drm_device *dev = crtc->base.dev;
7824 struct drm_i915_private *dev_priv = dev->dev_private;
7825 int refclk, num_connectors = 0;
7826 intel_clock_t clock;
7828 bool is_dsi = false;
7829 struct intel_encoder *encoder;
7830 const intel_limit_t *limit;
7831 struct drm_atomic_state *state = crtc_state->base.state;
7832 struct drm_connector *connector;
7833 struct drm_connector_state *connector_state;
7836 memset(&crtc_state->dpll_hw_state, 0,
7837 sizeof(crtc_state->dpll_hw_state));
7839 for_each_connector_in_state(state, connector, connector_state, i) {
7840 if (connector_state->crtc != &crtc->base)
7843 encoder = to_intel_encoder(connector_state->best_encoder);
7845 switch (encoder->type) {
7846 case INTEL_OUTPUT_DSI:
7859 if (!crtc_state->clock_set) {
7860 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7863 * Returns a set of divisors for the desired target clock with
7864 * the given refclk, or FALSE. The returned values represent
7865 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7868 limit = intel_limit(crtc_state, refclk);
7869 ok = dev_priv->display.find_dpll(limit, crtc_state,
7870 crtc_state->port_clock,
7871 refclk, NULL, &clock);
7873 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7877 /* Compat-code for transition, will disappear. */
7878 crtc_state->dpll.n = clock.n;
7879 crtc_state->dpll.m1 = clock.m1;
7880 crtc_state->dpll.m2 = clock.m2;
7881 crtc_state->dpll.p1 = clock.p1;
7882 crtc_state->dpll.p2 = clock.p2;
7886 i8xx_compute_dpll(crtc, crtc_state, NULL,
7888 } else if (IS_CHERRYVIEW(dev)) {
7889 chv_compute_dpll(crtc, crtc_state);
7890 } else if (IS_VALLEYVIEW(dev)) {
7891 vlv_compute_dpll(crtc, crtc_state);
7893 i9xx_compute_dpll(crtc, crtc_state, NULL,
7900 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7901 struct intel_crtc_state *pipe_config)
7903 struct drm_device *dev = crtc->base.dev;
7904 struct drm_i915_private *dev_priv = dev->dev_private;
7907 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7910 tmp = I915_READ(PFIT_CONTROL);
7911 if (!(tmp & PFIT_ENABLE))
7914 /* Check whether the pfit is attached to our pipe. */
7915 if (INTEL_INFO(dev)->gen < 4) {
7916 if (crtc->pipe != PIPE_B)
7919 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7923 pipe_config->gmch_pfit.control = tmp;
7924 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7925 if (INTEL_INFO(dev)->gen < 5)
7926 pipe_config->gmch_pfit.lvds_border_bits =
7927 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7930 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7931 struct intel_crtc_state *pipe_config)
7933 struct drm_device *dev = crtc->base.dev;
7934 struct drm_i915_private *dev_priv = dev->dev_private;
7935 int pipe = pipe_config->cpu_transcoder;
7936 intel_clock_t clock;
7938 int refclk = 100000;
7940 /* In case of MIPI DPLL will not even be used */
7941 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7944 mutex_lock(&dev_priv->sb_lock);
7945 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7946 mutex_unlock(&dev_priv->sb_lock);
7948 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7949 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7950 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7951 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7952 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7954 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7958 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7959 struct intel_initial_plane_config *plane_config)
7961 struct drm_device *dev = crtc->base.dev;
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 u32 val, base, offset;
7964 int pipe = crtc->pipe, plane = crtc->plane;
7965 int fourcc, pixel_format;
7966 unsigned int aligned_height;
7967 struct drm_framebuffer *fb;
7968 struct intel_framebuffer *intel_fb;
7970 val = I915_READ(DSPCNTR(plane));
7971 if (!(val & DISPLAY_PLANE_ENABLE))
7974 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7976 DRM_DEBUG_KMS("failed to alloc fb\n");
7980 fb = &intel_fb->base;
7982 if (INTEL_INFO(dev)->gen >= 4) {
7983 if (val & DISPPLANE_TILED) {
7984 plane_config->tiling = I915_TILING_X;
7985 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7989 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7990 fourcc = i9xx_format_to_fourcc(pixel_format);
7991 fb->pixel_format = fourcc;
7992 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7994 if (INTEL_INFO(dev)->gen >= 4) {
7995 if (plane_config->tiling)
7996 offset = I915_READ(DSPTILEOFF(plane));
7998 offset = I915_READ(DSPLINOFF(plane));
7999 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8001 base = I915_READ(DSPADDR(plane));
8003 plane_config->base = base;
8005 val = I915_READ(PIPESRC(pipe));
8006 fb->width = ((val >> 16) & 0xfff) + 1;
8007 fb->height = ((val >> 0) & 0xfff) + 1;
8009 val = I915_READ(DSPSTRIDE(pipe));
8010 fb->pitches[0] = val & 0xffffffc0;
8012 aligned_height = intel_fb_align_height(dev, fb->height,
8016 plane_config->size = fb->pitches[0] * aligned_height;
8018 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8019 pipe_name(pipe), plane, fb->width, fb->height,
8020 fb->bits_per_pixel, base, fb->pitches[0],
8021 plane_config->size);
8023 plane_config->fb = intel_fb;
8026 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8027 struct intel_crtc_state *pipe_config)
8029 struct drm_device *dev = crtc->base.dev;
8030 struct drm_i915_private *dev_priv = dev->dev_private;
8031 int pipe = pipe_config->cpu_transcoder;
8032 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8033 intel_clock_t clock;
8034 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8035 int refclk = 100000;
8037 mutex_lock(&dev_priv->sb_lock);
8038 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8039 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8040 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8041 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8042 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8043 mutex_unlock(&dev_priv->sb_lock);
8045 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8046 clock.m2 = (pll_dw0 & 0xff) << 22;
8047 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8048 clock.m2 |= pll_dw2 & 0x3fffff;
8049 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8050 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8051 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8053 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8056 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8057 struct intel_crtc_state *pipe_config)
8059 struct drm_device *dev = crtc->base.dev;
8060 struct drm_i915_private *dev_priv = dev->dev_private;
8063 if (!intel_display_power_is_enabled(dev_priv,
8064 POWER_DOMAIN_PIPE(crtc->pipe)))
8067 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8068 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8070 tmp = I915_READ(PIPECONF(crtc->pipe));
8071 if (!(tmp & PIPECONF_ENABLE))
8074 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8075 switch (tmp & PIPECONF_BPC_MASK) {
8077 pipe_config->pipe_bpp = 18;
8080 pipe_config->pipe_bpp = 24;
8082 case PIPECONF_10BPC:
8083 pipe_config->pipe_bpp = 30;
8090 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8091 pipe_config->limited_color_range = true;
8093 if (INTEL_INFO(dev)->gen < 4)
8094 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8096 intel_get_pipe_timings(crtc, pipe_config);
8098 i9xx_get_pfit_config(crtc, pipe_config);
8100 if (INTEL_INFO(dev)->gen >= 4) {
8101 tmp = I915_READ(DPLL_MD(crtc->pipe));
8102 pipe_config->pixel_multiplier =
8103 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8104 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8105 pipe_config->dpll_hw_state.dpll_md = tmp;
8106 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8107 tmp = I915_READ(DPLL(crtc->pipe));
8108 pipe_config->pixel_multiplier =
8109 ((tmp & SDVO_MULTIPLIER_MASK)
8110 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8112 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8113 * port and will be fixed up in the encoder->get_config
8115 pipe_config->pixel_multiplier = 1;
8117 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8118 if (!IS_VALLEYVIEW(dev)) {
8120 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8121 * on 830. Filter it out here so that we don't
8122 * report errors due to that.
8125 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8127 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8128 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8130 /* Mask out read-only status bits. */
8131 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8132 DPLL_PORTC_READY_MASK |
8133 DPLL_PORTB_READY_MASK);
8136 if (IS_CHERRYVIEW(dev))
8137 chv_crtc_clock_get(crtc, pipe_config);
8138 else if (IS_VALLEYVIEW(dev))
8139 vlv_crtc_clock_get(crtc, pipe_config);
8141 i9xx_crtc_clock_get(crtc, pipe_config);
8144 * Normally the dotclock is filled in by the encoder .get_config()
8145 * but in case the pipe is enabled w/o any ports we need a sane
8148 pipe_config->base.adjusted_mode.crtc_clock =
8149 pipe_config->port_clock / pipe_config->pixel_multiplier;
8154 static void ironlake_init_pch_refclk(struct drm_device *dev)
8156 struct drm_i915_private *dev_priv = dev->dev_private;
8157 struct intel_encoder *encoder;
8159 bool has_lvds = false;
8160 bool has_cpu_edp = false;
8161 bool has_panel = false;
8162 bool has_ck505 = false;
8163 bool can_ssc = false;
8165 /* We need to take the global config into account */
8166 for_each_intel_encoder(dev, encoder) {
8167 switch (encoder->type) {
8168 case INTEL_OUTPUT_LVDS:
8172 case INTEL_OUTPUT_EDP:
8174 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8182 if (HAS_PCH_IBX(dev)) {
8183 has_ck505 = dev_priv->vbt.display_clock_mode;
8184 can_ssc = has_ck505;
8190 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8191 has_panel, has_lvds, has_ck505);
8193 /* Ironlake: try to setup display ref clock before DPLL
8194 * enabling. This is only under driver's control after
8195 * PCH B stepping, previous chipset stepping should be
8196 * ignoring this setting.
8198 val = I915_READ(PCH_DREF_CONTROL);
8200 /* As we must carefully and slowly disable/enable each source in turn,
8201 * compute the final state we want first and check if we need to
8202 * make any changes at all.
8205 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8207 final |= DREF_NONSPREAD_CK505_ENABLE;
8209 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8211 final &= ~DREF_SSC_SOURCE_MASK;
8212 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8213 final &= ~DREF_SSC1_ENABLE;
8216 final |= DREF_SSC_SOURCE_ENABLE;
8218 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8219 final |= DREF_SSC1_ENABLE;
8222 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8223 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8225 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8227 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8229 final |= DREF_SSC_SOURCE_DISABLE;
8230 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8236 /* Always enable nonspread source */
8237 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8240 val |= DREF_NONSPREAD_CK505_ENABLE;
8242 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8245 val &= ~DREF_SSC_SOURCE_MASK;
8246 val |= DREF_SSC_SOURCE_ENABLE;
8248 /* SSC must be turned on before enabling the CPU output */
8249 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8250 DRM_DEBUG_KMS("Using SSC on panel\n");
8251 val |= DREF_SSC1_ENABLE;
8253 val &= ~DREF_SSC1_ENABLE;
8255 /* Get SSC going before enabling the outputs */
8256 I915_WRITE(PCH_DREF_CONTROL, val);
8257 POSTING_READ(PCH_DREF_CONTROL);
8260 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8262 /* Enable CPU source on CPU attached eDP */
8264 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8265 DRM_DEBUG_KMS("Using SSC on eDP\n");
8266 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8268 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8270 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8272 I915_WRITE(PCH_DREF_CONTROL, val);
8273 POSTING_READ(PCH_DREF_CONTROL);
8276 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8278 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8280 /* Turn off CPU output */
8281 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8283 I915_WRITE(PCH_DREF_CONTROL, val);
8284 POSTING_READ(PCH_DREF_CONTROL);
8287 /* Turn off the SSC source */
8288 val &= ~DREF_SSC_SOURCE_MASK;
8289 val |= DREF_SSC_SOURCE_DISABLE;
8292 val &= ~DREF_SSC1_ENABLE;
8294 I915_WRITE(PCH_DREF_CONTROL, val);
8295 POSTING_READ(PCH_DREF_CONTROL);
8299 BUG_ON(val != final);
8302 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8306 tmp = I915_READ(SOUTH_CHICKEN2);
8307 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8308 I915_WRITE(SOUTH_CHICKEN2, tmp);
8310 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8311 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8312 DRM_ERROR("FDI mPHY reset assert timeout\n");
8314 tmp = I915_READ(SOUTH_CHICKEN2);
8315 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8316 I915_WRITE(SOUTH_CHICKEN2, tmp);
8318 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8319 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8320 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8323 /* WaMPhyProgramming:hsw */
8324 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8328 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8329 tmp &= ~(0xFF << 24);
8330 tmp |= (0x12 << 24);
8331 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8333 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8335 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8337 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8339 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8341 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8342 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8343 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8345 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8346 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8347 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8349 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8352 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8354 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8357 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8359 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8362 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8364 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8367 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8369 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8370 tmp &= ~(0xFF << 16);
8371 tmp |= (0x1C << 16);
8372 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8374 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8375 tmp &= ~(0xFF << 16);
8376 tmp |= (0x1C << 16);
8377 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8379 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8381 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8383 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8385 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8387 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8388 tmp &= ~(0xF << 28);
8390 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8392 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8393 tmp &= ~(0xF << 28);
8395 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8398 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8399 * Programming" based on the parameters passed:
8400 * - Sequence to enable CLKOUT_DP
8401 * - Sequence to enable CLKOUT_DP without spread
8402 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8404 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8407 struct drm_i915_private *dev_priv = dev->dev_private;
8410 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8412 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8415 mutex_lock(&dev_priv->sb_lock);
8417 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8418 tmp &= ~SBI_SSCCTL_DISABLE;
8419 tmp |= SBI_SSCCTL_PATHALT;
8420 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8425 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8426 tmp &= ~SBI_SSCCTL_PATHALT;
8427 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8430 lpt_reset_fdi_mphy(dev_priv);
8431 lpt_program_fdi_mphy(dev_priv);
8435 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8436 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8437 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8438 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8440 mutex_unlock(&dev_priv->sb_lock);
8443 /* Sequence to disable CLKOUT_DP */
8444 static void lpt_disable_clkout_dp(struct drm_device *dev)
8446 struct drm_i915_private *dev_priv = dev->dev_private;
8449 mutex_lock(&dev_priv->sb_lock);
8451 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8452 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8453 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8454 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8456 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8457 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8458 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8459 tmp |= SBI_SSCCTL_PATHALT;
8460 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8463 tmp |= SBI_SSCCTL_DISABLE;
8464 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8467 mutex_unlock(&dev_priv->sb_lock);
8470 static void lpt_init_pch_refclk(struct drm_device *dev)
8472 struct intel_encoder *encoder;
8473 bool has_vga = false;
8475 for_each_intel_encoder(dev, encoder) {
8476 switch (encoder->type) {
8477 case INTEL_OUTPUT_ANALOG:
8486 lpt_enable_clkout_dp(dev, true, true);
8488 lpt_disable_clkout_dp(dev);
8492 * Initialize reference clocks when the driver loads
8494 void intel_init_pch_refclk(struct drm_device *dev)
8496 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8497 ironlake_init_pch_refclk(dev);
8498 else if (HAS_PCH_LPT(dev))
8499 lpt_init_pch_refclk(dev);
8502 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8504 struct drm_device *dev = crtc_state->base.crtc->dev;
8505 struct drm_i915_private *dev_priv = dev->dev_private;
8506 struct drm_atomic_state *state = crtc_state->base.state;
8507 struct drm_connector *connector;
8508 struct drm_connector_state *connector_state;
8509 struct intel_encoder *encoder;
8510 int num_connectors = 0, i;
8511 bool is_lvds = false;
8513 for_each_connector_in_state(state, connector, connector_state, i) {
8514 if (connector_state->crtc != crtc_state->base.crtc)
8517 encoder = to_intel_encoder(connector_state->best_encoder);
8519 switch (encoder->type) {
8520 case INTEL_OUTPUT_LVDS:
8529 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8530 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8531 dev_priv->vbt.lvds_ssc_freq);
8532 return dev_priv->vbt.lvds_ssc_freq;
8538 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8540 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8542 int pipe = intel_crtc->pipe;
8547 switch (intel_crtc->config->pipe_bpp) {
8549 val |= PIPECONF_6BPC;
8552 val |= PIPECONF_8BPC;
8555 val |= PIPECONF_10BPC;
8558 val |= PIPECONF_12BPC;
8561 /* Case prevented by intel_choose_pipe_bpp_dither. */
8565 if (intel_crtc->config->dither)
8566 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8568 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8569 val |= PIPECONF_INTERLACED_ILK;
8571 val |= PIPECONF_PROGRESSIVE;
8573 if (intel_crtc->config->limited_color_range)
8574 val |= PIPECONF_COLOR_RANGE_SELECT;
8576 I915_WRITE(PIPECONF(pipe), val);
8577 POSTING_READ(PIPECONF(pipe));
8581 * Set up the pipe CSC unit.
8583 * Currently only full range RGB to limited range RGB conversion
8584 * is supported, but eventually this should handle various
8585 * RGB<->YCbCr scenarios as well.
8587 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8589 struct drm_device *dev = crtc->dev;
8590 struct drm_i915_private *dev_priv = dev->dev_private;
8591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8592 int pipe = intel_crtc->pipe;
8593 uint16_t coeff = 0x7800; /* 1.0 */
8596 * TODO: Check what kind of values actually come out of the pipe
8597 * with these coeff/postoff values and adjust to get the best
8598 * accuracy. Perhaps we even need to take the bpc value into
8602 if (intel_crtc->config->limited_color_range)
8603 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8606 * GY/GU and RY/RU should be the other way around according
8607 * to BSpec, but reality doesn't agree. Just set them up in
8608 * a way that results in the correct picture.
8610 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8611 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8613 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8614 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8616 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8617 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8619 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8620 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8621 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8623 if (INTEL_INFO(dev)->gen > 6) {
8624 uint16_t postoff = 0;
8626 if (intel_crtc->config->limited_color_range)
8627 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8629 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8630 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8631 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8633 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8635 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8637 if (intel_crtc->config->limited_color_range)
8638 mode |= CSC_BLACK_SCREEN_OFFSET;
8640 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8644 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8646 struct drm_device *dev = crtc->dev;
8647 struct drm_i915_private *dev_priv = dev->dev_private;
8648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8649 enum pipe pipe = intel_crtc->pipe;
8650 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8655 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8656 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8658 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8659 val |= PIPECONF_INTERLACED_ILK;
8661 val |= PIPECONF_PROGRESSIVE;
8663 I915_WRITE(PIPECONF(cpu_transcoder), val);
8664 POSTING_READ(PIPECONF(cpu_transcoder));
8666 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8667 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8669 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8672 switch (intel_crtc->config->pipe_bpp) {
8674 val |= PIPEMISC_DITHER_6_BPC;
8677 val |= PIPEMISC_DITHER_8_BPC;
8680 val |= PIPEMISC_DITHER_10_BPC;
8683 val |= PIPEMISC_DITHER_12_BPC;
8686 /* Case prevented by pipe_config_set_bpp. */
8690 if (intel_crtc->config->dither)
8691 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8693 I915_WRITE(PIPEMISC(pipe), val);
8697 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8698 struct intel_crtc_state *crtc_state,
8699 intel_clock_t *clock,
8700 bool *has_reduced_clock,
8701 intel_clock_t *reduced_clock)
8703 struct drm_device *dev = crtc->dev;
8704 struct drm_i915_private *dev_priv = dev->dev_private;
8706 const intel_limit_t *limit;
8709 refclk = ironlake_get_refclk(crtc_state);
8712 * Returns a set of divisors for the desired target clock with the given
8713 * refclk, or FALSE. The returned values represent the clock equation:
8714 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8716 limit = intel_limit(crtc_state, refclk);
8717 ret = dev_priv->display.find_dpll(limit, crtc_state,
8718 crtc_state->port_clock,
8719 refclk, NULL, clock);
8726 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8729 * Account for spread spectrum to avoid
8730 * oversubscribing the link. Max center spread
8731 * is 2.5%; use 5% for safety's sake.
8733 u32 bps = target_clock * bpp * 21 / 20;
8734 return DIV_ROUND_UP(bps, link_bw * 8);
8737 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8739 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8742 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8743 struct intel_crtc_state *crtc_state,
8745 intel_clock_t *reduced_clock, u32 *fp2)
8747 struct drm_crtc *crtc = &intel_crtc->base;
8748 struct drm_device *dev = crtc->dev;
8749 struct drm_i915_private *dev_priv = dev->dev_private;
8750 struct drm_atomic_state *state = crtc_state->base.state;
8751 struct drm_connector *connector;
8752 struct drm_connector_state *connector_state;
8753 struct intel_encoder *encoder;
8755 int factor, num_connectors = 0, i;
8756 bool is_lvds = false, is_sdvo = false;
8758 for_each_connector_in_state(state, connector, connector_state, i) {
8759 if (connector_state->crtc != crtc_state->base.crtc)
8762 encoder = to_intel_encoder(connector_state->best_encoder);
8764 switch (encoder->type) {
8765 case INTEL_OUTPUT_LVDS:
8768 case INTEL_OUTPUT_SDVO:
8769 case INTEL_OUTPUT_HDMI:
8779 /* Enable autotuning of the PLL clock (if permissible) */
8782 if ((intel_panel_use_ssc(dev_priv) &&
8783 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8784 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8786 } else if (crtc_state->sdvo_tv_clock)
8789 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8792 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8798 dpll |= DPLLB_MODE_LVDS;
8800 dpll |= DPLLB_MODE_DAC_SERIAL;
8802 dpll |= (crtc_state->pixel_multiplier - 1)
8803 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8806 dpll |= DPLL_SDVO_HIGH_SPEED;
8807 if (crtc_state->has_dp_encoder)
8808 dpll |= DPLL_SDVO_HIGH_SPEED;
8810 /* compute bitmask from p1 value */
8811 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8813 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8815 switch (crtc_state->dpll.p2) {
8817 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8820 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8823 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8826 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8830 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8831 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8833 dpll |= PLL_REF_INPUT_DREFCLK;
8835 return dpll | DPLL_VCO_ENABLE;
8838 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8839 struct intel_crtc_state *crtc_state)
8841 struct drm_device *dev = crtc->base.dev;
8842 intel_clock_t clock, reduced_clock;
8843 u32 dpll = 0, fp = 0, fp2 = 0;
8844 bool ok, has_reduced_clock = false;
8845 bool is_lvds = false;
8846 struct intel_shared_dpll *pll;
8848 memset(&crtc_state->dpll_hw_state, 0,
8849 sizeof(crtc_state->dpll_hw_state));
8851 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8853 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8854 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8856 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8857 &has_reduced_clock, &reduced_clock);
8858 if (!ok && !crtc_state->clock_set) {
8859 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8862 /* Compat-code for transition, will disappear. */
8863 if (!crtc_state->clock_set) {
8864 crtc_state->dpll.n = clock.n;
8865 crtc_state->dpll.m1 = clock.m1;
8866 crtc_state->dpll.m2 = clock.m2;
8867 crtc_state->dpll.p1 = clock.p1;
8868 crtc_state->dpll.p2 = clock.p2;
8871 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8872 if (crtc_state->has_pch_encoder) {
8873 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8874 if (has_reduced_clock)
8875 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8877 dpll = ironlake_compute_dpll(crtc, crtc_state,
8878 &fp, &reduced_clock,
8879 has_reduced_clock ? &fp2 : NULL);
8881 crtc_state->dpll_hw_state.dpll = dpll;
8882 crtc_state->dpll_hw_state.fp0 = fp;
8883 if (has_reduced_clock)
8884 crtc_state->dpll_hw_state.fp1 = fp2;
8886 crtc_state->dpll_hw_state.fp1 = fp;
8888 pll = intel_get_shared_dpll(crtc, crtc_state);
8890 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8891 pipe_name(crtc->pipe));
8896 if (is_lvds && has_reduced_clock)
8897 crtc->lowfreq_avail = true;
8899 crtc->lowfreq_avail = false;
8904 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8905 struct intel_link_m_n *m_n)
8907 struct drm_device *dev = crtc->base.dev;
8908 struct drm_i915_private *dev_priv = dev->dev_private;
8909 enum pipe pipe = crtc->pipe;
8911 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8912 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8913 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8915 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8916 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8917 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8920 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8921 enum transcoder transcoder,
8922 struct intel_link_m_n *m_n,
8923 struct intel_link_m_n *m2_n2)
8925 struct drm_device *dev = crtc->base.dev;
8926 struct drm_i915_private *dev_priv = dev->dev_private;
8927 enum pipe pipe = crtc->pipe;
8929 if (INTEL_INFO(dev)->gen >= 5) {
8930 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8931 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8932 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8934 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8935 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8936 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8937 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8938 * gen < 8) and if DRRS is supported (to make sure the
8939 * registers are not unnecessarily read).
8941 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8942 crtc->config->has_drrs) {
8943 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8944 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8945 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8947 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8948 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8949 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8952 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8953 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8954 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8956 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8957 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8958 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8962 void intel_dp_get_m_n(struct intel_crtc *crtc,
8963 struct intel_crtc_state *pipe_config)
8965 if (pipe_config->has_pch_encoder)
8966 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8968 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8969 &pipe_config->dp_m_n,
8970 &pipe_config->dp_m2_n2);
8973 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8974 struct intel_crtc_state *pipe_config)
8976 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8977 &pipe_config->fdi_m_n, NULL);
8980 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8981 struct intel_crtc_state *pipe_config)
8983 struct drm_device *dev = crtc->base.dev;
8984 struct drm_i915_private *dev_priv = dev->dev_private;
8985 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8986 uint32_t ps_ctrl = 0;
8990 /* find scaler attached to this pipe */
8991 for (i = 0; i < crtc->num_scalers; i++) {
8992 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8993 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8995 pipe_config->pch_pfit.enabled = true;
8996 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8997 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9002 scaler_state->scaler_id = id;
9004 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9006 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9011 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9012 struct intel_initial_plane_config *plane_config)
9014 struct drm_device *dev = crtc->base.dev;
9015 struct drm_i915_private *dev_priv = dev->dev_private;
9016 u32 val, base, offset, stride_mult, tiling;
9017 int pipe = crtc->pipe;
9018 int fourcc, pixel_format;
9019 unsigned int aligned_height;
9020 struct drm_framebuffer *fb;
9021 struct intel_framebuffer *intel_fb;
9023 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9025 DRM_DEBUG_KMS("failed to alloc fb\n");
9029 fb = &intel_fb->base;
9031 val = I915_READ(PLANE_CTL(pipe, 0));
9032 if (!(val & PLANE_CTL_ENABLE))
9035 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9036 fourcc = skl_format_to_fourcc(pixel_format,
9037 val & PLANE_CTL_ORDER_RGBX,
9038 val & PLANE_CTL_ALPHA_MASK);
9039 fb->pixel_format = fourcc;
9040 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9042 tiling = val & PLANE_CTL_TILED_MASK;
9044 case PLANE_CTL_TILED_LINEAR:
9045 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9047 case PLANE_CTL_TILED_X:
9048 plane_config->tiling = I915_TILING_X;
9049 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9051 case PLANE_CTL_TILED_Y:
9052 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9054 case PLANE_CTL_TILED_YF:
9055 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9058 MISSING_CASE(tiling);
9062 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9063 plane_config->base = base;
9065 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9067 val = I915_READ(PLANE_SIZE(pipe, 0));
9068 fb->height = ((val >> 16) & 0xfff) + 1;
9069 fb->width = ((val >> 0) & 0x1fff) + 1;
9071 val = I915_READ(PLANE_STRIDE(pipe, 0));
9072 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9074 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9076 aligned_height = intel_fb_align_height(dev, fb->height,
9080 plane_config->size = fb->pitches[0] * aligned_height;
9082 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9083 pipe_name(pipe), fb->width, fb->height,
9084 fb->bits_per_pixel, base, fb->pitches[0],
9085 plane_config->size);
9087 plane_config->fb = intel_fb;
9094 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9095 struct intel_crtc_state *pipe_config)
9097 struct drm_device *dev = crtc->base.dev;
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9101 tmp = I915_READ(PF_CTL(crtc->pipe));
9103 if (tmp & PF_ENABLE) {
9104 pipe_config->pch_pfit.enabled = true;
9105 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9106 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9108 /* We currently do not free assignements of panel fitters on
9109 * ivb/hsw (since we don't use the higher upscaling modes which
9110 * differentiates them) so just WARN about this case for now. */
9112 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9113 PF_PIPE_SEL_IVB(crtc->pipe));
9119 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9120 struct intel_initial_plane_config *plane_config)
9122 struct drm_device *dev = crtc->base.dev;
9123 struct drm_i915_private *dev_priv = dev->dev_private;
9124 u32 val, base, offset;
9125 int pipe = crtc->pipe;
9126 int fourcc, pixel_format;
9127 unsigned int aligned_height;
9128 struct drm_framebuffer *fb;
9129 struct intel_framebuffer *intel_fb;
9131 val = I915_READ(DSPCNTR(pipe));
9132 if (!(val & DISPLAY_PLANE_ENABLE))
9135 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9137 DRM_DEBUG_KMS("failed to alloc fb\n");
9141 fb = &intel_fb->base;
9143 if (INTEL_INFO(dev)->gen >= 4) {
9144 if (val & DISPPLANE_TILED) {
9145 plane_config->tiling = I915_TILING_X;
9146 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9150 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9151 fourcc = i9xx_format_to_fourcc(pixel_format);
9152 fb->pixel_format = fourcc;
9153 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9155 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9156 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9157 offset = I915_READ(DSPOFFSET(pipe));
9159 if (plane_config->tiling)
9160 offset = I915_READ(DSPTILEOFF(pipe));
9162 offset = I915_READ(DSPLINOFF(pipe));
9164 plane_config->base = base;
9166 val = I915_READ(PIPESRC(pipe));
9167 fb->width = ((val >> 16) & 0xfff) + 1;
9168 fb->height = ((val >> 0) & 0xfff) + 1;
9170 val = I915_READ(DSPSTRIDE(pipe));
9171 fb->pitches[0] = val & 0xffffffc0;
9173 aligned_height = intel_fb_align_height(dev, fb->height,
9177 plane_config->size = fb->pitches[0] * aligned_height;
9179 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9180 pipe_name(pipe), fb->width, fb->height,
9181 fb->bits_per_pixel, base, fb->pitches[0],
9182 plane_config->size);
9184 plane_config->fb = intel_fb;
9187 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9188 struct intel_crtc_state *pipe_config)
9190 struct drm_device *dev = crtc->base.dev;
9191 struct drm_i915_private *dev_priv = dev->dev_private;
9194 if (!intel_display_power_is_enabled(dev_priv,
9195 POWER_DOMAIN_PIPE(crtc->pipe)))
9198 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9199 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9201 tmp = I915_READ(PIPECONF(crtc->pipe));
9202 if (!(tmp & PIPECONF_ENABLE))
9205 switch (tmp & PIPECONF_BPC_MASK) {
9207 pipe_config->pipe_bpp = 18;
9210 pipe_config->pipe_bpp = 24;
9212 case PIPECONF_10BPC:
9213 pipe_config->pipe_bpp = 30;
9215 case PIPECONF_12BPC:
9216 pipe_config->pipe_bpp = 36;
9222 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9223 pipe_config->limited_color_range = true;
9225 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9226 struct intel_shared_dpll *pll;
9228 pipe_config->has_pch_encoder = true;
9230 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9231 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9232 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9234 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9236 if (HAS_PCH_IBX(dev_priv->dev)) {
9237 pipe_config->shared_dpll =
9238 (enum intel_dpll_id) crtc->pipe;
9240 tmp = I915_READ(PCH_DPLL_SEL);
9241 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9242 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9244 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9247 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9249 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9250 &pipe_config->dpll_hw_state));
9252 tmp = pipe_config->dpll_hw_state.dpll;
9253 pipe_config->pixel_multiplier =
9254 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9255 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9257 ironlake_pch_clock_get(crtc, pipe_config);
9259 pipe_config->pixel_multiplier = 1;
9262 intel_get_pipe_timings(crtc, pipe_config);
9264 ironlake_get_pfit_config(crtc, pipe_config);
9269 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9271 struct drm_device *dev = dev_priv->dev;
9272 struct intel_crtc *crtc;
9274 for_each_intel_crtc(dev, crtc)
9275 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9276 pipe_name(crtc->pipe));
9278 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9279 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9280 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9281 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9282 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9283 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9284 "CPU PWM1 enabled\n");
9285 if (IS_HASWELL(dev))
9286 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9287 "CPU PWM2 enabled\n");
9288 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9289 "PCH PWM1 enabled\n");
9290 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9291 "Utility pin enabled\n");
9292 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9295 * In theory we can still leave IRQs enabled, as long as only the HPD
9296 * interrupts remain enabled. We used to check for that, but since it's
9297 * gen-specific and since we only disable LCPLL after we fully disable
9298 * the interrupts, the check below should be enough.
9300 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9303 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9305 struct drm_device *dev = dev_priv->dev;
9307 if (IS_HASWELL(dev))
9308 return I915_READ(D_COMP_HSW);
9310 return I915_READ(D_COMP_BDW);
9313 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9315 struct drm_device *dev = dev_priv->dev;
9317 if (IS_HASWELL(dev)) {
9318 mutex_lock(&dev_priv->rps.hw_lock);
9319 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9321 DRM_ERROR("Failed to write to D_COMP\n");
9322 mutex_unlock(&dev_priv->rps.hw_lock);
9324 I915_WRITE(D_COMP_BDW, val);
9325 POSTING_READ(D_COMP_BDW);
9330 * This function implements pieces of two sequences from BSpec:
9331 * - Sequence for display software to disable LCPLL
9332 * - Sequence for display software to allow package C8+
9333 * The steps implemented here are just the steps that actually touch the LCPLL
9334 * register. Callers should take care of disabling all the display engine
9335 * functions, doing the mode unset, fixing interrupts, etc.
9337 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9338 bool switch_to_fclk, bool allow_power_down)
9342 assert_can_disable_lcpll(dev_priv);
9344 val = I915_READ(LCPLL_CTL);
9346 if (switch_to_fclk) {
9347 val |= LCPLL_CD_SOURCE_FCLK;
9348 I915_WRITE(LCPLL_CTL, val);
9350 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9351 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9352 DRM_ERROR("Switching to FCLK failed\n");
9354 val = I915_READ(LCPLL_CTL);
9357 val |= LCPLL_PLL_DISABLE;
9358 I915_WRITE(LCPLL_CTL, val);
9359 POSTING_READ(LCPLL_CTL);
9361 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9362 DRM_ERROR("LCPLL still locked\n");
9364 val = hsw_read_dcomp(dev_priv);
9365 val |= D_COMP_COMP_DISABLE;
9366 hsw_write_dcomp(dev_priv, val);
9369 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9371 DRM_ERROR("D_COMP RCOMP still in progress\n");
9373 if (allow_power_down) {
9374 val = I915_READ(LCPLL_CTL);
9375 val |= LCPLL_POWER_DOWN_ALLOW;
9376 I915_WRITE(LCPLL_CTL, val);
9377 POSTING_READ(LCPLL_CTL);
9382 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9385 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9389 val = I915_READ(LCPLL_CTL);
9391 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9392 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9396 * Make sure we're not on PC8 state before disabling PC8, otherwise
9397 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9399 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9401 if (val & LCPLL_POWER_DOWN_ALLOW) {
9402 val &= ~LCPLL_POWER_DOWN_ALLOW;
9403 I915_WRITE(LCPLL_CTL, val);
9404 POSTING_READ(LCPLL_CTL);
9407 val = hsw_read_dcomp(dev_priv);
9408 val |= D_COMP_COMP_FORCE;
9409 val &= ~D_COMP_COMP_DISABLE;
9410 hsw_write_dcomp(dev_priv, val);
9412 val = I915_READ(LCPLL_CTL);
9413 val &= ~LCPLL_PLL_DISABLE;
9414 I915_WRITE(LCPLL_CTL, val);
9416 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9417 DRM_ERROR("LCPLL not locked yet\n");
9419 if (val & LCPLL_CD_SOURCE_FCLK) {
9420 val = I915_READ(LCPLL_CTL);
9421 val &= ~LCPLL_CD_SOURCE_FCLK;
9422 I915_WRITE(LCPLL_CTL, val);
9424 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9425 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9426 DRM_ERROR("Switching back to LCPLL failed\n");
9429 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9430 intel_update_cdclk(dev_priv->dev);
9434 * Package states C8 and deeper are really deep PC states that can only be
9435 * reached when all the devices on the system allow it, so even if the graphics
9436 * device allows PC8+, it doesn't mean the system will actually get to these
9437 * states. Our driver only allows PC8+ when going into runtime PM.
9439 * The requirements for PC8+ are that all the outputs are disabled, the power
9440 * well is disabled and most interrupts are disabled, and these are also
9441 * requirements for runtime PM. When these conditions are met, we manually do
9442 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9443 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9446 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9447 * the state of some registers, so when we come back from PC8+ we need to
9448 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9449 * need to take care of the registers kept by RC6. Notice that this happens even
9450 * if we don't put the device in PCI D3 state (which is what currently happens
9451 * because of the runtime PM support).
9453 * For more, read "Display Sequences for Package C8" on the hardware
9456 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9458 struct drm_device *dev = dev_priv->dev;
9461 DRM_DEBUG_KMS("Enabling package C8+\n");
9463 if (HAS_PCH_LPT_LP(dev)) {
9464 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9465 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9466 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9469 lpt_disable_clkout_dp(dev);
9470 hsw_disable_lcpll(dev_priv, true, true);
9473 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9475 struct drm_device *dev = dev_priv->dev;
9478 DRM_DEBUG_KMS("Disabling package C8+\n");
9480 hsw_restore_lcpll(dev_priv);
9481 lpt_init_pch_refclk(dev);
9483 if (HAS_PCH_LPT_LP(dev)) {
9484 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9485 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9486 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9489 intel_prepare_ddi(dev);
9492 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9494 struct drm_device *dev = old_state->dev;
9495 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9497 broxton_set_cdclk(dev, req_cdclk);
9500 /* compute the max rate for new configuration */
9501 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9503 struct intel_crtc *intel_crtc;
9504 struct intel_crtc_state *crtc_state;
9505 int max_pixel_rate = 0;
9507 for_each_intel_crtc(state->dev, intel_crtc) {
9510 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9511 if (IS_ERR(crtc_state))
9512 return PTR_ERR(crtc_state);
9514 if (!crtc_state->base.enable)
9517 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9519 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9520 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9521 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9523 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9526 return max_pixel_rate;
9529 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9531 struct drm_i915_private *dev_priv = dev->dev_private;
9535 if (WARN((I915_READ(LCPLL_CTL) &
9536 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9537 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9538 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9539 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9540 "trying to change cdclk frequency with cdclk not enabled\n"))
9543 mutex_lock(&dev_priv->rps.hw_lock);
9544 ret = sandybridge_pcode_write(dev_priv,
9545 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9546 mutex_unlock(&dev_priv->rps.hw_lock);
9548 DRM_ERROR("failed to inform pcode about cdclk change\n");
9552 val = I915_READ(LCPLL_CTL);
9553 val |= LCPLL_CD_SOURCE_FCLK;
9554 I915_WRITE(LCPLL_CTL, val);
9556 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9557 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9558 DRM_ERROR("Switching to FCLK failed\n");
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CLK_FREQ_MASK;
9565 val |= LCPLL_CLK_FREQ_450;
9569 val |= LCPLL_CLK_FREQ_54O_BDW;
9573 val |= LCPLL_CLK_FREQ_337_5_BDW;
9577 val |= LCPLL_CLK_FREQ_675_BDW;
9581 WARN(1, "invalid cdclk frequency\n");
9585 I915_WRITE(LCPLL_CTL, val);
9587 val = I915_READ(LCPLL_CTL);
9588 val &= ~LCPLL_CD_SOURCE_FCLK;
9589 I915_WRITE(LCPLL_CTL, val);
9591 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9592 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9593 DRM_ERROR("Switching back to LCPLL failed\n");
9595 mutex_lock(&dev_priv->rps.hw_lock);
9596 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9597 mutex_unlock(&dev_priv->rps.hw_lock);
9599 intel_update_cdclk(dev);
9601 WARN(cdclk != dev_priv->cdclk_freq,
9602 "cdclk requested %d kHz but got %d kHz\n",
9603 cdclk, dev_priv->cdclk_freq);
9606 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9608 struct drm_i915_private *dev_priv = to_i915(state->dev);
9609 int max_pixclk = ilk_max_pixel_rate(state);
9613 * FIXME should also account for plane ratio
9614 * once 64bpp pixel formats are supported.
9616 if (max_pixclk > 540000)
9618 else if (max_pixclk > 450000)
9620 else if (max_pixclk > 337500)
9626 * FIXME move the cdclk caclulation to
9627 * compute_config() so we can fail gracegully.
9629 if (cdclk > dev_priv->max_cdclk_freq) {
9630 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9631 cdclk, dev_priv->max_cdclk_freq);
9632 cdclk = dev_priv->max_cdclk_freq;
9635 to_intel_atomic_state(state)->cdclk = cdclk;
9640 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9642 struct drm_device *dev = old_state->dev;
9643 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9645 broadwell_set_cdclk(dev, req_cdclk);
9648 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9649 struct intel_crtc_state *crtc_state)
9651 if (!intel_ddi_pll_select(crtc, crtc_state))
9654 crtc->lowfreq_avail = false;
9659 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9661 struct intel_crtc_state *pipe_config)
9665 pipe_config->ddi_pll_sel = SKL_DPLL0;
9666 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9669 pipe_config->ddi_pll_sel = SKL_DPLL1;
9670 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9673 pipe_config->ddi_pll_sel = SKL_DPLL2;
9674 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9677 DRM_ERROR("Incorrect port type\n");
9681 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9683 struct intel_crtc_state *pipe_config)
9685 u32 temp, dpll_ctl1;
9687 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9688 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9690 switch (pipe_config->ddi_pll_sel) {
9693 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9694 * of the shared DPLL framework and thus needs to be read out
9697 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9698 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9701 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9704 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9707 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9712 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9714 struct intel_crtc_state *pipe_config)
9716 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9718 switch (pipe_config->ddi_pll_sel) {
9719 case PORT_CLK_SEL_WRPLL1:
9720 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9722 case PORT_CLK_SEL_WRPLL2:
9723 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9728 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9729 struct intel_crtc_state *pipe_config)
9731 struct drm_device *dev = crtc->base.dev;
9732 struct drm_i915_private *dev_priv = dev->dev_private;
9733 struct intel_shared_dpll *pll;
9737 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9739 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9741 if (IS_SKYLAKE(dev))
9742 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9743 else if (IS_BROXTON(dev))
9744 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9746 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9748 if (pipe_config->shared_dpll >= 0) {
9749 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9751 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9752 &pipe_config->dpll_hw_state));
9756 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9757 * DDI E. So just check whether this pipe is wired to DDI E and whether
9758 * the PCH transcoder is on.
9760 if (INTEL_INFO(dev)->gen < 9 &&
9761 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9762 pipe_config->has_pch_encoder = true;
9764 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9765 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9766 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9768 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9772 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9773 struct intel_crtc_state *pipe_config)
9775 struct drm_device *dev = crtc->base.dev;
9776 struct drm_i915_private *dev_priv = dev->dev_private;
9777 enum intel_display_power_domain pfit_domain;
9780 if (!intel_display_power_is_enabled(dev_priv,
9781 POWER_DOMAIN_PIPE(crtc->pipe)))
9784 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9785 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9787 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9788 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9789 enum pipe trans_edp_pipe;
9790 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9792 WARN(1, "unknown pipe linked to edp transcoder\n");
9793 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9794 case TRANS_DDI_EDP_INPUT_A_ON:
9795 trans_edp_pipe = PIPE_A;
9797 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9798 trans_edp_pipe = PIPE_B;
9800 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9801 trans_edp_pipe = PIPE_C;
9805 if (trans_edp_pipe == crtc->pipe)
9806 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9809 if (!intel_display_power_is_enabled(dev_priv,
9810 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9813 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9814 if (!(tmp & PIPECONF_ENABLE))
9817 haswell_get_ddi_port_state(crtc, pipe_config);
9819 intel_get_pipe_timings(crtc, pipe_config);
9821 if (INTEL_INFO(dev)->gen >= 9) {
9822 skl_init_scalers(dev, crtc, pipe_config);
9825 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9827 if (INTEL_INFO(dev)->gen >= 9) {
9828 pipe_config->scaler_state.scaler_id = -1;
9829 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9832 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9833 if (INTEL_INFO(dev)->gen >= 9)
9834 skylake_get_pfit_config(crtc, pipe_config);
9836 ironlake_get_pfit_config(crtc, pipe_config);
9839 if (IS_HASWELL(dev))
9840 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9841 (I915_READ(IPS_CTL) & IPS_ENABLE);
9843 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9844 pipe_config->pixel_multiplier =
9845 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9847 pipe_config->pixel_multiplier = 1;
9853 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9855 struct drm_device *dev = crtc->dev;
9856 struct drm_i915_private *dev_priv = dev->dev_private;
9857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9858 uint32_t cntl = 0, size = 0;
9861 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9862 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9863 unsigned int stride = roundup_pow_of_two(width) * 4;
9867 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9878 cntl |= CURSOR_ENABLE |
9879 CURSOR_GAMMA_ENABLE |
9880 CURSOR_FORMAT_ARGB |
9881 CURSOR_STRIDE(stride);
9883 size = (height << 12) | width;
9886 if (intel_crtc->cursor_cntl != 0 &&
9887 (intel_crtc->cursor_base != base ||
9888 intel_crtc->cursor_size != size ||
9889 intel_crtc->cursor_cntl != cntl)) {
9890 /* On these chipsets we can only modify the base/size/stride
9891 * whilst the cursor is disabled.
9893 I915_WRITE(CURCNTR(PIPE_A), 0);
9894 POSTING_READ(CURCNTR(PIPE_A));
9895 intel_crtc->cursor_cntl = 0;
9898 if (intel_crtc->cursor_base != base) {
9899 I915_WRITE(CURBASE(PIPE_A), base);
9900 intel_crtc->cursor_base = base;
9903 if (intel_crtc->cursor_size != size) {
9904 I915_WRITE(CURSIZE, size);
9905 intel_crtc->cursor_size = size;
9908 if (intel_crtc->cursor_cntl != cntl) {
9909 I915_WRITE(CURCNTR(PIPE_A), cntl);
9910 POSTING_READ(CURCNTR(PIPE_A));
9911 intel_crtc->cursor_cntl = cntl;
9915 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9917 struct drm_device *dev = crtc->dev;
9918 struct drm_i915_private *dev_priv = dev->dev_private;
9919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9920 int pipe = intel_crtc->pipe;
9925 cntl = MCURSOR_GAMMA_ENABLE;
9926 switch (intel_crtc->base.cursor->state->crtc_w) {
9928 cntl |= CURSOR_MODE_64_ARGB_AX;
9931 cntl |= CURSOR_MODE_128_ARGB_AX;
9934 cntl |= CURSOR_MODE_256_ARGB_AX;
9937 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9940 cntl |= pipe << 28; /* Connect to correct pipe */
9942 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9943 cntl |= CURSOR_PIPE_CSC_ENABLE;
9946 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9947 cntl |= CURSOR_ROTATE_180;
9949 if (intel_crtc->cursor_cntl != cntl) {
9950 I915_WRITE(CURCNTR(pipe), cntl);
9951 POSTING_READ(CURCNTR(pipe));
9952 intel_crtc->cursor_cntl = cntl;
9955 /* and commit changes on next vblank */
9956 I915_WRITE(CURBASE(pipe), base);
9957 POSTING_READ(CURBASE(pipe));
9959 intel_crtc->cursor_base = base;
9962 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9963 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9966 struct drm_device *dev = crtc->dev;
9967 struct drm_i915_private *dev_priv = dev->dev_private;
9968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9969 int pipe = intel_crtc->pipe;
9970 struct drm_plane_state *cursor_state = crtc->cursor->state;
9971 int x = cursor_state->crtc_x;
9972 int y = cursor_state->crtc_y;
9973 u32 base = 0, pos = 0;
9976 base = intel_crtc->cursor_addr;
9978 if (x >= intel_crtc->config->pipe_src_w)
9981 if (y >= intel_crtc->config->pipe_src_h)
9985 if (x + cursor_state->crtc_w <= 0)
9988 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9991 pos |= x << CURSOR_X_SHIFT;
9994 if (y + cursor_state->crtc_h <= 0)
9997 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10000 pos |= y << CURSOR_Y_SHIFT;
10002 if (base == 0 && intel_crtc->cursor_base == 0)
10005 I915_WRITE(CURPOS(pipe), pos);
10007 /* ILK+ do this automagically */
10008 if (HAS_GMCH_DISPLAY(dev) &&
10009 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10010 base += (cursor_state->crtc_h *
10011 cursor_state->crtc_w - 1) * 4;
10014 if (IS_845G(dev) || IS_I865G(dev))
10015 i845_update_cursor(crtc, base);
10017 i9xx_update_cursor(crtc, base);
10020 static bool cursor_size_ok(struct drm_device *dev,
10021 uint32_t width, uint32_t height)
10023 if (width == 0 || height == 0)
10027 * 845g/865g are special in that they are only limited by
10028 * the width of their cursors, the height is arbitrary up to
10029 * the precision of the register. Everything else requires
10030 * square cursors, limited to a few power-of-two sizes.
10032 if (IS_845G(dev) || IS_I865G(dev)) {
10033 if ((width & 63) != 0)
10036 if (width > (IS_845G(dev) ? 64 : 512))
10042 switch (width | height) {
10057 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10058 u16 *blue, uint32_t start, uint32_t size)
10060 int end = (start + size > 256) ? 256 : start + size, i;
10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063 for (i = start; i < end; i++) {
10064 intel_crtc->lut_r[i] = red[i] >> 8;
10065 intel_crtc->lut_g[i] = green[i] >> 8;
10066 intel_crtc->lut_b[i] = blue[i] >> 8;
10069 intel_crtc_load_lut(crtc);
10072 /* VESA 640x480x72Hz mode to set on the pipe */
10073 static struct drm_display_mode load_detect_mode = {
10074 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10075 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10078 struct drm_framebuffer *
10079 __intel_framebuffer_create(struct drm_device *dev,
10080 struct drm_mode_fb_cmd2 *mode_cmd,
10081 struct drm_i915_gem_object *obj)
10083 struct intel_framebuffer *intel_fb;
10086 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10088 drm_gem_object_unreference(&obj->base);
10089 return ERR_PTR(-ENOMEM);
10092 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10096 return &intel_fb->base;
10098 drm_gem_object_unreference(&obj->base);
10101 return ERR_PTR(ret);
10104 static struct drm_framebuffer *
10105 intel_framebuffer_create(struct drm_device *dev,
10106 struct drm_mode_fb_cmd2 *mode_cmd,
10107 struct drm_i915_gem_object *obj)
10109 struct drm_framebuffer *fb;
10112 ret = i915_mutex_lock_interruptible(dev);
10114 return ERR_PTR(ret);
10115 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10116 mutex_unlock(&dev->struct_mutex);
10122 intel_framebuffer_pitch_for_width(int width, int bpp)
10124 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10125 return ALIGN(pitch, 64);
10129 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10131 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10132 return PAGE_ALIGN(pitch * mode->vdisplay);
10135 static struct drm_framebuffer *
10136 intel_framebuffer_create_for_mode(struct drm_device *dev,
10137 struct drm_display_mode *mode,
10138 int depth, int bpp)
10140 struct drm_i915_gem_object *obj;
10141 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10143 obj = i915_gem_alloc_object(dev,
10144 intel_framebuffer_size_for_mode(mode, bpp));
10146 return ERR_PTR(-ENOMEM);
10148 mode_cmd.width = mode->hdisplay;
10149 mode_cmd.height = mode->vdisplay;
10150 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10152 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10154 return intel_framebuffer_create(dev, &mode_cmd, obj);
10157 static struct drm_framebuffer *
10158 mode_fits_in_fbdev(struct drm_device *dev,
10159 struct drm_display_mode *mode)
10161 #ifdef CONFIG_DRM_FBDEV_EMULATION
10162 struct drm_i915_private *dev_priv = dev->dev_private;
10163 struct drm_i915_gem_object *obj;
10164 struct drm_framebuffer *fb;
10166 if (!dev_priv->fbdev)
10169 if (!dev_priv->fbdev->fb)
10172 obj = dev_priv->fbdev->fb->obj;
10175 fb = &dev_priv->fbdev->fb->base;
10176 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10177 fb->bits_per_pixel))
10180 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10189 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10190 struct drm_crtc *crtc,
10191 struct drm_display_mode *mode,
10192 struct drm_framebuffer *fb,
10195 struct drm_plane_state *plane_state;
10196 int hdisplay, vdisplay;
10199 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10200 if (IS_ERR(plane_state))
10201 return PTR_ERR(plane_state);
10204 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10206 hdisplay = vdisplay = 0;
10208 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10211 drm_atomic_set_fb_for_plane(plane_state, fb);
10212 plane_state->crtc_x = 0;
10213 plane_state->crtc_y = 0;
10214 plane_state->crtc_w = hdisplay;
10215 plane_state->crtc_h = vdisplay;
10216 plane_state->src_x = x << 16;
10217 plane_state->src_y = y << 16;
10218 plane_state->src_w = hdisplay << 16;
10219 plane_state->src_h = vdisplay << 16;
10224 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10225 struct drm_display_mode *mode,
10226 struct intel_load_detect_pipe *old,
10227 struct drm_modeset_acquire_ctx *ctx)
10229 struct intel_crtc *intel_crtc;
10230 struct intel_encoder *intel_encoder =
10231 intel_attached_encoder(connector);
10232 struct drm_crtc *possible_crtc;
10233 struct drm_encoder *encoder = &intel_encoder->base;
10234 struct drm_crtc *crtc = NULL;
10235 struct drm_device *dev = encoder->dev;
10236 struct drm_framebuffer *fb;
10237 struct drm_mode_config *config = &dev->mode_config;
10238 struct drm_atomic_state *state = NULL;
10239 struct drm_connector_state *connector_state;
10240 struct intel_crtc_state *crtc_state;
10243 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10244 connector->base.id, connector->name,
10245 encoder->base.id, encoder->name);
10248 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10253 * Algorithm gets a little messy:
10255 * - if the connector already has an assigned crtc, use it (but make
10256 * sure it's on first)
10258 * - try to find the first unused crtc that can drive this connector,
10259 * and use that if we find one
10262 /* See if we already have a CRTC for this connector */
10263 if (encoder->crtc) {
10264 crtc = encoder->crtc;
10266 ret = drm_modeset_lock(&crtc->mutex, ctx);
10269 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10273 old->dpms_mode = connector->dpms;
10274 old->load_detect_temp = false;
10276 /* Make sure the crtc and connector are running */
10277 if (connector->dpms != DRM_MODE_DPMS_ON)
10278 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10283 /* Find an unused one (if possible) */
10284 for_each_crtc(dev, possible_crtc) {
10286 if (!(encoder->possible_crtcs & (1 << i)))
10288 if (possible_crtc->state->enable)
10291 crtc = possible_crtc;
10296 * If we didn't find an unused CRTC, don't use any.
10299 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10303 ret = drm_modeset_lock(&crtc->mutex, ctx);
10306 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10310 intel_crtc = to_intel_crtc(crtc);
10311 old->dpms_mode = connector->dpms;
10312 old->load_detect_temp = true;
10313 old->release_fb = NULL;
10315 state = drm_atomic_state_alloc(dev);
10319 state->acquire_ctx = ctx;
10321 connector_state = drm_atomic_get_connector_state(state, connector);
10322 if (IS_ERR(connector_state)) {
10323 ret = PTR_ERR(connector_state);
10327 connector_state->crtc = crtc;
10328 connector_state->best_encoder = &intel_encoder->base;
10330 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10331 if (IS_ERR(crtc_state)) {
10332 ret = PTR_ERR(crtc_state);
10336 crtc_state->base.active = crtc_state->base.enable = true;
10339 mode = &load_detect_mode;
10341 /* We need a framebuffer large enough to accommodate all accesses
10342 * that the plane may generate whilst we perform load detection.
10343 * We can not rely on the fbcon either being present (we get called
10344 * during its initialisation to detect all boot displays, or it may
10345 * not even exist) or that it is large enough to satisfy the
10348 fb = mode_fits_in_fbdev(dev, mode);
10350 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10351 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10352 old->release_fb = fb;
10354 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10356 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10360 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10364 drm_mode_copy(&crtc_state->base.mode, mode);
10366 if (drm_atomic_commit(state)) {
10367 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10368 if (old->release_fb)
10369 old->release_fb->funcs->destroy(old->release_fb);
10372 crtc->primary->crtc = crtc;
10374 /* let the connector get through one full cycle before testing */
10375 intel_wait_for_vblank(dev, intel_crtc->pipe);
10379 drm_atomic_state_free(state);
10382 if (ret == -EDEADLK) {
10383 drm_modeset_backoff(ctx);
10390 void intel_release_load_detect_pipe(struct drm_connector *connector,
10391 struct intel_load_detect_pipe *old,
10392 struct drm_modeset_acquire_ctx *ctx)
10394 struct drm_device *dev = connector->dev;
10395 struct intel_encoder *intel_encoder =
10396 intel_attached_encoder(connector);
10397 struct drm_encoder *encoder = &intel_encoder->base;
10398 struct drm_crtc *crtc = encoder->crtc;
10399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10400 struct drm_atomic_state *state;
10401 struct drm_connector_state *connector_state;
10402 struct intel_crtc_state *crtc_state;
10405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10406 connector->base.id, connector->name,
10407 encoder->base.id, encoder->name);
10409 if (old->load_detect_temp) {
10410 state = drm_atomic_state_alloc(dev);
10414 state->acquire_ctx = ctx;
10416 connector_state = drm_atomic_get_connector_state(state, connector);
10417 if (IS_ERR(connector_state))
10420 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10421 if (IS_ERR(crtc_state))
10424 connector_state->best_encoder = NULL;
10425 connector_state->crtc = NULL;
10427 crtc_state->base.enable = crtc_state->base.active = false;
10429 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10434 ret = drm_atomic_commit(state);
10438 if (old->release_fb) {
10439 drm_framebuffer_unregister_private(old->release_fb);
10440 drm_framebuffer_unreference(old->release_fb);
10446 /* Switch crtc and encoder back off if necessary */
10447 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10448 connector->funcs->dpms(connector, old->dpms_mode);
10452 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10453 drm_atomic_state_free(state);
10456 static int i9xx_pll_refclk(struct drm_device *dev,
10457 const struct intel_crtc_state *pipe_config)
10459 struct drm_i915_private *dev_priv = dev->dev_private;
10460 u32 dpll = pipe_config->dpll_hw_state.dpll;
10462 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10463 return dev_priv->vbt.lvds_ssc_freq;
10464 else if (HAS_PCH_SPLIT(dev))
10466 else if (!IS_GEN2(dev))
10472 /* Returns the clock of the currently programmed mode of the given pipe. */
10473 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10474 struct intel_crtc_state *pipe_config)
10476 struct drm_device *dev = crtc->base.dev;
10477 struct drm_i915_private *dev_priv = dev->dev_private;
10478 int pipe = pipe_config->cpu_transcoder;
10479 u32 dpll = pipe_config->dpll_hw_state.dpll;
10481 intel_clock_t clock;
10483 int refclk = i9xx_pll_refclk(dev, pipe_config);
10485 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10486 fp = pipe_config->dpll_hw_state.fp0;
10488 fp = pipe_config->dpll_hw_state.fp1;
10490 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10491 if (IS_PINEVIEW(dev)) {
10492 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10493 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10495 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10496 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10499 if (!IS_GEN2(dev)) {
10500 if (IS_PINEVIEW(dev))
10501 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10502 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10504 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10505 DPLL_FPA01_P1_POST_DIV_SHIFT);
10507 switch (dpll & DPLL_MODE_MASK) {
10508 case DPLLB_MODE_DAC_SERIAL:
10509 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10512 case DPLLB_MODE_LVDS:
10513 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10517 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10518 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10522 if (IS_PINEVIEW(dev))
10523 port_clock = pnv_calc_dpll_params(refclk, &clock);
10525 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10527 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10528 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10531 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10532 DPLL_FPA01_P1_POST_DIV_SHIFT);
10534 if (lvds & LVDS_CLKB_POWER_UP)
10539 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10542 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10543 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10545 if (dpll & PLL_P2_DIVIDE_BY_4)
10551 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10555 * This value includes pixel_multiplier. We will use
10556 * port_clock to compute adjusted_mode.crtc_clock in the
10557 * encoder's get_config() function.
10559 pipe_config->port_clock = port_clock;
10562 int intel_dotclock_calculate(int link_freq,
10563 const struct intel_link_m_n *m_n)
10566 * The calculation for the data clock is:
10567 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10568 * But we want to avoid losing precison if possible, so:
10569 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10571 * and the link clock is simpler:
10572 * link_clock = (m * link_clock) / n
10578 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10581 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10582 struct intel_crtc_state *pipe_config)
10584 struct drm_device *dev = crtc->base.dev;
10586 /* read out port_clock from the DPLL */
10587 i9xx_crtc_clock_get(crtc, pipe_config);
10590 * This value does not include pixel_multiplier.
10591 * We will check that port_clock and adjusted_mode.crtc_clock
10592 * agree once we know their relationship in the encoder's
10593 * get_config() function.
10595 pipe_config->base.adjusted_mode.crtc_clock =
10596 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10597 &pipe_config->fdi_m_n);
10600 /** Returns the currently programmed mode of the given pipe. */
10601 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10602 struct drm_crtc *crtc)
10604 struct drm_i915_private *dev_priv = dev->dev_private;
10605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10606 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10607 struct drm_display_mode *mode;
10608 struct intel_crtc_state pipe_config;
10609 int htot = I915_READ(HTOTAL(cpu_transcoder));
10610 int hsync = I915_READ(HSYNC(cpu_transcoder));
10611 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10612 int vsync = I915_READ(VSYNC(cpu_transcoder));
10613 enum pipe pipe = intel_crtc->pipe;
10615 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10620 * Construct a pipe_config sufficient for getting the clock info
10621 * back out of crtc_clock_get.
10623 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10624 * to use a real value here instead.
10626 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10627 pipe_config.pixel_multiplier = 1;
10628 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10629 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10630 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10631 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10633 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10634 mode->hdisplay = (htot & 0xffff) + 1;
10635 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10636 mode->hsync_start = (hsync & 0xffff) + 1;
10637 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10638 mode->vdisplay = (vtot & 0xffff) + 1;
10639 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10640 mode->vsync_start = (vsync & 0xffff) + 1;
10641 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10643 drm_mode_set_name(mode);
10648 void intel_mark_busy(struct drm_device *dev)
10650 struct drm_i915_private *dev_priv = dev->dev_private;
10652 if (dev_priv->mm.busy)
10655 intel_runtime_pm_get(dev_priv);
10656 i915_update_gfx_val(dev_priv);
10657 if (INTEL_INFO(dev)->gen >= 6)
10658 gen6_rps_busy(dev_priv);
10659 dev_priv->mm.busy = true;
10662 void intel_mark_idle(struct drm_device *dev)
10664 struct drm_i915_private *dev_priv = dev->dev_private;
10666 if (!dev_priv->mm.busy)
10669 dev_priv->mm.busy = false;
10671 if (INTEL_INFO(dev)->gen >= 6)
10672 gen6_rps_idle(dev->dev_private);
10674 intel_runtime_pm_put(dev_priv);
10677 static void intel_crtc_destroy(struct drm_crtc *crtc)
10679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10680 struct drm_device *dev = crtc->dev;
10681 struct intel_unpin_work *work;
10683 spin_lock_irq(&dev->event_lock);
10684 work = intel_crtc->unpin_work;
10685 intel_crtc->unpin_work = NULL;
10686 spin_unlock_irq(&dev->event_lock);
10689 cancel_work_sync(&work->work);
10693 drm_crtc_cleanup(crtc);
10698 static void intel_unpin_work_fn(struct work_struct *__work)
10700 struct intel_unpin_work *work =
10701 container_of(__work, struct intel_unpin_work, work);
10702 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10703 struct drm_device *dev = crtc->base.dev;
10704 struct drm_plane *primary = crtc->base.primary;
10706 mutex_lock(&dev->struct_mutex);
10707 intel_unpin_fb_obj(work->old_fb, primary->state);
10708 drm_gem_object_unreference(&work->pending_flip_obj->base);
10710 if (work->flip_queued_req)
10711 i915_gem_request_assign(&work->flip_queued_req, NULL);
10712 mutex_unlock(&dev->struct_mutex);
10714 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10715 drm_framebuffer_unreference(work->old_fb);
10717 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10718 atomic_dec(&crtc->unpin_work_count);
10723 static void do_intel_finish_page_flip(struct drm_device *dev,
10724 struct drm_crtc *crtc)
10726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10727 struct intel_unpin_work *work;
10728 unsigned long flags;
10730 /* Ignore early vblank irqs */
10731 if (intel_crtc == NULL)
10735 * This is called both by irq handlers and the reset code (to complete
10736 * lost pageflips) so needs the full irqsave spinlocks.
10738 spin_lock_irqsave(&dev->event_lock, flags);
10739 work = intel_crtc->unpin_work;
10741 /* Ensure we don't miss a work->pending update ... */
10744 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10745 spin_unlock_irqrestore(&dev->event_lock, flags);
10749 page_flip_completed(intel_crtc);
10751 spin_unlock_irqrestore(&dev->event_lock, flags);
10754 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10759 do_intel_finish_page_flip(dev, crtc);
10762 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10764 struct drm_i915_private *dev_priv = dev->dev_private;
10765 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10767 do_intel_finish_page_flip(dev, crtc);
10770 /* Is 'a' after or equal to 'b'? */
10771 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10773 return !((a - b) & 0x80000000);
10776 static bool page_flip_finished(struct intel_crtc *crtc)
10778 struct drm_device *dev = crtc->base.dev;
10779 struct drm_i915_private *dev_priv = dev->dev_private;
10781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10782 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10786 * The relevant registers doen't exist on pre-ctg.
10787 * As the flip done interrupt doesn't trigger for mmio
10788 * flips on gmch platforms, a flip count check isn't
10789 * really needed there. But since ctg has the registers,
10790 * include it in the check anyway.
10792 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10796 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10797 * used the same base address. In that case the mmio flip might
10798 * have completed, but the CS hasn't even executed the flip yet.
10800 * A flip count check isn't enough as the CS might have updated
10801 * the base address just after start of vblank, but before we
10802 * managed to process the interrupt. This means we'd complete the
10803 * CS flip too soon.
10805 * Combining both checks should get us a good enough result. It may
10806 * still happen that the CS flip has been executed, but has not
10807 * yet actually completed. But in case the base address is the same
10808 * anyway, we don't really care.
10810 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10811 crtc->unpin_work->gtt_offset &&
10812 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10813 crtc->unpin_work->flip_count);
10816 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10818 struct drm_i915_private *dev_priv = dev->dev_private;
10819 struct intel_crtc *intel_crtc =
10820 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10821 unsigned long flags;
10825 * This is called both by irq handlers and the reset code (to complete
10826 * lost pageflips) so needs the full irqsave spinlocks.
10828 * NB: An MMIO update of the plane base pointer will also
10829 * generate a page-flip completion irq, i.e. every modeset
10830 * is also accompanied by a spurious intel_prepare_page_flip().
10832 spin_lock_irqsave(&dev->event_lock, flags);
10833 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10834 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10835 spin_unlock_irqrestore(&dev->event_lock, flags);
10838 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10840 /* Ensure that the work item is consistent when activating it ... */
10842 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10843 /* and that it is marked active as soon as the irq could fire. */
10847 static int intel_gen2_queue_flip(struct drm_device *dev,
10848 struct drm_crtc *crtc,
10849 struct drm_framebuffer *fb,
10850 struct drm_i915_gem_object *obj,
10851 struct drm_i915_gem_request *req,
10854 struct intel_engine_cs *ring = req->ring;
10855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10859 ret = intel_ring_begin(req, 6);
10863 /* Can't queue multiple flips, so wait for the previous
10864 * one to finish before executing the next.
10866 if (intel_crtc->plane)
10867 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10869 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10870 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10871 intel_ring_emit(ring, MI_NOOP);
10872 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10873 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10874 intel_ring_emit(ring, fb->pitches[0]);
10875 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10876 intel_ring_emit(ring, 0); /* aux display base address, unused */
10878 intel_mark_page_flip_active(intel_crtc);
10882 static int intel_gen3_queue_flip(struct drm_device *dev,
10883 struct drm_crtc *crtc,
10884 struct drm_framebuffer *fb,
10885 struct drm_i915_gem_object *obj,
10886 struct drm_i915_gem_request *req,
10889 struct intel_engine_cs *ring = req->ring;
10890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10894 ret = intel_ring_begin(req, 6);
10898 if (intel_crtc->plane)
10899 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10901 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10902 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10903 intel_ring_emit(ring, MI_NOOP);
10904 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10905 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10906 intel_ring_emit(ring, fb->pitches[0]);
10907 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10908 intel_ring_emit(ring, MI_NOOP);
10910 intel_mark_page_flip_active(intel_crtc);
10914 static int intel_gen4_queue_flip(struct drm_device *dev,
10915 struct drm_crtc *crtc,
10916 struct drm_framebuffer *fb,
10917 struct drm_i915_gem_object *obj,
10918 struct drm_i915_gem_request *req,
10921 struct intel_engine_cs *ring = req->ring;
10922 struct drm_i915_private *dev_priv = dev->dev_private;
10923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10924 uint32_t pf, pipesrc;
10927 ret = intel_ring_begin(req, 4);
10931 /* i965+ uses the linear or tiled offsets from the
10932 * Display Registers (which do not change across a page-flip)
10933 * so we need only reprogram the base address.
10935 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10936 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10937 intel_ring_emit(ring, fb->pitches[0]);
10938 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10941 /* XXX Enabling the panel-fitter across page-flip is so far
10942 * untested on non-native modes, so ignore it for now.
10943 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10946 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10947 intel_ring_emit(ring, pf | pipesrc);
10949 intel_mark_page_flip_active(intel_crtc);
10953 static int intel_gen6_queue_flip(struct drm_device *dev,
10954 struct drm_crtc *crtc,
10955 struct drm_framebuffer *fb,
10956 struct drm_i915_gem_object *obj,
10957 struct drm_i915_gem_request *req,
10960 struct intel_engine_cs *ring = req->ring;
10961 struct drm_i915_private *dev_priv = dev->dev_private;
10962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10963 uint32_t pf, pipesrc;
10966 ret = intel_ring_begin(req, 4);
10970 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10971 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10972 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10973 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10975 /* Contrary to the suggestions in the documentation,
10976 * "Enable Panel Fitter" does not seem to be required when page
10977 * flipping with a non-native mode, and worse causes a normal
10979 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10982 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10983 intel_ring_emit(ring, pf | pipesrc);
10985 intel_mark_page_flip_active(intel_crtc);
10989 static int intel_gen7_queue_flip(struct drm_device *dev,
10990 struct drm_crtc *crtc,
10991 struct drm_framebuffer *fb,
10992 struct drm_i915_gem_object *obj,
10993 struct drm_i915_gem_request *req,
10996 struct intel_engine_cs *ring = req->ring;
10997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10998 uint32_t plane_bit = 0;
11001 switch (intel_crtc->plane) {
11003 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11006 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11009 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11012 WARN_ONCE(1, "unknown plane in flip command\n");
11017 if (ring->id == RCS) {
11020 * On Gen 8, SRM is now taking an extra dword to accommodate
11021 * 48bits addresses, and we need a NOOP for the batch size to
11029 * BSpec MI_DISPLAY_FLIP for IVB:
11030 * "The full packet must be contained within the same cache line."
11032 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11033 * cacheline, if we ever start emitting more commands before
11034 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11035 * then do the cacheline alignment, and finally emit the
11038 ret = intel_ring_cacheline_align(req);
11042 ret = intel_ring_begin(req, len);
11046 /* Unmask the flip-done completion message. Note that the bspec says that
11047 * we should do this for both the BCS and RCS, and that we must not unmask
11048 * more than one flip event at any time (or ensure that one flip message
11049 * can be sent by waiting for flip-done prior to queueing new flips).
11050 * Experimentation says that BCS works despite DERRMR masking all
11051 * flip-done completion events and that unmasking all planes at once
11052 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11053 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11055 if (ring->id == RCS) {
11056 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11057 intel_ring_emit(ring, DERRMR);
11058 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11059 DERRMR_PIPEB_PRI_FLIP_DONE |
11060 DERRMR_PIPEC_PRI_FLIP_DONE));
11062 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11063 MI_SRM_LRM_GLOBAL_GTT);
11065 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11066 MI_SRM_LRM_GLOBAL_GTT);
11067 intel_ring_emit(ring, DERRMR);
11068 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11069 if (IS_GEN8(dev)) {
11070 intel_ring_emit(ring, 0);
11071 intel_ring_emit(ring, MI_NOOP);
11075 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11076 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11077 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11078 intel_ring_emit(ring, (MI_NOOP));
11080 intel_mark_page_flip_active(intel_crtc);
11084 static bool use_mmio_flip(struct intel_engine_cs *ring,
11085 struct drm_i915_gem_object *obj)
11088 * This is not being used for older platforms, because
11089 * non-availability of flip done interrupt forces us to use
11090 * CS flips. Older platforms derive flip done using some clever
11091 * tricks involving the flip_pending status bits and vblank irqs.
11092 * So using MMIO flips there would disrupt this mechanism.
11098 if (INTEL_INFO(ring->dev)->gen < 5)
11101 if (i915.use_mmio_flip < 0)
11103 else if (i915.use_mmio_flip > 0)
11105 else if (i915.enable_execlists)
11108 return ring != i915_gem_request_get_ring(obj->last_write_req);
11111 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11113 struct drm_device *dev = intel_crtc->base.dev;
11114 struct drm_i915_private *dev_priv = dev->dev_private;
11115 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11116 const enum pipe pipe = intel_crtc->pipe;
11119 ctl = I915_READ(PLANE_CTL(pipe, 0));
11120 ctl &= ~PLANE_CTL_TILED_MASK;
11121 switch (fb->modifier[0]) {
11122 case DRM_FORMAT_MOD_NONE:
11124 case I915_FORMAT_MOD_X_TILED:
11125 ctl |= PLANE_CTL_TILED_X;
11127 case I915_FORMAT_MOD_Y_TILED:
11128 ctl |= PLANE_CTL_TILED_Y;
11130 case I915_FORMAT_MOD_Yf_TILED:
11131 ctl |= PLANE_CTL_TILED_YF;
11134 MISSING_CASE(fb->modifier[0]);
11138 * The stride is either expressed as a multiple of 64 bytes chunks for
11139 * linear buffers or in number of tiles for tiled buffers.
11141 stride = fb->pitches[0] /
11142 intel_fb_stride_alignment(dev, fb->modifier[0],
11146 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11147 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11149 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11150 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11152 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11153 POSTING_READ(PLANE_SURF(pipe, 0));
11156 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11158 struct drm_device *dev = intel_crtc->base.dev;
11159 struct drm_i915_private *dev_priv = dev->dev_private;
11160 struct intel_framebuffer *intel_fb =
11161 to_intel_framebuffer(intel_crtc->base.primary->fb);
11162 struct drm_i915_gem_object *obj = intel_fb->obj;
11166 reg = DSPCNTR(intel_crtc->plane);
11167 dspcntr = I915_READ(reg);
11169 if (obj->tiling_mode != I915_TILING_NONE)
11170 dspcntr |= DISPPLANE_TILED;
11172 dspcntr &= ~DISPPLANE_TILED;
11174 I915_WRITE(reg, dspcntr);
11176 I915_WRITE(DSPSURF(intel_crtc->plane),
11177 intel_crtc->unpin_work->gtt_offset);
11178 POSTING_READ(DSPSURF(intel_crtc->plane));
11183 * XXX: This is the temporary way to update the plane registers until we get
11184 * around to using the usual plane update functions for MMIO flips
11186 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11188 struct drm_device *dev = intel_crtc->base.dev;
11190 intel_mark_page_flip_active(intel_crtc);
11192 intel_pipe_update_start(intel_crtc);
11194 if (INTEL_INFO(dev)->gen >= 9)
11195 skl_do_mmio_flip(intel_crtc);
11197 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11198 ilk_do_mmio_flip(intel_crtc);
11200 intel_pipe_update_end(intel_crtc);
11203 static void intel_mmio_flip_work_func(struct work_struct *work)
11205 struct intel_mmio_flip *mmio_flip =
11206 container_of(work, struct intel_mmio_flip, work);
11208 if (mmio_flip->req)
11209 WARN_ON(__i915_wait_request(mmio_flip->req,
11210 mmio_flip->crtc->reset_counter,
11212 &mmio_flip->i915->rps.mmioflips));
11214 intel_do_mmio_flip(mmio_flip->crtc);
11216 i915_gem_request_unreference__unlocked(mmio_flip->req);
11220 static int intel_queue_mmio_flip(struct drm_device *dev,
11221 struct drm_crtc *crtc,
11222 struct drm_framebuffer *fb,
11223 struct drm_i915_gem_object *obj,
11224 struct intel_engine_cs *ring,
11227 struct intel_mmio_flip *mmio_flip;
11229 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11230 if (mmio_flip == NULL)
11233 mmio_flip->i915 = to_i915(dev);
11234 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11235 mmio_flip->crtc = to_intel_crtc(crtc);
11237 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11238 schedule_work(&mmio_flip->work);
11243 static int intel_default_queue_flip(struct drm_device *dev,
11244 struct drm_crtc *crtc,
11245 struct drm_framebuffer *fb,
11246 struct drm_i915_gem_object *obj,
11247 struct drm_i915_gem_request *req,
11253 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11254 struct drm_crtc *crtc)
11256 struct drm_i915_private *dev_priv = dev->dev_private;
11257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11258 struct intel_unpin_work *work = intel_crtc->unpin_work;
11261 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11264 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11267 if (!work->enable_stall_check)
11270 if (work->flip_ready_vblank == 0) {
11271 if (work->flip_queued_req &&
11272 !i915_gem_request_completed(work->flip_queued_req, true))
11275 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11278 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11281 /* Potential stall - if we see that the flip has happened,
11282 * assume a missed interrupt. */
11283 if (INTEL_INFO(dev)->gen >= 4)
11284 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11286 addr = I915_READ(DSPADDR(intel_crtc->plane));
11288 /* There is a potential issue here with a false positive after a flip
11289 * to the same address. We could address this by checking for a
11290 * non-incrementing frame counter.
11292 return addr == work->gtt_offset;
11295 void intel_check_page_flip(struct drm_device *dev, int pipe)
11297 struct drm_i915_private *dev_priv = dev->dev_private;
11298 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11300 struct intel_unpin_work *work;
11302 WARN_ON(!in_interrupt());
11307 spin_lock(&dev->event_lock);
11308 work = intel_crtc->unpin_work;
11309 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11310 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11311 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11312 page_flip_completed(intel_crtc);
11315 if (work != NULL &&
11316 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11317 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11318 spin_unlock(&dev->event_lock);
11321 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11322 struct drm_framebuffer *fb,
11323 struct drm_pending_vblank_event *event,
11324 uint32_t page_flip_flags)
11326 struct drm_device *dev = crtc->dev;
11327 struct drm_i915_private *dev_priv = dev->dev_private;
11328 struct drm_framebuffer *old_fb = crtc->primary->fb;
11329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11331 struct drm_plane *primary = crtc->primary;
11332 enum pipe pipe = intel_crtc->pipe;
11333 struct intel_unpin_work *work;
11334 struct intel_engine_cs *ring;
11336 struct drm_i915_gem_request *request = NULL;
11340 * drm_mode_page_flip_ioctl() should already catch this, but double
11341 * check to be safe. In the future we may enable pageflipping from
11342 * a disabled primary plane.
11344 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11347 /* Can't change pixel format via MI display flips. */
11348 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11352 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11353 * Note that pitch changes could also affect these register.
11355 if (INTEL_INFO(dev)->gen > 3 &&
11356 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11357 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11360 if (i915_terminally_wedged(&dev_priv->gpu_error))
11363 work = kzalloc(sizeof(*work), GFP_KERNEL);
11367 work->event = event;
11369 work->old_fb = old_fb;
11370 INIT_WORK(&work->work, intel_unpin_work_fn);
11372 ret = drm_crtc_vblank_get(crtc);
11376 /* We borrow the event spin lock for protecting unpin_work */
11377 spin_lock_irq(&dev->event_lock);
11378 if (intel_crtc->unpin_work) {
11379 /* Before declaring the flip queue wedged, check if
11380 * the hardware completed the operation behind our backs.
11382 if (__intel_pageflip_stall_check(dev, crtc)) {
11383 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11384 page_flip_completed(intel_crtc);
11386 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11387 spin_unlock_irq(&dev->event_lock);
11389 drm_crtc_vblank_put(crtc);
11394 intel_crtc->unpin_work = work;
11395 spin_unlock_irq(&dev->event_lock);
11397 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11398 flush_workqueue(dev_priv->wq);
11400 /* Reference the objects for the scheduled work. */
11401 drm_framebuffer_reference(work->old_fb);
11402 drm_gem_object_reference(&obj->base);
11404 crtc->primary->fb = fb;
11405 update_state_fb(crtc->primary);
11407 work->pending_flip_obj = obj;
11409 ret = i915_mutex_lock_interruptible(dev);
11413 atomic_inc(&intel_crtc->unpin_work_count);
11414 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11416 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11417 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11419 if (IS_VALLEYVIEW(dev)) {
11420 ring = &dev_priv->ring[BCS];
11421 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11422 /* vlv: DISPLAY_FLIP fails to change tiling */
11424 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11425 ring = &dev_priv->ring[BCS];
11426 } else if (INTEL_INFO(dev)->gen >= 7) {
11427 ring = i915_gem_request_get_ring(obj->last_write_req);
11428 if (ring == NULL || ring->id != RCS)
11429 ring = &dev_priv->ring[BCS];
11431 ring = &dev_priv->ring[RCS];
11434 mmio_flip = use_mmio_flip(ring, obj);
11436 /* When using CS flips, we want to emit semaphores between rings.
11437 * However, when using mmio flips we will create a task to do the
11438 * synchronisation, so all we want here is to pin the framebuffer
11439 * into the display plane and skip any waits.
11441 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11442 crtc->primary->state,
11443 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11445 goto cleanup_pending;
11447 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11449 work->gtt_offset += intel_crtc->dspaddr_offset;
11452 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11455 goto cleanup_unpin;
11457 i915_gem_request_assign(&work->flip_queued_req,
11458 obj->last_write_req);
11461 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11463 goto cleanup_unpin;
11466 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11469 goto cleanup_unpin;
11471 i915_gem_request_assign(&work->flip_queued_req, request);
11475 i915_add_request_no_flush(request);
11477 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11478 work->enable_stall_check = true;
11480 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11481 to_intel_plane(primary)->frontbuffer_bit);
11482 mutex_unlock(&dev->struct_mutex);
11484 intel_fbc_disable_crtc(intel_crtc);
11485 intel_frontbuffer_flip_prepare(dev,
11486 to_intel_plane(primary)->frontbuffer_bit);
11488 trace_i915_flip_request(intel_crtc->plane, obj);
11493 intel_unpin_fb_obj(fb, crtc->primary->state);
11496 i915_gem_request_cancel(request);
11497 atomic_dec(&intel_crtc->unpin_work_count);
11498 mutex_unlock(&dev->struct_mutex);
11500 crtc->primary->fb = old_fb;
11501 update_state_fb(crtc->primary);
11503 drm_gem_object_unreference_unlocked(&obj->base);
11504 drm_framebuffer_unreference(work->old_fb);
11506 spin_lock_irq(&dev->event_lock);
11507 intel_crtc->unpin_work = NULL;
11508 spin_unlock_irq(&dev->event_lock);
11510 drm_crtc_vblank_put(crtc);
11515 struct drm_atomic_state *state;
11516 struct drm_plane_state *plane_state;
11519 state = drm_atomic_state_alloc(dev);
11522 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11525 plane_state = drm_atomic_get_plane_state(state, primary);
11526 ret = PTR_ERR_OR_ZERO(plane_state);
11528 drm_atomic_set_fb_for_plane(plane_state, fb);
11530 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11532 ret = drm_atomic_commit(state);
11535 if (ret == -EDEADLK) {
11536 drm_modeset_backoff(state->acquire_ctx);
11537 drm_atomic_state_clear(state);
11542 drm_atomic_state_free(state);
11544 if (ret == 0 && event) {
11545 spin_lock_irq(&dev->event_lock);
11546 drm_send_vblank_event(dev, pipe, event);
11547 spin_unlock_irq(&dev->event_lock);
11555 * intel_wm_need_update - Check whether watermarks need updating
11556 * @plane: drm plane
11557 * @state: new plane state
11559 * Check current plane state versus the new one to determine whether
11560 * watermarks need to be recalculated.
11562 * Returns true or false.
11564 static bool intel_wm_need_update(struct drm_plane *plane,
11565 struct drm_plane_state *state)
11567 /* Update watermarks on tiling changes. */
11568 if (!plane->state->fb || !state->fb ||
11569 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11570 plane->state->rotation != state->rotation)
11573 if (plane->state->crtc_w != state->crtc_w)
11579 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11580 struct drm_plane_state *plane_state)
11582 struct drm_crtc *crtc = crtc_state->crtc;
11583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11584 struct drm_plane *plane = plane_state->plane;
11585 struct drm_device *dev = crtc->dev;
11586 struct drm_i915_private *dev_priv = dev->dev_private;
11587 struct intel_plane_state *old_plane_state =
11588 to_intel_plane_state(plane->state);
11589 int idx = intel_crtc->base.base.id, ret;
11590 int i = drm_plane_index(plane);
11591 bool mode_changed = needs_modeset(crtc_state);
11592 bool was_crtc_enabled = crtc->state->active;
11593 bool is_crtc_enabled = crtc_state->active;
11595 bool turn_off, turn_on, visible, was_visible;
11596 struct drm_framebuffer *fb = plane_state->fb;
11598 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11599 plane->type != DRM_PLANE_TYPE_CURSOR) {
11600 ret = skl_update_scaler_plane(
11601 to_intel_crtc_state(crtc_state),
11602 to_intel_plane_state(plane_state));
11608 * Disabling a plane is always okay; we just need to update
11609 * fb tracking in a special way since cleanup_fb() won't
11610 * get called by the plane helpers.
11612 if (old_plane_state->base.fb && !fb)
11613 intel_crtc->atomic.disabled_planes |= 1 << i;
11615 was_visible = old_plane_state->visible;
11616 visible = to_intel_plane_state(plane_state)->visible;
11618 if (!was_crtc_enabled && WARN_ON(was_visible))
11619 was_visible = false;
11621 if (!is_crtc_enabled && WARN_ON(visible))
11624 if (!was_visible && !visible)
11627 turn_off = was_visible && (!visible || mode_changed);
11628 turn_on = visible && (!was_visible || mode_changed);
11630 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11631 plane->base.id, fb ? fb->base.id : -1);
11633 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11634 plane->base.id, was_visible, visible,
11635 turn_off, turn_on, mode_changed);
11638 intel_crtc->atomic.update_wm_pre = true;
11639 /* must disable cxsr around plane enable/disable */
11640 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11641 intel_crtc->atomic.disable_cxsr = true;
11642 /* to potentially re-enable cxsr */
11643 intel_crtc->atomic.wait_vblank = true;
11644 intel_crtc->atomic.update_wm_post = true;
11646 } else if (turn_off) {
11647 intel_crtc->atomic.update_wm_post = true;
11648 /* must disable cxsr around plane enable/disable */
11649 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11650 if (is_crtc_enabled)
11651 intel_crtc->atomic.wait_vblank = true;
11652 intel_crtc->atomic.disable_cxsr = true;
11654 } else if (intel_wm_need_update(plane, plane_state)) {
11655 intel_crtc->atomic.update_wm_pre = true;
11658 if (visible || was_visible)
11659 intel_crtc->atomic.fb_bits |=
11660 to_intel_plane(plane)->frontbuffer_bit;
11662 switch (plane->type) {
11663 case DRM_PLANE_TYPE_PRIMARY:
11664 intel_crtc->atomic.wait_for_flips = true;
11665 intel_crtc->atomic.pre_disable_primary = turn_off;
11666 intel_crtc->atomic.post_enable_primary = turn_on;
11670 * FIXME: Actually if we will still have any other
11671 * plane enabled on the pipe we could let IPS enabled
11672 * still, but for now lets consider that when we make
11673 * primary invisible by setting DSPCNTR to 0 on
11674 * update_primary_plane function IPS needs to be
11677 intel_crtc->atomic.disable_ips = true;
11679 intel_crtc->atomic.disable_fbc = true;
11683 * FBC does not work on some platforms for rotated
11684 * planes, so disable it when rotation is not 0 and
11685 * update it when rotation is set back to 0.
11687 * FIXME: This is redundant with the fbc update done in
11688 * the primary plane enable function except that that
11689 * one is done too late. We eventually need to unify
11694 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11695 dev_priv->fbc.crtc == intel_crtc &&
11696 plane_state->rotation != BIT(DRM_ROTATE_0))
11697 intel_crtc->atomic.disable_fbc = true;
11700 * BDW signals flip done immediately if the plane
11701 * is disabled, even if the plane enable is already
11702 * armed to occur at the next vblank :(
11704 if (turn_on && IS_BROADWELL(dev))
11705 intel_crtc->atomic.wait_vblank = true;
11707 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11709 case DRM_PLANE_TYPE_CURSOR:
11711 case DRM_PLANE_TYPE_OVERLAY:
11712 if (turn_off && !mode_changed) {
11713 intel_crtc->atomic.wait_vblank = true;
11714 intel_crtc->atomic.update_sprite_watermarks |=
11721 static bool encoders_cloneable(const struct intel_encoder *a,
11722 const struct intel_encoder *b)
11724 /* masks could be asymmetric, so check both ways */
11725 return a == b || (a->cloneable & (1 << b->type) &&
11726 b->cloneable & (1 << a->type));
11729 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11730 struct intel_crtc *crtc,
11731 struct intel_encoder *encoder)
11733 struct intel_encoder *source_encoder;
11734 struct drm_connector *connector;
11735 struct drm_connector_state *connector_state;
11738 for_each_connector_in_state(state, connector, connector_state, i) {
11739 if (connector_state->crtc != &crtc->base)
11743 to_intel_encoder(connector_state->best_encoder);
11744 if (!encoders_cloneable(encoder, source_encoder))
11751 static bool check_encoder_cloning(struct drm_atomic_state *state,
11752 struct intel_crtc *crtc)
11754 struct intel_encoder *encoder;
11755 struct drm_connector *connector;
11756 struct drm_connector_state *connector_state;
11759 for_each_connector_in_state(state, connector, connector_state, i) {
11760 if (connector_state->crtc != &crtc->base)
11763 encoder = to_intel_encoder(connector_state->best_encoder);
11764 if (!check_single_encoder_cloning(state, crtc, encoder))
11771 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11772 struct drm_crtc_state *crtc_state)
11774 struct drm_device *dev = crtc->dev;
11775 struct drm_i915_private *dev_priv = dev->dev_private;
11776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11777 struct intel_crtc_state *pipe_config =
11778 to_intel_crtc_state(crtc_state);
11779 struct drm_atomic_state *state = crtc_state->state;
11781 bool mode_changed = needs_modeset(crtc_state);
11783 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11784 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11788 if (mode_changed && !crtc_state->active)
11789 intel_crtc->atomic.update_wm_post = true;
11791 if (mode_changed && crtc_state->enable &&
11792 dev_priv->display.crtc_compute_clock &&
11793 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11794 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11801 if (INTEL_INFO(dev)->gen >= 9) {
11803 ret = skl_update_scaler_crtc(pipe_config);
11806 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11813 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11814 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11815 .load_lut = intel_crtc_load_lut,
11816 .atomic_begin = intel_begin_crtc_commit,
11817 .atomic_flush = intel_finish_crtc_commit,
11818 .atomic_check = intel_crtc_atomic_check,
11821 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11823 struct intel_connector *connector;
11825 for_each_intel_connector(dev, connector) {
11826 if (connector->base.encoder) {
11827 connector->base.state->best_encoder =
11828 connector->base.encoder;
11829 connector->base.state->crtc =
11830 connector->base.encoder->crtc;
11832 connector->base.state->best_encoder = NULL;
11833 connector->base.state->crtc = NULL;
11839 connected_sink_compute_bpp(struct intel_connector *connector,
11840 struct intel_crtc_state *pipe_config)
11842 int bpp = pipe_config->pipe_bpp;
11844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11845 connector->base.base.id,
11846 connector->base.name);
11848 /* Don't use an invalid EDID bpc value */
11849 if (connector->base.display_info.bpc &&
11850 connector->base.display_info.bpc * 3 < bpp) {
11851 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11852 bpp, connector->base.display_info.bpc*3);
11853 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11856 /* Clamp bpp to 8 on screens without EDID 1.4 */
11857 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11858 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11860 pipe_config->pipe_bpp = 24;
11865 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11866 struct intel_crtc_state *pipe_config)
11868 struct drm_device *dev = crtc->base.dev;
11869 struct drm_atomic_state *state;
11870 struct drm_connector *connector;
11871 struct drm_connector_state *connector_state;
11874 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11876 else if (INTEL_INFO(dev)->gen >= 5)
11882 pipe_config->pipe_bpp = bpp;
11884 state = pipe_config->base.state;
11886 /* Clamp display bpp to EDID value */
11887 for_each_connector_in_state(state, connector, connector_state, i) {
11888 if (connector_state->crtc != &crtc->base)
11891 connected_sink_compute_bpp(to_intel_connector(connector),
11898 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11900 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11901 "type: 0x%x flags: 0x%x\n",
11903 mode->crtc_hdisplay, mode->crtc_hsync_start,
11904 mode->crtc_hsync_end, mode->crtc_htotal,
11905 mode->crtc_vdisplay, mode->crtc_vsync_start,
11906 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11909 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11910 struct intel_crtc_state *pipe_config,
11911 const char *context)
11913 struct drm_device *dev = crtc->base.dev;
11914 struct drm_plane *plane;
11915 struct intel_plane *intel_plane;
11916 struct intel_plane_state *state;
11917 struct drm_framebuffer *fb;
11919 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11920 context, pipe_config, pipe_name(crtc->pipe));
11922 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11923 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11924 pipe_config->pipe_bpp, pipe_config->dither);
11925 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11926 pipe_config->has_pch_encoder,
11927 pipe_config->fdi_lanes,
11928 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11929 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11930 pipe_config->fdi_m_n.tu);
11931 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11932 pipe_config->has_dp_encoder,
11933 pipe_config->lane_count,
11934 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11935 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11936 pipe_config->dp_m_n.tu);
11938 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11939 pipe_config->has_dp_encoder,
11940 pipe_config->lane_count,
11941 pipe_config->dp_m2_n2.gmch_m,
11942 pipe_config->dp_m2_n2.gmch_n,
11943 pipe_config->dp_m2_n2.link_m,
11944 pipe_config->dp_m2_n2.link_n,
11945 pipe_config->dp_m2_n2.tu);
11947 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11948 pipe_config->has_audio,
11949 pipe_config->has_infoframe);
11951 DRM_DEBUG_KMS("requested mode:\n");
11952 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11953 DRM_DEBUG_KMS("adjusted mode:\n");
11954 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11955 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11956 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11957 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11958 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11959 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11961 pipe_config->scaler_state.scaler_users,
11962 pipe_config->scaler_state.scaler_id);
11963 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11964 pipe_config->gmch_pfit.control,
11965 pipe_config->gmch_pfit.pgm_ratios,
11966 pipe_config->gmch_pfit.lvds_border_bits);
11967 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11968 pipe_config->pch_pfit.pos,
11969 pipe_config->pch_pfit.size,
11970 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11971 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11972 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11974 if (IS_BROXTON(dev)) {
11975 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11976 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11977 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11978 pipe_config->ddi_pll_sel,
11979 pipe_config->dpll_hw_state.ebb0,
11980 pipe_config->dpll_hw_state.ebb4,
11981 pipe_config->dpll_hw_state.pll0,
11982 pipe_config->dpll_hw_state.pll1,
11983 pipe_config->dpll_hw_state.pll2,
11984 pipe_config->dpll_hw_state.pll3,
11985 pipe_config->dpll_hw_state.pll6,
11986 pipe_config->dpll_hw_state.pll8,
11987 pipe_config->dpll_hw_state.pll9,
11988 pipe_config->dpll_hw_state.pll10,
11989 pipe_config->dpll_hw_state.pcsdw12);
11990 } else if (IS_SKYLAKE(dev)) {
11991 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11992 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11993 pipe_config->ddi_pll_sel,
11994 pipe_config->dpll_hw_state.ctrl1,
11995 pipe_config->dpll_hw_state.cfgcr1,
11996 pipe_config->dpll_hw_state.cfgcr2);
11997 } else if (HAS_DDI(dev)) {
11998 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11999 pipe_config->ddi_pll_sel,
12000 pipe_config->dpll_hw_state.wrpll);
12002 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12003 "fp0: 0x%x, fp1: 0x%x\n",
12004 pipe_config->dpll_hw_state.dpll,
12005 pipe_config->dpll_hw_state.dpll_md,
12006 pipe_config->dpll_hw_state.fp0,
12007 pipe_config->dpll_hw_state.fp1);
12010 DRM_DEBUG_KMS("planes on this crtc\n");
12011 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12012 intel_plane = to_intel_plane(plane);
12013 if (intel_plane->pipe != crtc->pipe)
12016 state = to_intel_plane_state(plane->state);
12017 fb = state->base.fb;
12019 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12020 "disabled, scaler_id = %d\n",
12021 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12022 plane->base.id, intel_plane->pipe,
12023 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12024 drm_plane_index(plane), state->scaler_id);
12028 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12029 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12030 plane->base.id, intel_plane->pipe,
12031 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12032 drm_plane_index(plane));
12033 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12034 fb->base.id, fb->width, fb->height, fb->pixel_format);
12035 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12037 state->src.x1 >> 16, state->src.y1 >> 16,
12038 drm_rect_width(&state->src) >> 16,
12039 drm_rect_height(&state->src) >> 16,
12040 state->dst.x1, state->dst.y1,
12041 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12045 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12047 struct drm_device *dev = state->dev;
12048 struct intel_encoder *encoder;
12049 struct drm_connector *connector;
12050 struct drm_connector_state *connector_state;
12051 unsigned int used_ports = 0;
12055 * Walk the connector list instead of the encoder
12056 * list to detect the problem on ddi platforms
12057 * where there's just one encoder per digital port.
12059 for_each_connector_in_state(state, connector, connector_state, i) {
12060 if (!connector_state->best_encoder)
12063 encoder = to_intel_encoder(connector_state->best_encoder);
12065 WARN_ON(!connector_state->crtc);
12067 switch (encoder->type) {
12068 unsigned int port_mask;
12069 case INTEL_OUTPUT_UNKNOWN:
12070 if (WARN_ON(!HAS_DDI(dev)))
12072 case INTEL_OUTPUT_DISPLAYPORT:
12073 case INTEL_OUTPUT_HDMI:
12074 case INTEL_OUTPUT_EDP:
12075 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12077 /* the same port mustn't appear more than once */
12078 if (used_ports & port_mask)
12081 used_ports |= port_mask;
12091 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12093 struct drm_crtc_state tmp_state;
12094 struct intel_crtc_scaler_state scaler_state;
12095 struct intel_dpll_hw_state dpll_hw_state;
12096 enum intel_dpll_id shared_dpll;
12097 uint32_t ddi_pll_sel;
12100 /* FIXME: before the switch to atomic started, a new pipe_config was
12101 * kzalloc'd. Code that depends on any field being zero should be
12102 * fixed, so that the crtc_state can be safely duplicated. For now,
12103 * only fields that are know to not cause problems are preserved. */
12105 tmp_state = crtc_state->base;
12106 scaler_state = crtc_state->scaler_state;
12107 shared_dpll = crtc_state->shared_dpll;
12108 dpll_hw_state = crtc_state->dpll_hw_state;
12109 ddi_pll_sel = crtc_state->ddi_pll_sel;
12110 force_thru = crtc_state->pch_pfit.force_thru;
12112 memset(crtc_state, 0, sizeof *crtc_state);
12114 crtc_state->base = tmp_state;
12115 crtc_state->scaler_state = scaler_state;
12116 crtc_state->shared_dpll = shared_dpll;
12117 crtc_state->dpll_hw_state = dpll_hw_state;
12118 crtc_state->ddi_pll_sel = ddi_pll_sel;
12119 crtc_state->pch_pfit.force_thru = force_thru;
12123 intel_modeset_pipe_config(struct drm_crtc *crtc,
12124 struct intel_crtc_state *pipe_config)
12126 struct drm_atomic_state *state = pipe_config->base.state;
12127 struct intel_encoder *encoder;
12128 struct drm_connector *connector;
12129 struct drm_connector_state *connector_state;
12130 int base_bpp, ret = -EINVAL;
12134 clear_intel_crtc_state(pipe_config);
12136 pipe_config->cpu_transcoder =
12137 (enum transcoder) to_intel_crtc(crtc)->pipe;
12140 * Sanitize sync polarity flags based on requested ones. If neither
12141 * positive or negative polarity is requested, treat this as meaning
12142 * negative polarity.
12144 if (!(pipe_config->base.adjusted_mode.flags &
12145 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12146 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12148 if (!(pipe_config->base.adjusted_mode.flags &
12149 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12150 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12152 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12158 * Determine the real pipe dimensions. Note that stereo modes can
12159 * increase the actual pipe size due to the frame doubling and
12160 * insertion of additional space for blanks between the frame. This
12161 * is stored in the crtc timings. We use the requested mode to do this
12162 * computation to clearly distinguish it from the adjusted mode, which
12163 * can be changed by the connectors in the below retry loop.
12165 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12166 &pipe_config->pipe_src_w,
12167 &pipe_config->pipe_src_h);
12170 /* Ensure the port clock defaults are reset when retrying. */
12171 pipe_config->port_clock = 0;
12172 pipe_config->pixel_multiplier = 1;
12174 /* Fill in default crtc timings, allow encoders to overwrite them. */
12175 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12176 CRTC_STEREO_DOUBLE);
12178 /* Pass our mode to the connectors and the CRTC to give them a chance to
12179 * adjust it according to limitations or connector properties, and also
12180 * a chance to reject the mode entirely.
12182 for_each_connector_in_state(state, connector, connector_state, i) {
12183 if (connector_state->crtc != crtc)
12186 encoder = to_intel_encoder(connector_state->best_encoder);
12188 if (!(encoder->compute_config(encoder, pipe_config))) {
12189 DRM_DEBUG_KMS("Encoder config failure\n");
12194 /* Set default port clock if not overwritten by the encoder. Needs to be
12195 * done afterwards in case the encoder adjusts the mode. */
12196 if (!pipe_config->port_clock)
12197 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12198 * pipe_config->pixel_multiplier;
12200 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12202 DRM_DEBUG_KMS("CRTC fixup failed\n");
12206 if (ret == RETRY) {
12207 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12212 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12214 goto encoder_retry;
12217 /* Dithering seems to not pass-through bits correctly when it should, so
12218 * only enable it on 6bpc panels. */
12219 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12220 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12221 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12228 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12230 struct drm_crtc *crtc;
12231 struct drm_crtc_state *crtc_state;
12234 /* Double check state. */
12235 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12236 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12238 /* Update hwmode for vblank functions */
12239 if (crtc->state->active)
12240 crtc->hwmode = crtc->state->adjusted_mode;
12242 crtc->hwmode.crtc_clock = 0;
12246 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12250 if (clock1 == clock2)
12253 if (!clock1 || !clock2)
12256 diff = abs(clock1 - clock2);
12258 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12264 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12265 list_for_each_entry((intel_crtc), \
12266 &(dev)->mode_config.crtc_list, \
12268 if (mask & (1 <<(intel_crtc)->pipe))
12271 intel_compare_m_n(unsigned int m, unsigned int n,
12272 unsigned int m2, unsigned int n2,
12275 if (m == m2 && n == n2)
12278 if (exact || !m || !n || !m2 || !n2)
12281 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12288 } else if (m < m2) {
12295 return m == m2 && n == n2;
12299 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12300 struct intel_link_m_n *m2_n2,
12303 if (m_n->tu == m2_n2->tu &&
12304 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12305 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12306 intel_compare_m_n(m_n->link_m, m_n->link_n,
12307 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12318 intel_pipe_config_compare(struct drm_device *dev,
12319 struct intel_crtc_state *current_config,
12320 struct intel_crtc_state *pipe_config,
12325 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12328 DRM_ERROR(fmt, ##__VA_ARGS__); \
12330 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12333 #define PIPE_CONF_CHECK_X(name) \
12334 if (current_config->name != pipe_config->name) { \
12335 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12336 "(expected 0x%08x, found 0x%08x)\n", \
12337 current_config->name, \
12338 pipe_config->name); \
12342 #define PIPE_CONF_CHECK_I(name) \
12343 if (current_config->name != pipe_config->name) { \
12344 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12345 "(expected %i, found %i)\n", \
12346 current_config->name, \
12347 pipe_config->name); \
12351 #define PIPE_CONF_CHECK_M_N(name) \
12352 if (!intel_compare_link_m_n(¤t_config->name, \
12353 &pipe_config->name,\
12355 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12356 "(expected tu %i gmch %i/%i link %i/%i, " \
12357 "found tu %i, gmch %i/%i link %i/%i)\n", \
12358 current_config->name.tu, \
12359 current_config->name.gmch_m, \
12360 current_config->name.gmch_n, \
12361 current_config->name.link_m, \
12362 current_config->name.link_n, \
12363 pipe_config->name.tu, \
12364 pipe_config->name.gmch_m, \
12365 pipe_config->name.gmch_n, \
12366 pipe_config->name.link_m, \
12367 pipe_config->name.link_n); \
12371 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12372 if (!intel_compare_link_m_n(¤t_config->name, \
12373 &pipe_config->name, adjust) && \
12374 !intel_compare_link_m_n(¤t_config->alt_name, \
12375 &pipe_config->name, adjust)) { \
12376 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12377 "(expected tu %i gmch %i/%i link %i/%i, " \
12378 "or tu %i gmch %i/%i link %i/%i, " \
12379 "found tu %i, gmch %i/%i link %i/%i)\n", \
12380 current_config->name.tu, \
12381 current_config->name.gmch_m, \
12382 current_config->name.gmch_n, \
12383 current_config->name.link_m, \
12384 current_config->name.link_n, \
12385 current_config->alt_name.tu, \
12386 current_config->alt_name.gmch_m, \
12387 current_config->alt_name.gmch_n, \
12388 current_config->alt_name.link_m, \
12389 current_config->alt_name.link_n, \
12390 pipe_config->name.tu, \
12391 pipe_config->name.gmch_m, \
12392 pipe_config->name.gmch_n, \
12393 pipe_config->name.link_m, \
12394 pipe_config->name.link_n); \
12398 /* This is required for BDW+ where there is only one set of registers for
12399 * switching between high and low RR.
12400 * This macro can be used whenever a comparison has to be made between one
12401 * hw state and multiple sw state variables.
12403 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12404 if ((current_config->name != pipe_config->name) && \
12405 (current_config->alt_name != pipe_config->name)) { \
12406 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12407 "(expected %i or %i, found %i)\n", \
12408 current_config->name, \
12409 current_config->alt_name, \
12410 pipe_config->name); \
12414 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12415 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12416 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12417 "(expected %i, found %i)\n", \
12418 current_config->name & (mask), \
12419 pipe_config->name & (mask)); \
12423 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12424 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12425 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12426 "(expected %i, found %i)\n", \
12427 current_config->name, \
12428 pipe_config->name); \
12432 #define PIPE_CONF_QUIRK(quirk) \
12433 ((current_config->quirks | pipe_config->quirks) & (quirk))
12435 PIPE_CONF_CHECK_I(cpu_transcoder);
12437 PIPE_CONF_CHECK_I(has_pch_encoder);
12438 PIPE_CONF_CHECK_I(fdi_lanes);
12439 PIPE_CONF_CHECK_M_N(fdi_m_n);
12441 PIPE_CONF_CHECK_I(has_dp_encoder);
12442 PIPE_CONF_CHECK_I(lane_count);
12444 if (INTEL_INFO(dev)->gen < 8) {
12445 PIPE_CONF_CHECK_M_N(dp_m_n);
12447 PIPE_CONF_CHECK_I(has_drrs);
12448 if (current_config->has_drrs)
12449 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12451 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12453 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12454 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12455 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12456 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12457 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12458 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12460 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12461 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12462 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12463 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12464 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12465 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12467 PIPE_CONF_CHECK_I(pixel_multiplier);
12468 PIPE_CONF_CHECK_I(has_hdmi_sink);
12469 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12470 IS_VALLEYVIEW(dev))
12471 PIPE_CONF_CHECK_I(limited_color_range);
12472 PIPE_CONF_CHECK_I(has_infoframe);
12474 PIPE_CONF_CHECK_I(has_audio);
12476 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12477 DRM_MODE_FLAG_INTERLACE);
12479 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12480 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12481 DRM_MODE_FLAG_PHSYNC);
12482 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12483 DRM_MODE_FLAG_NHSYNC);
12484 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12485 DRM_MODE_FLAG_PVSYNC);
12486 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12487 DRM_MODE_FLAG_NVSYNC);
12490 PIPE_CONF_CHECK_X(gmch_pfit.control);
12491 /* pfit ratios are autocomputed by the hw on gen4+ */
12492 if (INTEL_INFO(dev)->gen < 4)
12493 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12494 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12497 PIPE_CONF_CHECK_I(pipe_src_w);
12498 PIPE_CONF_CHECK_I(pipe_src_h);
12500 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12501 if (current_config->pch_pfit.enabled) {
12502 PIPE_CONF_CHECK_X(pch_pfit.pos);
12503 PIPE_CONF_CHECK_X(pch_pfit.size);
12506 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12509 /* BDW+ don't expose a synchronous way to read the state */
12510 if (IS_HASWELL(dev))
12511 PIPE_CONF_CHECK_I(ips_enabled);
12513 PIPE_CONF_CHECK_I(double_wide);
12515 PIPE_CONF_CHECK_X(ddi_pll_sel);
12517 PIPE_CONF_CHECK_I(shared_dpll);
12518 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12519 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12520 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12521 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12522 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12523 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12524 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12525 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12528 PIPE_CONF_CHECK_I(pipe_bpp);
12530 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12531 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12533 #undef PIPE_CONF_CHECK_X
12534 #undef PIPE_CONF_CHECK_I
12535 #undef PIPE_CONF_CHECK_I_ALT
12536 #undef PIPE_CONF_CHECK_FLAGS
12537 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12538 #undef PIPE_CONF_QUIRK
12539 #undef INTEL_ERR_OR_DBG_KMS
12544 static void check_wm_state(struct drm_device *dev)
12546 struct drm_i915_private *dev_priv = dev->dev_private;
12547 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12548 struct intel_crtc *intel_crtc;
12551 if (INTEL_INFO(dev)->gen < 9)
12554 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12555 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12557 for_each_intel_crtc(dev, intel_crtc) {
12558 struct skl_ddb_entry *hw_entry, *sw_entry;
12559 const enum pipe pipe = intel_crtc->pipe;
12561 if (!intel_crtc->active)
12565 for_each_plane(dev_priv, pipe, plane) {
12566 hw_entry = &hw_ddb.plane[pipe][plane];
12567 sw_entry = &sw_ddb->plane[pipe][plane];
12569 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12572 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12573 "(expected (%u,%u), found (%u,%u))\n",
12574 pipe_name(pipe), plane + 1,
12575 sw_entry->start, sw_entry->end,
12576 hw_entry->start, hw_entry->end);
12580 hw_entry = &hw_ddb.cursor[pipe];
12581 sw_entry = &sw_ddb->cursor[pipe];
12583 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12586 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12587 "(expected (%u,%u), found (%u,%u))\n",
12589 sw_entry->start, sw_entry->end,
12590 hw_entry->start, hw_entry->end);
12595 check_connector_state(struct drm_device *dev,
12596 struct drm_atomic_state *old_state)
12598 struct drm_connector_state *old_conn_state;
12599 struct drm_connector *connector;
12602 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12603 struct drm_encoder *encoder = connector->encoder;
12604 struct drm_connector_state *state = connector->state;
12606 /* This also checks the encoder/connector hw state with the
12607 * ->get_hw_state callbacks. */
12608 intel_connector_check_state(to_intel_connector(connector));
12610 I915_STATE_WARN(state->best_encoder != encoder,
12611 "connector's atomic encoder doesn't match legacy encoder\n");
12616 check_encoder_state(struct drm_device *dev)
12618 struct intel_encoder *encoder;
12619 struct intel_connector *connector;
12621 for_each_intel_encoder(dev, encoder) {
12622 bool enabled = false;
12625 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12626 encoder->base.base.id,
12627 encoder->base.name);
12629 for_each_intel_connector(dev, connector) {
12630 if (connector->base.state->best_encoder != &encoder->base)
12634 I915_STATE_WARN(connector->base.state->crtc !=
12635 encoder->base.crtc,
12636 "connector's crtc doesn't match encoder crtc\n");
12639 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12640 "encoder's enabled state mismatch "
12641 "(expected %i, found %i)\n",
12642 !!encoder->base.crtc, enabled);
12644 if (!encoder->base.crtc) {
12647 active = encoder->get_hw_state(encoder, &pipe);
12648 I915_STATE_WARN(active,
12649 "encoder detached but still enabled on pipe %c.\n",
12656 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12658 struct drm_i915_private *dev_priv = dev->dev_private;
12659 struct intel_encoder *encoder;
12660 struct drm_crtc_state *old_crtc_state;
12661 struct drm_crtc *crtc;
12664 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12666 struct intel_crtc_state *pipe_config, *sw_config;
12669 if (!needs_modeset(crtc->state) &&
12670 !to_intel_crtc_state(crtc->state)->update_pipe)
12673 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12674 pipe_config = to_intel_crtc_state(old_crtc_state);
12675 memset(pipe_config, 0, sizeof(*pipe_config));
12676 pipe_config->base.crtc = crtc;
12677 pipe_config->base.state = old_state;
12679 DRM_DEBUG_KMS("[CRTC:%d]\n",
12682 active = dev_priv->display.get_pipe_config(intel_crtc,
12685 /* hw state is inconsistent with the pipe quirk */
12686 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12687 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12688 active = crtc->state->active;
12690 I915_STATE_WARN(crtc->state->active != active,
12691 "crtc active state doesn't match with hw state "
12692 "(expected %i, found %i)\n", crtc->state->active, active);
12694 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12695 "transitional active state does not match atomic hw state "
12696 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12698 for_each_encoder_on_crtc(dev, crtc, encoder) {
12701 active = encoder->get_hw_state(encoder, &pipe);
12702 I915_STATE_WARN(active != crtc->state->active,
12703 "[ENCODER:%i] active %i with crtc active %i\n",
12704 encoder->base.base.id, active, crtc->state->active);
12706 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12707 "Encoder connected to wrong pipe %c\n",
12711 encoder->get_config(encoder, pipe_config);
12714 if (!crtc->state->active)
12717 sw_config = to_intel_crtc_state(crtc->state);
12718 if (!intel_pipe_config_compare(dev, sw_config,
12719 pipe_config, false)) {
12720 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12721 intel_dump_pipe_config(intel_crtc, pipe_config,
12723 intel_dump_pipe_config(intel_crtc, sw_config,
12730 check_shared_dpll_state(struct drm_device *dev)
12732 struct drm_i915_private *dev_priv = dev->dev_private;
12733 struct intel_crtc *crtc;
12734 struct intel_dpll_hw_state dpll_hw_state;
12737 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12738 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12739 int enabled_crtcs = 0, active_crtcs = 0;
12742 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12744 DRM_DEBUG_KMS("%s\n", pll->name);
12746 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12748 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12749 "more active pll users than references: %i vs %i\n",
12750 pll->active, hweight32(pll->config.crtc_mask));
12751 I915_STATE_WARN(pll->active && !pll->on,
12752 "pll in active use but not on in sw tracking\n");
12753 I915_STATE_WARN(pll->on && !pll->active,
12754 "pll in on but not on in use in sw tracking\n");
12755 I915_STATE_WARN(pll->on != active,
12756 "pll on state mismatch (expected %i, found %i)\n",
12759 for_each_intel_crtc(dev, crtc) {
12760 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12762 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12765 I915_STATE_WARN(pll->active != active_crtcs,
12766 "pll active crtcs mismatch (expected %i, found %i)\n",
12767 pll->active, active_crtcs);
12768 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12769 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12770 hweight32(pll->config.crtc_mask), enabled_crtcs);
12772 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12773 sizeof(dpll_hw_state)),
12774 "pll hw state mismatch\n");
12779 intel_modeset_check_state(struct drm_device *dev,
12780 struct drm_atomic_state *old_state)
12782 check_wm_state(dev);
12783 check_connector_state(dev, old_state);
12784 check_encoder_state(dev);
12785 check_crtc_state(dev, old_state);
12786 check_shared_dpll_state(dev);
12789 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12793 * FDI already provided one idea for the dotclock.
12794 * Yell if the encoder disagrees.
12796 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12797 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12798 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12801 static void update_scanline_offset(struct intel_crtc *crtc)
12803 struct drm_device *dev = crtc->base.dev;
12806 * The scanline counter increments at the leading edge of hsync.
12808 * On most platforms it starts counting from vtotal-1 on the
12809 * first active line. That means the scanline counter value is
12810 * always one less than what we would expect. Ie. just after
12811 * start of vblank, which also occurs at start of hsync (on the
12812 * last active line), the scanline counter will read vblank_start-1.
12814 * On gen2 the scanline counter starts counting from 1 instead
12815 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12816 * to keep the value positive), instead of adding one.
12818 * On HSW+ the behaviour of the scanline counter depends on the output
12819 * type. For DP ports it behaves like most other platforms, but on HDMI
12820 * there's an extra 1 line difference. So we need to add two instead of
12821 * one to the value.
12823 if (IS_GEN2(dev)) {
12824 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12827 vtotal = adjusted_mode->crtc_vtotal;
12828 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12831 crtc->scanline_offset = vtotal - 1;
12832 } else if (HAS_DDI(dev) &&
12833 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12834 crtc->scanline_offset = 2;
12836 crtc->scanline_offset = 1;
12839 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12841 struct drm_device *dev = state->dev;
12842 struct drm_i915_private *dev_priv = to_i915(dev);
12843 struct intel_shared_dpll_config *shared_dpll = NULL;
12844 struct intel_crtc *intel_crtc;
12845 struct intel_crtc_state *intel_crtc_state;
12846 struct drm_crtc *crtc;
12847 struct drm_crtc_state *crtc_state;
12850 if (!dev_priv->display.crtc_compute_clock)
12853 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12856 intel_crtc = to_intel_crtc(crtc);
12857 intel_crtc_state = to_intel_crtc_state(crtc_state);
12858 dpll = intel_crtc_state->shared_dpll;
12860 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12863 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12866 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12868 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12873 * This implements the workaround described in the "notes" section of the mode
12874 * set sequence documentation. When going from no pipes or single pipe to
12875 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12876 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12878 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12880 struct drm_crtc_state *crtc_state;
12881 struct intel_crtc *intel_crtc;
12882 struct drm_crtc *crtc;
12883 struct intel_crtc_state *first_crtc_state = NULL;
12884 struct intel_crtc_state *other_crtc_state = NULL;
12885 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12888 /* look at all crtc's that are going to be enabled in during modeset */
12889 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12890 intel_crtc = to_intel_crtc(crtc);
12892 if (!crtc_state->active || !needs_modeset(crtc_state))
12895 if (first_crtc_state) {
12896 other_crtc_state = to_intel_crtc_state(crtc_state);
12899 first_crtc_state = to_intel_crtc_state(crtc_state);
12900 first_pipe = intel_crtc->pipe;
12904 /* No workaround needed? */
12905 if (!first_crtc_state)
12908 /* w/a possibly needed, check how many crtc's are already enabled. */
12909 for_each_intel_crtc(state->dev, intel_crtc) {
12910 struct intel_crtc_state *pipe_config;
12912 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12913 if (IS_ERR(pipe_config))
12914 return PTR_ERR(pipe_config);
12916 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12918 if (!pipe_config->base.active ||
12919 needs_modeset(&pipe_config->base))
12922 /* 2 or more enabled crtcs means no need for w/a */
12923 if (enabled_pipe != INVALID_PIPE)
12926 enabled_pipe = intel_crtc->pipe;
12929 if (enabled_pipe != INVALID_PIPE)
12930 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12931 else if (other_crtc_state)
12932 other_crtc_state->hsw_workaround_pipe = first_pipe;
12937 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12939 struct drm_crtc *crtc;
12940 struct drm_crtc_state *crtc_state;
12943 /* add all active pipes to the state */
12944 for_each_crtc(state->dev, crtc) {
12945 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12946 if (IS_ERR(crtc_state))
12947 return PTR_ERR(crtc_state);
12949 if (!crtc_state->active || needs_modeset(crtc_state))
12952 crtc_state->mode_changed = true;
12954 ret = drm_atomic_add_affected_connectors(state, crtc);
12958 ret = drm_atomic_add_affected_planes(state, crtc);
12966 static int intel_modeset_checks(struct drm_atomic_state *state)
12968 struct drm_device *dev = state->dev;
12969 struct drm_i915_private *dev_priv = dev->dev_private;
12972 if (!check_digital_port_conflicts(state)) {
12973 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12978 * See if the config requires any additional preparation, e.g.
12979 * to adjust global state with pipes off. We need to do this
12980 * here so we can get the modeset_pipe updated config for the new
12981 * mode set on this crtc. For other crtcs we need to use the
12982 * adjusted_mode bits in the crtc directly.
12984 if (dev_priv->display.modeset_calc_cdclk) {
12985 unsigned int cdclk;
12987 ret = dev_priv->display.modeset_calc_cdclk(state);
12989 cdclk = to_intel_atomic_state(state)->cdclk;
12990 if (!ret && cdclk != dev_priv->cdclk_freq)
12991 ret = intel_modeset_all_pipes(state);
12996 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
12998 intel_modeset_clear_plls(state);
13000 if (IS_HASWELL(dev))
13001 return haswell_mode_set_planes_workaround(state);
13007 * intel_atomic_check - validate state object
13009 * @state: state to validate
13011 static int intel_atomic_check(struct drm_device *dev,
13012 struct drm_atomic_state *state)
13014 struct drm_crtc *crtc;
13015 struct drm_crtc_state *crtc_state;
13017 bool any_ms = false;
13019 ret = drm_atomic_helper_check_modeset(dev, state);
13023 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13024 struct intel_crtc_state *pipe_config =
13025 to_intel_crtc_state(crtc_state);
13027 /* Catch I915_MODE_FLAG_INHERITED */
13028 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13029 crtc_state->mode_changed = true;
13031 if (!crtc_state->enable) {
13032 if (needs_modeset(crtc_state))
13037 if (!needs_modeset(crtc_state))
13040 /* FIXME: For only active_changed we shouldn't need to do any
13041 * state recomputation at all. */
13043 ret = drm_atomic_add_affected_connectors(state, crtc);
13047 ret = intel_modeset_pipe_config(crtc, pipe_config);
13051 if (intel_pipe_config_compare(state->dev,
13052 to_intel_crtc_state(crtc->state),
13053 pipe_config, true)) {
13054 crtc_state->mode_changed = false;
13055 to_intel_crtc_state(crtc_state)->update_pipe = true;
13058 if (needs_modeset(crtc_state)) {
13061 ret = drm_atomic_add_affected_planes(state, crtc);
13066 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13067 needs_modeset(crtc_state) ?
13068 "[modeset]" : "[fastset]");
13072 ret = intel_modeset_checks(state);
13077 to_intel_atomic_state(state)->cdclk =
13078 to_i915(state->dev)->cdclk_freq;
13080 return drm_atomic_helper_check_planes(state->dev, state);
13084 * intel_atomic_commit - commit validated state object
13086 * @state: the top-level driver state object
13087 * @async: asynchronous commit
13089 * This function commits a top-level state object that has been validated
13090 * with drm_atomic_helper_check().
13092 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13093 * we can only handle plane-related operations and do not yet support
13094 * asynchronous commit.
13097 * Zero for success or -errno.
13099 static int intel_atomic_commit(struct drm_device *dev,
13100 struct drm_atomic_state *state,
13103 struct drm_i915_private *dev_priv = dev->dev_private;
13104 struct drm_crtc *crtc;
13105 struct drm_crtc_state *crtc_state;
13108 bool any_ms = false;
13111 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13115 ret = drm_atomic_helper_prepare_planes(dev, state);
13119 drm_atomic_helper_swap_state(dev, state);
13121 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13124 if (!needs_modeset(crtc->state))
13128 intel_pre_plane_update(intel_crtc);
13130 if (crtc_state->active) {
13131 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13132 dev_priv->display.crtc_disable(crtc);
13133 intel_crtc->active = false;
13134 intel_disable_shared_dpll(intel_crtc);
13138 /* Only after disabling all output pipelines that will be changed can we
13139 * update the the output configuration. */
13140 intel_modeset_update_crtc_state(state);
13143 intel_shared_dpll_commit(state);
13145 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13146 modeset_update_crtc_power_domains(state);
13149 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13150 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13152 bool modeset = needs_modeset(crtc->state);
13153 bool update_pipe = !modeset &&
13154 to_intel_crtc_state(crtc->state)->update_pipe;
13155 unsigned long put_domains = 0;
13157 if (modeset && crtc->state->active) {
13158 update_scanline_offset(to_intel_crtc(crtc));
13159 dev_priv->display.crtc_enable(crtc);
13163 put_domains = modeset_get_crtc_power_domains(crtc);
13165 /* make sure intel_modeset_check_state runs */
13170 intel_pre_plane_update(intel_crtc);
13172 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13175 modeset_put_power_domains(dev_priv, put_domains);
13177 intel_post_plane_update(intel_crtc);
13180 /* FIXME: add subpixel order */
13182 drm_atomic_helper_wait_for_vblanks(dev, state);
13183 drm_atomic_helper_cleanup_planes(dev, state);
13186 intel_modeset_check_state(dev, state);
13188 drm_atomic_state_free(state);
13193 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13195 struct drm_device *dev = crtc->dev;
13196 struct drm_atomic_state *state;
13197 struct drm_crtc_state *crtc_state;
13200 state = drm_atomic_state_alloc(dev);
13202 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13207 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13210 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13211 ret = PTR_ERR_OR_ZERO(crtc_state);
13213 if (!crtc_state->active)
13216 crtc_state->mode_changed = true;
13217 ret = drm_atomic_commit(state);
13220 if (ret == -EDEADLK) {
13221 drm_atomic_state_clear(state);
13222 drm_modeset_backoff(state->acquire_ctx);
13228 drm_atomic_state_free(state);
13231 #undef for_each_intel_crtc_masked
13233 static const struct drm_crtc_funcs intel_crtc_funcs = {
13234 .gamma_set = intel_crtc_gamma_set,
13235 .set_config = drm_atomic_helper_set_config,
13236 .destroy = intel_crtc_destroy,
13237 .page_flip = intel_crtc_page_flip,
13238 .atomic_duplicate_state = intel_crtc_duplicate_state,
13239 .atomic_destroy_state = intel_crtc_destroy_state,
13242 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13243 struct intel_shared_dpll *pll,
13244 struct intel_dpll_hw_state *hw_state)
13248 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13251 val = I915_READ(PCH_DPLL(pll->id));
13252 hw_state->dpll = val;
13253 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13254 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13256 return val & DPLL_VCO_ENABLE;
13259 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13260 struct intel_shared_dpll *pll)
13262 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13263 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13266 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13267 struct intel_shared_dpll *pll)
13269 /* PCH refclock must be enabled first */
13270 ibx_assert_pch_refclk_enabled(dev_priv);
13272 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13274 /* Wait for the clocks to stabilize. */
13275 POSTING_READ(PCH_DPLL(pll->id));
13278 /* The pixel multiplier can only be updated once the
13279 * DPLL is enabled and the clocks are stable.
13281 * So write it again.
13283 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13284 POSTING_READ(PCH_DPLL(pll->id));
13288 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13289 struct intel_shared_dpll *pll)
13291 struct drm_device *dev = dev_priv->dev;
13292 struct intel_crtc *crtc;
13294 /* Make sure no transcoder isn't still depending on us. */
13295 for_each_intel_crtc(dev, crtc) {
13296 if (intel_crtc_to_shared_dpll(crtc) == pll)
13297 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13300 I915_WRITE(PCH_DPLL(pll->id), 0);
13301 POSTING_READ(PCH_DPLL(pll->id));
13305 static char *ibx_pch_dpll_names[] = {
13310 static void ibx_pch_dpll_init(struct drm_device *dev)
13312 struct drm_i915_private *dev_priv = dev->dev_private;
13315 dev_priv->num_shared_dpll = 2;
13317 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13318 dev_priv->shared_dplls[i].id = i;
13319 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13320 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13321 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13322 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13323 dev_priv->shared_dplls[i].get_hw_state =
13324 ibx_pch_dpll_get_hw_state;
13328 static void intel_shared_dpll_init(struct drm_device *dev)
13330 struct drm_i915_private *dev_priv = dev->dev_private;
13332 intel_update_cdclk(dev);
13335 intel_ddi_pll_init(dev);
13336 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13337 ibx_pch_dpll_init(dev);
13339 dev_priv->num_shared_dpll = 0;
13341 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13345 * intel_prepare_plane_fb - Prepare fb for usage on plane
13346 * @plane: drm plane to prepare for
13347 * @fb: framebuffer to prepare for presentation
13349 * Prepares a framebuffer for usage on a display plane. Generally this
13350 * involves pinning the underlying object and updating the frontbuffer tracking
13351 * bits. Some older platforms need special physical address handling for
13354 * Returns 0 on success, negative error code on failure.
13357 intel_prepare_plane_fb(struct drm_plane *plane,
13358 const struct drm_plane_state *new_state)
13360 struct drm_device *dev = plane->dev;
13361 struct drm_framebuffer *fb = new_state->fb;
13362 struct intel_plane *intel_plane = to_intel_plane(plane);
13363 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13364 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13370 mutex_lock(&dev->struct_mutex);
13372 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13373 INTEL_INFO(dev)->cursor_needs_physical) {
13374 int align = IS_I830(dev) ? 16 * 1024 : 256;
13375 ret = i915_gem_object_attach_phys(obj, align);
13377 DRM_DEBUG_KMS("failed to attach phys object\n");
13379 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13383 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13385 mutex_unlock(&dev->struct_mutex);
13391 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13392 * @plane: drm plane to clean up for
13393 * @fb: old framebuffer that was on plane
13395 * Cleans up a framebuffer that has just been removed from a plane.
13398 intel_cleanup_plane_fb(struct drm_plane *plane,
13399 const struct drm_plane_state *old_state)
13401 struct drm_device *dev = plane->dev;
13402 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13407 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13408 !INTEL_INFO(dev)->cursor_needs_physical) {
13409 mutex_lock(&dev->struct_mutex);
13410 intel_unpin_fb_obj(old_state->fb, old_state);
13411 mutex_unlock(&dev->struct_mutex);
13416 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13419 struct drm_device *dev;
13420 struct drm_i915_private *dev_priv;
13421 int crtc_clock, cdclk;
13423 if (!intel_crtc || !crtc_state)
13424 return DRM_PLANE_HELPER_NO_SCALING;
13426 dev = intel_crtc->base.dev;
13427 dev_priv = dev->dev_private;
13428 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13429 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13431 if (!crtc_clock || !cdclk)
13432 return DRM_PLANE_HELPER_NO_SCALING;
13435 * skl max scale is lower of:
13436 * close to 3 but not 3, -1 is for that purpose
13440 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13446 intel_check_primary_plane(struct drm_plane *plane,
13447 struct intel_crtc_state *crtc_state,
13448 struct intel_plane_state *state)
13450 struct drm_crtc *crtc = state->base.crtc;
13451 struct drm_framebuffer *fb = state->base.fb;
13452 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13453 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13454 bool can_position = false;
13456 /* use scaler when colorkey is not required */
13457 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13458 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13460 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13461 can_position = true;
13464 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13465 &state->dst, &state->clip,
13466 min_scale, max_scale,
13467 can_position, true,
13472 intel_commit_primary_plane(struct drm_plane *plane,
13473 struct intel_plane_state *state)
13475 struct drm_crtc *crtc = state->base.crtc;
13476 struct drm_framebuffer *fb = state->base.fb;
13477 struct drm_device *dev = plane->dev;
13478 struct drm_i915_private *dev_priv = dev->dev_private;
13479 struct intel_crtc *intel_crtc;
13480 struct drm_rect *src = &state->src;
13482 crtc = crtc ? crtc : plane->crtc;
13483 intel_crtc = to_intel_crtc(crtc);
13486 crtc->x = src->x1 >> 16;
13487 crtc->y = src->y1 >> 16;
13489 if (!crtc->state->active)
13492 dev_priv->display.update_primary_plane(crtc, fb,
13493 state->src.x1 >> 16,
13494 state->src.y1 >> 16);
13498 intel_disable_primary_plane(struct drm_plane *plane,
13499 struct drm_crtc *crtc)
13501 struct drm_device *dev = plane->dev;
13502 struct drm_i915_private *dev_priv = dev->dev_private;
13504 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13507 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13508 struct drm_crtc_state *old_crtc_state)
13510 struct drm_device *dev = crtc->dev;
13511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13512 struct intel_crtc_state *old_intel_state =
13513 to_intel_crtc_state(old_crtc_state);
13514 bool modeset = needs_modeset(crtc->state);
13516 if (intel_crtc->atomic.update_wm_pre)
13517 intel_update_watermarks(crtc);
13519 /* Perform vblank evasion around commit operation */
13520 if (crtc->state->active)
13521 intel_pipe_update_start(intel_crtc);
13526 if (to_intel_crtc_state(crtc->state)->update_pipe)
13527 intel_update_pipe_config(intel_crtc, old_intel_state);
13528 else if (INTEL_INFO(dev)->gen >= 9)
13529 skl_detach_scalers(intel_crtc);
13532 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13533 struct drm_crtc_state *old_crtc_state)
13535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13537 if (crtc->state->active)
13538 intel_pipe_update_end(intel_crtc);
13542 * intel_plane_destroy - destroy a plane
13543 * @plane: plane to destroy
13545 * Common destruction function for all types of planes (primary, cursor,
13548 void intel_plane_destroy(struct drm_plane *plane)
13550 struct intel_plane *intel_plane = to_intel_plane(plane);
13551 drm_plane_cleanup(plane);
13552 kfree(intel_plane);
13555 const struct drm_plane_funcs intel_plane_funcs = {
13556 .update_plane = drm_atomic_helper_update_plane,
13557 .disable_plane = drm_atomic_helper_disable_plane,
13558 .destroy = intel_plane_destroy,
13559 .set_property = drm_atomic_helper_plane_set_property,
13560 .atomic_get_property = intel_plane_atomic_get_property,
13561 .atomic_set_property = intel_plane_atomic_set_property,
13562 .atomic_duplicate_state = intel_plane_duplicate_state,
13563 .atomic_destroy_state = intel_plane_destroy_state,
13567 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13570 struct intel_plane *primary;
13571 struct intel_plane_state *state;
13572 const uint32_t *intel_primary_formats;
13573 unsigned int num_formats;
13575 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13576 if (primary == NULL)
13579 state = intel_create_plane_state(&primary->base);
13584 primary->base.state = &state->base;
13586 primary->can_scale = false;
13587 primary->max_downscale = 1;
13588 if (INTEL_INFO(dev)->gen >= 9) {
13589 primary->can_scale = true;
13590 state->scaler_id = -1;
13592 primary->pipe = pipe;
13593 primary->plane = pipe;
13594 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13595 primary->check_plane = intel_check_primary_plane;
13596 primary->commit_plane = intel_commit_primary_plane;
13597 primary->disable_plane = intel_disable_primary_plane;
13598 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13599 primary->plane = !pipe;
13601 if (INTEL_INFO(dev)->gen >= 9) {
13602 intel_primary_formats = skl_primary_formats;
13603 num_formats = ARRAY_SIZE(skl_primary_formats);
13604 } else if (INTEL_INFO(dev)->gen >= 4) {
13605 intel_primary_formats = i965_primary_formats;
13606 num_formats = ARRAY_SIZE(i965_primary_formats);
13608 intel_primary_formats = i8xx_primary_formats;
13609 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13612 drm_universal_plane_init(dev, &primary->base, 0,
13613 &intel_plane_funcs,
13614 intel_primary_formats, num_formats,
13615 DRM_PLANE_TYPE_PRIMARY);
13617 if (INTEL_INFO(dev)->gen >= 4)
13618 intel_create_rotation_property(dev, primary);
13620 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13622 return &primary->base;
13625 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13627 if (!dev->mode_config.rotation_property) {
13628 unsigned long flags = BIT(DRM_ROTATE_0) |
13629 BIT(DRM_ROTATE_180);
13631 if (INTEL_INFO(dev)->gen >= 9)
13632 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13634 dev->mode_config.rotation_property =
13635 drm_mode_create_rotation_property(dev, flags);
13637 if (dev->mode_config.rotation_property)
13638 drm_object_attach_property(&plane->base.base,
13639 dev->mode_config.rotation_property,
13640 plane->base.state->rotation);
13644 intel_check_cursor_plane(struct drm_plane *plane,
13645 struct intel_crtc_state *crtc_state,
13646 struct intel_plane_state *state)
13648 struct drm_crtc *crtc = crtc_state->base.crtc;
13649 struct drm_framebuffer *fb = state->base.fb;
13650 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13654 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13655 &state->dst, &state->clip,
13656 DRM_PLANE_HELPER_NO_SCALING,
13657 DRM_PLANE_HELPER_NO_SCALING,
13658 true, true, &state->visible);
13662 /* if we want to turn off the cursor ignore width and height */
13666 /* Check for which cursor types we support */
13667 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13668 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13669 state->base.crtc_w, state->base.crtc_h);
13673 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13674 if (obj->base.size < stride * state->base.crtc_h) {
13675 DRM_DEBUG_KMS("buffer is too small\n");
13679 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13680 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13688 intel_disable_cursor_plane(struct drm_plane *plane,
13689 struct drm_crtc *crtc)
13691 intel_crtc_update_cursor(crtc, false);
13695 intel_commit_cursor_plane(struct drm_plane *plane,
13696 struct intel_plane_state *state)
13698 struct drm_crtc *crtc = state->base.crtc;
13699 struct drm_device *dev = plane->dev;
13700 struct intel_crtc *intel_crtc;
13701 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13704 crtc = crtc ? crtc : plane->crtc;
13705 intel_crtc = to_intel_crtc(crtc);
13707 if (intel_crtc->cursor_bo == obj)
13712 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13713 addr = i915_gem_obj_ggtt_offset(obj);
13715 addr = obj->phys_handle->busaddr;
13717 intel_crtc->cursor_addr = addr;
13718 intel_crtc->cursor_bo = obj;
13721 if (crtc->state->active)
13722 intel_crtc_update_cursor(crtc, state->visible);
13725 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13728 struct intel_plane *cursor;
13729 struct intel_plane_state *state;
13731 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13732 if (cursor == NULL)
13735 state = intel_create_plane_state(&cursor->base);
13740 cursor->base.state = &state->base;
13742 cursor->can_scale = false;
13743 cursor->max_downscale = 1;
13744 cursor->pipe = pipe;
13745 cursor->plane = pipe;
13746 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13747 cursor->check_plane = intel_check_cursor_plane;
13748 cursor->commit_plane = intel_commit_cursor_plane;
13749 cursor->disable_plane = intel_disable_cursor_plane;
13751 drm_universal_plane_init(dev, &cursor->base, 0,
13752 &intel_plane_funcs,
13753 intel_cursor_formats,
13754 ARRAY_SIZE(intel_cursor_formats),
13755 DRM_PLANE_TYPE_CURSOR);
13757 if (INTEL_INFO(dev)->gen >= 4) {
13758 if (!dev->mode_config.rotation_property)
13759 dev->mode_config.rotation_property =
13760 drm_mode_create_rotation_property(dev,
13761 BIT(DRM_ROTATE_0) |
13762 BIT(DRM_ROTATE_180));
13763 if (dev->mode_config.rotation_property)
13764 drm_object_attach_property(&cursor->base.base,
13765 dev->mode_config.rotation_property,
13766 state->base.rotation);
13769 if (INTEL_INFO(dev)->gen >=9)
13770 state->scaler_id = -1;
13772 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13774 return &cursor->base;
13777 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13778 struct intel_crtc_state *crtc_state)
13781 struct intel_scaler *intel_scaler;
13782 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13784 for (i = 0; i < intel_crtc->num_scalers; i++) {
13785 intel_scaler = &scaler_state->scalers[i];
13786 intel_scaler->in_use = 0;
13787 intel_scaler->mode = PS_SCALER_MODE_DYN;
13790 scaler_state->scaler_id = -1;
13793 static void intel_crtc_init(struct drm_device *dev, int pipe)
13795 struct drm_i915_private *dev_priv = dev->dev_private;
13796 struct intel_crtc *intel_crtc;
13797 struct intel_crtc_state *crtc_state = NULL;
13798 struct drm_plane *primary = NULL;
13799 struct drm_plane *cursor = NULL;
13802 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13803 if (intel_crtc == NULL)
13806 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13809 intel_crtc->config = crtc_state;
13810 intel_crtc->base.state = &crtc_state->base;
13811 crtc_state->base.crtc = &intel_crtc->base;
13813 /* initialize shared scalers */
13814 if (INTEL_INFO(dev)->gen >= 9) {
13815 if (pipe == PIPE_C)
13816 intel_crtc->num_scalers = 1;
13818 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13820 skl_init_scalers(dev, intel_crtc, crtc_state);
13823 primary = intel_primary_plane_create(dev, pipe);
13827 cursor = intel_cursor_plane_create(dev, pipe);
13831 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13832 cursor, &intel_crtc_funcs);
13836 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13837 for (i = 0; i < 256; i++) {
13838 intel_crtc->lut_r[i] = i;
13839 intel_crtc->lut_g[i] = i;
13840 intel_crtc->lut_b[i] = i;
13844 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13845 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13847 intel_crtc->pipe = pipe;
13848 intel_crtc->plane = pipe;
13849 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13850 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13851 intel_crtc->plane = !pipe;
13854 intel_crtc->cursor_base = ~0;
13855 intel_crtc->cursor_cntl = ~0;
13856 intel_crtc->cursor_size = ~0;
13858 intel_crtc->wm.cxsr_allowed = true;
13860 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13861 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13862 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13863 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13865 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13867 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13872 drm_plane_cleanup(primary);
13874 drm_plane_cleanup(cursor);
13879 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13881 struct drm_encoder *encoder = connector->base.encoder;
13882 struct drm_device *dev = connector->base.dev;
13884 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13886 if (!encoder || WARN_ON(!encoder->crtc))
13887 return INVALID_PIPE;
13889 return to_intel_crtc(encoder->crtc)->pipe;
13892 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13893 struct drm_file *file)
13895 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13896 struct drm_crtc *drmmode_crtc;
13897 struct intel_crtc *crtc;
13899 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13901 if (!drmmode_crtc) {
13902 DRM_ERROR("no such CRTC id\n");
13906 crtc = to_intel_crtc(drmmode_crtc);
13907 pipe_from_crtc_id->pipe = crtc->pipe;
13912 static int intel_encoder_clones(struct intel_encoder *encoder)
13914 struct drm_device *dev = encoder->base.dev;
13915 struct intel_encoder *source_encoder;
13916 int index_mask = 0;
13919 for_each_intel_encoder(dev, source_encoder) {
13920 if (encoders_cloneable(encoder, source_encoder))
13921 index_mask |= (1 << entry);
13929 static bool has_edp_a(struct drm_device *dev)
13931 struct drm_i915_private *dev_priv = dev->dev_private;
13933 if (!IS_MOBILE(dev))
13936 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13939 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13945 static bool intel_crt_present(struct drm_device *dev)
13947 struct drm_i915_private *dev_priv = dev->dev_private;
13949 if (INTEL_INFO(dev)->gen >= 9)
13952 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13955 if (IS_CHERRYVIEW(dev))
13958 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13964 static void intel_setup_outputs(struct drm_device *dev)
13966 struct drm_i915_private *dev_priv = dev->dev_private;
13967 struct intel_encoder *encoder;
13968 bool dpd_is_edp = false;
13970 intel_lvds_init(dev);
13972 if (intel_crt_present(dev))
13973 intel_crt_init(dev);
13975 if (IS_BROXTON(dev)) {
13977 * FIXME: Broxton doesn't support port detection via the
13978 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13979 * detect the ports.
13981 intel_ddi_init(dev, PORT_A);
13982 intel_ddi_init(dev, PORT_B);
13983 intel_ddi_init(dev, PORT_C);
13984 } else if (HAS_DDI(dev)) {
13988 * Haswell uses DDI functions to detect digital outputs.
13989 * On SKL pre-D0 the strap isn't connected, so we assume
13992 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13993 /* WaIgnoreDDIAStrap: skl */
13994 if (found || IS_SKYLAKE(dev))
13995 intel_ddi_init(dev, PORT_A);
13997 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13999 found = I915_READ(SFUSE_STRAP);
14001 if (found & SFUSE_STRAP_DDIB_DETECTED)
14002 intel_ddi_init(dev, PORT_B);
14003 if (found & SFUSE_STRAP_DDIC_DETECTED)
14004 intel_ddi_init(dev, PORT_C);
14005 if (found & SFUSE_STRAP_DDID_DETECTED)
14006 intel_ddi_init(dev, PORT_D);
14008 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14010 if (IS_SKYLAKE(dev) &&
14011 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14012 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14013 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14014 intel_ddi_init(dev, PORT_E);
14016 } else if (HAS_PCH_SPLIT(dev)) {
14018 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14020 if (has_edp_a(dev))
14021 intel_dp_init(dev, DP_A, PORT_A);
14023 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14024 /* PCH SDVOB multiplex with HDMIB */
14025 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14027 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14028 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14029 intel_dp_init(dev, PCH_DP_B, PORT_B);
14032 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14033 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14035 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14036 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14038 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14039 intel_dp_init(dev, PCH_DP_C, PORT_C);
14041 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14042 intel_dp_init(dev, PCH_DP_D, PORT_D);
14043 } else if (IS_VALLEYVIEW(dev)) {
14045 * The DP_DETECTED bit is the latched state of the DDC
14046 * SDA pin at boot. However since eDP doesn't require DDC
14047 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14048 * eDP ports may have been muxed to an alternate function.
14049 * Thus we can't rely on the DP_DETECTED bit alone to detect
14050 * eDP ports. Consult the VBT as well as DP_DETECTED to
14051 * detect eDP ports.
14053 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14054 !intel_dp_is_edp(dev, PORT_B))
14055 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14056 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14057 intel_dp_is_edp(dev, PORT_B))
14058 intel_dp_init(dev, VLV_DP_B, PORT_B);
14060 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14061 !intel_dp_is_edp(dev, PORT_C))
14062 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14063 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14064 intel_dp_is_edp(dev, PORT_C))
14065 intel_dp_init(dev, VLV_DP_C, PORT_C);
14067 if (IS_CHERRYVIEW(dev)) {
14068 /* eDP not supported on port D, so don't check VBT */
14069 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14070 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14071 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14072 intel_dp_init(dev, CHV_DP_D, PORT_D);
14075 intel_dsi_init(dev);
14076 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14077 bool found = false;
14079 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14080 DRM_DEBUG_KMS("probing SDVOB\n");
14081 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14082 if (!found && IS_G4X(dev)) {
14083 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14084 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14087 if (!found && IS_G4X(dev))
14088 intel_dp_init(dev, DP_B, PORT_B);
14091 /* Before G4X SDVOC doesn't have its own detect register */
14093 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14094 DRM_DEBUG_KMS("probing SDVOC\n");
14095 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14098 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14101 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14102 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14105 intel_dp_init(dev, DP_C, PORT_C);
14109 (I915_READ(DP_D) & DP_DETECTED))
14110 intel_dp_init(dev, DP_D, PORT_D);
14111 } else if (IS_GEN2(dev))
14112 intel_dvo_init(dev);
14114 if (SUPPORTS_TV(dev))
14115 intel_tv_init(dev);
14117 intel_psr_init(dev);
14119 for_each_intel_encoder(dev, encoder) {
14120 encoder->base.possible_crtcs = encoder->crtc_mask;
14121 encoder->base.possible_clones =
14122 intel_encoder_clones(encoder);
14125 intel_init_pch_refclk(dev);
14127 drm_helper_move_panel_connectors_to_head(dev);
14130 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14132 struct drm_device *dev = fb->dev;
14133 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14135 drm_framebuffer_cleanup(fb);
14136 mutex_lock(&dev->struct_mutex);
14137 WARN_ON(!intel_fb->obj->framebuffer_references--);
14138 drm_gem_object_unreference(&intel_fb->obj->base);
14139 mutex_unlock(&dev->struct_mutex);
14143 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14144 struct drm_file *file,
14145 unsigned int *handle)
14147 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14148 struct drm_i915_gem_object *obj = intel_fb->obj;
14150 return drm_gem_handle_create(file, &obj->base, handle);
14153 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14154 struct drm_file *file,
14155 unsigned flags, unsigned color,
14156 struct drm_clip_rect *clips,
14157 unsigned num_clips)
14159 struct drm_device *dev = fb->dev;
14160 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14161 struct drm_i915_gem_object *obj = intel_fb->obj;
14163 mutex_lock(&dev->struct_mutex);
14164 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14165 mutex_unlock(&dev->struct_mutex);
14170 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14171 .destroy = intel_user_framebuffer_destroy,
14172 .create_handle = intel_user_framebuffer_create_handle,
14173 .dirty = intel_user_framebuffer_dirty,
14177 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14178 uint32_t pixel_format)
14180 u32 gen = INTEL_INFO(dev)->gen;
14183 /* "The stride in bytes must not exceed the of the size of 8K
14184 * pixels and 32K bytes."
14186 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14187 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14189 } else if (gen >= 4) {
14190 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14194 } else if (gen >= 3) {
14195 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14200 /* XXX DSPC is limited to 4k tiled */
14205 static int intel_framebuffer_init(struct drm_device *dev,
14206 struct intel_framebuffer *intel_fb,
14207 struct drm_mode_fb_cmd2 *mode_cmd,
14208 struct drm_i915_gem_object *obj)
14210 unsigned int aligned_height;
14212 u32 pitch_limit, stride_alignment;
14214 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14216 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14217 /* Enforce that fb modifier and tiling mode match, but only for
14218 * X-tiled. This is needed for FBC. */
14219 if (!!(obj->tiling_mode == I915_TILING_X) !=
14220 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14221 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14225 if (obj->tiling_mode == I915_TILING_X)
14226 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14227 else if (obj->tiling_mode == I915_TILING_Y) {
14228 DRM_DEBUG("No Y tiling for legacy addfb\n");
14233 /* Passed in modifier sanity checking. */
14234 switch (mode_cmd->modifier[0]) {
14235 case I915_FORMAT_MOD_Y_TILED:
14236 case I915_FORMAT_MOD_Yf_TILED:
14237 if (INTEL_INFO(dev)->gen < 9) {
14238 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14239 mode_cmd->modifier[0]);
14242 case DRM_FORMAT_MOD_NONE:
14243 case I915_FORMAT_MOD_X_TILED:
14246 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14247 mode_cmd->modifier[0]);
14251 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14252 mode_cmd->pixel_format);
14253 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14254 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14255 mode_cmd->pitches[0], stride_alignment);
14259 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14260 mode_cmd->pixel_format);
14261 if (mode_cmd->pitches[0] > pitch_limit) {
14262 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14263 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14264 "tiled" : "linear",
14265 mode_cmd->pitches[0], pitch_limit);
14269 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14270 mode_cmd->pitches[0] != obj->stride) {
14271 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14272 mode_cmd->pitches[0], obj->stride);
14276 /* Reject formats not supported by any plane early. */
14277 switch (mode_cmd->pixel_format) {
14278 case DRM_FORMAT_C8:
14279 case DRM_FORMAT_RGB565:
14280 case DRM_FORMAT_XRGB8888:
14281 case DRM_FORMAT_ARGB8888:
14283 case DRM_FORMAT_XRGB1555:
14284 if (INTEL_INFO(dev)->gen > 3) {
14285 DRM_DEBUG("unsupported pixel format: %s\n",
14286 drm_get_format_name(mode_cmd->pixel_format));
14290 case DRM_FORMAT_ABGR8888:
14291 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14292 DRM_DEBUG("unsupported pixel format: %s\n",
14293 drm_get_format_name(mode_cmd->pixel_format));
14297 case DRM_FORMAT_XBGR8888:
14298 case DRM_FORMAT_XRGB2101010:
14299 case DRM_FORMAT_XBGR2101010:
14300 if (INTEL_INFO(dev)->gen < 4) {
14301 DRM_DEBUG("unsupported pixel format: %s\n",
14302 drm_get_format_name(mode_cmd->pixel_format));
14306 case DRM_FORMAT_ABGR2101010:
14307 if (!IS_VALLEYVIEW(dev)) {
14308 DRM_DEBUG("unsupported pixel format: %s\n",
14309 drm_get_format_name(mode_cmd->pixel_format));
14313 case DRM_FORMAT_YUYV:
14314 case DRM_FORMAT_UYVY:
14315 case DRM_FORMAT_YVYU:
14316 case DRM_FORMAT_VYUY:
14317 if (INTEL_INFO(dev)->gen < 5) {
14318 DRM_DEBUG("unsupported pixel format: %s\n",
14319 drm_get_format_name(mode_cmd->pixel_format));
14324 DRM_DEBUG("unsupported pixel format: %s\n",
14325 drm_get_format_name(mode_cmd->pixel_format));
14329 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14330 if (mode_cmd->offsets[0] != 0)
14333 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14334 mode_cmd->pixel_format,
14335 mode_cmd->modifier[0]);
14336 /* FIXME drm helper for size checks (especially planar formats)? */
14337 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14340 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14341 intel_fb->obj = obj;
14342 intel_fb->obj->framebuffer_references++;
14344 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14346 DRM_ERROR("framebuffer init failed %d\n", ret);
14353 static struct drm_framebuffer *
14354 intel_user_framebuffer_create(struct drm_device *dev,
14355 struct drm_file *filp,
14356 struct drm_mode_fb_cmd2 *mode_cmd)
14358 struct drm_i915_gem_object *obj;
14360 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14361 mode_cmd->handles[0]));
14362 if (&obj->base == NULL)
14363 return ERR_PTR(-ENOENT);
14365 return intel_framebuffer_create(dev, mode_cmd, obj);
14368 #ifndef CONFIG_DRM_FBDEV_EMULATION
14369 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14374 static const struct drm_mode_config_funcs intel_mode_funcs = {
14375 .fb_create = intel_user_framebuffer_create,
14376 .output_poll_changed = intel_fbdev_output_poll_changed,
14377 .atomic_check = intel_atomic_check,
14378 .atomic_commit = intel_atomic_commit,
14379 .atomic_state_alloc = intel_atomic_state_alloc,
14380 .atomic_state_clear = intel_atomic_state_clear,
14383 /* Set up chip specific display functions */
14384 static void intel_init_display(struct drm_device *dev)
14386 struct drm_i915_private *dev_priv = dev->dev_private;
14388 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14389 dev_priv->display.find_dpll = g4x_find_best_dpll;
14390 else if (IS_CHERRYVIEW(dev))
14391 dev_priv->display.find_dpll = chv_find_best_dpll;
14392 else if (IS_VALLEYVIEW(dev))
14393 dev_priv->display.find_dpll = vlv_find_best_dpll;
14394 else if (IS_PINEVIEW(dev))
14395 dev_priv->display.find_dpll = pnv_find_best_dpll;
14397 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14399 if (INTEL_INFO(dev)->gen >= 9) {
14400 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14401 dev_priv->display.get_initial_plane_config =
14402 skylake_get_initial_plane_config;
14403 dev_priv->display.crtc_compute_clock =
14404 haswell_crtc_compute_clock;
14405 dev_priv->display.crtc_enable = haswell_crtc_enable;
14406 dev_priv->display.crtc_disable = haswell_crtc_disable;
14407 dev_priv->display.update_primary_plane =
14408 skylake_update_primary_plane;
14409 } else if (HAS_DDI(dev)) {
14410 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14411 dev_priv->display.get_initial_plane_config =
14412 ironlake_get_initial_plane_config;
14413 dev_priv->display.crtc_compute_clock =
14414 haswell_crtc_compute_clock;
14415 dev_priv->display.crtc_enable = haswell_crtc_enable;
14416 dev_priv->display.crtc_disable = haswell_crtc_disable;
14417 dev_priv->display.update_primary_plane =
14418 ironlake_update_primary_plane;
14419 } else if (HAS_PCH_SPLIT(dev)) {
14420 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14421 dev_priv->display.get_initial_plane_config =
14422 ironlake_get_initial_plane_config;
14423 dev_priv->display.crtc_compute_clock =
14424 ironlake_crtc_compute_clock;
14425 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14426 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14427 dev_priv->display.update_primary_plane =
14428 ironlake_update_primary_plane;
14429 } else if (IS_VALLEYVIEW(dev)) {
14430 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14431 dev_priv->display.get_initial_plane_config =
14432 i9xx_get_initial_plane_config;
14433 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14434 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14435 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14436 dev_priv->display.update_primary_plane =
14437 i9xx_update_primary_plane;
14439 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14440 dev_priv->display.get_initial_plane_config =
14441 i9xx_get_initial_plane_config;
14442 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14443 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14444 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14445 dev_priv->display.update_primary_plane =
14446 i9xx_update_primary_plane;
14449 /* Returns the core display clock speed */
14450 if (IS_SKYLAKE(dev))
14451 dev_priv->display.get_display_clock_speed =
14452 skylake_get_display_clock_speed;
14453 else if (IS_BROXTON(dev))
14454 dev_priv->display.get_display_clock_speed =
14455 broxton_get_display_clock_speed;
14456 else if (IS_BROADWELL(dev))
14457 dev_priv->display.get_display_clock_speed =
14458 broadwell_get_display_clock_speed;
14459 else if (IS_HASWELL(dev))
14460 dev_priv->display.get_display_clock_speed =
14461 haswell_get_display_clock_speed;
14462 else if (IS_VALLEYVIEW(dev))
14463 dev_priv->display.get_display_clock_speed =
14464 valleyview_get_display_clock_speed;
14465 else if (IS_GEN5(dev))
14466 dev_priv->display.get_display_clock_speed =
14467 ilk_get_display_clock_speed;
14468 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14469 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14470 dev_priv->display.get_display_clock_speed =
14471 i945_get_display_clock_speed;
14472 else if (IS_GM45(dev))
14473 dev_priv->display.get_display_clock_speed =
14474 gm45_get_display_clock_speed;
14475 else if (IS_CRESTLINE(dev))
14476 dev_priv->display.get_display_clock_speed =
14477 i965gm_get_display_clock_speed;
14478 else if (IS_PINEVIEW(dev))
14479 dev_priv->display.get_display_clock_speed =
14480 pnv_get_display_clock_speed;
14481 else if (IS_G33(dev) || IS_G4X(dev))
14482 dev_priv->display.get_display_clock_speed =
14483 g33_get_display_clock_speed;
14484 else if (IS_I915G(dev))
14485 dev_priv->display.get_display_clock_speed =
14486 i915_get_display_clock_speed;
14487 else if (IS_I945GM(dev) || IS_845G(dev))
14488 dev_priv->display.get_display_clock_speed =
14489 i9xx_misc_get_display_clock_speed;
14490 else if (IS_PINEVIEW(dev))
14491 dev_priv->display.get_display_clock_speed =
14492 pnv_get_display_clock_speed;
14493 else if (IS_I915GM(dev))
14494 dev_priv->display.get_display_clock_speed =
14495 i915gm_get_display_clock_speed;
14496 else if (IS_I865G(dev))
14497 dev_priv->display.get_display_clock_speed =
14498 i865_get_display_clock_speed;
14499 else if (IS_I85X(dev))
14500 dev_priv->display.get_display_clock_speed =
14501 i85x_get_display_clock_speed;
14503 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14504 dev_priv->display.get_display_clock_speed =
14505 i830_get_display_clock_speed;
14508 if (IS_GEN5(dev)) {
14509 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14510 } else if (IS_GEN6(dev)) {
14511 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14512 } else if (IS_IVYBRIDGE(dev)) {
14513 /* FIXME: detect B0+ stepping and use auto training */
14514 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14515 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14516 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14517 if (IS_BROADWELL(dev)) {
14518 dev_priv->display.modeset_commit_cdclk =
14519 broadwell_modeset_commit_cdclk;
14520 dev_priv->display.modeset_calc_cdclk =
14521 broadwell_modeset_calc_cdclk;
14523 } else if (IS_VALLEYVIEW(dev)) {
14524 dev_priv->display.modeset_commit_cdclk =
14525 valleyview_modeset_commit_cdclk;
14526 dev_priv->display.modeset_calc_cdclk =
14527 valleyview_modeset_calc_cdclk;
14528 } else if (IS_BROXTON(dev)) {
14529 dev_priv->display.modeset_commit_cdclk =
14530 broxton_modeset_commit_cdclk;
14531 dev_priv->display.modeset_calc_cdclk =
14532 broxton_modeset_calc_cdclk;
14535 switch (INTEL_INFO(dev)->gen) {
14537 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14541 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14546 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14550 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14553 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14554 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14557 /* Drop through - unsupported since execlist only. */
14559 /* Default just returns -ENODEV to indicate unsupported */
14560 dev_priv->display.queue_flip = intel_default_queue_flip;
14563 intel_panel_init_backlight_funcs(dev);
14565 mutex_init(&dev_priv->pps_mutex);
14569 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14570 * resume, or other times. This quirk makes sure that's the case for
14571 * affected systems.
14573 static void quirk_pipea_force(struct drm_device *dev)
14575 struct drm_i915_private *dev_priv = dev->dev_private;
14577 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14578 DRM_INFO("applying pipe a force quirk\n");
14581 static void quirk_pipeb_force(struct drm_device *dev)
14583 struct drm_i915_private *dev_priv = dev->dev_private;
14585 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14586 DRM_INFO("applying pipe b force quirk\n");
14590 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14592 static void quirk_ssc_force_disable(struct drm_device *dev)
14594 struct drm_i915_private *dev_priv = dev->dev_private;
14595 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14596 DRM_INFO("applying lvds SSC disable quirk\n");
14600 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14603 static void quirk_invert_brightness(struct drm_device *dev)
14605 struct drm_i915_private *dev_priv = dev->dev_private;
14606 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14607 DRM_INFO("applying inverted panel brightness quirk\n");
14610 /* Some VBT's incorrectly indicate no backlight is present */
14611 static void quirk_backlight_present(struct drm_device *dev)
14613 struct drm_i915_private *dev_priv = dev->dev_private;
14614 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14615 DRM_INFO("applying backlight present quirk\n");
14618 struct intel_quirk {
14620 int subsystem_vendor;
14621 int subsystem_device;
14622 void (*hook)(struct drm_device *dev);
14625 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14626 struct intel_dmi_quirk {
14627 void (*hook)(struct drm_device *dev);
14628 const struct dmi_system_id (*dmi_id_list)[];
14631 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14633 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14637 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14639 .dmi_id_list = &(const struct dmi_system_id[]) {
14641 .callback = intel_dmi_reverse_brightness,
14642 .ident = "NCR Corporation",
14643 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14644 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14647 { } /* terminating entry */
14649 .hook = quirk_invert_brightness,
14653 static struct intel_quirk intel_quirks[] = {
14654 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14655 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14657 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14658 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14660 /* 830 needs to leave pipe A & dpll A up */
14661 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14663 /* 830 needs to leave pipe B & dpll B up */
14664 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14666 /* Lenovo U160 cannot use SSC on LVDS */
14667 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14669 /* Sony Vaio Y cannot use SSC on LVDS */
14670 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14672 /* Acer Aspire 5734Z must invert backlight brightness */
14673 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14675 /* Acer/eMachines G725 */
14676 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14678 /* Acer/eMachines e725 */
14679 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14681 /* Acer/Packard Bell NCL20 */
14682 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14684 /* Acer Aspire 4736Z */
14685 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14687 /* Acer Aspire 5336 */
14688 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14690 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14691 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14693 /* Acer C720 Chromebook (Core i3 4005U) */
14694 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14696 /* Apple Macbook 2,1 (Core 2 T7400) */
14697 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14699 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14700 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14702 /* HP Chromebook 14 (Celeron 2955U) */
14703 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14705 /* Dell Chromebook 11 */
14706 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14709 static void intel_init_quirks(struct drm_device *dev)
14711 struct pci_dev *d = dev->pdev;
14714 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14715 struct intel_quirk *q = &intel_quirks[i];
14717 if (d->device == q->device &&
14718 (d->subsystem_vendor == q->subsystem_vendor ||
14719 q->subsystem_vendor == PCI_ANY_ID) &&
14720 (d->subsystem_device == q->subsystem_device ||
14721 q->subsystem_device == PCI_ANY_ID))
14724 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14725 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14726 intel_dmi_quirks[i].hook(dev);
14730 /* Disable the VGA plane that we never use */
14731 static void i915_disable_vga(struct drm_device *dev)
14733 struct drm_i915_private *dev_priv = dev->dev_private;
14735 u32 vga_reg = i915_vgacntrl_reg(dev);
14737 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14738 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14739 outb(SR01, VGA_SR_INDEX);
14740 sr1 = inb(VGA_SR_DATA);
14741 outb(sr1 | 1<<5, VGA_SR_DATA);
14742 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14745 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14746 POSTING_READ(vga_reg);
14749 void intel_modeset_init_hw(struct drm_device *dev)
14751 intel_update_cdclk(dev);
14752 intel_prepare_ddi(dev);
14753 intel_init_clock_gating(dev);
14754 intel_enable_gt_powersave(dev);
14757 void intel_modeset_init(struct drm_device *dev)
14759 struct drm_i915_private *dev_priv = dev->dev_private;
14762 struct intel_crtc *crtc;
14764 drm_mode_config_init(dev);
14766 dev->mode_config.min_width = 0;
14767 dev->mode_config.min_height = 0;
14769 dev->mode_config.preferred_depth = 24;
14770 dev->mode_config.prefer_shadow = 1;
14772 dev->mode_config.allow_fb_modifiers = true;
14774 dev->mode_config.funcs = &intel_mode_funcs;
14776 intel_init_quirks(dev);
14778 intel_init_pm(dev);
14780 if (INTEL_INFO(dev)->num_pipes == 0)
14784 * There may be no VBT; and if the BIOS enabled SSC we can
14785 * just keep using it to avoid unnecessary flicker. Whereas if the
14786 * BIOS isn't using it, don't assume it will work even if the VBT
14787 * indicates as much.
14789 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14790 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14793 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14794 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14795 bios_lvds_use_ssc ? "en" : "dis",
14796 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14797 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14801 intel_init_display(dev);
14802 intel_init_audio(dev);
14804 if (IS_GEN2(dev)) {
14805 dev->mode_config.max_width = 2048;
14806 dev->mode_config.max_height = 2048;
14807 } else if (IS_GEN3(dev)) {
14808 dev->mode_config.max_width = 4096;
14809 dev->mode_config.max_height = 4096;
14811 dev->mode_config.max_width = 8192;
14812 dev->mode_config.max_height = 8192;
14815 if (IS_845G(dev) || IS_I865G(dev)) {
14816 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14817 dev->mode_config.cursor_height = 1023;
14818 } else if (IS_GEN2(dev)) {
14819 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14820 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14822 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14823 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14826 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14828 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14829 INTEL_INFO(dev)->num_pipes,
14830 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14832 for_each_pipe(dev_priv, pipe) {
14833 intel_crtc_init(dev, pipe);
14834 for_each_sprite(dev_priv, pipe, sprite) {
14835 ret = intel_plane_init(dev, pipe, sprite);
14837 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14838 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14842 intel_shared_dpll_init(dev);
14844 /* Just disable it once at startup */
14845 i915_disable_vga(dev);
14846 intel_setup_outputs(dev);
14848 /* Just in case the BIOS is doing something questionable. */
14849 intel_fbc_disable(dev_priv);
14851 drm_modeset_lock_all(dev);
14852 intel_modeset_setup_hw_state(dev);
14853 drm_modeset_unlock_all(dev);
14855 for_each_intel_crtc(dev, crtc) {
14856 struct intel_initial_plane_config plane_config = {};
14862 * Note that reserving the BIOS fb up front prevents us
14863 * from stuffing other stolen allocations like the ring
14864 * on top. This prevents some ugliness at boot time, and
14865 * can even allow for smooth boot transitions if the BIOS
14866 * fb is large enough for the active pipe configuration.
14868 dev_priv->display.get_initial_plane_config(crtc,
14872 * If the fb is shared between multiple heads, we'll
14873 * just get the first one.
14875 intel_find_initial_plane_obj(crtc, &plane_config);
14879 static void intel_enable_pipe_a(struct drm_device *dev)
14881 struct intel_connector *connector;
14882 struct drm_connector *crt = NULL;
14883 struct intel_load_detect_pipe load_detect_temp;
14884 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14886 /* We can't just switch on the pipe A, we need to set things up with a
14887 * proper mode and output configuration. As a gross hack, enable pipe A
14888 * by enabling the load detect pipe once. */
14889 for_each_intel_connector(dev, connector) {
14890 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14891 crt = &connector->base;
14899 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14900 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14904 intel_check_plane_mapping(struct intel_crtc *crtc)
14906 struct drm_device *dev = crtc->base.dev;
14907 struct drm_i915_private *dev_priv = dev->dev_private;
14910 if (INTEL_INFO(dev)->num_pipes == 1)
14913 reg = DSPCNTR(!crtc->plane);
14914 val = I915_READ(reg);
14916 if ((val & DISPLAY_PLANE_ENABLE) &&
14917 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14923 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14925 struct drm_device *dev = crtc->base.dev;
14926 struct intel_encoder *encoder;
14928 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14934 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14936 struct drm_device *dev = crtc->base.dev;
14937 struct drm_i915_private *dev_priv = dev->dev_private;
14940 /* Clear any frame start delays used for debugging left by the BIOS */
14941 reg = PIPECONF(crtc->config->cpu_transcoder);
14942 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14944 /* restore vblank interrupts to correct state */
14945 drm_crtc_vblank_reset(&crtc->base);
14946 if (crtc->active) {
14947 struct intel_plane *plane;
14949 drm_crtc_vblank_on(&crtc->base);
14951 /* Disable everything but the primary plane */
14952 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14953 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14956 plane->disable_plane(&plane->base, &crtc->base);
14960 /* We need to sanitize the plane -> pipe mapping first because this will
14961 * disable the crtc (and hence change the state) if it is wrong. Note
14962 * that gen4+ has a fixed plane -> pipe mapping. */
14963 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14966 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14967 crtc->base.base.id);
14969 /* Pipe has the wrong plane attached and the plane is active.
14970 * Temporarily change the plane mapping and disable everything
14972 plane = crtc->plane;
14973 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14974 crtc->plane = !plane;
14975 intel_crtc_disable_noatomic(&crtc->base);
14976 crtc->plane = plane;
14979 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14980 crtc->pipe == PIPE_A && !crtc->active) {
14981 /* BIOS forgot to enable pipe A, this mostly happens after
14982 * resume. Force-enable the pipe to fix this, the update_dpms
14983 * call below we restore the pipe to the right state, but leave
14984 * the required bits on. */
14985 intel_enable_pipe_a(dev);
14988 /* Adjust the state of the output pipe according to whether we
14989 * have active connectors/encoders. */
14990 if (!intel_crtc_has_encoders(crtc))
14991 intel_crtc_disable_noatomic(&crtc->base);
14993 if (crtc->active != crtc->base.state->active) {
14994 struct intel_encoder *encoder;
14996 /* This can happen either due to bugs in the get_hw_state
14997 * functions or because of calls to intel_crtc_disable_noatomic,
14998 * or because the pipe is force-enabled due to the
15000 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15001 crtc->base.base.id,
15002 crtc->base.state->enable ? "enabled" : "disabled",
15003 crtc->active ? "enabled" : "disabled");
15005 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15006 crtc->base.state->active = crtc->active;
15007 crtc->base.enabled = crtc->active;
15009 /* Because we only establish the connector -> encoder ->
15010 * crtc links if something is active, this means the
15011 * crtc is now deactivated. Break the links. connector
15012 * -> encoder links are only establish when things are
15013 * actually up, hence no need to break them. */
15014 WARN_ON(crtc->active);
15016 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15017 encoder->base.crtc = NULL;
15020 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15022 * We start out with underrun reporting disabled to avoid races.
15023 * For correct bookkeeping mark this on active crtcs.
15025 * Also on gmch platforms we dont have any hardware bits to
15026 * disable the underrun reporting. Which means we need to start
15027 * out with underrun reporting disabled also on inactive pipes,
15028 * since otherwise we'll complain about the garbage we read when
15029 * e.g. coming up after runtime pm.
15031 * No protection against concurrent access is required - at
15032 * worst a fifo underrun happens which also sets this to false.
15034 crtc->cpu_fifo_underrun_disabled = true;
15035 crtc->pch_fifo_underrun_disabled = true;
15039 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15041 struct intel_connector *connector;
15042 struct drm_device *dev = encoder->base.dev;
15043 bool active = false;
15045 /* We need to check both for a crtc link (meaning that the
15046 * encoder is active and trying to read from a pipe) and the
15047 * pipe itself being active. */
15048 bool has_active_crtc = encoder->base.crtc &&
15049 to_intel_crtc(encoder->base.crtc)->active;
15051 for_each_intel_connector(dev, connector) {
15052 if (connector->base.encoder != &encoder->base)
15059 if (active && !has_active_crtc) {
15060 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15061 encoder->base.base.id,
15062 encoder->base.name);
15064 /* Connector is active, but has no active pipe. This is
15065 * fallout from our resume register restoring. Disable
15066 * the encoder manually again. */
15067 if (encoder->base.crtc) {
15068 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15069 encoder->base.base.id,
15070 encoder->base.name);
15071 encoder->disable(encoder);
15072 if (encoder->post_disable)
15073 encoder->post_disable(encoder);
15075 encoder->base.crtc = NULL;
15077 /* Inconsistent output/port/pipe state happens presumably due to
15078 * a bug in one of the get_hw_state functions. Or someplace else
15079 * in our code, like the register restore mess on resume. Clamp
15080 * things to off as a safer default. */
15081 for_each_intel_connector(dev, connector) {
15082 if (connector->encoder != encoder)
15084 connector->base.dpms = DRM_MODE_DPMS_OFF;
15085 connector->base.encoder = NULL;
15088 /* Enabled encoders without active connectors will be fixed in
15089 * the crtc fixup. */
15092 void i915_redisable_vga_power_on(struct drm_device *dev)
15094 struct drm_i915_private *dev_priv = dev->dev_private;
15095 u32 vga_reg = i915_vgacntrl_reg(dev);
15097 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15098 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15099 i915_disable_vga(dev);
15103 void i915_redisable_vga(struct drm_device *dev)
15105 struct drm_i915_private *dev_priv = dev->dev_private;
15107 /* This function can be called both from intel_modeset_setup_hw_state or
15108 * at a very early point in our resume sequence, where the power well
15109 * structures are not yet restored. Since this function is at a very
15110 * paranoid "someone might have enabled VGA while we were not looking"
15111 * level, just check if the power well is enabled instead of trying to
15112 * follow the "don't touch the power well if we don't need it" policy
15113 * the rest of the driver uses. */
15114 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15117 i915_redisable_vga_power_on(dev);
15120 static bool primary_get_hw_state(struct intel_plane *plane)
15122 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15124 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15127 /* FIXME read out full plane state for all planes */
15128 static void readout_plane_state(struct intel_crtc *crtc)
15130 struct drm_plane *primary = crtc->base.primary;
15131 struct intel_plane_state *plane_state =
15132 to_intel_plane_state(primary->state);
15134 plane_state->visible =
15135 primary_get_hw_state(to_intel_plane(primary));
15137 if (plane_state->visible)
15138 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15141 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15143 struct drm_i915_private *dev_priv = dev->dev_private;
15145 struct intel_crtc *crtc;
15146 struct intel_encoder *encoder;
15147 struct intel_connector *connector;
15150 for_each_intel_crtc(dev, crtc) {
15151 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15152 memset(crtc->config, 0, sizeof(*crtc->config));
15153 crtc->config->base.crtc = &crtc->base;
15155 crtc->active = dev_priv->display.get_pipe_config(crtc,
15158 crtc->base.state->active = crtc->active;
15159 crtc->base.enabled = crtc->active;
15161 readout_plane_state(crtc);
15163 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15164 crtc->base.base.id,
15165 crtc->active ? "enabled" : "disabled");
15168 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15169 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15171 pll->on = pll->get_hw_state(dev_priv, pll,
15172 &pll->config.hw_state);
15174 pll->config.crtc_mask = 0;
15175 for_each_intel_crtc(dev, crtc) {
15176 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15178 pll->config.crtc_mask |= 1 << crtc->pipe;
15182 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15183 pll->name, pll->config.crtc_mask, pll->on);
15185 if (pll->config.crtc_mask)
15186 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15189 for_each_intel_encoder(dev, encoder) {
15192 if (encoder->get_hw_state(encoder, &pipe)) {
15193 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15194 encoder->base.crtc = &crtc->base;
15195 encoder->get_config(encoder, crtc->config);
15197 encoder->base.crtc = NULL;
15200 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15201 encoder->base.base.id,
15202 encoder->base.name,
15203 encoder->base.crtc ? "enabled" : "disabled",
15207 for_each_intel_connector(dev, connector) {
15208 if (connector->get_hw_state(connector)) {
15209 connector->base.dpms = DRM_MODE_DPMS_ON;
15210 connector->base.encoder = &connector->encoder->base;
15212 connector->base.dpms = DRM_MODE_DPMS_OFF;
15213 connector->base.encoder = NULL;
15215 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15216 connector->base.base.id,
15217 connector->base.name,
15218 connector->base.encoder ? "enabled" : "disabled");
15221 for_each_intel_crtc(dev, crtc) {
15222 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15224 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15225 if (crtc->base.state->active) {
15226 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15227 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15228 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15231 * The initial mode needs to be set in order to keep
15232 * the atomic core happy. It wants a valid mode if the
15233 * crtc's enabled, so we do the above call.
15235 * At this point some state updated by the connectors
15236 * in their ->detect() callback has not run yet, so
15237 * no recalculation can be done yet.
15239 * Even if we could do a recalculation and modeset
15240 * right now it would cause a double modeset if
15241 * fbdev or userspace chooses a different initial mode.
15243 * If that happens, someone indicated they wanted a
15244 * mode change, which means it's safe to do a full
15247 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15249 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15250 update_scanline_offset(crtc);
15255 /* Scan out the current hw modeset state,
15256 * and sanitizes it to the current state
15259 intel_modeset_setup_hw_state(struct drm_device *dev)
15261 struct drm_i915_private *dev_priv = dev->dev_private;
15263 struct intel_crtc *crtc;
15264 struct intel_encoder *encoder;
15267 intel_modeset_readout_hw_state(dev);
15269 /* HW state is read out, now we need to sanitize this mess. */
15270 for_each_intel_encoder(dev, encoder) {
15271 intel_sanitize_encoder(encoder);
15274 for_each_pipe(dev_priv, pipe) {
15275 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15276 intel_sanitize_crtc(crtc);
15277 intel_dump_pipe_config(crtc, crtc->config,
15278 "[setup_hw_state]");
15281 intel_modeset_update_connector_atomic_state(dev);
15283 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15284 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15286 if (!pll->on || pll->active)
15289 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15291 pll->disable(dev_priv, pll);
15295 if (IS_VALLEYVIEW(dev))
15296 vlv_wm_get_hw_state(dev);
15297 else if (IS_GEN9(dev))
15298 skl_wm_get_hw_state(dev);
15299 else if (HAS_PCH_SPLIT(dev))
15300 ilk_wm_get_hw_state(dev);
15302 for_each_intel_crtc(dev, crtc) {
15303 unsigned long put_domains;
15305 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15306 if (WARN_ON(put_domains))
15307 modeset_put_power_domains(dev_priv, put_domains);
15309 intel_display_set_init_power(dev_priv, false);
15312 void intel_display_resume(struct drm_device *dev)
15314 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15315 struct intel_connector *conn;
15316 struct intel_plane *plane;
15317 struct drm_crtc *crtc;
15323 state->acquire_ctx = dev->mode_config.acquire_ctx;
15325 /* preserve complete old state, including dpll */
15326 intel_atomic_get_shared_dpll_state(state);
15328 for_each_crtc(dev, crtc) {
15329 struct drm_crtc_state *crtc_state =
15330 drm_atomic_get_crtc_state(state, crtc);
15332 ret = PTR_ERR_OR_ZERO(crtc_state);
15336 /* force a restore */
15337 crtc_state->mode_changed = true;
15340 for_each_intel_plane(dev, plane) {
15341 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15346 for_each_intel_connector(dev, conn) {
15347 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15352 intel_modeset_setup_hw_state(dev);
15354 i915_redisable_vga(dev);
15355 ret = drm_atomic_commit(state);
15360 DRM_ERROR("Restoring old state failed with %i\n", ret);
15361 drm_atomic_state_free(state);
15364 void intel_modeset_gem_init(struct drm_device *dev)
15366 struct drm_crtc *c;
15367 struct drm_i915_gem_object *obj;
15370 mutex_lock(&dev->struct_mutex);
15371 intel_init_gt_powersave(dev);
15372 mutex_unlock(&dev->struct_mutex);
15374 intel_modeset_init_hw(dev);
15376 intel_setup_overlay(dev);
15379 * Make sure any fbs we allocated at startup are properly
15380 * pinned & fenced. When we do the allocation it's too early
15383 for_each_crtc(dev, c) {
15384 obj = intel_fb_obj(c->primary->fb);
15388 mutex_lock(&dev->struct_mutex);
15389 ret = intel_pin_and_fence_fb_obj(c->primary,
15393 mutex_unlock(&dev->struct_mutex);
15395 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15396 to_intel_crtc(c)->pipe);
15397 drm_framebuffer_unreference(c->primary->fb);
15398 c->primary->fb = NULL;
15399 c->primary->crtc = c->primary->state->crtc = NULL;
15400 update_state_fb(c->primary);
15401 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15405 intel_backlight_register(dev);
15408 void intel_connector_unregister(struct intel_connector *intel_connector)
15410 struct drm_connector *connector = &intel_connector->base;
15412 intel_panel_destroy_backlight(connector);
15413 drm_connector_unregister(connector);
15416 void intel_modeset_cleanup(struct drm_device *dev)
15418 struct drm_i915_private *dev_priv = dev->dev_private;
15419 struct drm_connector *connector;
15421 intel_disable_gt_powersave(dev);
15423 intel_backlight_unregister(dev);
15426 * Interrupts and polling as the first thing to avoid creating havoc.
15427 * Too much stuff here (turning of connectors, ...) would
15428 * experience fancy races otherwise.
15430 intel_irq_uninstall(dev_priv);
15433 * Due to the hpd irq storm handling the hotplug work can re-arm the
15434 * poll handlers. Hence disable polling after hpd handling is shut down.
15436 drm_kms_helper_poll_fini(dev);
15438 intel_unregister_dsm_handler();
15440 intel_fbc_disable(dev_priv);
15442 /* flush any delayed tasks or pending work */
15443 flush_scheduled_work();
15445 /* destroy the backlight and sysfs files before encoders/connectors */
15446 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15447 struct intel_connector *intel_connector;
15449 intel_connector = to_intel_connector(connector);
15450 intel_connector->unregister(intel_connector);
15453 drm_mode_config_cleanup(dev);
15455 intel_cleanup_overlay(dev);
15457 mutex_lock(&dev->struct_mutex);
15458 intel_cleanup_gt_powersave(dev);
15459 mutex_unlock(&dev->struct_mutex);
15463 * Return which encoder is currently attached for connector.
15465 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15467 return &intel_attached_encoder(connector)->base;
15470 void intel_connector_attach_encoder(struct intel_connector *connector,
15471 struct intel_encoder *encoder)
15473 connector->encoder = encoder;
15474 drm_mode_connector_attach_encoder(&connector->base,
15479 * set vga decode state - true == enable VGA decode
15481 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15483 struct drm_i915_private *dev_priv = dev->dev_private;
15484 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15487 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15488 DRM_ERROR("failed to read control word\n");
15492 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15496 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15498 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15500 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15501 DRM_ERROR("failed to write control word\n");
15508 struct intel_display_error_state {
15510 u32 power_well_driver;
15512 int num_transcoders;
15514 struct intel_cursor_error_state {
15519 } cursor[I915_MAX_PIPES];
15521 struct intel_pipe_error_state {
15522 bool power_domain_on;
15525 } pipe[I915_MAX_PIPES];
15527 struct intel_plane_error_state {
15535 } plane[I915_MAX_PIPES];
15537 struct intel_transcoder_error_state {
15538 bool power_domain_on;
15539 enum transcoder cpu_transcoder;
15552 struct intel_display_error_state *
15553 intel_display_capture_error_state(struct drm_device *dev)
15555 struct drm_i915_private *dev_priv = dev->dev_private;
15556 struct intel_display_error_state *error;
15557 int transcoders[] = {
15565 if (INTEL_INFO(dev)->num_pipes == 0)
15568 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15572 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15573 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15575 for_each_pipe(dev_priv, i) {
15576 error->pipe[i].power_domain_on =
15577 __intel_display_power_is_enabled(dev_priv,
15578 POWER_DOMAIN_PIPE(i));
15579 if (!error->pipe[i].power_domain_on)
15582 error->cursor[i].control = I915_READ(CURCNTR(i));
15583 error->cursor[i].position = I915_READ(CURPOS(i));
15584 error->cursor[i].base = I915_READ(CURBASE(i));
15586 error->plane[i].control = I915_READ(DSPCNTR(i));
15587 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15588 if (INTEL_INFO(dev)->gen <= 3) {
15589 error->plane[i].size = I915_READ(DSPSIZE(i));
15590 error->plane[i].pos = I915_READ(DSPPOS(i));
15592 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15593 error->plane[i].addr = I915_READ(DSPADDR(i));
15594 if (INTEL_INFO(dev)->gen >= 4) {
15595 error->plane[i].surface = I915_READ(DSPSURF(i));
15596 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15599 error->pipe[i].source = I915_READ(PIPESRC(i));
15601 if (HAS_GMCH_DISPLAY(dev))
15602 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15605 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15606 if (HAS_DDI(dev_priv->dev))
15607 error->num_transcoders++; /* Account for eDP. */
15609 for (i = 0; i < error->num_transcoders; i++) {
15610 enum transcoder cpu_transcoder = transcoders[i];
15612 error->transcoder[i].power_domain_on =
15613 __intel_display_power_is_enabled(dev_priv,
15614 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15615 if (!error->transcoder[i].power_domain_on)
15618 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15620 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15621 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15622 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15623 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15624 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15625 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15626 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15632 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15635 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15636 struct drm_device *dev,
15637 struct intel_display_error_state *error)
15639 struct drm_i915_private *dev_priv = dev->dev_private;
15645 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15646 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15647 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15648 error->power_well_driver);
15649 for_each_pipe(dev_priv, i) {
15650 err_printf(m, "Pipe [%d]:\n", i);
15651 err_printf(m, " Power: %s\n",
15652 error->pipe[i].power_domain_on ? "on" : "off");
15653 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15654 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15656 err_printf(m, "Plane [%d]:\n", i);
15657 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15658 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15659 if (INTEL_INFO(dev)->gen <= 3) {
15660 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15661 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15663 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15664 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15665 if (INTEL_INFO(dev)->gen >= 4) {
15666 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15667 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15670 err_printf(m, "Cursor [%d]:\n", i);
15671 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15672 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15673 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15676 for (i = 0; i < error->num_transcoders; i++) {
15677 err_printf(m, "CPU transcoder: %c\n",
15678 transcoder_name(error->transcoder[i].cpu_transcoder));
15679 err_printf(m, " Power: %s\n",
15680 error->transcoder[i].power_domain_on ? "on" : "off");
15681 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15682 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15683 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15684 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15685 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15686 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15687 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15691 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15693 struct intel_crtc *crtc;
15695 for_each_intel_crtc(dev, crtc) {
15696 struct intel_unpin_work *work;
15698 spin_lock_irq(&dev->event_lock);
15700 work = crtc->unpin_work;
15702 if (work && work->event &&
15703 work->event->base.file_priv == file) {
15704 kfree(work->event);
15705 work->event = NULL;
15708 spin_unlock_irq(&dev->event_lock);