drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198                            struct drm_i915_gem_object *obj,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         u32 alignment;
2203         int ret;
2204
2205         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207         switch (obj->tiling_mode) {
2208         case I915_TILING_NONE:
2209                 if (INTEL_INFO(dev)->gen >= 9)
2210                         alignment = 256 * 1024;
2211                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212                         alignment = 128 * 1024;
2213                 else if (INTEL_INFO(dev)->gen >= 4)
2214                         alignment = 4 * 1024;
2215                 else
2216                         alignment = 64 * 1024;
2217                 break;
2218         case I915_TILING_X:
2219                 if (INTEL_INFO(dev)->gen >= 9)
2220                         alignment = 256 * 1024;
2221                 else {
2222                         /* pin() will align the object as required by fence */
2223                         alignment = 0;
2224                 }
2225                 break;
2226         case I915_TILING_Y:
2227                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228                 return -EINVAL;
2229         default:
2230                 BUG();
2231         }
2232
2233         /* Note that the w/a also requires 64 PTE of padding following the
2234          * bo. We currently fill all unused PTE with the shadow page and so
2235          * we should always have valid PTE following the scanout preventing
2236          * the VT-d warning.
2237          */
2238         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239                 alignment = 256 * 1024;
2240
2241         /*
2242          * Global gtt pte registers are special registers which actually forward
2243          * writes to a chunk of system memory. Which means that there is no risk
2244          * that the register values disappear as soon as we call
2245          * intel_runtime_pm_put(), so it is correct to wrap only the
2246          * pin/unpin/fence and not more.
2247          */
2248         intel_runtime_pm_get(dev_priv);
2249
2250         dev_priv->mm.interruptible = false;
2251         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252         if (ret)
2253                 goto err_interruptible;
2254
2255         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256          * fence, whereas 965+ only requires a fence if using
2257          * framebuffer compression.  For simplicity, we always install
2258          * a fence as the cost is not that onerous.
2259          */
2260         ret = i915_gem_object_get_fence(obj);
2261         if (ret)
2262                 goto err_unpin;
2263
2264         i915_gem_object_pin_fence(obj);
2265
2266         dev_priv->mm.interruptible = true;
2267         intel_runtime_pm_put(dev_priv);
2268         return 0;
2269
2270 err_unpin:
2271         i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273         dev_priv->mm.interruptible = true;
2274         intel_runtime_pm_put(dev_priv);
2275         return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282         i915_gem_object_unpin_fence(obj);
2283         i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287  * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289                                              unsigned int tiling_mode,
2290                                              unsigned int cpp,
2291                                              unsigned int pitch)
2292 {
2293         if (tiling_mode != I915_TILING_NONE) {
2294                 unsigned int tile_rows, tiles;
2295
2296                 tile_rows = *y / 8;
2297                 *y %= 8;
2298
2299                 tiles = *x / (512/cpp);
2300                 *x %= 512/cpp;
2301
2302                 return tile_rows * pitch * 8 + tiles * 4096;
2303         } else {
2304                 unsigned int offset;
2305
2306                 offset = *y * pitch + *x * cpp;
2307                 *y = 0;
2308                 *x = (offset & 4095) / cpp;
2309                 return offset & -4096;
2310         }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315         switch (format) {
2316         case DISPPLANE_8BPP:
2317                 return DRM_FORMAT_C8;
2318         case DISPPLANE_BGRX555:
2319                 return DRM_FORMAT_XRGB1555;
2320         case DISPPLANE_BGRX565:
2321                 return DRM_FORMAT_RGB565;
2322         default:
2323         case DISPPLANE_BGRX888:
2324                 return DRM_FORMAT_XRGB8888;
2325         case DISPPLANE_RGBX888:
2326                 return DRM_FORMAT_XBGR8888;
2327         case DISPPLANE_BGRX101010:
2328                 return DRM_FORMAT_XRGB2101010;
2329         case DISPPLANE_RGBX101010:
2330                 return DRM_FORMAT_XBGR2101010;
2331         }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335                                   struct intel_plane_config *plane_config)
2336 {
2337         struct drm_device *dev = crtc->base.dev;
2338         struct drm_i915_gem_object *obj = NULL;
2339         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340         u32 base = plane_config->base;
2341
2342         if (plane_config->size == 0)
2343                 return false;
2344
2345         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346                                                              plane_config->size);
2347         if (!obj)
2348                 return false;
2349
2350         if (plane_config->tiled) {
2351                 obj->tiling_mode = I915_TILING_X;
2352                 obj->stride = crtc->base.primary->fb->pitches[0];
2353         }
2354
2355         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356         mode_cmd.width = crtc->base.primary->fb->width;
2357         mode_cmd.height = crtc->base.primary->fb->height;
2358         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360         mutex_lock(&dev->struct_mutex);
2361
2362         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363                                    &mode_cmd, obj)) {
2364                 DRM_DEBUG_KMS("intel fb init failed\n");
2365                 goto out_unref_obj;
2366         }
2367
2368         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369         mutex_unlock(&dev->struct_mutex);
2370
2371         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372         return true;
2373
2374 out_unref_obj:
2375         drm_gem_object_unreference(&obj->base);
2376         mutex_unlock(&dev->struct_mutex);
2377         return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381                                  struct intel_plane_config *plane_config)
2382 {
2383         struct drm_device *dev = intel_crtc->base.dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct drm_crtc *c;
2386         struct intel_crtc *i;
2387         struct drm_i915_gem_object *obj;
2388
2389         if (!intel_crtc->base.primary->fb)
2390                 return;
2391
2392         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2393                 return;
2394
2395         kfree(intel_crtc->base.primary->fb);
2396         intel_crtc->base.primary->fb = NULL;
2397
2398         /*
2399          * Failed to alloc the obj, check to see if we should share
2400          * an fb with another CRTC instead
2401          */
2402         for_each_crtc(dev, c) {
2403                 i = to_intel_crtc(c);
2404
2405                 if (c == &intel_crtc->base)
2406                         continue;
2407
2408                 if (!i->active)
2409                         continue;
2410
2411                 obj = intel_fb_obj(c->primary->fb);
2412                 if (obj == NULL)
2413                         continue;
2414
2415                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2416                         if (obj->tiling_mode != I915_TILING_NONE)
2417                                 dev_priv->preserve_bios_swizzle = true;
2418
2419                         drm_framebuffer_reference(c->primary->fb);
2420                         intel_crtc->base.primary->fb = c->primary->fb;
2421                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2422                         break;
2423                 }
2424         }
2425 }
2426
2427 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2428                                       struct drm_framebuffer *fb,
2429                                       int x, int y)
2430 {
2431         struct drm_device *dev = crtc->dev;
2432         struct drm_i915_private *dev_priv = dev->dev_private;
2433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2434         struct drm_i915_gem_object *obj;
2435         int plane = intel_crtc->plane;
2436         unsigned long linear_offset;
2437         u32 dspcntr;
2438         u32 reg = DSPCNTR(plane);
2439         int pixel_size;
2440
2441         if (!intel_crtc->primary_enabled) {
2442                 I915_WRITE(reg, 0);
2443                 if (INTEL_INFO(dev)->gen >= 4)
2444                         I915_WRITE(DSPSURF(plane), 0);
2445                 else
2446                         I915_WRITE(DSPADDR(plane), 0);
2447                 POSTING_READ(reg);
2448                 return;
2449         }
2450
2451         obj = intel_fb_obj(fb);
2452         if (WARN_ON(obj == NULL))
2453                 return;
2454
2455         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2456
2457         dspcntr = DISPPLANE_GAMMA_ENABLE;
2458
2459         dspcntr |= DISPLAY_PLANE_ENABLE;
2460
2461         if (INTEL_INFO(dev)->gen < 4) {
2462                 if (intel_crtc->pipe == PIPE_B)
2463                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2464
2465                 /* pipesrc and dspsize control the size that is scaled from,
2466                  * which should always be the user's requested size.
2467                  */
2468                 I915_WRITE(DSPSIZE(plane),
2469                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2470                            (intel_crtc->config.pipe_src_w - 1));
2471                 I915_WRITE(DSPPOS(plane), 0);
2472         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2473                 I915_WRITE(PRIMSIZE(plane),
2474                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2475                            (intel_crtc->config.pipe_src_w - 1));
2476                 I915_WRITE(PRIMPOS(plane), 0);
2477                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2478         }
2479
2480         switch (fb->pixel_format) {
2481         case DRM_FORMAT_C8:
2482                 dspcntr |= DISPPLANE_8BPP;
2483                 break;
2484         case DRM_FORMAT_XRGB1555:
2485         case DRM_FORMAT_ARGB1555:
2486                 dspcntr |= DISPPLANE_BGRX555;
2487                 break;
2488         case DRM_FORMAT_RGB565:
2489                 dspcntr |= DISPPLANE_BGRX565;
2490                 break;
2491         case DRM_FORMAT_XRGB8888:
2492         case DRM_FORMAT_ARGB8888:
2493                 dspcntr |= DISPPLANE_BGRX888;
2494                 break;
2495         case DRM_FORMAT_XBGR8888:
2496         case DRM_FORMAT_ABGR8888:
2497                 dspcntr |= DISPPLANE_RGBX888;
2498                 break;
2499         case DRM_FORMAT_XRGB2101010:
2500         case DRM_FORMAT_ARGB2101010:
2501                 dspcntr |= DISPPLANE_BGRX101010;
2502                 break;
2503         case DRM_FORMAT_XBGR2101010:
2504         case DRM_FORMAT_ABGR2101010:
2505                 dspcntr |= DISPPLANE_RGBX101010;
2506                 break;
2507         default:
2508                 BUG();
2509         }
2510
2511         if (INTEL_INFO(dev)->gen >= 4 &&
2512             obj->tiling_mode != I915_TILING_NONE)
2513                 dspcntr |= DISPPLANE_TILED;
2514
2515         if (IS_G4X(dev))
2516                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2517
2518         linear_offset = y * fb->pitches[0] + x * pixel_size;
2519
2520         if (INTEL_INFO(dev)->gen >= 4) {
2521                 intel_crtc->dspaddr_offset =
2522                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2523                                                        pixel_size,
2524                                                        fb->pitches[0]);
2525                 linear_offset -= intel_crtc->dspaddr_offset;
2526         } else {
2527                 intel_crtc->dspaddr_offset = linear_offset;
2528         }
2529
2530         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2531                 dspcntr |= DISPPLANE_ROTATE_180;
2532
2533                 x += (intel_crtc->config.pipe_src_w - 1);
2534                 y += (intel_crtc->config.pipe_src_h - 1);
2535
2536                 /* Finding the last pixel of the last line of the display
2537                 data and adding to linear_offset*/
2538                 linear_offset +=
2539                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2540                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2541         }
2542
2543         I915_WRITE(reg, dspcntr);
2544
2545         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2546                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2547                       fb->pitches[0]);
2548         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2549         if (INTEL_INFO(dev)->gen >= 4) {
2550                 I915_WRITE(DSPSURF(plane),
2551                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2552                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2553                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2554         } else
2555                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2556         POSTING_READ(reg);
2557 }
2558
2559 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2560                                           struct drm_framebuffer *fb,
2561                                           int x, int y)
2562 {
2563         struct drm_device *dev = crtc->dev;
2564         struct drm_i915_private *dev_priv = dev->dev_private;
2565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2566         struct drm_i915_gem_object *obj;
2567         int plane = intel_crtc->plane;
2568         unsigned long linear_offset;
2569         u32 dspcntr;
2570         u32 reg = DSPCNTR(plane);
2571         int pixel_size;
2572
2573         if (!intel_crtc->primary_enabled) {
2574                 I915_WRITE(reg, 0);
2575                 I915_WRITE(DSPSURF(plane), 0);
2576                 POSTING_READ(reg);
2577                 return;
2578         }
2579
2580         obj = intel_fb_obj(fb);
2581         if (WARN_ON(obj == NULL))
2582                 return;
2583
2584         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2585
2586         dspcntr = DISPPLANE_GAMMA_ENABLE;
2587
2588         dspcntr |= DISPLAY_PLANE_ENABLE;
2589
2590         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2591                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2592
2593         switch (fb->pixel_format) {
2594         case DRM_FORMAT_C8:
2595                 dspcntr |= DISPPLANE_8BPP;
2596                 break;
2597         case DRM_FORMAT_RGB565:
2598                 dspcntr |= DISPPLANE_BGRX565;
2599                 break;
2600         case DRM_FORMAT_XRGB8888:
2601         case DRM_FORMAT_ARGB8888:
2602                 dspcntr |= DISPPLANE_BGRX888;
2603                 break;
2604         case DRM_FORMAT_XBGR8888:
2605         case DRM_FORMAT_ABGR8888:
2606                 dspcntr |= DISPPLANE_RGBX888;
2607                 break;
2608         case DRM_FORMAT_XRGB2101010:
2609         case DRM_FORMAT_ARGB2101010:
2610                 dspcntr |= DISPPLANE_BGRX101010;
2611                 break;
2612         case DRM_FORMAT_XBGR2101010:
2613         case DRM_FORMAT_ABGR2101010:
2614                 dspcntr |= DISPPLANE_RGBX101010;
2615                 break;
2616         default:
2617                 BUG();
2618         }
2619
2620         if (obj->tiling_mode != I915_TILING_NONE)
2621                 dspcntr |= DISPPLANE_TILED;
2622
2623         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2624                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2625
2626         linear_offset = y * fb->pitches[0] + x * pixel_size;
2627         intel_crtc->dspaddr_offset =
2628                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2629                                                pixel_size,
2630                                                fb->pitches[0]);
2631         linear_offset -= intel_crtc->dspaddr_offset;
2632         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2633                 dspcntr |= DISPPLANE_ROTATE_180;
2634
2635                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2636                         x += (intel_crtc->config.pipe_src_w - 1);
2637                         y += (intel_crtc->config.pipe_src_h - 1);
2638
2639                         /* Finding the last pixel of the last line of the display
2640                         data and adding to linear_offset*/
2641                         linear_offset +=
2642                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2643                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2644                 }
2645         }
2646
2647         I915_WRITE(reg, dspcntr);
2648
2649         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2650                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2651                       fb->pitches[0]);
2652         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2653         I915_WRITE(DSPSURF(plane),
2654                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2655         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2656                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2657         } else {
2658                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2659                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2660         }
2661         POSTING_READ(reg);
2662 }
2663
2664 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2665                                          struct drm_framebuffer *fb,
2666                                          int x, int y)
2667 {
2668         struct drm_device *dev = crtc->dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671         struct intel_framebuffer *intel_fb;
2672         struct drm_i915_gem_object *obj;
2673         int pipe = intel_crtc->pipe;
2674         u32 plane_ctl, stride;
2675
2676         if (!intel_crtc->primary_enabled) {
2677                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2678                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2679                 POSTING_READ(PLANE_CTL(pipe, 0));
2680                 return;
2681         }
2682
2683         plane_ctl = PLANE_CTL_ENABLE |
2684                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2685                     PLANE_CTL_PIPE_CSC_ENABLE;
2686
2687         switch (fb->pixel_format) {
2688         case DRM_FORMAT_RGB565:
2689                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2690                 break;
2691         case DRM_FORMAT_XRGB8888:
2692                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2693                 break;
2694         case DRM_FORMAT_XBGR8888:
2695                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2696                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2697                 break;
2698         case DRM_FORMAT_XRGB2101010:
2699                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2700                 break;
2701         case DRM_FORMAT_XBGR2101010:
2702                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2703                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2704                 break;
2705         default:
2706                 BUG();
2707         }
2708
2709         intel_fb = to_intel_framebuffer(fb);
2710         obj = intel_fb->obj;
2711
2712         /*
2713          * The stride is either expressed as a multiple of 64 bytes chunks for
2714          * linear buffers or in number of tiles for tiled buffers.
2715          */
2716         switch (obj->tiling_mode) {
2717         case I915_TILING_NONE:
2718                 stride = fb->pitches[0] >> 6;
2719                 break;
2720         case I915_TILING_X:
2721                 plane_ctl |= PLANE_CTL_TILED_X;
2722                 stride = fb->pitches[0] >> 9;
2723                 break;
2724         default:
2725                 BUG();
2726         }
2727
2728         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2729         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2730                 plane_ctl |= PLANE_CTL_ROTATE_180;
2731
2732         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2733
2734         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2735                       i915_gem_obj_ggtt_offset(obj),
2736                       x, y, fb->width, fb->height,
2737                       fb->pitches[0]);
2738
2739         I915_WRITE(PLANE_POS(pipe, 0), 0);
2740         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2741         I915_WRITE(PLANE_SIZE(pipe, 0),
2742                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2743                    (intel_crtc->config.pipe_src_w - 1));
2744         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2745         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2746
2747         POSTING_READ(PLANE_SURF(pipe, 0));
2748 }
2749
2750 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2751 static int
2752 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2753                            int x, int y, enum mode_set_atomic state)
2754 {
2755         struct drm_device *dev = crtc->dev;
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757
2758         if (dev_priv->display.disable_fbc)
2759                 dev_priv->display.disable_fbc(dev);
2760
2761         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2762
2763         return 0;
2764 }
2765
2766 void intel_display_handle_reset(struct drm_device *dev)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct drm_crtc *crtc;
2770
2771         /*
2772          * Flips in the rings have been nuked by the reset,
2773          * so complete all pending flips so that user space
2774          * will get its events and not get stuck.
2775          *
2776          * Also update the base address of all primary
2777          * planes to the the last fb to make sure we're
2778          * showing the correct fb after a reset.
2779          *
2780          * Need to make two loops over the crtcs so that we
2781          * don't try to grab a crtc mutex before the
2782          * pending_flip_queue really got woken up.
2783          */
2784
2785         for_each_crtc(dev, crtc) {
2786                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2787                 enum plane plane = intel_crtc->plane;
2788
2789                 intel_prepare_page_flip(dev, plane);
2790                 intel_finish_page_flip_plane(dev, plane);
2791         }
2792
2793         for_each_crtc(dev, crtc) {
2794                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2795
2796                 drm_modeset_lock(&crtc->mutex, NULL);
2797                 /*
2798                  * FIXME: Once we have proper support for primary planes (and
2799                  * disabling them without disabling the entire crtc) allow again
2800                  * a NULL crtc->primary->fb.
2801                  */
2802                 if (intel_crtc->active && crtc->primary->fb)
2803                         dev_priv->display.update_primary_plane(crtc,
2804                                                                crtc->primary->fb,
2805                                                                crtc->x,
2806                                                                crtc->y);
2807                 drm_modeset_unlock(&crtc->mutex);
2808         }
2809 }
2810
2811 static int
2812 intel_finish_fb(struct drm_framebuffer *old_fb)
2813 {
2814         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2815         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2816         bool was_interruptible = dev_priv->mm.interruptible;
2817         int ret;
2818
2819         /* Big Hammer, we also need to ensure that any pending
2820          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2821          * current scanout is retired before unpinning the old
2822          * framebuffer.
2823          *
2824          * This should only fail upon a hung GPU, in which case we
2825          * can safely continue.
2826          */
2827         dev_priv->mm.interruptible = false;
2828         ret = i915_gem_object_finish_gpu(obj);
2829         dev_priv->mm.interruptible = was_interruptible;
2830
2831         return ret;
2832 }
2833
2834 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2835 {
2836         struct drm_device *dev = crtc->dev;
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839         bool pending;
2840
2841         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2843                 return false;
2844
2845         spin_lock_irq(&dev->event_lock);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irq(&dev->event_lock);
2848
2849         return pending;
2850 }
2851
2852 static void intel_update_pipe_size(struct intel_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->base.dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856         const struct drm_display_mode *adjusted_mode;
2857
2858         if (!i915.fastboot)
2859                 return;
2860
2861         /*
2862          * Update pipe size and adjust fitter if needed: the reason for this is
2863          * that in compute_mode_changes we check the native mode (not the pfit
2864          * mode) to see if we can flip rather than do a full mode set. In the
2865          * fastboot case, we'll flip, but if we don't update the pipesrc and
2866          * pfit state, we'll end up with a big fb scanned out into the wrong
2867          * sized surface.
2868          *
2869          * To fix this properly, we need to hoist the checks up into
2870          * compute_mode_changes (or above), check the actual pfit state and
2871          * whether the platform allows pfit disable with pipe active, and only
2872          * then update the pipesrc and pfit state, even on the flip path.
2873          */
2874
2875         adjusted_mode = &crtc->config.adjusted_mode;
2876
2877         I915_WRITE(PIPESRC(crtc->pipe),
2878                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2879                    (adjusted_mode->crtc_vdisplay - 1));
2880         if (!crtc->config.pch_pfit.enabled &&
2881             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2882              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2883                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2884                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2885                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2886         }
2887         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2888         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2889 }
2890
2891 static int
2892 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2893                     struct drm_framebuffer *fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         enum pipe pipe = intel_crtc->pipe;
2899         struct drm_framebuffer *old_fb = crtc->primary->fb;
2900         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2901         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2902         int ret;
2903
2904         if (intel_crtc_has_pending_flip(crtc)) {
2905                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2906                 return -EBUSY;
2907         }
2908
2909         /* no fb bound */
2910         if (!fb) {
2911                 DRM_ERROR("No FB bound\n");
2912                 return 0;
2913         }
2914
2915         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2916                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2917                           plane_name(intel_crtc->plane),
2918                           INTEL_INFO(dev)->num_pipes);
2919                 return -EINVAL;
2920         }
2921
2922         mutex_lock(&dev->struct_mutex);
2923         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2924         if (ret == 0)
2925                 i915_gem_track_fb(old_obj, obj,
2926                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2927         mutex_unlock(&dev->struct_mutex);
2928         if (ret != 0) {
2929                 DRM_ERROR("pin & fence failed\n");
2930                 return ret;
2931         }
2932
2933         intel_update_pipe_size(intel_crtc);
2934
2935         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2936
2937         if (intel_crtc->active)
2938                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2939
2940         crtc->primary->fb = fb;
2941         crtc->x = x;
2942         crtc->y = y;
2943
2944         if (old_fb) {
2945                 if (intel_crtc->active && old_fb != fb)
2946                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2947                 mutex_lock(&dev->struct_mutex);
2948                 intel_unpin_fb_obj(old_obj);
2949                 mutex_unlock(&dev->struct_mutex);
2950         }
2951
2952         mutex_lock(&dev->struct_mutex);
2953         intel_update_fbc(dev);
2954         mutex_unlock(&dev->struct_mutex);
2955
2956         return 0;
2957 }
2958
2959 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2960 {
2961         struct drm_device *dev = crtc->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2964         int pipe = intel_crtc->pipe;
2965         u32 reg, temp;
2966
2967         /* enable normal train */
2968         reg = FDI_TX_CTL(pipe);
2969         temp = I915_READ(reg);
2970         if (IS_IVYBRIDGE(dev)) {
2971                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2972                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2973         } else {
2974                 temp &= ~FDI_LINK_TRAIN_NONE;
2975                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2976         }
2977         I915_WRITE(reg, temp);
2978
2979         reg = FDI_RX_CTL(pipe);
2980         temp = I915_READ(reg);
2981         if (HAS_PCH_CPT(dev)) {
2982                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2983                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2984         } else {
2985                 temp &= ~FDI_LINK_TRAIN_NONE;
2986                 temp |= FDI_LINK_TRAIN_NONE;
2987         }
2988         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2989
2990         /* wait one idle pattern time */
2991         POSTING_READ(reg);
2992         udelay(1000);
2993
2994         /* IVB wants error correction enabled */
2995         if (IS_IVYBRIDGE(dev))
2996                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2997                            FDI_FE_ERRC_ENABLE);
2998 }
2999
3000 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3001 {
3002         return crtc->base.enabled && crtc->active &&
3003                 crtc->config.has_pch_encoder;
3004 }
3005
3006 static void ivb_modeset_global_resources(struct drm_device *dev)
3007 {
3008         struct drm_i915_private *dev_priv = dev->dev_private;
3009         struct intel_crtc *pipe_B_crtc =
3010                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3011         struct intel_crtc *pipe_C_crtc =
3012                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3013         uint32_t temp;
3014
3015         /*
3016          * When everything is off disable fdi C so that we could enable fdi B
3017          * with all lanes. Note that we don't care about enabled pipes without
3018          * an enabled pch encoder.
3019          */
3020         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3021             !pipe_has_enabled_pch(pipe_C_crtc)) {
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3023                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3024
3025                 temp = I915_READ(SOUTH_CHICKEN1);
3026                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3027                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3028                 I915_WRITE(SOUTH_CHICKEN1, temp);
3029         }
3030 }
3031
3032 /* The FDI link training functions for ILK/Ibexpeak. */
3033 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3034 {
3035         struct drm_device *dev = crtc->dev;
3036         struct drm_i915_private *dev_priv = dev->dev_private;
3037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038         int pipe = intel_crtc->pipe;
3039         u32 reg, temp, tries;
3040
3041         /* FDI needs bits from pipe first */
3042         assert_pipe_enabled(dev_priv, pipe);
3043
3044         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3045            for train result */
3046         reg = FDI_RX_IMR(pipe);
3047         temp = I915_READ(reg);
3048         temp &= ~FDI_RX_SYMBOL_LOCK;
3049         temp &= ~FDI_RX_BIT_LOCK;
3050         I915_WRITE(reg, temp);
3051         I915_READ(reg);
3052         udelay(150);
3053
3054         /* enable CPU FDI TX and PCH FDI RX */
3055         reg = FDI_TX_CTL(pipe);
3056         temp = I915_READ(reg);
3057         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3058         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3059         temp &= ~FDI_LINK_TRAIN_NONE;
3060         temp |= FDI_LINK_TRAIN_PATTERN_1;
3061         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3062
3063         reg = FDI_RX_CTL(pipe);
3064         temp = I915_READ(reg);
3065         temp &= ~FDI_LINK_TRAIN_NONE;
3066         temp |= FDI_LINK_TRAIN_PATTERN_1;
3067         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3068
3069         POSTING_READ(reg);
3070         udelay(150);
3071
3072         /* Ironlake workaround, enable clock pointer after FDI enable*/
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3074         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3075                    FDI_RX_PHASE_SYNC_POINTER_EN);
3076
3077         reg = FDI_RX_IIR(pipe);
3078         for (tries = 0; tries < 5; tries++) {
3079                 temp = I915_READ(reg);
3080                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3081
3082                 if ((temp & FDI_RX_BIT_LOCK)) {
3083                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3084                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3085                         break;
3086                 }
3087         }
3088         if (tries == 5)
3089                 DRM_ERROR("FDI train 1 fail!\n");
3090
3091         /* Train 2 */
3092         reg = FDI_TX_CTL(pipe);
3093         temp = I915_READ(reg);
3094         temp &= ~FDI_LINK_TRAIN_NONE;
3095         temp |= FDI_LINK_TRAIN_PATTERN_2;
3096         I915_WRITE(reg, temp);
3097
3098         reg = FDI_RX_CTL(pipe);
3099         temp = I915_READ(reg);
3100         temp &= ~FDI_LINK_TRAIN_NONE;
3101         temp |= FDI_LINK_TRAIN_PATTERN_2;
3102         I915_WRITE(reg, temp);
3103
3104         POSTING_READ(reg);
3105         udelay(150);
3106
3107         reg = FDI_RX_IIR(pipe);
3108         for (tries = 0; tries < 5; tries++) {
3109                 temp = I915_READ(reg);
3110                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3111
3112                 if (temp & FDI_RX_SYMBOL_LOCK) {
3113                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3114                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3115                         break;
3116                 }
3117         }
3118         if (tries == 5)
3119                 DRM_ERROR("FDI train 2 fail!\n");
3120
3121         DRM_DEBUG_KMS("FDI train done\n");
3122
3123 }
3124
3125 static const int snb_b_fdi_train_param[] = {
3126         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3127         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3128         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3129         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3130 };
3131
3132 /* The FDI link training functions for SNB/Cougarpoint. */
3133 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3134 {
3135         struct drm_device *dev = crtc->dev;
3136         struct drm_i915_private *dev_priv = dev->dev_private;
3137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3138         int pipe = intel_crtc->pipe;
3139         u32 reg, temp, i, retry;
3140
3141         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3142            for train result */
3143         reg = FDI_RX_IMR(pipe);
3144         temp = I915_READ(reg);
3145         temp &= ~FDI_RX_SYMBOL_LOCK;
3146         temp &= ~FDI_RX_BIT_LOCK;
3147         I915_WRITE(reg, temp);
3148
3149         POSTING_READ(reg);
3150         udelay(150);
3151
3152         /* enable CPU FDI TX and PCH FDI RX */
3153         reg = FDI_TX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp &= ~FDI_LINK_TRAIN_NONE;
3158         temp |= FDI_LINK_TRAIN_PATTERN_1;
3159         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3160         /* SNB-B */
3161         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3162         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3163
3164         I915_WRITE(FDI_RX_MISC(pipe),
3165                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3166
3167         reg = FDI_RX_CTL(pipe);
3168         temp = I915_READ(reg);
3169         if (HAS_PCH_CPT(dev)) {
3170                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3171                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3172         } else {
3173                 temp &= ~FDI_LINK_TRAIN_NONE;
3174                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3175         }
3176         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3177
3178         POSTING_READ(reg);
3179         udelay(150);
3180
3181         for (i = 0; i < 4; i++) {
3182                 reg = FDI_TX_CTL(pipe);
3183                 temp = I915_READ(reg);
3184                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3185                 temp |= snb_b_fdi_train_param[i];
3186                 I915_WRITE(reg, temp);
3187
3188                 POSTING_READ(reg);
3189                 udelay(500);
3190
3191                 for (retry = 0; retry < 5; retry++) {
3192                         reg = FDI_RX_IIR(pipe);
3193                         temp = I915_READ(reg);
3194                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3195                         if (temp & FDI_RX_BIT_LOCK) {
3196                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3198                                 break;
3199                         }
3200                         udelay(50);
3201                 }
3202                 if (retry < 5)
3203                         break;
3204         }
3205         if (i == 4)
3206                 DRM_ERROR("FDI train 1 fail!\n");
3207
3208         /* Train 2 */
3209         reg = FDI_TX_CTL(pipe);
3210         temp = I915_READ(reg);
3211         temp &= ~FDI_LINK_TRAIN_NONE;
3212         temp |= FDI_LINK_TRAIN_PATTERN_2;
3213         if (IS_GEN6(dev)) {
3214                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3215                 /* SNB-B */
3216                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3217         }
3218         I915_WRITE(reg, temp);
3219
3220         reg = FDI_RX_CTL(pipe);
3221         temp = I915_READ(reg);
3222         if (HAS_PCH_CPT(dev)) {
3223                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3224                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3225         } else {
3226                 temp &= ~FDI_LINK_TRAIN_NONE;
3227                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3228         }
3229         I915_WRITE(reg, temp);
3230
3231         POSTING_READ(reg);
3232         udelay(150);
3233
3234         for (i = 0; i < 4; i++) {
3235                 reg = FDI_TX_CTL(pipe);
3236                 temp = I915_READ(reg);
3237                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3238                 temp |= snb_b_fdi_train_param[i];
3239                 I915_WRITE(reg, temp);
3240
3241                 POSTING_READ(reg);
3242                 udelay(500);
3243
3244                 for (retry = 0; retry < 5; retry++) {
3245                         reg = FDI_RX_IIR(pipe);
3246                         temp = I915_READ(reg);
3247                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248                         if (temp & FDI_RX_SYMBOL_LOCK) {
3249                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3250                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3251                                 break;
3252                         }
3253                         udelay(50);
3254                 }
3255                 if (retry < 5)
3256                         break;
3257         }
3258         if (i == 4)
3259                 DRM_ERROR("FDI train 2 fail!\n");
3260
3261         DRM_DEBUG_KMS("FDI train done.\n");
3262 }
3263
3264 /* Manual link training for Ivy Bridge A0 parts */
3265 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3266 {
3267         struct drm_device *dev = crtc->dev;
3268         struct drm_i915_private *dev_priv = dev->dev_private;
3269         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270         int pipe = intel_crtc->pipe;
3271         u32 reg, temp, i, j;
3272
3273         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3274            for train result */
3275         reg = FDI_RX_IMR(pipe);
3276         temp = I915_READ(reg);
3277         temp &= ~FDI_RX_SYMBOL_LOCK;
3278         temp &= ~FDI_RX_BIT_LOCK;
3279         I915_WRITE(reg, temp);
3280
3281         POSTING_READ(reg);
3282         udelay(150);
3283
3284         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3285                       I915_READ(FDI_RX_IIR(pipe)));
3286
3287         /* Try each vswing and preemphasis setting twice before moving on */
3288         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3289                 /* disable first in case we need to retry */
3290                 reg = FDI_TX_CTL(pipe);
3291                 temp = I915_READ(reg);
3292                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3293                 temp &= ~FDI_TX_ENABLE;
3294                 I915_WRITE(reg, temp);
3295
3296                 reg = FDI_RX_CTL(pipe);
3297                 temp = I915_READ(reg);
3298                 temp &= ~FDI_LINK_TRAIN_AUTO;
3299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300                 temp &= ~FDI_RX_ENABLE;
3301                 I915_WRITE(reg, temp);
3302
3303                 /* enable CPU FDI TX and PCH FDI RX */
3304                 reg = FDI_TX_CTL(pipe);
3305                 temp = I915_READ(reg);
3306                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3308                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3309                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3310                 temp |= snb_b_fdi_train_param[j/2];
3311                 temp |= FDI_COMPOSITE_SYNC;
3312                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3313
3314                 I915_WRITE(FDI_RX_MISC(pipe),
3315                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3316
3317                 reg = FDI_RX_CTL(pipe);
3318                 temp = I915_READ(reg);
3319                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3320                 temp |= FDI_COMPOSITE_SYNC;
3321                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3322
3323                 POSTING_READ(reg);
3324                 udelay(1); /* should be 0.5us */
3325
3326                 for (i = 0; i < 4; i++) {
3327                         reg = FDI_RX_IIR(pipe);
3328                         temp = I915_READ(reg);
3329                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3330
3331                         if (temp & FDI_RX_BIT_LOCK ||
3332                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3333                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3335                                               i);
3336                                 break;
3337                         }
3338                         udelay(1); /* should be 0.5us */
3339                 }
3340                 if (i == 4) {
3341                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3342                         continue;
3343                 }
3344
3345                 /* Train 2 */
3346                 reg = FDI_TX_CTL(pipe);
3347                 temp = I915_READ(reg);
3348                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3350                 I915_WRITE(reg, temp);
3351
3352                 reg = FDI_RX_CTL(pipe);
3353                 temp = I915_READ(reg);
3354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3355                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3356                 I915_WRITE(reg, temp);
3357
3358                 POSTING_READ(reg);
3359                 udelay(2); /* should be 1.5us */
3360
3361                 for (i = 0; i < 4; i++) {
3362                         reg = FDI_RX_IIR(pipe);
3363                         temp = I915_READ(reg);
3364                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3365
3366                         if (temp & FDI_RX_SYMBOL_LOCK ||
3367                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3368                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3369                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3370                                               i);
3371                                 goto train_done;
3372                         }
3373                         udelay(2); /* should be 1.5us */
3374                 }
3375                 if (i == 4)
3376                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3377         }
3378
3379 train_done:
3380         DRM_DEBUG_KMS("FDI train done.\n");
3381 }
3382
3383 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3384 {
3385         struct drm_device *dev = intel_crtc->base.dev;
3386         struct drm_i915_private *dev_priv = dev->dev_private;
3387         int pipe = intel_crtc->pipe;
3388         u32 reg, temp;
3389
3390
3391         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3392         reg = FDI_RX_CTL(pipe);
3393         temp = I915_READ(reg);
3394         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3395         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3396         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3397         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3398
3399         POSTING_READ(reg);
3400         udelay(200);
3401
3402         /* Switch from Rawclk to PCDclk */
3403         temp = I915_READ(reg);
3404         I915_WRITE(reg, temp | FDI_PCDCLK);
3405
3406         POSTING_READ(reg);
3407         udelay(200);
3408
3409         /* Enable CPU FDI TX PLL, always on for Ironlake */
3410         reg = FDI_TX_CTL(pipe);
3411         temp = I915_READ(reg);
3412         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3413                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3414
3415                 POSTING_READ(reg);
3416                 udelay(100);
3417         }
3418 }
3419
3420 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3421 {
3422         struct drm_device *dev = intel_crtc->base.dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         int pipe = intel_crtc->pipe;
3425         u32 reg, temp;
3426
3427         /* Switch from PCDclk to Rawclk */
3428         reg = FDI_RX_CTL(pipe);
3429         temp = I915_READ(reg);
3430         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3431
3432         /* Disable CPU FDI TX PLL */
3433         reg = FDI_TX_CTL(pipe);
3434         temp = I915_READ(reg);
3435         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3436
3437         POSTING_READ(reg);
3438         udelay(100);
3439
3440         reg = FDI_RX_CTL(pipe);
3441         temp = I915_READ(reg);
3442         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3443
3444         /* Wait for the clocks to turn off. */
3445         POSTING_READ(reg);
3446         udelay(100);
3447 }
3448
3449 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         int pipe = intel_crtc->pipe;
3455         u32 reg, temp;
3456
3457         /* disable CPU FDI tx and PCH FDI rx */
3458         reg = FDI_TX_CTL(pipe);
3459         temp = I915_READ(reg);
3460         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3461         POSTING_READ(reg);
3462
3463         reg = FDI_RX_CTL(pipe);
3464         temp = I915_READ(reg);
3465         temp &= ~(0x7 << 16);
3466         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3467         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3468
3469         POSTING_READ(reg);
3470         udelay(100);
3471
3472         /* Ironlake workaround, disable clock pointer after downing FDI */
3473         if (HAS_PCH_IBX(dev))
3474                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3475
3476         /* still set train pattern 1 */
3477         reg = FDI_TX_CTL(pipe);
3478         temp = I915_READ(reg);
3479         temp &= ~FDI_LINK_TRAIN_NONE;
3480         temp |= FDI_LINK_TRAIN_PATTERN_1;
3481         I915_WRITE(reg, temp);
3482
3483         reg = FDI_RX_CTL(pipe);
3484         temp = I915_READ(reg);
3485         if (HAS_PCH_CPT(dev)) {
3486                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488         } else {
3489                 temp &= ~FDI_LINK_TRAIN_NONE;
3490                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491         }
3492         /* BPC in FDI rx is consistent with that in PIPECONF */
3493         temp &= ~(0x07 << 16);
3494         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3495         I915_WRITE(reg, temp);
3496
3497         POSTING_READ(reg);
3498         udelay(100);
3499 }
3500
3501 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3502 {
3503         struct intel_crtc *crtc;
3504
3505         /* Note that we don't need to be called with mode_config.lock here
3506          * as our list of CRTC objects is static for the lifetime of the
3507          * device and so cannot disappear as we iterate. Similarly, we can
3508          * happily treat the predicates as racy, atomic checks as userspace
3509          * cannot claim and pin a new fb without at least acquring the
3510          * struct_mutex and so serialising with us.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (atomic_read(&crtc->unpin_work_count) == 0)
3514                         continue;
3515
3516                 if (crtc->unpin_work)
3517                         intel_wait_for_vblank(dev, crtc->pipe);
3518
3519                 return true;
3520         }
3521
3522         return false;
3523 }
3524
3525 static void page_flip_completed(struct intel_crtc *intel_crtc)
3526 {
3527         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3528         struct intel_unpin_work *work = intel_crtc->unpin_work;
3529
3530         /* ensure that the unpin work is consistent wrt ->pending. */
3531         smp_rmb();
3532         intel_crtc->unpin_work = NULL;
3533
3534         if (work->event)
3535                 drm_send_vblank_event(intel_crtc->base.dev,
3536                                       intel_crtc->pipe,
3537                                       work->event);
3538
3539         drm_crtc_vblank_put(&intel_crtc->base);
3540
3541         wake_up_all(&dev_priv->pending_flip_queue);
3542         queue_work(dev_priv->wq, &work->work);
3543
3544         trace_i915_flip_complete(intel_crtc->plane,
3545                                  work->pending_flip_obj);
3546 }
3547
3548 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3549 {
3550         struct drm_device *dev = crtc->dev;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3554         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3555                                        !intel_crtc_has_pending_flip(crtc),
3556                                        60*HZ) == 0)) {
3557                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558
3559                 spin_lock_irq(&dev->event_lock);
3560                 if (intel_crtc->unpin_work) {
3561                         WARN_ONCE(1, "Removing stuck page flip\n");
3562                         page_flip_completed(intel_crtc);
3563                 }
3564                 spin_unlock_irq(&dev->event_lock);
3565         }
3566
3567         if (crtc->primary->fb) {
3568                 mutex_lock(&dev->struct_mutex);
3569                 intel_finish_fb(crtc->primary->fb);
3570                 mutex_unlock(&dev->struct_mutex);
3571         }
3572 }
3573
3574 /* Program iCLKIP clock to the desired frequency */
3575 static void lpt_program_iclkip(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3580         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3581         u32 temp;
3582
3583         mutex_lock(&dev_priv->dpio_lock);
3584
3585         /* It is necessary to ungate the pixclk gate prior to programming
3586          * the divisors, and gate it back when it is done.
3587          */
3588         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3589
3590         /* Disable SSCCTL */
3591         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3592                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3593                                 SBI_SSCCTL_DISABLE,
3594                         SBI_ICLK);
3595
3596         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3597         if (clock == 20000) {
3598                 auxdiv = 1;
3599                 divsel = 0x41;
3600                 phaseinc = 0x20;
3601         } else {
3602                 /* The iCLK virtual clock root frequency is in MHz,
3603                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3604                  * divisors, it is necessary to divide one by another, so we
3605                  * convert the virtual clock precision to KHz here for higher
3606                  * precision.
3607                  */
3608                 u32 iclk_virtual_root_freq = 172800 * 1000;
3609                 u32 iclk_pi_range = 64;
3610                 u32 desired_divisor, msb_divisor_value, pi_value;
3611
3612                 desired_divisor = (iclk_virtual_root_freq / clock);
3613                 msb_divisor_value = desired_divisor / iclk_pi_range;
3614                 pi_value = desired_divisor % iclk_pi_range;
3615
3616                 auxdiv = 0;
3617                 divsel = msb_divisor_value - 2;
3618                 phaseinc = pi_value;
3619         }
3620
3621         /* This should not happen with any sane values */
3622         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3623                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3624         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3625                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3626
3627         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3628                         clock,
3629                         auxdiv,
3630                         divsel,
3631                         phasedir,
3632                         phaseinc);
3633
3634         /* Program SSCDIVINTPHASE6 */
3635         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3636         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3637         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3638         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3639         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3640         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3641         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3642         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3643
3644         /* Program SSCAUXDIV */
3645         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3646         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3647         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3648         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3649
3650         /* Enable modulator and associated divider */
3651         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3652         temp &= ~SBI_SSCCTL_DISABLE;
3653         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3654
3655         /* Wait for initialization time */
3656         udelay(24);
3657
3658         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3659
3660         mutex_unlock(&dev_priv->dpio_lock);
3661 }
3662
3663 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3664                                                 enum pipe pch_transcoder)
3665 {
3666         struct drm_device *dev = crtc->base.dev;
3667         struct drm_i915_private *dev_priv = dev->dev_private;
3668         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3669
3670         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3671                    I915_READ(HTOTAL(cpu_transcoder)));
3672         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3673                    I915_READ(HBLANK(cpu_transcoder)));
3674         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3675                    I915_READ(HSYNC(cpu_transcoder)));
3676
3677         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3678                    I915_READ(VTOTAL(cpu_transcoder)));
3679         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3680                    I915_READ(VBLANK(cpu_transcoder)));
3681         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3682                    I915_READ(VSYNC(cpu_transcoder)));
3683         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3684                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3685 }
3686
3687 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3688 {
3689         struct drm_i915_private *dev_priv = dev->dev_private;
3690         uint32_t temp;
3691
3692         temp = I915_READ(SOUTH_CHICKEN1);
3693         if (temp & FDI_BC_BIFURCATION_SELECT)
3694                 return;
3695
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3697         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3698
3699         temp |= FDI_BC_BIFURCATION_SELECT;
3700         DRM_DEBUG_KMS("enabling fdi C rx\n");
3701         I915_WRITE(SOUTH_CHICKEN1, temp);
3702         POSTING_READ(SOUTH_CHICKEN1);
3703 }
3704
3705 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3706 {
3707         struct drm_device *dev = intel_crtc->base.dev;
3708         struct drm_i915_private *dev_priv = dev->dev_private;
3709
3710         switch (intel_crtc->pipe) {
3711         case PIPE_A:
3712                 break;
3713         case PIPE_B:
3714                 if (intel_crtc->config.fdi_lanes > 2)
3715                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3716                 else
3717                         cpt_enable_fdi_bc_bifurcation(dev);
3718
3719                 break;
3720         case PIPE_C:
3721                 cpt_enable_fdi_bc_bifurcation(dev);
3722
3723                 break;
3724         default:
3725                 BUG();
3726         }
3727 }
3728
3729 /*
3730  * Enable PCH resources required for PCH ports:
3731  *   - PCH PLLs
3732  *   - FDI training & RX/TX
3733  *   - update transcoder timings
3734  *   - DP transcoding bits
3735  *   - transcoder
3736  */
3737 static void ironlake_pch_enable(struct drm_crtc *crtc)
3738 {
3739         struct drm_device *dev = crtc->dev;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3742         int pipe = intel_crtc->pipe;
3743         u32 reg, temp;
3744
3745         assert_pch_transcoder_disabled(dev_priv, pipe);
3746
3747         if (IS_IVYBRIDGE(dev))
3748                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3749
3750         /* Write the TU size bits before fdi link training, so that error
3751          * detection works. */
3752         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3753                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3754
3755         /* For PCH output, training FDI link */
3756         dev_priv->display.fdi_link_train(crtc);
3757
3758         /* We need to program the right clock selection before writing the pixel
3759          * mutliplier into the DPLL. */
3760         if (HAS_PCH_CPT(dev)) {
3761                 u32 sel;
3762
3763                 temp = I915_READ(PCH_DPLL_SEL);
3764                 temp |= TRANS_DPLL_ENABLE(pipe);
3765                 sel = TRANS_DPLLB_SEL(pipe);
3766                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3767                         temp |= sel;
3768                 else
3769                         temp &= ~sel;
3770                 I915_WRITE(PCH_DPLL_SEL, temp);
3771         }
3772
3773         /* XXX: pch pll's can be enabled any time before we enable the PCH
3774          * transcoder, and we actually should do this to not upset any PCH
3775          * transcoder that already use the clock when we share it.
3776          *
3777          * Note that enable_shared_dpll tries to do the right thing, but
3778          * get_shared_dpll unconditionally resets the pll - we need that to have
3779          * the right LVDS enable sequence. */
3780         intel_enable_shared_dpll(intel_crtc);
3781
3782         /* set transcoder timing, panel must allow it */
3783         assert_panel_unlocked(dev_priv, pipe);
3784         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3785
3786         intel_fdi_normal_train(crtc);
3787
3788         /* For PCH DP, enable TRANS_DP_CTL */
3789         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3790                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3791                 reg = TRANS_DP_CTL(pipe);
3792                 temp = I915_READ(reg);
3793                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3794                           TRANS_DP_SYNC_MASK |
3795                           TRANS_DP_BPC_MASK);
3796                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3797                          TRANS_DP_ENH_FRAMING);
3798                 temp |= bpc << 9; /* same format but at 11:9 */
3799
3800                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3801                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3802                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3803                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3804
3805                 switch (intel_trans_dp_port_sel(crtc)) {
3806                 case PCH_DP_B:
3807                         temp |= TRANS_DP_PORT_SEL_B;
3808                         break;
3809                 case PCH_DP_C:
3810                         temp |= TRANS_DP_PORT_SEL_C;
3811                         break;
3812                 case PCH_DP_D:
3813                         temp |= TRANS_DP_PORT_SEL_D;
3814                         break;
3815                 default:
3816                         BUG();
3817                 }
3818
3819                 I915_WRITE(reg, temp);
3820         }
3821
3822         ironlake_enable_pch_transcoder(dev_priv, pipe);
3823 }
3824
3825 static void lpt_pch_enable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_i915_private *dev_priv = dev->dev_private;
3829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3831
3832         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3833
3834         lpt_program_iclkip(crtc);
3835
3836         /* Set transcoder timing. */
3837         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3838
3839         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3840 }
3841
3842 void intel_put_shared_dpll(struct intel_crtc *crtc)
3843 {
3844         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3845
3846         if (pll == NULL)
3847                 return;
3848
3849         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3850                 WARN(1, "bad %s crtc mask\n", pll->name);
3851                 return;
3852         }
3853
3854         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3855         if (pll->config.crtc_mask == 0) {
3856                 WARN_ON(pll->on);
3857                 WARN_ON(pll->active);
3858         }
3859
3860         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3861 }
3862
3863 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3864 {
3865         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3866         struct intel_shared_dpll *pll;
3867         enum intel_dpll_id i;
3868
3869         if (HAS_PCH_IBX(dev_priv->dev)) {
3870                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3871                 i = (enum intel_dpll_id) crtc->pipe;
3872                 pll = &dev_priv->shared_dplls[i];
3873
3874                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3875                               crtc->base.base.id, pll->name);
3876
3877                 WARN_ON(pll->new_config->crtc_mask);
3878
3879                 goto found;
3880         }
3881
3882         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3883                 pll = &dev_priv->shared_dplls[i];
3884
3885                 /* Only want to check enabled timings first */
3886                 if (pll->new_config->crtc_mask == 0)
3887                         continue;
3888
3889                 if (memcmp(&crtc->new_config->dpll_hw_state,
3890                            &pll->new_config->hw_state,
3891                            sizeof(pll->new_config->hw_state)) == 0) {
3892                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3893                                       crtc->base.base.id, pll->name,
3894                                       pll->new_config->crtc_mask,
3895                                       pll->active);
3896                         goto found;
3897                 }
3898         }
3899
3900         /* Ok no matching timings, maybe there's a free one? */
3901         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3902                 pll = &dev_priv->shared_dplls[i];
3903                 if (pll->new_config->crtc_mask == 0) {
3904                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3905                                       crtc->base.base.id, pll->name);
3906                         goto found;
3907                 }
3908         }
3909
3910         return NULL;
3911
3912 found:
3913         if (pll->new_config->crtc_mask == 0)
3914                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3915
3916         crtc->new_config->shared_dpll = i;
3917         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3918                          pipe_name(crtc->pipe));
3919
3920         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3921
3922         return pll;
3923 }
3924
3925 /**
3926  * intel_shared_dpll_start_config - start a new PLL staged config
3927  * @dev_priv: DRM device
3928  * @clear_pipes: mask of pipes that will have their PLLs freed
3929  *
3930  * Starts a new PLL staged config, copying the current config but
3931  * releasing the references of pipes specified in clear_pipes.
3932  */
3933 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3934                                           unsigned clear_pipes)
3935 {
3936         struct intel_shared_dpll *pll;
3937         enum intel_dpll_id i;
3938
3939         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3940                 pll = &dev_priv->shared_dplls[i];
3941
3942                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3943                                           GFP_KERNEL);
3944                 if (!pll->new_config)
3945                         goto cleanup;
3946
3947                 pll->new_config->crtc_mask &= ~clear_pipes;
3948         }
3949
3950         return 0;
3951
3952 cleanup:
3953         while (--i >= 0) {
3954                 pll = &dev_priv->shared_dplls[i];
3955                 pll->new_config = NULL;
3956         }
3957
3958         return -ENOMEM;
3959 }
3960
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962 {
3963         struct intel_shared_dpll *pll;
3964         enum intel_dpll_id i;
3965
3966         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967                 pll = &dev_priv->shared_dplls[i];
3968
3969                 WARN_ON(pll->new_config == &pll->config);
3970
3971                 pll->config = *pll->new_config;
3972                 kfree(pll->new_config);
3973                 pll->new_config = NULL;
3974         }
3975 }
3976
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978 {
3979         struct intel_shared_dpll *pll;
3980         enum intel_dpll_id i;
3981
3982         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983                 pll = &dev_priv->shared_dplls[i];
3984
3985                 WARN_ON(pll->new_config == &pll->config);
3986
3987                 kfree(pll->new_config);
3988                 pll->new_config = NULL;
3989         }
3990 }
3991
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3993 {
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         int dslreg = PIPEDSL(pipe);
3996         u32 temp;
3997
3998         temp = I915_READ(dslreg);
3999         udelay(500);
4000         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001                 if (wait_for(I915_READ(dslreg) != temp, 5))
4002                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4003         }
4004 }
4005
4006 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4007 {
4008         struct drm_device *dev = crtc->base.dev;
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         int pipe = crtc->pipe;
4011
4012         if (crtc->config.pch_pfit.enabled) {
4013                 /* Force use of hard-coded filter coefficients
4014                  * as some pre-programmed values are broken,
4015                  * e.g. x201.
4016                  */
4017                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4018                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4019                                                  PF_PIPE_SEL_IVB(pipe));
4020                 else
4021                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4022                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4023                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4024         }
4025 }
4026
4027 static void intel_enable_planes(struct drm_crtc *crtc)
4028 {
4029         struct drm_device *dev = crtc->dev;
4030         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4031         struct drm_plane *plane;
4032         struct intel_plane *intel_plane;
4033
4034         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4035                 intel_plane = to_intel_plane(plane);
4036                 if (intel_plane->pipe == pipe)
4037                         intel_plane_restore(&intel_plane->base);
4038         }
4039 }
4040
4041 static void intel_disable_planes(struct drm_crtc *crtc)
4042 {
4043         struct drm_device *dev = crtc->dev;
4044         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4045         struct drm_plane *plane;
4046         struct intel_plane *intel_plane;
4047
4048         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4049                 intel_plane = to_intel_plane(plane);
4050                 if (intel_plane->pipe == pipe)
4051                         intel_plane_disable(&intel_plane->base);
4052         }
4053 }
4054
4055 void hsw_enable_ips(struct intel_crtc *crtc)
4056 {
4057         struct drm_device *dev = crtc->base.dev;
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059
4060         if (!crtc->config.ips_enabled)
4061                 return;
4062
4063         /* We can only enable IPS after we enable a plane and wait for a vblank */
4064         intel_wait_for_vblank(dev, crtc->pipe);
4065
4066         assert_plane_enabled(dev_priv, crtc->plane);
4067         if (IS_BROADWELL(dev)) {
4068                 mutex_lock(&dev_priv->rps.hw_lock);
4069                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4070                 mutex_unlock(&dev_priv->rps.hw_lock);
4071                 /* Quoting Art Runyan: "its not safe to expect any particular
4072                  * value in IPS_CTL bit 31 after enabling IPS through the
4073                  * mailbox." Moreover, the mailbox may return a bogus state,
4074                  * so we need to just enable it and continue on.
4075                  */
4076         } else {
4077                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4078                 /* The bit only becomes 1 in the next vblank, so this wait here
4079                  * is essentially intel_wait_for_vblank. If we don't have this
4080                  * and don't wait for vblanks until the end of crtc_enable, then
4081                  * the HW state readout code will complain that the expected
4082                  * IPS_CTL value is not the one we read. */
4083                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4084                         DRM_ERROR("Timed out waiting for IPS enable\n");
4085         }
4086 }
4087
4088 void hsw_disable_ips(struct intel_crtc *crtc)
4089 {
4090         struct drm_device *dev = crtc->base.dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092
4093         if (!crtc->config.ips_enabled)
4094                 return;
4095
4096         assert_plane_enabled(dev_priv, crtc->plane);
4097         if (IS_BROADWELL(dev)) {
4098                 mutex_lock(&dev_priv->rps.hw_lock);
4099                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4100                 mutex_unlock(&dev_priv->rps.hw_lock);
4101                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4102                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4103                         DRM_ERROR("Timed out waiting for IPS disable\n");
4104         } else {
4105                 I915_WRITE(IPS_CTL, 0);
4106                 POSTING_READ(IPS_CTL);
4107         }
4108
4109         /* We need to wait for a vblank before we can disable the plane. */
4110         intel_wait_for_vblank(dev, crtc->pipe);
4111 }
4112
4113 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4114 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         enum pipe pipe = intel_crtc->pipe;
4120         int palreg = PALETTE(pipe);
4121         int i;
4122         bool reenable_ips = false;
4123
4124         /* The clocks have to be on to load the palette. */
4125         if (!crtc->enabled || !intel_crtc->active)
4126                 return;
4127
4128         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4129                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4130                         assert_dsi_pll_enabled(dev_priv);
4131                 else
4132                         assert_pll_enabled(dev_priv, pipe);
4133         }
4134
4135         /* use legacy palette for Ironlake */
4136         if (!HAS_GMCH_DISPLAY(dev))
4137                 palreg = LGC_PALETTE(pipe);
4138
4139         /* Workaround : Do not read or write the pipe palette/gamma data while
4140          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4141          */
4142         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4143             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4144              GAMMA_MODE_MODE_SPLIT)) {
4145                 hsw_disable_ips(intel_crtc);
4146                 reenable_ips = true;
4147         }
4148
4149         for (i = 0; i < 256; i++) {
4150                 I915_WRITE(palreg + 4 * i,
4151                            (intel_crtc->lut_r[i] << 16) |
4152                            (intel_crtc->lut_g[i] << 8) |
4153                            intel_crtc->lut_b[i]);
4154         }
4155
4156         if (reenable_ips)
4157                 hsw_enable_ips(intel_crtc);
4158 }
4159
4160 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4161 {
4162         if (!enable && intel_crtc->overlay) {
4163                 struct drm_device *dev = intel_crtc->base.dev;
4164                 struct drm_i915_private *dev_priv = dev->dev_private;
4165
4166                 mutex_lock(&dev->struct_mutex);
4167                 dev_priv->mm.interruptible = false;
4168                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4169                 dev_priv->mm.interruptible = true;
4170                 mutex_unlock(&dev->struct_mutex);
4171         }
4172
4173         /* Let userspace switch the overlay on again. In most cases userspace
4174          * has to recompute where to put it anyway.
4175          */
4176 }
4177
4178 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182         int pipe = intel_crtc->pipe;
4183
4184         intel_enable_primary_hw_plane(crtc->primary, crtc);
4185         intel_enable_planes(crtc);
4186         intel_crtc_update_cursor(crtc, true);
4187         intel_crtc_dpms_overlay(intel_crtc, true);
4188
4189         hsw_enable_ips(intel_crtc);
4190
4191         mutex_lock(&dev->struct_mutex);
4192         intel_update_fbc(dev);
4193         mutex_unlock(&dev->struct_mutex);
4194
4195         /*
4196          * FIXME: Once we grow proper nuclear flip support out of this we need
4197          * to compute the mask of flip planes precisely. For the time being
4198          * consider this a flip from a NULL plane.
4199          */
4200         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4201 }
4202
4203 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208         int pipe = intel_crtc->pipe;
4209         int plane = intel_crtc->plane;
4210
4211         intel_crtc_wait_for_pending_flips(crtc);
4212
4213         if (dev_priv->fbc.plane == plane)
4214                 intel_disable_fbc(dev);
4215
4216         hsw_disable_ips(intel_crtc);
4217
4218         intel_crtc_dpms_overlay(intel_crtc, false);
4219         intel_crtc_update_cursor(crtc, false);
4220         intel_disable_planes(crtc);
4221         intel_disable_primary_hw_plane(crtc->primary, crtc);
4222
4223         /*
4224          * FIXME: Once we grow proper nuclear flip support out of this we need
4225          * to compute the mask of flip planes precisely. For the time being
4226          * consider this a flip to a NULL plane.
4227          */
4228         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4229 }
4230
4231 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236         struct intel_encoder *encoder;
4237         int pipe = intel_crtc->pipe;
4238
4239         WARN_ON(!crtc->enabled);
4240
4241         if (intel_crtc->active)
4242                 return;
4243
4244         if (intel_crtc->config.has_pch_encoder)
4245                 intel_prepare_shared_dpll(intel_crtc);
4246
4247         if (intel_crtc->config.has_dp_encoder)
4248                 intel_dp_set_m_n(intel_crtc);
4249
4250         intel_set_pipe_timings(intel_crtc);
4251
4252         if (intel_crtc->config.has_pch_encoder) {
4253                 intel_cpu_transcoder_set_m_n(intel_crtc,
4254                                      &intel_crtc->config.fdi_m_n, NULL);
4255         }
4256
4257         ironlake_set_pipeconf(crtc);
4258
4259         intel_crtc->active = true;
4260
4261         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4262         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4263
4264         for_each_encoder_on_crtc(dev, crtc, encoder)
4265                 if (encoder->pre_enable)
4266                         encoder->pre_enable(encoder);
4267
4268         if (intel_crtc->config.has_pch_encoder) {
4269                 /* Note: FDI PLL enabling _must_ be done before we enable the
4270                  * cpu pipes, hence this is separate from all the other fdi/pch
4271                  * enabling. */
4272                 ironlake_fdi_pll_enable(intel_crtc);
4273         } else {
4274                 assert_fdi_tx_disabled(dev_priv, pipe);
4275                 assert_fdi_rx_disabled(dev_priv, pipe);
4276         }
4277
4278         ironlake_pfit_enable(intel_crtc);
4279
4280         /*
4281          * On ILK+ LUT must be loaded before the pipe is running but with
4282          * clocks enabled
4283          */
4284         intel_crtc_load_lut(crtc);
4285
4286         intel_update_watermarks(crtc);
4287         intel_enable_pipe(intel_crtc);
4288
4289         if (intel_crtc->config.has_pch_encoder)
4290                 ironlake_pch_enable(crtc);
4291
4292         for_each_encoder_on_crtc(dev, crtc, encoder)
4293                 encoder->enable(encoder);
4294
4295         if (HAS_PCH_CPT(dev))
4296                 cpt_verify_modeset(dev, intel_crtc->pipe);
4297
4298         assert_vblank_disabled(crtc);
4299         drm_crtc_vblank_on(crtc);
4300
4301         intel_crtc_enable_planes(crtc);
4302 }
4303
4304 /* IPS only exists on ULT machines and is tied to pipe A. */
4305 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4306 {
4307         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4308 }
4309
4310 /*
4311  * This implements the workaround described in the "notes" section of the mode
4312  * set sequence documentation. When going from no pipes or single pipe to
4313  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4314  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4315  */
4316 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4317 {
4318         struct drm_device *dev = crtc->base.dev;
4319         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4320
4321         /* We want to get the other_active_crtc only if there's only 1 other
4322          * active crtc. */
4323         for_each_intel_crtc(dev, crtc_it) {
4324                 if (!crtc_it->active || crtc_it == crtc)
4325                         continue;
4326
4327                 if (other_active_crtc)
4328                         return;
4329
4330                 other_active_crtc = crtc_it;
4331         }
4332         if (!other_active_crtc)
4333                 return;
4334
4335         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4336         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337 }
4338
4339 static void haswell_crtc_enable(struct drm_crtc *crtc)
4340 {
4341         struct drm_device *dev = crtc->dev;
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344         struct intel_encoder *encoder;
4345         int pipe = intel_crtc->pipe;
4346
4347         WARN_ON(!crtc->enabled);
4348
4349         if (intel_crtc->active)
4350                 return;
4351
4352         if (intel_crtc_to_shared_dpll(intel_crtc))
4353                 intel_enable_shared_dpll(intel_crtc);
4354
4355         if (intel_crtc->config.has_dp_encoder)
4356                 intel_dp_set_m_n(intel_crtc);
4357
4358         intel_set_pipe_timings(intel_crtc);
4359
4360         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4361                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4362                            intel_crtc->config.pixel_multiplier - 1);
4363         }
4364
4365         if (intel_crtc->config.has_pch_encoder) {
4366                 intel_cpu_transcoder_set_m_n(intel_crtc,
4367                                      &intel_crtc->config.fdi_m_n, NULL);
4368         }
4369
4370         haswell_set_pipeconf(crtc);
4371
4372         intel_set_pipe_csc(crtc);
4373
4374         intel_crtc->active = true;
4375
4376         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4377         for_each_encoder_on_crtc(dev, crtc, encoder)
4378                 if (encoder->pre_enable)
4379                         encoder->pre_enable(encoder);
4380
4381         if (intel_crtc->config.has_pch_encoder) {
4382                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4383                                                       true);
4384                 dev_priv->display.fdi_link_train(crtc);
4385         }
4386
4387         intel_ddi_enable_pipe_clock(intel_crtc);
4388
4389         ironlake_pfit_enable(intel_crtc);
4390
4391         /*
4392          * On ILK+ LUT must be loaded before the pipe is running but with
4393          * clocks enabled
4394          */
4395         intel_crtc_load_lut(crtc);
4396
4397         intel_ddi_set_pipe_settings(crtc);
4398         intel_ddi_enable_transcoder_func(crtc);
4399
4400         intel_update_watermarks(crtc);
4401         intel_enable_pipe(intel_crtc);
4402
4403         if (intel_crtc->config.has_pch_encoder)
4404                 lpt_pch_enable(crtc);
4405
4406         if (intel_crtc->config.dp_encoder_is_mst)
4407                 intel_ddi_set_vc_payload_alloc(crtc, true);
4408
4409         for_each_encoder_on_crtc(dev, crtc, encoder) {
4410                 encoder->enable(encoder);
4411                 intel_opregion_notify_encoder(encoder, true);
4412         }
4413
4414         assert_vblank_disabled(crtc);
4415         drm_crtc_vblank_on(crtc);
4416
4417         /* If we change the relative order between pipe/planes enabling, we need
4418          * to change the workaround. */
4419         haswell_mode_set_planes_workaround(intel_crtc);
4420         intel_crtc_enable_planes(crtc);
4421 }
4422
4423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4424 {
4425         struct drm_device *dev = crtc->base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         int pipe = crtc->pipe;
4428
4429         /* To avoid upsetting the power well on haswell only disable the pfit if
4430          * it's in use. The hw state code will make sure we get this right. */
4431         if (crtc->config.pch_pfit.enabled) {
4432                 I915_WRITE(PF_CTL(pipe), 0);
4433                 I915_WRITE(PF_WIN_POS(pipe), 0);
4434                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4435         }
4436 }
4437
4438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4439 {
4440         struct drm_device *dev = crtc->dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443         struct intel_encoder *encoder;
4444         int pipe = intel_crtc->pipe;
4445         u32 reg, temp;
4446
4447         if (!intel_crtc->active)
4448                 return;
4449
4450         intel_crtc_disable_planes(crtc);
4451
4452         drm_crtc_vblank_off(crtc);
4453         assert_vblank_disabled(crtc);
4454
4455         for_each_encoder_on_crtc(dev, crtc, encoder)
4456                 encoder->disable(encoder);
4457
4458         if (intel_crtc->config.has_pch_encoder)
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4460
4461         intel_disable_pipe(intel_crtc);
4462
4463         ironlake_pfit_disable(intel_crtc);
4464
4465         for_each_encoder_on_crtc(dev, crtc, encoder)
4466                 if (encoder->post_disable)
4467                         encoder->post_disable(encoder);
4468
4469         if (intel_crtc->config.has_pch_encoder) {
4470                 ironlake_fdi_disable(crtc);
4471
4472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4473                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4474
4475                 if (HAS_PCH_CPT(dev)) {
4476                         /* disable TRANS_DP_CTL */
4477                         reg = TRANS_DP_CTL(pipe);
4478                         temp = I915_READ(reg);
4479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4480                                   TRANS_DP_PORT_SEL_MASK);
4481                         temp |= TRANS_DP_PORT_SEL_NONE;
4482                         I915_WRITE(reg, temp);
4483
4484                         /* disable DPLL_SEL */
4485                         temp = I915_READ(PCH_DPLL_SEL);
4486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4487                         I915_WRITE(PCH_DPLL_SEL, temp);
4488                 }
4489
4490                 /* disable PCH DPLL */
4491                 intel_disable_shared_dpll(intel_crtc);
4492
4493                 ironlake_fdi_pll_disable(intel_crtc);
4494         }
4495
4496         intel_crtc->active = false;
4497         intel_update_watermarks(crtc);
4498
4499         mutex_lock(&dev->struct_mutex);
4500         intel_update_fbc(dev);
4501         mutex_unlock(&dev->struct_mutex);
4502 }
4503
4504 static void haswell_crtc_disable(struct drm_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509         struct intel_encoder *encoder;
4510         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4511
4512         if (!intel_crtc->active)
4513                 return;
4514
4515         intel_crtc_disable_planes(crtc);
4516
4517         drm_crtc_vblank_off(crtc);
4518         assert_vblank_disabled(crtc);
4519
4520         for_each_encoder_on_crtc(dev, crtc, encoder) {
4521                 intel_opregion_notify_encoder(encoder, false);
4522                 encoder->disable(encoder);
4523         }
4524
4525         if (intel_crtc->config.has_pch_encoder)
4526                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4527                                                       false);
4528         intel_disable_pipe(intel_crtc);
4529
4530         if (intel_crtc->config.dp_encoder_is_mst)
4531                 intel_ddi_set_vc_payload_alloc(crtc, false);
4532
4533         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4534
4535         ironlake_pfit_disable(intel_crtc);
4536
4537         intel_ddi_disable_pipe_clock(intel_crtc);
4538
4539         if (intel_crtc->config.has_pch_encoder) {
4540                 lpt_disable_pch_transcoder(dev_priv);
4541                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4542                                                       true);
4543                 intel_ddi_fdi_disable(crtc);
4544         }
4545
4546         for_each_encoder_on_crtc(dev, crtc, encoder)
4547                 if (encoder->post_disable)
4548                         encoder->post_disable(encoder);
4549
4550         intel_crtc->active = false;
4551         intel_update_watermarks(crtc);
4552
4553         mutex_lock(&dev->struct_mutex);
4554         intel_update_fbc(dev);
4555         mutex_unlock(&dev->struct_mutex);
4556
4557         if (intel_crtc_to_shared_dpll(intel_crtc))
4558                 intel_disable_shared_dpll(intel_crtc);
4559 }
4560
4561 static void ironlake_crtc_off(struct drm_crtc *crtc)
4562 {
4563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4564         intel_put_shared_dpll(intel_crtc);
4565 }
4566
4567
4568 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572         struct intel_crtc_config *pipe_config = &crtc->config;
4573
4574         if (!crtc->config.gmch_pfit.control)
4575                 return;
4576
4577         /*
4578          * The panel fitter should only be adjusted whilst the pipe is disabled,
4579          * according to register description and PRM.
4580          */
4581         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4582         assert_pipe_disabled(dev_priv, crtc->pipe);
4583
4584         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4585         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4586
4587         /* Border color in case we don't scale up to the full screen. Black by
4588          * default, change to something else for debugging. */
4589         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4590 }
4591
4592 static enum intel_display_power_domain port_to_power_domain(enum port port)
4593 {
4594         switch (port) {
4595         case PORT_A:
4596                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4597         case PORT_B:
4598                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4599         case PORT_C:
4600                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4601         case PORT_D:
4602                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4603         default:
4604                 WARN_ON_ONCE(1);
4605                 return POWER_DOMAIN_PORT_OTHER;
4606         }
4607 }
4608
4609 #define for_each_power_domain(domain, mask)                             \
4610         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4611                 if ((1 << (domain)) & (mask))
4612
4613 enum intel_display_power_domain
4614 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4615 {
4616         struct drm_device *dev = intel_encoder->base.dev;
4617         struct intel_digital_port *intel_dig_port;
4618
4619         switch (intel_encoder->type) {
4620         case INTEL_OUTPUT_UNKNOWN:
4621                 /* Only DDI platforms should ever use this output type */
4622                 WARN_ON_ONCE(!HAS_DDI(dev));
4623         case INTEL_OUTPUT_DISPLAYPORT:
4624         case INTEL_OUTPUT_HDMI:
4625         case INTEL_OUTPUT_EDP:
4626                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4627                 return port_to_power_domain(intel_dig_port->port);
4628         case INTEL_OUTPUT_DP_MST:
4629                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4630                 return port_to_power_domain(intel_dig_port->port);
4631         case INTEL_OUTPUT_ANALOG:
4632                 return POWER_DOMAIN_PORT_CRT;
4633         case INTEL_OUTPUT_DSI:
4634                 return POWER_DOMAIN_PORT_DSI;
4635         default:
4636                 return POWER_DOMAIN_PORT_OTHER;
4637         }
4638 }
4639
4640 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct intel_encoder *intel_encoder;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         enum pipe pipe = intel_crtc->pipe;
4646         unsigned long mask;
4647         enum transcoder transcoder;
4648
4649         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4650
4651         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4652         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4653         if (intel_crtc->config.pch_pfit.enabled ||
4654             intel_crtc->config.pch_pfit.force_thru)
4655                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4656
4657         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4658                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4659
4660         return mask;
4661 }
4662
4663 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4664 {
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4667         struct intel_crtc *crtc;
4668
4669         /*
4670          * First get all needed power domains, then put all unneeded, to avoid
4671          * any unnecessary toggling of the power wells.
4672          */
4673         for_each_intel_crtc(dev, crtc) {
4674                 enum intel_display_power_domain domain;
4675
4676                 if (!crtc->base.enabled)
4677                         continue;
4678
4679                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4680
4681                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4682                         intel_display_power_get(dev_priv, domain);
4683         }
4684
4685         for_each_intel_crtc(dev, crtc) {
4686                 enum intel_display_power_domain domain;
4687
4688                 for_each_power_domain(domain, crtc->enabled_power_domains)
4689                         intel_display_power_put(dev_priv, domain);
4690
4691                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4692         }
4693
4694         intel_display_set_init_power(dev_priv, false);
4695 }
4696
4697 /* returns HPLL frequency in kHz */
4698 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4699 {
4700         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4701
4702         /* Obtain SKU information */
4703         mutex_lock(&dev_priv->dpio_lock);
4704         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4705                 CCK_FUSE_HPLL_FREQ_MASK;
4706         mutex_unlock(&dev_priv->dpio_lock);
4707
4708         return vco_freq[hpll_freq] * 1000;
4709 }
4710
4711 static void vlv_update_cdclk(struct drm_device *dev)
4712 {
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714
4715         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4716         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4717                          dev_priv->vlv_cdclk_freq);
4718
4719         /*
4720          * Program the gmbus_freq based on the cdclk frequency.
4721          * BSpec erroneously claims we should aim for 4MHz, but
4722          * in fact 1MHz is the correct frequency.
4723          */
4724         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4725 }
4726
4727 /* Adjust CDclk dividers to allow high res or save power if possible */
4728 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4729 {
4730         struct drm_i915_private *dev_priv = dev->dev_private;
4731         u32 val, cmd;
4732
4733         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4734
4735         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4736                 cmd = 2;
4737         else if (cdclk == 266667)
4738                 cmd = 1;
4739         else
4740                 cmd = 0;
4741
4742         mutex_lock(&dev_priv->rps.hw_lock);
4743         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4744         val &= ~DSPFREQGUAR_MASK;
4745         val |= (cmd << DSPFREQGUAR_SHIFT);
4746         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4747         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4748                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4749                      50)) {
4750                 DRM_ERROR("timed out waiting for CDclk change\n");
4751         }
4752         mutex_unlock(&dev_priv->rps.hw_lock);
4753
4754         if (cdclk == 400000) {
4755                 u32 divider, vco;
4756
4757                 vco = valleyview_get_vco(dev_priv);
4758                 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4759
4760                 mutex_lock(&dev_priv->dpio_lock);
4761                 /* adjust cdclk divider */
4762                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4763                 val &= ~DISPLAY_FREQUENCY_VALUES;
4764                 val |= divider;
4765                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4766
4767                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4768                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4769                              50))
4770                         DRM_ERROR("timed out waiting for CDclk change\n");
4771                 mutex_unlock(&dev_priv->dpio_lock);
4772         }
4773
4774         mutex_lock(&dev_priv->dpio_lock);
4775         /* adjust self-refresh exit latency value */
4776         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4777         val &= ~0x7f;
4778
4779         /*
4780          * For high bandwidth configs, we set a higher latency in the bunit
4781          * so that the core display fetch happens in time to avoid underruns.
4782          */
4783         if (cdclk == 400000)
4784                 val |= 4500 / 250; /* 4.5 usec */
4785         else
4786                 val |= 3000 / 250; /* 3.0 usec */
4787         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4788         mutex_unlock(&dev_priv->dpio_lock);
4789
4790         vlv_update_cdclk(dev);
4791 }
4792
4793 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         u32 val, cmd;
4797
4798         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4799
4800         switch (cdclk) {
4801         case 400000:
4802                 cmd = 3;
4803                 break;
4804         case 333333:
4805         case 320000:
4806                 cmd = 2;
4807                 break;
4808         case 266667:
4809                 cmd = 1;
4810                 break;
4811         case 200000:
4812                 cmd = 0;
4813                 break;
4814         default:
4815                 WARN_ON(1);
4816                 return;
4817         }
4818
4819         mutex_lock(&dev_priv->rps.hw_lock);
4820         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4821         val &= ~DSPFREQGUAR_MASK_CHV;
4822         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4823         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4824         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4825                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4826                      50)) {
4827                 DRM_ERROR("timed out waiting for CDclk change\n");
4828         }
4829         mutex_unlock(&dev_priv->rps.hw_lock);
4830
4831         vlv_update_cdclk(dev);
4832 }
4833
4834 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4835                                  int max_pixclk)
4836 {
4837         int vco = valleyview_get_vco(dev_priv);
4838         int freq_320 = (vco <<  1) % 320000 != 0 ? 333333 : 320000;
4839
4840         /* FIXME: Punit isn't quite ready yet */
4841         if (IS_CHERRYVIEW(dev_priv->dev))
4842                 return 400000;
4843
4844         /*
4845          * Really only a few cases to deal with, as only 4 CDclks are supported:
4846          *   200MHz
4847          *   267MHz
4848          *   320/333MHz (depends on HPLL freq)
4849          *   400MHz
4850          * So we check to see whether we're above 90% of the lower bin and
4851          * adjust if needed.
4852          *
4853          * We seem to get an unstable or solid color picture at 200MHz.
4854          * Not sure what's wrong. For now use 200MHz only when all pipes
4855          * are off.
4856          */
4857         if (max_pixclk > freq_320*9/10)
4858                 return 400000;
4859         else if (max_pixclk > 266667*9/10)
4860                 return freq_320;
4861         else if (max_pixclk > 0)
4862                 return 266667;
4863         else
4864                 return 200000;
4865 }
4866
4867 /* compute the max pixel clock for new configuration */
4868 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4869 {
4870         struct drm_device *dev = dev_priv->dev;
4871         struct intel_crtc *intel_crtc;
4872         int max_pixclk = 0;
4873
4874         for_each_intel_crtc(dev, intel_crtc) {
4875                 if (intel_crtc->new_enabled)
4876                         max_pixclk = max(max_pixclk,
4877                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4878         }
4879
4880         return max_pixclk;
4881 }
4882
4883 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4884                                             unsigned *prepare_pipes)
4885 {
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887         struct intel_crtc *intel_crtc;
4888         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4889
4890         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4891             dev_priv->vlv_cdclk_freq)
4892                 return;
4893
4894         /* disable/enable all currently active pipes while we change cdclk */
4895         for_each_intel_crtc(dev, intel_crtc)
4896                 if (intel_crtc->base.enabled)
4897                         *prepare_pipes |= (1 << intel_crtc->pipe);
4898 }
4899
4900 static void valleyview_modeset_global_resources(struct drm_device *dev)
4901 {
4902         struct drm_i915_private *dev_priv = dev->dev_private;
4903         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4904         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4905
4906         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4907                 if (IS_CHERRYVIEW(dev))
4908                         cherryview_set_cdclk(dev, req_cdclk);
4909                 else
4910                         valleyview_set_cdclk(dev, req_cdclk);
4911         }
4912
4913         modeset_update_crtc_power_domains(dev);
4914 }
4915
4916 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4917 {
4918         struct drm_device *dev = crtc->dev;
4919         struct drm_i915_private *dev_priv = to_i915(dev);
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         struct intel_encoder *encoder;
4922         int pipe = intel_crtc->pipe;
4923         bool is_dsi;
4924
4925         WARN_ON(!crtc->enabled);
4926
4927         if (intel_crtc->active)
4928                 return;
4929
4930         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4931
4932         if (!is_dsi) {
4933                 if (IS_CHERRYVIEW(dev))
4934                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4935                 else
4936                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4937         }
4938
4939         if (intel_crtc->config.has_dp_encoder)
4940                 intel_dp_set_m_n(intel_crtc);
4941
4942         intel_set_pipe_timings(intel_crtc);
4943
4944         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4945                 struct drm_i915_private *dev_priv = dev->dev_private;
4946
4947                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4948                 I915_WRITE(CHV_CANVAS(pipe), 0);
4949         }
4950
4951         i9xx_set_pipeconf(intel_crtc);
4952
4953         intel_crtc->active = true;
4954
4955         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4956
4957         for_each_encoder_on_crtc(dev, crtc, encoder)
4958                 if (encoder->pre_pll_enable)
4959                         encoder->pre_pll_enable(encoder);
4960
4961         if (!is_dsi) {
4962                 if (IS_CHERRYVIEW(dev))
4963                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4964                 else
4965                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4966         }
4967
4968         for_each_encoder_on_crtc(dev, crtc, encoder)
4969                 if (encoder->pre_enable)
4970                         encoder->pre_enable(encoder);
4971
4972         i9xx_pfit_enable(intel_crtc);
4973
4974         intel_crtc_load_lut(crtc);
4975
4976         intel_update_watermarks(crtc);
4977         intel_enable_pipe(intel_crtc);
4978
4979         for_each_encoder_on_crtc(dev, crtc, encoder)
4980                 encoder->enable(encoder);
4981
4982         assert_vblank_disabled(crtc);
4983         drm_crtc_vblank_on(crtc);
4984
4985         intel_crtc_enable_planes(crtc);
4986
4987         /* Underruns don't raise interrupts, so check manually. */
4988         i9xx_check_fifo_underruns(dev_priv);
4989 }
4990
4991 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4992 {
4993         struct drm_device *dev = crtc->base.dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995
4996         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4997         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4998 }
4999
5000 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5001 {
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_private *dev_priv = to_i915(dev);
5004         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005         struct intel_encoder *encoder;
5006         int pipe = intel_crtc->pipe;
5007
5008         WARN_ON(!crtc->enabled);
5009
5010         if (intel_crtc->active)
5011                 return;
5012
5013         i9xx_set_pll_dividers(intel_crtc);
5014
5015         if (intel_crtc->config.has_dp_encoder)
5016                 intel_dp_set_m_n(intel_crtc);
5017
5018         intel_set_pipe_timings(intel_crtc);
5019
5020         i9xx_set_pipeconf(intel_crtc);
5021
5022         intel_crtc->active = true;
5023
5024         if (!IS_GEN2(dev))
5025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5026
5027         for_each_encoder_on_crtc(dev, crtc, encoder)
5028                 if (encoder->pre_enable)
5029                         encoder->pre_enable(encoder);
5030
5031         i9xx_enable_pll(intel_crtc);
5032
5033         i9xx_pfit_enable(intel_crtc);
5034
5035         intel_crtc_load_lut(crtc);
5036
5037         intel_update_watermarks(crtc);
5038         intel_enable_pipe(intel_crtc);
5039
5040         for_each_encoder_on_crtc(dev, crtc, encoder)
5041                 encoder->enable(encoder);
5042
5043         assert_vblank_disabled(crtc);
5044         drm_crtc_vblank_on(crtc);
5045
5046         intel_crtc_enable_planes(crtc);
5047
5048         /*
5049          * Gen2 reports pipe underruns whenever all planes are disabled.
5050          * So don't enable underrun reporting before at least some planes
5051          * are enabled.
5052          * FIXME: Need to fix the logic to work when we turn off all planes
5053          * but leave the pipe running.
5054          */
5055         if (IS_GEN2(dev))
5056                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5057
5058         /* Underruns don't raise interrupts, so check manually. */
5059         i9xx_check_fifo_underruns(dev_priv);
5060 }
5061
5062 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5063 {
5064         struct drm_device *dev = crtc->base.dev;
5065         struct drm_i915_private *dev_priv = dev->dev_private;
5066
5067         if (!crtc->config.gmch_pfit.control)
5068                 return;
5069
5070         assert_pipe_disabled(dev_priv, crtc->pipe);
5071
5072         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5073                          I915_READ(PFIT_CONTROL));
5074         I915_WRITE(PFIT_CONTROL, 0);
5075 }
5076
5077 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5078 {
5079         struct drm_device *dev = crtc->dev;
5080         struct drm_i915_private *dev_priv = dev->dev_private;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         struct intel_encoder *encoder;
5083         int pipe = intel_crtc->pipe;
5084
5085         if (!intel_crtc->active)
5086                 return;
5087
5088         /*
5089          * Gen2 reports pipe underruns whenever all planes are disabled.
5090          * So diasble underrun reporting before all the planes get disabled.
5091          * FIXME: Need to fix the logic to work when we turn off all planes
5092          * but leave the pipe running.
5093          */
5094         if (IS_GEN2(dev))
5095                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5096
5097         /*
5098          * Vblank time updates from the shadow to live plane control register
5099          * are blocked if the memory self-refresh mode is active at that
5100          * moment. So to make sure the plane gets truly disabled, disable
5101          * first the self-refresh mode. The self-refresh enable bit in turn
5102          * will be checked/applied by the HW only at the next frame start
5103          * event which is after the vblank start event, so we need to have a
5104          * wait-for-vblank between disabling the plane and the pipe.
5105          */
5106         intel_set_memory_cxsr(dev_priv, false);
5107         intel_crtc_disable_planes(crtc);
5108
5109         /*
5110          * On gen2 planes are double buffered but the pipe isn't, so we must
5111          * wait for planes to fully turn off before disabling the pipe.
5112          * We also need to wait on all gmch platforms because of the
5113          * self-refresh mode constraint explained above.
5114          */
5115         intel_wait_for_vblank(dev, pipe);
5116
5117         drm_crtc_vblank_off(crtc);
5118         assert_vblank_disabled(crtc);
5119
5120         for_each_encoder_on_crtc(dev, crtc, encoder)
5121                 encoder->disable(encoder);
5122
5123         intel_disable_pipe(intel_crtc);
5124
5125         i9xx_pfit_disable(intel_crtc);
5126
5127         for_each_encoder_on_crtc(dev, crtc, encoder)
5128                 if (encoder->post_disable)
5129                         encoder->post_disable(encoder);
5130
5131         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5132                 if (IS_CHERRYVIEW(dev))
5133                         chv_disable_pll(dev_priv, pipe);
5134                 else if (IS_VALLEYVIEW(dev))
5135                         vlv_disable_pll(dev_priv, pipe);
5136                 else
5137                         i9xx_disable_pll(intel_crtc);
5138         }
5139
5140         if (!IS_GEN2(dev))
5141                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143         intel_crtc->active = false;
5144         intel_update_watermarks(crtc);
5145
5146         mutex_lock(&dev->struct_mutex);
5147         intel_update_fbc(dev);
5148         mutex_unlock(&dev->struct_mutex);
5149 }
5150
5151 static void i9xx_crtc_off(struct drm_crtc *crtc)
5152 {
5153 }
5154
5155 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5156                                     bool enabled)
5157 {
5158         struct drm_device *dev = crtc->dev;
5159         struct drm_i915_master_private *master_priv;
5160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161         int pipe = intel_crtc->pipe;
5162
5163         if (!dev->primary->master)
5164                 return;
5165
5166         master_priv = dev->primary->master->driver_priv;
5167         if (!master_priv->sarea_priv)
5168                 return;
5169
5170         switch (pipe) {
5171         case 0:
5172                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5173                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5174                 break;
5175         case 1:
5176                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5177                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5178                 break;
5179         default:
5180                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5181                 break;
5182         }
5183 }
5184
5185 /* Master function to enable/disable CRTC and corresponding power wells */
5186 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5187 {
5188         struct drm_device *dev = crtc->dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191         enum intel_display_power_domain domain;
5192         unsigned long domains;
5193
5194         if (enable) {
5195                 if (!intel_crtc->active) {
5196                         domains = get_crtc_power_domains(crtc);
5197                         for_each_power_domain(domain, domains)
5198                                 intel_display_power_get(dev_priv, domain);
5199                         intel_crtc->enabled_power_domains = domains;
5200
5201                         dev_priv->display.crtc_enable(crtc);
5202                 }
5203         } else {
5204                 if (intel_crtc->active) {
5205                         dev_priv->display.crtc_disable(crtc);
5206
5207                         domains = intel_crtc->enabled_power_domains;
5208                         for_each_power_domain(domain, domains)
5209                                 intel_display_power_put(dev_priv, domain);
5210                         intel_crtc->enabled_power_domains = 0;
5211                 }
5212         }
5213 }
5214
5215 /**
5216  * Sets the power management mode of the pipe and plane.
5217  */
5218 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5219 {
5220         struct drm_device *dev = crtc->dev;
5221         struct intel_encoder *intel_encoder;
5222         bool enable = false;
5223
5224         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5225                 enable |= intel_encoder->connectors_active;
5226
5227         intel_crtc_control(crtc, enable);
5228
5229         intel_crtc_update_sarea(crtc, enable);
5230 }
5231
5232 static void intel_crtc_disable(struct drm_crtc *crtc)
5233 {
5234         struct drm_device *dev = crtc->dev;
5235         struct drm_connector *connector;
5236         struct drm_i915_private *dev_priv = dev->dev_private;
5237         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5238         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5239
5240         /* crtc should still be enabled when we disable it. */
5241         WARN_ON(!crtc->enabled);
5242
5243         dev_priv->display.crtc_disable(crtc);
5244         intel_crtc_update_sarea(crtc, false);
5245         dev_priv->display.off(crtc);
5246
5247         if (crtc->primary->fb) {
5248                 mutex_lock(&dev->struct_mutex);
5249                 intel_unpin_fb_obj(old_obj);
5250                 i915_gem_track_fb(old_obj, NULL,
5251                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5252                 mutex_unlock(&dev->struct_mutex);
5253                 crtc->primary->fb = NULL;
5254         }
5255
5256         /* Update computed state. */
5257         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5258                 if (!connector->encoder || !connector->encoder->crtc)
5259                         continue;
5260
5261                 if (connector->encoder->crtc != crtc)
5262                         continue;
5263
5264                 connector->dpms = DRM_MODE_DPMS_OFF;
5265                 to_intel_encoder(connector->encoder)->connectors_active = false;
5266         }
5267 }
5268
5269 void intel_encoder_destroy(struct drm_encoder *encoder)
5270 {
5271         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5272
5273         drm_encoder_cleanup(encoder);
5274         kfree(intel_encoder);
5275 }
5276
5277 /* Simple dpms helper for encoders with just one connector, no cloning and only
5278  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5279  * state of the entire output pipe. */
5280 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5281 {
5282         if (mode == DRM_MODE_DPMS_ON) {
5283                 encoder->connectors_active = true;
5284
5285                 intel_crtc_update_dpms(encoder->base.crtc);
5286         } else {
5287                 encoder->connectors_active = false;
5288
5289                 intel_crtc_update_dpms(encoder->base.crtc);
5290         }
5291 }
5292
5293 /* Cross check the actual hw state with our own modeset state tracking (and it's
5294  * internal consistency). */
5295 static void intel_connector_check_state(struct intel_connector *connector)
5296 {
5297         if (connector->get_hw_state(connector)) {
5298                 struct intel_encoder *encoder = connector->encoder;
5299                 struct drm_crtc *crtc;
5300                 bool encoder_enabled;
5301                 enum pipe pipe;
5302
5303                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5304                               connector->base.base.id,
5305                               connector->base.name);
5306
5307                 /* there is no real hw state for MST connectors */
5308                 if (connector->mst_port)
5309                         return;
5310
5311                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5312                      "wrong connector dpms state\n");
5313                 WARN(connector->base.encoder != &encoder->base,
5314                      "active connector not linked to encoder\n");
5315
5316                 if (encoder) {
5317                         WARN(!encoder->connectors_active,
5318                              "encoder->connectors_active not set\n");
5319
5320                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5321                         WARN(!encoder_enabled, "encoder not enabled\n");
5322                         if (WARN_ON(!encoder->base.crtc))
5323                                 return;
5324
5325                         crtc = encoder->base.crtc;
5326
5327                         WARN(!crtc->enabled, "crtc not enabled\n");
5328                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5329                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5330                              "encoder active on the wrong pipe\n");
5331                 }
5332         }
5333 }
5334
5335 /* Even simpler default implementation, if there's really no special case to
5336  * consider. */
5337 void intel_connector_dpms(struct drm_connector *connector, int mode)
5338 {
5339         /* All the simple cases only support two dpms states. */
5340         if (mode != DRM_MODE_DPMS_ON)
5341                 mode = DRM_MODE_DPMS_OFF;
5342
5343         if (mode == connector->dpms)
5344                 return;
5345
5346         connector->dpms = mode;
5347
5348         /* Only need to change hw state when actually enabled */
5349         if (connector->encoder)
5350                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5351
5352         intel_modeset_check_state(connector->dev);
5353 }
5354
5355 /* Simple connector->get_hw_state implementation for encoders that support only
5356  * one connector and no cloning and hence the encoder state determines the state
5357  * of the connector. */
5358 bool intel_connector_get_hw_state(struct intel_connector *connector)
5359 {
5360         enum pipe pipe = 0;
5361         struct intel_encoder *encoder = connector->encoder;
5362
5363         return encoder->get_hw_state(encoder, &pipe);
5364 }
5365
5366 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5367                                      struct intel_crtc_config *pipe_config)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         struct intel_crtc *pipe_B_crtc =
5371                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5372
5373         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5374                       pipe_name(pipe), pipe_config->fdi_lanes);
5375         if (pipe_config->fdi_lanes > 4) {
5376                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5377                               pipe_name(pipe), pipe_config->fdi_lanes);
5378                 return false;
5379         }
5380
5381         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5382                 if (pipe_config->fdi_lanes > 2) {
5383                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5384                                       pipe_config->fdi_lanes);
5385                         return false;
5386                 } else {
5387                         return true;
5388                 }
5389         }
5390
5391         if (INTEL_INFO(dev)->num_pipes == 2)
5392                 return true;
5393
5394         /* Ivybridge 3 pipe is really complicated */
5395         switch (pipe) {
5396         case PIPE_A:
5397                 return true;
5398         case PIPE_B:
5399                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5400                     pipe_config->fdi_lanes > 2) {
5401                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5402                                       pipe_name(pipe), pipe_config->fdi_lanes);
5403                         return false;
5404                 }
5405                 return true;
5406         case PIPE_C:
5407                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5408                     pipe_B_crtc->config.fdi_lanes <= 2) {
5409                         if (pipe_config->fdi_lanes > 2) {
5410                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5411                                               pipe_name(pipe), pipe_config->fdi_lanes);
5412                                 return false;
5413                         }
5414                 } else {
5415                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5416                         return false;
5417                 }
5418                 return true;
5419         default:
5420                 BUG();
5421         }
5422 }
5423
5424 #define RETRY 1
5425 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5426                                        struct intel_crtc_config *pipe_config)
5427 {
5428         struct drm_device *dev = intel_crtc->base.dev;
5429         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5430         int lane, link_bw, fdi_dotclock;
5431         bool setup_ok, needs_recompute = false;
5432
5433 retry:
5434         /* FDI is a binary signal running at ~2.7GHz, encoding
5435          * each output octet as 10 bits. The actual frequency
5436          * is stored as a divider into a 100MHz clock, and the
5437          * mode pixel clock is stored in units of 1KHz.
5438          * Hence the bw of each lane in terms of the mode signal
5439          * is:
5440          */
5441         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5442
5443         fdi_dotclock = adjusted_mode->crtc_clock;
5444
5445         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5446                                            pipe_config->pipe_bpp);
5447
5448         pipe_config->fdi_lanes = lane;
5449
5450         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5451                                link_bw, &pipe_config->fdi_m_n);
5452
5453         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5454                                             intel_crtc->pipe, pipe_config);
5455         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5456                 pipe_config->pipe_bpp -= 2*3;
5457                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5458                               pipe_config->pipe_bpp);
5459                 needs_recompute = true;
5460                 pipe_config->bw_constrained = true;
5461
5462                 goto retry;
5463         }
5464
5465         if (needs_recompute)
5466                 return RETRY;
5467
5468         return setup_ok ? 0 : -EINVAL;
5469 }
5470
5471 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5472                                    struct intel_crtc_config *pipe_config)
5473 {
5474         pipe_config->ips_enabled = i915.enable_ips &&
5475                                    hsw_crtc_supports_ips(crtc) &&
5476                                    pipe_config->pipe_bpp <= 24;
5477 }
5478
5479 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5480                                      struct intel_crtc_config *pipe_config)
5481 {
5482         struct drm_device *dev = crtc->base.dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5485
5486         /* FIXME should check pixel clock limits on all platforms */
5487         if (INTEL_INFO(dev)->gen < 4) {
5488                 int clock_limit =
5489                         dev_priv->display.get_display_clock_speed(dev);
5490
5491                 /*
5492                  * Enable pixel doubling when the dot clock
5493                  * is > 90% of the (display) core speed.
5494                  *
5495                  * GDG double wide on either pipe,
5496                  * otherwise pipe A only.
5497                  */
5498                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5499                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5500                         clock_limit *= 2;
5501                         pipe_config->double_wide = true;
5502                 }
5503
5504                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5505                         return -EINVAL;
5506         }
5507
5508         /*
5509          * Pipe horizontal size must be even in:
5510          * - DVO ganged mode
5511          * - LVDS dual channel mode
5512          * - Double wide pipe
5513          */
5514         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5515              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5516                 pipe_config->pipe_src_w &= ~1;
5517
5518         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5519          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5520          */
5521         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5522                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5523                 return -EINVAL;
5524
5525         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5526                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5527         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5528                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5529                  * for lvds. */
5530                 pipe_config->pipe_bpp = 8*3;
5531         }
5532
5533         if (HAS_IPS(dev))
5534                 hsw_compute_ips_config(crtc, pipe_config);
5535
5536         /*
5537          * XXX: PCH/WRPLL clock sharing is done in ->mode_set if ->compute_clock is not
5538          * set, so make sure the old clock survives for now.
5539          */
5540         if (dev_priv->display.crtc_compute_clock == NULL &&
5541             (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)))
5542                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5543
5544         if (pipe_config->has_pch_encoder)
5545                 return ironlake_fdi_compute_config(crtc, pipe_config);
5546
5547         return 0;
5548 }
5549
5550 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5551 {
5552         struct drm_i915_private *dev_priv = dev->dev_private;
5553         int vco = valleyview_get_vco(dev_priv);
5554         u32 val;
5555         int divider;
5556
5557         /* FIXME: Punit isn't quite ready yet */
5558         if (IS_CHERRYVIEW(dev))
5559                 return 400000;
5560
5561         mutex_lock(&dev_priv->dpio_lock);
5562         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5563         mutex_unlock(&dev_priv->dpio_lock);
5564
5565         divider = val & DISPLAY_FREQUENCY_VALUES;
5566
5567         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5568              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5569              "cdclk change in progress\n");
5570
5571         return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5572 }
5573
5574 static int i945_get_display_clock_speed(struct drm_device *dev)
5575 {
5576         return 400000;
5577 }
5578
5579 static int i915_get_display_clock_speed(struct drm_device *dev)
5580 {
5581         return 333000;
5582 }
5583
5584 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5585 {
5586         return 200000;
5587 }
5588
5589 static int pnv_get_display_clock_speed(struct drm_device *dev)
5590 {
5591         u16 gcfgc = 0;
5592
5593         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5594
5595         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5596         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5597                 return 267000;
5598         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5599                 return 333000;
5600         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5601                 return 444000;
5602         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5603                 return 200000;
5604         default:
5605                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5606         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5607                 return 133000;
5608         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5609                 return 167000;
5610         }
5611 }
5612
5613 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5614 {
5615         u16 gcfgc = 0;
5616
5617         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5618
5619         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5620                 return 133000;
5621         else {
5622                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5623                 case GC_DISPLAY_CLOCK_333_MHZ:
5624                         return 333000;
5625                 default:
5626                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5627                         return 190000;
5628                 }
5629         }
5630 }
5631
5632 static int i865_get_display_clock_speed(struct drm_device *dev)
5633 {
5634         return 266000;
5635 }
5636
5637 static int i855_get_display_clock_speed(struct drm_device *dev)
5638 {
5639         u16 hpllcc = 0;
5640         /* Assume that the hardware is in the high speed state.  This
5641          * should be the default.
5642          */
5643         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5644         case GC_CLOCK_133_200:
5645         case GC_CLOCK_100_200:
5646                 return 200000;
5647         case GC_CLOCK_166_250:
5648                 return 250000;
5649         case GC_CLOCK_100_133:
5650                 return 133000;
5651         }
5652
5653         /* Shouldn't happen */
5654         return 0;
5655 }
5656
5657 static int i830_get_display_clock_speed(struct drm_device *dev)
5658 {
5659         return 133000;
5660 }
5661
5662 static void
5663 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5664 {
5665         while (*num > DATA_LINK_M_N_MASK ||
5666                *den > DATA_LINK_M_N_MASK) {
5667                 *num >>= 1;
5668                 *den >>= 1;
5669         }
5670 }
5671
5672 static void compute_m_n(unsigned int m, unsigned int n,
5673                         uint32_t *ret_m, uint32_t *ret_n)
5674 {
5675         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5676         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5677         intel_reduce_m_n_ratio(ret_m, ret_n);
5678 }
5679
5680 void
5681 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5682                        int pixel_clock, int link_clock,
5683                        struct intel_link_m_n *m_n)
5684 {
5685         m_n->tu = 64;
5686
5687         compute_m_n(bits_per_pixel * pixel_clock,
5688                     link_clock * nlanes * 8,
5689                     &m_n->gmch_m, &m_n->gmch_n);
5690
5691         compute_m_n(pixel_clock, link_clock,
5692                     &m_n->link_m, &m_n->link_n);
5693 }
5694
5695 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5696 {
5697         if (i915.panel_use_ssc >= 0)
5698                 return i915.panel_use_ssc != 0;
5699         return dev_priv->vbt.lvds_use_ssc
5700                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5701 }
5702
5703 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5704 {
5705         struct drm_device *dev = crtc->base.dev;
5706         struct drm_i915_private *dev_priv = dev->dev_private;
5707         int refclk;
5708
5709         if (IS_VALLEYVIEW(dev)) {
5710                 refclk = 100000;
5711         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5712             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5713                 refclk = dev_priv->vbt.lvds_ssc_freq;
5714                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5715         } else if (!IS_GEN2(dev)) {
5716                 refclk = 96000;
5717         } else {
5718                 refclk = 48000;
5719         }
5720
5721         return refclk;
5722 }
5723
5724 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5725 {
5726         return (1 << dpll->n) << 16 | dpll->m2;
5727 }
5728
5729 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5730 {
5731         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5732 }
5733
5734 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5735                                      intel_clock_t *reduced_clock)
5736 {
5737         struct drm_device *dev = crtc->base.dev;
5738         u32 fp, fp2 = 0;
5739
5740         if (IS_PINEVIEW(dev)) {
5741                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5742                 if (reduced_clock)
5743                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5744         } else {
5745                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5746                 if (reduced_clock)
5747                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5748         }
5749
5750         crtc->config.dpll_hw_state.fp0 = fp;
5751
5752         crtc->lowfreq_avail = false;
5753         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5754             reduced_clock && i915.powersave) {
5755                 crtc->config.dpll_hw_state.fp1 = fp2;
5756                 crtc->lowfreq_avail = true;
5757         } else {
5758                 crtc->config.dpll_hw_state.fp1 = fp;
5759         }
5760 }
5761
5762 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5763                 pipe)
5764 {
5765         u32 reg_val;
5766
5767         /*
5768          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5769          * and set it to a reasonable value instead.
5770          */
5771         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5772         reg_val &= 0xffffff00;
5773         reg_val |= 0x00000030;
5774         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5775
5776         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5777         reg_val &= 0x8cffffff;
5778         reg_val = 0x8c000000;
5779         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5780
5781         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5782         reg_val &= 0xffffff00;
5783         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5784
5785         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5786         reg_val &= 0x00ffffff;
5787         reg_val |= 0xb0000000;
5788         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5789 }
5790
5791 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5792                                          struct intel_link_m_n *m_n)
5793 {
5794         struct drm_device *dev = crtc->base.dev;
5795         struct drm_i915_private *dev_priv = dev->dev_private;
5796         int pipe = crtc->pipe;
5797
5798         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5799         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5800         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5801         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5802 }
5803
5804 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5805                                          struct intel_link_m_n *m_n,
5806                                          struct intel_link_m_n *m2_n2)
5807 {
5808         struct drm_device *dev = crtc->base.dev;
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         int pipe = crtc->pipe;
5811         enum transcoder transcoder = crtc->config.cpu_transcoder;
5812
5813         if (INTEL_INFO(dev)->gen >= 5) {
5814                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5815                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5816                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5817                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5818                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5819                  * for gen < 8) and if DRRS is supported (to make sure the
5820                  * registers are not unnecessarily accessed).
5821                  */
5822                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5823                         crtc->config.has_drrs) {
5824                         I915_WRITE(PIPE_DATA_M2(transcoder),
5825                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5826                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5827                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5828                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5829                 }
5830         } else {
5831                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5832                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5833                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5834                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5835         }
5836 }
5837
5838 void intel_dp_set_m_n(struct intel_crtc *crtc)
5839 {
5840         if (crtc->config.has_pch_encoder)
5841                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5842         else
5843                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5844                                                    &crtc->config.dp_m2_n2);
5845 }
5846
5847 static void vlv_update_pll(struct intel_crtc *crtc,
5848                            struct intel_crtc_config *pipe_config)
5849 {
5850         u32 dpll, dpll_md;
5851
5852         /*
5853          * Enable DPIO clock input. We should never disable the reference
5854          * clock for pipe B, since VGA hotplug / manual detection depends
5855          * on it.
5856          */
5857         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5858                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5859         /* We should never disable this, set it here for state tracking */
5860         if (crtc->pipe == PIPE_B)
5861                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5862         dpll |= DPLL_VCO_ENABLE;
5863         pipe_config->dpll_hw_state.dpll = dpll;
5864
5865         dpll_md = (pipe_config->pixel_multiplier - 1)
5866                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5867         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5868 }
5869
5870 static void vlv_prepare_pll(struct intel_crtc *crtc,
5871                             const struct intel_crtc_config *pipe_config)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         int pipe = crtc->pipe;
5876         u32 mdiv;
5877         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5878         u32 coreclk, reg_val;
5879
5880         mutex_lock(&dev_priv->dpio_lock);
5881
5882         bestn = pipe_config->dpll.n;
5883         bestm1 = pipe_config->dpll.m1;
5884         bestm2 = pipe_config->dpll.m2;
5885         bestp1 = pipe_config->dpll.p1;
5886         bestp2 = pipe_config->dpll.p2;
5887
5888         /* See eDP HDMI DPIO driver vbios notes doc */
5889
5890         /* PLL B needs special handling */
5891         if (pipe == PIPE_B)
5892                 vlv_pllb_recal_opamp(dev_priv, pipe);
5893
5894         /* Set up Tx target for periodic Rcomp update */
5895         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5896
5897         /* Disable target IRef on PLL */
5898         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5899         reg_val &= 0x00ffffff;
5900         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5901
5902         /* Disable fast lock */
5903         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5904
5905         /* Set idtafcrecal before PLL is enabled */
5906         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5907         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5908         mdiv |= ((bestn << DPIO_N_SHIFT));
5909         mdiv |= (1 << DPIO_K_SHIFT);
5910
5911         /*
5912          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5913          * but we don't support that).
5914          * Note: don't use the DAC post divider as it seems unstable.
5915          */
5916         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5917         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5918
5919         mdiv |= DPIO_ENABLE_CALIBRATION;
5920         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5921
5922         /* Set HBR and RBR LPF coefficients */
5923         if (pipe_config->port_clock == 162000 ||
5924             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5925             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5926                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5927                                  0x009f0003);
5928         else
5929                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5930                                  0x00d0000f);
5931
5932         if (crtc->config.has_dp_encoder) {
5933                 /* Use SSC source */
5934                 if (pipe == PIPE_A)
5935                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5936                                          0x0df40000);
5937                 else
5938                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5939                                          0x0df70000);
5940         } else { /* HDMI or VGA */
5941                 /* Use bend source */
5942                 if (pipe == PIPE_A)
5943                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5944                                          0x0df70000);
5945                 else
5946                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5947                                          0x0df40000);
5948         }
5949
5950         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5951         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5952         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5953             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5954                 coreclk |= 0x01000000;
5955         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5956
5957         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5958         mutex_unlock(&dev_priv->dpio_lock);
5959 }
5960
5961 static void chv_update_pll(struct intel_crtc *crtc,
5962                            struct intel_crtc_config *pipe_config)
5963 {
5964         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5965                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5966                 DPLL_VCO_ENABLE;
5967         if (crtc->pipe != PIPE_A)
5968                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5969
5970         pipe_config->dpll_hw_state.dpll_md =
5971                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5972 }
5973
5974 static void chv_prepare_pll(struct intel_crtc *crtc,
5975                             const struct intel_crtc_config *pipe_config)
5976 {
5977         struct drm_device *dev = crtc->base.dev;
5978         struct drm_i915_private *dev_priv = dev->dev_private;
5979         int pipe = crtc->pipe;
5980         int dpll_reg = DPLL(crtc->pipe);
5981         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5982         u32 loopfilter, intcoeff;
5983         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5984         int refclk;
5985
5986         bestn = pipe_config->dpll.n;
5987         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5988         bestm1 = pipe_config->dpll.m1;
5989         bestm2 = pipe_config->dpll.m2 >> 22;
5990         bestp1 = pipe_config->dpll.p1;
5991         bestp2 = pipe_config->dpll.p2;
5992
5993         /*
5994          * Enable Refclk and SSC
5995          */
5996         I915_WRITE(dpll_reg,
5997                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5998
5999         mutex_lock(&dev_priv->dpio_lock);
6000
6001         /* p1 and p2 divider */
6002         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6003                         5 << DPIO_CHV_S1_DIV_SHIFT |
6004                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6005                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6006                         1 << DPIO_CHV_K_DIV_SHIFT);
6007
6008         /* Feedback post-divider - m2 */
6009         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6010
6011         /* Feedback refclk divider - n and m1 */
6012         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6013                         DPIO_CHV_M1_DIV_BY_2 |
6014                         1 << DPIO_CHV_N_DIV_SHIFT);
6015
6016         /* M2 fraction division */
6017         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6018
6019         /* M2 fraction division enable */
6020         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6021                        DPIO_CHV_FRAC_DIV_EN |
6022                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6023
6024         /* Loop filter */
6025         refclk = i9xx_get_refclk(crtc, 0);
6026         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6027                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6028         if (refclk == 100000)
6029                 intcoeff = 11;
6030         else if (refclk == 38400)
6031                 intcoeff = 10;
6032         else
6033                 intcoeff = 9;
6034         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6035         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6036
6037         /* AFC Recal */
6038         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6039                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6040                         DPIO_AFC_RECAL);
6041
6042         mutex_unlock(&dev_priv->dpio_lock);
6043 }
6044
6045 /**
6046  * vlv_force_pll_on - forcibly enable just the PLL
6047  * @dev_priv: i915 private structure
6048  * @pipe: pipe PLL to enable
6049  * @dpll: PLL configuration
6050  *
6051  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6052  * in cases where we need the PLL enabled even when @pipe is not going to
6053  * be enabled.
6054  */
6055 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6056                       const struct dpll *dpll)
6057 {
6058         struct intel_crtc *crtc =
6059                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6060         struct intel_crtc_config pipe_config = {
6061                 .pixel_multiplier = 1,
6062                 .dpll = *dpll,
6063         };
6064
6065         if (IS_CHERRYVIEW(dev)) {
6066                 chv_update_pll(crtc, &pipe_config);
6067                 chv_prepare_pll(crtc, &pipe_config);
6068                 chv_enable_pll(crtc, &pipe_config);
6069         } else {
6070                 vlv_update_pll(crtc, &pipe_config);
6071                 vlv_prepare_pll(crtc, &pipe_config);
6072                 vlv_enable_pll(crtc, &pipe_config);
6073         }
6074 }
6075
6076 /**
6077  * vlv_force_pll_off - forcibly disable just the PLL
6078  * @dev_priv: i915 private structure
6079  * @pipe: pipe PLL to disable
6080  *
6081  * Disable the PLL for @pipe. To be used in cases where we need
6082  * the PLL enabled even when @pipe is not going to be enabled.
6083  */
6084 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6085 {
6086         if (IS_CHERRYVIEW(dev))
6087                 chv_disable_pll(to_i915(dev), pipe);
6088         else
6089                 vlv_disable_pll(to_i915(dev), pipe);
6090 }
6091
6092 static void i9xx_update_pll(struct intel_crtc *crtc,
6093                             intel_clock_t *reduced_clock,
6094                             int num_connectors)
6095 {
6096         struct drm_device *dev = crtc->base.dev;
6097         struct drm_i915_private *dev_priv = dev->dev_private;
6098         u32 dpll;
6099         bool is_sdvo;
6100         struct dpll *clock = &crtc->new_config->dpll;
6101
6102         i9xx_update_pll_dividers(crtc, reduced_clock);
6103
6104         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6105                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6106
6107         dpll = DPLL_VGA_MODE_DIS;
6108
6109         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6110                 dpll |= DPLLB_MODE_LVDS;
6111         else
6112                 dpll |= DPLLB_MODE_DAC_SERIAL;
6113
6114         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6115                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6116                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6117         }
6118
6119         if (is_sdvo)
6120                 dpll |= DPLL_SDVO_HIGH_SPEED;
6121
6122         if (crtc->new_config->has_dp_encoder)
6123                 dpll |= DPLL_SDVO_HIGH_SPEED;
6124
6125         /* compute bitmask from p1 value */
6126         if (IS_PINEVIEW(dev))
6127                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6128         else {
6129                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6130                 if (IS_G4X(dev) && reduced_clock)
6131                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6132         }
6133         switch (clock->p2) {
6134         case 5:
6135                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6136                 break;
6137         case 7:
6138                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6139                 break;
6140         case 10:
6141                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6142                 break;
6143         case 14:
6144                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6145                 break;
6146         }
6147         if (INTEL_INFO(dev)->gen >= 4)
6148                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6149
6150         if (crtc->new_config->sdvo_tv_clock)
6151                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6152         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6153                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6154                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6155         else
6156                 dpll |= PLL_REF_INPUT_DREFCLK;
6157
6158         dpll |= DPLL_VCO_ENABLE;
6159         crtc->new_config->dpll_hw_state.dpll = dpll;
6160
6161         if (INTEL_INFO(dev)->gen >= 4) {
6162                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6163                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6164                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6165         }
6166 }
6167
6168 static void i8xx_update_pll(struct intel_crtc *crtc,
6169                             intel_clock_t *reduced_clock,
6170                             int num_connectors)
6171 {
6172         struct drm_device *dev = crtc->base.dev;
6173         struct drm_i915_private *dev_priv = dev->dev_private;
6174         u32 dpll;
6175         struct dpll *clock = &crtc->new_config->dpll;
6176
6177         i9xx_update_pll_dividers(crtc, reduced_clock);
6178
6179         dpll = DPLL_VGA_MODE_DIS;
6180
6181         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6182                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6183         } else {
6184                 if (clock->p1 == 2)
6185                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6186                 else
6187                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6188                 if (clock->p2 == 4)
6189                         dpll |= PLL_P2_DIVIDE_BY_4;
6190         }
6191
6192         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6193                 dpll |= DPLL_DVO_2X_MODE;
6194
6195         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6196                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6197                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6198         else
6199                 dpll |= PLL_REF_INPUT_DREFCLK;
6200
6201         dpll |= DPLL_VCO_ENABLE;
6202         crtc->new_config->dpll_hw_state.dpll = dpll;
6203 }
6204
6205 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6206 {
6207         struct drm_device *dev = intel_crtc->base.dev;
6208         struct drm_i915_private *dev_priv = dev->dev_private;
6209         enum pipe pipe = intel_crtc->pipe;
6210         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6211         struct drm_display_mode *adjusted_mode =
6212                 &intel_crtc->config.adjusted_mode;
6213         uint32_t crtc_vtotal, crtc_vblank_end;
6214         int vsyncshift = 0;
6215
6216         /* We need to be careful not to changed the adjusted mode, for otherwise
6217          * the hw state checker will get angry at the mismatch. */
6218         crtc_vtotal = adjusted_mode->crtc_vtotal;
6219         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6220
6221         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6222                 /* the chip adds 2 halflines automatically */
6223                 crtc_vtotal -= 1;
6224                 crtc_vblank_end -= 1;
6225
6226                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6227                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6228                 else
6229                         vsyncshift = adjusted_mode->crtc_hsync_start -
6230                                 adjusted_mode->crtc_htotal / 2;
6231                 if (vsyncshift < 0)
6232                         vsyncshift += adjusted_mode->crtc_htotal;
6233         }
6234
6235         if (INTEL_INFO(dev)->gen > 3)
6236                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6237
6238         I915_WRITE(HTOTAL(cpu_transcoder),
6239                    (adjusted_mode->crtc_hdisplay - 1) |
6240                    ((adjusted_mode->crtc_htotal - 1) << 16));
6241         I915_WRITE(HBLANK(cpu_transcoder),
6242                    (adjusted_mode->crtc_hblank_start - 1) |
6243                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6244         I915_WRITE(HSYNC(cpu_transcoder),
6245                    (adjusted_mode->crtc_hsync_start - 1) |
6246                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6247
6248         I915_WRITE(VTOTAL(cpu_transcoder),
6249                    (adjusted_mode->crtc_vdisplay - 1) |
6250                    ((crtc_vtotal - 1) << 16));
6251         I915_WRITE(VBLANK(cpu_transcoder),
6252                    (adjusted_mode->crtc_vblank_start - 1) |
6253                    ((crtc_vblank_end - 1) << 16));
6254         I915_WRITE(VSYNC(cpu_transcoder),
6255                    (adjusted_mode->crtc_vsync_start - 1) |
6256                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6257
6258         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6259          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6260          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6261          * bits. */
6262         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6263             (pipe == PIPE_B || pipe == PIPE_C))
6264                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6265
6266         /* pipesrc controls the size that is scaled from, which should
6267          * always be the user's requested size.
6268          */
6269         I915_WRITE(PIPESRC(pipe),
6270                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6271                    (intel_crtc->config.pipe_src_h - 1));
6272 }
6273
6274 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6275                                    struct intel_crtc_config *pipe_config)
6276 {
6277         struct drm_device *dev = crtc->base.dev;
6278         struct drm_i915_private *dev_priv = dev->dev_private;
6279         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6280         uint32_t tmp;
6281
6282         tmp = I915_READ(HTOTAL(cpu_transcoder));
6283         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6284         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6285         tmp = I915_READ(HBLANK(cpu_transcoder));
6286         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6287         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6288         tmp = I915_READ(HSYNC(cpu_transcoder));
6289         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6290         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6291
6292         tmp = I915_READ(VTOTAL(cpu_transcoder));
6293         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6294         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6295         tmp = I915_READ(VBLANK(cpu_transcoder));
6296         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6297         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6298         tmp = I915_READ(VSYNC(cpu_transcoder));
6299         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6300         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6301
6302         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6303                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6304                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6305                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6306         }
6307
6308         tmp = I915_READ(PIPESRC(crtc->pipe));
6309         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6310         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6311
6312         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6313         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6314 }
6315
6316 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6317                                  struct intel_crtc_config *pipe_config)
6318 {
6319         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6320         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6321         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6322         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6323
6324         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6325         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6326         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6327         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6328
6329         mode->flags = pipe_config->adjusted_mode.flags;
6330
6331         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6332         mode->flags |= pipe_config->adjusted_mode.flags;
6333 }
6334
6335 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6336 {
6337         struct drm_device *dev = intel_crtc->base.dev;
6338         struct drm_i915_private *dev_priv = dev->dev_private;
6339         uint32_t pipeconf;
6340
6341         pipeconf = 0;
6342
6343         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6344             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6345                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6346
6347         if (intel_crtc->config.double_wide)
6348                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6349
6350         /* only g4x and later have fancy bpc/dither controls */
6351         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6352                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6353                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6354                         pipeconf |= PIPECONF_DITHER_EN |
6355                                     PIPECONF_DITHER_TYPE_SP;
6356
6357                 switch (intel_crtc->config.pipe_bpp) {
6358                 case 18:
6359                         pipeconf |= PIPECONF_6BPC;
6360                         break;
6361                 case 24:
6362                         pipeconf |= PIPECONF_8BPC;
6363                         break;
6364                 case 30:
6365                         pipeconf |= PIPECONF_10BPC;
6366                         break;
6367                 default:
6368                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6369                         BUG();
6370                 }
6371         }
6372
6373         if (HAS_PIPE_CXSR(dev)) {
6374                 if (intel_crtc->lowfreq_avail) {
6375                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6376                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6377                 } else {
6378                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6379                 }
6380         }
6381
6382         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6383                 if (INTEL_INFO(dev)->gen < 4 ||
6384                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6385                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6386                 else
6387                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6388         } else
6389                 pipeconf |= PIPECONF_PROGRESSIVE;
6390
6391         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6392                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6393
6394         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6395         POSTING_READ(PIPECONF(intel_crtc->pipe));
6396 }
6397
6398 static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
6399                               int x, int y,
6400                               struct drm_framebuffer *fb)
6401 {
6402         struct drm_device *dev = crtc->base.dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         int refclk, num_connectors = 0;
6405         intel_clock_t clock, reduced_clock;
6406         bool ok, has_reduced_clock = false;
6407         bool is_lvds = false, is_dsi = false;
6408         struct intel_encoder *encoder;
6409         const intel_limit_t *limit;
6410
6411         for_each_intel_encoder(dev, encoder) {
6412                 if (encoder->new_crtc != crtc)
6413                         continue;
6414
6415                 switch (encoder->type) {
6416                 case INTEL_OUTPUT_LVDS:
6417                         is_lvds = true;
6418                         break;
6419                 case INTEL_OUTPUT_DSI:
6420                         is_dsi = true;
6421                         break;
6422                 default:
6423                         break;
6424                 }
6425
6426                 num_connectors++;
6427         }
6428
6429         if (is_dsi)
6430                 return 0;
6431
6432         if (!crtc->new_config->clock_set) {
6433                 refclk = i9xx_get_refclk(crtc, num_connectors);
6434
6435                 /*
6436                  * Returns a set of divisors for the desired target clock with
6437                  * the given refclk, or FALSE.  The returned values represent
6438                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6439                  * 2) / p1 / p2.
6440                  */
6441                 limit = intel_limit(crtc, refclk);
6442                 ok = dev_priv->display.find_dpll(limit, crtc,
6443                                                  crtc->new_config->port_clock,
6444                                                  refclk, NULL, &clock);
6445                 if (!ok) {
6446                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6447                         return -EINVAL;
6448                 }
6449
6450                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6451                         /*
6452                          * Ensure we match the reduced clock's P to the target
6453                          * clock.  If the clocks don't match, we can't switch
6454                          * the display clock by using the FP0/FP1. In such case
6455                          * we will disable the LVDS downclock feature.
6456                          */
6457                         has_reduced_clock =
6458                                 dev_priv->display.find_dpll(limit, crtc,
6459                                                             dev_priv->lvds_downclock,
6460                                                             refclk, &clock,
6461                                                             &reduced_clock);
6462                 }
6463                 /* Compat-code for transition, will disappear. */
6464                 crtc->new_config->dpll.n = clock.n;
6465                 crtc->new_config->dpll.m1 = clock.m1;
6466                 crtc->new_config->dpll.m2 = clock.m2;
6467                 crtc->new_config->dpll.p1 = clock.p1;
6468                 crtc->new_config->dpll.p2 = clock.p2;
6469         }
6470
6471         if (IS_GEN2(dev)) {
6472                 i8xx_update_pll(crtc,
6473                                 has_reduced_clock ? &reduced_clock : NULL,
6474                                 num_connectors);
6475         } else if (IS_CHERRYVIEW(dev)) {
6476                 chv_update_pll(crtc, crtc->new_config);
6477         } else if (IS_VALLEYVIEW(dev)) {
6478                 vlv_update_pll(crtc, crtc->new_config);
6479         } else {
6480                 i9xx_update_pll(crtc,
6481                                 has_reduced_clock ? &reduced_clock : NULL,
6482                                 num_connectors);
6483         }
6484
6485         return 0;
6486 }
6487
6488 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6489                                  struct intel_crtc_config *pipe_config)
6490 {
6491         struct drm_device *dev = crtc->base.dev;
6492         struct drm_i915_private *dev_priv = dev->dev_private;
6493         uint32_t tmp;
6494
6495         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6496                 return;
6497
6498         tmp = I915_READ(PFIT_CONTROL);
6499         if (!(tmp & PFIT_ENABLE))
6500                 return;
6501
6502         /* Check whether the pfit is attached to our pipe. */
6503         if (INTEL_INFO(dev)->gen < 4) {
6504                 if (crtc->pipe != PIPE_B)
6505                         return;
6506         } else {
6507                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6508                         return;
6509         }
6510
6511         pipe_config->gmch_pfit.control = tmp;
6512         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6513         if (INTEL_INFO(dev)->gen < 5)
6514                 pipe_config->gmch_pfit.lvds_border_bits =
6515                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6516 }
6517
6518 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6519                                struct intel_crtc_config *pipe_config)
6520 {
6521         struct drm_device *dev = crtc->base.dev;
6522         struct drm_i915_private *dev_priv = dev->dev_private;
6523         int pipe = pipe_config->cpu_transcoder;
6524         intel_clock_t clock;
6525         u32 mdiv;
6526         int refclk = 100000;
6527
6528         /* In case of MIPI DPLL will not even be used */
6529         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6530                 return;
6531
6532         mutex_lock(&dev_priv->dpio_lock);
6533         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6534         mutex_unlock(&dev_priv->dpio_lock);
6535
6536         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6537         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6538         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6539         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6540         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6541
6542         vlv_clock(refclk, &clock);
6543
6544         /* clock.dot is the fast clock */
6545         pipe_config->port_clock = clock.dot / 5;
6546 }
6547
6548 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6549                                   struct intel_plane_config *plane_config)
6550 {
6551         struct drm_device *dev = crtc->base.dev;
6552         struct drm_i915_private *dev_priv = dev->dev_private;
6553         u32 val, base, offset;
6554         int pipe = crtc->pipe, plane = crtc->plane;
6555         int fourcc, pixel_format;
6556         int aligned_height;
6557
6558         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6559         if (!crtc->base.primary->fb) {
6560                 DRM_DEBUG_KMS("failed to alloc fb\n");
6561                 return;
6562         }
6563
6564         val = I915_READ(DSPCNTR(plane));
6565
6566         if (INTEL_INFO(dev)->gen >= 4)
6567                 if (val & DISPPLANE_TILED)
6568                         plane_config->tiled = true;
6569
6570         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6571         fourcc = intel_format_to_fourcc(pixel_format);
6572         crtc->base.primary->fb->pixel_format = fourcc;
6573         crtc->base.primary->fb->bits_per_pixel =
6574                 drm_format_plane_cpp(fourcc, 0) * 8;
6575
6576         if (INTEL_INFO(dev)->gen >= 4) {
6577                 if (plane_config->tiled)
6578                         offset = I915_READ(DSPTILEOFF(plane));
6579                 else
6580                         offset = I915_READ(DSPLINOFF(plane));
6581                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6582         } else {
6583                 base = I915_READ(DSPADDR(plane));
6584         }
6585         plane_config->base = base;
6586
6587         val = I915_READ(PIPESRC(pipe));
6588         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6589         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6590
6591         val = I915_READ(DSPSTRIDE(pipe));
6592         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6593
6594         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6595                                             plane_config->tiled);
6596
6597         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6598                                         aligned_height);
6599
6600         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6601                       pipe, plane, crtc->base.primary->fb->width,
6602                       crtc->base.primary->fb->height,
6603                       crtc->base.primary->fb->bits_per_pixel, base,
6604                       crtc->base.primary->fb->pitches[0],
6605                       plane_config->size);
6606
6607 }
6608
6609 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6610                                struct intel_crtc_config *pipe_config)
6611 {
6612         struct drm_device *dev = crtc->base.dev;
6613         struct drm_i915_private *dev_priv = dev->dev_private;
6614         int pipe = pipe_config->cpu_transcoder;
6615         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6616         intel_clock_t clock;
6617         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6618         int refclk = 100000;
6619
6620         mutex_lock(&dev_priv->dpio_lock);
6621         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6622         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6623         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6624         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6625         mutex_unlock(&dev_priv->dpio_lock);
6626
6627         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6628         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6629         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6630         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6631         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6632
6633         chv_clock(refclk, &clock);
6634
6635         /* clock.dot is the fast clock */
6636         pipe_config->port_clock = clock.dot / 5;
6637 }
6638
6639 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6640                                  struct intel_crtc_config *pipe_config)
6641 {
6642         struct drm_device *dev = crtc->base.dev;
6643         struct drm_i915_private *dev_priv = dev->dev_private;
6644         uint32_t tmp;
6645
6646         if (!intel_display_power_is_enabled(dev_priv,
6647                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6648                 return false;
6649
6650         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6651         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6652
6653         tmp = I915_READ(PIPECONF(crtc->pipe));
6654         if (!(tmp & PIPECONF_ENABLE))
6655                 return false;
6656
6657         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6658                 switch (tmp & PIPECONF_BPC_MASK) {
6659                 case PIPECONF_6BPC:
6660                         pipe_config->pipe_bpp = 18;
6661                         break;
6662                 case PIPECONF_8BPC:
6663                         pipe_config->pipe_bpp = 24;
6664                         break;
6665                 case PIPECONF_10BPC:
6666                         pipe_config->pipe_bpp = 30;
6667                         break;
6668                 default:
6669                         break;
6670                 }
6671         }
6672
6673         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6674                 pipe_config->limited_color_range = true;
6675
6676         if (INTEL_INFO(dev)->gen < 4)
6677                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6678
6679         intel_get_pipe_timings(crtc, pipe_config);
6680
6681         i9xx_get_pfit_config(crtc, pipe_config);
6682
6683         if (INTEL_INFO(dev)->gen >= 4) {
6684                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6685                 pipe_config->pixel_multiplier =
6686                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6687                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6688                 pipe_config->dpll_hw_state.dpll_md = tmp;
6689         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6690                 tmp = I915_READ(DPLL(crtc->pipe));
6691                 pipe_config->pixel_multiplier =
6692                         ((tmp & SDVO_MULTIPLIER_MASK)
6693                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6694         } else {
6695                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6696                  * port and will be fixed up in the encoder->get_config
6697                  * function. */
6698                 pipe_config->pixel_multiplier = 1;
6699         }
6700         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6701         if (!IS_VALLEYVIEW(dev)) {
6702                 /*
6703                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6704                  * on 830. Filter it out here so that we don't
6705                  * report errors due to that.
6706                  */
6707                 if (IS_I830(dev))
6708                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6709
6710                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6711                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6712         } else {
6713                 /* Mask out read-only status bits. */
6714                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6715                                                      DPLL_PORTC_READY_MASK |
6716                                                      DPLL_PORTB_READY_MASK);
6717         }
6718
6719         if (IS_CHERRYVIEW(dev))
6720                 chv_crtc_clock_get(crtc, pipe_config);
6721         else if (IS_VALLEYVIEW(dev))
6722                 vlv_crtc_clock_get(crtc, pipe_config);
6723         else
6724                 i9xx_crtc_clock_get(crtc, pipe_config);
6725
6726         return true;
6727 }
6728
6729 static void ironlake_init_pch_refclk(struct drm_device *dev)
6730 {
6731         struct drm_i915_private *dev_priv = dev->dev_private;
6732         struct intel_encoder *encoder;
6733         u32 val, final;
6734         bool has_lvds = false;
6735         bool has_cpu_edp = false;
6736         bool has_panel = false;
6737         bool has_ck505 = false;
6738         bool can_ssc = false;
6739
6740         /* We need to take the global config into account */
6741         for_each_intel_encoder(dev, encoder) {
6742                 switch (encoder->type) {
6743                 case INTEL_OUTPUT_LVDS:
6744                         has_panel = true;
6745                         has_lvds = true;
6746                         break;
6747                 case INTEL_OUTPUT_EDP:
6748                         has_panel = true;
6749                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6750                                 has_cpu_edp = true;
6751                         break;
6752                 default:
6753                         break;
6754                 }
6755         }
6756
6757         if (HAS_PCH_IBX(dev)) {
6758                 has_ck505 = dev_priv->vbt.display_clock_mode;
6759                 can_ssc = has_ck505;
6760         } else {
6761                 has_ck505 = false;
6762                 can_ssc = true;
6763         }
6764
6765         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6766                       has_panel, has_lvds, has_ck505);
6767
6768         /* Ironlake: try to setup display ref clock before DPLL
6769          * enabling. This is only under driver's control after
6770          * PCH B stepping, previous chipset stepping should be
6771          * ignoring this setting.
6772          */
6773         val = I915_READ(PCH_DREF_CONTROL);
6774
6775         /* As we must carefully and slowly disable/enable each source in turn,
6776          * compute the final state we want first and check if we need to
6777          * make any changes at all.
6778          */
6779         final = val;
6780         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6781         if (has_ck505)
6782                 final |= DREF_NONSPREAD_CK505_ENABLE;
6783         else
6784                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6785
6786         final &= ~DREF_SSC_SOURCE_MASK;
6787         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6788         final &= ~DREF_SSC1_ENABLE;
6789
6790         if (has_panel) {
6791                 final |= DREF_SSC_SOURCE_ENABLE;
6792
6793                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6794                         final |= DREF_SSC1_ENABLE;
6795
6796                 if (has_cpu_edp) {
6797                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6798                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6799                         else
6800                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6801                 } else
6802                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6803         } else {
6804                 final |= DREF_SSC_SOURCE_DISABLE;
6805                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6806         }
6807
6808         if (final == val)
6809                 return;
6810
6811         /* Always enable nonspread source */
6812         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6813
6814         if (has_ck505)
6815                 val |= DREF_NONSPREAD_CK505_ENABLE;
6816         else
6817                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6818
6819         if (has_panel) {
6820                 val &= ~DREF_SSC_SOURCE_MASK;
6821                 val |= DREF_SSC_SOURCE_ENABLE;
6822
6823                 /* SSC must be turned on before enabling the CPU output  */
6824                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6825                         DRM_DEBUG_KMS("Using SSC on panel\n");
6826                         val |= DREF_SSC1_ENABLE;
6827                 } else
6828                         val &= ~DREF_SSC1_ENABLE;
6829
6830                 /* Get SSC going before enabling the outputs */
6831                 I915_WRITE(PCH_DREF_CONTROL, val);
6832                 POSTING_READ(PCH_DREF_CONTROL);
6833                 udelay(200);
6834
6835                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6836
6837                 /* Enable CPU source on CPU attached eDP */
6838                 if (has_cpu_edp) {
6839                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6840                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6841                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6842                         } else
6843                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6844                 } else
6845                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6846
6847                 I915_WRITE(PCH_DREF_CONTROL, val);
6848                 POSTING_READ(PCH_DREF_CONTROL);
6849                 udelay(200);
6850         } else {
6851                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6852
6853                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6854
6855                 /* Turn off CPU output */
6856                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6857
6858                 I915_WRITE(PCH_DREF_CONTROL, val);
6859                 POSTING_READ(PCH_DREF_CONTROL);
6860                 udelay(200);
6861
6862                 /* Turn off the SSC source */
6863                 val &= ~DREF_SSC_SOURCE_MASK;
6864                 val |= DREF_SSC_SOURCE_DISABLE;
6865
6866                 /* Turn off SSC1 */
6867                 val &= ~DREF_SSC1_ENABLE;
6868
6869                 I915_WRITE(PCH_DREF_CONTROL, val);
6870                 POSTING_READ(PCH_DREF_CONTROL);
6871                 udelay(200);
6872         }
6873
6874         BUG_ON(val != final);
6875 }
6876
6877 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6878 {
6879         uint32_t tmp;
6880
6881         tmp = I915_READ(SOUTH_CHICKEN2);
6882         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6883         I915_WRITE(SOUTH_CHICKEN2, tmp);
6884
6885         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6886                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6887                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6888
6889         tmp = I915_READ(SOUTH_CHICKEN2);
6890         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6891         I915_WRITE(SOUTH_CHICKEN2, tmp);
6892
6893         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6894                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6895                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6896 }
6897
6898 /* WaMPhyProgramming:hsw */
6899 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6900 {
6901         uint32_t tmp;
6902
6903         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6904         tmp &= ~(0xFF << 24);
6905         tmp |= (0x12 << 24);
6906         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6907
6908         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6909         tmp |= (1 << 11);
6910         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6911
6912         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6913         tmp |= (1 << 11);
6914         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6915
6916         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6917         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6918         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6919
6920         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6921         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6922         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6923
6924         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6925         tmp &= ~(7 << 13);
6926         tmp |= (5 << 13);
6927         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6928
6929         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6930         tmp &= ~(7 << 13);
6931         tmp |= (5 << 13);
6932         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6933
6934         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6935         tmp &= ~0xFF;
6936         tmp |= 0x1C;
6937         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6938
6939         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6940         tmp &= ~0xFF;
6941         tmp |= 0x1C;
6942         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6943
6944         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6945         tmp &= ~(0xFF << 16);
6946         tmp |= (0x1C << 16);
6947         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6948
6949         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6950         tmp &= ~(0xFF << 16);
6951         tmp |= (0x1C << 16);
6952         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6953
6954         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6955         tmp |= (1 << 27);
6956         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6957
6958         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6959         tmp |= (1 << 27);
6960         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6961
6962         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6963         tmp &= ~(0xF << 28);
6964         tmp |= (4 << 28);
6965         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6966
6967         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6968         tmp &= ~(0xF << 28);
6969         tmp |= (4 << 28);
6970         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6971 }
6972
6973 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6974  * Programming" based on the parameters passed:
6975  * - Sequence to enable CLKOUT_DP
6976  * - Sequence to enable CLKOUT_DP without spread
6977  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6978  */
6979 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6980                                  bool with_fdi)
6981 {
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983         uint32_t reg, tmp;
6984
6985         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6986                 with_spread = true;
6987         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6988                  with_fdi, "LP PCH doesn't have FDI\n"))
6989                 with_fdi = false;
6990
6991         mutex_lock(&dev_priv->dpio_lock);
6992
6993         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994         tmp &= ~SBI_SSCCTL_DISABLE;
6995         tmp |= SBI_SSCCTL_PATHALT;
6996         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6997
6998         udelay(24);
6999
7000         if (with_spread) {
7001                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7002                 tmp &= ~SBI_SSCCTL_PATHALT;
7003                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7004
7005                 if (with_fdi) {
7006                         lpt_reset_fdi_mphy(dev_priv);
7007                         lpt_program_fdi_mphy(dev_priv);
7008                 }
7009         }
7010
7011         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7012                SBI_GEN0 : SBI_DBUFF0;
7013         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7014         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7015         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7016
7017         mutex_unlock(&dev_priv->dpio_lock);
7018 }
7019
7020 /* Sequence to disable CLKOUT_DP */
7021 static void lpt_disable_clkout_dp(struct drm_device *dev)
7022 {
7023         struct drm_i915_private *dev_priv = dev->dev_private;
7024         uint32_t reg, tmp;
7025
7026         mutex_lock(&dev_priv->dpio_lock);
7027
7028         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7029                SBI_GEN0 : SBI_DBUFF0;
7030         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7031         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7032         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7033
7034         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7035         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7036                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7037                         tmp |= SBI_SSCCTL_PATHALT;
7038                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7039                         udelay(32);
7040                 }
7041                 tmp |= SBI_SSCCTL_DISABLE;
7042                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7043         }
7044
7045         mutex_unlock(&dev_priv->dpio_lock);
7046 }
7047
7048 static void lpt_init_pch_refclk(struct drm_device *dev)
7049 {
7050         struct intel_encoder *encoder;
7051         bool has_vga = false;
7052
7053         for_each_intel_encoder(dev, encoder) {
7054                 switch (encoder->type) {
7055                 case INTEL_OUTPUT_ANALOG:
7056                         has_vga = true;
7057                         break;
7058                 default:
7059                         break;
7060                 }
7061         }
7062
7063         if (has_vga)
7064                 lpt_enable_clkout_dp(dev, true, true);
7065         else
7066                 lpt_disable_clkout_dp(dev);
7067 }
7068
7069 /*
7070  * Initialize reference clocks when the driver loads
7071  */
7072 void intel_init_pch_refclk(struct drm_device *dev)
7073 {
7074         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7075                 ironlake_init_pch_refclk(dev);
7076         else if (HAS_PCH_LPT(dev))
7077                 lpt_init_pch_refclk(dev);
7078 }
7079
7080 static int ironlake_get_refclk(struct drm_crtc *crtc)
7081 {
7082         struct drm_device *dev = crtc->dev;
7083         struct drm_i915_private *dev_priv = dev->dev_private;
7084         struct intel_encoder *encoder;
7085         int num_connectors = 0;
7086         bool is_lvds = false;
7087
7088         for_each_intel_encoder(dev, encoder) {
7089                 if (encoder->new_crtc != to_intel_crtc(crtc))
7090                         continue;
7091
7092                 switch (encoder->type) {
7093                 case INTEL_OUTPUT_LVDS:
7094                         is_lvds = true;
7095                         break;
7096                 default:
7097                         break;
7098                 }
7099                 num_connectors++;
7100         }
7101
7102         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7103                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7104                               dev_priv->vbt.lvds_ssc_freq);
7105                 return dev_priv->vbt.lvds_ssc_freq;
7106         }
7107
7108         return 120000;
7109 }
7110
7111 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7112 {
7113         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7115         int pipe = intel_crtc->pipe;
7116         uint32_t val;
7117
7118         val = 0;
7119
7120         switch (intel_crtc->config.pipe_bpp) {
7121         case 18:
7122                 val |= PIPECONF_6BPC;
7123                 break;
7124         case 24:
7125                 val |= PIPECONF_8BPC;
7126                 break;
7127         case 30:
7128                 val |= PIPECONF_10BPC;
7129                 break;
7130         case 36:
7131                 val |= PIPECONF_12BPC;
7132                 break;
7133         default:
7134                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7135                 BUG();
7136         }
7137
7138         if (intel_crtc->config.dither)
7139                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7140
7141         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7142                 val |= PIPECONF_INTERLACED_ILK;
7143         else
7144                 val |= PIPECONF_PROGRESSIVE;
7145
7146         if (intel_crtc->config.limited_color_range)
7147                 val |= PIPECONF_COLOR_RANGE_SELECT;
7148
7149         I915_WRITE(PIPECONF(pipe), val);
7150         POSTING_READ(PIPECONF(pipe));
7151 }
7152
7153 /*
7154  * Set up the pipe CSC unit.
7155  *
7156  * Currently only full range RGB to limited range RGB conversion
7157  * is supported, but eventually this should handle various
7158  * RGB<->YCbCr scenarios as well.
7159  */
7160 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7161 {
7162         struct drm_device *dev = crtc->dev;
7163         struct drm_i915_private *dev_priv = dev->dev_private;
7164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165         int pipe = intel_crtc->pipe;
7166         uint16_t coeff = 0x7800; /* 1.0 */
7167
7168         /*
7169          * TODO: Check what kind of values actually come out of the pipe
7170          * with these coeff/postoff values and adjust to get the best
7171          * accuracy. Perhaps we even need to take the bpc value into
7172          * consideration.
7173          */
7174
7175         if (intel_crtc->config.limited_color_range)
7176                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7177
7178         /*
7179          * GY/GU and RY/RU should be the other way around according
7180          * to BSpec, but reality doesn't agree. Just set them up in
7181          * a way that results in the correct picture.
7182          */
7183         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7184         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7185
7186         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7187         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7188
7189         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7190         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7191
7192         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7193         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7194         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7195
7196         if (INTEL_INFO(dev)->gen > 6) {
7197                 uint16_t postoff = 0;
7198
7199                 if (intel_crtc->config.limited_color_range)
7200                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7201
7202                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7203                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7204                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7205
7206                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7207         } else {
7208                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7209
7210                 if (intel_crtc->config.limited_color_range)
7211                         mode |= CSC_BLACK_SCREEN_OFFSET;
7212
7213                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7214         }
7215 }
7216
7217 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7218 {
7219         struct drm_device *dev = crtc->dev;
7220         struct drm_i915_private *dev_priv = dev->dev_private;
7221         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7222         enum pipe pipe = intel_crtc->pipe;
7223         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7224         uint32_t val;
7225
7226         val = 0;
7227
7228         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7229                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7230
7231         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7232                 val |= PIPECONF_INTERLACED_ILK;
7233         else
7234                 val |= PIPECONF_PROGRESSIVE;
7235
7236         I915_WRITE(PIPECONF(cpu_transcoder), val);
7237         POSTING_READ(PIPECONF(cpu_transcoder));
7238
7239         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7240         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7241
7242         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7243                 val = 0;
7244
7245                 switch (intel_crtc->config.pipe_bpp) {
7246                 case 18:
7247                         val |= PIPEMISC_DITHER_6_BPC;
7248                         break;
7249                 case 24:
7250                         val |= PIPEMISC_DITHER_8_BPC;
7251                         break;
7252                 case 30:
7253                         val |= PIPEMISC_DITHER_10_BPC;
7254                         break;
7255                 case 36:
7256                         val |= PIPEMISC_DITHER_12_BPC;
7257                         break;
7258                 default:
7259                         /* Case prevented by pipe_config_set_bpp. */
7260                         BUG();
7261                 }
7262
7263                 if (intel_crtc->config.dither)
7264                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7265
7266                 I915_WRITE(PIPEMISC(pipe), val);
7267         }
7268 }
7269
7270 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7271                                     intel_clock_t *clock,
7272                                     bool *has_reduced_clock,
7273                                     intel_clock_t *reduced_clock)
7274 {
7275         struct drm_device *dev = crtc->dev;
7276         struct drm_i915_private *dev_priv = dev->dev_private;
7277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7278         int refclk;
7279         const intel_limit_t *limit;
7280         bool ret, is_lvds = false;
7281
7282         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7283
7284         refclk = ironlake_get_refclk(crtc);
7285
7286         /*
7287          * Returns a set of divisors for the desired target clock with the given
7288          * refclk, or FALSE.  The returned values represent the clock equation:
7289          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7290          */
7291         limit = intel_limit(intel_crtc, refclk);
7292         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7293                                           intel_crtc->new_config->port_clock,
7294                                           refclk, NULL, clock);
7295         if (!ret)
7296                 return false;
7297
7298         if (is_lvds && dev_priv->lvds_downclock_avail) {
7299                 /*
7300                  * Ensure we match the reduced clock's P to the target clock.
7301                  * If the clocks don't match, we can't switch the display clock
7302                  * by using the FP0/FP1. In such case we will disable the LVDS
7303                  * downclock feature.
7304                 */
7305                 *has_reduced_clock =
7306                         dev_priv->display.find_dpll(limit, intel_crtc,
7307                                                     dev_priv->lvds_downclock,
7308                                                     refclk, clock,
7309                                                     reduced_clock);
7310         }
7311
7312         return true;
7313 }
7314
7315 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7316 {
7317         /*
7318          * Account for spread spectrum to avoid
7319          * oversubscribing the link. Max center spread
7320          * is 2.5%; use 5% for safety's sake.
7321          */
7322         u32 bps = target_clock * bpp * 21 / 20;
7323         return DIV_ROUND_UP(bps, link_bw * 8);
7324 }
7325
7326 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7327 {
7328         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7329 }
7330
7331 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7332                                       u32 *fp,
7333                                       intel_clock_t *reduced_clock, u32 *fp2)
7334 {
7335         struct drm_crtc *crtc = &intel_crtc->base;
7336         struct drm_device *dev = crtc->dev;
7337         struct drm_i915_private *dev_priv = dev->dev_private;
7338         struct intel_encoder *intel_encoder;
7339         uint32_t dpll;
7340         int factor, num_connectors = 0;
7341         bool is_lvds = false, is_sdvo = false;
7342
7343         for_each_intel_encoder(dev, intel_encoder) {
7344                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7345                         continue;
7346
7347                 switch (intel_encoder->type) {
7348                 case INTEL_OUTPUT_LVDS:
7349                         is_lvds = true;
7350                         break;
7351                 case INTEL_OUTPUT_SDVO:
7352                 case INTEL_OUTPUT_HDMI:
7353                         is_sdvo = true;
7354                         break;
7355                 default:
7356                         break;
7357                 }
7358
7359                 num_connectors++;
7360         }
7361
7362         /* Enable autotuning of the PLL clock (if permissible) */
7363         factor = 21;
7364         if (is_lvds) {
7365                 if ((intel_panel_use_ssc(dev_priv) &&
7366                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7367                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7368                         factor = 25;
7369         } else if (intel_crtc->new_config->sdvo_tv_clock)
7370                 factor = 20;
7371
7372         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7373                 *fp |= FP_CB_TUNE;
7374
7375         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7376                 *fp2 |= FP_CB_TUNE;
7377
7378         dpll = 0;
7379
7380         if (is_lvds)
7381                 dpll |= DPLLB_MODE_LVDS;
7382         else
7383                 dpll |= DPLLB_MODE_DAC_SERIAL;
7384
7385         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7386                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7387
7388         if (is_sdvo)
7389                 dpll |= DPLL_SDVO_HIGH_SPEED;
7390         if (intel_crtc->new_config->has_dp_encoder)
7391                 dpll |= DPLL_SDVO_HIGH_SPEED;
7392
7393         /* compute bitmask from p1 value */
7394         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7395         /* also FPA1 */
7396         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7397
7398         switch (intel_crtc->new_config->dpll.p2) {
7399         case 5:
7400                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7401                 break;
7402         case 7:
7403                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7404                 break;
7405         case 10:
7406                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7407                 break;
7408         case 14:
7409                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7410                 break;
7411         }
7412
7413         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7414                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7415         else
7416                 dpll |= PLL_REF_INPUT_DREFCLK;
7417
7418         return dpll | DPLL_VCO_ENABLE;
7419 }
7420
7421 static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7422                                   int x, int y,
7423                                   struct drm_framebuffer *fb)
7424 {
7425         struct drm_device *dev = crtc->base.dev;
7426         intel_clock_t clock, reduced_clock;
7427         u32 dpll = 0, fp = 0, fp2 = 0;
7428         bool ok, has_reduced_clock = false;
7429         bool is_lvds = false;
7430         struct intel_shared_dpll *pll;
7431
7432         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7433
7434         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7435              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7436
7437         ok = ironlake_compute_clocks(&crtc->base, &clock,
7438                                      &has_reduced_clock, &reduced_clock);
7439         if (!ok && !crtc->new_config->clock_set) {
7440                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7441                 return -EINVAL;
7442         }
7443         /* Compat-code for transition, will disappear. */
7444         if (!crtc->new_config->clock_set) {
7445                 crtc->new_config->dpll.n = clock.n;
7446                 crtc->new_config->dpll.m1 = clock.m1;
7447                 crtc->new_config->dpll.m2 = clock.m2;
7448                 crtc->new_config->dpll.p1 = clock.p1;
7449                 crtc->new_config->dpll.p2 = clock.p2;
7450         }
7451
7452         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7453         if (crtc->new_config->has_pch_encoder) {
7454                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7455                 if (has_reduced_clock)
7456                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7457
7458                 dpll = ironlake_compute_dpll(crtc,
7459                                              &fp, &reduced_clock,
7460                                              has_reduced_clock ? &fp2 : NULL);
7461
7462                 crtc->new_config->dpll_hw_state.dpll = dpll;
7463                 crtc->new_config->dpll_hw_state.fp0 = fp;
7464                 if (has_reduced_clock)
7465                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7466                 else
7467                         crtc->new_config->dpll_hw_state.fp1 = fp;
7468
7469                 if (intel_crtc_to_shared_dpll(crtc))
7470                         intel_put_shared_dpll(crtc);
7471
7472                 pll = intel_get_shared_dpll(crtc);
7473                 if (pll == NULL) {
7474                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7475                                          pipe_name(crtc->pipe));
7476                         return -EINVAL;
7477                 }
7478         } else
7479                 intel_put_shared_dpll(crtc);
7480
7481         if (is_lvds && has_reduced_clock && i915.powersave)
7482                 crtc->lowfreq_avail = true;
7483         else
7484                 crtc->lowfreq_avail = false;
7485
7486         return 0;
7487 }
7488
7489 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7490                                          struct intel_link_m_n *m_n)
7491 {
7492         struct drm_device *dev = crtc->base.dev;
7493         struct drm_i915_private *dev_priv = dev->dev_private;
7494         enum pipe pipe = crtc->pipe;
7495
7496         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7497         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7498         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7499                 & ~TU_SIZE_MASK;
7500         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7501         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7502                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7503 }
7504
7505 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7506                                          enum transcoder transcoder,
7507                                          struct intel_link_m_n *m_n,
7508                                          struct intel_link_m_n *m2_n2)
7509 {
7510         struct drm_device *dev = crtc->base.dev;
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512         enum pipe pipe = crtc->pipe;
7513
7514         if (INTEL_INFO(dev)->gen >= 5) {
7515                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7516                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7517                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7518                         & ~TU_SIZE_MASK;
7519                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7520                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7521                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7523                  * gen < 8) and if DRRS is supported (to make sure the
7524                  * registers are not unnecessarily read).
7525                  */
7526                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7527                         crtc->config.has_drrs) {
7528                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7529                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7530                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7531                                         & ~TU_SIZE_MASK;
7532                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7533                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7534                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7535                 }
7536         } else {
7537                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7538                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7539                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7540                         & ~TU_SIZE_MASK;
7541                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7542                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7543                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7544         }
7545 }
7546
7547 void intel_dp_get_m_n(struct intel_crtc *crtc,
7548                       struct intel_crtc_config *pipe_config)
7549 {
7550         if (crtc->config.has_pch_encoder)
7551                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7552         else
7553                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7554                                              &pipe_config->dp_m_n,
7555                                              &pipe_config->dp_m2_n2);
7556 }
7557
7558 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7559                                         struct intel_crtc_config *pipe_config)
7560 {
7561         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7562                                      &pipe_config->fdi_m_n, NULL);
7563 }
7564
7565 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7566                                      struct intel_crtc_config *pipe_config)
7567 {
7568         struct drm_device *dev = crtc->base.dev;
7569         struct drm_i915_private *dev_priv = dev->dev_private;
7570         uint32_t tmp;
7571
7572         tmp = I915_READ(PF_CTL(crtc->pipe));
7573
7574         if (tmp & PF_ENABLE) {
7575                 pipe_config->pch_pfit.enabled = true;
7576                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7577                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7578
7579                 /* We currently do not free assignements of panel fitters on
7580                  * ivb/hsw (since we don't use the higher upscaling modes which
7581                  * differentiates them) so just WARN about this case for now. */
7582                 if (IS_GEN7(dev)) {
7583                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7584                                 PF_PIPE_SEL_IVB(crtc->pipe));
7585                 }
7586         }
7587 }
7588
7589 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7590                                       struct intel_plane_config *plane_config)
7591 {
7592         struct drm_device *dev = crtc->base.dev;
7593         struct drm_i915_private *dev_priv = dev->dev_private;
7594         u32 val, base, offset;
7595         int pipe = crtc->pipe, plane = crtc->plane;
7596         int fourcc, pixel_format;
7597         int aligned_height;
7598
7599         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7600         if (!crtc->base.primary->fb) {
7601                 DRM_DEBUG_KMS("failed to alloc fb\n");
7602                 return;
7603         }
7604
7605         val = I915_READ(DSPCNTR(plane));
7606
7607         if (INTEL_INFO(dev)->gen >= 4)
7608                 if (val & DISPPLANE_TILED)
7609                         plane_config->tiled = true;
7610
7611         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7612         fourcc = intel_format_to_fourcc(pixel_format);
7613         crtc->base.primary->fb->pixel_format = fourcc;
7614         crtc->base.primary->fb->bits_per_pixel =
7615                 drm_format_plane_cpp(fourcc, 0) * 8;
7616
7617         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7618         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7619                 offset = I915_READ(DSPOFFSET(plane));
7620         } else {
7621                 if (plane_config->tiled)
7622                         offset = I915_READ(DSPTILEOFF(plane));
7623                 else
7624                         offset = I915_READ(DSPLINOFF(plane));
7625         }
7626         plane_config->base = base;
7627
7628         val = I915_READ(PIPESRC(pipe));
7629         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7630         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7631
7632         val = I915_READ(DSPSTRIDE(pipe));
7633         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7634
7635         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7636                                             plane_config->tiled);
7637
7638         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7639                                         aligned_height);
7640
7641         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7642                       pipe, plane, crtc->base.primary->fb->width,
7643                       crtc->base.primary->fb->height,
7644                       crtc->base.primary->fb->bits_per_pixel, base,
7645                       crtc->base.primary->fb->pitches[0],
7646                       plane_config->size);
7647 }
7648
7649 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7650                                      struct intel_crtc_config *pipe_config)
7651 {
7652         struct drm_device *dev = crtc->base.dev;
7653         struct drm_i915_private *dev_priv = dev->dev_private;
7654         uint32_t tmp;
7655
7656         if (!intel_display_power_is_enabled(dev_priv,
7657                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7658                 return false;
7659
7660         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7661         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7662
7663         tmp = I915_READ(PIPECONF(crtc->pipe));
7664         if (!(tmp & PIPECONF_ENABLE))
7665                 return false;
7666
7667         switch (tmp & PIPECONF_BPC_MASK) {
7668         case PIPECONF_6BPC:
7669                 pipe_config->pipe_bpp = 18;
7670                 break;
7671         case PIPECONF_8BPC:
7672                 pipe_config->pipe_bpp = 24;
7673                 break;
7674         case PIPECONF_10BPC:
7675                 pipe_config->pipe_bpp = 30;
7676                 break;
7677         case PIPECONF_12BPC:
7678                 pipe_config->pipe_bpp = 36;
7679                 break;
7680         default:
7681                 break;
7682         }
7683
7684         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7685                 pipe_config->limited_color_range = true;
7686
7687         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7688                 struct intel_shared_dpll *pll;
7689
7690                 pipe_config->has_pch_encoder = true;
7691
7692                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7693                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7694                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7695
7696                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7697
7698                 if (HAS_PCH_IBX(dev_priv->dev)) {
7699                         pipe_config->shared_dpll =
7700                                 (enum intel_dpll_id) crtc->pipe;
7701                 } else {
7702                         tmp = I915_READ(PCH_DPLL_SEL);
7703                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7704                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7705                         else
7706                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7707                 }
7708
7709                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7710
7711                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7712                                            &pipe_config->dpll_hw_state));
7713
7714                 tmp = pipe_config->dpll_hw_state.dpll;
7715                 pipe_config->pixel_multiplier =
7716                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7717                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7718
7719                 ironlake_pch_clock_get(crtc, pipe_config);
7720         } else {
7721                 pipe_config->pixel_multiplier = 1;
7722         }
7723
7724         intel_get_pipe_timings(crtc, pipe_config);
7725
7726         ironlake_get_pfit_config(crtc, pipe_config);
7727
7728         return true;
7729 }
7730
7731 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7732 {
7733         struct drm_device *dev = dev_priv->dev;
7734         struct intel_crtc *crtc;
7735
7736         for_each_intel_crtc(dev, crtc)
7737                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7738                      pipe_name(crtc->pipe));
7739
7740         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7741         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7742         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7743         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7744         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7745         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7746              "CPU PWM1 enabled\n");
7747         if (IS_HASWELL(dev))
7748                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7749                      "CPU PWM2 enabled\n");
7750         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7751              "PCH PWM1 enabled\n");
7752         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7753              "Utility pin enabled\n");
7754         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7755
7756         /*
7757          * In theory we can still leave IRQs enabled, as long as only the HPD
7758          * interrupts remain enabled. We used to check for that, but since it's
7759          * gen-specific and since we only disable LCPLL after we fully disable
7760          * the interrupts, the check below should be enough.
7761          */
7762         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7763 }
7764
7765 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7766 {
7767         struct drm_device *dev = dev_priv->dev;
7768
7769         if (IS_HASWELL(dev))
7770                 return I915_READ(D_COMP_HSW);
7771         else
7772                 return I915_READ(D_COMP_BDW);
7773 }
7774
7775 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7776 {
7777         struct drm_device *dev = dev_priv->dev;
7778
7779         if (IS_HASWELL(dev)) {
7780                 mutex_lock(&dev_priv->rps.hw_lock);
7781                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7782                                             val))
7783                         DRM_ERROR("Failed to write to D_COMP\n");
7784                 mutex_unlock(&dev_priv->rps.hw_lock);
7785         } else {
7786                 I915_WRITE(D_COMP_BDW, val);
7787                 POSTING_READ(D_COMP_BDW);
7788         }
7789 }
7790
7791 /*
7792  * This function implements pieces of two sequences from BSpec:
7793  * - Sequence for display software to disable LCPLL
7794  * - Sequence for display software to allow package C8+
7795  * The steps implemented here are just the steps that actually touch the LCPLL
7796  * register. Callers should take care of disabling all the display engine
7797  * functions, doing the mode unset, fixing interrupts, etc.
7798  */
7799 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7800                               bool switch_to_fclk, bool allow_power_down)
7801 {
7802         uint32_t val;
7803
7804         assert_can_disable_lcpll(dev_priv);
7805
7806         val = I915_READ(LCPLL_CTL);
7807
7808         if (switch_to_fclk) {
7809                 val |= LCPLL_CD_SOURCE_FCLK;
7810                 I915_WRITE(LCPLL_CTL, val);
7811
7812                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7813                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7814                         DRM_ERROR("Switching to FCLK failed\n");
7815
7816                 val = I915_READ(LCPLL_CTL);
7817         }
7818
7819         val |= LCPLL_PLL_DISABLE;
7820         I915_WRITE(LCPLL_CTL, val);
7821         POSTING_READ(LCPLL_CTL);
7822
7823         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7824                 DRM_ERROR("LCPLL still locked\n");
7825
7826         val = hsw_read_dcomp(dev_priv);
7827         val |= D_COMP_COMP_DISABLE;
7828         hsw_write_dcomp(dev_priv, val);
7829         ndelay(100);
7830
7831         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7832                      1))
7833                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7834
7835         if (allow_power_down) {
7836                 val = I915_READ(LCPLL_CTL);
7837                 val |= LCPLL_POWER_DOWN_ALLOW;
7838                 I915_WRITE(LCPLL_CTL, val);
7839                 POSTING_READ(LCPLL_CTL);
7840         }
7841 }
7842
7843 /*
7844  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7845  * source.
7846  */
7847 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7848 {
7849         uint32_t val;
7850
7851         val = I915_READ(LCPLL_CTL);
7852
7853         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7854                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7855                 return;
7856
7857         /*
7858          * Make sure we're not on PC8 state before disabling PC8, otherwise
7859          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7860          *
7861          * The other problem is that hsw_restore_lcpll() is called as part of
7862          * the runtime PM resume sequence, so we can't just call
7863          * gen6_gt_force_wake_get() because that function calls
7864          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7865          * while we are on the resume sequence. So to solve this problem we have
7866          * to call special forcewake code that doesn't touch runtime PM and
7867          * doesn't enable the forcewake delayed work.
7868          */
7869         spin_lock_irq(&dev_priv->uncore.lock);
7870         if (dev_priv->uncore.forcewake_count++ == 0)
7871                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7872         spin_unlock_irq(&dev_priv->uncore.lock);
7873
7874         if (val & LCPLL_POWER_DOWN_ALLOW) {
7875                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7876                 I915_WRITE(LCPLL_CTL, val);
7877                 POSTING_READ(LCPLL_CTL);
7878         }
7879
7880         val = hsw_read_dcomp(dev_priv);
7881         val |= D_COMP_COMP_FORCE;
7882         val &= ~D_COMP_COMP_DISABLE;
7883         hsw_write_dcomp(dev_priv, val);
7884
7885         val = I915_READ(LCPLL_CTL);
7886         val &= ~LCPLL_PLL_DISABLE;
7887         I915_WRITE(LCPLL_CTL, val);
7888
7889         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7890                 DRM_ERROR("LCPLL not locked yet\n");
7891
7892         if (val & LCPLL_CD_SOURCE_FCLK) {
7893                 val = I915_READ(LCPLL_CTL);
7894                 val &= ~LCPLL_CD_SOURCE_FCLK;
7895                 I915_WRITE(LCPLL_CTL, val);
7896
7897                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7898                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7899                         DRM_ERROR("Switching back to LCPLL failed\n");
7900         }
7901
7902         /* See the big comment above. */
7903         spin_lock_irq(&dev_priv->uncore.lock);
7904         if (--dev_priv->uncore.forcewake_count == 0)
7905                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7906         spin_unlock_irq(&dev_priv->uncore.lock);
7907 }
7908
7909 /*
7910  * Package states C8 and deeper are really deep PC states that can only be
7911  * reached when all the devices on the system allow it, so even if the graphics
7912  * device allows PC8+, it doesn't mean the system will actually get to these
7913  * states. Our driver only allows PC8+ when going into runtime PM.
7914  *
7915  * The requirements for PC8+ are that all the outputs are disabled, the power
7916  * well is disabled and most interrupts are disabled, and these are also
7917  * requirements for runtime PM. When these conditions are met, we manually do
7918  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7919  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7920  * hang the machine.
7921  *
7922  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7923  * the state of some registers, so when we come back from PC8+ we need to
7924  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7925  * need to take care of the registers kept by RC6. Notice that this happens even
7926  * if we don't put the device in PCI D3 state (which is what currently happens
7927  * because of the runtime PM support).
7928  *
7929  * For more, read "Display Sequences for Package C8" on the hardware
7930  * documentation.
7931  */
7932 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7933 {
7934         struct drm_device *dev = dev_priv->dev;
7935         uint32_t val;
7936
7937         DRM_DEBUG_KMS("Enabling package C8+\n");
7938
7939         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7940                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7941                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7942                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7943         }
7944
7945         lpt_disable_clkout_dp(dev);
7946         hsw_disable_lcpll(dev_priv, true, true);
7947 }
7948
7949 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7950 {
7951         struct drm_device *dev = dev_priv->dev;
7952         uint32_t val;
7953
7954         DRM_DEBUG_KMS("Disabling package C8+\n");
7955
7956         hsw_restore_lcpll(dev_priv);
7957         lpt_init_pch_refclk(dev);
7958
7959         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7960                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7961                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7962                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7963         }
7964
7965         intel_prepare_ddi(dev);
7966 }
7967
7968 static void snb_modeset_global_resources(struct drm_device *dev)
7969 {
7970         modeset_update_crtc_power_domains(dev);
7971 }
7972
7973 static void haswell_modeset_global_resources(struct drm_device *dev)
7974 {
7975         modeset_update_crtc_power_domains(dev);
7976 }
7977
7978 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7979 {
7980         if (!intel_ddi_pll_select(crtc))
7981                 return -EINVAL;
7982
7983         crtc->lowfreq_avail = false;
7984
7985         return 0;
7986 }
7987
7988 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7989                                 enum port port,
7990                                 struct intel_crtc_config *pipe_config)
7991 {
7992         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7993
7994         switch (pipe_config->ddi_pll_sel) {
7995         case PORT_CLK_SEL_WRPLL1:
7996                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7997                 break;
7998         case PORT_CLK_SEL_WRPLL2:
7999                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8000                 break;
8001         }
8002 }
8003
8004 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8005                                        struct intel_crtc_config *pipe_config)
8006 {
8007         struct drm_device *dev = crtc->base.dev;
8008         struct drm_i915_private *dev_priv = dev->dev_private;
8009         struct intel_shared_dpll *pll;
8010         enum port port;
8011         uint32_t tmp;
8012
8013         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8014
8015         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8016
8017         haswell_get_ddi_pll(dev_priv, port, pipe_config);
8018
8019         if (pipe_config->shared_dpll >= 0) {
8020                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8021
8022                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8023                                            &pipe_config->dpll_hw_state));
8024         }
8025
8026         /*
8027          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8028          * DDI E. So just check whether this pipe is wired to DDI E and whether
8029          * the PCH transcoder is on.
8030          */
8031         if (INTEL_INFO(dev)->gen < 9 &&
8032             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8033                 pipe_config->has_pch_encoder = true;
8034
8035                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8036                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8037                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8038
8039                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8040         }
8041 }
8042
8043 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8044                                     struct intel_crtc_config *pipe_config)
8045 {
8046         struct drm_device *dev = crtc->base.dev;
8047         struct drm_i915_private *dev_priv = dev->dev_private;
8048         enum intel_display_power_domain pfit_domain;
8049         uint32_t tmp;
8050
8051         if (!intel_display_power_is_enabled(dev_priv,
8052                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8053                 return false;
8054
8055         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8056         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8057
8058         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8059         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8060                 enum pipe trans_edp_pipe;
8061                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8062                 default:
8063                         WARN(1, "unknown pipe linked to edp transcoder\n");
8064                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8065                 case TRANS_DDI_EDP_INPUT_A_ON:
8066                         trans_edp_pipe = PIPE_A;
8067                         break;
8068                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8069                         trans_edp_pipe = PIPE_B;
8070                         break;
8071                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8072                         trans_edp_pipe = PIPE_C;
8073                         break;
8074                 }
8075
8076                 if (trans_edp_pipe == crtc->pipe)
8077                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8078         }
8079
8080         if (!intel_display_power_is_enabled(dev_priv,
8081                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8082                 return false;
8083
8084         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8085         if (!(tmp & PIPECONF_ENABLE))
8086                 return false;
8087
8088         haswell_get_ddi_port_state(crtc, pipe_config);
8089
8090         intel_get_pipe_timings(crtc, pipe_config);
8091
8092         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8093         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8094                 ironlake_get_pfit_config(crtc, pipe_config);
8095
8096         if (IS_HASWELL(dev))
8097                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8098                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8099
8100         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8101                 pipe_config->pixel_multiplier =
8102                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8103         } else {
8104                 pipe_config->pixel_multiplier = 1;
8105         }
8106
8107         return true;
8108 }
8109
8110 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8111 {
8112         struct drm_device *dev = crtc->dev;
8113         struct drm_i915_private *dev_priv = dev->dev_private;
8114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8115         uint32_t cntl = 0, size = 0;
8116
8117         if (base) {
8118                 unsigned int width = intel_crtc->cursor_width;
8119                 unsigned int height = intel_crtc->cursor_height;
8120                 unsigned int stride = roundup_pow_of_two(width) * 4;
8121
8122                 switch (stride) {
8123                 default:
8124                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8125                                   width, stride);
8126                         stride = 256;
8127                         /* fallthrough */
8128                 case 256:
8129                 case 512:
8130                 case 1024:
8131                 case 2048:
8132                         break;
8133                 }
8134
8135                 cntl |= CURSOR_ENABLE |
8136                         CURSOR_GAMMA_ENABLE |
8137                         CURSOR_FORMAT_ARGB |
8138                         CURSOR_STRIDE(stride);
8139
8140                 size = (height << 12) | width;
8141         }
8142
8143         if (intel_crtc->cursor_cntl != 0 &&
8144             (intel_crtc->cursor_base != base ||
8145              intel_crtc->cursor_size != size ||
8146              intel_crtc->cursor_cntl != cntl)) {
8147                 /* On these chipsets we can only modify the base/size/stride
8148                  * whilst the cursor is disabled.
8149                  */
8150                 I915_WRITE(_CURACNTR, 0);
8151                 POSTING_READ(_CURACNTR);
8152                 intel_crtc->cursor_cntl = 0;
8153         }
8154
8155         if (intel_crtc->cursor_base != base) {
8156                 I915_WRITE(_CURABASE, base);
8157                 intel_crtc->cursor_base = base;
8158         }
8159
8160         if (intel_crtc->cursor_size != size) {
8161                 I915_WRITE(CURSIZE, size);
8162                 intel_crtc->cursor_size = size;
8163         }
8164
8165         if (intel_crtc->cursor_cntl != cntl) {
8166                 I915_WRITE(_CURACNTR, cntl);
8167                 POSTING_READ(_CURACNTR);
8168                 intel_crtc->cursor_cntl = cntl;
8169         }
8170 }
8171
8172 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8173 {
8174         struct drm_device *dev = crtc->dev;
8175         struct drm_i915_private *dev_priv = dev->dev_private;
8176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8177         int pipe = intel_crtc->pipe;
8178         uint32_t cntl;
8179
8180         cntl = 0;
8181         if (base) {
8182                 cntl = MCURSOR_GAMMA_ENABLE;
8183                 switch (intel_crtc->cursor_width) {
8184                         case 64:
8185                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8186                                 break;
8187                         case 128:
8188                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8189                                 break;
8190                         case 256:
8191                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8192                                 break;
8193                         default:
8194                                 WARN_ON(1);
8195                                 return;
8196                 }
8197                 cntl |= pipe << 28; /* Connect to correct pipe */
8198
8199                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8200                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8201         }
8202
8203         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8204                 cntl |= CURSOR_ROTATE_180;
8205
8206         if (intel_crtc->cursor_cntl != cntl) {
8207                 I915_WRITE(CURCNTR(pipe), cntl);
8208                 POSTING_READ(CURCNTR(pipe));
8209                 intel_crtc->cursor_cntl = cntl;
8210         }
8211
8212         /* and commit changes on next vblank */
8213         I915_WRITE(CURBASE(pipe), base);
8214         POSTING_READ(CURBASE(pipe));
8215
8216         intel_crtc->cursor_base = base;
8217 }
8218
8219 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8220 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8221                                      bool on)
8222 {
8223         struct drm_device *dev = crtc->dev;
8224         struct drm_i915_private *dev_priv = dev->dev_private;
8225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8226         int pipe = intel_crtc->pipe;
8227         int x = crtc->cursor_x;
8228         int y = crtc->cursor_y;
8229         u32 base = 0, pos = 0;
8230
8231         if (on)
8232                 base = intel_crtc->cursor_addr;
8233
8234         if (x >= intel_crtc->config.pipe_src_w)
8235                 base = 0;
8236
8237         if (y >= intel_crtc->config.pipe_src_h)
8238                 base = 0;
8239
8240         if (x < 0) {
8241                 if (x + intel_crtc->cursor_width <= 0)
8242                         base = 0;
8243
8244                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8245                 x = -x;
8246         }
8247         pos |= x << CURSOR_X_SHIFT;
8248
8249         if (y < 0) {
8250                 if (y + intel_crtc->cursor_height <= 0)
8251                         base = 0;
8252
8253                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8254                 y = -y;
8255         }
8256         pos |= y << CURSOR_Y_SHIFT;
8257
8258         if (base == 0 && intel_crtc->cursor_base == 0)
8259                 return;
8260
8261         I915_WRITE(CURPOS(pipe), pos);
8262
8263         /* ILK+ do this automagically */
8264         if (HAS_GMCH_DISPLAY(dev) &&
8265                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8266                 base += (intel_crtc->cursor_height *
8267                         intel_crtc->cursor_width - 1) * 4;
8268         }
8269
8270         if (IS_845G(dev) || IS_I865G(dev))
8271                 i845_update_cursor(crtc, base);
8272         else
8273                 i9xx_update_cursor(crtc, base);
8274 }
8275
8276 static bool cursor_size_ok(struct drm_device *dev,
8277                            uint32_t width, uint32_t height)
8278 {
8279         if (width == 0 || height == 0)
8280                 return false;
8281
8282         /*
8283          * 845g/865g are special in that they are only limited by
8284          * the width of their cursors, the height is arbitrary up to
8285          * the precision of the register. Everything else requires
8286          * square cursors, limited to a few power-of-two sizes.
8287          */
8288         if (IS_845G(dev) || IS_I865G(dev)) {
8289                 if ((width & 63) != 0)
8290                         return false;
8291
8292                 if (width > (IS_845G(dev) ? 64 : 512))
8293                         return false;
8294
8295                 if (height > 1023)
8296                         return false;
8297         } else {
8298                 switch (width | height) {
8299                 case 256:
8300                 case 128:
8301                         if (IS_GEN2(dev))
8302                                 return false;
8303                 case 64:
8304                         break;
8305                 default:
8306                         return false;
8307                 }
8308         }
8309
8310         return true;
8311 }
8312
8313 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8314                                      struct drm_i915_gem_object *obj,
8315                                      uint32_t width, uint32_t height)
8316 {
8317         struct drm_device *dev = crtc->dev;
8318         struct drm_i915_private *dev_priv = dev->dev_private;
8319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8320         enum pipe pipe = intel_crtc->pipe;
8321         unsigned old_width;
8322         uint32_t addr;
8323         int ret;
8324
8325         /* if we want to turn off the cursor ignore width and height */
8326         if (!obj) {
8327                 DRM_DEBUG_KMS("cursor off\n");
8328                 addr = 0;
8329                 mutex_lock(&dev->struct_mutex);
8330                 goto finish;
8331         }
8332
8333         /* we only need to pin inside GTT if cursor is non-phy */
8334         mutex_lock(&dev->struct_mutex);
8335         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8336                 unsigned alignment;
8337
8338                 /*
8339                  * Global gtt pte registers are special registers which actually
8340                  * forward writes to a chunk of system memory. Which means that
8341                  * there is no risk that the register values disappear as soon
8342                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8343                  * only the pin/unpin/fence and not more.
8344                  */
8345                 intel_runtime_pm_get(dev_priv);
8346
8347                 /* Note that the w/a also requires 2 PTE of padding following
8348                  * the bo. We currently fill all unused PTE with the shadow
8349                  * page and so we should always have valid PTE following the
8350                  * cursor preventing the VT-d warning.
8351                  */
8352                 alignment = 0;
8353                 if (need_vtd_wa(dev))
8354                         alignment = 64*1024;
8355
8356                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8357                 if (ret) {
8358                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8359                         intel_runtime_pm_put(dev_priv);
8360                         goto fail_locked;
8361                 }
8362
8363                 ret = i915_gem_object_put_fence(obj);
8364                 if (ret) {
8365                         DRM_DEBUG_KMS("failed to release fence for cursor");
8366                         intel_runtime_pm_put(dev_priv);
8367                         goto fail_unpin;
8368                 }
8369
8370                 addr = i915_gem_obj_ggtt_offset(obj);
8371
8372                 intel_runtime_pm_put(dev_priv);
8373         } else {
8374                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8375                 ret = i915_gem_object_attach_phys(obj, align);
8376                 if (ret) {
8377                         DRM_DEBUG_KMS("failed to attach phys object\n");
8378                         goto fail_locked;
8379                 }
8380                 addr = obj->phys_handle->busaddr;
8381         }
8382
8383  finish:
8384         if (intel_crtc->cursor_bo) {
8385                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8386                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8387         }
8388
8389         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8390                           INTEL_FRONTBUFFER_CURSOR(pipe));
8391         mutex_unlock(&dev->struct_mutex);
8392
8393         old_width = intel_crtc->cursor_width;
8394
8395         intel_crtc->cursor_addr = addr;
8396         intel_crtc->cursor_bo = obj;
8397         intel_crtc->cursor_width = width;
8398         intel_crtc->cursor_height = height;
8399
8400         if (intel_crtc->active) {
8401                 if (old_width != width)
8402                         intel_update_watermarks(crtc);
8403                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8404
8405                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8406         }
8407
8408         return 0;
8409 fail_unpin:
8410         i915_gem_object_unpin_from_display_plane(obj);
8411 fail_locked:
8412         mutex_unlock(&dev->struct_mutex);
8413         return ret;
8414 }
8415
8416 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8417                                  u16 *blue, uint32_t start, uint32_t size)
8418 {
8419         int end = (start + size > 256) ? 256 : start + size, i;
8420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8421
8422         for (i = start; i < end; i++) {
8423                 intel_crtc->lut_r[i] = red[i] >> 8;
8424                 intel_crtc->lut_g[i] = green[i] >> 8;
8425                 intel_crtc->lut_b[i] = blue[i] >> 8;
8426         }
8427
8428         intel_crtc_load_lut(crtc);
8429 }
8430
8431 /* VESA 640x480x72Hz mode to set on the pipe */
8432 static struct drm_display_mode load_detect_mode = {
8433         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8434                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8435 };
8436
8437 struct drm_framebuffer *
8438 __intel_framebuffer_create(struct drm_device *dev,
8439                            struct drm_mode_fb_cmd2 *mode_cmd,
8440                            struct drm_i915_gem_object *obj)
8441 {
8442         struct intel_framebuffer *intel_fb;
8443         int ret;
8444
8445         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8446         if (!intel_fb) {
8447                 drm_gem_object_unreference_unlocked(&obj->base);
8448                 return ERR_PTR(-ENOMEM);
8449         }
8450
8451         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8452         if (ret)
8453                 goto err;
8454
8455         return &intel_fb->base;
8456 err:
8457         drm_gem_object_unreference_unlocked(&obj->base);
8458         kfree(intel_fb);
8459
8460         return ERR_PTR(ret);
8461 }
8462
8463 static struct drm_framebuffer *
8464 intel_framebuffer_create(struct drm_device *dev,
8465                          struct drm_mode_fb_cmd2 *mode_cmd,
8466                          struct drm_i915_gem_object *obj)
8467 {
8468         struct drm_framebuffer *fb;
8469         int ret;
8470
8471         ret = i915_mutex_lock_interruptible(dev);
8472         if (ret)
8473                 return ERR_PTR(ret);
8474         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8475         mutex_unlock(&dev->struct_mutex);
8476
8477         return fb;
8478 }
8479
8480 static u32
8481 intel_framebuffer_pitch_for_width(int width, int bpp)
8482 {
8483         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8484         return ALIGN(pitch, 64);
8485 }
8486
8487 static u32
8488 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8489 {
8490         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8491         return PAGE_ALIGN(pitch * mode->vdisplay);
8492 }
8493
8494 static struct drm_framebuffer *
8495 intel_framebuffer_create_for_mode(struct drm_device *dev,
8496                                   struct drm_display_mode *mode,
8497                                   int depth, int bpp)
8498 {
8499         struct drm_i915_gem_object *obj;
8500         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8501
8502         obj = i915_gem_alloc_object(dev,
8503                                     intel_framebuffer_size_for_mode(mode, bpp));
8504         if (obj == NULL)
8505                 return ERR_PTR(-ENOMEM);
8506
8507         mode_cmd.width = mode->hdisplay;
8508         mode_cmd.height = mode->vdisplay;
8509         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8510                                                                 bpp);
8511         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8512
8513         return intel_framebuffer_create(dev, &mode_cmd, obj);
8514 }
8515
8516 static struct drm_framebuffer *
8517 mode_fits_in_fbdev(struct drm_device *dev,
8518                    struct drm_display_mode *mode)
8519 {
8520 #ifdef CONFIG_DRM_I915_FBDEV
8521         struct drm_i915_private *dev_priv = dev->dev_private;
8522         struct drm_i915_gem_object *obj;
8523         struct drm_framebuffer *fb;
8524
8525         if (!dev_priv->fbdev)
8526                 return NULL;
8527
8528         if (!dev_priv->fbdev->fb)
8529                 return NULL;
8530
8531         obj = dev_priv->fbdev->fb->obj;
8532         BUG_ON(!obj);
8533
8534         fb = &dev_priv->fbdev->fb->base;
8535         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8536                                                                fb->bits_per_pixel))
8537                 return NULL;
8538
8539         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8540                 return NULL;
8541
8542         return fb;
8543 #else
8544         return NULL;
8545 #endif
8546 }
8547
8548 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8549                                 struct drm_display_mode *mode,
8550                                 struct intel_load_detect_pipe *old,
8551                                 struct drm_modeset_acquire_ctx *ctx)
8552 {
8553         struct intel_crtc *intel_crtc;
8554         struct intel_encoder *intel_encoder =
8555                 intel_attached_encoder(connector);
8556         struct drm_crtc *possible_crtc;
8557         struct drm_encoder *encoder = &intel_encoder->base;
8558         struct drm_crtc *crtc = NULL;
8559         struct drm_device *dev = encoder->dev;
8560         struct drm_framebuffer *fb;
8561         struct drm_mode_config *config = &dev->mode_config;
8562         int ret, i = -1;
8563
8564         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8565                       connector->base.id, connector->name,
8566                       encoder->base.id, encoder->name);
8567
8568 retry:
8569         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8570         if (ret)
8571                 goto fail_unlock;
8572
8573         /*
8574          * Algorithm gets a little messy:
8575          *
8576          *   - if the connector already has an assigned crtc, use it (but make
8577          *     sure it's on first)
8578          *
8579          *   - try to find the first unused crtc that can drive this connector,
8580          *     and use that if we find one
8581          */
8582
8583         /* See if we already have a CRTC for this connector */
8584         if (encoder->crtc) {
8585                 crtc = encoder->crtc;
8586
8587                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8588                 if (ret)
8589                         goto fail_unlock;
8590
8591                 old->dpms_mode = connector->dpms;
8592                 old->load_detect_temp = false;
8593
8594                 /* Make sure the crtc and connector are running */
8595                 if (connector->dpms != DRM_MODE_DPMS_ON)
8596                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8597
8598                 return true;
8599         }
8600
8601         /* Find an unused one (if possible) */
8602         for_each_crtc(dev, possible_crtc) {
8603                 i++;
8604                 if (!(encoder->possible_crtcs & (1 << i)))
8605                         continue;
8606                 if (possible_crtc->enabled)
8607                         continue;
8608                 /* This can occur when applying the pipe A quirk on resume. */
8609                 if (to_intel_crtc(possible_crtc)->new_enabled)
8610                         continue;
8611
8612                 crtc = possible_crtc;
8613                 break;
8614         }
8615
8616         /*
8617          * If we didn't find an unused CRTC, don't use any.
8618          */
8619         if (!crtc) {
8620                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8621                 goto fail_unlock;
8622         }
8623
8624         ret = drm_modeset_lock(&crtc->mutex, ctx);
8625         if (ret)
8626                 goto fail_unlock;
8627         intel_encoder->new_crtc = to_intel_crtc(crtc);
8628         to_intel_connector(connector)->new_encoder = intel_encoder;
8629
8630         intel_crtc = to_intel_crtc(crtc);
8631         intel_crtc->new_enabled = true;
8632         intel_crtc->new_config = &intel_crtc->config;
8633         old->dpms_mode = connector->dpms;
8634         old->load_detect_temp = true;
8635         old->release_fb = NULL;
8636
8637         if (!mode)
8638                 mode = &load_detect_mode;
8639
8640         /* We need a framebuffer large enough to accommodate all accesses
8641          * that the plane may generate whilst we perform load detection.
8642          * We can not rely on the fbcon either being present (we get called
8643          * during its initialisation to detect all boot displays, or it may
8644          * not even exist) or that it is large enough to satisfy the
8645          * requested mode.
8646          */
8647         fb = mode_fits_in_fbdev(dev, mode);
8648         if (fb == NULL) {
8649                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8650                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8651                 old->release_fb = fb;
8652         } else
8653                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8654         if (IS_ERR(fb)) {
8655                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8656                 goto fail;
8657         }
8658
8659         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8660                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8661                 if (old->release_fb)
8662                         old->release_fb->funcs->destroy(old->release_fb);
8663                 goto fail;
8664         }
8665
8666         /* let the connector get through one full cycle before testing */
8667         intel_wait_for_vblank(dev, intel_crtc->pipe);
8668         return true;
8669
8670  fail:
8671         intel_crtc->new_enabled = crtc->enabled;
8672         if (intel_crtc->new_enabled)
8673                 intel_crtc->new_config = &intel_crtc->config;
8674         else
8675                 intel_crtc->new_config = NULL;
8676 fail_unlock:
8677         if (ret == -EDEADLK) {
8678                 drm_modeset_backoff(ctx);
8679                 goto retry;
8680         }
8681
8682         return false;
8683 }
8684
8685 void intel_release_load_detect_pipe(struct drm_connector *connector,
8686                                     struct intel_load_detect_pipe *old)
8687 {
8688         struct intel_encoder *intel_encoder =
8689                 intel_attached_encoder(connector);
8690         struct drm_encoder *encoder = &intel_encoder->base;
8691         struct drm_crtc *crtc = encoder->crtc;
8692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8693
8694         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8695                       connector->base.id, connector->name,
8696                       encoder->base.id, encoder->name);
8697
8698         if (old->load_detect_temp) {
8699                 to_intel_connector(connector)->new_encoder = NULL;
8700                 intel_encoder->new_crtc = NULL;
8701                 intel_crtc->new_enabled = false;
8702                 intel_crtc->new_config = NULL;
8703                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8704
8705                 if (old->release_fb) {
8706                         drm_framebuffer_unregister_private(old->release_fb);
8707                         drm_framebuffer_unreference(old->release_fb);
8708                 }
8709
8710                 return;
8711         }
8712
8713         /* Switch crtc and encoder back off if necessary */
8714         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8715                 connector->funcs->dpms(connector, old->dpms_mode);
8716 }
8717
8718 static int i9xx_pll_refclk(struct drm_device *dev,
8719                            const struct intel_crtc_config *pipe_config)
8720 {
8721         struct drm_i915_private *dev_priv = dev->dev_private;
8722         u32 dpll = pipe_config->dpll_hw_state.dpll;
8723
8724         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8725                 return dev_priv->vbt.lvds_ssc_freq;
8726         else if (HAS_PCH_SPLIT(dev))
8727                 return 120000;
8728         else if (!IS_GEN2(dev))
8729                 return 96000;
8730         else
8731                 return 48000;
8732 }
8733
8734 /* Returns the clock of the currently programmed mode of the given pipe. */
8735 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8736                                 struct intel_crtc_config *pipe_config)
8737 {
8738         struct drm_device *dev = crtc->base.dev;
8739         struct drm_i915_private *dev_priv = dev->dev_private;
8740         int pipe = pipe_config->cpu_transcoder;
8741         u32 dpll = pipe_config->dpll_hw_state.dpll;
8742         u32 fp;
8743         intel_clock_t clock;
8744         int refclk = i9xx_pll_refclk(dev, pipe_config);
8745
8746         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8747                 fp = pipe_config->dpll_hw_state.fp0;
8748         else
8749                 fp = pipe_config->dpll_hw_state.fp1;
8750
8751         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8752         if (IS_PINEVIEW(dev)) {
8753                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8754                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8755         } else {
8756                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8757                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8758         }
8759
8760         if (!IS_GEN2(dev)) {
8761                 if (IS_PINEVIEW(dev))
8762                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8763                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8764                 else
8765                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8766                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8767
8768                 switch (dpll & DPLL_MODE_MASK) {
8769                 case DPLLB_MODE_DAC_SERIAL:
8770                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8771                                 5 : 10;
8772                         break;
8773                 case DPLLB_MODE_LVDS:
8774                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8775                                 7 : 14;
8776                         break;
8777                 default:
8778                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8779                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8780                         return;
8781                 }
8782
8783                 if (IS_PINEVIEW(dev))
8784                         pineview_clock(refclk, &clock);
8785                 else
8786                         i9xx_clock(refclk, &clock);
8787         } else {
8788                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8789                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8790
8791                 if (is_lvds) {
8792                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8793                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8794
8795                         if (lvds & LVDS_CLKB_POWER_UP)
8796                                 clock.p2 = 7;
8797                         else
8798                                 clock.p2 = 14;
8799                 } else {
8800                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8801                                 clock.p1 = 2;
8802                         else {
8803                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8804                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8805                         }
8806                         if (dpll & PLL_P2_DIVIDE_BY_4)
8807                                 clock.p2 = 4;
8808                         else
8809                                 clock.p2 = 2;
8810                 }
8811
8812                 i9xx_clock(refclk, &clock);
8813         }
8814
8815         /*
8816          * This value includes pixel_multiplier. We will use
8817          * port_clock to compute adjusted_mode.crtc_clock in the
8818          * encoder's get_config() function.
8819          */
8820         pipe_config->port_clock = clock.dot;
8821 }
8822
8823 int intel_dotclock_calculate(int link_freq,
8824                              const struct intel_link_m_n *m_n)
8825 {
8826         /*
8827          * The calculation for the data clock is:
8828          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8829          * But we want to avoid losing precison if possible, so:
8830          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8831          *
8832          * and the link clock is simpler:
8833          * link_clock = (m * link_clock) / n
8834          */
8835
8836         if (!m_n->link_n)
8837                 return 0;
8838
8839         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8840 }
8841
8842 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8843                                    struct intel_crtc_config *pipe_config)
8844 {
8845         struct drm_device *dev = crtc->base.dev;
8846
8847         /* read out port_clock from the DPLL */
8848         i9xx_crtc_clock_get(crtc, pipe_config);
8849
8850         /*
8851          * This value does not include pixel_multiplier.
8852          * We will check that port_clock and adjusted_mode.crtc_clock
8853          * agree once we know their relationship in the encoder's
8854          * get_config() function.
8855          */
8856         pipe_config->adjusted_mode.crtc_clock =
8857                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8858                                          &pipe_config->fdi_m_n);
8859 }
8860
8861 /** Returns the currently programmed mode of the given pipe. */
8862 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8863                                              struct drm_crtc *crtc)
8864 {
8865         struct drm_i915_private *dev_priv = dev->dev_private;
8866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8867         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8868         struct drm_display_mode *mode;
8869         struct intel_crtc_config pipe_config;
8870         int htot = I915_READ(HTOTAL(cpu_transcoder));
8871         int hsync = I915_READ(HSYNC(cpu_transcoder));
8872         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8873         int vsync = I915_READ(VSYNC(cpu_transcoder));
8874         enum pipe pipe = intel_crtc->pipe;
8875
8876         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8877         if (!mode)
8878                 return NULL;
8879
8880         /*
8881          * Construct a pipe_config sufficient for getting the clock info
8882          * back out of crtc_clock_get.
8883          *
8884          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8885          * to use a real value here instead.
8886          */
8887         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8888         pipe_config.pixel_multiplier = 1;
8889         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8890         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8891         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8892         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8893
8894         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8895         mode->hdisplay = (htot & 0xffff) + 1;
8896         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8897         mode->hsync_start = (hsync & 0xffff) + 1;
8898         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8899         mode->vdisplay = (vtot & 0xffff) + 1;
8900         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8901         mode->vsync_start = (vsync & 0xffff) + 1;
8902         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8903
8904         drm_mode_set_name(mode);
8905
8906         return mode;
8907 }
8908
8909 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8910 {
8911         struct drm_device *dev = crtc->dev;
8912         struct drm_i915_private *dev_priv = dev->dev_private;
8913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8914
8915         if (!HAS_GMCH_DISPLAY(dev))
8916                 return;
8917
8918         if (!dev_priv->lvds_downclock_avail)
8919                 return;
8920
8921         /*
8922          * Since this is called by a timer, we should never get here in
8923          * the manual case.
8924          */
8925         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8926                 int pipe = intel_crtc->pipe;
8927                 int dpll_reg = DPLL(pipe);
8928                 int dpll;
8929
8930                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8931
8932                 assert_panel_unlocked(dev_priv, pipe);
8933
8934                 dpll = I915_READ(dpll_reg);
8935                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8936                 I915_WRITE(dpll_reg, dpll);
8937                 intel_wait_for_vblank(dev, pipe);
8938                 dpll = I915_READ(dpll_reg);
8939                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8940                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8941         }
8942
8943 }
8944
8945 void intel_mark_busy(struct drm_device *dev)
8946 {
8947         struct drm_i915_private *dev_priv = dev->dev_private;
8948
8949         if (dev_priv->mm.busy)
8950                 return;
8951
8952         intel_runtime_pm_get(dev_priv);
8953         i915_update_gfx_val(dev_priv);
8954         dev_priv->mm.busy = true;
8955 }
8956
8957 void intel_mark_idle(struct drm_device *dev)
8958 {
8959         struct drm_i915_private *dev_priv = dev->dev_private;
8960         struct drm_crtc *crtc;
8961
8962         if (!dev_priv->mm.busy)
8963                 return;
8964
8965         dev_priv->mm.busy = false;
8966
8967         if (!i915.powersave)
8968                 goto out;
8969
8970         for_each_crtc(dev, crtc) {
8971                 if (!crtc->primary->fb)
8972                         continue;
8973
8974                 intel_decrease_pllclock(crtc);
8975         }
8976
8977         if (INTEL_INFO(dev)->gen >= 6)
8978                 gen6_rps_idle(dev->dev_private);
8979
8980 out:
8981         intel_runtime_pm_put(dev_priv);
8982 }
8983
8984 static void intel_crtc_destroy(struct drm_crtc *crtc)
8985 {
8986         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8987         struct drm_device *dev = crtc->dev;
8988         struct intel_unpin_work *work;
8989
8990         spin_lock_irq(&dev->event_lock);
8991         work = intel_crtc->unpin_work;
8992         intel_crtc->unpin_work = NULL;
8993         spin_unlock_irq(&dev->event_lock);
8994
8995         if (work) {
8996                 cancel_work_sync(&work->work);
8997                 kfree(work);
8998         }
8999
9000         drm_crtc_cleanup(crtc);
9001
9002         kfree(intel_crtc);
9003 }
9004
9005 static void intel_unpin_work_fn(struct work_struct *__work)
9006 {
9007         struct intel_unpin_work *work =
9008                 container_of(__work, struct intel_unpin_work, work);
9009         struct drm_device *dev = work->crtc->dev;
9010         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9011
9012         mutex_lock(&dev->struct_mutex);
9013         intel_unpin_fb_obj(work->old_fb_obj);
9014         drm_gem_object_unreference(&work->pending_flip_obj->base);
9015         drm_gem_object_unreference(&work->old_fb_obj->base);
9016
9017         intel_update_fbc(dev);
9018         mutex_unlock(&dev->struct_mutex);
9019
9020         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9021
9022         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9023         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9024
9025         kfree(work);
9026 }
9027
9028 static void do_intel_finish_page_flip(struct drm_device *dev,
9029                                       struct drm_crtc *crtc)
9030 {
9031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9032         struct intel_unpin_work *work;
9033         unsigned long flags;
9034
9035         /* Ignore early vblank irqs */
9036         if (intel_crtc == NULL)
9037                 return;
9038
9039         /*
9040          * This is called both by irq handlers and the reset code (to complete
9041          * lost pageflips) so needs the full irqsave spinlocks.
9042          */
9043         spin_lock_irqsave(&dev->event_lock, flags);
9044         work = intel_crtc->unpin_work;
9045
9046         /* Ensure we don't miss a work->pending update ... */
9047         smp_rmb();
9048
9049         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9050                 spin_unlock_irqrestore(&dev->event_lock, flags);
9051                 return;
9052         }
9053
9054         page_flip_completed(intel_crtc);
9055
9056         spin_unlock_irqrestore(&dev->event_lock, flags);
9057 }
9058
9059 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9060 {
9061         struct drm_i915_private *dev_priv = dev->dev_private;
9062         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9063
9064         do_intel_finish_page_flip(dev, crtc);
9065 }
9066
9067 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9068 {
9069         struct drm_i915_private *dev_priv = dev->dev_private;
9070         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9071
9072         do_intel_finish_page_flip(dev, crtc);
9073 }
9074
9075 /* Is 'a' after or equal to 'b'? */
9076 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9077 {
9078         return !((a - b) & 0x80000000);
9079 }
9080
9081 static bool page_flip_finished(struct intel_crtc *crtc)
9082 {
9083         struct drm_device *dev = crtc->base.dev;
9084         struct drm_i915_private *dev_priv = dev->dev_private;
9085
9086         /*
9087          * The relevant registers doen't exist on pre-ctg.
9088          * As the flip done interrupt doesn't trigger for mmio
9089          * flips on gmch platforms, a flip count check isn't
9090          * really needed there. But since ctg has the registers,
9091          * include it in the check anyway.
9092          */
9093         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9094                 return true;
9095
9096         /*
9097          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9098          * used the same base address. In that case the mmio flip might
9099          * have completed, but the CS hasn't even executed the flip yet.
9100          *
9101          * A flip count check isn't enough as the CS might have updated
9102          * the base address just after start of vblank, but before we
9103          * managed to process the interrupt. This means we'd complete the
9104          * CS flip too soon.
9105          *
9106          * Combining both checks should get us a good enough result. It may
9107          * still happen that the CS flip has been executed, but has not
9108          * yet actually completed. But in case the base address is the same
9109          * anyway, we don't really care.
9110          */
9111         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9112                 crtc->unpin_work->gtt_offset &&
9113                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9114                                     crtc->unpin_work->flip_count);
9115 }
9116
9117 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9118 {
9119         struct drm_i915_private *dev_priv = dev->dev_private;
9120         struct intel_crtc *intel_crtc =
9121                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9122         unsigned long flags;
9123
9124
9125         /*
9126          * This is called both by irq handlers and the reset code (to complete
9127          * lost pageflips) so needs the full irqsave spinlocks.
9128          *
9129          * NB: An MMIO update of the plane base pointer will also
9130          * generate a page-flip completion irq, i.e. every modeset
9131          * is also accompanied by a spurious intel_prepare_page_flip().
9132          */
9133         spin_lock_irqsave(&dev->event_lock, flags);
9134         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9135                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9136         spin_unlock_irqrestore(&dev->event_lock, flags);
9137 }
9138
9139 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9140 {
9141         /* Ensure that the work item is consistent when activating it ... */
9142         smp_wmb();
9143         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9144         /* and that it is marked active as soon as the irq could fire. */
9145         smp_wmb();
9146 }
9147
9148 static int intel_gen2_queue_flip(struct drm_device *dev,
9149                                  struct drm_crtc *crtc,
9150                                  struct drm_framebuffer *fb,
9151                                  struct drm_i915_gem_object *obj,
9152                                  struct intel_engine_cs *ring,
9153                                  uint32_t flags)
9154 {
9155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9156         u32 flip_mask;
9157         int ret;
9158
9159         ret = intel_ring_begin(ring, 6);
9160         if (ret)
9161                 return ret;
9162
9163         /* Can't queue multiple flips, so wait for the previous
9164          * one to finish before executing the next.
9165          */
9166         if (intel_crtc->plane)
9167                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9168         else
9169                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9170         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9171         intel_ring_emit(ring, MI_NOOP);
9172         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9173                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9174         intel_ring_emit(ring, fb->pitches[0]);
9175         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9176         intel_ring_emit(ring, 0); /* aux display base address, unused */
9177
9178         intel_mark_page_flip_active(intel_crtc);
9179         __intel_ring_advance(ring);
9180         return 0;
9181 }
9182
9183 static int intel_gen3_queue_flip(struct drm_device *dev,
9184                                  struct drm_crtc *crtc,
9185                                  struct drm_framebuffer *fb,
9186                                  struct drm_i915_gem_object *obj,
9187                                  struct intel_engine_cs *ring,
9188                                  uint32_t flags)
9189 {
9190         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9191         u32 flip_mask;
9192         int ret;
9193
9194         ret = intel_ring_begin(ring, 6);
9195         if (ret)
9196                 return ret;
9197
9198         if (intel_crtc->plane)
9199                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9200         else
9201                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9202         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9203         intel_ring_emit(ring, MI_NOOP);
9204         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9205                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9206         intel_ring_emit(ring, fb->pitches[0]);
9207         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9208         intel_ring_emit(ring, MI_NOOP);
9209
9210         intel_mark_page_flip_active(intel_crtc);
9211         __intel_ring_advance(ring);
9212         return 0;
9213 }
9214
9215 static int intel_gen4_queue_flip(struct drm_device *dev,
9216                                  struct drm_crtc *crtc,
9217                                  struct drm_framebuffer *fb,
9218                                  struct drm_i915_gem_object *obj,
9219                                  struct intel_engine_cs *ring,
9220                                  uint32_t flags)
9221 {
9222         struct drm_i915_private *dev_priv = dev->dev_private;
9223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9224         uint32_t pf, pipesrc;
9225         int ret;
9226
9227         ret = intel_ring_begin(ring, 4);
9228         if (ret)
9229                 return ret;
9230
9231         /* i965+ uses the linear or tiled offsets from the
9232          * Display Registers (which do not change across a page-flip)
9233          * so we need only reprogram the base address.
9234          */
9235         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9236                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9237         intel_ring_emit(ring, fb->pitches[0]);
9238         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9239                         obj->tiling_mode);
9240
9241         /* XXX Enabling the panel-fitter across page-flip is so far
9242          * untested on non-native modes, so ignore it for now.
9243          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9244          */
9245         pf = 0;
9246         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9247         intel_ring_emit(ring, pf | pipesrc);
9248
9249         intel_mark_page_flip_active(intel_crtc);
9250         __intel_ring_advance(ring);
9251         return 0;
9252 }
9253
9254 static int intel_gen6_queue_flip(struct drm_device *dev,
9255                                  struct drm_crtc *crtc,
9256                                  struct drm_framebuffer *fb,
9257                                  struct drm_i915_gem_object *obj,
9258                                  struct intel_engine_cs *ring,
9259                                  uint32_t flags)
9260 {
9261         struct drm_i915_private *dev_priv = dev->dev_private;
9262         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9263         uint32_t pf, pipesrc;
9264         int ret;
9265
9266         ret = intel_ring_begin(ring, 4);
9267         if (ret)
9268                 return ret;
9269
9270         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9271                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9272         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9273         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9274
9275         /* Contrary to the suggestions in the documentation,
9276          * "Enable Panel Fitter" does not seem to be required when page
9277          * flipping with a non-native mode, and worse causes a normal
9278          * modeset to fail.
9279          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9280          */
9281         pf = 0;
9282         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9283         intel_ring_emit(ring, pf | pipesrc);
9284
9285         intel_mark_page_flip_active(intel_crtc);
9286         __intel_ring_advance(ring);
9287         return 0;
9288 }
9289
9290 static int intel_gen7_queue_flip(struct drm_device *dev,
9291                                  struct drm_crtc *crtc,
9292                                  struct drm_framebuffer *fb,
9293                                  struct drm_i915_gem_object *obj,
9294                                  struct intel_engine_cs *ring,
9295                                  uint32_t flags)
9296 {
9297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9298         uint32_t plane_bit = 0;
9299         int len, ret;
9300
9301         switch (intel_crtc->plane) {
9302         case PLANE_A:
9303                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9304                 break;
9305         case PLANE_B:
9306                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9307                 break;
9308         case PLANE_C:
9309                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9310                 break;
9311         default:
9312                 WARN_ONCE(1, "unknown plane in flip command\n");
9313                 return -ENODEV;
9314         }
9315
9316         len = 4;
9317         if (ring->id == RCS) {
9318                 len += 6;
9319                 /*
9320                  * On Gen 8, SRM is now taking an extra dword to accommodate
9321                  * 48bits addresses, and we need a NOOP for the batch size to
9322                  * stay even.
9323                  */
9324                 if (IS_GEN8(dev))
9325                         len += 2;
9326         }
9327
9328         /*
9329          * BSpec MI_DISPLAY_FLIP for IVB:
9330          * "The full packet must be contained within the same cache line."
9331          *
9332          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9333          * cacheline, if we ever start emitting more commands before
9334          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9335          * then do the cacheline alignment, and finally emit the
9336          * MI_DISPLAY_FLIP.
9337          */
9338         ret = intel_ring_cacheline_align(ring);
9339         if (ret)
9340                 return ret;
9341
9342         ret = intel_ring_begin(ring, len);
9343         if (ret)
9344                 return ret;
9345
9346         /* Unmask the flip-done completion message. Note that the bspec says that
9347          * we should do this for both the BCS and RCS, and that we must not unmask
9348          * more than one flip event at any time (or ensure that one flip message
9349          * can be sent by waiting for flip-done prior to queueing new flips).
9350          * Experimentation says that BCS works despite DERRMR masking all
9351          * flip-done completion events and that unmasking all planes at once
9352          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9353          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9354          */
9355         if (ring->id == RCS) {
9356                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9357                 intel_ring_emit(ring, DERRMR);
9358                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9359                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9360                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9361                 if (IS_GEN8(dev))
9362                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9363                                               MI_SRM_LRM_GLOBAL_GTT);
9364                 else
9365                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9366                                               MI_SRM_LRM_GLOBAL_GTT);
9367                 intel_ring_emit(ring, DERRMR);
9368                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9369                 if (IS_GEN8(dev)) {
9370                         intel_ring_emit(ring, 0);
9371                         intel_ring_emit(ring, MI_NOOP);
9372                 }
9373         }
9374
9375         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9376         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9377         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9378         intel_ring_emit(ring, (MI_NOOP));
9379
9380         intel_mark_page_flip_active(intel_crtc);
9381         __intel_ring_advance(ring);
9382         return 0;
9383 }
9384
9385 static bool use_mmio_flip(struct intel_engine_cs *ring,
9386                           struct drm_i915_gem_object *obj)
9387 {
9388         /*
9389          * This is not being used for older platforms, because
9390          * non-availability of flip done interrupt forces us to use
9391          * CS flips. Older platforms derive flip done using some clever
9392          * tricks involving the flip_pending status bits and vblank irqs.
9393          * So using MMIO flips there would disrupt this mechanism.
9394          */
9395
9396         if (ring == NULL)
9397                 return true;
9398
9399         if (INTEL_INFO(ring->dev)->gen < 5)
9400                 return false;
9401
9402         if (i915.use_mmio_flip < 0)
9403                 return false;
9404         else if (i915.use_mmio_flip > 0)
9405                 return true;
9406         else if (i915.enable_execlists)
9407                 return true;
9408         else
9409                 return ring != obj->ring;
9410 }
9411
9412 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9413 {
9414         struct drm_device *dev = intel_crtc->base.dev;
9415         struct drm_i915_private *dev_priv = dev->dev_private;
9416         struct intel_framebuffer *intel_fb =
9417                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9418         struct drm_i915_gem_object *obj = intel_fb->obj;
9419         u32 dspcntr;
9420         u32 reg;
9421
9422         intel_mark_page_flip_active(intel_crtc);
9423
9424         reg = DSPCNTR(intel_crtc->plane);
9425         dspcntr = I915_READ(reg);
9426
9427         if (obj->tiling_mode != I915_TILING_NONE)
9428                 dspcntr |= DISPPLANE_TILED;
9429         else
9430                 dspcntr &= ~DISPPLANE_TILED;
9431
9432         I915_WRITE(reg, dspcntr);
9433
9434         I915_WRITE(DSPSURF(intel_crtc->plane),
9435                    intel_crtc->unpin_work->gtt_offset);
9436         POSTING_READ(DSPSURF(intel_crtc->plane));
9437 }
9438
9439 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9440 {
9441         struct intel_engine_cs *ring;
9442         int ret;
9443
9444         lockdep_assert_held(&obj->base.dev->struct_mutex);
9445
9446         if (!obj->last_write_seqno)
9447                 return 0;
9448
9449         ring = obj->ring;
9450
9451         if (i915_seqno_passed(ring->get_seqno(ring, true),
9452                               obj->last_write_seqno))
9453                 return 0;
9454
9455         ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9456         if (ret)
9457                 return ret;
9458
9459         if (WARN_ON(!ring->irq_get(ring)))
9460                 return 0;
9461
9462         return 1;
9463 }
9464
9465 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9466 {
9467         struct drm_i915_private *dev_priv = to_i915(ring->dev);
9468         struct intel_crtc *intel_crtc;
9469         unsigned long irq_flags;
9470         u32 seqno;
9471
9472         seqno = ring->get_seqno(ring, false);
9473
9474         spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9475         for_each_intel_crtc(ring->dev, intel_crtc) {
9476                 struct intel_mmio_flip *mmio_flip;
9477
9478                 mmio_flip = &intel_crtc->mmio_flip;
9479                 if (mmio_flip->seqno == 0)
9480                         continue;
9481
9482                 if (ring->id != mmio_flip->ring_id)
9483                         continue;
9484
9485                 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9486                         intel_do_mmio_flip(intel_crtc);
9487                         mmio_flip->seqno = 0;
9488                         ring->irq_put(ring);
9489                 }
9490         }
9491         spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9492 }
9493
9494 static int intel_queue_mmio_flip(struct drm_device *dev,
9495                                  struct drm_crtc *crtc,
9496                                  struct drm_framebuffer *fb,
9497                                  struct drm_i915_gem_object *obj,
9498                                  struct intel_engine_cs *ring,
9499                                  uint32_t flags)
9500 {
9501         struct drm_i915_private *dev_priv = dev->dev_private;
9502         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9503         int ret;
9504
9505         if (WARN_ON(intel_crtc->mmio_flip.seqno))
9506                 return -EBUSY;
9507
9508         ret = intel_postpone_flip(obj);
9509         if (ret < 0)
9510                 return ret;
9511         if (ret == 0) {
9512                 intel_do_mmio_flip(intel_crtc);
9513                 return 0;
9514         }
9515
9516         spin_lock_irq(&dev_priv->mmio_flip_lock);
9517         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9518         intel_crtc->mmio_flip.ring_id = obj->ring->id;
9519         spin_unlock_irq(&dev_priv->mmio_flip_lock);
9520
9521         /*
9522          * Double check to catch cases where irq fired before
9523          * mmio flip data was ready
9524          */
9525         intel_notify_mmio_flip(obj->ring);
9526         return 0;
9527 }
9528
9529 static int intel_default_queue_flip(struct drm_device *dev,
9530                                     struct drm_crtc *crtc,
9531                                     struct drm_framebuffer *fb,
9532                                     struct drm_i915_gem_object *obj,
9533                                     struct intel_engine_cs *ring,
9534                                     uint32_t flags)
9535 {
9536         return -ENODEV;
9537 }
9538
9539 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9540                                          struct drm_crtc *crtc)
9541 {
9542         struct drm_i915_private *dev_priv = dev->dev_private;
9543         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9544         struct intel_unpin_work *work = intel_crtc->unpin_work;
9545         u32 addr;
9546
9547         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9548                 return true;
9549
9550         if (!work->enable_stall_check)
9551                 return false;
9552
9553         if (work->flip_ready_vblank == 0) {
9554                 if (work->flip_queued_ring &&
9555                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9556                                        work->flip_queued_seqno))
9557                         return false;
9558
9559                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9560         }
9561
9562         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9563                 return false;
9564
9565         /* Potential stall - if we see that the flip has happened,
9566          * assume a missed interrupt. */
9567         if (INTEL_INFO(dev)->gen >= 4)
9568                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9569         else
9570                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9571
9572         /* There is a potential issue here with a false positive after a flip
9573          * to the same address. We could address this by checking for a
9574          * non-incrementing frame counter.
9575          */
9576         return addr == work->gtt_offset;
9577 }
9578
9579 void intel_check_page_flip(struct drm_device *dev, int pipe)
9580 {
9581         struct drm_i915_private *dev_priv = dev->dev_private;
9582         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9583         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9584
9585         WARN_ON(!in_irq());
9586
9587         if (crtc == NULL)
9588                 return;
9589
9590         spin_lock(&dev->event_lock);
9591         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9592                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9593                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9594                 page_flip_completed(intel_crtc);
9595         }
9596         spin_unlock(&dev->event_lock);
9597 }
9598
9599 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9600                                 struct drm_framebuffer *fb,
9601                                 struct drm_pending_vblank_event *event,
9602                                 uint32_t page_flip_flags)
9603 {
9604         struct drm_device *dev = crtc->dev;
9605         struct drm_i915_private *dev_priv = dev->dev_private;
9606         struct drm_framebuffer *old_fb = crtc->primary->fb;
9607         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9609         enum pipe pipe = intel_crtc->pipe;
9610         struct intel_unpin_work *work;
9611         struct intel_engine_cs *ring;
9612         int ret;
9613
9614         /*
9615          * drm_mode_page_flip_ioctl() should already catch this, but double
9616          * check to be safe.  In the future we may enable pageflipping from
9617          * a disabled primary plane.
9618          */
9619         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9620                 return -EBUSY;
9621
9622         /* Can't change pixel format via MI display flips. */
9623         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9624                 return -EINVAL;
9625
9626         /*
9627          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9628          * Note that pitch changes could also affect these register.
9629          */
9630         if (INTEL_INFO(dev)->gen > 3 &&
9631             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9632              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9633                 return -EINVAL;
9634
9635         if (i915_terminally_wedged(&dev_priv->gpu_error))
9636                 goto out_hang;
9637
9638         work = kzalloc(sizeof(*work), GFP_KERNEL);
9639         if (work == NULL)
9640                 return -ENOMEM;
9641
9642         work->event = event;
9643         work->crtc = crtc;
9644         work->old_fb_obj = intel_fb_obj(old_fb);
9645         INIT_WORK(&work->work, intel_unpin_work_fn);
9646
9647         ret = drm_crtc_vblank_get(crtc);
9648         if (ret)
9649                 goto free_work;
9650
9651         /* We borrow the event spin lock for protecting unpin_work */
9652         spin_lock_irq(&dev->event_lock);
9653         if (intel_crtc->unpin_work) {
9654                 /* Before declaring the flip queue wedged, check if
9655                  * the hardware completed the operation behind our backs.
9656                  */
9657                 if (__intel_pageflip_stall_check(dev, crtc)) {
9658                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9659                         page_flip_completed(intel_crtc);
9660                 } else {
9661                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9662                         spin_unlock_irq(&dev->event_lock);
9663
9664                         drm_crtc_vblank_put(crtc);
9665                         kfree(work);
9666                         return -EBUSY;
9667                 }
9668         }
9669         intel_crtc->unpin_work = work;
9670         spin_unlock_irq(&dev->event_lock);
9671
9672         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9673                 flush_workqueue(dev_priv->wq);
9674
9675         ret = i915_mutex_lock_interruptible(dev);
9676         if (ret)
9677                 goto cleanup;
9678
9679         /* Reference the objects for the scheduled work. */
9680         drm_gem_object_reference(&work->old_fb_obj->base);
9681         drm_gem_object_reference(&obj->base);
9682
9683         crtc->primary->fb = fb;
9684
9685         work->pending_flip_obj = obj;
9686
9687         atomic_inc(&intel_crtc->unpin_work_count);
9688         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9689
9690         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9691                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9692
9693         if (IS_VALLEYVIEW(dev)) {
9694                 ring = &dev_priv->ring[BCS];
9695                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9696                         /* vlv: DISPLAY_FLIP fails to change tiling */
9697                         ring = NULL;
9698         } else if (IS_IVYBRIDGE(dev)) {
9699                 ring = &dev_priv->ring[BCS];
9700         } else if (INTEL_INFO(dev)->gen >= 7) {
9701                 ring = obj->ring;
9702                 if (ring == NULL || ring->id != RCS)
9703                         ring = &dev_priv->ring[BCS];
9704         } else {
9705                 ring = &dev_priv->ring[RCS];
9706         }
9707
9708         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9709         if (ret)
9710                 goto cleanup_pending;
9711
9712         work->gtt_offset =
9713                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9714
9715         if (use_mmio_flip(ring, obj)) {
9716                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9717                                             page_flip_flags);
9718                 if (ret)
9719                         goto cleanup_unpin;
9720
9721                 work->flip_queued_seqno = obj->last_write_seqno;
9722                 work->flip_queued_ring = obj->ring;
9723         } else {
9724                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9725                                                    page_flip_flags);
9726                 if (ret)
9727                         goto cleanup_unpin;
9728
9729                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9730                 work->flip_queued_ring = ring;
9731         }
9732
9733         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9734         work->enable_stall_check = true;
9735
9736         i915_gem_track_fb(work->old_fb_obj, obj,
9737                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9738
9739         intel_disable_fbc(dev);
9740         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9741         mutex_unlock(&dev->struct_mutex);
9742
9743         trace_i915_flip_request(intel_crtc->plane, obj);
9744
9745         return 0;
9746
9747 cleanup_unpin:
9748         intel_unpin_fb_obj(obj);
9749 cleanup_pending:
9750         atomic_dec(&intel_crtc->unpin_work_count);
9751         crtc->primary->fb = old_fb;
9752         drm_gem_object_unreference(&work->old_fb_obj->base);
9753         drm_gem_object_unreference(&obj->base);
9754         mutex_unlock(&dev->struct_mutex);
9755
9756 cleanup:
9757         spin_lock_irq(&dev->event_lock);
9758         intel_crtc->unpin_work = NULL;
9759         spin_unlock_irq(&dev->event_lock);
9760
9761         drm_crtc_vblank_put(crtc);
9762 free_work:
9763         kfree(work);
9764
9765         if (ret == -EIO) {
9766 out_hang:
9767                 intel_crtc_wait_for_pending_flips(crtc);
9768                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9769                 if (ret == 0 && event) {
9770                         spin_lock_irq(&dev->event_lock);
9771                         drm_send_vblank_event(dev, pipe, event);
9772                         spin_unlock_irq(&dev->event_lock);
9773                 }
9774         }
9775         return ret;
9776 }
9777
9778 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9779         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9780         .load_lut = intel_crtc_load_lut,
9781 };
9782
9783 /**
9784  * intel_modeset_update_staged_output_state
9785  *
9786  * Updates the staged output configuration state, e.g. after we've read out the
9787  * current hw state.
9788  */
9789 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9790 {
9791         struct intel_crtc *crtc;
9792         struct intel_encoder *encoder;
9793         struct intel_connector *connector;
9794
9795         list_for_each_entry(connector, &dev->mode_config.connector_list,
9796                             base.head) {
9797                 connector->new_encoder =
9798                         to_intel_encoder(connector->base.encoder);
9799         }
9800
9801         for_each_intel_encoder(dev, encoder) {
9802                 encoder->new_crtc =
9803                         to_intel_crtc(encoder->base.crtc);
9804         }
9805
9806         for_each_intel_crtc(dev, crtc) {
9807                 crtc->new_enabled = crtc->base.enabled;
9808
9809                 if (crtc->new_enabled)
9810                         crtc->new_config = &crtc->config;
9811                 else
9812                         crtc->new_config = NULL;
9813         }
9814 }
9815
9816 /**
9817  * intel_modeset_commit_output_state
9818  *
9819  * This function copies the stage display pipe configuration to the real one.
9820  */
9821 static void intel_modeset_commit_output_state(struct drm_device *dev)
9822 {
9823         struct intel_crtc *crtc;
9824         struct intel_encoder *encoder;
9825         struct intel_connector *connector;
9826
9827         list_for_each_entry(connector, &dev->mode_config.connector_list,
9828                             base.head) {
9829                 connector->base.encoder = &connector->new_encoder->base;
9830         }
9831
9832         for_each_intel_encoder(dev, encoder) {
9833                 encoder->base.crtc = &encoder->new_crtc->base;
9834         }
9835
9836         for_each_intel_crtc(dev, crtc) {
9837                 crtc->base.enabled = crtc->new_enabled;
9838         }
9839 }
9840
9841 static void
9842 connected_sink_compute_bpp(struct intel_connector *connector,
9843                            struct intel_crtc_config *pipe_config)
9844 {
9845         int bpp = pipe_config->pipe_bpp;
9846
9847         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9848                 connector->base.base.id,
9849                 connector->base.name);
9850
9851         /* Don't use an invalid EDID bpc value */
9852         if (connector->base.display_info.bpc &&
9853             connector->base.display_info.bpc * 3 < bpp) {
9854                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9855                               bpp, connector->base.display_info.bpc*3);
9856                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9857         }
9858
9859         /* Clamp bpp to 8 on screens without EDID 1.4 */
9860         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9861                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9862                               bpp);
9863                 pipe_config->pipe_bpp = 24;
9864         }
9865 }
9866
9867 static int
9868 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9869                           struct drm_framebuffer *fb,
9870                           struct intel_crtc_config *pipe_config)
9871 {
9872         struct drm_device *dev = crtc->base.dev;
9873         struct intel_connector *connector;
9874         int bpp;
9875
9876         switch (fb->pixel_format) {
9877         case DRM_FORMAT_C8:
9878                 bpp = 8*3; /* since we go through a colormap */
9879                 break;
9880         case DRM_FORMAT_XRGB1555:
9881         case DRM_FORMAT_ARGB1555:
9882                 /* checked in intel_framebuffer_init already */
9883                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9884                         return -EINVAL;
9885         case DRM_FORMAT_RGB565:
9886                 bpp = 6*3; /* min is 18bpp */
9887                 break;
9888         case DRM_FORMAT_XBGR8888:
9889         case DRM_FORMAT_ABGR8888:
9890                 /* checked in intel_framebuffer_init already */
9891                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9892                         return -EINVAL;
9893         case DRM_FORMAT_XRGB8888:
9894         case DRM_FORMAT_ARGB8888:
9895                 bpp = 8*3;
9896                 break;
9897         case DRM_FORMAT_XRGB2101010:
9898         case DRM_FORMAT_ARGB2101010:
9899         case DRM_FORMAT_XBGR2101010:
9900         case DRM_FORMAT_ABGR2101010:
9901                 /* checked in intel_framebuffer_init already */
9902                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9903                         return -EINVAL;
9904                 bpp = 10*3;
9905                 break;
9906         /* TODO: gen4+ supports 16 bpc floating point, too. */
9907         default:
9908                 DRM_DEBUG_KMS("unsupported depth\n");
9909                 return -EINVAL;
9910         }
9911
9912         pipe_config->pipe_bpp = bpp;
9913
9914         /* Clamp display bpp to EDID value */
9915         list_for_each_entry(connector, &dev->mode_config.connector_list,
9916                             base.head) {
9917                 if (!connector->new_encoder ||
9918                     connector->new_encoder->new_crtc != crtc)
9919                         continue;
9920
9921                 connected_sink_compute_bpp(connector, pipe_config);
9922         }
9923
9924         return bpp;
9925 }
9926
9927 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9928 {
9929         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9930                         "type: 0x%x flags: 0x%x\n",
9931                 mode->crtc_clock,
9932                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9933                 mode->crtc_hsync_end, mode->crtc_htotal,
9934                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9935                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9936 }
9937
9938 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9939                                    struct intel_crtc_config *pipe_config,
9940                                    const char *context)
9941 {
9942         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9943                       context, pipe_name(crtc->pipe));
9944
9945         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9946         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9947                       pipe_config->pipe_bpp, pipe_config->dither);
9948         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9949                       pipe_config->has_pch_encoder,
9950                       pipe_config->fdi_lanes,
9951                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9952                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9953                       pipe_config->fdi_m_n.tu);
9954         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9955                       pipe_config->has_dp_encoder,
9956                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9957                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9958                       pipe_config->dp_m_n.tu);
9959
9960         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9961                       pipe_config->has_dp_encoder,
9962                       pipe_config->dp_m2_n2.gmch_m,
9963                       pipe_config->dp_m2_n2.gmch_n,
9964                       pipe_config->dp_m2_n2.link_m,
9965                       pipe_config->dp_m2_n2.link_n,
9966                       pipe_config->dp_m2_n2.tu);
9967
9968         DRM_DEBUG_KMS("requested mode:\n");
9969         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9970         DRM_DEBUG_KMS("adjusted mode:\n");
9971         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9972         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9973         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9974         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9975                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9976         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9977                       pipe_config->gmch_pfit.control,
9978                       pipe_config->gmch_pfit.pgm_ratios,
9979                       pipe_config->gmch_pfit.lvds_border_bits);
9980         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9981                       pipe_config->pch_pfit.pos,
9982                       pipe_config->pch_pfit.size,
9983                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9984         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9985         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9986 }
9987
9988 static bool encoders_cloneable(const struct intel_encoder *a,
9989                                const struct intel_encoder *b)
9990 {
9991         /* masks could be asymmetric, so check both ways */
9992         return a == b || (a->cloneable & (1 << b->type) &&
9993                           b->cloneable & (1 << a->type));
9994 }
9995
9996 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9997                                          struct intel_encoder *encoder)
9998 {
9999         struct drm_device *dev = crtc->base.dev;
10000         struct intel_encoder *source_encoder;
10001
10002         for_each_intel_encoder(dev, source_encoder) {
10003                 if (source_encoder->new_crtc != crtc)
10004                         continue;
10005
10006                 if (!encoders_cloneable(encoder, source_encoder))
10007                         return false;
10008         }
10009
10010         return true;
10011 }
10012
10013 static bool check_encoder_cloning(struct intel_crtc *crtc)
10014 {
10015         struct drm_device *dev = crtc->base.dev;
10016         struct intel_encoder *encoder;
10017
10018         for_each_intel_encoder(dev, encoder) {
10019                 if (encoder->new_crtc != crtc)
10020                         continue;
10021
10022                 if (!check_single_encoder_cloning(crtc, encoder))
10023                         return false;
10024         }
10025
10026         return true;
10027 }
10028
10029 static struct intel_crtc_config *
10030 intel_modeset_pipe_config(struct drm_crtc *crtc,
10031                           struct drm_framebuffer *fb,
10032                           struct drm_display_mode *mode)
10033 {
10034         struct drm_device *dev = crtc->dev;
10035         struct intel_encoder *encoder;
10036         struct intel_crtc_config *pipe_config;
10037         int plane_bpp, ret = -EINVAL;
10038         bool retry = true;
10039
10040         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10041                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10042                 return ERR_PTR(-EINVAL);
10043         }
10044
10045         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10046         if (!pipe_config)
10047                 return ERR_PTR(-ENOMEM);
10048
10049         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10050         drm_mode_copy(&pipe_config->requested_mode, mode);
10051
10052         pipe_config->cpu_transcoder =
10053                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10054         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10055
10056         /*
10057          * Sanitize sync polarity flags based on requested ones. If neither
10058          * positive or negative polarity is requested, treat this as meaning
10059          * negative polarity.
10060          */
10061         if (!(pipe_config->adjusted_mode.flags &
10062               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10063                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10064
10065         if (!(pipe_config->adjusted_mode.flags &
10066               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10067                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10068
10069         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10070          * plane pixel format and any sink constraints into account. Returns the
10071          * source plane bpp so that dithering can be selected on mismatches
10072          * after encoders and crtc also have had their say. */
10073         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10074                                               fb, pipe_config);
10075         if (plane_bpp < 0)
10076                 goto fail;
10077
10078         /*
10079          * Determine the real pipe dimensions. Note that stereo modes can
10080          * increase the actual pipe size due to the frame doubling and
10081          * insertion of additional space for blanks between the frame. This
10082          * is stored in the crtc timings. We use the requested mode to do this
10083          * computation to clearly distinguish it from the adjusted mode, which
10084          * can be changed by the connectors in the below retry loop.
10085          */
10086         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10087         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10088         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10089
10090 encoder_retry:
10091         /* Ensure the port clock defaults are reset when retrying. */
10092         pipe_config->port_clock = 0;
10093         pipe_config->pixel_multiplier = 1;
10094
10095         /* Fill in default crtc timings, allow encoders to overwrite them. */
10096         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10097
10098         /* Pass our mode to the connectors and the CRTC to give them a chance to
10099          * adjust it according to limitations or connector properties, and also
10100          * a chance to reject the mode entirely.
10101          */
10102         for_each_intel_encoder(dev, encoder) {
10103
10104                 if (&encoder->new_crtc->base != crtc)
10105                         continue;
10106
10107                 if (!(encoder->compute_config(encoder, pipe_config))) {
10108                         DRM_DEBUG_KMS("Encoder config failure\n");
10109                         goto fail;
10110                 }
10111         }
10112
10113         /* Set default port clock if not overwritten by the encoder. Needs to be
10114          * done afterwards in case the encoder adjusts the mode. */
10115         if (!pipe_config->port_clock)
10116                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10117                         * pipe_config->pixel_multiplier;
10118
10119         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10120         if (ret < 0) {
10121                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10122                 goto fail;
10123         }
10124
10125         if (ret == RETRY) {
10126                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10127                         ret = -EINVAL;
10128                         goto fail;
10129                 }
10130
10131                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10132                 retry = false;
10133                 goto encoder_retry;
10134         }
10135
10136         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10137         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10138                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10139
10140         return pipe_config;
10141 fail:
10142         kfree(pipe_config);
10143         return ERR_PTR(ret);
10144 }
10145
10146 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10147  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10148 static void
10149 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10150                              unsigned *prepare_pipes, unsigned *disable_pipes)
10151 {
10152         struct intel_crtc *intel_crtc;
10153         struct drm_device *dev = crtc->dev;
10154         struct intel_encoder *encoder;
10155         struct intel_connector *connector;
10156         struct drm_crtc *tmp_crtc;
10157
10158         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10159
10160         /* Check which crtcs have changed outputs connected to them, these need
10161          * to be part of the prepare_pipes mask. We don't (yet) support global
10162          * modeset across multiple crtcs, so modeset_pipes will only have one
10163          * bit set at most. */
10164         list_for_each_entry(connector, &dev->mode_config.connector_list,
10165                             base.head) {
10166                 if (connector->base.encoder == &connector->new_encoder->base)
10167                         continue;
10168
10169                 if (connector->base.encoder) {
10170                         tmp_crtc = connector->base.encoder->crtc;
10171
10172                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10173                 }
10174
10175                 if (connector->new_encoder)
10176                         *prepare_pipes |=
10177                                 1 << connector->new_encoder->new_crtc->pipe;
10178         }
10179
10180         for_each_intel_encoder(dev, encoder) {
10181                 if (encoder->base.crtc == &encoder->new_crtc->base)
10182                         continue;
10183
10184                 if (encoder->base.crtc) {
10185                         tmp_crtc = encoder->base.crtc;
10186
10187                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10188                 }
10189
10190                 if (encoder->new_crtc)
10191                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10192         }
10193
10194         /* Check for pipes that will be enabled/disabled ... */
10195         for_each_intel_crtc(dev, intel_crtc) {
10196                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10197                         continue;
10198
10199                 if (!intel_crtc->new_enabled)
10200                         *disable_pipes |= 1 << intel_crtc->pipe;
10201                 else
10202                         *prepare_pipes |= 1 << intel_crtc->pipe;
10203         }
10204
10205
10206         /* set_mode is also used to update properties on life display pipes. */
10207         intel_crtc = to_intel_crtc(crtc);
10208         if (intel_crtc->new_enabled)
10209                 *prepare_pipes |= 1 << intel_crtc->pipe;
10210
10211         /*
10212          * For simplicity do a full modeset on any pipe where the output routing
10213          * changed. We could be more clever, but that would require us to be
10214          * more careful with calling the relevant encoder->mode_set functions.
10215          */
10216         if (*prepare_pipes)
10217                 *modeset_pipes = *prepare_pipes;
10218
10219         /* ... and mask these out. */
10220         *modeset_pipes &= ~(*disable_pipes);
10221         *prepare_pipes &= ~(*disable_pipes);
10222
10223         /*
10224          * HACK: We don't (yet) fully support global modesets. intel_set_config
10225          * obies this rule, but the modeset restore mode of
10226          * intel_modeset_setup_hw_state does not.
10227          */
10228         *modeset_pipes &= 1 << intel_crtc->pipe;
10229         *prepare_pipes &= 1 << intel_crtc->pipe;
10230
10231         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10232                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10233 }
10234
10235 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10236 {
10237         struct drm_encoder *encoder;
10238         struct drm_device *dev = crtc->dev;
10239
10240         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10241                 if (encoder->crtc == crtc)
10242                         return true;
10243
10244         return false;
10245 }
10246
10247 static void
10248 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10249 {
10250         struct intel_encoder *intel_encoder;
10251         struct intel_crtc *intel_crtc;
10252         struct drm_connector *connector;
10253
10254         for_each_intel_encoder(dev, intel_encoder) {
10255                 if (!intel_encoder->base.crtc)
10256                         continue;
10257
10258                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10259
10260                 if (prepare_pipes & (1 << intel_crtc->pipe))
10261                         intel_encoder->connectors_active = false;
10262         }
10263
10264         intel_modeset_commit_output_state(dev);
10265
10266         /* Double check state. */
10267         for_each_intel_crtc(dev, intel_crtc) {
10268                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10269                 WARN_ON(intel_crtc->new_config &&
10270                         intel_crtc->new_config != &intel_crtc->config);
10271                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10272         }
10273
10274         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10275                 if (!connector->encoder || !connector->encoder->crtc)
10276                         continue;
10277
10278                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10279
10280                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10281                         struct drm_property *dpms_property =
10282                                 dev->mode_config.dpms_property;
10283
10284                         connector->dpms = DRM_MODE_DPMS_ON;
10285                         drm_object_property_set_value(&connector->base,
10286                                                          dpms_property,
10287                                                          DRM_MODE_DPMS_ON);
10288
10289                         intel_encoder = to_intel_encoder(connector->encoder);
10290                         intel_encoder->connectors_active = true;
10291                 }
10292         }
10293
10294 }
10295
10296 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10297 {
10298         int diff;
10299
10300         if (clock1 == clock2)
10301                 return true;
10302
10303         if (!clock1 || !clock2)
10304                 return false;
10305
10306         diff = abs(clock1 - clock2);
10307
10308         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10309                 return true;
10310
10311         return false;
10312 }
10313
10314 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10315         list_for_each_entry((intel_crtc), \
10316                             &(dev)->mode_config.crtc_list, \
10317                             base.head) \
10318                 if (mask & (1 <<(intel_crtc)->pipe))
10319
10320 static bool
10321 intel_pipe_config_compare(struct drm_device *dev,
10322                           struct intel_crtc_config *current_config,
10323                           struct intel_crtc_config *pipe_config)
10324 {
10325 #define PIPE_CONF_CHECK_X(name) \
10326         if (current_config->name != pipe_config->name) { \
10327                 DRM_ERROR("mismatch in " #name " " \
10328                           "(expected 0x%08x, found 0x%08x)\n", \
10329                           current_config->name, \
10330                           pipe_config->name); \
10331                 return false; \
10332         }
10333
10334 #define PIPE_CONF_CHECK_I(name) \
10335         if (current_config->name != pipe_config->name) { \
10336                 DRM_ERROR("mismatch in " #name " " \
10337                           "(expected %i, found %i)\n", \
10338                           current_config->name, \
10339                           pipe_config->name); \
10340                 return false; \
10341         }
10342
10343 /* This is required for BDW+ where there is only one set of registers for
10344  * switching between high and low RR.
10345  * This macro can be used whenever a comparison has to be made between one
10346  * hw state and multiple sw state variables.
10347  */
10348 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10349         if ((current_config->name != pipe_config->name) && \
10350                 (current_config->alt_name != pipe_config->name)) { \
10351                         DRM_ERROR("mismatch in " #name " " \
10352                                   "(expected %i or %i, found %i)\n", \
10353                                   current_config->name, \
10354                                   current_config->alt_name, \
10355                                   pipe_config->name); \
10356                         return false; \
10357         }
10358
10359 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10360         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10361                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10362                           "(expected %i, found %i)\n", \
10363                           current_config->name & (mask), \
10364                           pipe_config->name & (mask)); \
10365                 return false; \
10366         }
10367
10368 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10369         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10370                 DRM_ERROR("mismatch in " #name " " \
10371                           "(expected %i, found %i)\n", \
10372                           current_config->name, \
10373                           pipe_config->name); \
10374                 return false; \
10375         }
10376
10377 #define PIPE_CONF_QUIRK(quirk)  \
10378         ((current_config->quirks | pipe_config->quirks) & (quirk))
10379
10380         PIPE_CONF_CHECK_I(cpu_transcoder);
10381
10382         PIPE_CONF_CHECK_I(has_pch_encoder);
10383         PIPE_CONF_CHECK_I(fdi_lanes);
10384         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10385         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10386         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10387         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10388         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10389
10390         PIPE_CONF_CHECK_I(has_dp_encoder);
10391
10392         if (INTEL_INFO(dev)->gen < 8) {
10393                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10394                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10395                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10396                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10397                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10398
10399                 if (current_config->has_drrs) {
10400                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10401                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10402                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10403                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10404                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10405                 }
10406         } else {
10407                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10408                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10409                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10410                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10411                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10412         }
10413
10414         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10415         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10416         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10417         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10418         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10419         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10420
10421         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10422         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10423         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10424         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10425         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10426         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10427
10428         PIPE_CONF_CHECK_I(pixel_multiplier);
10429         PIPE_CONF_CHECK_I(has_hdmi_sink);
10430         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10431             IS_VALLEYVIEW(dev))
10432                 PIPE_CONF_CHECK_I(limited_color_range);
10433
10434         PIPE_CONF_CHECK_I(has_audio);
10435
10436         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10437                               DRM_MODE_FLAG_INTERLACE);
10438
10439         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10440                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10441                                       DRM_MODE_FLAG_PHSYNC);
10442                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10443                                       DRM_MODE_FLAG_NHSYNC);
10444                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10445                                       DRM_MODE_FLAG_PVSYNC);
10446                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10447                                       DRM_MODE_FLAG_NVSYNC);
10448         }
10449
10450         PIPE_CONF_CHECK_I(pipe_src_w);
10451         PIPE_CONF_CHECK_I(pipe_src_h);
10452
10453         /*
10454          * FIXME: BIOS likes to set up a cloned config with lvds+external
10455          * screen. Since we don't yet re-compute the pipe config when moving
10456          * just the lvds port away to another pipe the sw tracking won't match.
10457          *
10458          * Proper atomic modesets with recomputed global state will fix this.
10459          * Until then just don't check gmch state for inherited modes.
10460          */
10461         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10462                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10463                 /* pfit ratios are autocomputed by the hw on gen4+ */
10464                 if (INTEL_INFO(dev)->gen < 4)
10465                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10466                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10467         }
10468
10469         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10470         if (current_config->pch_pfit.enabled) {
10471                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10472                 PIPE_CONF_CHECK_I(pch_pfit.size);
10473         }
10474
10475         /* BDW+ don't expose a synchronous way to read the state */
10476         if (IS_HASWELL(dev))
10477                 PIPE_CONF_CHECK_I(ips_enabled);
10478
10479         PIPE_CONF_CHECK_I(double_wide);
10480
10481         PIPE_CONF_CHECK_X(ddi_pll_sel);
10482
10483         PIPE_CONF_CHECK_I(shared_dpll);
10484         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10485         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10486         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10487         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10488         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10489
10490         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10491                 PIPE_CONF_CHECK_I(pipe_bpp);
10492
10493         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10494         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10495
10496 #undef PIPE_CONF_CHECK_X
10497 #undef PIPE_CONF_CHECK_I
10498 #undef PIPE_CONF_CHECK_I_ALT
10499 #undef PIPE_CONF_CHECK_FLAGS
10500 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10501 #undef PIPE_CONF_QUIRK
10502
10503         return true;
10504 }
10505
10506 static void
10507 check_connector_state(struct drm_device *dev)
10508 {
10509         struct intel_connector *connector;
10510
10511         list_for_each_entry(connector, &dev->mode_config.connector_list,
10512                             base.head) {
10513                 /* This also checks the encoder/connector hw state with the
10514                  * ->get_hw_state callbacks. */
10515                 intel_connector_check_state(connector);
10516
10517                 WARN(&connector->new_encoder->base != connector->base.encoder,
10518                      "connector's staged encoder doesn't match current encoder\n");
10519         }
10520 }
10521
10522 static void
10523 check_encoder_state(struct drm_device *dev)
10524 {
10525         struct intel_encoder *encoder;
10526         struct intel_connector *connector;
10527
10528         for_each_intel_encoder(dev, encoder) {
10529                 bool enabled = false;
10530                 bool active = false;
10531                 enum pipe pipe, tracked_pipe;
10532
10533                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10534                               encoder->base.base.id,
10535                               encoder->base.name);
10536
10537                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10538                      "encoder's stage crtc doesn't match current crtc\n");
10539                 WARN(encoder->connectors_active && !encoder->base.crtc,
10540                      "encoder's active_connectors set, but no crtc\n");
10541
10542                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10543                                     base.head) {
10544                         if (connector->base.encoder != &encoder->base)
10545                                 continue;
10546                         enabled = true;
10547                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10548                                 active = true;
10549                 }
10550                 /*
10551                  * for MST connectors if we unplug the connector is gone
10552                  * away but the encoder is still connected to a crtc
10553                  * until a modeset happens in response to the hotplug.
10554                  */
10555                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10556                         continue;
10557
10558                 WARN(!!encoder->base.crtc != enabled,
10559                      "encoder's enabled state mismatch "
10560                      "(expected %i, found %i)\n",
10561                      !!encoder->base.crtc, enabled);
10562                 WARN(active && !encoder->base.crtc,
10563                      "active encoder with no crtc\n");
10564
10565                 WARN(encoder->connectors_active != active,
10566                      "encoder's computed active state doesn't match tracked active state "
10567                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10568
10569                 active = encoder->get_hw_state(encoder, &pipe);
10570                 WARN(active != encoder->connectors_active,
10571                      "encoder's hw state doesn't match sw tracking "
10572                      "(expected %i, found %i)\n",
10573                      encoder->connectors_active, active);
10574
10575                 if (!encoder->base.crtc)
10576                         continue;
10577
10578                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10579                 WARN(active && pipe != tracked_pipe,
10580                      "active encoder's pipe doesn't match"
10581                      "(expected %i, found %i)\n",
10582                      tracked_pipe, pipe);
10583
10584         }
10585 }
10586
10587 static void
10588 check_crtc_state(struct drm_device *dev)
10589 {
10590         struct drm_i915_private *dev_priv = dev->dev_private;
10591         struct intel_crtc *crtc;
10592         struct intel_encoder *encoder;
10593         struct intel_crtc_config pipe_config;
10594
10595         for_each_intel_crtc(dev, crtc) {
10596                 bool enabled = false;
10597                 bool active = false;
10598
10599                 memset(&pipe_config, 0, sizeof(pipe_config));
10600
10601                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10602                               crtc->base.base.id);
10603
10604                 WARN(crtc->active && !crtc->base.enabled,
10605                      "active crtc, but not enabled in sw tracking\n");
10606
10607                 for_each_intel_encoder(dev, encoder) {
10608                         if (encoder->base.crtc != &crtc->base)
10609                                 continue;
10610                         enabled = true;
10611                         if (encoder->connectors_active)
10612                                 active = true;
10613                 }
10614
10615                 WARN(active != crtc->active,
10616                      "crtc's computed active state doesn't match tracked active state "
10617                      "(expected %i, found %i)\n", active, crtc->active);
10618                 WARN(enabled != crtc->base.enabled,
10619                      "crtc's computed enabled state doesn't match tracked enabled state "
10620                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10621
10622                 active = dev_priv->display.get_pipe_config(crtc,
10623                                                            &pipe_config);
10624
10625                 /* hw state is inconsistent with the pipe quirk */
10626                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10627                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10628                         active = crtc->active;
10629
10630                 for_each_intel_encoder(dev, encoder) {
10631                         enum pipe pipe;
10632                         if (encoder->base.crtc != &crtc->base)
10633                                 continue;
10634                         if (encoder->get_hw_state(encoder, &pipe))
10635                                 encoder->get_config(encoder, &pipe_config);
10636                 }
10637
10638                 WARN(crtc->active != active,
10639                      "crtc active state doesn't match with hw state "
10640                      "(expected %i, found %i)\n", crtc->active, active);
10641
10642                 if (active &&
10643                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10644                         WARN(1, "pipe state doesn't match!\n");
10645                         intel_dump_pipe_config(crtc, &pipe_config,
10646                                                "[hw state]");
10647                         intel_dump_pipe_config(crtc, &crtc->config,
10648                                                "[sw state]");
10649                 }
10650         }
10651 }
10652
10653 static void
10654 check_shared_dpll_state(struct drm_device *dev)
10655 {
10656         struct drm_i915_private *dev_priv = dev->dev_private;
10657         struct intel_crtc *crtc;
10658         struct intel_dpll_hw_state dpll_hw_state;
10659         int i;
10660
10661         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10662                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10663                 int enabled_crtcs = 0, active_crtcs = 0;
10664                 bool active;
10665
10666                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10667
10668                 DRM_DEBUG_KMS("%s\n", pll->name);
10669
10670                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10671
10672                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10673                      "more active pll users than references: %i vs %i\n",
10674                      pll->active, hweight32(pll->config.crtc_mask));
10675                 WARN(pll->active && !pll->on,
10676                      "pll in active use but not on in sw tracking\n");
10677                 WARN(pll->on && !pll->active,
10678                      "pll in on but not on in use in sw tracking\n");
10679                 WARN(pll->on != active,
10680                      "pll on state mismatch (expected %i, found %i)\n",
10681                      pll->on, active);
10682
10683                 for_each_intel_crtc(dev, crtc) {
10684                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10685                                 enabled_crtcs++;
10686                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10687                                 active_crtcs++;
10688                 }
10689                 WARN(pll->active != active_crtcs,
10690                      "pll active crtcs mismatch (expected %i, found %i)\n",
10691                      pll->active, active_crtcs);
10692                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10693                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10694                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10695
10696                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10697                                        sizeof(dpll_hw_state)),
10698                      "pll hw state mismatch\n");
10699         }
10700 }
10701
10702 void
10703 intel_modeset_check_state(struct drm_device *dev)
10704 {
10705         check_connector_state(dev);
10706         check_encoder_state(dev);
10707         check_crtc_state(dev);
10708         check_shared_dpll_state(dev);
10709 }
10710
10711 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10712                                      int dotclock)
10713 {
10714         /*
10715          * FDI already provided one idea for the dotclock.
10716          * Yell if the encoder disagrees.
10717          */
10718         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10719              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10720              pipe_config->adjusted_mode.crtc_clock, dotclock);
10721 }
10722
10723 static void update_scanline_offset(struct intel_crtc *crtc)
10724 {
10725         struct drm_device *dev = crtc->base.dev;
10726
10727         /*
10728          * The scanline counter increments at the leading edge of hsync.
10729          *
10730          * On most platforms it starts counting from vtotal-1 on the
10731          * first active line. That means the scanline counter value is
10732          * always one less than what we would expect. Ie. just after
10733          * start of vblank, which also occurs at start of hsync (on the
10734          * last active line), the scanline counter will read vblank_start-1.
10735          *
10736          * On gen2 the scanline counter starts counting from 1 instead
10737          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10738          * to keep the value positive), instead of adding one.
10739          *
10740          * On HSW+ the behaviour of the scanline counter depends on the output
10741          * type. For DP ports it behaves like most other platforms, but on HDMI
10742          * there's an extra 1 line difference. So we need to add two instead of
10743          * one to the value.
10744          */
10745         if (IS_GEN2(dev)) {
10746                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10747                 int vtotal;
10748
10749                 vtotal = mode->crtc_vtotal;
10750                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10751                         vtotal /= 2;
10752
10753                 crtc->scanline_offset = vtotal - 1;
10754         } else if (HAS_DDI(dev) &&
10755                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10756                 crtc->scanline_offset = 2;
10757         } else
10758                 crtc->scanline_offset = 1;
10759 }
10760
10761 static int __intel_set_mode(struct drm_crtc *crtc,
10762                             struct drm_display_mode *mode,
10763                             int x, int y, struct drm_framebuffer *fb)
10764 {
10765         struct drm_device *dev = crtc->dev;
10766         struct drm_i915_private *dev_priv = dev->dev_private;
10767         struct drm_display_mode *saved_mode;
10768         struct intel_crtc_config *pipe_config = NULL;
10769         struct intel_crtc *intel_crtc;
10770         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10771         int ret = 0;
10772
10773         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10774         if (!saved_mode)
10775                 return -ENOMEM;
10776
10777         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10778                                      &prepare_pipes, &disable_pipes);
10779
10780         *saved_mode = crtc->mode;
10781
10782         /* Hack: Because we don't (yet) support global modeset on multiple
10783          * crtcs, we don't keep track of the new mode for more than one crtc.
10784          * Hence simply check whether any bit is set in modeset_pipes in all the
10785          * pieces of code that are not yet converted to deal with mutliple crtcs
10786          * changing their mode at the same time. */
10787         if (modeset_pipes) {
10788                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10789                 if (IS_ERR(pipe_config)) {
10790                         ret = PTR_ERR(pipe_config);
10791                         pipe_config = NULL;
10792
10793                         goto out;
10794                 }
10795                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10796                                        "[modeset]");
10797                 to_intel_crtc(crtc)->new_config = pipe_config;
10798         }
10799
10800         /*
10801          * See if the config requires any additional preparation, e.g.
10802          * to adjust global state with pipes off.  We need to do this
10803          * here so we can get the modeset_pipe updated config for the new
10804          * mode set on this crtc.  For other crtcs we need to use the
10805          * adjusted_mode bits in the crtc directly.
10806          */
10807         if (IS_VALLEYVIEW(dev)) {
10808                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10809
10810                 /* may have added more to prepare_pipes than we should */
10811                 prepare_pipes &= ~disable_pipes;
10812         }
10813
10814         if (dev_priv->display.crtc_compute_clock) {
10815                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10816
10817                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10818                 if (ret)
10819                         goto done;
10820
10821                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10822                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10823                         if (ret) {
10824                                 intel_shared_dpll_abort_config(dev_priv);
10825                                 goto done;
10826                         }
10827                 }
10828         }
10829
10830         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10831                 intel_crtc_disable(&intel_crtc->base);
10832
10833         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10834                 if (intel_crtc->base.enabled)
10835                         dev_priv->display.crtc_disable(&intel_crtc->base);
10836         }
10837
10838         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10839          * to set it here already despite that we pass it down the callchain.
10840          */
10841         if (modeset_pipes) {
10842                 crtc->mode = *mode;
10843                 /* mode_set/enable/disable functions rely on a correct pipe
10844                  * config. */
10845                 to_intel_crtc(crtc)->config = *pipe_config;
10846                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10847
10848                 /*
10849                  * Calculate and store various constants which
10850                  * are later needed by vblank and swap-completion
10851                  * timestamping. They are derived from true hwmode.
10852                  */
10853                 drm_calc_timestamping_constants(crtc,
10854                                                 &pipe_config->adjusted_mode);
10855         }
10856
10857         if (dev_priv->display.crtc_compute_clock)
10858                 intel_shared_dpll_commit(dev_priv);
10859
10860         /* Only after disabling all output pipelines that will be changed can we
10861          * update the the output configuration. */
10862         intel_modeset_update_state(dev, prepare_pipes);
10863
10864         if (dev_priv->display.modeset_global_resources)
10865                 dev_priv->display.modeset_global_resources(dev);
10866
10867         /* Set up the DPLL and any encoders state that needs to adjust or depend
10868          * on the DPLL.
10869          */
10870         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10871                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10872                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10873                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10874
10875                 mutex_lock(&dev->struct_mutex);
10876                 ret = intel_pin_and_fence_fb_obj(dev,
10877                                                  obj,
10878                                                  NULL);
10879                 if (ret != 0) {
10880                         DRM_ERROR("pin & fence failed\n");
10881                         mutex_unlock(&dev->struct_mutex);
10882                         goto done;
10883                 }
10884                 if (old_fb)
10885                         intel_unpin_fb_obj(old_obj);
10886                 i915_gem_track_fb(old_obj, obj,
10887                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10888                 mutex_unlock(&dev->struct_mutex);
10889
10890                 crtc->primary->fb = fb;
10891                 crtc->x = x;
10892                 crtc->y = y;
10893
10894                 if (dev_priv->display.crtc_mode_set) {
10895                         ret = dev_priv->display.crtc_mode_set(intel_crtc,
10896                                                               x, y, fb);
10897                         if (ret)
10898                                 goto done;
10899                 }
10900         }
10901
10902         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10903         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10904                 update_scanline_offset(intel_crtc);
10905
10906                 dev_priv->display.crtc_enable(&intel_crtc->base);
10907         }
10908
10909         /* FIXME: add subpixel order */
10910 done:
10911         if (ret && crtc->enabled)
10912                 crtc->mode = *saved_mode;
10913
10914 out:
10915         kfree(pipe_config);
10916         kfree(saved_mode);
10917         return ret;
10918 }
10919
10920 static int intel_set_mode(struct drm_crtc *crtc,
10921                           struct drm_display_mode *mode,
10922                           int x, int y, struct drm_framebuffer *fb)
10923 {
10924         int ret;
10925
10926         ret = __intel_set_mode(crtc, mode, x, y, fb);
10927
10928         if (ret == 0)
10929                 intel_modeset_check_state(crtc->dev);
10930
10931         return ret;
10932 }
10933
10934 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10935 {
10936         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10937 }
10938
10939 #undef for_each_intel_crtc_masked
10940
10941 static void intel_set_config_free(struct intel_set_config *config)
10942 {
10943         if (!config)
10944                 return;
10945
10946         kfree(config->save_connector_encoders);
10947         kfree(config->save_encoder_crtcs);
10948         kfree(config->save_crtc_enabled);
10949         kfree(config);
10950 }
10951
10952 static int intel_set_config_save_state(struct drm_device *dev,
10953                                        struct intel_set_config *config)
10954 {
10955         struct drm_crtc *crtc;
10956         struct drm_encoder *encoder;
10957         struct drm_connector *connector;
10958         int count;
10959
10960         config->save_crtc_enabled =
10961                 kcalloc(dev->mode_config.num_crtc,
10962                         sizeof(bool), GFP_KERNEL);
10963         if (!config->save_crtc_enabled)
10964                 return -ENOMEM;
10965
10966         config->save_encoder_crtcs =
10967                 kcalloc(dev->mode_config.num_encoder,
10968                         sizeof(struct drm_crtc *), GFP_KERNEL);
10969         if (!config->save_encoder_crtcs)
10970                 return -ENOMEM;
10971
10972         config->save_connector_encoders =
10973                 kcalloc(dev->mode_config.num_connector,
10974                         sizeof(struct drm_encoder *), GFP_KERNEL);
10975         if (!config->save_connector_encoders)
10976                 return -ENOMEM;
10977
10978         /* Copy data. Note that driver private data is not affected.
10979          * Should anything bad happen only the expected state is
10980          * restored, not the drivers personal bookkeeping.
10981          */
10982         count = 0;
10983         for_each_crtc(dev, crtc) {
10984                 config->save_crtc_enabled[count++] = crtc->enabled;
10985         }
10986
10987         count = 0;
10988         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10989                 config->save_encoder_crtcs[count++] = encoder->crtc;
10990         }
10991
10992         count = 0;
10993         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10994                 config->save_connector_encoders[count++] = connector->encoder;
10995         }
10996
10997         return 0;
10998 }
10999
11000 static void intel_set_config_restore_state(struct drm_device *dev,
11001                                            struct intel_set_config *config)
11002 {
11003         struct intel_crtc *crtc;
11004         struct intel_encoder *encoder;
11005         struct intel_connector *connector;
11006         int count;
11007
11008         count = 0;
11009         for_each_intel_crtc(dev, crtc) {
11010                 crtc->new_enabled = config->save_crtc_enabled[count++];
11011
11012                 if (crtc->new_enabled)
11013                         crtc->new_config = &crtc->config;
11014                 else
11015                         crtc->new_config = NULL;
11016         }
11017
11018         count = 0;
11019         for_each_intel_encoder(dev, encoder) {
11020                 encoder->new_crtc =
11021                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11022         }
11023
11024         count = 0;
11025         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11026                 connector->new_encoder =
11027                         to_intel_encoder(config->save_connector_encoders[count++]);
11028         }
11029 }
11030
11031 static bool
11032 is_crtc_connector_off(struct drm_mode_set *set)
11033 {
11034         int i;
11035
11036         if (set->num_connectors == 0)
11037                 return false;
11038
11039         if (WARN_ON(set->connectors == NULL))
11040                 return false;
11041
11042         for (i = 0; i < set->num_connectors; i++)
11043                 if (set->connectors[i]->encoder &&
11044                     set->connectors[i]->encoder->crtc == set->crtc &&
11045                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11046                         return true;
11047
11048         return false;
11049 }
11050
11051 static void
11052 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11053                                       struct intel_set_config *config)
11054 {
11055
11056         /* We should be able to check here if the fb has the same properties
11057          * and then just flip_or_move it */
11058         if (is_crtc_connector_off(set)) {
11059                 config->mode_changed = true;
11060         } else if (set->crtc->primary->fb != set->fb) {
11061                 /*
11062                  * If we have no fb, we can only flip as long as the crtc is
11063                  * active, otherwise we need a full mode set.  The crtc may
11064                  * be active if we've only disabled the primary plane, or
11065                  * in fastboot situations.
11066                  */
11067                 if (set->crtc->primary->fb == NULL) {
11068                         struct intel_crtc *intel_crtc =
11069                                 to_intel_crtc(set->crtc);
11070
11071                         if (intel_crtc->active) {
11072                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11073                                 config->fb_changed = true;
11074                         } else {
11075                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11076                                 config->mode_changed = true;
11077                         }
11078                 } else if (set->fb == NULL) {
11079                         config->mode_changed = true;
11080                 } else if (set->fb->pixel_format !=
11081                            set->crtc->primary->fb->pixel_format) {
11082                         config->mode_changed = true;
11083                 } else {
11084                         config->fb_changed = true;
11085                 }
11086         }
11087
11088         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11089                 config->fb_changed = true;
11090
11091         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11092                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11093                 drm_mode_debug_printmodeline(&set->crtc->mode);
11094                 drm_mode_debug_printmodeline(set->mode);
11095                 config->mode_changed = true;
11096         }
11097
11098         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11099                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11100 }
11101
11102 static int
11103 intel_modeset_stage_output_state(struct drm_device *dev,
11104                                  struct drm_mode_set *set,
11105                                  struct intel_set_config *config)
11106 {
11107         struct intel_connector *connector;
11108         struct intel_encoder *encoder;
11109         struct intel_crtc *crtc;
11110         int ro;
11111
11112         /* The upper layers ensure that we either disable a crtc or have a list
11113          * of connectors. For paranoia, double-check this. */
11114         WARN_ON(!set->fb && (set->num_connectors != 0));
11115         WARN_ON(set->fb && (set->num_connectors == 0));
11116
11117         list_for_each_entry(connector, &dev->mode_config.connector_list,
11118                             base.head) {
11119                 /* Otherwise traverse passed in connector list and get encoders
11120                  * for them. */
11121                 for (ro = 0; ro < set->num_connectors; ro++) {
11122                         if (set->connectors[ro] == &connector->base) {
11123                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11124                                 break;
11125                         }
11126                 }
11127
11128                 /* If we disable the crtc, disable all its connectors. Also, if
11129                  * the connector is on the changing crtc but not on the new
11130                  * connector list, disable it. */
11131                 if ((!set->fb || ro == set->num_connectors) &&
11132                     connector->base.encoder &&
11133                     connector->base.encoder->crtc == set->crtc) {
11134                         connector->new_encoder = NULL;
11135
11136                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11137                                 connector->base.base.id,
11138                                 connector->base.name);
11139                 }
11140
11141
11142                 if (&connector->new_encoder->base != connector->base.encoder) {
11143                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11144                         config->mode_changed = true;
11145                 }
11146         }
11147         /* connector->new_encoder is now updated for all connectors. */
11148
11149         /* Update crtc of enabled connectors. */
11150         list_for_each_entry(connector, &dev->mode_config.connector_list,
11151                             base.head) {
11152                 struct drm_crtc *new_crtc;
11153
11154                 if (!connector->new_encoder)
11155                         continue;
11156
11157                 new_crtc = connector->new_encoder->base.crtc;
11158
11159                 for (ro = 0; ro < set->num_connectors; ro++) {
11160                         if (set->connectors[ro] == &connector->base)
11161                                 new_crtc = set->crtc;
11162                 }
11163
11164                 /* Make sure the new CRTC will work with the encoder */
11165                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11166                                          new_crtc)) {
11167                         return -EINVAL;
11168                 }
11169                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11170
11171                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11172                         connector->base.base.id,
11173                         connector->base.name,
11174                         new_crtc->base.id);
11175         }
11176
11177         /* Check for any encoders that needs to be disabled. */
11178         for_each_intel_encoder(dev, encoder) {
11179                 int num_connectors = 0;
11180                 list_for_each_entry(connector,
11181                                     &dev->mode_config.connector_list,
11182                                     base.head) {
11183                         if (connector->new_encoder == encoder) {
11184                                 WARN_ON(!connector->new_encoder->new_crtc);
11185                                 num_connectors++;
11186                         }
11187                 }
11188
11189                 if (num_connectors == 0)
11190                         encoder->new_crtc = NULL;
11191                 else if (num_connectors > 1)
11192                         return -EINVAL;
11193
11194                 /* Only now check for crtc changes so we don't miss encoders
11195                  * that will be disabled. */
11196                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11197                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11198                         config->mode_changed = true;
11199                 }
11200         }
11201         /* Now we've also updated encoder->new_crtc for all encoders. */
11202         list_for_each_entry(connector, &dev->mode_config.connector_list,
11203                             base.head) {
11204                 if (connector->new_encoder)
11205                         if (connector->new_encoder != connector->encoder)
11206                                 connector->encoder = connector->new_encoder;
11207         }
11208         for_each_intel_crtc(dev, crtc) {
11209                 crtc->new_enabled = false;
11210
11211                 for_each_intel_encoder(dev, encoder) {
11212                         if (encoder->new_crtc == crtc) {
11213                                 crtc->new_enabled = true;
11214                                 break;
11215                         }
11216                 }
11217
11218                 if (crtc->new_enabled != crtc->base.enabled) {
11219                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11220                                       crtc->new_enabled ? "en" : "dis");
11221                         config->mode_changed = true;
11222                 }
11223
11224                 if (crtc->new_enabled)
11225                         crtc->new_config = &crtc->config;
11226                 else
11227                         crtc->new_config = NULL;
11228         }
11229
11230         return 0;
11231 }
11232
11233 static void disable_crtc_nofb(struct intel_crtc *crtc)
11234 {
11235         struct drm_device *dev = crtc->base.dev;
11236         struct intel_encoder *encoder;
11237         struct intel_connector *connector;
11238
11239         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11240                       pipe_name(crtc->pipe));
11241
11242         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11243                 if (connector->new_encoder &&
11244                     connector->new_encoder->new_crtc == crtc)
11245                         connector->new_encoder = NULL;
11246         }
11247
11248         for_each_intel_encoder(dev, encoder) {
11249                 if (encoder->new_crtc == crtc)
11250                         encoder->new_crtc = NULL;
11251         }
11252
11253         crtc->new_enabled = false;
11254         crtc->new_config = NULL;
11255 }
11256
11257 static int intel_crtc_set_config(struct drm_mode_set *set)
11258 {
11259         struct drm_device *dev;
11260         struct drm_mode_set save_set;
11261         struct intel_set_config *config;
11262         int ret;
11263
11264         BUG_ON(!set);
11265         BUG_ON(!set->crtc);
11266         BUG_ON(!set->crtc->helper_private);
11267
11268         /* Enforce sane interface api - has been abused by the fb helper. */
11269         BUG_ON(!set->mode && set->fb);
11270         BUG_ON(set->fb && set->num_connectors == 0);
11271
11272         if (set->fb) {
11273                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11274                                 set->crtc->base.id, set->fb->base.id,
11275                                 (int)set->num_connectors, set->x, set->y);
11276         } else {
11277                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11278         }
11279
11280         dev = set->crtc->dev;
11281
11282         ret = -ENOMEM;
11283         config = kzalloc(sizeof(*config), GFP_KERNEL);
11284         if (!config)
11285                 goto out_config;
11286
11287         ret = intel_set_config_save_state(dev, config);
11288         if (ret)
11289                 goto out_config;
11290
11291         save_set.crtc = set->crtc;
11292         save_set.mode = &set->crtc->mode;
11293         save_set.x = set->crtc->x;
11294         save_set.y = set->crtc->y;
11295         save_set.fb = set->crtc->primary->fb;
11296
11297         /* Compute whether we need a full modeset, only an fb base update or no
11298          * change at all. In the future we might also check whether only the
11299          * mode changed, e.g. for LVDS where we only change the panel fitter in
11300          * such cases. */
11301         intel_set_config_compute_mode_changes(set, config);
11302
11303         ret = intel_modeset_stage_output_state(dev, set, config);
11304         if (ret)
11305                 goto fail;
11306
11307         if (config->mode_changed) {
11308                 ret = intel_set_mode(set->crtc, set->mode,
11309                                      set->x, set->y, set->fb);
11310         } else if (config->fb_changed) {
11311                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11312
11313                 intel_crtc_wait_for_pending_flips(set->crtc);
11314
11315                 ret = intel_pipe_set_base(set->crtc,
11316                                           set->x, set->y, set->fb);
11317
11318                 /*
11319                  * We need to make sure the primary plane is re-enabled if it
11320                  * has previously been turned off.
11321                  */
11322                 if (!intel_crtc->primary_enabled && ret == 0) {
11323                         WARN_ON(!intel_crtc->active);
11324                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11325                 }
11326
11327                 /*
11328                  * In the fastboot case this may be our only check of the
11329                  * state after boot.  It would be better to only do it on
11330                  * the first update, but we don't have a nice way of doing that
11331                  * (and really, set_config isn't used much for high freq page
11332                  * flipping, so increasing its cost here shouldn't be a big
11333                  * deal).
11334                  */
11335                 if (i915.fastboot && ret == 0)
11336                         intel_modeset_check_state(set->crtc->dev);
11337         }
11338
11339         if (ret) {
11340                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11341                               set->crtc->base.id, ret);
11342 fail:
11343                 intel_set_config_restore_state(dev, config);
11344
11345                 /*
11346                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11347                  * force the pipe off to avoid oopsing in the modeset code
11348                  * due to fb==NULL. This should only happen during boot since
11349                  * we don't yet reconstruct the FB from the hardware state.
11350                  */
11351                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11352                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11353
11354                 /* Try to restore the config */
11355                 if (config->mode_changed &&
11356                     intel_set_mode(save_set.crtc, save_set.mode,
11357                                    save_set.x, save_set.y, save_set.fb))
11358                         DRM_ERROR("failed to restore config after modeset failure\n");
11359         }
11360
11361 out_config:
11362         intel_set_config_free(config);
11363         return ret;
11364 }
11365
11366 static const struct drm_crtc_funcs intel_crtc_funcs = {
11367         .gamma_set = intel_crtc_gamma_set,
11368         .set_config = intel_crtc_set_config,
11369         .destroy = intel_crtc_destroy,
11370         .page_flip = intel_crtc_page_flip,
11371 };
11372
11373 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11374                                       struct intel_shared_dpll *pll,
11375                                       struct intel_dpll_hw_state *hw_state)
11376 {
11377         uint32_t val;
11378
11379         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11380                 return false;
11381
11382         val = I915_READ(PCH_DPLL(pll->id));
11383         hw_state->dpll = val;
11384         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11385         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11386
11387         return val & DPLL_VCO_ENABLE;
11388 }
11389
11390 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11391                                   struct intel_shared_dpll *pll)
11392 {
11393         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11394         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11395 }
11396
11397 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11398                                 struct intel_shared_dpll *pll)
11399 {
11400         /* PCH refclock must be enabled first */
11401         ibx_assert_pch_refclk_enabled(dev_priv);
11402
11403         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11404
11405         /* Wait for the clocks to stabilize. */
11406         POSTING_READ(PCH_DPLL(pll->id));
11407         udelay(150);
11408
11409         /* The pixel multiplier can only be updated once the
11410          * DPLL is enabled and the clocks are stable.
11411          *
11412          * So write it again.
11413          */
11414         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11415         POSTING_READ(PCH_DPLL(pll->id));
11416         udelay(200);
11417 }
11418
11419 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11420                                  struct intel_shared_dpll *pll)
11421 {
11422         struct drm_device *dev = dev_priv->dev;
11423         struct intel_crtc *crtc;
11424
11425         /* Make sure no transcoder isn't still depending on us. */
11426         for_each_intel_crtc(dev, crtc) {
11427                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11428                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11429         }
11430
11431         I915_WRITE(PCH_DPLL(pll->id), 0);
11432         POSTING_READ(PCH_DPLL(pll->id));
11433         udelay(200);
11434 }
11435
11436 static char *ibx_pch_dpll_names[] = {
11437         "PCH DPLL A",
11438         "PCH DPLL B",
11439 };
11440
11441 static void ibx_pch_dpll_init(struct drm_device *dev)
11442 {
11443         struct drm_i915_private *dev_priv = dev->dev_private;
11444         int i;
11445
11446         dev_priv->num_shared_dpll = 2;
11447
11448         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11449                 dev_priv->shared_dplls[i].id = i;
11450                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11451                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11452                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11453                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11454                 dev_priv->shared_dplls[i].get_hw_state =
11455                         ibx_pch_dpll_get_hw_state;
11456         }
11457 }
11458
11459 static void intel_shared_dpll_init(struct drm_device *dev)
11460 {
11461         struct drm_i915_private *dev_priv = dev->dev_private;
11462
11463         if (HAS_DDI(dev))
11464                 intel_ddi_pll_init(dev);
11465         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11466                 ibx_pch_dpll_init(dev);
11467         else
11468                 dev_priv->num_shared_dpll = 0;
11469
11470         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11471 }
11472
11473 static int
11474 intel_primary_plane_disable(struct drm_plane *plane)
11475 {
11476         struct drm_device *dev = plane->dev;
11477         struct intel_crtc *intel_crtc;
11478
11479         if (!plane->fb)
11480                 return 0;
11481
11482         BUG_ON(!plane->crtc);
11483
11484         intel_crtc = to_intel_crtc(plane->crtc);
11485
11486         /*
11487          * Even though we checked plane->fb above, it's still possible that
11488          * the primary plane has been implicitly disabled because the crtc
11489          * coordinates given weren't visible, or because we detected
11490          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11491          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11492          * In either case, we need to unpin the FB and let the fb pointer get
11493          * updated, but otherwise we don't need to touch the hardware.
11494          */
11495         if (!intel_crtc->primary_enabled)
11496                 goto disable_unpin;
11497
11498         intel_crtc_wait_for_pending_flips(plane->crtc);
11499         intel_disable_primary_hw_plane(plane, plane->crtc);
11500
11501 disable_unpin:
11502         mutex_lock(&dev->struct_mutex);
11503         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11504                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11505         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11506         mutex_unlock(&dev->struct_mutex);
11507         plane->fb = NULL;
11508
11509         return 0;
11510 }
11511
11512 static int
11513 intel_check_primary_plane(struct drm_plane *plane,
11514                           struct intel_plane_state *state)
11515 {
11516         struct drm_crtc *crtc = state->crtc;
11517         struct drm_framebuffer *fb = state->fb;
11518         struct drm_rect *dest = &state->dst;
11519         struct drm_rect *src = &state->src;
11520         const struct drm_rect *clip = &state->clip;
11521
11522         return drm_plane_helper_check_update(plane, crtc, fb,
11523                                              src, dest, clip,
11524                                              DRM_PLANE_HELPER_NO_SCALING,
11525                                              DRM_PLANE_HELPER_NO_SCALING,
11526                                              false, true, &state->visible);
11527 }
11528
11529 static int
11530 intel_prepare_primary_plane(struct drm_plane *plane,
11531                             struct intel_plane_state *state)
11532 {
11533         struct drm_crtc *crtc = state->crtc;
11534         struct drm_framebuffer *fb = state->fb;
11535         struct drm_device *dev = crtc->dev;
11536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11537         enum pipe pipe = intel_crtc->pipe;
11538         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11539         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11540         int ret;
11541
11542         intel_crtc_wait_for_pending_flips(crtc);
11543
11544         if (intel_crtc_has_pending_flip(crtc)) {
11545                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11546                 return -EBUSY;
11547         }
11548
11549         if (old_obj != obj) {
11550                 mutex_lock(&dev->struct_mutex);
11551                 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11552                 if (ret == 0)
11553                         i915_gem_track_fb(old_obj, obj,
11554                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11555                 mutex_unlock(&dev->struct_mutex);
11556                 if (ret != 0) {
11557                         DRM_DEBUG_KMS("pin & fence failed\n");
11558                         return ret;
11559                 }
11560         }
11561
11562         return 0;
11563 }
11564
11565 static void
11566 intel_commit_primary_plane(struct drm_plane *plane,
11567                            struct intel_plane_state *state)
11568 {
11569         struct drm_crtc *crtc = state->crtc;
11570         struct drm_framebuffer *fb = state->fb;
11571         struct drm_device *dev = crtc->dev;
11572         struct drm_i915_private *dev_priv = dev->dev_private;
11573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11574         enum pipe pipe = intel_crtc->pipe;
11575         struct drm_framebuffer *old_fb = plane->fb;
11576         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11577         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11578         struct intel_plane *intel_plane = to_intel_plane(plane);
11579         struct drm_rect *src = &state->src;
11580
11581         crtc->primary->fb = fb;
11582         crtc->x = src->x1;
11583         crtc->y = src->y1;
11584
11585         intel_plane->crtc_x = state->orig_dst.x1;
11586         intel_plane->crtc_y = state->orig_dst.y1;
11587         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11588         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11589         intel_plane->src_x = state->orig_src.x1;
11590         intel_plane->src_y = state->orig_src.y1;
11591         intel_plane->src_w = drm_rect_width(&state->orig_src);
11592         intel_plane->src_h = drm_rect_height(&state->orig_src);
11593         intel_plane->obj = obj;
11594
11595         if (intel_crtc->active) {
11596                 /*
11597                  * FBC does not work on some platforms for rotated
11598                  * planes, so disable it when rotation is not 0 and
11599                  * update it when rotation is set back to 0.
11600                  *
11601                  * FIXME: This is redundant with the fbc update done in
11602                  * the primary plane enable function except that that
11603                  * one is done too late. We eventually need to unify
11604                  * this.
11605                  */
11606                 if (intel_crtc->primary_enabled &&
11607                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11608                     dev_priv->fbc.plane == intel_crtc->plane &&
11609                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11610                         intel_disable_fbc(dev);
11611                 }
11612
11613                 if (state->visible) {
11614                         bool was_enabled = intel_crtc->primary_enabled;
11615
11616                         /* FIXME: kill this fastboot hack */
11617                         intel_update_pipe_size(intel_crtc);
11618
11619                         intel_crtc->primary_enabled = true;
11620
11621                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11622                                         crtc->x, crtc->y);
11623
11624                         /*
11625                          * BDW signals flip done immediately if the plane
11626                          * is disabled, even if the plane enable is already
11627                          * armed to occur at the next vblank :(
11628                          */
11629                         if (IS_BROADWELL(dev) && !was_enabled)
11630                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11631                 } else {
11632                         /*
11633                          * If clipping results in a non-visible primary plane,
11634                          * we'll disable the primary plane.  Note that this is
11635                          * a bit different than what happens if userspace
11636                          * explicitly disables the plane by passing fb=0
11637                          * because plane->fb still gets set and pinned.
11638                          */
11639                         intel_disable_primary_hw_plane(plane, crtc);
11640                 }
11641
11642                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11643
11644                 mutex_lock(&dev->struct_mutex);
11645                 intel_update_fbc(dev);
11646                 mutex_unlock(&dev->struct_mutex);
11647         }
11648
11649         if (old_fb && old_fb != fb) {
11650                 if (intel_crtc->active)
11651                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11652
11653                 mutex_lock(&dev->struct_mutex);
11654                 intel_unpin_fb_obj(old_obj);
11655                 mutex_unlock(&dev->struct_mutex);
11656         }
11657 }
11658
11659 static int
11660 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11661                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11662                              unsigned int crtc_w, unsigned int crtc_h,
11663                              uint32_t src_x, uint32_t src_y,
11664                              uint32_t src_w, uint32_t src_h)
11665 {
11666         struct intel_plane_state state;
11667         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11668         int ret;
11669
11670         state.crtc = crtc;
11671         state.fb = fb;
11672
11673         /* sample coordinates in 16.16 fixed point */
11674         state.src.x1 = src_x;
11675         state.src.x2 = src_x + src_w;
11676         state.src.y1 = src_y;
11677         state.src.y2 = src_y + src_h;
11678
11679         /* integer pixels */
11680         state.dst.x1 = crtc_x;
11681         state.dst.x2 = crtc_x + crtc_w;
11682         state.dst.y1 = crtc_y;
11683         state.dst.y2 = crtc_y + crtc_h;
11684
11685         state.clip.x1 = 0;
11686         state.clip.y1 = 0;
11687         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11688         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11689
11690         state.orig_src = state.src;
11691         state.orig_dst = state.dst;
11692
11693         ret = intel_check_primary_plane(plane, &state);
11694         if (ret)
11695                 return ret;
11696
11697         ret = intel_prepare_primary_plane(plane, &state);
11698         if (ret)
11699                 return ret;
11700
11701         intel_commit_primary_plane(plane, &state);
11702
11703         return 0;
11704 }
11705
11706 /* Common destruction function for both primary and cursor planes */
11707 static void intel_plane_destroy(struct drm_plane *plane)
11708 {
11709         struct intel_plane *intel_plane = to_intel_plane(plane);
11710         drm_plane_cleanup(plane);
11711         kfree(intel_plane);
11712 }
11713
11714 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11715         .update_plane = intel_primary_plane_setplane,
11716         .disable_plane = intel_primary_plane_disable,
11717         .destroy = intel_plane_destroy,
11718         .set_property = intel_plane_set_property
11719 };
11720
11721 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11722                                                     int pipe)
11723 {
11724         struct intel_plane *primary;
11725         const uint32_t *intel_primary_formats;
11726         int num_formats;
11727
11728         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11729         if (primary == NULL)
11730                 return NULL;
11731
11732         primary->can_scale = false;
11733         primary->max_downscale = 1;
11734         primary->pipe = pipe;
11735         primary->plane = pipe;
11736         primary->rotation = BIT(DRM_ROTATE_0);
11737         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11738                 primary->plane = !pipe;
11739
11740         if (INTEL_INFO(dev)->gen <= 3) {
11741                 intel_primary_formats = intel_primary_formats_gen2;
11742                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11743         } else {
11744                 intel_primary_formats = intel_primary_formats_gen4;
11745                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11746         }
11747
11748         drm_universal_plane_init(dev, &primary->base, 0,
11749                                  &intel_primary_plane_funcs,
11750                                  intel_primary_formats, num_formats,
11751                                  DRM_PLANE_TYPE_PRIMARY);
11752
11753         if (INTEL_INFO(dev)->gen >= 4) {
11754                 if (!dev->mode_config.rotation_property)
11755                         dev->mode_config.rotation_property =
11756                                 drm_mode_create_rotation_property(dev,
11757                                                         BIT(DRM_ROTATE_0) |
11758                                                         BIT(DRM_ROTATE_180));
11759                 if (dev->mode_config.rotation_property)
11760                         drm_object_attach_property(&primary->base.base,
11761                                 dev->mode_config.rotation_property,
11762                                 primary->rotation);
11763         }
11764
11765         return &primary->base;
11766 }
11767
11768 static int
11769 intel_cursor_plane_disable(struct drm_plane *plane)
11770 {
11771         if (!plane->fb)
11772                 return 0;
11773
11774         BUG_ON(!plane->crtc);
11775
11776         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11777 }
11778
11779 static int
11780 intel_check_cursor_plane(struct drm_plane *plane,
11781                          struct intel_plane_state *state)
11782 {
11783         struct drm_crtc *crtc = state->crtc;
11784         struct drm_device *dev = crtc->dev;
11785         struct drm_framebuffer *fb = state->fb;
11786         struct drm_rect *dest = &state->dst;
11787         struct drm_rect *src = &state->src;
11788         const struct drm_rect *clip = &state->clip;
11789         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11790         int crtc_w, crtc_h;
11791         unsigned stride;
11792         int ret;
11793
11794         ret = drm_plane_helper_check_update(plane, crtc, fb,
11795                                             src, dest, clip,
11796                                             DRM_PLANE_HELPER_NO_SCALING,
11797                                             DRM_PLANE_HELPER_NO_SCALING,
11798                                             true, true, &state->visible);
11799         if (ret)
11800                 return ret;
11801
11802
11803         /* if we want to turn off the cursor ignore width and height */
11804         if (!obj)
11805                 return 0;
11806
11807         /* Check for which cursor types we support */
11808         crtc_w = drm_rect_width(&state->orig_dst);
11809         crtc_h = drm_rect_height(&state->orig_dst);
11810         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11811                 DRM_DEBUG("Cursor dimension not supported\n");
11812                 return -EINVAL;
11813         }
11814
11815         stride = roundup_pow_of_two(crtc_w) * 4;
11816         if (obj->base.size < stride * crtc_h) {
11817                 DRM_DEBUG_KMS("buffer is too small\n");
11818                 return -ENOMEM;
11819         }
11820
11821         if (fb == crtc->cursor->fb)
11822                 return 0;
11823
11824         /* we only need to pin inside GTT if cursor is non-phy */
11825         mutex_lock(&dev->struct_mutex);
11826         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11827                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11828                 ret = -EINVAL;
11829         }
11830         mutex_unlock(&dev->struct_mutex);
11831
11832         return ret;
11833 }
11834
11835 static int
11836 intel_commit_cursor_plane(struct drm_plane *plane,
11837                           struct intel_plane_state *state)
11838 {
11839         struct drm_crtc *crtc = state->crtc;
11840         struct drm_framebuffer *fb = state->fb;
11841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11842         struct intel_plane *intel_plane = to_intel_plane(plane);
11843         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11844         struct drm_i915_gem_object *obj = intel_fb->obj;
11845         int crtc_w, crtc_h;
11846
11847         crtc->cursor_x = state->orig_dst.x1;
11848         crtc->cursor_y = state->orig_dst.y1;
11849
11850         intel_plane->crtc_x = state->orig_dst.x1;
11851         intel_plane->crtc_y = state->orig_dst.y1;
11852         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11853         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11854         intel_plane->src_x = state->orig_src.x1;
11855         intel_plane->src_y = state->orig_src.y1;
11856         intel_plane->src_w = drm_rect_width(&state->orig_src);
11857         intel_plane->src_h = drm_rect_height(&state->orig_src);
11858         intel_plane->obj = obj;
11859
11860         if (fb != crtc->cursor->fb) {
11861                 crtc_w = drm_rect_width(&state->orig_dst);
11862                 crtc_h = drm_rect_height(&state->orig_dst);
11863                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11864         } else {
11865                 intel_crtc_update_cursor(crtc, state->visible);
11866
11867                 intel_frontbuffer_flip(crtc->dev,
11868                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11869
11870                 return 0;
11871         }
11872 }
11873
11874 static int
11875 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11876                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11877                           unsigned int crtc_w, unsigned int crtc_h,
11878                           uint32_t src_x, uint32_t src_y,
11879                           uint32_t src_w, uint32_t src_h)
11880 {
11881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11882         struct intel_plane_state state;
11883         int ret;
11884
11885         state.crtc = crtc;
11886         state.fb = fb;
11887
11888         /* sample coordinates in 16.16 fixed point */
11889         state.src.x1 = src_x;
11890         state.src.x2 = src_x + src_w;
11891         state.src.y1 = src_y;
11892         state.src.y2 = src_y + src_h;
11893
11894         /* integer pixels */
11895         state.dst.x1 = crtc_x;
11896         state.dst.x2 = crtc_x + crtc_w;
11897         state.dst.y1 = crtc_y;
11898         state.dst.y2 = crtc_y + crtc_h;
11899
11900         state.clip.x1 = 0;
11901         state.clip.y1 = 0;
11902         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11903         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11904
11905         state.orig_src = state.src;
11906         state.orig_dst = state.dst;
11907
11908         ret = intel_check_cursor_plane(plane, &state);
11909         if (ret)
11910                 return ret;
11911
11912         return intel_commit_cursor_plane(plane, &state);
11913 }
11914
11915 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11916         .update_plane = intel_cursor_plane_update,
11917         .disable_plane = intel_cursor_plane_disable,
11918         .destroy = intel_plane_destroy,
11919         .set_property = intel_plane_set_property,
11920 };
11921
11922 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11923                                                    int pipe)
11924 {
11925         struct intel_plane *cursor;
11926
11927         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11928         if (cursor == NULL)
11929                 return NULL;
11930
11931         cursor->can_scale = false;
11932         cursor->max_downscale = 1;
11933         cursor->pipe = pipe;
11934         cursor->plane = pipe;
11935         cursor->rotation = BIT(DRM_ROTATE_0);
11936
11937         drm_universal_plane_init(dev, &cursor->base, 0,
11938                                  &intel_cursor_plane_funcs,
11939                                  intel_cursor_formats,
11940                                  ARRAY_SIZE(intel_cursor_formats),
11941                                  DRM_PLANE_TYPE_CURSOR);
11942
11943         if (INTEL_INFO(dev)->gen >= 4) {
11944                 if (!dev->mode_config.rotation_property)
11945                         dev->mode_config.rotation_property =
11946                                 drm_mode_create_rotation_property(dev,
11947                                                         BIT(DRM_ROTATE_0) |
11948                                                         BIT(DRM_ROTATE_180));
11949                 if (dev->mode_config.rotation_property)
11950                         drm_object_attach_property(&cursor->base.base,
11951                                 dev->mode_config.rotation_property,
11952                                 cursor->rotation);
11953         }
11954
11955         return &cursor->base;
11956 }
11957
11958 static void intel_crtc_init(struct drm_device *dev, int pipe)
11959 {
11960         struct drm_i915_private *dev_priv = dev->dev_private;
11961         struct intel_crtc *intel_crtc;
11962         struct drm_plane *primary = NULL;
11963         struct drm_plane *cursor = NULL;
11964         int i, ret;
11965
11966         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11967         if (intel_crtc == NULL)
11968                 return;
11969
11970         primary = intel_primary_plane_create(dev, pipe);
11971         if (!primary)
11972                 goto fail;
11973
11974         cursor = intel_cursor_plane_create(dev, pipe);
11975         if (!cursor)
11976                 goto fail;
11977
11978         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11979                                         cursor, &intel_crtc_funcs);
11980         if (ret)
11981                 goto fail;
11982
11983         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11984         for (i = 0; i < 256; i++) {
11985                 intel_crtc->lut_r[i] = i;
11986                 intel_crtc->lut_g[i] = i;
11987                 intel_crtc->lut_b[i] = i;
11988         }
11989
11990         /*
11991          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11992          * is hooked to pipe B. Hence we want plane A feeding pipe B.
11993          */
11994         intel_crtc->pipe = pipe;
11995         intel_crtc->plane = pipe;
11996         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11997                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11998                 intel_crtc->plane = !pipe;
11999         }
12000
12001         intel_crtc->cursor_base = ~0;
12002         intel_crtc->cursor_cntl = ~0;
12003         intel_crtc->cursor_size = ~0;
12004
12005         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12006                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12007         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12008         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12009
12010         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12011
12012         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12013         return;
12014
12015 fail:
12016         if (primary)
12017                 drm_plane_cleanup(primary);
12018         if (cursor)
12019                 drm_plane_cleanup(cursor);
12020         kfree(intel_crtc);
12021 }
12022
12023 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12024 {
12025         struct drm_encoder *encoder = connector->base.encoder;
12026         struct drm_device *dev = connector->base.dev;
12027
12028         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12029
12030         if (!encoder)
12031                 return INVALID_PIPE;
12032
12033         return to_intel_crtc(encoder->crtc)->pipe;
12034 }
12035
12036 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12037                                 struct drm_file *file)
12038 {
12039         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12040         struct drm_crtc *drmmode_crtc;
12041         struct intel_crtc *crtc;
12042
12043         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12044                 return -ENODEV;
12045
12046         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12047
12048         if (!drmmode_crtc) {
12049                 DRM_ERROR("no such CRTC id\n");
12050                 return -ENOENT;
12051         }
12052
12053         crtc = to_intel_crtc(drmmode_crtc);
12054         pipe_from_crtc_id->pipe = crtc->pipe;
12055
12056         return 0;
12057 }
12058
12059 static int intel_encoder_clones(struct intel_encoder *encoder)
12060 {
12061         struct drm_device *dev = encoder->base.dev;
12062         struct intel_encoder *source_encoder;
12063         int index_mask = 0;
12064         int entry = 0;
12065
12066         for_each_intel_encoder(dev, source_encoder) {
12067                 if (encoders_cloneable(encoder, source_encoder))
12068                         index_mask |= (1 << entry);
12069
12070                 entry++;
12071         }
12072
12073         return index_mask;
12074 }
12075
12076 static bool has_edp_a(struct drm_device *dev)
12077 {
12078         struct drm_i915_private *dev_priv = dev->dev_private;
12079
12080         if (!IS_MOBILE(dev))
12081                 return false;
12082
12083         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12084                 return false;
12085
12086         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12087                 return false;
12088
12089         return true;
12090 }
12091
12092 const char *intel_output_name(int output)
12093 {
12094         static const char *names[] = {
12095                 [INTEL_OUTPUT_UNUSED] = "Unused",
12096                 [INTEL_OUTPUT_ANALOG] = "Analog",
12097                 [INTEL_OUTPUT_DVO] = "DVO",
12098                 [INTEL_OUTPUT_SDVO] = "SDVO",
12099                 [INTEL_OUTPUT_LVDS] = "LVDS",
12100                 [INTEL_OUTPUT_TVOUT] = "TV",
12101                 [INTEL_OUTPUT_HDMI] = "HDMI",
12102                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12103                 [INTEL_OUTPUT_EDP] = "eDP",
12104                 [INTEL_OUTPUT_DSI] = "DSI",
12105                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12106         };
12107
12108         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12109                 return "Invalid";
12110
12111         return names[output];
12112 }
12113
12114 static bool intel_crt_present(struct drm_device *dev)
12115 {
12116         struct drm_i915_private *dev_priv = dev->dev_private;
12117
12118         if (INTEL_INFO(dev)->gen >= 9)
12119                 return false;
12120
12121         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12122                 return false;
12123
12124         if (IS_CHERRYVIEW(dev))
12125                 return false;
12126
12127         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12128                 return false;
12129
12130         return true;
12131 }
12132
12133 static void intel_setup_outputs(struct drm_device *dev)
12134 {
12135         struct drm_i915_private *dev_priv = dev->dev_private;
12136         struct intel_encoder *encoder;
12137         bool dpd_is_edp = false;
12138
12139         intel_lvds_init(dev);
12140
12141         if (intel_crt_present(dev))
12142                 intel_crt_init(dev);
12143
12144         if (HAS_DDI(dev)) {
12145                 int found;
12146
12147                 /* Haswell uses DDI functions to detect digital outputs */
12148                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12149                 /* DDI A only supports eDP */
12150                 if (found)
12151                         intel_ddi_init(dev, PORT_A);
12152
12153                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12154                  * register */
12155                 found = I915_READ(SFUSE_STRAP);
12156
12157                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12158                         intel_ddi_init(dev, PORT_B);
12159                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12160                         intel_ddi_init(dev, PORT_C);
12161                 if (found & SFUSE_STRAP_DDID_DETECTED)
12162                         intel_ddi_init(dev, PORT_D);
12163         } else if (HAS_PCH_SPLIT(dev)) {
12164                 int found;
12165                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12166
12167                 if (has_edp_a(dev))
12168                         intel_dp_init(dev, DP_A, PORT_A);
12169
12170                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12171                         /* PCH SDVOB multiplex with HDMIB */
12172                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12173                         if (!found)
12174                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12175                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12176                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12177                 }
12178
12179                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12180                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12181
12182                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12183                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12184
12185                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12186                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12187
12188                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12189                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12190         } else if (IS_VALLEYVIEW(dev)) {
12191                 /*
12192                  * The DP_DETECTED bit is the latched state of the DDC
12193                  * SDA pin at boot. However since eDP doesn't require DDC
12194                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12195                  * eDP ports may have been muxed to an alternate function.
12196                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12197                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12198                  * detect eDP ports.
12199                  */
12200                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12201                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12202                                         PORT_B);
12203                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12204                     intel_dp_is_edp(dev, PORT_B))
12205                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12206
12207                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12208                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12209                                         PORT_C);
12210                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12211                     intel_dp_is_edp(dev, PORT_C))
12212                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12213
12214                 if (IS_CHERRYVIEW(dev)) {
12215                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12216                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12217                                                 PORT_D);
12218                         /* eDP not supported on port D, so don't check VBT */
12219                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12220                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12221                 }
12222
12223                 intel_dsi_init(dev);
12224         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12225                 bool found = false;
12226
12227                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12228                         DRM_DEBUG_KMS("probing SDVOB\n");
12229                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12230                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12231                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12232                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12233                         }
12234
12235                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12236                                 intel_dp_init(dev, DP_B, PORT_B);
12237                 }
12238
12239                 /* Before G4X SDVOC doesn't have its own detect register */
12240
12241                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12242                         DRM_DEBUG_KMS("probing SDVOC\n");
12243                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12244                 }
12245
12246                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12247
12248                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12249                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12250                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12251                         }
12252                         if (SUPPORTS_INTEGRATED_DP(dev))
12253                                 intel_dp_init(dev, DP_C, PORT_C);
12254                 }
12255
12256                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12257                     (I915_READ(DP_D) & DP_DETECTED))
12258                         intel_dp_init(dev, DP_D, PORT_D);
12259         } else if (IS_GEN2(dev))
12260                 intel_dvo_init(dev);
12261
12262         if (SUPPORTS_TV(dev))
12263                 intel_tv_init(dev);
12264
12265         intel_edp_psr_init(dev);
12266
12267         for_each_intel_encoder(dev, encoder) {
12268                 encoder->base.possible_crtcs = encoder->crtc_mask;
12269                 encoder->base.possible_clones =
12270                         intel_encoder_clones(encoder);
12271         }
12272
12273         intel_init_pch_refclk(dev);
12274
12275         drm_helper_move_panel_connectors_to_head(dev);
12276 }
12277
12278 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12279 {
12280         struct drm_device *dev = fb->dev;
12281         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12282
12283         drm_framebuffer_cleanup(fb);
12284         mutex_lock(&dev->struct_mutex);
12285         WARN_ON(!intel_fb->obj->framebuffer_references--);
12286         drm_gem_object_unreference(&intel_fb->obj->base);
12287         mutex_unlock(&dev->struct_mutex);
12288         kfree(intel_fb);
12289 }
12290
12291 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12292                                                 struct drm_file *file,
12293                                                 unsigned int *handle)
12294 {
12295         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12296         struct drm_i915_gem_object *obj = intel_fb->obj;
12297
12298         return drm_gem_handle_create(file, &obj->base, handle);
12299 }
12300
12301 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12302         .destroy = intel_user_framebuffer_destroy,
12303         .create_handle = intel_user_framebuffer_create_handle,
12304 };
12305
12306 static int intel_framebuffer_init(struct drm_device *dev,
12307                                   struct intel_framebuffer *intel_fb,
12308                                   struct drm_mode_fb_cmd2 *mode_cmd,
12309                                   struct drm_i915_gem_object *obj)
12310 {
12311         int aligned_height;
12312         int pitch_limit;
12313         int ret;
12314
12315         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12316
12317         if (obj->tiling_mode == I915_TILING_Y) {
12318                 DRM_DEBUG("hardware does not support tiling Y\n");
12319                 return -EINVAL;
12320         }
12321
12322         if (mode_cmd->pitches[0] & 63) {
12323                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12324                           mode_cmd->pitches[0]);
12325                 return -EINVAL;
12326         }
12327
12328         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12329                 pitch_limit = 32*1024;
12330         } else if (INTEL_INFO(dev)->gen >= 4) {
12331                 if (obj->tiling_mode)
12332                         pitch_limit = 16*1024;
12333                 else
12334                         pitch_limit = 32*1024;
12335         } else if (INTEL_INFO(dev)->gen >= 3) {
12336                 if (obj->tiling_mode)
12337                         pitch_limit = 8*1024;
12338                 else
12339                         pitch_limit = 16*1024;
12340         } else
12341                 /* XXX DSPC is limited to 4k tiled */
12342                 pitch_limit = 8*1024;
12343
12344         if (mode_cmd->pitches[0] > pitch_limit) {
12345                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12346                           obj->tiling_mode ? "tiled" : "linear",
12347                           mode_cmd->pitches[0], pitch_limit);
12348                 return -EINVAL;
12349         }
12350
12351         if (obj->tiling_mode != I915_TILING_NONE &&
12352             mode_cmd->pitches[0] != obj->stride) {
12353                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12354                           mode_cmd->pitches[0], obj->stride);
12355                 return -EINVAL;
12356         }
12357
12358         /* Reject formats not supported by any plane early. */
12359         switch (mode_cmd->pixel_format) {
12360         case DRM_FORMAT_C8:
12361         case DRM_FORMAT_RGB565:
12362         case DRM_FORMAT_XRGB8888:
12363         case DRM_FORMAT_ARGB8888:
12364                 break;
12365         case DRM_FORMAT_XRGB1555:
12366         case DRM_FORMAT_ARGB1555:
12367                 if (INTEL_INFO(dev)->gen > 3) {
12368                         DRM_DEBUG("unsupported pixel format: %s\n",
12369                                   drm_get_format_name(mode_cmd->pixel_format));
12370                         return -EINVAL;
12371                 }
12372                 break;
12373         case DRM_FORMAT_XBGR8888:
12374         case DRM_FORMAT_ABGR8888:
12375         case DRM_FORMAT_XRGB2101010:
12376         case DRM_FORMAT_ARGB2101010:
12377         case DRM_FORMAT_XBGR2101010:
12378         case DRM_FORMAT_ABGR2101010:
12379                 if (INTEL_INFO(dev)->gen < 4) {
12380                         DRM_DEBUG("unsupported pixel format: %s\n",
12381                                   drm_get_format_name(mode_cmd->pixel_format));
12382                         return -EINVAL;
12383                 }
12384                 break;
12385         case DRM_FORMAT_YUYV:
12386         case DRM_FORMAT_UYVY:
12387         case DRM_FORMAT_YVYU:
12388         case DRM_FORMAT_VYUY:
12389                 if (INTEL_INFO(dev)->gen < 5) {
12390                         DRM_DEBUG("unsupported pixel format: %s\n",
12391                                   drm_get_format_name(mode_cmd->pixel_format));
12392                         return -EINVAL;
12393                 }
12394                 break;
12395         default:
12396                 DRM_DEBUG("unsupported pixel format: %s\n",
12397                           drm_get_format_name(mode_cmd->pixel_format));
12398                 return -EINVAL;
12399         }
12400
12401         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12402         if (mode_cmd->offsets[0] != 0)
12403                 return -EINVAL;
12404
12405         aligned_height = intel_align_height(dev, mode_cmd->height,
12406                                             obj->tiling_mode);
12407         /* FIXME drm helper for size checks (especially planar formats)? */
12408         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12409                 return -EINVAL;
12410
12411         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12412         intel_fb->obj = obj;
12413         intel_fb->obj->framebuffer_references++;
12414
12415         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12416         if (ret) {
12417                 DRM_ERROR("framebuffer init failed %d\n", ret);
12418                 return ret;
12419         }
12420
12421         return 0;
12422 }
12423
12424 static struct drm_framebuffer *
12425 intel_user_framebuffer_create(struct drm_device *dev,
12426                               struct drm_file *filp,
12427                               struct drm_mode_fb_cmd2 *mode_cmd)
12428 {
12429         struct drm_i915_gem_object *obj;
12430
12431         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12432                                                 mode_cmd->handles[0]));
12433         if (&obj->base == NULL)
12434                 return ERR_PTR(-ENOENT);
12435
12436         return intel_framebuffer_create(dev, mode_cmd, obj);
12437 }
12438
12439 #ifndef CONFIG_DRM_I915_FBDEV
12440 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12441 {
12442 }
12443 #endif
12444
12445 static const struct drm_mode_config_funcs intel_mode_funcs = {
12446         .fb_create = intel_user_framebuffer_create,
12447         .output_poll_changed = intel_fbdev_output_poll_changed,
12448 };
12449
12450 /* Set up chip specific display functions */
12451 static void intel_init_display(struct drm_device *dev)
12452 {
12453         struct drm_i915_private *dev_priv = dev->dev_private;
12454
12455         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12456                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12457         else if (IS_CHERRYVIEW(dev))
12458                 dev_priv->display.find_dpll = chv_find_best_dpll;
12459         else if (IS_VALLEYVIEW(dev))
12460                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12461         else if (IS_PINEVIEW(dev))
12462                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12463         else
12464                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12465
12466         if (HAS_DDI(dev)) {
12467                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12468                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12469                 dev_priv->display.crtc_compute_clock =
12470                         haswell_crtc_compute_clock;
12471                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12472                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12473                 dev_priv->display.off = ironlake_crtc_off;
12474                 if (INTEL_INFO(dev)->gen >= 9)
12475                         dev_priv->display.update_primary_plane =
12476                                 skylake_update_primary_plane;
12477                 else
12478                         dev_priv->display.update_primary_plane =
12479                                 ironlake_update_primary_plane;
12480         } else if (HAS_PCH_SPLIT(dev)) {
12481                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12482                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12483                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12484                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12485                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12486                 dev_priv->display.off = ironlake_crtc_off;
12487                 dev_priv->display.update_primary_plane =
12488                         ironlake_update_primary_plane;
12489         } else if (IS_VALLEYVIEW(dev)) {
12490                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12491                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12492                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12493                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12494                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12495                 dev_priv->display.off = i9xx_crtc_off;
12496                 dev_priv->display.update_primary_plane =
12497                         i9xx_update_primary_plane;
12498         } else {
12499                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12500                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12501                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12502                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12503                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12504                 dev_priv->display.off = i9xx_crtc_off;
12505                 dev_priv->display.update_primary_plane =
12506                         i9xx_update_primary_plane;
12507         }
12508
12509         /* Returns the core display clock speed */
12510         if (IS_VALLEYVIEW(dev))
12511                 dev_priv->display.get_display_clock_speed =
12512                         valleyview_get_display_clock_speed;
12513         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12514                 dev_priv->display.get_display_clock_speed =
12515                         i945_get_display_clock_speed;
12516         else if (IS_I915G(dev))
12517                 dev_priv->display.get_display_clock_speed =
12518                         i915_get_display_clock_speed;
12519         else if (IS_I945GM(dev) || IS_845G(dev))
12520                 dev_priv->display.get_display_clock_speed =
12521                         i9xx_misc_get_display_clock_speed;
12522         else if (IS_PINEVIEW(dev))
12523                 dev_priv->display.get_display_clock_speed =
12524                         pnv_get_display_clock_speed;
12525         else if (IS_I915GM(dev))
12526                 dev_priv->display.get_display_clock_speed =
12527                         i915gm_get_display_clock_speed;
12528         else if (IS_I865G(dev))
12529                 dev_priv->display.get_display_clock_speed =
12530                         i865_get_display_clock_speed;
12531         else if (IS_I85X(dev))
12532                 dev_priv->display.get_display_clock_speed =
12533                         i855_get_display_clock_speed;
12534         else /* 852, 830 */
12535                 dev_priv->display.get_display_clock_speed =
12536                         i830_get_display_clock_speed;
12537
12538         if (IS_GEN5(dev)) {
12539                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12540         } else if (IS_GEN6(dev)) {
12541                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12542                 dev_priv->display.modeset_global_resources =
12543                         snb_modeset_global_resources;
12544         } else if (IS_IVYBRIDGE(dev)) {
12545                 /* FIXME: detect B0+ stepping and use auto training */
12546                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12547                 dev_priv->display.modeset_global_resources =
12548                         ivb_modeset_global_resources;
12549         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12550                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12551                 dev_priv->display.modeset_global_resources =
12552                         haswell_modeset_global_resources;
12553         } else if (IS_VALLEYVIEW(dev)) {
12554                 dev_priv->display.modeset_global_resources =
12555                         valleyview_modeset_global_resources;
12556         } else if (INTEL_INFO(dev)->gen >= 9) {
12557                 dev_priv->display.modeset_global_resources =
12558                         haswell_modeset_global_resources;
12559         }
12560
12561         /* Default just returns -ENODEV to indicate unsupported */
12562         dev_priv->display.queue_flip = intel_default_queue_flip;
12563
12564         switch (INTEL_INFO(dev)->gen) {
12565         case 2:
12566                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12567                 break;
12568
12569         case 3:
12570                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12571                 break;
12572
12573         case 4:
12574         case 5:
12575                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12576                 break;
12577
12578         case 6:
12579                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12580                 break;
12581         case 7:
12582         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12583                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12584                 break;
12585         }
12586
12587         intel_panel_init_backlight_funcs(dev);
12588
12589         mutex_init(&dev_priv->pps_mutex);
12590 }
12591
12592 /*
12593  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12594  * resume, or other times.  This quirk makes sure that's the case for
12595  * affected systems.
12596  */
12597 static void quirk_pipea_force(struct drm_device *dev)
12598 {
12599         struct drm_i915_private *dev_priv = dev->dev_private;
12600
12601         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12602         DRM_INFO("applying pipe a force quirk\n");
12603 }
12604
12605 static void quirk_pipeb_force(struct drm_device *dev)
12606 {
12607         struct drm_i915_private *dev_priv = dev->dev_private;
12608
12609         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12610         DRM_INFO("applying pipe b force quirk\n");
12611 }
12612
12613 /*
12614  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12615  */
12616 static void quirk_ssc_force_disable(struct drm_device *dev)
12617 {
12618         struct drm_i915_private *dev_priv = dev->dev_private;
12619         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12620         DRM_INFO("applying lvds SSC disable quirk\n");
12621 }
12622
12623 /*
12624  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12625  * brightness value
12626  */
12627 static void quirk_invert_brightness(struct drm_device *dev)
12628 {
12629         struct drm_i915_private *dev_priv = dev->dev_private;
12630         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12631         DRM_INFO("applying inverted panel brightness quirk\n");
12632 }
12633
12634 /* Some VBT's incorrectly indicate no backlight is present */
12635 static void quirk_backlight_present(struct drm_device *dev)
12636 {
12637         struct drm_i915_private *dev_priv = dev->dev_private;
12638         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12639         DRM_INFO("applying backlight present quirk\n");
12640 }
12641
12642 struct intel_quirk {
12643         int device;
12644         int subsystem_vendor;
12645         int subsystem_device;
12646         void (*hook)(struct drm_device *dev);
12647 };
12648
12649 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12650 struct intel_dmi_quirk {
12651         void (*hook)(struct drm_device *dev);
12652         const struct dmi_system_id (*dmi_id_list)[];
12653 };
12654
12655 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12656 {
12657         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12658         return 1;
12659 }
12660
12661 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12662         {
12663                 .dmi_id_list = &(const struct dmi_system_id[]) {
12664                         {
12665                                 .callback = intel_dmi_reverse_brightness,
12666                                 .ident = "NCR Corporation",
12667                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12668                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12669                                 },
12670                         },
12671                         { }  /* terminating entry */
12672                 },
12673                 .hook = quirk_invert_brightness,
12674         },
12675 };
12676
12677 static struct intel_quirk intel_quirks[] = {
12678         /* HP Mini needs pipe A force quirk (LP: #322104) */
12679         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12680
12681         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12682         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12683
12684         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12685         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12686
12687         /* 830 needs to leave pipe A & dpll A up */
12688         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12689
12690         /* 830 needs to leave pipe B & dpll B up */
12691         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12692
12693         /* Lenovo U160 cannot use SSC on LVDS */
12694         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12695
12696         /* Sony Vaio Y cannot use SSC on LVDS */
12697         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12698
12699         /* Acer Aspire 5734Z must invert backlight brightness */
12700         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12701
12702         /* Acer/eMachines G725 */
12703         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12704
12705         /* Acer/eMachines e725 */
12706         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12707
12708         /* Acer/Packard Bell NCL20 */
12709         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12710
12711         /* Acer Aspire 4736Z */
12712         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12713
12714         /* Acer Aspire 5336 */
12715         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12716
12717         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12718         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12719
12720         /* Acer C720 Chromebook (Core i3 4005U) */
12721         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12722
12723         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12724         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12725
12726         /* HP Chromebook 14 (Celeron 2955U) */
12727         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12728 };
12729
12730 static void intel_init_quirks(struct drm_device *dev)
12731 {
12732         struct pci_dev *d = dev->pdev;
12733         int i;
12734
12735         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12736                 struct intel_quirk *q = &intel_quirks[i];
12737
12738                 if (d->device == q->device &&
12739                     (d->subsystem_vendor == q->subsystem_vendor ||
12740                      q->subsystem_vendor == PCI_ANY_ID) &&
12741                     (d->subsystem_device == q->subsystem_device ||
12742                      q->subsystem_device == PCI_ANY_ID))
12743                         q->hook(dev);
12744         }
12745         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12746                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12747                         intel_dmi_quirks[i].hook(dev);
12748         }
12749 }
12750
12751 /* Disable the VGA plane that we never use */
12752 static void i915_disable_vga(struct drm_device *dev)
12753 {
12754         struct drm_i915_private *dev_priv = dev->dev_private;
12755         u8 sr1;
12756         u32 vga_reg = i915_vgacntrl_reg(dev);
12757
12758         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12759         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12760         outb(SR01, VGA_SR_INDEX);
12761         sr1 = inb(VGA_SR_DATA);
12762         outb(sr1 | 1<<5, VGA_SR_DATA);
12763         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12764         udelay(300);
12765
12766         /*
12767          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12768          * from S3 without preserving (some of?) the other bits.
12769          */
12770         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12771         POSTING_READ(vga_reg);
12772 }
12773
12774 void intel_modeset_init_hw(struct drm_device *dev)
12775 {
12776         intel_prepare_ddi(dev);
12777
12778         if (IS_VALLEYVIEW(dev))
12779                 vlv_update_cdclk(dev);
12780
12781         intel_init_clock_gating(dev);
12782
12783         intel_enable_gt_powersave(dev);
12784 }
12785
12786 void intel_modeset_init(struct drm_device *dev)
12787 {
12788         struct drm_i915_private *dev_priv = dev->dev_private;
12789         int sprite, ret;
12790         enum pipe pipe;
12791         struct intel_crtc *crtc;
12792
12793         drm_mode_config_init(dev);
12794
12795         dev->mode_config.min_width = 0;
12796         dev->mode_config.min_height = 0;
12797
12798         dev->mode_config.preferred_depth = 24;
12799         dev->mode_config.prefer_shadow = 1;
12800
12801         dev->mode_config.funcs = &intel_mode_funcs;
12802
12803         intel_init_quirks(dev);
12804
12805         intel_init_pm(dev);
12806
12807         if (INTEL_INFO(dev)->num_pipes == 0)
12808                 return;
12809
12810         intel_init_display(dev);
12811         intel_init_audio(dev);
12812
12813         if (IS_GEN2(dev)) {
12814                 dev->mode_config.max_width = 2048;
12815                 dev->mode_config.max_height = 2048;
12816         } else if (IS_GEN3(dev)) {
12817                 dev->mode_config.max_width = 4096;
12818                 dev->mode_config.max_height = 4096;
12819         } else {
12820                 dev->mode_config.max_width = 8192;
12821                 dev->mode_config.max_height = 8192;
12822         }
12823
12824         if (IS_845G(dev) || IS_I865G(dev)) {
12825                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12826                 dev->mode_config.cursor_height = 1023;
12827         } else if (IS_GEN2(dev)) {
12828                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12829                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12830         } else {
12831                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12832                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12833         }
12834
12835         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12836
12837         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12838                       INTEL_INFO(dev)->num_pipes,
12839                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12840
12841         for_each_pipe(dev_priv, pipe) {
12842                 intel_crtc_init(dev, pipe);
12843                 for_each_sprite(pipe, sprite) {
12844                         ret = intel_plane_init(dev, pipe, sprite);
12845                         if (ret)
12846                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12847                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12848                 }
12849         }
12850
12851         intel_init_dpio(dev);
12852
12853         intel_shared_dpll_init(dev);
12854
12855         /* save the BIOS value before clobbering it */
12856         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12857         /* Just disable it once at startup */
12858         i915_disable_vga(dev);
12859         intel_setup_outputs(dev);
12860
12861         /* Just in case the BIOS is doing something questionable. */
12862         intel_disable_fbc(dev);
12863
12864         drm_modeset_lock_all(dev);
12865         intel_modeset_setup_hw_state(dev, false);
12866         drm_modeset_unlock_all(dev);
12867
12868         for_each_intel_crtc(dev, crtc) {
12869                 if (!crtc->active)
12870                         continue;
12871
12872                 /*
12873                  * Note that reserving the BIOS fb up front prevents us
12874                  * from stuffing other stolen allocations like the ring
12875                  * on top.  This prevents some ugliness at boot time, and
12876                  * can even allow for smooth boot transitions if the BIOS
12877                  * fb is large enough for the active pipe configuration.
12878                  */
12879                 if (dev_priv->display.get_plane_config) {
12880                         dev_priv->display.get_plane_config(crtc,
12881                                                            &crtc->plane_config);
12882                         /*
12883                          * If the fb is shared between multiple heads, we'll
12884                          * just get the first one.
12885                          */
12886                         intel_find_plane_obj(crtc, &crtc->plane_config);
12887                 }
12888         }
12889 }
12890
12891 static void intel_enable_pipe_a(struct drm_device *dev)
12892 {
12893         struct intel_connector *connector;
12894         struct drm_connector *crt = NULL;
12895         struct intel_load_detect_pipe load_detect_temp;
12896         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12897
12898         /* We can't just switch on the pipe A, we need to set things up with a
12899          * proper mode and output configuration. As a gross hack, enable pipe A
12900          * by enabling the load detect pipe once. */
12901         list_for_each_entry(connector,
12902                             &dev->mode_config.connector_list,
12903                             base.head) {
12904                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12905                         crt = &connector->base;
12906                         break;
12907                 }
12908         }
12909
12910         if (!crt)
12911                 return;
12912
12913         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12914                 intel_release_load_detect_pipe(crt, &load_detect_temp);
12915 }
12916
12917 static bool
12918 intel_check_plane_mapping(struct intel_crtc *crtc)
12919 {
12920         struct drm_device *dev = crtc->base.dev;
12921         struct drm_i915_private *dev_priv = dev->dev_private;
12922         u32 reg, val;
12923
12924         if (INTEL_INFO(dev)->num_pipes == 1)
12925                 return true;
12926
12927         reg = DSPCNTR(!crtc->plane);
12928         val = I915_READ(reg);
12929
12930         if ((val & DISPLAY_PLANE_ENABLE) &&
12931             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12932                 return false;
12933
12934         return true;
12935 }
12936
12937 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12938 {
12939         struct drm_device *dev = crtc->base.dev;
12940         struct drm_i915_private *dev_priv = dev->dev_private;
12941         u32 reg;
12942
12943         /* Clear any frame start delays used for debugging left by the BIOS */
12944         reg = PIPECONF(crtc->config.cpu_transcoder);
12945         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12946
12947         /* restore vblank interrupts to correct state */
12948         if (crtc->active) {
12949                 update_scanline_offset(crtc);
12950                 drm_vblank_on(dev, crtc->pipe);
12951         } else
12952                 drm_vblank_off(dev, crtc->pipe);
12953
12954         /* We need to sanitize the plane -> pipe mapping first because this will
12955          * disable the crtc (and hence change the state) if it is wrong. Note
12956          * that gen4+ has a fixed plane -> pipe mapping.  */
12957         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12958                 struct intel_connector *connector;
12959                 bool plane;
12960
12961                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12962                               crtc->base.base.id);
12963
12964                 /* Pipe has the wrong plane attached and the plane is active.
12965                  * Temporarily change the plane mapping and disable everything
12966                  * ...  */
12967                 plane = crtc->plane;
12968                 crtc->plane = !plane;
12969                 crtc->primary_enabled = true;
12970                 dev_priv->display.crtc_disable(&crtc->base);
12971                 crtc->plane = plane;
12972
12973                 /* ... and break all links. */
12974                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12975                                     base.head) {
12976                         if (connector->encoder->base.crtc != &crtc->base)
12977                                 continue;
12978
12979                         connector->base.dpms = DRM_MODE_DPMS_OFF;
12980                         connector->base.encoder = NULL;
12981                 }
12982                 /* multiple connectors may have the same encoder:
12983                  *  handle them and break crtc link separately */
12984                 list_for_each_entry(connector, &dev->mode_config.connector_list,
12985                                     base.head)
12986                         if (connector->encoder->base.crtc == &crtc->base) {
12987                                 connector->encoder->base.crtc = NULL;
12988                                 connector->encoder->connectors_active = false;
12989                         }
12990
12991                 WARN_ON(crtc->active);
12992                 crtc->base.enabled = false;
12993         }
12994
12995         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12996             crtc->pipe == PIPE_A && !crtc->active) {
12997                 /* BIOS forgot to enable pipe A, this mostly happens after
12998                  * resume. Force-enable the pipe to fix this, the update_dpms
12999                  * call below we restore the pipe to the right state, but leave
13000                  * the required bits on. */
13001                 intel_enable_pipe_a(dev);
13002         }
13003
13004         /* Adjust the state of the output pipe according to whether we
13005          * have active connectors/encoders. */
13006         intel_crtc_update_dpms(&crtc->base);
13007
13008         if (crtc->active != crtc->base.enabled) {
13009                 struct intel_encoder *encoder;
13010
13011                 /* This can happen either due to bugs in the get_hw_state
13012                  * functions or because the pipe is force-enabled due to the
13013                  * pipe A quirk. */
13014                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13015                               crtc->base.base.id,
13016                               crtc->base.enabled ? "enabled" : "disabled",
13017                               crtc->active ? "enabled" : "disabled");
13018
13019                 crtc->base.enabled = crtc->active;
13020
13021                 /* Because we only establish the connector -> encoder ->
13022                  * crtc links if something is active, this means the
13023                  * crtc is now deactivated. Break the links. connector
13024                  * -> encoder links are only establish when things are
13025                  *  actually up, hence no need to break them. */
13026                 WARN_ON(crtc->active);
13027
13028                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13029                         WARN_ON(encoder->connectors_active);
13030                         encoder->base.crtc = NULL;
13031                 }
13032         }
13033
13034         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13035                 /*
13036                  * We start out with underrun reporting disabled to avoid races.
13037                  * For correct bookkeeping mark this on active crtcs.
13038                  *
13039                  * Also on gmch platforms we dont have any hardware bits to
13040                  * disable the underrun reporting. Which means we need to start
13041                  * out with underrun reporting disabled also on inactive pipes,
13042                  * since otherwise we'll complain about the garbage we read when
13043                  * e.g. coming up after runtime pm.
13044                  *
13045                  * No protection against concurrent access is required - at
13046                  * worst a fifo underrun happens which also sets this to false.
13047                  */
13048                 crtc->cpu_fifo_underrun_disabled = true;
13049                 crtc->pch_fifo_underrun_disabled = true;
13050         }
13051 }
13052
13053 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13054 {
13055         struct intel_connector *connector;
13056         struct drm_device *dev = encoder->base.dev;
13057
13058         /* We need to check both for a crtc link (meaning that the
13059          * encoder is active and trying to read from a pipe) and the
13060          * pipe itself being active. */
13061         bool has_active_crtc = encoder->base.crtc &&
13062                 to_intel_crtc(encoder->base.crtc)->active;
13063
13064         if (encoder->connectors_active && !has_active_crtc) {
13065                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13066                               encoder->base.base.id,
13067                               encoder->base.name);
13068
13069                 /* Connector is active, but has no active pipe. This is
13070                  * fallout from our resume register restoring. Disable
13071                  * the encoder manually again. */
13072                 if (encoder->base.crtc) {
13073                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13074                                       encoder->base.base.id,
13075                                       encoder->base.name);
13076                         encoder->disable(encoder);
13077                         if (encoder->post_disable)
13078                                 encoder->post_disable(encoder);
13079                 }
13080                 encoder->base.crtc = NULL;
13081                 encoder->connectors_active = false;
13082
13083                 /* Inconsistent output/port/pipe state happens presumably due to
13084                  * a bug in one of the get_hw_state functions. Or someplace else
13085                  * in our code, like the register restore mess on resume. Clamp
13086                  * things to off as a safer default. */
13087                 list_for_each_entry(connector,
13088                                     &dev->mode_config.connector_list,
13089                                     base.head) {
13090                         if (connector->encoder != encoder)
13091                                 continue;
13092                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13093                         connector->base.encoder = NULL;
13094                 }
13095         }
13096         /* Enabled encoders without active connectors will be fixed in
13097          * the crtc fixup. */
13098 }
13099
13100 void i915_redisable_vga_power_on(struct drm_device *dev)
13101 {
13102         struct drm_i915_private *dev_priv = dev->dev_private;
13103         u32 vga_reg = i915_vgacntrl_reg(dev);
13104
13105         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13106                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13107                 i915_disable_vga(dev);
13108         }
13109 }
13110
13111 void i915_redisable_vga(struct drm_device *dev)
13112 {
13113         struct drm_i915_private *dev_priv = dev->dev_private;
13114
13115         /* This function can be called both from intel_modeset_setup_hw_state or
13116          * at a very early point in our resume sequence, where the power well
13117          * structures are not yet restored. Since this function is at a very
13118          * paranoid "someone might have enabled VGA while we were not looking"
13119          * level, just check if the power well is enabled instead of trying to
13120          * follow the "don't touch the power well if we don't need it" policy
13121          * the rest of the driver uses. */
13122         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13123                 return;
13124
13125         i915_redisable_vga_power_on(dev);
13126 }
13127
13128 static bool primary_get_hw_state(struct intel_crtc *crtc)
13129 {
13130         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13131
13132         if (!crtc->active)
13133                 return false;
13134
13135         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13136 }
13137
13138 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13139 {
13140         struct drm_i915_private *dev_priv = dev->dev_private;
13141         enum pipe pipe;
13142         struct intel_crtc *crtc;
13143         struct intel_encoder *encoder;
13144         struct intel_connector *connector;
13145         int i;
13146
13147         for_each_intel_crtc(dev, crtc) {
13148                 memset(&crtc->config, 0, sizeof(crtc->config));
13149
13150                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13151
13152                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13153                                                                  &crtc->config);
13154
13155                 crtc->base.enabled = crtc->active;
13156                 crtc->primary_enabled = primary_get_hw_state(crtc);
13157
13158                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13159                               crtc->base.base.id,
13160                               crtc->active ? "enabled" : "disabled");
13161         }
13162
13163         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13164                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13165
13166                 pll->on = pll->get_hw_state(dev_priv, pll,
13167                                             &pll->config.hw_state);
13168                 pll->active = 0;
13169                 pll->config.crtc_mask = 0;
13170                 for_each_intel_crtc(dev, crtc) {
13171                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13172                                 pll->active++;
13173                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13174                         }
13175                 }
13176
13177                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13178                               pll->name, pll->config.crtc_mask, pll->on);
13179
13180                 if (pll->config.crtc_mask)
13181                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13182         }
13183
13184         for_each_intel_encoder(dev, encoder) {
13185                 pipe = 0;
13186
13187                 if (encoder->get_hw_state(encoder, &pipe)) {
13188                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13189                         encoder->base.crtc = &crtc->base;
13190                         encoder->get_config(encoder, &crtc->config);
13191                 } else {
13192                         encoder->base.crtc = NULL;
13193                 }
13194
13195                 encoder->connectors_active = false;
13196                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13197                               encoder->base.base.id,
13198                               encoder->base.name,
13199                               encoder->base.crtc ? "enabled" : "disabled",
13200                               pipe_name(pipe));
13201         }
13202
13203         list_for_each_entry(connector, &dev->mode_config.connector_list,
13204                             base.head) {
13205                 if (connector->get_hw_state(connector)) {
13206                         connector->base.dpms = DRM_MODE_DPMS_ON;
13207                         connector->encoder->connectors_active = true;
13208                         connector->base.encoder = &connector->encoder->base;
13209                 } else {
13210                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13211                         connector->base.encoder = NULL;
13212                 }
13213                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13214                               connector->base.base.id,
13215                               connector->base.name,
13216                               connector->base.encoder ? "enabled" : "disabled");
13217         }
13218 }
13219
13220 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13221  * and i915 state tracking structures. */
13222 void intel_modeset_setup_hw_state(struct drm_device *dev,
13223                                   bool force_restore)
13224 {
13225         struct drm_i915_private *dev_priv = dev->dev_private;
13226         enum pipe pipe;
13227         struct intel_crtc *crtc;
13228         struct intel_encoder *encoder;
13229         int i;
13230
13231         intel_modeset_readout_hw_state(dev);
13232
13233         /*
13234          * Now that we have the config, copy it to each CRTC struct
13235          * Note that this could go away if we move to using crtc_config
13236          * checking everywhere.
13237          */
13238         for_each_intel_crtc(dev, crtc) {
13239                 if (crtc->active && i915.fastboot) {
13240                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13241                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13242                                       crtc->base.base.id);
13243                         drm_mode_debug_printmodeline(&crtc->base.mode);
13244                 }
13245         }
13246
13247         /* HW state is read out, now we need to sanitize this mess. */
13248         for_each_intel_encoder(dev, encoder) {
13249                 intel_sanitize_encoder(encoder);
13250         }
13251
13252         for_each_pipe(dev_priv, pipe) {
13253                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13254                 intel_sanitize_crtc(crtc);
13255                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13256         }
13257
13258         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13259                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13260
13261                 if (!pll->on || pll->active)
13262                         continue;
13263
13264                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13265
13266                 pll->disable(dev_priv, pll);
13267                 pll->on = false;
13268         }
13269
13270         if (HAS_PCH_SPLIT(dev))
13271                 ilk_wm_get_hw_state(dev);
13272
13273         if (force_restore) {
13274                 i915_redisable_vga(dev);
13275
13276                 /*
13277                  * We need to use raw interfaces for restoring state to avoid
13278                  * checking (bogus) intermediate states.
13279                  */
13280                 for_each_pipe(dev_priv, pipe) {
13281                         struct drm_crtc *crtc =
13282                                 dev_priv->pipe_to_crtc_mapping[pipe];
13283
13284                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13285                                          crtc->primary->fb);
13286                 }
13287         } else {
13288                 intel_modeset_update_staged_output_state(dev);
13289         }
13290
13291         intel_modeset_check_state(dev);
13292 }
13293
13294 void intel_modeset_gem_init(struct drm_device *dev)
13295 {
13296         struct drm_crtc *c;
13297         struct drm_i915_gem_object *obj;
13298
13299         mutex_lock(&dev->struct_mutex);
13300         intel_init_gt_powersave(dev);
13301         mutex_unlock(&dev->struct_mutex);
13302
13303         intel_modeset_init_hw(dev);
13304
13305         intel_setup_overlay(dev);
13306
13307         /*
13308          * Make sure any fbs we allocated at startup are properly
13309          * pinned & fenced.  When we do the allocation it's too early
13310          * for this.
13311          */
13312         mutex_lock(&dev->struct_mutex);
13313         for_each_crtc(dev, c) {
13314                 obj = intel_fb_obj(c->primary->fb);
13315                 if (obj == NULL)
13316                         continue;
13317
13318                 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13319                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13320                                   to_intel_crtc(c)->pipe);
13321                         drm_framebuffer_unreference(c->primary->fb);
13322                         c->primary->fb = NULL;
13323                 }
13324         }
13325         mutex_unlock(&dev->struct_mutex);
13326 }
13327
13328 void intel_connector_unregister(struct intel_connector *intel_connector)
13329 {
13330         struct drm_connector *connector = &intel_connector->base;
13331
13332         intel_panel_destroy_backlight(connector);
13333         drm_connector_unregister(connector);
13334 }
13335
13336 void intel_modeset_cleanup(struct drm_device *dev)
13337 {
13338         struct drm_i915_private *dev_priv = dev->dev_private;
13339         struct drm_connector *connector;
13340
13341         /*
13342          * Interrupts and polling as the first thing to avoid creating havoc.
13343          * Too much stuff here (turning of rps, connectors, ...) would
13344          * experience fancy races otherwise.
13345          */
13346         intel_irq_uninstall(dev_priv);
13347
13348         /*
13349          * Due to the hpd irq storm handling the hotplug work can re-arm the
13350          * poll handlers. Hence disable polling after hpd handling is shut down.
13351          */
13352         drm_kms_helper_poll_fini(dev);
13353
13354         mutex_lock(&dev->struct_mutex);
13355
13356         intel_unregister_dsm_handler();
13357
13358         intel_disable_fbc(dev);
13359
13360         intel_disable_gt_powersave(dev);
13361
13362         ironlake_teardown_rc6(dev);
13363
13364         mutex_unlock(&dev->struct_mutex);
13365
13366         /* flush any delayed tasks or pending work */
13367         flush_scheduled_work();
13368
13369         /* destroy the backlight and sysfs files before encoders/connectors */
13370         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13371                 struct intel_connector *intel_connector;
13372
13373                 intel_connector = to_intel_connector(connector);
13374                 intel_connector->unregister(intel_connector);
13375         }
13376
13377         drm_mode_config_cleanup(dev);
13378
13379         intel_cleanup_overlay(dev);
13380
13381         mutex_lock(&dev->struct_mutex);
13382         intel_cleanup_gt_powersave(dev);
13383         mutex_unlock(&dev->struct_mutex);
13384 }
13385
13386 /*
13387  * Return which encoder is currently attached for connector.
13388  */
13389 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13390 {
13391         return &intel_attached_encoder(connector)->base;
13392 }
13393
13394 void intel_connector_attach_encoder(struct intel_connector *connector,
13395                                     struct intel_encoder *encoder)
13396 {
13397         connector->encoder = encoder;
13398         drm_mode_connector_attach_encoder(&connector->base,
13399                                           &encoder->base);
13400 }
13401
13402 /*
13403  * set vga decode state - true == enable VGA decode
13404  */
13405 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13406 {
13407         struct drm_i915_private *dev_priv = dev->dev_private;
13408         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13409         u16 gmch_ctrl;
13410
13411         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13412                 DRM_ERROR("failed to read control word\n");
13413                 return -EIO;
13414         }
13415
13416         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13417                 return 0;
13418
13419         if (state)
13420                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13421         else
13422                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13423
13424         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13425                 DRM_ERROR("failed to write control word\n");
13426                 return -EIO;
13427         }
13428
13429         return 0;
13430 }
13431
13432 struct intel_display_error_state {
13433
13434         u32 power_well_driver;
13435
13436         int num_transcoders;
13437
13438         struct intel_cursor_error_state {
13439                 u32 control;
13440                 u32 position;
13441                 u32 base;
13442                 u32 size;
13443         } cursor[I915_MAX_PIPES];
13444
13445         struct intel_pipe_error_state {
13446                 bool power_domain_on;
13447                 u32 source;
13448                 u32 stat;
13449         } pipe[I915_MAX_PIPES];
13450
13451         struct intel_plane_error_state {
13452                 u32 control;
13453                 u32 stride;
13454                 u32 size;
13455                 u32 pos;
13456                 u32 addr;
13457                 u32 surface;
13458                 u32 tile_offset;
13459         } plane[I915_MAX_PIPES];
13460
13461         struct intel_transcoder_error_state {
13462                 bool power_domain_on;
13463                 enum transcoder cpu_transcoder;
13464
13465                 u32 conf;
13466
13467                 u32 htotal;
13468                 u32 hblank;
13469                 u32 hsync;
13470                 u32 vtotal;
13471                 u32 vblank;
13472                 u32 vsync;
13473         } transcoder[4];
13474 };
13475
13476 struct intel_display_error_state *
13477 intel_display_capture_error_state(struct drm_device *dev)
13478 {
13479         struct drm_i915_private *dev_priv = dev->dev_private;
13480         struct intel_display_error_state *error;
13481         int transcoders[] = {
13482                 TRANSCODER_A,
13483                 TRANSCODER_B,
13484                 TRANSCODER_C,
13485                 TRANSCODER_EDP,
13486         };
13487         int i;
13488
13489         if (INTEL_INFO(dev)->num_pipes == 0)
13490                 return NULL;
13491
13492         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13493         if (error == NULL)
13494                 return NULL;
13495
13496         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13497                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13498
13499         for_each_pipe(dev_priv, i) {
13500                 error->pipe[i].power_domain_on =
13501                         __intel_display_power_is_enabled(dev_priv,
13502                                                          POWER_DOMAIN_PIPE(i));
13503                 if (!error->pipe[i].power_domain_on)
13504                         continue;
13505
13506                 error->cursor[i].control = I915_READ(CURCNTR(i));
13507                 error->cursor[i].position = I915_READ(CURPOS(i));
13508                 error->cursor[i].base = I915_READ(CURBASE(i));
13509
13510                 error->plane[i].control = I915_READ(DSPCNTR(i));
13511                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13512                 if (INTEL_INFO(dev)->gen <= 3) {
13513                         error->plane[i].size = I915_READ(DSPSIZE(i));
13514                         error->plane[i].pos = I915_READ(DSPPOS(i));
13515                 }
13516                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13517                         error->plane[i].addr = I915_READ(DSPADDR(i));
13518                 if (INTEL_INFO(dev)->gen >= 4) {
13519                         error->plane[i].surface = I915_READ(DSPSURF(i));
13520                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13521                 }
13522
13523                 error->pipe[i].source = I915_READ(PIPESRC(i));
13524
13525                 if (HAS_GMCH_DISPLAY(dev))
13526                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13527         }
13528
13529         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13530         if (HAS_DDI(dev_priv->dev))
13531                 error->num_transcoders++; /* Account for eDP. */
13532
13533         for (i = 0; i < error->num_transcoders; i++) {
13534                 enum transcoder cpu_transcoder = transcoders[i];
13535
13536                 error->transcoder[i].power_domain_on =
13537                         __intel_display_power_is_enabled(dev_priv,
13538                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13539                 if (!error->transcoder[i].power_domain_on)
13540                         continue;
13541
13542                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13543
13544                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13545                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13546                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13547                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13548                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13549                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13550                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13551         }
13552
13553         return error;
13554 }
13555
13556 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13557
13558 void
13559 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13560                                 struct drm_device *dev,
13561                                 struct intel_display_error_state *error)
13562 {
13563         struct drm_i915_private *dev_priv = dev->dev_private;
13564         int i;
13565
13566         if (!error)
13567                 return;
13568
13569         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13570         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13571                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13572                            error->power_well_driver);
13573         for_each_pipe(dev_priv, i) {
13574                 err_printf(m, "Pipe [%d]:\n", i);
13575                 err_printf(m, "  Power: %s\n",
13576                            error->pipe[i].power_domain_on ? "on" : "off");
13577                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13578                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13579
13580                 err_printf(m, "Plane [%d]:\n", i);
13581                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13582                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13583                 if (INTEL_INFO(dev)->gen <= 3) {
13584                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13585                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13586                 }
13587                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13588                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13589                 if (INTEL_INFO(dev)->gen >= 4) {
13590                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13591                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13592                 }
13593
13594                 err_printf(m, "Cursor [%d]:\n", i);
13595                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13596                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13597                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13598         }
13599
13600         for (i = 0; i < error->num_transcoders; i++) {
13601                 err_printf(m, "CPU transcoder: %c\n",
13602                            transcoder_name(error->transcoder[i].cpu_transcoder));
13603                 err_printf(m, "  Power: %s\n",
13604                            error->transcoder[i].power_domain_on ? "on" : "off");
13605                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13606                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13607                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13608                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13609                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13610                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13611                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13612         }
13613 }
13614
13615 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13616 {
13617         struct intel_crtc *crtc;
13618
13619         for_each_intel_crtc(dev, crtc) {
13620                 struct intel_unpin_work *work;
13621
13622                 spin_lock_irq(&dev->event_lock);
13623
13624                 work = crtc->unpin_work;
13625
13626                 if (work && work->event &&
13627                     work->event->base.file_priv == file) {
13628                         kfree(work->event);
13629                         work->event = NULL;
13630                 }
13631
13632                 spin_unlock_irq(&dev->event_lock);
13633         }
13634 }