2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/kernel.h>
30 #include "intel_drv.h"
35 #include "drm_crtc_helper.h"
37 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
38 static void intel_update_watermarks(struct drm_device *dev);
61 #define INTEL_P2_NUM 2
62 typedef struct intel_limit intel_limit_t;
64 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
67 int, int, intel_clock_t *);
70 #define I8XX_DOT_MIN 25000
71 #define I8XX_DOT_MAX 350000
72 #define I8XX_VCO_MIN 930000
73 #define I8XX_VCO_MAX 1400000
77 #define I8XX_M_MAX 140
78 #define I8XX_M1_MIN 18
79 #define I8XX_M1_MAX 26
81 #define I8XX_M2_MAX 16
83 #define I8XX_P_MAX 128
85 #define I8XX_P1_MAX 33
86 #define I8XX_P1_LVDS_MIN 1
87 #define I8XX_P1_LVDS_MAX 6
88 #define I8XX_P2_SLOW 4
89 #define I8XX_P2_FAST 2
90 #define I8XX_P2_LVDS_SLOW 14
91 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
92 #define I8XX_P2_SLOW_LIMIT 165000
94 #define I9XX_DOT_MIN 20000
95 #define I9XX_DOT_MAX 400000
96 #define I9XX_VCO_MIN 1400000
97 #define I9XX_VCO_MAX 2800000
98 #define IGD_VCO_MIN 1700000
99 #define IGD_VCO_MAX 3500000
102 /* IGD's Ncounter is a ring counter */
105 #define I9XX_M_MIN 70
106 #define I9XX_M_MAX 120
108 #define IGD_M_MAX 256
109 #define I9XX_M1_MIN 10
110 #define I9XX_M1_MAX 22
111 #define I9XX_M2_MIN 5
112 #define I9XX_M2_MAX 9
113 /* IGD M1 is reserved, and must be 0 */
117 #define IGD_M2_MAX 254
118 #define I9XX_P_SDVO_DAC_MIN 5
119 #define I9XX_P_SDVO_DAC_MAX 80
120 #define I9XX_P_LVDS_MIN 7
121 #define I9XX_P_LVDS_MAX 98
122 #define IGD_P_LVDS_MIN 7
123 #define IGD_P_LVDS_MAX 112
124 #define I9XX_P1_MIN 1
125 #define I9XX_P1_MAX 8
126 #define I9XX_P2_SDVO_DAC_SLOW 10
127 #define I9XX_P2_SDVO_DAC_FAST 5
128 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
129 #define I9XX_P2_LVDS_SLOW 14
130 #define I9XX_P2_LVDS_FAST 7
131 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
133 /*The parameter is for SDVO on G4x platform*/
134 #define G4X_DOT_SDVO_MIN 25000
135 #define G4X_DOT_SDVO_MAX 270000
136 #define G4X_VCO_MIN 1750000
137 #define G4X_VCO_MAX 3500000
138 #define G4X_N_SDVO_MIN 1
139 #define G4X_N_SDVO_MAX 4
140 #define G4X_M_SDVO_MIN 104
141 #define G4X_M_SDVO_MAX 138
142 #define G4X_M1_SDVO_MIN 17
143 #define G4X_M1_SDVO_MAX 23
144 #define G4X_M2_SDVO_MIN 5
145 #define G4X_M2_SDVO_MAX 11
146 #define G4X_P_SDVO_MIN 10
147 #define G4X_P_SDVO_MAX 30
148 #define G4X_P1_SDVO_MIN 1
149 #define G4X_P1_SDVO_MAX 3
150 #define G4X_P2_SDVO_SLOW 10
151 #define G4X_P2_SDVO_FAST 10
152 #define G4X_P2_SDVO_LIMIT 270000
154 /*The parameter is for HDMI_DAC on G4x platform*/
155 #define G4X_DOT_HDMI_DAC_MIN 22000
156 #define G4X_DOT_HDMI_DAC_MAX 400000
157 #define G4X_N_HDMI_DAC_MIN 1
158 #define G4X_N_HDMI_DAC_MAX 4
159 #define G4X_M_HDMI_DAC_MIN 104
160 #define G4X_M_HDMI_DAC_MAX 138
161 #define G4X_M1_HDMI_DAC_MIN 16
162 #define G4X_M1_HDMI_DAC_MAX 23
163 #define G4X_M2_HDMI_DAC_MIN 5
164 #define G4X_M2_HDMI_DAC_MAX 11
165 #define G4X_P_HDMI_DAC_MIN 5
166 #define G4X_P_HDMI_DAC_MAX 80
167 #define G4X_P1_HDMI_DAC_MIN 1
168 #define G4X_P1_HDMI_DAC_MAX 8
169 #define G4X_P2_HDMI_DAC_SLOW 10
170 #define G4X_P2_HDMI_DAC_FAST 5
171 #define G4X_P2_HDMI_DAC_LIMIT 165000
173 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
174 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
175 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
176 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
177 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
178 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
179 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
180 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
181 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
182 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
183 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
184 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
185 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
186 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
187 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
188 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
189 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
190 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
192 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
193 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
194 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
195 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
196 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
197 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
198 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
199 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
200 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
201 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
202 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
203 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
204 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
205 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
206 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
207 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
208 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
209 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
211 /*The parameter is for DISPLAY PORT on G4x platform*/
212 #define G4X_DOT_DISPLAY_PORT_MIN 161670
213 #define G4X_DOT_DISPLAY_PORT_MAX 227000
214 #define G4X_N_DISPLAY_PORT_MIN 1
215 #define G4X_N_DISPLAY_PORT_MAX 2
216 #define G4X_M_DISPLAY_PORT_MIN 97
217 #define G4X_M_DISPLAY_PORT_MAX 108
218 #define G4X_M1_DISPLAY_PORT_MIN 0x10
219 #define G4X_M1_DISPLAY_PORT_MAX 0x12
220 #define G4X_M2_DISPLAY_PORT_MIN 0x05
221 #define G4X_M2_DISPLAY_PORT_MAX 0x06
222 #define G4X_P_DISPLAY_PORT_MIN 10
223 #define G4X_P_DISPLAY_PORT_MAX 20
224 #define G4X_P1_DISPLAY_PORT_MIN 1
225 #define G4X_P1_DISPLAY_PORT_MAX 2
226 #define G4X_P2_DISPLAY_PORT_SLOW 10
227 #define G4X_P2_DISPLAY_PORT_FAST 10
228 #define G4X_P2_DISPLAY_PORT_LIMIT 0
231 /* as we calculate clock using (register_value + 2) for
232 N/M1/M2, so here the range value for them is (actual_value-2).
234 #define IGDNG_DOT_MIN 25000
235 #define IGDNG_DOT_MAX 350000
236 #define IGDNG_VCO_MIN 1760000
237 #define IGDNG_VCO_MAX 3510000
238 #define IGDNG_N_MIN 1
239 #define IGDNG_N_MAX 5
240 #define IGDNG_M_MIN 79
241 #define IGDNG_M_MAX 118
242 #define IGDNG_M1_MIN 12
243 #define IGDNG_M1_MAX 23
244 #define IGDNG_M2_MIN 5
245 #define IGDNG_M2_MAX 9
246 #define IGDNG_P_SDVO_DAC_MIN 5
247 #define IGDNG_P_SDVO_DAC_MAX 80
248 #define IGDNG_P_LVDS_MIN 28
249 #define IGDNG_P_LVDS_MAX 112
250 #define IGDNG_P1_MIN 1
251 #define IGDNG_P1_MAX 8
252 #define IGDNG_P2_SDVO_DAC_SLOW 10
253 #define IGDNG_P2_SDVO_DAC_FAST 5
254 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
255 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
256 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
259 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
260 int target, int refclk, intel_clock_t *best_clock);
262 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
263 int target, int refclk, intel_clock_t *best_clock);
265 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
266 int target, int refclk, intel_clock_t *best_clock);
269 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
272 static const intel_limit_t intel_limits_i8xx_dvo = {
273 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
274 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
275 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
276 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
277 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
278 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
279 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
280 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
281 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
282 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
283 .find_pll = intel_find_best_PLL,
286 static const intel_limit_t intel_limits_i8xx_lvds = {
287 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
288 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
289 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
290 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
291 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
292 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
293 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
294 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
295 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
296 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
297 .find_pll = intel_find_best_PLL,
300 static const intel_limit_t intel_limits_i9xx_sdvo = {
301 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
302 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
303 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
304 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
305 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
306 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
307 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
308 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
309 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
310 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
311 .find_pll = intel_find_best_PLL,
314 static const intel_limit_t intel_limits_i9xx_lvds = {
315 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
316 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
317 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
318 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
319 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
320 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
321 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
322 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
323 /* The single-channel range is 25-112Mhz, and dual-channel
324 * is 80-224Mhz. Prefer single channel as much as possible.
326 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
327 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
328 .find_pll = intel_find_best_PLL,
331 /* below parameter and function is for G4X Chipset Family*/
332 static const intel_limit_t intel_limits_g4x_sdvo = {
333 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
334 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
335 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
336 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
337 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
338 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
339 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
340 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
341 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
342 .p2_slow = G4X_P2_SDVO_SLOW,
343 .p2_fast = G4X_P2_SDVO_FAST
345 .find_pll = intel_g4x_find_best_PLL,
348 static const intel_limit_t intel_limits_g4x_hdmi = {
349 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
350 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
351 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
352 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
353 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
354 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
355 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
356 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
357 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
358 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
359 .p2_fast = G4X_P2_HDMI_DAC_FAST
361 .find_pll = intel_g4x_find_best_PLL,
364 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
365 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
366 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
367 .vco = { .min = G4X_VCO_MIN,
368 .max = G4X_VCO_MAX },
369 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
370 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
371 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
372 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
373 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
374 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
375 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
376 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
377 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
378 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
379 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
380 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
381 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
382 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
383 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
385 .find_pll = intel_g4x_find_best_PLL,
388 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
389 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
390 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
391 .vco = { .min = G4X_VCO_MIN,
392 .max = G4X_VCO_MAX },
393 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
394 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
395 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
396 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
397 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
398 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
399 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
400 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
401 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
402 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
403 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
404 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
405 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
406 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
407 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
409 .find_pll = intel_g4x_find_best_PLL,
412 static const intel_limit_t intel_limits_g4x_display_port = {
413 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
414 .max = G4X_DOT_DISPLAY_PORT_MAX },
415 .vco = { .min = G4X_VCO_MIN,
417 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
418 .max = G4X_N_DISPLAY_PORT_MAX },
419 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
420 .max = G4X_M_DISPLAY_PORT_MAX },
421 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
422 .max = G4X_M1_DISPLAY_PORT_MAX },
423 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
424 .max = G4X_M2_DISPLAY_PORT_MAX },
425 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
426 .max = G4X_P_DISPLAY_PORT_MAX },
427 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
428 .max = G4X_P1_DISPLAY_PORT_MAX},
429 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
430 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
431 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
432 .find_pll = intel_find_pll_g4x_dp,
435 static const intel_limit_t intel_limits_igd_sdvo = {
436 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
437 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
438 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
439 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
440 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
441 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
442 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
443 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
444 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
445 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
446 .find_pll = intel_find_best_PLL,
449 static const intel_limit_t intel_limits_igd_lvds = {
450 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
451 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
452 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
453 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
454 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
455 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
456 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
457 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
458 /* IGD only supports single-channel mode. */
459 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
460 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
461 .find_pll = intel_find_best_PLL,
464 static const intel_limit_t intel_limits_igdng_sdvo = {
465 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
466 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
467 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
468 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
469 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
470 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
471 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
472 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
473 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
474 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
475 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
476 .find_pll = intel_igdng_find_best_PLL,
479 static const intel_limit_t intel_limits_igdng_lvds = {
480 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
481 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
482 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
483 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
484 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
485 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
486 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
487 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
488 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
489 .p2_slow = IGDNG_P2_LVDS_SLOW,
490 .p2_fast = IGDNG_P2_LVDS_FAST },
491 .find_pll = intel_igdng_find_best_PLL,
494 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
496 const intel_limit_t *limit;
497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
498 limit = &intel_limits_igdng_lvds;
500 limit = &intel_limits_igdng_sdvo;
505 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
507 struct drm_device *dev = crtc->dev;
508 struct drm_i915_private *dev_priv = dev->dev_private;
509 const intel_limit_t *limit;
511 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
512 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
514 /* LVDS with dual channel */
515 limit = &intel_limits_g4x_dual_channel_lvds;
517 /* LVDS with dual channel */
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
538 limit = intel_igdng_limit(crtc);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_i9xx_lvds;
545 limit = &intel_limits_i9xx_sdvo;
546 } else if (IS_IGD(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
548 limit = &intel_limits_igd_lvds;
550 limit = &intel_limits_igd_sdvo;
552 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
553 limit = &intel_limits_i8xx_lvds;
555 limit = &intel_limits_i8xx_dvo;
560 /* m1 is reserved as 0 in IGD, n is a ring counter */
561 static void igd_clock(int refclk, intel_clock_t *clock)
563 clock->m = clock->m2 + 2;
564 clock->p = clock->p1 * clock->p2;
565 clock->vco = refclk * clock->m / clock->n;
566 clock->dot = clock->vco / clock->p;
569 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
572 igd_clock(refclk, clock);
575 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
576 clock->p = clock->p1 * clock->p2;
577 clock->vco = refclk * clock->m / (clock->n + 2);
578 clock->dot = clock->vco / clock->p;
582 * Returns whether any output on the specified pipe is of the specified type
584 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
586 struct drm_device *dev = crtc->dev;
587 struct drm_mode_config *mode_config = &dev->mode_config;
588 struct drm_connector *l_entry;
590 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
591 if (l_entry->encoder &&
592 l_entry->encoder->crtc == crtc) {
593 struct intel_output *intel_output = to_intel_output(l_entry);
594 if (intel_output->type == type)
601 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
603 * Returns whether the given set of divisors are valid for a given refclk with
604 * the given connectors.
607 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
609 const intel_limit_t *limit = intel_limit (crtc);
610 struct drm_device *dev = crtc->dev;
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid ("p1 out of range\n");
614 if (clock->p < limit->p.min || limit->p.max < clock->p)
615 INTELPllInvalid ("p out of range\n");
616 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
617 INTELPllInvalid ("m2 out of range\n");
618 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
619 INTELPllInvalid ("m1 out of range\n");
620 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
621 INTELPllInvalid ("m1 <= m2\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid ("m out of range\n");
624 if (clock->n < limit->n.min || limit->n.max < clock->n)
625 INTELPllInvalid ("n out of range\n");
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid ("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid ("dot out of range\n");
638 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
639 int target, int refclk, intel_clock_t *best_clock)
642 struct drm_device *dev = crtc->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
647 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
648 (I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
650 * For LVDS, if the panel is on, just rely on its current
651 * settings for dual-channel. We haven't figured out how to
652 * reliably set up different single/dual channel state, if we
655 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
657 clock.p2 = limit->p2.p2_fast;
659 clock.p2 = limit->p2.p2_slow;
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
664 clock.p2 = limit->p2.p2_fast;
667 memset (best_clock, 0, sizeof (*best_clock));
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
670 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in IGD */
672 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
674 for (clock.n = limit->n.min; clock.n <= limit->n.max;
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
680 intel_clock(dev, refclk, &clock);
682 if (!intel_PLL_is_valid(crtc, &clock))
685 this_err = abs(clock.dot - target);
686 if (this_err < err) {
695 return (err != target);
699 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
700 int target, int refclk, intel_clock_t *best_clock)
702 struct drm_device *dev = crtc->dev;
703 struct drm_i915_private *dev_priv = dev->dev_private;
707 /* approximately equals target * 0.00488 */
708 int err_most = (target >> 8) + (target >> 10);
711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
712 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
714 clock.p2 = limit->p2.p2_fast;
716 clock.p2 = limit->p2.p2_slow;
718 if (target < limit->p2.dot_limit)
719 clock.p2 = limit->p2.p2_slow;
721 clock.p2 = limit->p2.p2_fast;
724 memset(best_clock, 0, sizeof(*best_clock));
725 max_n = limit->n.max;
726 /* based on hardware requriment prefer smaller n to precision */
727 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
728 /* based on hardware requirment prefere larger m1,m2, p1 */
729 for (clock.m1 = limit->m1.max;
730 clock.m1 >= limit->m1.min; clock.m1--) {
731 for (clock.m2 = limit->m2.max;
732 clock.m2 >= limit->m2.min; clock.m2--) {
733 for (clock.p1 = limit->p1.max;
734 clock.p1 >= limit->p1.min; clock.p1--) {
737 intel_clock(dev, refclk, &clock);
738 if (!intel_PLL_is_valid(crtc, &clock))
740 this_err = abs(clock.dot - target) ;
741 if (this_err < err_most) {
755 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *best_clock)
758 struct drm_device *dev = crtc->dev;
759 struct drm_i915_private *dev_priv = dev->dev_private;
766 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
769 clock.p2 = limit->p2.p2_fast;
771 clock.p2 = limit->p2.p2_slow;
773 if (target < limit->p2.dot_limit)
774 clock.p2 = limit->p2.p2_slow;
776 clock.p2 = limit->p2.p2_fast;
779 memset(best_clock, 0, sizeof(*best_clock));
780 max_n = limit->n.max;
781 /* based on hardware requriment prefer smaller n to precision */
782 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
783 /* based on hardware requirment prefere larger m1,m2, p1 */
784 for (clock.m1 = limit->m1.max;
785 clock.m1 >= limit->m1.min; clock.m1--) {
786 for (clock.m2 = limit->m2.max;
787 clock.m2 >= limit->m2.min; clock.m2--) {
788 for (clock.p1 = limit->p1.max;
789 clock.p1 >= limit->p1.min; clock.p1--) {
792 intel_clock(dev, refclk, &clock);
793 if (!intel_PLL_is_valid(crtc, &clock))
795 this_err = abs((10000 - (target*10000/clock.dot)));
796 if (this_err < err_most) {
801 /* found on first matching */
812 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
814 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
815 int target, int refclk, intel_clock_t *best_clock)
818 if (target < 200000) {
831 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
832 clock.p = (clock.p1 * clock.p2);
833 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
834 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 intel_wait_for_vblank(struct drm_device *dev)
841 /* Wait for 20ms, i.e. one cycle at 50hz. */
846 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
847 struct drm_framebuffer *old_fb)
849 struct drm_device *dev = crtc->dev;
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 struct drm_i915_master_private *master_priv;
852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853 struct intel_framebuffer *intel_fb;
854 struct drm_i915_gem_object *obj_priv;
855 struct drm_gem_object *obj;
856 int pipe = intel_crtc->pipe;
857 unsigned long Start, Offset;
858 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
859 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
860 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
861 int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
862 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
863 u32 dspcntr, alignment;
868 DRM_DEBUG("No FB bound\n");
877 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
881 intel_fb = to_intel_framebuffer(crtc->fb);
883 obj_priv = obj->driver_private;
885 switch (obj_priv->tiling_mode) {
886 case I915_TILING_NONE:
887 alignment = 64 * 1024;
890 /* pin() will align the object as required by fence */
894 /* FIXME: Is this true? */
895 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
901 mutex_lock(&dev->struct_mutex);
902 ret = i915_gem_object_pin(obj, alignment);
904 mutex_unlock(&dev->struct_mutex);
908 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
910 i915_gem_object_unpin(obj);
911 mutex_unlock(&dev->struct_mutex);
915 /* Pre-i965 needs to install a fence for tiled scan-out */
916 if (!IS_I965G(dev) &&
917 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
918 obj_priv->tiling_mode != I915_TILING_NONE) {
919 ret = i915_gem_object_get_fence_reg(obj);
921 i915_gem_object_unpin(obj);
922 mutex_unlock(&dev->struct_mutex);
927 dspcntr = I915_READ(dspcntr_reg);
928 /* Mask out pixel format bits in case we change it */
929 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
930 switch (crtc->fb->bits_per_pixel) {
932 dspcntr |= DISPPLANE_8BPP;
935 if (crtc->fb->depth == 15)
936 dspcntr |= DISPPLANE_15_16BPP;
938 dspcntr |= DISPPLANE_16BPP;
942 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
945 DRM_ERROR("Unknown color depth\n");
946 i915_gem_object_unpin(obj);
947 mutex_unlock(&dev->struct_mutex);
951 if (obj_priv->tiling_mode != I915_TILING_NONE)
952 dspcntr |= DISPPLANE_TILED;
954 dspcntr &= ~DISPPLANE_TILED;
957 I915_WRITE(dspcntr_reg, dspcntr);
959 Start = obj_priv->gtt_offset;
960 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
962 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
963 I915_WRITE(dspstride, crtc->fb->pitch);
965 I915_WRITE(dspbase, Offset);
967 I915_WRITE(dspsurf, Start);
969 I915_WRITE(dsptileoff, (y << 16) | x);
971 I915_WRITE(dspbase, Start + Offset);
975 intel_wait_for_vblank(dev);
978 intel_fb = to_intel_framebuffer(old_fb);
979 i915_gem_object_unpin(intel_fb->obj);
981 mutex_unlock(&dev->struct_mutex);
983 if (!dev->primary->master)
986 master_priv = dev->primary->master->driver_priv;
987 if (!master_priv->sarea_priv)
991 master_priv->sarea_priv->pipeB_x = x;
992 master_priv->sarea_priv->pipeB_y = y;
994 master_priv->sarea_priv->pipeA_x = x;
995 master_priv->sarea_priv->pipeA_y = y;
1001 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1003 struct drm_device *dev = crtc->dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 int pipe = intel_crtc->pipe;
1007 int plane = intel_crtc->plane;
1008 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1009 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1010 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1011 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1012 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1013 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1014 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1015 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1016 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1017 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1018 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1019 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1020 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1021 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1022 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1023 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1024 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1025 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1026 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1027 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1028 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1029 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1033 /* XXX: When our outputs are all unaware of DPMS modes other than off
1034 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1037 case DRM_MODE_DPMS_ON:
1038 case DRM_MODE_DPMS_STANDBY:
1039 case DRM_MODE_DPMS_SUSPEND:
1040 DRM_DEBUG("crtc %d dpms on\n", pipe);
1041 /* enable PCH DPLL */
1042 temp = I915_READ(pch_dpll_reg);
1043 if ((temp & DPLL_VCO_ENABLE) == 0) {
1044 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1045 I915_READ(pch_dpll_reg);
1048 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1049 temp = I915_READ(fdi_rx_reg);
1050 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1052 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1053 I915_READ(fdi_rx_reg);
1056 /* Enable CPU FDI TX PLL, always on for IGDNG */
1057 temp = I915_READ(fdi_tx_reg);
1058 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1059 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1060 I915_READ(fdi_tx_reg);
1064 /* Enable CPU pipe */
1065 temp = I915_READ(pipeconf_reg);
1066 if ((temp & PIPEACONF_ENABLE) == 0) {
1067 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1068 I915_READ(pipeconf_reg);
1072 /* configure and enable CPU plane */
1073 temp = I915_READ(dspcntr_reg);
1074 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1075 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1076 /* Flush the plane changes */
1077 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1080 /* enable CPU FDI TX and PCH FDI RX */
1081 temp = I915_READ(fdi_tx_reg);
1082 temp |= FDI_TX_ENABLE;
1083 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1084 temp &= ~FDI_LINK_TRAIN_NONE;
1085 temp |= FDI_LINK_TRAIN_PATTERN_1;
1086 I915_WRITE(fdi_tx_reg, temp);
1087 I915_READ(fdi_tx_reg);
1089 temp = I915_READ(fdi_rx_reg);
1090 temp &= ~FDI_LINK_TRAIN_NONE;
1091 temp |= FDI_LINK_TRAIN_PATTERN_1;
1092 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1093 I915_READ(fdi_rx_reg);
1098 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1100 temp = I915_READ(fdi_rx_imr_reg);
1101 temp &= ~FDI_RX_SYMBOL_LOCK;
1102 temp &= ~FDI_RX_BIT_LOCK;
1103 I915_WRITE(fdi_rx_imr_reg, temp);
1104 I915_READ(fdi_rx_imr_reg);
1107 temp = I915_READ(fdi_rx_iir_reg);
1108 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1110 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1111 for (j = 0; j < tries; j++) {
1112 temp = I915_READ(fdi_rx_iir_reg);
1113 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1114 if (temp & FDI_RX_BIT_LOCK)
1119 I915_WRITE(fdi_rx_iir_reg,
1120 temp | FDI_RX_BIT_LOCK);
1122 DRM_DEBUG("train 1 fail\n");
1124 I915_WRITE(fdi_rx_iir_reg,
1125 temp | FDI_RX_BIT_LOCK);
1126 DRM_DEBUG("train 1 ok 2!\n");
1128 temp = I915_READ(fdi_tx_reg);
1129 temp &= ~FDI_LINK_TRAIN_NONE;
1130 temp |= FDI_LINK_TRAIN_PATTERN_2;
1131 I915_WRITE(fdi_tx_reg, temp);
1133 temp = I915_READ(fdi_rx_reg);
1134 temp &= ~FDI_LINK_TRAIN_NONE;
1135 temp |= FDI_LINK_TRAIN_PATTERN_2;
1136 I915_WRITE(fdi_rx_reg, temp);
1140 temp = I915_READ(fdi_rx_iir_reg);
1141 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1143 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1144 for (j = 0; j < tries; j++) {
1145 temp = I915_READ(fdi_rx_iir_reg);
1146 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1147 if (temp & FDI_RX_SYMBOL_LOCK)
1152 I915_WRITE(fdi_rx_iir_reg,
1153 temp | FDI_RX_SYMBOL_LOCK);
1154 DRM_DEBUG("train 2 ok 1!\n");
1156 DRM_DEBUG("train 2 fail\n");
1158 I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1159 DRM_DEBUG("train 2 ok 2!\n");
1161 DRM_DEBUG("train done\n");
1163 /* set transcoder timing */
1164 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1165 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1166 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1168 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1169 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1170 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1172 /* enable PCH transcoder */
1173 temp = I915_READ(transconf_reg);
1174 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1175 I915_READ(transconf_reg);
1177 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1182 temp = I915_READ(fdi_tx_reg);
1183 temp &= ~FDI_LINK_TRAIN_NONE;
1184 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1185 FDI_TX_ENHANCE_FRAME_ENABLE);
1186 I915_READ(fdi_tx_reg);
1188 temp = I915_READ(fdi_rx_reg);
1189 temp &= ~FDI_LINK_TRAIN_NONE;
1190 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1191 FDI_RX_ENHANCE_FRAME_ENABLE);
1192 I915_READ(fdi_rx_reg);
1194 /* wait one idle pattern time */
1197 intel_crtc_load_lut(crtc);
1200 case DRM_MODE_DPMS_OFF:
1201 DRM_DEBUG("crtc %d dpms off\n", pipe);
1203 /* Disable the VGA plane that we never use */
1204 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1206 /* Disable display plane */
1207 temp = I915_READ(dspcntr_reg);
1208 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1209 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1210 /* Flush the plane changes */
1211 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1212 I915_READ(dspbase_reg);
1215 /* disable cpu pipe, disable after all planes disabled */
1216 temp = I915_READ(pipeconf_reg);
1217 if ((temp & PIPEACONF_ENABLE) != 0) {
1218 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1219 I915_READ(pipeconf_reg);
1220 /* wait for cpu pipe off, pipe state */
1221 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1224 DRM_DEBUG("crtc %d is disabled\n", pipe);
1226 /* IGDNG-A : disable cpu panel fitter ? */
1227 temp = I915_READ(pf_ctl_reg);
1228 if ((temp & PF_ENABLE) != 0) {
1229 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1230 I915_READ(pf_ctl_reg);
1233 /* disable CPU FDI tx and PCH FDI rx */
1234 temp = I915_READ(fdi_tx_reg);
1235 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1236 I915_READ(fdi_tx_reg);
1238 temp = I915_READ(fdi_rx_reg);
1239 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1240 I915_READ(fdi_rx_reg);
1242 /* still set train pattern 1 */
1243 temp = I915_READ(fdi_tx_reg);
1244 temp &= ~FDI_LINK_TRAIN_NONE;
1245 temp |= FDI_LINK_TRAIN_PATTERN_1;
1246 I915_WRITE(fdi_tx_reg, temp);
1248 temp = I915_READ(fdi_rx_reg);
1249 temp &= ~FDI_LINK_TRAIN_NONE;
1250 temp |= FDI_LINK_TRAIN_PATTERN_1;
1251 I915_WRITE(fdi_rx_reg, temp);
1253 /* disable PCH transcoder */
1254 temp = I915_READ(transconf_reg);
1255 if ((temp & TRANS_ENABLE) != 0) {
1256 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1257 I915_READ(transconf_reg);
1258 /* wait for PCH transcoder off, transcoder state */
1259 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1263 /* disable PCH DPLL */
1264 temp = I915_READ(pch_dpll_reg);
1265 if ((temp & DPLL_VCO_ENABLE) != 0) {
1266 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1267 I915_READ(pch_dpll_reg);
1270 temp = I915_READ(fdi_rx_reg);
1271 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1272 temp &= ~FDI_SEL_PCDCLK;
1273 temp &= ~FDI_RX_PLL_ENABLE;
1274 I915_WRITE(fdi_rx_reg, temp);
1275 I915_READ(fdi_rx_reg);
1278 /* Wait for the clocks to turn off. */
1284 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1286 struct drm_device *dev = crtc->dev;
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1289 int pipe = intel_crtc->pipe;
1290 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1291 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1292 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1293 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1296 /* XXX: When our outputs are all unaware of DPMS modes other than off
1297 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1300 case DRM_MODE_DPMS_ON:
1301 case DRM_MODE_DPMS_STANDBY:
1302 case DRM_MODE_DPMS_SUSPEND:
1303 /* Enable the DPLL */
1304 temp = I915_READ(dpll_reg);
1305 if ((temp & DPLL_VCO_ENABLE) == 0) {
1306 I915_WRITE(dpll_reg, temp);
1307 I915_READ(dpll_reg);
1308 /* Wait for the clocks to stabilize. */
1310 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1311 I915_READ(dpll_reg);
1312 /* Wait for the clocks to stabilize. */
1314 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1315 I915_READ(dpll_reg);
1316 /* Wait for the clocks to stabilize. */
1320 /* Enable the pipe */
1321 temp = I915_READ(pipeconf_reg);
1322 if ((temp & PIPEACONF_ENABLE) == 0)
1323 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1325 /* Enable the plane */
1326 temp = I915_READ(dspcntr_reg);
1327 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1328 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1329 /* Flush the plane changes */
1330 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1333 intel_crtc_load_lut(crtc);
1335 /* Give the overlay scaler a chance to enable if it's on this pipe */
1336 //intel_crtc_dpms_video(crtc, true); TODO
1337 intel_update_watermarks(dev);
1339 case DRM_MODE_DPMS_OFF:
1340 intel_update_watermarks(dev);
1341 /* Give the overlay scaler a chance to disable if it's on this pipe */
1342 //intel_crtc_dpms_video(crtc, FALSE); TODO
1344 /* Disable the VGA plane that we never use */
1345 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1347 /* Disable display plane */
1348 temp = I915_READ(dspcntr_reg);
1349 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1350 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1351 /* Flush the plane changes */
1352 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1353 I915_READ(dspbase_reg);
1356 if (!IS_I9XX(dev)) {
1357 /* Wait for vblank for the disable to take effect */
1358 intel_wait_for_vblank(dev);
1361 /* Next, disable display pipes */
1362 temp = I915_READ(pipeconf_reg);
1363 if ((temp & PIPEACONF_ENABLE) != 0) {
1364 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1365 I915_READ(pipeconf_reg);
1368 /* Wait for vblank for the disable to take effect. */
1369 intel_wait_for_vblank(dev);
1371 temp = I915_READ(dpll_reg);
1372 if ((temp & DPLL_VCO_ENABLE) != 0) {
1373 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1374 I915_READ(dpll_reg);
1377 /* Wait for the clocks to turn off. */
1384 * Sets the power management mode of the pipe and plane.
1386 * This code should probably grow support for turning the cursor off and back
1387 * on appropriately at the same time as we're turning the pipe off/on.
1389 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1391 struct drm_device *dev = crtc->dev;
1392 struct drm_i915_master_private *master_priv;
1393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1394 int pipe = intel_crtc->pipe;
1398 igdng_crtc_dpms(crtc, mode);
1400 i9xx_crtc_dpms(crtc, mode);
1402 if (!dev->primary->master)
1405 master_priv = dev->primary->master->driver_priv;
1406 if (!master_priv->sarea_priv)
1409 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1413 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1414 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1417 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1418 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1421 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1425 intel_crtc->dpms_mode = mode;
1428 static void intel_crtc_prepare (struct drm_crtc *crtc)
1430 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1431 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1434 static void intel_crtc_commit (struct drm_crtc *crtc)
1436 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1437 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1440 void intel_encoder_prepare (struct drm_encoder *encoder)
1442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1443 /* lvds has its own version of prepare see intel_lvds_prepare */
1444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1447 void intel_encoder_commit (struct drm_encoder *encoder)
1449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1450 /* lvds has its own version of commit see intel_lvds_commit */
1451 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1454 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1455 struct drm_display_mode *mode,
1456 struct drm_display_mode *adjusted_mode)
1458 struct drm_device *dev = crtc->dev;
1459 if (IS_IGDNG(dev)) {
1460 /* FDI link clock is fixed at 2.7G */
1461 if (mode->clock * 3 > 27000 * 4)
1462 return MODE_CLOCK_HIGH;
1468 /** Returns the core display clock speed for i830 - i945 */
1469 static int intel_get_core_clock_speed(struct drm_device *dev)
1472 /* Core clock values taken from the published datasheets.
1473 * The 830 may go up to 166 Mhz, which we should check.
1477 else if (IS_I915G(dev))
1479 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1481 else if (IS_I915GM(dev)) {
1484 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1486 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1489 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1490 case GC_DISPLAY_CLOCK_333_MHZ:
1493 case GC_DISPLAY_CLOCK_190_200_MHZ:
1497 } else if (IS_I865G(dev))
1499 else if (IS_I855(dev)) {
1501 /* Assume that the hardware is in the high speed state. This
1502 * should be the default.
1504 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1505 case GC_CLOCK_133_200:
1506 case GC_CLOCK_100_200:
1508 case GC_CLOCK_166_250:
1510 case GC_CLOCK_100_133:
1513 } else /* 852, 830 */
1516 return 0; /* Silence gcc warning */
1520 * Return the pipe currently connected to the panel fitter,
1521 * or -1 if the panel fitter is not present or not in use
1523 static int intel_panel_fitter_pipe (struct drm_device *dev)
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1528 /* i830 doesn't have a panel fitter */
1532 pfit_control = I915_READ(PFIT_CONTROL);
1534 /* See if the panel fitter is in use */
1535 if ((pfit_control & PFIT_ENABLE) == 0)
1538 /* 965 can place panel fitter on either pipe */
1540 return (pfit_control >> 29) & 0x3;
1542 /* older chips can only use pipe 1 */
1555 fdi_reduce_ratio(u32 *num, u32 *den)
1557 while (*num > 0xffffff || *den > 0xffffff) {
1563 #define DATA_N 0x800000
1564 #define LINK_N 0x80000
1567 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1568 int pixel_clock, int link_clock,
1569 struct fdi_m_n *m_n)
1573 m_n->tu = 64; /* default size */
1575 temp = (u64) DATA_N * pixel_clock;
1576 temp = div_u64(temp, link_clock);
1577 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
1578 m_n->gmch_n = DATA_N;
1579 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1581 temp = (u64) LINK_N * pixel_clock;
1582 m_n->link_m = div_u64(temp, link_clock);
1583 m_n->link_n = LINK_N;
1584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1588 struct intel_watermark_params {
1589 unsigned long fifo_size;
1590 unsigned long max_wm;
1591 unsigned long default_wm;
1592 unsigned long guard_size;
1593 unsigned long cacheline_size;
1596 /* IGD has different values for various configs */
1597 static struct intel_watermark_params igd_display_wm = {
1604 static struct intel_watermark_params igd_display_hplloff_wm = {
1611 static struct intel_watermark_params igd_cursor_wm = {
1615 IGD_CURSOR_GUARD_WM,
1618 static struct intel_watermark_params igd_cursor_hplloff_wm = {
1622 IGD_CURSOR_GUARD_WM,
1625 static struct intel_watermark_params i945_wm_info = {
1626 I915_FIFO_LINE_SIZE,
1632 static struct intel_watermark_params i915_wm_info = {
1639 static struct intel_watermark_params i855_wm_info = {
1646 static struct intel_watermark_params i830_wm_info = {
1654 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1655 struct intel_watermark_params *wm,
1657 unsigned long latency_ns)
1659 unsigned long bytes_required, wm_size;
1661 bytes_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1662 bytes_required /= wm->cacheline_size;
1663 wm_size = wm->fifo_size - bytes_required - wm->guard_size;
1665 if (wm_size > wm->max_wm)
1666 wm_size = wm->max_wm;
1668 wm_size = wm->default_wm;
1672 struct cxsr_latency {
1674 unsigned long fsb_freq;
1675 unsigned long mem_freq;
1676 unsigned long display_sr;
1677 unsigned long display_hpll_disable;
1678 unsigned long cursor_sr;
1679 unsigned long cursor_hpll_disable;
1682 static struct cxsr_latency cxsr_latency_table[] = {
1683 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1684 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1685 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1687 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1688 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1689 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1691 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1692 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1693 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1695 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1696 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1697 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1699 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1700 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1701 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1703 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1704 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1705 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1708 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1712 struct cxsr_latency *latency;
1714 if (fsb == 0 || mem == 0)
1717 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1718 latency = &cxsr_latency_table[i];
1719 if (is_desktop == latency->is_desktop &&
1720 fsb == latency->fsb_freq && mem == latency->mem_freq)
1723 if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1724 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1730 static void igd_disable_cxsr(struct drm_device *dev)
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1735 /* deactivate cxsr */
1736 reg = I915_READ(DSPFW3);
1737 reg &= ~(IGD_SELF_REFRESH_EN);
1738 I915_WRITE(DSPFW3, reg);
1739 DRM_INFO("Big FIFO is disabled\n");
1742 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1745 struct drm_i915_private *dev_priv = dev->dev_private;
1748 struct cxsr_latency *latency;
1750 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1751 dev_priv->mem_freq);
1753 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1754 igd_disable_cxsr(dev);
1759 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1760 latency->display_sr);
1761 reg = I915_READ(DSPFW1);
1764 I915_WRITE(DSPFW1, reg);
1765 DRM_DEBUG("DSPFW1 register is %x\n", reg);
1768 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1769 latency->cursor_sr);
1770 reg = I915_READ(DSPFW3);
1771 reg &= ~(0x3f << 24);
1772 reg |= (wm & 0x3f) << 24;
1773 I915_WRITE(DSPFW3, reg);
1775 /* Display HPLL off SR */
1776 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1777 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1778 reg = I915_READ(DSPFW3);
1781 I915_WRITE(DSPFW3, reg);
1783 /* cursor HPLL off SR */
1784 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1785 latency->cursor_hpll_disable);
1786 reg = I915_READ(DSPFW3);
1787 reg &= ~(0x3f << 16);
1788 reg |= (wm & 0x3f) << 16;
1789 I915_WRITE(DSPFW3, reg);
1790 DRM_DEBUG("DSPFW3 register is %x\n", reg);
1793 reg = I915_READ(DSPFW3);
1794 reg |= IGD_SELF_REFRESH_EN;
1795 I915_WRITE(DSPFW3, reg);
1797 DRM_INFO("Big FIFO is enabled\n");
1802 const static int latency_ns = 5000; /* default for non-igd platforms */
1805 static void i965_update_wm(struct drm_device *dev)
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1809 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
1811 /* 965 has limitations... */
1812 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
1813 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1816 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1817 int planeb_clock, int sr_hdisplay, int pixel_size)
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1821 uint32_t fwater_hi = I915_READ(FW_BLC2) & LM_FIFO_WATERMARK;
1822 int bsize, asize, cwm, bwm = 1, awm = 1, srwm = 1;
1823 uint32_t dsparb = I915_READ(DSPARB);
1824 int planea_entries, planeb_entries;
1825 struct intel_watermark_params *wm_params;
1826 unsigned long line_time_us;
1827 int sr_clock, sr_entries = 0;
1829 if (IS_I965GM(dev) || IS_I945GM(dev))
1830 wm_params = &i945_wm_info;
1831 else if (IS_I9XX(dev))
1832 wm_params = &i915_wm_info;
1834 wm_params = &i855_wm_info;
1836 planea_entries = intel_calculate_wm(planea_clock, wm_params,
1837 pixel_size, latency_ns);
1838 planeb_entries = intel_calculate_wm(planeb_clock, wm_params,
1839 pixel_size, latency_ns);
1841 DRM_DEBUG("FIFO entries - A: %d, B: %d\n", planea_entries,
1845 asize = dsparb & 0x7f;
1846 bsize = (dsparb >> DSPARB_CSTART_SHIFT) & 0x7f;
1848 asize = dsparb & 0x1ff;
1849 bsize = (dsparb >> DSPARB_BEND_SHIFT) & 0x1ff;
1851 DRM_DEBUG("FIFO size - A: %d, B: %d\n", asize, bsize);
1853 /* Two extra entries for padding */
1854 awm = asize - (planea_entries + 2);
1855 bwm = bsize - (planeb_entries + 2);
1857 /* Sanity check against potentially bad FIFO allocations */
1859 /* pipe is on but has too few FIFO entries */
1860 if (planea_entries != 0)
1861 DRM_DEBUG("plane A needs more FIFO entries\n");
1865 if (planeb_entries != 0)
1866 DRM_DEBUG("plane B needs more FIFO entries\n");
1871 * Overlay gets an aggressive default since video jitter is bad.
1875 /* Calc sr entries for one pipe configs */
1876 if (!planea_clock || !planeb_clock) {
1877 sr_clock = planea_clock ? planea_clock : planeb_clock;
1878 line_time_us = (sr_hdisplay * 1000) / sr_clock;
1879 sr_entries = (((latency_ns / line_time_us) + 1) * pixel_size *
1880 sr_hdisplay) / 1000;
1881 sr_entries = roundup(sr_entries / wm_params->cacheline_size, 1);
1882 if (sr_entries < wm_params->fifo_size)
1883 srwm = wm_params->fifo_size - sr_entries;
1886 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1887 awm, bwm, cwm, srwm);
1889 fwater_lo = fwater_lo | ((bwm & 0x3f) << 16) | (awm & 0x3f);
1890 fwater_hi = fwater_hi | (cwm & 0x1f);
1892 I915_WRITE(FW_BLC, fwater_lo);
1893 I915_WRITE(FW_BLC2, fwater_hi);
1895 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
1898 static void i830_update_wm(struct drm_device *dev, int planea_clock,
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 uint32_t dsparb = I915_READ(DSPARB);
1903 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1904 unsigned int asize, awm;
1907 planea_entries = intel_calculate_wm(planea_clock, &i830_wm_info,
1908 pixel_size, latency_ns);
1910 asize = dsparb & 0x7f;
1912 awm = asize - planea_entries;
1914 fwater_lo = fwater_lo | awm;
1916 I915_WRITE(FW_BLC, fwater_lo);
1920 * intel_update_watermarks - update FIFO watermark values based on current modes
1922 * Calculate watermark values for the various WM regs based on current mode
1923 * and plane configuration.
1925 * There are several cases to deal with here:
1926 * - normal (i.e. non-self-refresh)
1927 * - self-refresh (SR) mode
1928 * - lines are large relative to FIFO size (buffer can hold up to 2)
1929 * - lines are small relative to FIFO size (buffer can hold more than 2
1930 * lines), so need to account for TLB latency
1932 * The normal calculation is:
1933 * watermark = dotclock * bytes per pixel * latency
1934 * where latency is platform & configuration dependent (we assume pessimal
1937 * The SR calculation is:
1938 * watermark = (trunc(latency/line time)+1) * surface width *
1941 * line time = htotal / dotclock
1942 * and latency is assumed to be high, as above.
1944 * The final value programmed to the register should always be rounded up,
1945 * and include an extra 2 entries to account for clock crossings.
1947 * We don't use the sprite, so we can ignore that. And on Crestline we have
1948 * to set the non-SR watermarks to 8.
1950 static void intel_update_watermarks(struct drm_device *dev)
1952 struct drm_crtc *crtc;
1953 struct intel_crtc *intel_crtc;
1954 int sr_hdisplay = 0;
1955 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
1956 int enabled = 0, pixel_size = 0;
1958 if (DSPARB_HWCONTROL(dev))
1961 /* Get the clock config from both planes */
1962 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1963 intel_crtc = to_intel_crtc(crtc);
1964 if (crtc->enabled) {
1966 if (intel_crtc->plane == 0) {
1967 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
1968 intel_crtc->pipe, crtc->mode.clock);
1969 planea_clock = crtc->mode.clock;
1971 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
1972 intel_crtc->pipe, crtc->mode.clock);
1973 planeb_clock = crtc->mode.clock;
1975 sr_hdisplay = crtc->mode.hdisplay;
1976 sr_clock = crtc->mode.clock;
1978 pixel_size = crtc->fb->bits_per_pixel / 8;
1980 pixel_size = 4; /* by default */
1987 /* Single pipe configs can enable self refresh */
1988 if (enabled == 1 && IS_IGD(dev))
1989 igd_enable_cxsr(dev, sr_clock, pixel_size);
1990 else if (IS_IGD(dev))
1991 igd_disable_cxsr(dev);
1994 i965_update_wm(dev);
1995 else if (IS_I9XX(dev) || IS_MOBILE(dev))
1996 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
1999 i830_update_wm(dev, planea_clock, pixel_size);
2002 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2003 struct drm_display_mode *mode,
2004 struct drm_display_mode *adjusted_mode,
2006 struct drm_framebuffer *old_fb)
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2011 int pipe = intel_crtc->pipe;
2012 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2013 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2014 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2015 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2016 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2017 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2018 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2019 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2020 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2021 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2022 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2023 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2024 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2025 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2026 int refclk, num_outputs = 0;
2027 intel_clock_t clock;
2028 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2029 bool ok, is_sdvo = false, is_dvo = false;
2030 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2031 struct drm_mode_config *mode_config = &dev->mode_config;
2032 struct drm_connector *connector;
2033 const intel_limit_t *limit;
2035 struct fdi_m_n m_n = {0};
2036 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2037 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2038 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2039 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2040 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2041 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2042 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2043 int lvds_reg = LVDS;
2045 int sdvo_pixel_multiply;
2047 drm_vblank_pre_modeset(dev, pipe);
2049 list_for_each_entry(connector, &mode_config->connector_list, head) {
2050 struct intel_output *intel_output = to_intel_output(connector);
2052 if (!connector->encoder || connector->encoder->crtc != crtc)
2055 switch (intel_output->type) {
2056 case INTEL_OUTPUT_LVDS:
2059 case INTEL_OUTPUT_SDVO:
2060 case INTEL_OUTPUT_HDMI:
2062 if (intel_output->needs_tv_clock)
2065 case INTEL_OUTPUT_DVO:
2068 case INTEL_OUTPUT_TVOUT:
2071 case INTEL_OUTPUT_ANALOG:
2074 case INTEL_OUTPUT_DISPLAYPORT:
2082 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2083 refclk = dev_priv->lvds_ssc_freq * 1000;
2084 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2085 } else if (IS_I9XX(dev)) {
2088 refclk = 120000; /* 120Mhz refclk */
2095 * Returns a set of divisors for the desired target clock with the given
2096 * refclk, or FALSE. The returned values represent the clock equation:
2097 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2099 limit = intel_limit(crtc);
2100 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2102 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2103 drm_vblank_post_modeset(dev, pipe);
2107 /* SDVO TV has fixed PLL values depend on its clock range,
2108 this mirrors vbios setting. */
2109 if (is_sdvo && is_tv) {
2110 if (adjusted_mode->clock >= 100000
2111 && adjusted_mode->clock < 140500) {
2117 } else if (adjusted_mode->clock >= 140500
2118 && adjusted_mode->clock <= 200000) {
2129 igdng_compute_m_n(3, 4, /* lane num 4 */
2130 adjusted_mode->clock,
2131 270000, /* lane clock */
2135 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2137 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2140 dpll = DPLL_VGA_MODE_DIS;
2144 dpll |= DPLLB_MODE_LVDS;
2146 dpll |= DPLLB_MODE_DAC_SERIAL;
2148 dpll |= DPLL_DVO_HIGH_SPEED;
2149 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2150 if (IS_I945G(dev) || IS_I945GM(dev))
2151 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2152 else if (IS_IGDNG(dev))
2153 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2156 dpll |= DPLL_DVO_HIGH_SPEED;
2158 /* compute bitmask from p1 value */
2160 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2162 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2165 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2181 if (IS_I965G(dev) && !IS_IGDNG(dev))
2182 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2185 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2188 dpll |= PLL_P1_DIVIDE_BY_TWO;
2190 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2192 dpll |= PLL_P2_DIVIDE_BY_4;
2196 if (is_sdvo && is_tv)
2197 dpll |= PLL_REF_INPUT_TVCLKINBC;
2199 /* XXX: just matching BIOS for now */
2200 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2202 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2203 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2205 dpll |= PLL_REF_INPUT_DREFCLK;
2207 /* setup pipeconf */
2208 pipeconf = I915_READ(pipeconf_reg);
2210 /* Set up the display plane register */
2211 dspcntr = DISPPLANE_GAMMA_ENABLE;
2213 /* IGDNG's plane is forced to pipe, bit 24 is to
2214 enable color space conversion */
2215 if (!IS_IGDNG(dev)) {
2217 dspcntr |= DISPPLANE_SEL_PIPE_A;
2219 dspcntr |= DISPPLANE_SEL_PIPE_B;
2222 if (pipe == 0 && !IS_I965G(dev)) {
2223 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2226 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2229 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2230 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2232 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2235 dspcntr |= DISPLAY_PLANE_ENABLE;
2236 pipeconf |= PIPEACONF_ENABLE;
2237 dpll |= DPLL_VCO_ENABLE;
2240 /* Disable the panel fitter if it was on our pipe */
2241 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2242 I915_WRITE(PFIT_CONTROL, 0);
2244 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2245 drm_mode_debug_printmodeline(mode);
2247 /* assign to IGDNG registers */
2248 if (IS_IGDNG(dev)) {
2249 fp_reg = pch_fp_reg;
2250 dpll_reg = pch_dpll_reg;
2253 if (dpll & DPLL_VCO_ENABLE) {
2254 I915_WRITE(fp_reg, fp);
2255 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2256 I915_READ(dpll_reg);
2260 if (IS_IGDNG(dev)) {
2261 /* enable PCH clock reference source */
2262 /* XXX need to change the setting for other outputs */
2264 temp = I915_READ(PCH_DREF_CONTROL);
2265 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2266 temp |= DREF_NONSPREAD_CK505_ENABLE;
2267 temp &= ~DREF_SSC_SOURCE_MASK;
2268 temp |= DREF_SSC_SOURCE_ENABLE;
2269 temp &= ~DREF_SSC1_ENABLE;
2270 /* if no eDP, disable source output to CPU */
2271 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2272 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2273 I915_WRITE(PCH_DREF_CONTROL, temp);
2276 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2277 * This is an exception to the general rule that mode_set doesn't turn
2284 lvds_reg = PCH_LVDS;
2286 lvds = I915_READ(lvds_reg);
2287 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2288 /* Set the B0-B3 data pairs corresponding to whether we're going to
2289 * set the DPLLs for dual-channel mode or not.
2292 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2294 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2296 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2297 * appropriately here, but we need to look more thoroughly into how
2298 * panels behave in the two modes.
2301 I915_WRITE(lvds_reg, lvds);
2302 I915_READ(lvds_reg);
2305 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2307 I915_WRITE(fp_reg, fp);
2308 I915_WRITE(dpll_reg, dpll);
2309 I915_READ(dpll_reg);
2310 /* Wait for the clocks to stabilize. */
2313 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2314 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2315 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2316 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2318 /* write it again -- the BIOS does, after all */
2319 I915_WRITE(dpll_reg, dpll);
2321 I915_READ(dpll_reg);
2322 /* Wait for the clocks to stabilize. */
2325 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2326 ((adjusted_mode->crtc_htotal - 1) << 16));
2327 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2328 ((adjusted_mode->crtc_hblank_end - 1) << 16));
2329 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2330 ((adjusted_mode->crtc_hsync_end - 1) << 16));
2331 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2332 ((adjusted_mode->crtc_vtotal - 1) << 16));
2333 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2334 ((adjusted_mode->crtc_vblank_end - 1) << 16));
2335 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2336 ((adjusted_mode->crtc_vsync_end - 1) << 16));
2337 /* pipesrc and dspsize control the size that is scaled from, which should
2338 * always be the user's requested size.
2340 if (!IS_IGDNG(dev)) {
2341 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2342 (mode->hdisplay - 1));
2343 I915_WRITE(dsppos_reg, 0);
2345 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2347 if (IS_IGDNG(dev)) {
2348 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2349 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2350 I915_WRITE(link_m1_reg, m_n.link_m);
2351 I915_WRITE(link_n1_reg, m_n.link_n);
2353 /* enable FDI RX PLL too */
2354 temp = I915_READ(fdi_rx_reg);
2355 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2359 I915_WRITE(pipeconf_reg, pipeconf);
2360 I915_READ(pipeconf_reg);
2362 intel_wait_for_vblank(dev);
2364 I915_WRITE(dspcntr_reg, dspcntr);
2366 /* Flush the plane changes */
2367 ret = intel_pipe_set_base(crtc, x, y, old_fb);
2369 intel_update_watermarks(dev);
2371 drm_vblank_post_modeset(dev, pipe);
2376 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2377 void intel_crtc_load_lut(struct drm_crtc *crtc)
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2385 /* The clocks have to be on to load the palette. */
2389 /* use legacy palette for IGDNG */
2391 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2394 for (i = 0; i < 256; i++) {
2395 I915_WRITE(palreg + 4 * i,
2396 (intel_crtc->lut_r[i] << 16) |
2397 (intel_crtc->lut_g[i] << 8) |
2398 intel_crtc->lut_b[i]);
2402 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2403 struct drm_file *file_priv,
2405 uint32_t width, uint32_t height)
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 struct drm_gem_object *bo;
2411 struct drm_i915_gem_object *obj_priv;
2412 int pipe = intel_crtc->pipe;
2413 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2414 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2415 uint32_t temp = I915_READ(control);
2421 /* if we want to turn off the cursor ignore width and height */
2423 DRM_DEBUG("cursor off\n");
2424 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2425 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2426 temp |= CURSOR_MODE_DISABLE;
2428 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2432 mutex_lock(&dev->struct_mutex);
2436 /* Currently we only support 64x64 cursors */
2437 if (width != 64 || height != 64) {
2438 DRM_ERROR("we currently only support 64x64 cursors\n");
2442 bo = drm_gem_object_lookup(dev, file_priv, handle);
2446 obj_priv = bo->driver_private;
2448 if (bo->size < width * height * 4) {
2449 DRM_ERROR("buffer is to small\n");
2454 /* we only need to pin inside GTT if cursor is non-phy */
2455 mutex_lock(&dev->struct_mutex);
2456 if (!dev_priv->cursor_needs_physical) {
2457 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2459 DRM_ERROR("failed to pin cursor bo\n");
2462 addr = obj_priv->gtt_offset;
2464 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2466 DRM_ERROR("failed to attach phys object\n");
2469 addr = obj_priv->phys_obj->handle->busaddr;
2473 I915_WRITE(CURSIZE, (height << 12) | width);
2475 /* Hooray for CUR*CNTR differences */
2476 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2477 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2478 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2479 temp |= (pipe << 28); /* Connect to correct pipe */
2481 temp &= ~(CURSOR_FORMAT_MASK);
2482 temp |= CURSOR_ENABLE;
2483 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2487 I915_WRITE(control, temp);
2488 I915_WRITE(base, addr);
2490 if (intel_crtc->cursor_bo) {
2491 if (dev_priv->cursor_needs_physical) {
2492 if (intel_crtc->cursor_bo != bo)
2493 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2495 i915_gem_object_unpin(intel_crtc->cursor_bo);
2496 drm_gem_object_unreference(intel_crtc->cursor_bo);
2498 mutex_unlock(&dev->struct_mutex);
2500 intel_crtc->cursor_addr = addr;
2501 intel_crtc->cursor_bo = bo;
2505 mutex_lock(&dev->struct_mutex);
2507 drm_gem_object_unreference(bo);
2508 mutex_unlock(&dev->struct_mutex);
2512 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 int pipe = intel_crtc->pipe;
2522 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2526 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2530 temp |= x << CURSOR_X_SHIFT;
2531 temp |= y << CURSOR_Y_SHIFT;
2533 adder = intel_crtc->cursor_addr;
2534 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2535 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2540 /** Sets the color ramps on behalf of RandR */
2541 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2542 u16 blue, int regno)
2544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546 intel_crtc->lut_r[regno] = red >> 8;
2547 intel_crtc->lut_g[regno] = green >> 8;
2548 intel_crtc->lut_b[regno] = blue >> 8;
2551 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2552 u16 *blue, uint32_t size)
2554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560 for (i = 0; i < 256; i++) {
2561 intel_crtc->lut_r[i] = red[i] >> 8;
2562 intel_crtc->lut_g[i] = green[i] >> 8;
2563 intel_crtc->lut_b[i] = blue[i] >> 8;
2566 intel_crtc_load_lut(crtc);
2570 * Get a pipe with a simple mode set on it for doing load-based monitor
2573 * It will be up to the load-detect code to adjust the pipe as appropriate for
2574 * its requirements. The pipe will be connected to no other outputs.
2576 * Currently this code will only succeed if there is a pipe with no outputs
2577 * configured for it. In the future, it could choose to temporarily disable
2578 * some outputs to free up a pipe for its use.
2580 * \return crtc, or NULL if no pipes are available.
2583 /* VESA 640x480x72Hz mode to set on the pipe */
2584 static struct drm_display_mode load_detect_mode = {
2585 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2586 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2589 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2590 struct drm_display_mode *mode,
2593 struct intel_crtc *intel_crtc;
2594 struct drm_crtc *possible_crtc;
2595 struct drm_crtc *supported_crtc =NULL;
2596 struct drm_encoder *encoder = &intel_output->enc;
2597 struct drm_crtc *crtc = NULL;
2598 struct drm_device *dev = encoder->dev;
2599 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2600 struct drm_crtc_helper_funcs *crtc_funcs;
2604 * Algorithm gets a little messy:
2605 * - if the connector already has an assigned crtc, use it (but make
2606 * sure it's on first)
2607 * - try to find the first unused crtc that can drive this connector,
2608 * and use that if we find one
2609 * - if there are no unused crtcs available, try to use the first
2610 * one we found that supports the connector
2613 /* See if we already have a CRTC for this connector */
2614 if (encoder->crtc) {
2615 crtc = encoder->crtc;
2616 /* Make sure the crtc and connector are running */
2617 intel_crtc = to_intel_crtc(crtc);
2618 *dpms_mode = intel_crtc->dpms_mode;
2619 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2620 crtc_funcs = crtc->helper_private;
2621 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2622 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2627 /* Find an unused one (if possible) */
2628 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2630 if (!(encoder->possible_crtcs & (1 << i)))
2632 if (!possible_crtc->enabled) {
2633 crtc = possible_crtc;
2636 if (!supported_crtc)
2637 supported_crtc = possible_crtc;
2641 * If we didn't find an unused CRTC, don't use any.
2647 encoder->crtc = crtc;
2648 intel_output->base.encoder = encoder;
2649 intel_output->load_detect_temp = true;
2651 intel_crtc = to_intel_crtc(crtc);
2652 *dpms_mode = intel_crtc->dpms_mode;
2654 if (!crtc->enabled) {
2656 mode = &load_detect_mode;
2657 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2659 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2660 crtc_funcs = crtc->helper_private;
2661 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2664 /* Add this connector to the crtc */
2665 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2666 encoder_funcs->commit(encoder);
2668 /* let the connector get through one full cycle before testing */
2669 intel_wait_for_vblank(dev);
2674 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2676 struct drm_encoder *encoder = &intel_output->enc;
2677 struct drm_device *dev = encoder->dev;
2678 struct drm_crtc *crtc = encoder->crtc;
2679 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2680 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2682 if (intel_output->load_detect_temp) {
2683 encoder->crtc = NULL;
2684 intel_output->base.encoder = NULL;
2685 intel_output->load_detect_temp = false;
2686 crtc->enabled = drm_helper_crtc_in_use(crtc);
2687 drm_helper_disable_unused_functions(dev);
2690 /* Switch crtc and output back off if necessary */
2691 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2692 if (encoder->crtc == crtc)
2693 encoder_funcs->dpms(encoder, dpms_mode);
2694 crtc_funcs->dpms(crtc, dpms_mode);
2698 /* Returns the clock of the currently programmed mode of the given pipe. */
2699 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 int pipe = intel_crtc->pipe;
2704 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2706 intel_clock_t clock;
2708 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2709 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2711 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2713 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2715 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2716 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2718 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2719 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2724 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2725 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2727 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2728 DPLL_FPA01_P1_POST_DIV_SHIFT);
2730 switch (dpll & DPLL_MODE_MASK) {
2731 case DPLLB_MODE_DAC_SERIAL:
2732 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2735 case DPLLB_MODE_LVDS:
2736 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2740 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2741 "mode\n", (int)(dpll & DPLL_MODE_MASK));
2745 /* XXX: Handle the 100Mhz refclk */
2746 intel_clock(dev, 96000, &clock);
2748 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2751 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2752 DPLL_FPA01_P1_POST_DIV_SHIFT);
2755 if ((dpll & PLL_REF_INPUT_MASK) ==
2756 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2757 /* XXX: might not be 66MHz */
2758 intel_clock(dev, 66000, &clock);
2760 intel_clock(dev, 48000, &clock);
2762 if (dpll & PLL_P1_DIVIDE_BY_TWO)
2765 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2766 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2768 if (dpll & PLL_P2_DIVIDE_BY_4)
2773 intel_clock(dev, 48000, &clock);
2777 /* XXX: It would be nice to validate the clocks, but we can't reuse
2778 * i830PllIsValid() because it relies on the xf86_config connector
2779 * configuration being accurate, which it isn't necessarily.
2785 /** Returns the currently programmed mode of the given pipe. */
2786 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2787 struct drm_crtc *crtc)
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2791 int pipe = intel_crtc->pipe;
2792 struct drm_display_mode *mode;
2793 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2794 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2795 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2796 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2798 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2802 mode->clock = intel_crtc_clock_get(dev, crtc);
2803 mode->hdisplay = (htot & 0xffff) + 1;
2804 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2805 mode->hsync_start = (hsync & 0xffff) + 1;
2806 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2807 mode->vdisplay = (vtot & 0xffff) + 1;
2808 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2809 mode->vsync_start = (vsync & 0xffff) + 1;
2810 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2812 drm_mode_set_name(mode);
2813 drm_mode_set_crtcinfo(mode, 0);
2818 static void intel_crtc_destroy(struct drm_crtc *crtc)
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2822 if (intel_crtc->mode_set.mode)
2823 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2824 drm_crtc_cleanup(crtc);
2828 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2829 .dpms = intel_crtc_dpms,
2830 .mode_fixup = intel_crtc_mode_fixup,
2831 .mode_set = intel_crtc_mode_set,
2832 .mode_set_base = intel_pipe_set_base,
2833 .prepare = intel_crtc_prepare,
2834 .commit = intel_crtc_commit,
2837 static const struct drm_crtc_funcs intel_crtc_funcs = {
2838 .cursor_set = intel_crtc_cursor_set,
2839 .cursor_move = intel_crtc_cursor_move,
2840 .gamma_set = intel_crtc_gamma_set,
2841 .set_config = drm_crtc_helper_set_config,
2842 .destroy = intel_crtc_destroy,
2846 static void intel_crtc_init(struct drm_device *dev, int pipe)
2848 struct intel_crtc *intel_crtc;
2851 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2852 if (intel_crtc == NULL)
2855 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2857 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2858 intel_crtc->pipe = pipe;
2859 intel_crtc->plane = pipe;
2860 for (i = 0; i < 256; i++) {
2861 intel_crtc->lut_r[i] = i;
2862 intel_crtc->lut_g[i] = i;
2863 intel_crtc->lut_b[i] = i;
2866 intel_crtc->cursor_addr = 0;
2867 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2868 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2870 intel_crtc->mode_set.crtc = &intel_crtc->base;
2871 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2872 intel_crtc->mode_set.num_connectors = 0;
2874 if (i915_fbpercrtc) {
2881 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv)
2884 drm_i915_private_t *dev_priv = dev->dev_private;
2885 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2886 struct drm_crtc *crtc = NULL;
2890 DRM_ERROR("called with no initialization\n");
2894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2896 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2897 pipe = intel_crtc->pipe;
2903 DRM_ERROR("no such CRTC id\n");
2907 pipe_from_crtc_id->pipe = pipe;
2912 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2914 struct drm_crtc *crtc = NULL;
2916 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2918 if (intel_crtc->pipe == pipe)
2924 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2927 struct drm_connector *connector;
2930 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2931 struct intel_output *intel_output = to_intel_output(connector);
2932 if (type_mask & (1 << intel_output->type))
2933 index_mask |= (1 << entry);
2940 static void intel_setup_outputs(struct drm_device *dev)
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct drm_connector *connector;
2945 intel_crt_init(dev);
2947 /* Set up integrated LVDS */
2948 if (IS_MOBILE(dev) && !IS_I830(dev))
2949 intel_lvds_init(dev);
2951 if (IS_IGDNG(dev)) {
2954 if (I915_READ(HDMIB) & PORT_DETECTED) {
2956 /* found = intel_sdvo_init(dev, HDMIB); */
2959 intel_hdmi_init(dev, HDMIB);
2962 if (I915_READ(HDMIC) & PORT_DETECTED)
2963 intel_hdmi_init(dev, HDMIC);
2965 if (I915_READ(HDMID) & PORT_DETECTED)
2966 intel_hdmi_init(dev, HDMID);
2968 } else if (IS_I9XX(dev)) {
2972 if (I915_READ(SDVOB) & SDVO_DETECTED) {
2973 found = intel_sdvo_init(dev, SDVOB);
2974 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2975 intel_hdmi_init(dev, SDVOB);
2976 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2977 intel_dp_init(dev, DP_B);
2980 /* Before G4X SDVOC doesn't have its own detect register */
2986 if (I915_READ(reg) & SDVO_DETECTED) {
2987 found = intel_sdvo_init(dev, SDVOC);
2988 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
2989 intel_hdmi_init(dev, SDVOC);
2990 if (!found && SUPPORTS_INTEGRATED_DP(dev))
2991 intel_dp_init(dev, DP_C);
2993 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
2994 intel_dp_init(dev, DP_D);
2996 intel_dvo_init(dev);
2998 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3001 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3002 struct intel_output *intel_output = to_intel_output(connector);
3003 struct drm_encoder *encoder = &intel_output->enc;
3004 int crtc_mask = 0, clone_mask = 0;
3007 switch(intel_output->type) {
3008 case INTEL_OUTPUT_HDMI:
3009 crtc_mask = ((1 << 0)|
3011 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3013 case INTEL_OUTPUT_DVO:
3014 case INTEL_OUTPUT_SDVO:
3015 crtc_mask = ((1 << 0)|
3017 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3018 (1 << INTEL_OUTPUT_DVO) |
3019 (1 << INTEL_OUTPUT_SDVO));
3021 case INTEL_OUTPUT_ANALOG:
3022 crtc_mask = ((1 << 0)|
3024 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3025 (1 << INTEL_OUTPUT_DVO) |
3026 (1 << INTEL_OUTPUT_SDVO));
3028 case INTEL_OUTPUT_LVDS:
3029 crtc_mask = (1 << 1);
3030 clone_mask = (1 << INTEL_OUTPUT_LVDS);
3032 case INTEL_OUTPUT_TVOUT:
3033 crtc_mask = ((1 << 0) |
3035 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3037 case INTEL_OUTPUT_DISPLAYPORT:
3038 crtc_mask = ((1 << 0) |
3040 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3043 encoder->possible_crtcs = crtc_mask;
3044 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3048 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3050 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3051 struct drm_device *dev = fb->dev;
3054 intelfb_remove(dev, fb);
3056 drm_framebuffer_cleanup(fb);
3057 mutex_lock(&dev->struct_mutex);
3058 drm_gem_object_unreference(intel_fb->obj);
3059 mutex_unlock(&dev->struct_mutex);
3064 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3065 struct drm_file *file_priv,
3066 unsigned int *handle)
3068 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3069 struct drm_gem_object *object = intel_fb->obj;
3071 return drm_gem_handle_create(file_priv, object, handle);
3074 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3075 .destroy = intel_user_framebuffer_destroy,
3076 .create_handle = intel_user_framebuffer_create_handle,
3079 int intel_framebuffer_create(struct drm_device *dev,
3080 struct drm_mode_fb_cmd *mode_cmd,
3081 struct drm_framebuffer **fb,
3082 struct drm_gem_object *obj)
3084 struct intel_framebuffer *intel_fb;
3087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3091 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3093 DRM_ERROR("framebuffer init failed %d\n", ret);
3097 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3099 intel_fb->obj = obj;
3101 *fb = &intel_fb->base;
3107 static struct drm_framebuffer *
3108 intel_user_framebuffer_create(struct drm_device *dev,
3109 struct drm_file *filp,
3110 struct drm_mode_fb_cmd *mode_cmd)
3112 struct drm_gem_object *obj;
3113 struct drm_framebuffer *fb;
3116 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3120 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3122 mutex_lock(&dev->struct_mutex);
3123 drm_gem_object_unreference(obj);
3124 mutex_unlock(&dev->struct_mutex);
3131 static const struct drm_mode_config_funcs intel_mode_funcs = {
3132 .fb_create = intel_user_framebuffer_create,
3133 .fb_changed = intelfb_probe,
3136 void intel_modeset_init(struct drm_device *dev)
3141 drm_mode_config_init(dev);
3143 dev->mode_config.min_width = 0;
3144 dev->mode_config.min_height = 0;
3146 dev->mode_config.funcs = (void *)&intel_mode_funcs;
3148 if (IS_I965G(dev)) {
3149 dev->mode_config.max_width = 8192;
3150 dev->mode_config.max_height = 8192;
3152 dev->mode_config.max_width = 2048;
3153 dev->mode_config.max_height = 2048;
3156 /* set memory base */
3158 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3160 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3162 if (IS_MOBILE(dev) || IS_I9XX(dev))
3166 DRM_DEBUG("%d display pipe%s available.\n",
3167 num_pipe, num_pipe > 1 ? "s" : "");
3169 for (i = 0; i < num_pipe; i++) {
3170 intel_crtc_init(dev, i);
3173 intel_setup_outputs(dev);
3176 void intel_modeset_cleanup(struct drm_device *dev)
3178 drm_mode_config_cleanup(dev);
3182 /* current intel driver doesn't take advantage of encoders
3183 always give back the encoder for the connector
3185 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3187 struct intel_output *intel_output = to_intel_output(connector);
3189 return &intel_output->enc;