drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_rect.h>
  44 #include <linux/dma_remapping.h>
  45
  46 /* Primary plane formats supported by all gen */
  47 #define COMMON_PRIMARY_FORMATS \
  48         DRM_FORMAT_C8, \
  49         DRM_FORMAT_RGB565, \
  50         DRM_FORMAT_XRGB8888, \
  51         DRM_FORMAT_ARGB8888
  52
  53 /* Primary plane formats for gen <= 3 */
  54 static const uint32_t intel_primary_formats_gen2[] = {
  55         COMMON_PRIMARY_FORMATS,
  56         DRM_FORMAT_XRGB1555,
  57         DRM_FORMAT_ARGB1555,
  58 };
  59
  60 /* Primary plane formats for gen >= 4 */
  61 static const uint32_t intel_primary_formats_gen4[] = {
  62         COMMON_PRIMARY_FORMATS, \
  63         DRM_FORMAT_XBGR8888,
  64         DRM_FORMAT_ABGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_ARGB2101010,
  67         DRM_FORMAT_XBGR2101010,
  68         DRM_FORMAT_ABGR2101010,
  69 };
  70
  71 /* Cursor formats */
  72 static const uint32_t intel_cursor_formats[] = {
  73         DRM_FORMAT_ARGB8888,
  74 };
  75
  76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  77
  78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  79                                 struct intel_crtc_config *pipe_config);
  80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  81                                    struct intel_crtc_config *pipe_config);
  82
  83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  84                           int x, int y, struct drm_framebuffer *old_fb);
  85 static int intel_framebuffer_init(struct drm_device *dev,
  86                                   struct intel_framebuffer *ifb,
  87                                   struct drm_mode_fb_cmd2 *mode_cmd,
  88                                   struct drm_i915_gem_object *obj);
  89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  92                                          struct intel_link_m_n *m_n,
  93                                          struct intel_link_m_n *m2_n2);
  94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  97 static void vlv_prepare_pll(struct intel_crtc *crtc,
  98                             const struct intel_crtc_config *pipe_config);
  99 static void chv_prepare_pll(struct intel_crtc *crtc,
 100                             const struct intel_crtc_config *pipe_config);
 101
 102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 103 {
 104         if (!connector->mst_port)
 105                 return connector->encoder;
 106         else
 107                 return &connector->mst_port->mst_encoders[pipe]->base;
 108 }
 109
 110 typedef struct {
 111         int     min, max;
 112 } intel_range_t;
 113
 114 typedef struct {
 115         int     dot_limit;
 116         int     p2_slow, p2_fast;
 117 } intel_p2_t;
 118
 119 typedef struct intel_limit intel_limit_t;
 120 struct intel_limit {
 121         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 122         intel_p2_t          p2;
 123 };
 124
 125 int
 126 intel_pch_rawclk(struct drm_device *dev)
 127 {
 128         struct drm_i915_private *dev_priv = dev->dev_private;
 129
 130         WARN_ON(!HAS_PCH_SPLIT(dev));
 131
 132         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 133 }
 134
 135 static inline u32 /* units of 100MHz */
 136 intel_fdi_link_freq(struct drm_device *dev)
 137 {
 138         if (IS_GEN5(dev)) {
 139                 struct drm_i915_private *dev_priv = dev->dev_private;
 140                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 141         } else
 142                 return 27;
 143 }
 144
 145 static const intel_limit_t intel_limits_i8xx_dac = {
 146         .dot = { .min = 25000, .max = 350000 },
 147         .vco = { .min = 908000, .max = 1512000 },
 148         .n = { .min = 2, .max = 16 },
 149         .m = { .min = 96, .max = 140 },
 150         .m1 = { .min = 18, .max = 26 },
 151         .m2 = { .min = 6, .max = 16 },
 152         .p = { .min = 4, .max = 128 },
 153         .p1 = { .min = 2, .max = 33 },
 154         .p2 = { .dot_limit = 165000,
 155                 .p2_slow = 4, .p2_fast = 2 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i8xx_dvo = {
 159         .dot = { .min = 25000, .max = 350000 },
 160         .vco = { .min = 908000, .max = 1512000 },
 161         .n = { .min = 2, .max = 16 },
 162         .m = { .min = 96, .max = 140 },
 163         .m1 = { .min = 18, .max = 26 },
 164         .m2 = { .min = 6, .max = 16 },
 165         .p = { .min = 4, .max = 128 },
 166         .p1 = { .min = 2, .max = 33 },
 167         .p2 = { .dot_limit = 165000,
 168                 .p2_slow = 4, .p2_fast = 4 },
 169 };
 170
 171 static const intel_limit_t intel_limits_i8xx_lvds = {
 172         .dot = { .min = 25000, .max = 350000 },
 173         .vco = { .min = 908000, .max = 1512000 },
 174         .n = { .min = 2, .max = 16 },
 175         .m = { .min = 96, .max = 140 },
 176         .m1 = { .min = 18, .max = 26 },
 177         .m2 = { .min = 6, .max = 16 },
 178         .p = { .min = 4, .max = 128 },
 179         .p1 = { .min = 1, .max = 6 },
 180         .p2 = { .dot_limit = 165000,
 181                 .p2_slow = 14, .p2_fast = 7 },
 182 };
 183
 184 static const intel_limit_t intel_limits_i9xx_sdvo = {
 185         .dot = { .min = 20000, .max = 400000 },
 186         .vco = { .min = 1400000, .max = 2800000 },
 187         .n = { .min = 1, .max = 6 },
 188         .m = { .min = 70, .max = 120 },
 189         .m1 = { .min = 8, .max = 18 },
 190         .m2 = { .min = 3, .max = 7 },
 191         .p = { .min = 5, .max = 80 },
 192         .p1 = { .min = 1, .max = 8 },
 193         .p2 = { .dot_limit = 200000,
 194                 .p2_slow = 10, .p2_fast = 5 },
 195 };
 196
 197 static const intel_limit_t intel_limits_i9xx_lvds = {
 198         .dot = { .min = 20000, .max = 400000 },
 199         .vco = { .min = 1400000, .max = 2800000 },
 200         .n = { .min = 1, .max = 6 },
 201         .m = { .min = 70, .max = 120 },
 202         .m1 = { .min = 8, .max = 18 },
 203         .m2 = { .min = 3, .max = 7 },
 204         .p = { .min = 7, .max = 98 },
 205         .p1 = { .min = 1, .max = 8 },
 206         .p2 = { .dot_limit = 112000,
 207                 .p2_slow = 14, .p2_fast = 7 },
 208 };
 209
 210
 211 static const intel_limit_t intel_limits_g4x_sdvo = {
 212         .dot = { .min = 25000, .max = 270000 },
 213         .vco = { .min = 1750000, .max = 3500000},
 214         .n = { .min = 1, .max = 4 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 10, .max = 30 },
 219         .p1 = { .min = 1, .max = 3},
 220         .p2 = { .dot_limit = 270000,
 221                 .p2_slow = 10,
 222                 .p2_fast = 10
 223         },
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_hdmi = {
 227         .dot = { .min = 22000, .max = 400000 },
 228         .vco = { .min = 1750000, .max = 3500000},
 229         .n = { .min = 1, .max = 4 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 16, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 5, .max = 80 },
 234         .p1 = { .min = 1, .max = 8},
 235         .p2 = { .dot_limit = 165000,
 236                 .p2_slow = 10, .p2_fast = 5 },
 237 };
 238
 239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 240         .dot = { .min = 20000, .max = 115000 },
 241         .vco = { .min = 1750000, .max = 3500000 },
 242         .n = { .min = 1, .max = 3 },
 243         .m = { .min = 104, .max = 138 },
 244         .m1 = { .min = 17, .max = 23 },
 245         .m2 = { .min = 5, .max = 11 },
 246         .p = { .min = 28, .max = 112 },
 247         .p1 = { .min = 2, .max = 8 },
 248         .p2 = { .dot_limit = 0,
 249                 .p2_slow = 14, .p2_fast = 14
 250         },
 251 };
 252
 253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 254         .dot = { .min = 80000, .max = 224000 },
 255         .vco = { .min = 1750000, .max = 3500000 },
 256         .n = { .min = 1, .max = 3 },
 257         .m = { .min = 104, .max = 138 },
 258         .m1 = { .min = 17, .max = 23 },
 259         .m2 = { .min = 5, .max = 11 },
 260         .p = { .min = 14, .max = 42 },
 261         .p1 = { .min = 2, .max = 6 },
 262         .p2 = { .dot_limit = 0,
 263                 .p2_slow = 7, .p2_fast = 7
 264         },
 265 };
 266
 267 static const intel_limit_t intel_limits_pineview_sdvo = {
 268         .dot = { .min = 20000, .max = 400000},
 269         .vco = { .min = 1700000, .max = 3500000 },
 270         /* Pineview's Ncounter is a ring counter */
 271         .n = { .min = 3, .max = 6 },
 272         .m = { .min = 2, .max = 256 },
 273         /* Pineview only has one combined m divider, which we treat as m2. */
 274         .m1 = { .min = 0, .max = 0 },
 275         .m2 = { .min = 0, .max = 254 },
 276         .p = { .min = 5, .max = 80 },
 277         .p1 = { .min = 1, .max = 8 },
 278         .p2 = { .dot_limit = 200000,
 279                 .p2_slow = 10, .p2_fast = 5 },
 280 };
 281
 282 static const intel_limit_t intel_limits_pineview_lvds = {
 283         .dot = { .min = 20000, .max = 400000 },
 284         .vco = { .min = 1700000, .max = 3500000 },
 285         .n = { .min = 3, .max = 6 },
 286         .m = { .min = 2, .max = 256 },
 287         .m1 = { .min = 0, .max = 0 },
 288         .m2 = { .min = 0, .max = 254 },
 289         .p = { .min = 7, .max = 112 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 112000,
 292                 .p2_slow = 14, .p2_fast = 14 },
 293 };
 294
 295 /* Ironlake / Sandybridge
 296  *
 297  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 298  * the range value for them is (actual_value - 2).
 299  */
 300 static const intel_limit_t intel_limits_ironlake_dac = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 5 },
 304         .m = { .min = 79, .max = 127 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 5, .max = 80 },
 308         .p1 = { .min = 1, .max = 8 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 10, .p2_fast = 5 },
 311 };
 312
 313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 314         .dot = { .min = 25000, .max = 350000 },
 315         .vco = { .min = 1760000, .max = 3510000 },
 316         .n = { .min = 1, .max = 3 },
 317         .m = { .min = 79, .max = 118 },
 318         .m1 = { .min = 12, .max = 22 },
 319         .m2 = { .min = 5, .max = 9 },
 320         .p = { .min = 28, .max = 112 },
 321         .p1 = { .min = 2, .max = 8 },
 322         .p2 = { .dot_limit = 225000,
 323                 .p2_slow = 14, .p2_fast = 14 },
 324 };
 325
 326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 327         .dot = { .min = 25000, .max = 350000 },
 328         .vco = { .min = 1760000, .max = 3510000 },
 329         .n = { .min = 1, .max = 3 },
 330         .m = { .min = 79, .max = 127 },
 331         .m1 = { .min = 12, .max = 22 },
 332         .m2 = { .min = 5, .max = 9 },
 333         .p = { .min = 14, .max = 56 },
 334         .p1 = { .min = 2, .max = 8 },
 335         .p2 = { .dot_limit = 225000,
 336                 .p2_slow = 7, .p2_fast = 7 },
 337 };
 338
 339 /* LVDS 100mhz refclk limits. */
 340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 341         .dot = { .min = 25000, .max = 350000 },
 342         .vco = { .min = 1760000, .max = 3510000 },
 343         .n = { .min = 1, .max = 2 },
 344         .m = { .min = 79, .max = 126 },
 345         .m1 = { .min = 12, .max = 22 },
 346         .m2 = { .min = 5, .max = 9 },
 347         .p = { .min = 28, .max = 112 },
 348         .p1 = { .min = 2, .max = 8 },
 349         .p2 = { .dot_limit = 225000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000 },
 356         .n = { .min = 1, .max = 3 },
 357         .m = { .min = 79, .max = 126 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 14, .max = 42 },
 361         .p1 = { .min = 2, .max = 6 },
 362         .p2 = { .dot_limit = 225000,
 363                 .p2_slow = 7, .p2_fast = 7 },
 364 };
 365
 366 static const intel_limit_t intel_limits_vlv = {
 367          /*
 368           * These are the data rate limits (measured in fast clocks)
 369           * since those are the strictest limits we have. The fast
 370           * clock and actual rate limits are more relaxed, so checking
 371           * them would make no difference.
 372           */
 373         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 374         .vco = { .min = 4000000, .max = 6000000 },
 375         .n = { .min = 1, .max = 7 },
 376         .m1 = { .min = 2, .max = 3 },
 377         .m2 = { .min = 11, .max = 156 },
 378         .p1 = { .min = 2, .max = 3 },
 379         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 380 };
 381
 382 static const intel_limit_t intel_limits_chv = {
 383         /*
 384          * These are the data rate limits (measured in fast clocks)
 385          * since those are the strictest limits we have.  The fast
 386          * clock and actual rate limits are more relaxed, so checking
 387          * them would make no difference.
 388          */
 389         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 390         .vco = { .min = 4860000, .max = 6700000 },
 391         .n = { .min = 1, .max = 1 },
 392         .m1 = { .min = 2, .max = 2 },
 393         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 394         .p1 = { .min = 2, .max = 4 },
 395         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 396 };
 397
 398 static void vlv_clock(int refclk, intel_clock_t *clock)
 399 {
 400         clock->m = clock->m1 * clock->m2;
 401         clock->p = clock->p1 * clock->p2;
 402         if (WARN_ON(clock->n == 0 || clock->p == 0))
 403                 return;
 404         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 405         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 406 }
 407
 408 /**
 409  * Returns whether any output on the specified pipe is of the specified type
 410  */
 411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 412 {
 413         struct drm_device *dev = crtc->base.dev;
 414         struct intel_encoder *encoder;
 415
 416         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 417                 if (encoder->type == type)
 418                         return true;
 419
 420         return false;
 421 }
 422
 423 /**
 424  * Returns whether any output on the specified pipe will have the specified
 425  * type after a staged modeset is complete, i.e., the same as
 426  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 427  * encoder->crtc.
 428  */
 429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
 430 {
 431         struct drm_device *dev = crtc->base.dev;
 432         struct intel_encoder *encoder;
 433
 434         for_each_intel_encoder(dev, encoder)
 435                 if (encoder->new_crtc == crtc && encoder->type == type)
 436                         return true;
 437
 438         return false;
 439 }
 440
 441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
 442                                                 int refclk)
 443 {
 444         struct drm_device *dev = crtc->base.dev;
 445         const intel_limit_t *limit;
 446
 447         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 448                 if (intel_is_dual_link_lvds(dev)) {
 449                         if (refclk == 100000)
 450                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 451                         else
 452                                 limit = &intel_limits_ironlake_dual_lvds;
 453                 } else {
 454                         if (refclk == 100000)
 455                                 limit = &intel_limits_ironlake_single_lvds_100m;
 456                         else
 457                                 limit = &intel_limits_ironlake_single_lvds;
 458                 }
 459         } else
 460                 limit = &intel_limits_ironlake_dac;
 461
 462         return limit;
 463 }
 464
 465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
 466 {
 467         struct drm_device *dev = crtc->base.dev;
 468         const intel_limit_t *limit;
 469
 470         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 471                 if (intel_is_dual_link_lvds(dev))
 472                         limit = &intel_limits_g4x_dual_channel_lvds;
 473                 else
 474                         limit = &intel_limits_g4x_single_channel_lvds;
 475         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
 476                    intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
 477                 limit = &intel_limits_g4x_hdmi;
 478         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
 479                 limit = &intel_limits_g4x_sdvo;
 480         } else /* The option is for other outputs */
 481                 limit = &intel_limits_i9xx_sdvo;
 482
 483         return limit;
 484 }
 485
 486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
 487 {
 488         struct drm_device *dev = crtc->base.dev;
 489         const intel_limit_t *limit;
 490
 491         if (HAS_PCH_SPLIT(dev))
 492                 limit = intel_ironlake_limit(crtc, refclk);
 493         else if (IS_G4X(dev)) {
 494                 limit = intel_g4x_limit(crtc);
 495         } else if (IS_PINEVIEW(dev)) {
 496                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 497                         limit = &intel_limits_pineview_lvds;
 498                 else
 499                         limit = &intel_limits_pineview_sdvo;
 500         } else if (IS_CHERRYVIEW(dev)) {
 501                 limit = &intel_limits_chv;
 502         } else if (IS_VALLEYVIEW(dev)) {
 503                 limit = &intel_limits_vlv;
 504         } else if (!IS_GEN2(dev)) {
 505                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 506                         limit = &intel_limits_i9xx_lvds;
 507                 else
 508                         limit = &intel_limits_i9xx_sdvo;
 509         } else {
 510                 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
 511                         limit = &intel_limits_i8xx_lvds;
 512                 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
 513                         limit = &intel_limits_i8xx_dvo;
 514                 else
 515                         limit = &intel_limits_i8xx_dac;
 516         }
 517         return limit;
 518 }
 519
 520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 521 static void pineview_clock(int refclk, intel_clock_t *clock)
 522 {
 523         clock->m = clock->m2 + 2;
 524         clock->p = clock->p1 * clock->p2;
 525         if (WARN_ON(clock->n == 0 || clock->p == 0))
 526                 return;
 527         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 528         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 529 }
 530
 531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 532 {
 533         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 534 }
 535
 536 static void i9xx_clock(int refclk, intel_clock_t *clock)
 537 {
 538         clock->m = i9xx_dpll_compute_m(clock);
 539         clock->p = clock->p1 * clock->p2;
 540         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 541                 return;
 542         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 543         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 544 }
 545
 546 static void chv_clock(int refclk, intel_clock_t *clock)
 547 {
 548         clock->m = clock->m1 * clock->m2;
 549         clock->p = clock->p1 * clock->p2;
 550         if (WARN_ON(clock->n == 0 || clock->p == 0))
 551                 return;
 552         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 553                         clock->n << 22);
 554         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 555 }
 556
 557 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 558 /**
 559  * Returns whether the given set of divisors are valid for a given refclk with
 560  * the given connectors.
 561  */
 562
 563 static bool intel_PLL_is_valid(struct drm_device *dev,
 564                                const intel_limit_t *limit,
 565                                const intel_clock_t *clock)
 566 {
 567         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 568                 INTELPllInvalid("n out of range\n");
 569         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 570                 INTELPllInvalid("p1 out of range\n");
 571         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 572                 INTELPllInvalid("m2 out of range\n");
 573         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 574                 INTELPllInvalid("m1 out of range\n");
 575
 576         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 577                 if (clock->m1 <= clock->m2)
 578                         INTELPllInvalid("m1 <= m2\n");
 579
 580         if (!IS_VALLEYVIEW(dev)) {
 581                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 582                         INTELPllInvalid("p out of range\n");
 583                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 584                         INTELPllInvalid("m out of range\n");
 585         }
 586
 587         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 588                 INTELPllInvalid("vco out of range\n");
 589         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 590          * connector, etc., rather than just a single range.
 591          */
 592         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 593                 INTELPllInvalid("dot out of range\n");
 594
 595         return true;
 596 }
 597
 598 static bool
 599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 600                     int target, int refclk, intel_clock_t *match_clock,
 601                     intel_clock_t *best_clock)
 602 {
 603         struct drm_device *dev = crtc->base.dev;
 604         intel_clock_t clock;
 605         int err = target;
 606
 607         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 608                 /*
 609                  * For LVDS just rely on its current settings for dual-channel.
 610                  * We haven't figured out how to reliably set up different
 611                  * single/dual channel state, if we even can.
 612                  */
 613                 if (intel_is_dual_link_lvds(dev))
 614                         clock.p2 = limit->p2.p2_fast;
 615                 else
 616                         clock.p2 = limit->p2.p2_slow;
 617         } else {
 618                 if (target < limit->p2.dot_limit)
 619                         clock.p2 = limit->p2.p2_slow;
 620                 else
 621                         clock.p2 = limit->p2.p2_fast;
 622         }
 623
 624         memset(best_clock, 0, sizeof(*best_clock));
 625
 626         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 627              clock.m1++) {
 628                 for (clock.m2 = limit->m2.min;
 629                      clock.m2 <= limit->m2.max; clock.m2++) {
 630                         if (clock.m2 >= clock.m1)
 631                                 break;
 632                         for (clock.n = limit->n.min;
 633                              clock.n <= limit->n.max; clock.n++) {
 634                                 for (clock.p1 = limit->p1.min;
 635                                         clock.p1 <= limit->p1.max; clock.p1++) {
 636                                         int this_err;
 637
 638                                         i9xx_clock(refclk, &clock);
 639                                         if (!intel_PLL_is_valid(dev, limit,
 640                                                                 &clock))
 641                                                 continue;
 642                                         if (match_clock &&
 643                                             clock.p != match_clock->p)
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err) {
 648                                                 *best_clock = clock;
 649                                                 err = this_err;
 650                                         }
 651                                 }
 652                         }
 653                 }
 654         }
 655
 656         return (err != target);
 657 }
 658
 659 static bool
 660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 661                    int target, int refclk, intel_clock_t *match_clock,
 662                    intel_clock_t *best_clock)
 663 {
 664         struct drm_device *dev = crtc->base.dev;
 665         intel_clock_t clock;
 666         int err = target;
 667
 668         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 669                 /*
 670                  * For LVDS just rely on its current settings for dual-channel.
 671                  * We haven't figured out how to reliably set up different
 672                  * single/dual channel state, if we even can.
 673                  */
 674                 if (intel_is_dual_link_lvds(dev))
 675                         clock.p2 = limit->p2.p2_fast;
 676                 else
 677                         clock.p2 = limit->p2.p2_slow;
 678         } else {
 679                 if (target < limit->p2.dot_limit)
 680                         clock.p2 = limit->p2.p2_slow;
 681                 else
 682                         clock.p2 = limit->p2.p2_fast;
 683         }
 684
 685         memset(best_clock, 0, sizeof(*best_clock));
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pineview_clock(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(dev, limit,
 699                                                                 &clock))
 700                                                 continue;
 701                                         if (match_clock &&
 702                                             clock.p != match_clock->p)
 703                                                 continue;
 704
 705                                         this_err = abs(clock.dot - target);
 706                                         if (this_err < err) {
 707                                                 *best_clock = clock;
 708                                                 err = this_err;
 709                                         }
 710                                 }
 711                         }
 712                 }
 713         }
 714
 715         return (err != target);
 716 }
 717
 718 static bool
 719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->base.dev;
 724         intel_clock_t clock;
 725         int max_n;
 726         bool found;
 727         /* approximately equals target * 0.00585 */
 728         int err_most = (target >> 8) + (target >> 9);
 729         found = false;
 730
 731         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
 732                 if (intel_is_dual_link_lvds(dev))
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744         max_n = limit->n.max;
 745         /* based on hardware requirement, prefer smaller n to precision */
 746         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 747                 /* based on hardware requirement, prefere larger m1,m2 */
 748                 for (clock.m1 = limit->m1.max;
 749                      clock.m1 >= limit->m1.min; clock.m1--) {
 750                         for (clock.m2 = limit->m2.max;
 751                              clock.m2 >= limit->m2.min; clock.m2--) {
 752                                 for (clock.p1 = limit->p1.max;
 753                                      clock.p1 >= limit->p1.min; clock.p1--) {
 754                                         int this_err;
 755
 756                                         i9xx_clock(refclk, &clock);
 757                                         if (!intel_PLL_is_valid(dev, limit,
 758                                                                 &clock))
 759                                                 continue;
 760
 761                                         this_err = abs(clock.dot - target);
 762                                         if (this_err < err_most) {
 763                                                 *best_clock = clock;
 764                                                 err_most = this_err;
 765                                                 max_n = clock.n;
 766                                                 found = true;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772         return found;
 773 }
 774
 775 static bool
 776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         intel_clock_t clock;
 782         unsigned int bestppm = 1000000;
 783         /* min update 19.2 MHz */
 784         int max_n = min(limit->n.max, refclk / 19200);
 785         bool found = false;
 786
 787         target *= 5; /* fast clock */
 788
 789         memset(best_clock, 0, sizeof(*best_clock));
 790
 791         /* based on hardware requirement, prefer smaller n to precision */
 792         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 793                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 794                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 795                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 796                                 clock.p = clock.p1 * clock.p2;
 797                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 798                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 799                                         unsigned int ppm, diff;
 800
 801                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 802                                                                      refclk * clock.m1);
 803
 804                                         vlv_clock(refclk, &clock);
 805
 806                                         if (!intel_PLL_is_valid(dev, limit,
 807                                                                 &clock))
 808                                                 continue;
 809
 810                                         diff = abs(clock.dot - target);
 811                                         ppm = div_u64(1000000ULL * diff, target);
 812
 813                                         if (ppm < 100 && clock.p > best_clock->p) {
 814                                                 bestppm = 0;
 815                                                 *best_clock = clock;
 816                                                 found = true;
 817                                         }
 818
 819                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 820                                                 bestppm = ppm;
 821                                                 *best_clock = clock;
 822                                                 found = true;
 823                                         }
 824                                 }
 825                         }
 826                 }
 827         }
 828
 829         return found;
 830 }
 831
 832 static bool
 833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
 834                    int target, int refclk, intel_clock_t *match_clock,
 835                    intel_clock_t *best_clock)
 836 {
 837         struct drm_device *dev = crtc->base.dev;
 838         intel_clock_t clock;
 839         uint64_t m2;
 840         int found = false;
 841
 842         memset(best_clock, 0, sizeof(*best_clock));
 843
 844         /*
 845          * Based on hardware doc, the n always set to 1, and m1 always
 846          * set to 2.  If requires to support 200Mhz refclk, we need to
 847          * revisit this because n may not 1 anymore.
 848          */
 849         clock.n = 1, clock.m1 = 2;
 850         target *= 5;    /* fast clock */
 851
 852         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 853                 for (clock.p2 = limit->p2.p2_fast;
 854                                 clock.p2 >= limit->p2.p2_slow;
 855                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 856
 857                         clock.p = clock.p1 * clock.p2;
 858
 859                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 860                                         clock.n) << 22, refclk * clock.m1);
 861
 862                         if (m2 > INT_MAX/clock.m1)
 863                                 continue;
 864
 865                         clock.m2 = m2;
 866
 867                         chv_clock(refclk, &clock);
 868
 869                         if (!intel_PLL_is_valid(dev, limit, &clock))
 870                                 continue;
 871
 872                         /* based on hardware requirement, prefer bigger p
 873                          */
 874                         if (clock.p > best_clock->p) {
 875                                 *best_clock = clock;
 876                                 found = true;
 877                         }
 878                 }
 879         }
 880
 881         return found;
 882 }
 883
 884 bool intel_crtc_active(struct drm_crtc *crtc)
 885 {
 886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 887
 888         /* Be paranoid as we can arrive here with only partial
 889          * state retrieved from the hardware during setup.
 890          *
 891          * We can ditch the adjusted_mode.crtc_clock check as soon
 892          * as Haswell has gained clock readout/fastboot support.
 893          *
 894          * We can ditch the crtc->primary->fb check as soon as we can
 895          * properly reconstruct framebuffers.
 896          */
 897         return intel_crtc->active && crtc->primary->fb &&
 898                 intel_crtc->config.adjusted_mode.crtc_clock;
 899 }
 900
 901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 902                                              enum pipe pipe)
 903 {
 904         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 906
 907         return intel_crtc->config.cpu_transcoder;
 908 }
 909
 910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 911 {
 912         struct drm_i915_private *dev_priv = dev->dev_private;
 913         u32 reg = PIPEDSL(pipe);
 914         u32 line1, line2;
 915         u32 line_mask;
 916
 917         if (IS_GEN2(dev))
 918                 line_mask = DSL_LINEMASK_GEN2;
 919         else
 920                 line_mask = DSL_LINEMASK_GEN3;
 921
 922         line1 = I915_READ(reg) & line_mask;
 923         mdelay(5);
 924         line2 = I915_READ(reg) & line_mask;
 925
 926         return line1 == line2;
 927 }
 928
 929 /*
 930  * intel_wait_for_pipe_off - wait for pipe to turn off
 931  * @crtc: crtc whose pipe to wait for
 932  *
 933  * After disabling a pipe, we can't wait for vblank in the usual way,
 934  * spinning on the vblank interrupt status bit, since we won't actually
 935  * see an interrupt when the pipe is disabled.
 936  *
 937  * On Gen4 and above:
 938  *   wait for the pipe register state bit to turn off
 939  *
 940  * Otherwise:
 941  *   wait for the display line value to settle (it usually
 942  *   ends up stopping at the start of the next frame).
 943  *
 944  */
 945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
 946 {
 947         struct drm_device *dev = crtc->base.dev;
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
 950         enum pipe pipe = crtc->pipe;
 951
 952         if (INTEL_INFO(dev)->gen >= 4) {
 953                 int reg = PIPECONF(cpu_transcoder);
 954
 955                 /* Wait for the Pipe State to go off */
 956                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 957                              100))
 958                         WARN(1, "pipe_off wait timed out\n");
 959         } else {
 960                 /* Wait for the display line to settle */
 961                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 962                         WARN(1, "pipe_off wait timed out\n");
 963         }
 964 }
 965
 966 /*
 967  * ibx_digital_port_connected - is the specified port connected?
 968  * @dev_priv: i915 private structure
 969  * @port: the port to test
 970  *
 971  * Returns true if @port is connected, false otherwise.
 972  */
 973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 974                                 struct intel_digital_port *port)
 975 {
 976         u32 bit;
 977
 978         if (HAS_PCH_IBX(dev_priv->dev)) {
 979                 switch (port->port) {
 980                 case PORT_B:
 981                         bit = SDE_PORTB_HOTPLUG;
 982                         break;
 983                 case PORT_C:
 984                         bit = SDE_PORTC_HOTPLUG;
 985                         break;
 986                 case PORT_D:
 987                         bit = SDE_PORTD_HOTPLUG;
 988                         break;
 989                 default:
 990                         return true;
 991                 }
 992         } else {
 993                 switch (port->port) {
 994                 case PORT_B:
 995                         bit = SDE_PORTB_HOTPLUG_CPT;
 996                         break;
 997                 case PORT_C:
 998                         bit = SDE_PORTC_HOTPLUG_CPT;
 999                         break;
1000                 case PORT_D:
1001                         bit = SDE_PORTD_HOTPLUG_CPT;
1002                         break;
1003                 default:
1004                         return true;
1005                 }
1006         }
1007
1008         return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013         return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018                 enum pipe pipe, bool state)
1019 {
1020         int reg;
1021         u32 val;
1022         bool cur_state;
1023
1024         reg = DPLL(pipe);
1025         val = I915_READ(reg);
1026         cur_state = !!(val & DPLL_VCO_ENABLE);
1027         WARN(cur_state != state,
1028              "PLL state assertion failure (expected %s, current %s)\n",
1029              state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035         u32 val;
1036         bool cur_state;
1037
1038         mutex_lock(&dev_priv->dpio_lock);
1039         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040         mutex_unlock(&dev_priv->dpio_lock);
1041
1042         cur_state = val & DSI_PLL_VCO_EN;
1043         WARN(cur_state != state,
1044              "DSI PLL state assertion failure (expected %s, current %s)\n",
1045              state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055         if (crtc->config.shared_dpll < 0)
1056                 return NULL;
1057
1058         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063                         struct intel_shared_dpll *pll,
1064                         bool state)
1065 {
1066         bool cur_state;
1067         struct intel_dpll_hw_state hw_state;
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                            enum pipe pipe)
1158 {
1159         struct drm_device *dev = dev_priv->dev;
1160         int pp_reg;
1161         u32 val;
1162         enum pipe panel_pipe = PIPE_A;
1163         bool locked = true;
1164
1165         if (WARN_ON(HAS_DDI(dev)))
1166                 return;
1167
1168         if (HAS_PCH_SPLIT(dev)) {
1169                 u32 port_sel;
1170
1171                 pp_reg = PCH_PP_CONTROL;
1172                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176                         panel_pipe = PIPE_B;
1177                 /* XXX: else fix for eDP */
1178         } else if (IS_VALLEYVIEW(dev)) {
1179                 /* presumably write lock depends on pipe, not port select */
1180                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181                 panel_pipe = pipe;
1182         } else {
1183                 pp_reg = PP_CONTROL;
1184                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185                         panel_pipe = PIPE_B;
1186         }
1187
1188         val = I915_READ(pp_reg);
1189         if (!(val & PANEL_POWER_ON) ||
1190             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191                 locked = false;
1192
1193         WARN(panel_pipe == pipe && locked,
1194              "panel assertion failure, pipe %c regs locked\n",
1195              pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199                           enum pipe pipe, bool state)
1200 {
1201         struct drm_device *dev = dev_priv->dev;
1202         bool cur_state;
1203
1204         if (IS_845G(dev) || IS_I865G(dev))
1205                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206         else
1207                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209         WARN(cur_state != state,
1210              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211              pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217                  enum pipe pipe, bool state)
1218 {
1219         int reg;
1220         u32 val;
1221         bool cur_state;
1222         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223                                                                       pipe);
1224
1225         /* if we need the pipe quirk it must be always on */
1226         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228                 state = true;
1229
1230         if (!intel_display_power_is_enabled(dev_priv,
1231                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232                 cur_state = false;
1233         } else {
1234                 reg = PIPECONF(cpu_transcoder);
1235                 val = I915_READ(reg);
1236                 cur_state = !!(val & PIPECONF_ENABLE);
1237         }
1238
1239         WARN(cur_state != state,
1240              "pipe %c assertion failure (expected %s, current %s)\n",
1241              pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245                          enum plane plane, bool state)
1246 {
1247         int reg;
1248         u32 val;
1249         bool cur_state;
1250
1251         reg = DSPCNTR(plane);
1252         val = I915_READ(reg);
1253         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254         WARN(cur_state != state,
1255              "plane %c assertion failure (expected %s, current %s)\n",
1256              plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263                                    enum pipe pipe)
1264 {
1265         struct drm_device *dev = dev_priv->dev;
1266         int reg, i;
1267         u32 val;
1268         int cur_pipe;
1269
1270         /* Primary planes are fixed to pipes on gen4+ */
1271         if (INTEL_INFO(dev)->gen >= 4) {
1272                 reg = DSPCNTR(pipe);
1273                 val = I915_READ(reg);
1274                 WARN(val & DISPLAY_PLANE_ENABLE,
1275                      "plane %c assertion failure, should be disabled but not\n",
1276                      plane_name(pipe));
1277                 return;
1278         }
1279
1280         /* Need to check both planes against the pipe */
1281         for_each_pipe(dev_priv, i) {
1282                 reg = DSPCNTR(i);
1283                 val = I915_READ(reg);
1284                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285                         DISPPLANE_SEL_PIPE_SHIFT;
1286                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288                      plane_name(i), pipe_name(pipe));
1289         }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293                                     enum pipe pipe)
1294 {
1295         struct drm_device *dev = dev_priv->dev;
1296         int reg, sprite;
1297         u32 val;
1298
1299         if (INTEL_INFO(dev)->gen >= 9) {
1300                 for_each_sprite(pipe, sprite) {
1301                         val = I915_READ(PLANE_CTL(pipe, sprite));
1302                         WARN(val & PLANE_CTL_ENABLE,
1303                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304                              sprite, pipe_name(pipe));
1305                 }
1306         } else if (IS_VALLEYVIEW(dev)) {
1307                 for_each_sprite(pipe, sprite) {
1308                         reg = SPCNTR(pipe, sprite);
1309                         val = I915_READ(reg);
1310                         WARN(val & SP_ENABLE,
1311                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312                              sprite_name(pipe, sprite), pipe_name(pipe));
1313                 }
1314         } else if (INTEL_INFO(dev)->gen >= 7) {
1315                 reg = SPRCTL(pipe);
1316                 val = I915_READ(reg);
1317                 WARN(val & SPRITE_ENABLE,
1318                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319                      plane_name(pipe), pipe_name(pipe));
1320         } else if (INTEL_INFO(dev)->gen >= 5) {
1321                 reg = DVSCNTR(pipe);
1322                 val = I915_READ(reg);
1323                 WARN(val & DVS_ENABLE,
1324                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325                      plane_name(pipe), pipe_name(pipe));
1326         }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331         if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332                 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337         u32 val;
1338         bool enabled;
1339
1340         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342         val = I915_READ(PCH_DREF_CONTROL);
1343         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344                             DREF_SUPERSPREAD_SOURCE_MASK));
1345         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349                                            enum pipe pipe)
1350 {
1351         int reg;
1352         u32 val;
1353         bool enabled;
1354
1355         reg = PCH_TRANSCONF(pipe);
1356         val = I915_READ(reg);
1357         enabled = !!(val & TRANS_ENABLE);
1358         WARN(enabled,
1359              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360              pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364                             enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366         if ((val & DP_PORT_EN) == 0)
1367                 return false;
1368
1369         if (HAS_PCH_CPT(dev_priv->dev)) {
1370                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373                         return false;
1374         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376                         return false;
1377         } else {
1378                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379                         return false;
1380         }
1381         return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385                               enum pipe pipe, u32 val)
1386 {
1387         if ((val & SDVO_ENABLE) == 0)
1388                 return false;
1389
1390         if (HAS_PCH_CPT(dev_priv->dev)) {
1391                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392                         return false;
1393         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395                         return false;
1396         } else {
1397                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398                         return false;
1399         }
1400         return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404                               enum pipe pipe, u32 val)
1405 {
1406         if ((val & LVDS_PORT_EN) == 0)
1407                 return false;
1408
1409         if (HAS_PCH_CPT(dev_priv->dev)) {
1410                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411                         return false;
1412         } else {
1413                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414                         return false;
1415         }
1416         return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420                               enum pipe pipe, u32 val)
1421 {
1422         if ((val & ADPA_DAC_ENABLE) == 0)
1423                 return false;
1424         if (HAS_PCH_CPT(dev_priv->dev)) {
1425                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426                         return false;
1427         } else {
1428                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429                         return false;
1430         }
1431         return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435                                    enum pipe pipe, int reg, u32 port_sel)
1436 {
1437         u32 val = I915_READ(reg);
1438         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440              reg, pipe_name(pipe));
1441
1442         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443              && (val & DP_PIPEB_SELECT),
1444              "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448                                      enum pipe pipe, int reg)
1449 {
1450         u32 val = I915_READ(reg);
1451         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453              reg, pipe_name(pipe));
1454
1455         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456              && (val & SDVO_PIPE_B_SELECT),
1457              "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461                                       enum pipe pipe)
1462 {
1463         int reg;
1464         u32 val;
1465
1466         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470         reg = PCH_ADPA;
1471         val = I915_READ(reg);
1472         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473              "PCH VGA enabled on transcoder %c, should be disabled\n",
1474              pipe_name(pipe));
1475
1476         reg = PCH_LVDS;
1477         val = I915_READ(reg);
1478         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480              pipe_name(pipe));
1481
1482         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491         if (!IS_VALLEYVIEW(dev))
1492                 return;
1493
1494         /*
1495          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496          * CHV x1 PHY (DP/HDMI D)
1497          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498          */
1499         if (IS_CHERRYVIEW(dev)) {
1500                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502         } else {
1503                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504         }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508                            const struct intel_crtc_config *pipe_config)
1509 {
1510         struct drm_device *dev = crtc->base.dev;
1511         struct drm_i915_private *dev_priv = dev->dev_private;
1512         int reg = DPLL(crtc->pipe);
1513         u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515         assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517         /* No really, not for ILK+ */
1518         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520         /* PLL is protected by panel, make sure we can write it */
1521         if (IS_MOBILE(dev_priv->dev))
1522                 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524         I915_WRITE(reg, dpll);
1525         POSTING_READ(reg);
1526         udelay(150);
1527
1528         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532         POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534         /* We do this three times for luck */
1535         I915_WRITE(reg, dpll);
1536         POSTING_READ(reg);
1537         udelay(150); /* wait for warmup */
1538         I915_WRITE(reg, dpll);
1539         POSTING_READ(reg);
1540         udelay(150); /* wait for warmup */
1541         I915_WRITE(reg, dpll);
1542         POSTING_READ(reg);
1543         udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_config *pipe_config)
1548 {
1549         struct drm_device *dev = crtc->base.dev;
1550         struct drm_i915_private *dev_priv = dev->dev_private;
1551         int pipe = crtc->pipe;
1552         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553         u32 tmp;
1554
1555         assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559         mutex_lock(&dev_priv->dpio_lock);
1560
1561         /* Enable back the 10bit clock to display controller */
1562         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563         tmp |= DPIO_DCLKP_EN;
1564         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566         /*
1567          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568          */
1569         udelay(1);
1570
1571         /* Enable PLL */
1572         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574         /* Check PLL is locked */
1575         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578         /* not sure when this should be written */
1579         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580         POSTING_READ(DPLL_MD(pipe));
1581
1582         mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587         struct intel_crtc *crtc;
1588         int count = 0;
1589
1590         for_each_intel_crtc(dev, crtc)
1591                 count += crtc->active &&
1592                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594         return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599         struct drm_device *dev = crtc->base.dev;
1600         struct drm_i915_private *dev_priv = dev->dev_private;
1601         int reg = DPLL(crtc->pipe);
1602         u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604         assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606         /* No really, not for ILK+ */
1607         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609         /* PLL is protected by panel, make sure we can write it */
1610         if (IS_MOBILE(dev) && !IS_I830(dev))
1611                 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613         /* Enable DVO 2x clock on both PLLs if necessary */
1614         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615                 /*
1616                  * It appears to be important that we don't enable this
1617                  * for the current pipe before otherwise configuring the
1618                  * PLL. No idea how this should be handled if multiple
1619                  * DVO outputs are enabled simultaneosly.
1620                  */
1621                 dpll |= DPLL_DVO_2X_MODE;
1622                 I915_WRITE(DPLL(!crtc->pipe),
1623                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624         }
1625
1626         /* Wait for the clocks to stabilize. */
1627         POSTING_READ(reg);
1628         udelay(150);
1629
1630         if (INTEL_INFO(dev)->gen >= 4) {
1631                 I915_WRITE(DPLL_MD(crtc->pipe),
1632                            crtc->config.dpll_hw_state.dpll_md);
1633         } else {
1634                 /* The pixel multiplier can only be updated once the
1635                  * DPLL is enabled and the clocks are stable.
1636                  *
1637                  * So write it again.
1638                  */
1639                 I915_WRITE(reg, dpll);
1640         }
1641
1642         /* We do this three times for luck */
1643         I915_WRITE(reg, dpll);
1644         POSTING_READ(reg);
1645         udelay(150); /* wait for warmup */
1646         I915_WRITE(reg, dpll);
1647         POSTING_READ(reg);
1648         udelay(150); /* wait for warmup */
1649         I915_WRITE(reg, dpll);
1650         POSTING_READ(reg);
1651         udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655  * i9xx_disable_pll - disable a PLL
1656  * @dev_priv: i915 private structure
1657  * @pipe: pipe PLL to disable
1658  *
1659  * Disable the PLL for @pipe, making sure the pipe is off first.
1660  *
1661  * Note!  This is for pre-ILK only.
1662  */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665         struct drm_device *dev = crtc->base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         enum pipe pipe = crtc->pipe;
1668
1669         /* Disable DVO 2x clock on both PLLs if necessary */
1670         if (IS_I830(dev) &&
1671             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672             intel_num_dvo_pipes(dev) == 1) {
1673                 I915_WRITE(DPLL(PIPE_B),
1674                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675                 I915_WRITE(DPLL(PIPE_A),
1676                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677         }
1678
1679         /* Don't disable pipe or pipe PLLs if needed */
1680         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682                 return;
1683
1684         /* Make sure the pipe isn't still relying on us */
1685         assert_pipe_disabled(dev_priv, pipe);
1686
1687         I915_WRITE(DPLL(pipe), 0);
1688         POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693         u32 val = 0;
1694
1695         /* Make sure the pipe isn't still relying on us */
1696         assert_pipe_disabled(dev_priv, pipe);
1697
1698         /*
1699          * Leave integrated clock source and reference clock enabled for pipe B.
1700          * The latter is needed for VGA hotplug / manual detection.
1701          */
1702         if (pipe == PIPE_B)
1703                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704         I915_WRITE(DPLL(pipe), val);
1705         POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712         u32 val;
1713
1714         /* Make sure the pipe isn't still relying on us */
1715         assert_pipe_disabled(dev_priv, pipe);
1716
1717         /* Set PLL en = 0 */
1718         val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719         if (pipe != PIPE_A)
1720                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721         I915_WRITE(DPLL(pipe), val);
1722         POSTING_READ(DPLL(pipe));
1723
1724         mutex_lock(&dev_priv->dpio_lock);
1725
1726         /* Disable 10bit clock to display controller */
1727         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728         val &= ~DPIO_DCLKP_EN;
1729         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731         /* disable left/right clock distribution */
1732         if (pipe != PIPE_B) {
1733                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736         } else {
1737                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740         }
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746                 struct intel_digital_port *dport)
1747 {
1748         u32 port_mask;
1749         int dpll_reg;
1750
1751         switch (dport->port) {
1752         case PORT_B:
1753                 port_mask = DPLL_PORTB_READY_MASK;
1754                 dpll_reg = DPLL(0);
1755                 break;
1756         case PORT_C:
1757                 port_mask = DPLL_PORTC_READY_MASK;
1758                 dpll_reg = DPLL(0);
1759                 break;
1760         case PORT_D:
1761                 port_mask = DPLL_PORTD_READY_MASK;
1762                 dpll_reg = DPIO_PHY_STATUS;
1763                 break;
1764         default:
1765                 BUG();
1766         }
1767
1768         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770                      port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775         struct drm_device *dev = crtc->base.dev;
1776         struct drm_i915_private *dev_priv = dev->dev_private;
1777         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779         if (WARN_ON(pll == NULL))
1780                 return;
1781
1782         WARN_ON(!pll->config.crtc_mask);
1783         if (pll->active == 0) {
1784                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785                 WARN_ON(pll->on);
1786                 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788                 pll->mode_set(dev_priv, pll);
1789         }
1790 }
1791
1792 /**
1793  * intel_enable_shared_dpll - enable PCH PLL
1794  * @dev_priv: i915 private structure
1795  * @pipe: pipe PLL to enable
1796  *
1797  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798  * drives the transcoder clock.
1799  */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802         struct drm_device *dev = crtc->base.dev;
1803         struct drm_i915_private *dev_priv = dev->dev_private;
1804         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806         if (WARN_ON(pll == NULL))
1807                 return;
1808
1809         if (WARN_ON(pll->config.crtc_mask == 0))
1810                 return;
1811
1812         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813                       pll->name, pll->active, pll->on,
1814                       crtc->base.base.id);
1815
1816         if (pll->active++) {
1817                 WARN_ON(!pll->on);
1818                 assert_shared_dpll_enabled(dev_priv, pll);
1819                 return;
1820         }
1821         WARN_ON(pll->on);
1822
1823         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826         pll->enable(dev_priv, pll);
1827         pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832         struct drm_device *dev = crtc->base.dev;
1833         struct drm_i915_private *dev_priv = dev->dev_private;
1834         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836         /* PCH only available on ILK+ */
1837         BUG_ON(INTEL_INFO(dev)->gen < 5);
1838         if (WARN_ON(pll == NULL))
1839                return;
1840
1841         if (WARN_ON(pll->config.crtc_mask == 0))
1842                 return;
1843
1844         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845                       pll->name, pll->active, pll->on,
1846                       crtc->base.base.id);
1847
1848         if (WARN_ON(pll->active == 0)) {
1849                 assert_shared_dpll_disabled(dev_priv, pll);
1850                 return;
1851         }
1852
1853         assert_shared_dpll_enabled(dev_priv, pll);
1854         WARN_ON(!pll->on);
1855         if (--pll->active)
1856                 return;
1857
1858         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859         pll->disable(dev_priv, pll);
1860         pll->on = false;
1861
1862         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866                                            enum pipe pipe)
1867 {
1868         struct drm_device *dev = dev_priv->dev;
1869         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871         uint32_t reg, val, pipeconf_val;
1872
1873         /* PCH only available on ILK+ */
1874         BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876         /* Make sure PCH DPLL is enabled */
1877         assert_shared_dpll_enabled(dev_priv,
1878                                    intel_crtc_to_shared_dpll(intel_crtc));
1879
1880         /* FDI must be feeding us bits for PCH ports */
1881         assert_fdi_tx_enabled(dev_priv, pipe);
1882         assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884         if (HAS_PCH_CPT(dev)) {
1885                 /* Workaround: Set the timing override bit before enabling the
1886                  * pch transcoder. */
1887                 reg = TRANS_CHICKEN2(pipe);
1888                 val = I915_READ(reg);
1889                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890                 I915_WRITE(reg, val);
1891         }
1892
1893         reg = PCH_TRANSCONF(pipe);
1894         val = I915_READ(reg);
1895         pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897         if (HAS_PCH_IBX(dev_priv->dev)) {
1898                 /*
1899                  * make the BPC in transcoder be consistent with
1900                  * that in pipeconf reg.
1901                  */
1902                 val &= ~PIPECONF_BPC_MASK;
1903                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904         }
1905
1906         val &= ~TRANS_INTERLACE_MASK;
1907         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908                 if (HAS_PCH_IBX(dev_priv->dev) &&
1909                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910                         val |= TRANS_LEGACY_INTERLACED_ILK;
1911                 else
1912                         val |= TRANS_INTERLACED;
1913         else
1914                 val |= TRANS_PROGRESSIVE;
1915
1916         I915_WRITE(reg, val | TRANS_ENABLE);
1917         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922                                       enum transcoder cpu_transcoder)
1923 {
1924         u32 val, pipeconf_val;
1925
1926         /* PCH only available on ILK+ */
1927         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929         /* FDI must be feeding us bits for PCH ports */
1930         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933         /* Workaround: set timing override bit. */
1934         val = I915_READ(_TRANSA_CHICKEN2);
1935         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936         I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938         val = TRANS_ENABLE;
1939         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942             PIPECONF_INTERLACED_ILK)
1943                 val |= TRANS_INTERLACED;
1944         else
1945                 val |= TRANS_PROGRESSIVE;
1946
1947         I915_WRITE(LPT_TRANSCONF, val);
1948         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949                 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953                                             enum pipe pipe)
1954 {
1955         struct drm_device *dev = dev_priv->dev;
1956         uint32_t reg, val;
1957
1958         /* FDI relies on the transcoder */
1959         assert_fdi_tx_disabled(dev_priv, pipe);
1960         assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962         /* Ports must be off as well */
1963         assert_pch_ports_disabled(dev_priv, pipe);
1964
1965         reg = PCH_TRANSCONF(pipe);
1966         val = I915_READ(reg);
1967         val &= ~TRANS_ENABLE;
1968         I915_WRITE(reg, val);
1969         /* wait for PCH transcoder off, transcoder state */
1970         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973         if (!HAS_PCH_IBX(dev)) {
1974                 /* Workaround: Clear the timing override chicken bit again. */
1975                 reg = TRANS_CHICKEN2(pipe);
1976                 val = I915_READ(reg);
1977                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978                 I915_WRITE(reg, val);
1979         }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984         u32 val;
1985
1986         val = I915_READ(LPT_TRANSCONF);
1987         val &= ~TRANS_ENABLE;
1988         I915_WRITE(LPT_TRANSCONF, val);
1989         /* wait for PCH transcoder off, transcoder state */
1990         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991                 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993         /* Workaround: clear timing override bit. */
1994         val = I915_READ(_TRANSA_CHICKEN2);
1995         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996         I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000  * intel_enable_pipe - enable a pipe, asserting requirements
2001  * @crtc: crtc responsible for the pipe
2002  *
2003  * Enable @crtc's pipe, making sure that various hardware specific requirements
2004  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005  */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008         struct drm_device *dev = crtc->base.dev;
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         enum pipe pipe = crtc->pipe;
2011         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012                                                                       pipe);
2013         enum pipe pch_transcoder;
2014         int reg;
2015         u32 val;
2016
2017         assert_planes_disabled(dev_priv, pipe);
2018         assert_cursor_disabled(dev_priv, pipe);
2019         assert_sprites_disabled(dev_priv, pipe);
2020
2021         if (HAS_PCH_LPT(dev_priv->dev))
2022                 pch_transcoder = TRANSCODER_A;
2023         else
2024                 pch_transcoder = pipe;
2025
2026         /*
2027          * A pipe without a PLL won't actually be able to drive bits from
2028          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
2029          * need the check.
2030          */
2031         if (!HAS_PCH_SPLIT(dev_priv->dev))
2032                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033                         assert_dsi_pll_enabled(dev_priv);
2034                 else
2035                         assert_pll_enabled(dev_priv, pipe);
2036         else {
2037                 if (crtc->config.has_pch_encoder) {
2038                         /* if driving the PCH, we need FDI enabled */
2039                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040                         assert_fdi_tx_pll_enabled(dev_priv,
2041                                                   (enum pipe) cpu_transcoder);
2042                 }
2043                 /* FIXME: assert CPU port conditions for SNB+ */
2044         }
2045
2046         reg = PIPECONF(cpu_transcoder);
2047         val = I915_READ(reg);
2048         if (val & PIPECONF_ENABLE) {
2049                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051                 return;
2052         }
2053
2054         I915_WRITE(reg, val | PIPECONF_ENABLE);
2055         POSTING_READ(reg);
2056 }
2057
2058 /**
2059  * intel_disable_pipe - disable a pipe, asserting requirements
2060  * @crtc: crtc whose pipes is to be disabled
2061  *
2062  * Disable the pipe of @crtc, making sure that various hardware
2063  * specific requirements are met, if applicable, e.g. plane
2064  * disabled, panel fitter off, etc.
2065  *
2066  * Will wait until the pipe has shut down before returning.
2067  */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072         enum pipe pipe = crtc->pipe;
2073         int reg;
2074         u32 val;
2075
2076         /*
2077          * Make sure planes won't keep trying to pump pixels to us,
2078          * or we might hang the display.
2079          */
2080         assert_planes_disabled(dev_priv, pipe);
2081         assert_cursor_disabled(dev_priv, pipe);
2082         assert_sprites_disabled(dev_priv, pipe);
2083
2084         reg = PIPECONF(cpu_transcoder);
2085         val = I915_READ(reg);
2086         if ((val & PIPECONF_ENABLE) == 0)
2087                 return;
2088
2089         /*
2090          * Double wide has implications for planes
2091          * so best keep it disabled when not needed.
2092          */
2093         if (crtc->config.double_wide)
2094                 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096         /* Don't disable pipe or pipe PLLs if needed */
2097         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099                 val &= ~PIPECONF_ENABLE;
2100
2101         I915_WRITE(reg, val);
2102         if ((val & PIPECONF_ENABLE) == 0)
2103                 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107  * Plane regs are double buffered, going from enabled->disabled needs a
2108  * trigger in order to latch.  The display address reg provides this.
2109  */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111                                enum plane plane)
2112 {
2113         struct drm_device *dev = dev_priv->dev;
2114         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116         I915_WRITE(reg, I915_READ(reg));
2117         POSTING_READ(reg);
2118 }
2119
2120 /**
2121  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122  * @plane:  plane to be enabled
2123  * @crtc: crtc for the plane
2124  *
2125  * Enable @plane on @crtc, making sure that the pipe is running first.
2126  */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128                                           struct drm_crtc *crtc)
2129 {
2130         struct drm_device *dev = plane->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137         if (intel_crtc->primary_enabled)
2138                 return;
2139
2140         intel_crtc->primary_enabled = true;
2141
2142         dev_priv->display.update_primary_plane(crtc, plane->fb,
2143                                                crtc->x, crtc->y);
2144
2145         /*
2146          * BDW signals flip done immediately if the plane
2147          * is disabled, even if the plane enable is already
2148          * armed to occur at the next vblank :(
2149          */
2150         if (IS_BROADWELL(dev))
2151                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155  * intel_disable_primary_hw_plane - disable the primary hardware plane
2156  * @plane: plane to be disabled
2157  * @crtc: crtc for the plane
2158  *
2159  * Disable @plane on @crtc, making sure that the pipe is running first.
2160  */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162                                            struct drm_crtc *crtc)
2163 {
2164         struct drm_device *dev = plane->dev;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168         assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170         if (!intel_crtc->primary_enabled)
2171                 return;
2172
2173         intel_crtc->primary_enabled = false;
2174
2175         dev_priv->display.update_primary_plane(crtc, plane->fb,
2176                                                crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183                 return true;
2184 #endif
2185         return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190         int tile_height;
2191
2192         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193         return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198                            struct drm_framebuffer *fb,
2199                            struct intel_engine_cs *pipelined)
2200 {
2201         struct drm_device *dev = fb->dev;
2202         struct drm_i915_private *dev_priv = dev->dev_private;
2203         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204         u32 alignment;
2205         int ret;
2206
2207         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209         switch (obj->tiling_mode) {
2210         case I915_TILING_NONE:
2211                 if (INTEL_INFO(dev)->gen >= 9)
2212                         alignment = 256 * 1024;
2213                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214                         alignment = 128 * 1024;
2215                 else if (INTEL_INFO(dev)->gen >= 4)
2216                         alignment = 4 * 1024;
2217                 else
2218                         alignment = 64 * 1024;
2219                 break;
2220         case I915_TILING_X:
2221                 if (INTEL_INFO(dev)->gen >= 9)
2222                         alignment = 256 * 1024;
2223                 else {
2224                         /* pin() will align the object as required by fence */
2225                         alignment = 0;
2226                 }
2227                 break;
2228         case I915_TILING_Y:
2229                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230                 return -EINVAL;
2231         default:
2232                 BUG();
2233         }
2234
2235         /* Note that the w/a also requires 64 PTE of padding following the
2236          * bo. We currently fill all unused PTE with the shadow page and so
2237          * we should always have valid PTE following the scanout preventing
2238          * the VT-d warning.
2239          */
2240         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241                 alignment = 256 * 1024;
2242
2243         /*
2244          * Global gtt pte registers are special registers which actually forward
2245          * writes to a chunk of system memory. Which means that there is no risk
2246          * that the register values disappear as soon as we call
2247          * intel_runtime_pm_put(), so it is correct to wrap only the
2248          * pin/unpin/fence and not more.
2249          */
2250         intel_runtime_pm_get(dev_priv);
2251
2252         dev_priv->mm.interruptible = false;
2253         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254         if (ret)
2255                 goto err_interruptible;
2256
2257         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258          * fence, whereas 965+ only requires a fence if using
2259          * framebuffer compression.  For simplicity, we always install
2260          * a fence as the cost is not that onerous.
2261          */
2262         ret = i915_gem_object_get_fence(obj);
2263         if (ret)
2264                 goto err_unpin;
2265
2266         i915_gem_object_pin_fence(obj);
2267
2268         dev_priv->mm.interruptible = true;
2269         intel_runtime_pm_put(dev_priv);
2270         return 0;
2271
2272 err_unpin:
2273         i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275         dev_priv->mm.interruptible = true;
2276         intel_runtime_pm_put(dev_priv);
2277         return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284         i915_gem_object_unpin_fence(obj);
2285         i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289  * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291                                              unsigned int tiling_mode,
2292                                              unsigned int cpp,
2293                                              unsigned int pitch)
2294 {
2295         if (tiling_mode != I915_TILING_NONE) {
2296                 unsigned int tile_rows, tiles;
2297
2298                 tile_rows = *y / 8;
2299                 *y %= 8;
2300
2301                 tiles = *x / (512/cpp);
2302                 *x %= 512/cpp;
2303
2304                 return tile_rows * pitch * 8 + tiles * 4096;
2305         } else {
2306                 unsigned int offset;
2307
2308                 offset = *y * pitch + *x * cpp;
2309                 *y = 0;
2310                 *x = (offset & 4095) / cpp;
2311                 return offset & -4096;
2312         }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317         switch (format) {
2318         case DISPPLANE_8BPP:
2319                 return DRM_FORMAT_C8;
2320         case DISPPLANE_BGRX555:
2321                 return DRM_FORMAT_XRGB1555;
2322         case DISPPLANE_BGRX565:
2323                 return DRM_FORMAT_RGB565;
2324         default:
2325         case DISPPLANE_BGRX888:
2326                 return DRM_FORMAT_XRGB8888;
2327         case DISPPLANE_RGBX888:
2328                 return DRM_FORMAT_XBGR8888;
2329         case DISPPLANE_BGRX101010:
2330                 return DRM_FORMAT_XRGB2101010;
2331         case DISPPLANE_RGBX101010:
2332                 return DRM_FORMAT_XBGR2101010;
2333         }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337                                   struct intel_plane_config *plane_config)
2338 {
2339         struct drm_device *dev = crtc->base.dev;
2340         struct drm_i915_gem_object *obj = NULL;
2341         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342         u32 base = plane_config->base;
2343
2344         if (plane_config->size == 0)
2345                 return false;
2346
2347         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348                                                              plane_config->size);
2349         if (!obj)
2350                 return false;
2351
2352         if (plane_config->tiled) {
2353                 obj->tiling_mode = I915_TILING_X;
2354                 obj->stride = crtc->base.primary->fb->pitches[0];
2355         }
2356
2357         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358         mode_cmd.width = crtc->base.primary->fb->width;
2359         mode_cmd.height = crtc->base.primary->fb->height;
2360         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362         mutex_lock(&dev->struct_mutex);
2363
2364         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365                                    &mode_cmd, obj)) {
2366                 DRM_DEBUG_KMS("intel fb init failed\n");
2367                 goto out_unref_obj;
2368         }
2369
2370         obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371         mutex_unlock(&dev->struct_mutex);
2372
2373         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374         return true;
2375
2376 out_unref_obj:
2377         drm_gem_object_unreference(&obj->base);
2378         mutex_unlock(&dev->struct_mutex);
2379         return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383                                  struct intel_plane_config *plane_config)
2384 {
2385         struct drm_device *dev = intel_crtc->base.dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct drm_crtc *c;
2388         struct intel_crtc *i;
2389         struct drm_i915_gem_object *obj;
2390
2391         if (!intel_crtc->base.primary->fb)
2392                 return;
2393
2394         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395                 return;
2396
2397         kfree(intel_crtc->base.primary->fb);
2398         intel_crtc->base.primary->fb = NULL;
2399
2400         /*
2401          * Failed to alloc the obj, check to see if we should share
2402          * an fb with another CRTC instead
2403          */
2404         for_each_crtc(dev, c) {
2405                 i = to_intel_crtc(c);
2406
2407                 if (c == &intel_crtc->base)
2408                         continue;
2409
2410                 if (!i->active)
2411                         continue;
2412
2413                 obj = intel_fb_obj(c->primary->fb);
2414                 if (obj == NULL)
2415                         continue;
2416
2417                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418                         if (obj->tiling_mode != I915_TILING_NONE)
2419                                 dev_priv->preserve_bios_swizzle = true;
2420
2421                         drm_framebuffer_reference(c->primary->fb);
2422                         intel_crtc->base.primary->fb = c->primary->fb;
2423                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424                         break;
2425                 }
2426         }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430                                       struct drm_framebuffer *fb,
2431                                       int x, int y)
2432 {
2433         struct drm_device *dev = crtc->dev;
2434         struct drm_i915_private *dev_priv = dev->dev_private;
2435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436         struct drm_i915_gem_object *obj;
2437         int plane = intel_crtc->plane;
2438         unsigned long linear_offset;
2439         u32 dspcntr;
2440         u32 reg = DSPCNTR(plane);
2441         int pixel_size;
2442
2443         if (!intel_crtc->primary_enabled) {
2444                 I915_WRITE(reg, 0);
2445                 if (INTEL_INFO(dev)->gen >= 4)
2446                         I915_WRITE(DSPSURF(plane), 0);
2447                 else
2448                         I915_WRITE(DSPADDR(plane), 0);
2449                 POSTING_READ(reg);
2450                 return;
2451         }
2452
2453         obj = intel_fb_obj(fb);
2454         if (WARN_ON(obj == NULL))
2455                 return;
2456
2457         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459         dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461         dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463         if (INTEL_INFO(dev)->gen < 4) {
2464                 if (intel_crtc->pipe == PIPE_B)
2465                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467                 /* pipesrc and dspsize control the size that is scaled from,
2468                  * which should always be the user's requested size.
2469                  */
2470                 I915_WRITE(DSPSIZE(plane),
2471                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472                            (intel_crtc->config.pipe_src_w - 1));
2473                 I915_WRITE(DSPPOS(plane), 0);
2474         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475                 I915_WRITE(PRIMSIZE(plane),
2476                            ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477                            (intel_crtc->config.pipe_src_w - 1));
2478                 I915_WRITE(PRIMPOS(plane), 0);
2479                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480         }
2481
2482         switch (fb->pixel_format) {
2483         case DRM_FORMAT_C8:
2484                 dspcntr |= DISPPLANE_8BPP;
2485                 break;
2486         case DRM_FORMAT_XRGB1555:
2487         case DRM_FORMAT_ARGB1555:
2488                 dspcntr |= DISPPLANE_BGRX555;
2489                 break;
2490         case DRM_FORMAT_RGB565:
2491                 dspcntr |= DISPPLANE_BGRX565;
2492                 break;
2493         case DRM_FORMAT_XRGB8888:
2494         case DRM_FORMAT_ARGB8888:
2495                 dspcntr |= DISPPLANE_BGRX888;
2496                 break;
2497         case DRM_FORMAT_XBGR8888:
2498         case DRM_FORMAT_ABGR8888:
2499                 dspcntr |= DISPPLANE_RGBX888;
2500                 break;
2501         case DRM_FORMAT_XRGB2101010:
2502         case DRM_FORMAT_ARGB2101010:
2503                 dspcntr |= DISPPLANE_BGRX101010;
2504                 break;
2505         case DRM_FORMAT_XBGR2101010:
2506         case DRM_FORMAT_ABGR2101010:
2507                 dspcntr |= DISPPLANE_RGBX101010;
2508                 break;
2509         default:
2510                 BUG();
2511         }
2512
2513         if (INTEL_INFO(dev)->gen >= 4 &&
2514             obj->tiling_mode != I915_TILING_NONE)
2515                 dspcntr |= DISPPLANE_TILED;
2516
2517         if (IS_G4X(dev))
2518                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520         linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522         if (INTEL_INFO(dev)->gen >= 4) {
2523                 intel_crtc->dspaddr_offset =
2524                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525                                                        pixel_size,
2526                                                        fb->pitches[0]);
2527                 linear_offset -= intel_crtc->dspaddr_offset;
2528         } else {
2529                 intel_crtc->dspaddr_offset = linear_offset;
2530         }
2531
2532         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533                 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535                 x += (intel_crtc->config.pipe_src_w - 1);
2536                 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538                 /* Finding the last pixel of the last line of the display
2539                 data and adding to linear_offset*/
2540                 linear_offset +=
2541                         (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542                         (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543         }
2544
2545         I915_WRITE(reg, dspcntr);
2546
2547         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549                       fb->pitches[0]);
2550         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551         if (INTEL_INFO(dev)->gen >= 4) {
2552                 I915_WRITE(DSPSURF(plane),
2553                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556         } else
2557                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558         POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562                                           struct drm_framebuffer *fb,
2563                                           int x, int y)
2564 {
2565         struct drm_device *dev = crtc->dev;
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568         struct drm_i915_gem_object *obj;
2569         int plane = intel_crtc->plane;
2570         unsigned long linear_offset;
2571         u32 dspcntr;
2572         u32 reg = DSPCNTR(plane);
2573         int pixel_size;
2574
2575         if (!intel_crtc->primary_enabled) {
2576                 I915_WRITE(reg, 0);
2577                 I915_WRITE(DSPSURF(plane), 0);
2578                 POSTING_READ(reg);
2579                 return;
2580         }
2581
2582         obj = intel_fb_obj(fb);
2583         if (WARN_ON(obj == NULL))
2584                 return;
2585
2586         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588         dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590         dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595         switch (fb->pixel_format) {
2596         case DRM_FORMAT_C8:
2597                 dspcntr |= DISPPLANE_8BPP;
2598                 break;
2599         case DRM_FORMAT_RGB565:
2600                 dspcntr |= DISPPLANE_BGRX565;
2601                 break;
2602         case DRM_FORMAT_XRGB8888:
2603         case DRM_FORMAT_ARGB8888:
2604                 dspcntr |= DISPPLANE_BGRX888;
2605                 break;
2606         case DRM_FORMAT_XBGR8888:
2607         case DRM_FORMAT_ABGR8888:
2608                 dspcntr |= DISPPLANE_RGBX888;
2609                 break;
2610         case DRM_FORMAT_XRGB2101010:
2611         case DRM_FORMAT_ARGB2101010:
2612                 dspcntr |= DISPPLANE_BGRX101010;
2613                 break;
2614         case DRM_FORMAT_XBGR2101010:
2615         case DRM_FORMAT_ABGR2101010:
2616                 dspcntr |= DISPPLANE_RGBX101010;
2617                 break;
2618         default:
2619                 BUG();
2620         }
2621
2622         if (obj->tiling_mode != I915_TILING_NONE)
2623                 dspcntr |= DISPPLANE_TILED;
2624
2625         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628         linear_offset = y * fb->pitches[0] + x * pixel_size;
2629         intel_crtc->dspaddr_offset =
2630                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631                                                pixel_size,
2632                                                fb->pitches[0]);
2633         linear_offset -= intel_crtc->dspaddr_offset;
2634         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635                 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638                         x += (intel_crtc->config.pipe_src_w - 1);
2639                         y += (intel_crtc->config.pipe_src_h - 1);
2640
2641                         /* Finding the last pixel of the last line of the display
2642                         data and adding to linear_offset*/
2643                         linear_offset +=
2644                                 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645                                 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646                 }
2647         }
2648
2649         I915_WRITE(reg, dspcntr);
2650
2651         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653                       fb->pitches[0]);
2654         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655         I915_WRITE(DSPSURF(plane),
2656                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659         } else {
2660                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662         }
2663         POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667                                          struct drm_framebuffer *fb,
2668                                          int x, int y)
2669 {
2670         struct drm_device *dev = crtc->dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673         struct intel_framebuffer *intel_fb;
2674         struct drm_i915_gem_object *obj;
2675         int pipe = intel_crtc->pipe;
2676         u32 plane_ctl, stride;
2677
2678         if (!intel_crtc->primary_enabled) {
2679                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681                 POSTING_READ(PLANE_CTL(pipe, 0));
2682                 return;
2683         }
2684
2685         plane_ctl = PLANE_CTL_ENABLE |
2686                     PLANE_CTL_PIPE_GAMMA_ENABLE |
2687                     PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689         switch (fb->pixel_format) {
2690         case DRM_FORMAT_RGB565:
2691                 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692                 break;
2693         case DRM_FORMAT_XRGB8888:
2694                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695                 break;
2696         case DRM_FORMAT_XBGR8888:
2697                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699                 break;
2700         case DRM_FORMAT_XRGB2101010:
2701                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702                 break;
2703         case DRM_FORMAT_XBGR2101010:
2704                 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705                 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706                 break;
2707         default:
2708                 BUG();
2709         }
2710
2711         intel_fb = to_intel_framebuffer(fb);
2712         obj = intel_fb->obj;
2713
2714         /*
2715          * The stride is either expressed as a multiple of 64 bytes chunks for
2716          * linear buffers or in number of tiles for tiled buffers.
2717          */
2718         switch (obj->tiling_mode) {
2719         case I915_TILING_NONE:
2720                 stride = fb->pitches[0] >> 6;
2721                 break;
2722         case I915_TILING_X:
2723                 plane_ctl |= PLANE_CTL_TILED_X;
2724                 stride = fb->pitches[0] >> 9;
2725                 break;
2726         default:
2727                 BUG();
2728         }
2729
2730         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731         if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732                 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737                       i915_gem_obj_ggtt_offset(obj),
2738                       x, y, fb->width, fb->height,
2739                       fb->pitches[0]);
2740
2741         I915_WRITE(PLANE_POS(pipe, 0), 0);
2742         I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743         I915_WRITE(PLANE_SIZE(pipe, 0),
2744                    (intel_crtc->config.pipe_src_h - 1) << 16 |
2745                    (intel_crtc->config.pipe_src_w - 1));
2746         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749         POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755                            int x, int y, enum mode_set_atomic state)
2756 {
2757         struct drm_device *dev = crtc->dev;
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760         if (dev_priv->display.disable_fbc)
2761                 dev_priv->display.disable_fbc(dev);
2762
2763         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765         return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771         struct drm_crtc *crtc;
2772
2773         /*
2774          * Flips in the rings have been nuked by the reset,
2775          * so complete all pending flips so that user space
2776          * will get its events and not get stuck.
2777          *
2778          * Also update the base address of all primary
2779          * planes to the the last fb to make sure we're
2780          * showing the correct fb after a reset.
2781          *
2782          * Need to make two loops over the crtcs so that we
2783          * don't try to grab a crtc mutex before the
2784          * pending_flip_queue really got woken up.
2785          */
2786
2787         for_each_crtc(dev, crtc) {
2788                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789                 enum plane plane = intel_crtc->plane;
2790
2791                 intel_prepare_page_flip(dev, plane);
2792                 intel_finish_page_flip_plane(dev, plane);
2793         }
2794
2795         for_each_crtc(dev, crtc) {
2796                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798                 drm_modeset_lock(&crtc->mutex, NULL);
2799                 /*
2800                  * FIXME: Once we have proper support for primary planes (and
2801                  * disabling them without disabling the entire crtc) allow again
2802                  * a NULL crtc->primary->fb.
2803                  */
2804                 if (intel_crtc->active && crtc->primary->fb)
2805                         dev_priv->display.update_primary_plane(crtc,
2806                                                                crtc->primary->fb,
2807                                                                crtc->x,
2808                                                                crtc->y);
2809                 drm_modeset_unlock(&crtc->mutex);
2810         }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818         bool was_interruptible = dev_priv->mm.interruptible;
2819         int ret;
2820
2821         /* Big Hammer, we also need to ensure that any pending
2822          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823          * current scanout is retired before unpinning the old
2824          * framebuffer.
2825          *
2826          * This should only fail upon a hung GPU, in which case we
2827          * can safely continue.
2828          */
2829         dev_priv->mm.interruptible = false;
2830         ret = i915_gem_object_finish_gpu(obj);
2831         dev_priv->mm.interruptible = was_interruptible;
2832
2833         return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841         bool pending;
2842
2843         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845                 return false;
2846
2847         spin_lock_irq(&dev->event_lock);
2848         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849         spin_unlock_irq(&dev->event_lock);
2850
2851         return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->base.dev;
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         const struct drm_display_mode *adjusted_mode;
2859
2860         if (!i915.fastboot)
2861                 return;
2862
2863         /*
2864          * Update pipe size and adjust fitter if needed: the reason for this is
2865          * that in compute_mode_changes we check the native mode (not the pfit
2866          * mode) to see if we can flip rather than do a full mode set. In the
2867          * fastboot case, we'll flip, but if we don't update the pipesrc and
2868          * pfit state, we'll end up with a big fb scanned out into the wrong
2869          * sized surface.
2870          *
2871          * To fix this properly, we need to hoist the checks up into
2872          * compute_mode_changes (or above), check the actual pfit state and
2873          * whether the platform allows pfit disable with pipe active, and only
2874          * then update the pipesrc and pfit state, even on the flip path.
2875          */
2876
2877         adjusted_mode = &crtc->config.adjusted_mode;
2878
2879         I915_WRITE(PIPESRC(crtc->pipe),
2880                    ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881                    (adjusted_mode->crtc_vdisplay - 1));
2882         if (!crtc->config.pch_pfit.enabled &&
2883             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885                 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886                 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887                 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888         }
2889         crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890         crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895                     struct drm_framebuffer *fb)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900         enum pipe pipe = intel_crtc->pipe;
2901         struct drm_framebuffer *old_fb = crtc->primary->fb;
2902         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903         int ret;
2904
2905         if (intel_crtc_has_pending_flip(crtc)) {
2906                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907                 return -EBUSY;
2908         }
2909
2910         /* no fb bound */
2911         if (!fb) {
2912                 DRM_ERROR("No FB bound\n");
2913                 return 0;
2914         }
2915
2916         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918                           plane_name(intel_crtc->plane),
2919                           INTEL_INFO(dev)->num_pipes);
2920                 return -EINVAL;
2921         }
2922
2923         mutex_lock(&dev->struct_mutex);
2924         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925         if (ret == 0)
2926                 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
2928         mutex_unlock(&dev->struct_mutex);
2929         if (ret != 0) {
2930                 DRM_ERROR("pin & fence failed\n");
2931                 return ret;
2932         }
2933
2934         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2935
2936         if (intel_crtc->active)
2937                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2938
2939         crtc->primary->fb = fb;
2940         crtc->x = x;
2941         crtc->y = y;
2942
2943         if (old_fb) {
2944                 if (intel_crtc->active && old_fb != fb)
2945                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2946                 mutex_lock(&dev->struct_mutex);
2947                 intel_unpin_fb_obj(old_obj);
2948                 mutex_unlock(&dev->struct_mutex);
2949         }
2950
2951         mutex_lock(&dev->struct_mutex);
2952         intel_update_fbc(dev);
2953         mutex_unlock(&dev->struct_mutex);
2954
2955         return 0;
2956 }
2957
2958 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2959 {
2960         struct drm_device *dev = crtc->dev;
2961         struct drm_i915_private *dev_priv = dev->dev_private;
2962         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963         int pipe = intel_crtc->pipe;
2964         u32 reg, temp;
2965
2966         /* enable normal train */
2967         reg = FDI_TX_CTL(pipe);
2968         temp = I915_READ(reg);
2969         if (IS_IVYBRIDGE(dev)) {
2970                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2971                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2972         } else {
2973                 temp &= ~FDI_LINK_TRAIN_NONE;
2974                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2975         }
2976         I915_WRITE(reg, temp);
2977
2978         reg = FDI_RX_CTL(pipe);
2979         temp = I915_READ(reg);
2980         if (HAS_PCH_CPT(dev)) {
2981                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2982                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2983         } else {
2984                 temp &= ~FDI_LINK_TRAIN_NONE;
2985                 temp |= FDI_LINK_TRAIN_NONE;
2986         }
2987         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2988
2989         /* wait one idle pattern time */
2990         POSTING_READ(reg);
2991         udelay(1000);
2992
2993         /* IVB wants error correction enabled */
2994         if (IS_IVYBRIDGE(dev))
2995                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2996                            FDI_FE_ERRC_ENABLE);
2997 }
2998
2999 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3000 {
3001         return crtc->base.enabled && crtc->active &&
3002                 crtc->config.has_pch_encoder;
3003 }
3004
3005 static void ivb_modeset_global_resources(struct drm_device *dev)
3006 {
3007         struct drm_i915_private *dev_priv = dev->dev_private;
3008         struct intel_crtc *pipe_B_crtc =
3009                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3010         struct intel_crtc *pipe_C_crtc =
3011                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3012         uint32_t temp;
3013
3014         /*
3015          * When everything is off disable fdi C so that we could enable fdi B
3016          * with all lanes. Note that we don't care about enabled pipes without
3017          * an enabled pch encoder.
3018          */
3019         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3020             !pipe_has_enabled_pch(pipe_C_crtc)) {
3021                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3022                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3023
3024                 temp = I915_READ(SOUTH_CHICKEN1);
3025                 temp &= ~FDI_BC_BIFURCATION_SELECT;
3026                 DRM_DEBUG_KMS("disabling fdi C rx\n");
3027                 I915_WRITE(SOUTH_CHICKEN1, temp);
3028         }
3029 }
3030
3031 /* The FDI link training functions for ILK/Ibexpeak. */
3032 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034         struct drm_device *dev = crtc->dev;
3035         struct drm_i915_private *dev_priv = dev->dev_private;
3036         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037         int pipe = intel_crtc->pipe;
3038         u32 reg, temp, tries;
3039
3040         /* FDI needs bits from pipe first */
3041         assert_pipe_enabled(dev_priv, pipe);
3042
3043         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3044            for train result */
3045         reg = FDI_RX_IMR(pipe);
3046         temp = I915_READ(reg);
3047         temp &= ~FDI_RX_SYMBOL_LOCK;
3048         temp &= ~FDI_RX_BIT_LOCK;
3049         I915_WRITE(reg, temp);
3050         I915_READ(reg);
3051         udelay(150);
3052
3053         /* enable CPU FDI TX and PCH FDI RX */
3054         reg = FDI_TX_CTL(pipe);
3055         temp = I915_READ(reg);
3056         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3057         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3058         temp &= ~FDI_LINK_TRAIN_NONE;
3059         temp |= FDI_LINK_TRAIN_PATTERN_1;
3060         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3061
3062         reg = FDI_RX_CTL(pipe);
3063         temp = I915_READ(reg);
3064         temp &= ~FDI_LINK_TRAIN_NONE;
3065         temp |= FDI_LINK_TRAIN_PATTERN_1;
3066         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3067
3068         POSTING_READ(reg);
3069         udelay(150);
3070
3071         /* Ironlake workaround, enable clock pointer after FDI enable*/
3072         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3073         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3074                    FDI_RX_PHASE_SYNC_POINTER_EN);
3075
3076         reg = FDI_RX_IIR(pipe);
3077         for (tries = 0; tries < 5; tries++) {
3078                 temp = I915_READ(reg);
3079                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3080
3081                 if ((temp & FDI_RX_BIT_LOCK)) {
3082                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3083                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3084                         break;
3085                 }
3086         }
3087         if (tries == 5)
3088                 DRM_ERROR("FDI train 1 fail!\n");
3089
3090         /* Train 2 */
3091         reg = FDI_TX_CTL(pipe);
3092         temp = I915_READ(reg);
3093         temp &= ~FDI_LINK_TRAIN_NONE;
3094         temp |= FDI_LINK_TRAIN_PATTERN_2;
3095         I915_WRITE(reg, temp);
3096
3097         reg = FDI_RX_CTL(pipe);
3098         temp = I915_READ(reg);
3099         temp &= ~FDI_LINK_TRAIN_NONE;
3100         temp |= FDI_LINK_TRAIN_PATTERN_2;
3101         I915_WRITE(reg, temp);
3102
3103         POSTING_READ(reg);
3104         udelay(150);
3105
3106         reg = FDI_RX_IIR(pipe);
3107         for (tries = 0; tries < 5; tries++) {
3108                 temp = I915_READ(reg);
3109                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111                 if (temp & FDI_RX_SYMBOL_LOCK) {
3112                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3113                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3114                         break;
3115                 }
3116         }
3117         if (tries == 5)
3118                 DRM_ERROR("FDI train 2 fail!\n");
3119
3120         DRM_DEBUG_KMS("FDI train done\n");
3121
3122 }
3123
3124 static const int snb_b_fdi_train_param[] = {
3125         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3126         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3127         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3128         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3129 };
3130
3131 /* The FDI link training functions for SNB/Cougarpoint. */
3132 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3133 {
3134         struct drm_device *dev = crtc->dev;
3135         struct drm_i915_private *dev_priv = dev->dev_private;
3136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3137         int pipe = intel_crtc->pipe;
3138         u32 reg, temp, i, retry;
3139
3140         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3141            for train result */
3142         reg = FDI_RX_IMR(pipe);
3143         temp = I915_READ(reg);
3144         temp &= ~FDI_RX_SYMBOL_LOCK;
3145         temp &= ~FDI_RX_BIT_LOCK;
3146         I915_WRITE(reg, temp);
3147
3148         POSTING_READ(reg);
3149         udelay(150);
3150
3151         /* enable CPU FDI TX and PCH FDI RX */
3152         reg = FDI_TX_CTL(pipe);
3153         temp = I915_READ(reg);
3154         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3155         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3156         temp &= ~FDI_LINK_TRAIN_NONE;
3157         temp |= FDI_LINK_TRAIN_PATTERN_1;
3158         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3159         /* SNB-B */
3160         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3161         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3162
3163         I915_WRITE(FDI_RX_MISC(pipe),
3164                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3165
3166         reg = FDI_RX_CTL(pipe);
3167         temp = I915_READ(reg);
3168         if (HAS_PCH_CPT(dev)) {
3169                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3170                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3171         } else {
3172                 temp &= ~FDI_LINK_TRAIN_NONE;
3173                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3174         }
3175         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3176
3177         POSTING_READ(reg);
3178         udelay(150);
3179
3180         for (i = 0; i < 4; i++) {
3181                 reg = FDI_TX_CTL(pipe);
3182                 temp = I915_READ(reg);
3183                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3184                 temp |= snb_b_fdi_train_param[i];
3185                 I915_WRITE(reg, temp);
3186
3187                 POSTING_READ(reg);
3188                 udelay(500);
3189
3190                 for (retry = 0; retry < 5; retry++) {
3191                         reg = FDI_RX_IIR(pipe);
3192                         temp = I915_READ(reg);
3193                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3194                         if (temp & FDI_RX_BIT_LOCK) {
3195                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3196                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3197                                 break;
3198                         }
3199                         udelay(50);
3200                 }
3201                 if (retry < 5)
3202                         break;
3203         }
3204         if (i == 4)
3205                 DRM_ERROR("FDI train 1 fail!\n");
3206
3207         /* Train 2 */
3208         reg = FDI_TX_CTL(pipe);
3209         temp = I915_READ(reg);
3210         temp &= ~FDI_LINK_TRAIN_NONE;
3211         temp |= FDI_LINK_TRAIN_PATTERN_2;
3212         if (IS_GEN6(dev)) {
3213                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214                 /* SNB-B */
3215                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3216         }
3217         I915_WRITE(reg, temp);
3218
3219         reg = FDI_RX_CTL(pipe);
3220         temp = I915_READ(reg);
3221         if (HAS_PCH_CPT(dev)) {
3222                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3223                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3224         } else {
3225                 temp &= ~FDI_LINK_TRAIN_NONE;
3226                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3227         }
3228         I915_WRITE(reg, temp);
3229
3230         POSTING_READ(reg);
3231         udelay(150);
3232
3233         for (i = 0; i < 4; i++) {
3234                 reg = FDI_TX_CTL(pipe);
3235                 temp = I915_READ(reg);
3236                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3237                 temp |= snb_b_fdi_train_param[i];
3238                 I915_WRITE(reg, temp);
3239
3240                 POSTING_READ(reg);
3241                 udelay(500);
3242
3243                 for (retry = 0; retry < 5; retry++) {
3244                         reg = FDI_RX_IIR(pipe);
3245                         temp = I915_READ(reg);
3246                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3247                         if (temp & FDI_RX_SYMBOL_LOCK) {
3248                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3249                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3250                                 break;
3251                         }
3252                         udelay(50);
3253                 }
3254                 if (retry < 5)
3255                         break;
3256         }
3257         if (i == 4)
3258                 DRM_ERROR("FDI train 2 fail!\n");
3259
3260         DRM_DEBUG_KMS("FDI train done.\n");
3261 }
3262
3263 /* Manual link training for Ivy Bridge A0 parts */
3264 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269         int pipe = intel_crtc->pipe;
3270         u32 reg, temp, i, j;
3271
3272         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3273            for train result */
3274         reg = FDI_RX_IMR(pipe);
3275         temp = I915_READ(reg);
3276         temp &= ~FDI_RX_SYMBOL_LOCK;
3277         temp &= ~FDI_RX_BIT_LOCK;
3278         I915_WRITE(reg, temp);
3279
3280         POSTING_READ(reg);
3281         udelay(150);
3282
3283         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3284                       I915_READ(FDI_RX_IIR(pipe)));
3285
3286         /* Try each vswing and preemphasis setting twice before moving on */
3287         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3288                 /* disable first in case we need to retry */
3289                 reg = FDI_TX_CTL(pipe);
3290                 temp = I915_READ(reg);
3291                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3292                 temp &= ~FDI_TX_ENABLE;
3293                 I915_WRITE(reg, temp);
3294
3295                 reg = FDI_RX_CTL(pipe);
3296                 temp = I915_READ(reg);
3297                 temp &= ~FDI_LINK_TRAIN_AUTO;
3298                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3299                 temp &= ~FDI_RX_ENABLE;
3300                 I915_WRITE(reg, temp);
3301
3302                 /* enable CPU FDI TX and PCH FDI RX */
3303                 reg = FDI_TX_CTL(pipe);
3304                 temp = I915_READ(reg);
3305                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3306                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3307                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3308                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3309                 temp |= snb_b_fdi_train_param[j/2];
3310                 temp |= FDI_COMPOSITE_SYNC;
3311                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3312
3313                 I915_WRITE(FDI_RX_MISC(pipe),
3314                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3315
3316                 reg = FDI_RX_CTL(pipe);
3317                 temp = I915_READ(reg);
3318                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3319                 temp |= FDI_COMPOSITE_SYNC;
3320                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3321
3322                 POSTING_READ(reg);
3323                 udelay(1); /* should be 0.5us */
3324
3325                 for (i = 0; i < 4; i++) {
3326                         reg = FDI_RX_IIR(pipe);
3327                         temp = I915_READ(reg);
3328                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330                         if (temp & FDI_RX_BIT_LOCK ||
3331                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3332                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3333                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3334                                               i);
3335                                 break;
3336                         }
3337                         udelay(1); /* should be 0.5us */
3338                 }
3339                 if (i == 4) {
3340                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3341                         continue;
3342                 }
3343
3344                 /* Train 2 */
3345                 reg = FDI_TX_CTL(pipe);
3346                 temp = I915_READ(reg);
3347                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3348                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3349                 I915_WRITE(reg, temp);
3350
3351                 reg = FDI_RX_CTL(pipe);
3352                 temp = I915_READ(reg);
3353                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3354                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3355                 I915_WRITE(reg, temp);
3356
3357                 POSTING_READ(reg);
3358                 udelay(2); /* should be 1.5us */
3359
3360                 for (i = 0; i < 4; i++) {
3361                         reg = FDI_RX_IIR(pipe);
3362                         temp = I915_READ(reg);
3363                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3364
3365                         if (temp & FDI_RX_SYMBOL_LOCK ||
3366                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3367                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3368                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3369                                               i);
3370                                 goto train_done;
3371                         }
3372                         udelay(2); /* should be 1.5us */
3373                 }
3374                 if (i == 4)
3375                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3376         }
3377
3378 train_done:
3379         DRM_DEBUG_KMS("FDI train done.\n");
3380 }
3381
3382 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3383 {
3384         struct drm_device *dev = intel_crtc->base.dev;
3385         struct drm_i915_private *dev_priv = dev->dev_private;
3386         int pipe = intel_crtc->pipe;
3387         u32 reg, temp;
3388
3389
3390         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3391         reg = FDI_RX_CTL(pipe);
3392         temp = I915_READ(reg);
3393         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3394         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3395         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3396         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3397
3398         POSTING_READ(reg);
3399         udelay(200);
3400
3401         /* Switch from Rawclk to PCDclk */
3402         temp = I915_READ(reg);
3403         I915_WRITE(reg, temp | FDI_PCDCLK);
3404
3405         POSTING_READ(reg);
3406         udelay(200);
3407
3408         /* Enable CPU FDI TX PLL, always on for Ironlake */
3409         reg = FDI_TX_CTL(pipe);
3410         temp = I915_READ(reg);
3411         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3412                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3413
3414                 POSTING_READ(reg);
3415                 udelay(100);
3416         }
3417 }
3418
3419 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3420 {
3421         struct drm_device *dev = intel_crtc->base.dev;
3422         struct drm_i915_private *dev_priv = dev->dev_private;
3423         int pipe = intel_crtc->pipe;
3424         u32 reg, temp;
3425
3426         /* Switch from PCDclk to Rawclk */
3427         reg = FDI_RX_CTL(pipe);
3428         temp = I915_READ(reg);
3429         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3430
3431         /* Disable CPU FDI TX PLL */
3432         reg = FDI_TX_CTL(pipe);
3433         temp = I915_READ(reg);
3434         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3435
3436         POSTING_READ(reg);
3437         udelay(100);
3438
3439         reg = FDI_RX_CTL(pipe);
3440         temp = I915_READ(reg);
3441         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3442
3443         /* Wait for the clocks to turn off. */
3444         POSTING_READ(reg);
3445         udelay(100);
3446 }
3447
3448 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3449 {
3450         struct drm_device *dev = crtc->dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3453         int pipe = intel_crtc->pipe;
3454         u32 reg, temp;
3455
3456         /* disable CPU FDI tx and PCH FDI rx */
3457         reg = FDI_TX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3460         POSTING_READ(reg);
3461
3462         reg = FDI_RX_CTL(pipe);
3463         temp = I915_READ(reg);
3464         temp &= ~(0x7 << 16);
3465         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3466         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3467
3468         POSTING_READ(reg);
3469         udelay(100);
3470
3471         /* Ironlake workaround, disable clock pointer after downing FDI */
3472         if (HAS_PCH_IBX(dev))
3473                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3474
3475         /* still set train pattern 1 */
3476         reg = FDI_TX_CTL(pipe);
3477         temp = I915_READ(reg);
3478         temp &= ~FDI_LINK_TRAIN_NONE;
3479         temp |= FDI_LINK_TRAIN_PATTERN_1;
3480         I915_WRITE(reg, temp);
3481
3482         reg = FDI_RX_CTL(pipe);
3483         temp = I915_READ(reg);
3484         if (HAS_PCH_CPT(dev)) {
3485                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3486                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3487         } else {
3488                 temp &= ~FDI_LINK_TRAIN_NONE;
3489                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3490         }
3491         /* BPC in FDI rx is consistent with that in PIPECONF */
3492         temp &= ~(0x07 << 16);
3493         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3494         I915_WRITE(reg, temp);
3495
3496         POSTING_READ(reg);
3497         udelay(100);
3498 }
3499
3500 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3501 {
3502         struct intel_crtc *crtc;
3503
3504         /* Note that we don't need to be called with mode_config.lock here
3505          * as our list of CRTC objects is static for the lifetime of the
3506          * device and so cannot disappear as we iterate. Similarly, we can
3507          * happily treat the predicates as racy, atomic checks as userspace
3508          * cannot claim and pin a new fb without at least acquring the
3509          * struct_mutex and so serialising with us.
3510          */
3511         for_each_intel_crtc(dev, crtc) {
3512                 if (atomic_read(&crtc->unpin_work_count) == 0)
3513                         continue;
3514
3515                 if (crtc->unpin_work)
3516                         intel_wait_for_vblank(dev, crtc->pipe);
3517
3518                 return true;
3519         }
3520
3521         return false;
3522 }
3523
3524 static void page_flip_completed(struct intel_crtc *intel_crtc)
3525 {
3526         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3527         struct intel_unpin_work *work = intel_crtc->unpin_work;
3528
3529         /* ensure that the unpin work is consistent wrt ->pending. */
3530         smp_rmb();
3531         intel_crtc->unpin_work = NULL;
3532
3533         if (work->event)
3534                 drm_send_vblank_event(intel_crtc->base.dev,
3535                                       intel_crtc->pipe,
3536                                       work->event);
3537
3538         drm_crtc_vblank_put(&intel_crtc->base);
3539
3540         wake_up_all(&dev_priv->pending_flip_queue);
3541         queue_work(dev_priv->wq, &work->work);
3542
3543         trace_i915_flip_complete(intel_crtc->plane,
3544                                  work->pending_flip_obj);
3545 }
3546
3547 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3548 {
3549         struct drm_device *dev = crtc->dev;
3550         struct drm_i915_private *dev_priv = dev->dev_private;
3551
3552         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3553         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3554                                        !intel_crtc_has_pending_flip(crtc),
3555                                        60*HZ) == 0)) {
3556                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3557
3558                 spin_lock_irq(&dev->event_lock);
3559                 if (intel_crtc->unpin_work) {
3560                         WARN_ONCE(1, "Removing stuck page flip\n");
3561                         page_flip_completed(intel_crtc);
3562                 }
3563                 spin_unlock_irq(&dev->event_lock);
3564         }
3565
3566         if (crtc->primary->fb) {
3567                 mutex_lock(&dev->struct_mutex);
3568                 intel_finish_fb(crtc->primary->fb);
3569                 mutex_unlock(&dev->struct_mutex);
3570         }
3571 }
3572
3573 /* Program iCLKIP clock to the desired frequency */
3574 static void lpt_program_iclkip(struct drm_crtc *crtc)
3575 {
3576         struct drm_device *dev = crtc->dev;
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3579         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3580         u32 temp;
3581
3582         mutex_lock(&dev_priv->dpio_lock);
3583
3584         /* It is necessary to ungate the pixclk gate prior to programming
3585          * the divisors, and gate it back when it is done.
3586          */
3587         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3588
3589         /* Disable SSCCTL */
3590         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3591                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3592                                 SBI_SSCCTL_DISABLE,
3593                         SBI_ICLK);
3594
3595         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3596         if (clock == 20000) {
3597                 auxdiv = 1;
3598                 divsel = 0x41;
3599                 phaseinc = 0x20;
3600         } else {
3601                 /* The iCLK virtual clock root frequency is in MHz,
3602                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3603                  * divisors, it is necessary to divide one by another, so we
3604                  * convert the virtual clock precision to KHz here for higher
3605                  * precision.
3606                  */
3607                 u32 iclk_virtual_root_freq = 172800 * 1000;
3608                 u32 iclk_pi_range = 64;
3609                 u32 desired_divisor, msb_divisor_value, pi_value;
3610
3611                 desired_divisor = (iclk_virtual_root_freq / clock);
3612                 msb_divisor_value = desired_divisor / iclk_pi_range;
3613                 pi_value = desired_divisor % iclk_pi_range;
3614
3615                 auxdiv = 0;
3616                 divsel = msb_divisor_value - 2;
3617                 phaseinc = pi_value;
3618         }
3619
3620         /* This should not happen with any sane values */
3621         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3622                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3623         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3624                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3625
3626         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3627                         clock,
3628                         auxdiv,
3629                         divsel,
3630                         phasedir,
3631                         phaseinc);
3632
3633         /* Program SSCDIVINTPHASE6 */
3634         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3635         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3636         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3637         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3638         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3639         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3640         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3641         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3642
3643         /* Program SSCAUXDIV */
3644         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3645         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3646         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3647         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3648
3649         /* Enable modulator and associated divider */
3650         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3651         temp &= ~SBI_SSCCTL_DISABLE;
3652         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3653
3654         /* Wait for initialization time */
3655         udelay(24);
3656
3657         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3658
3659         mutex_unlock(&dev_priv->dpio_lock);
3660 }
3661
3662 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3663                                                 enum pipe pch_transcoder)
3664 {
3665         struct drm_device *dev = crtc->base.dev;
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3668
3669         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3670                    I915_READ(HTOTAL(cpu_transcoder)));
3671         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3672                    I915_READ(HBLANK(cpu_transcoder)));
3673         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3674                    I915_READ(HSYNC(cpu_transcoder)));
3675
3676         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3677                    I915_READ(VTOTAL(cpu_transcoder)));
3678         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3679                    I915_READ(VBLANK(cpu_transcoder)));
3680         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3681                    I915_READ(VSYNC(cpu_transcoder)));
3682         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3683                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3684 }
3685
3686 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3687 {
3688         struct drm_i915_private *dev_priv = dev->dev_private;
3689         uint32_t temp;
3690
3691         temp = I915_READ(SOUTH_CHICKEN1);
3692         if (temp & FDI_BC_BIFURCATION_SELECT)
3693                 return;
3694
3695         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3696         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3697
3698         temp |= FDI_BC_BIFURCATION_SELECT;
3699         DRM_DEBUG_KMS("enabling fdi C rx\n");
3700         I915_WRITE(SOUTH_CHICKEN1, temp);
3701         POSTING_READ(SOUTH_CHICKEN1);
3702 }
3703
3704 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3705 {
3706         struct drm_device *dev = intel_crtc->base.dev;
3707         struct drm_i915_private *dev_priv = dev->dev_private;
3708
3709         switch (intel_crtc->pipe) {
3710         case PIPE_A:
3711                 break;
3712         case PIPE_B:
3713                 if (intel_crtc->config.fdi_lanes > 2)
3714                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3715                 else
3716                         cpt_enable_fdi_bc_bifurcation(dev);
3717
3718                 break;
3719         case PIPE_C:
3720                 cpt_enable_fdi_bc_bifurcation(dev);
3721
3722                 break;
3723         default:
3724                 BUG();
3725         }
3726 }
3727
3728 /*
3729  * Enable PCH resources required for PCH ports:
3730  *   - PCH PLLs
3731  *   - FDI training & RX/TX
3732  *   - update transcoder timings
3733  *   - DP transcoding bits
3734  *   - transcoder
3735  */
3736 static void ironlake_pch_enable(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_i915_private *dev_priv = dev->dev_private;
3740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741         int pipe = intel_crtc->pipe;
3742         u32 reg, temp;
3743
3744         assert_pch_transcoder_disabled(dev_priv, pipe);
3745
3746         if (IS_IVYBRIDGE(dev))
3747                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3748
3749         /* Write the TU size bits before fdi link training, so that error
3750          * detection works. */
3751         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3752                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3753
3754         /* For PCH output, training FDI link */
3755         dev_priv->display.fdi_link_train(crtc);
3756
3757         /* We need to program the right clock selection before writing the pixel
3758          * mutliplier into the DPLL. */
3759         if (HAS_PCH_CPT(dev)) {
3760                 u32 sel;
3761
3762                 temp = I915_READ(PCH_DPLL_SEL);
3763                 temp |= TRANS_DPLL_ENABLE(pipe);
3764                 sel = TRANS_DPLLB_SEL(pipe);
3765                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3766                         temp |= sel;
3767                 else
3768                         temp &= ~sel;
3769                 I915_WRITE(PCH_DPLL_SEL, temp);
3770         }
3771
3772         /* XXX: pch pll's can be enabled any time before we enable the PCH
3773          * transcoder, and we actually should do this to not upset any PCH
3774          * transcoder that already use the clock when we share it.
3775          *
3776          * Note that enable_shared_dpll tries to do the right thing, but
3777          * get_shared_dpll unconditionally resets the pll - we need that to have
3778          * the right LVDS enable sequence. */
3779         intel_enable_shared_dpll(intel_crtc);
3780
3781         /* set transcoder timing, panel must allow it */
3782         assert_panel_unlocked(dev_priv, pipe);
3783         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3784
3785         intel_fdi_normal_train(crtc);
3786
3787         /* For PCH DP, enable TRANS_DP_CTL */
3788         if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3789                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3790                 reg = TRANS_DP_CTL(pipe);
3791                 temp = I915_READ(reg);
3792                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3793                           TRANS_DP_SYNC_MASK |
3794                           TRANS_DP_BPC_MASK);
3795                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3796                          TRANS_DP_ENH_FRAMING);
3797                 temp |= bpc << 9; /* same format but at 11:9 */
3798
3799                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3800                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3801                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3802                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3803
3804                 switch (intel_trans_dp_port_sel(crtc)) {
3805                 case PCH_DP_B:
3806                         temp |= TRANS_DP_PORT_SEL_B;
3807                         break;
3808                 case PCH_DP_C:
3809                         temp |= TRANS_DP_PORT_SEL_C;
3810                         break;
3811                 case PCH_DP_D:
3812                         temp |= TRANS_DP_PORT_SEL_D;
3813                         break;
3814                 default:
3815                         BUG();
3816                 }
3817
3818                 I915_WRITE(reg, temp);
3819         }
3820
3821         ironlake_enable_pch_transcoder(dev_priv, pipe);
3822 }
3823
3824 static void lpt_pch_enable(struct drm_crtc *crtc)
3825 {
3826         struct drm_device *dev = crtc->dev;
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3829         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3830
3831         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3832
3833         lpt_program_iclkip(crtc);
3834
3835         /* Set transcoder timing. */
3836         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3837
3838         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3839 }
3840
3841 void intel_put_shared_dpll(struct intel_crtc *crtc)
3842 {
3843         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3844
3845         if (pll == NULL)
3846                 return;
3847
3848         if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3849                 WARN(1, "bad %s crtc mask\n", pll->name);
3850                 return;
3851         }
3852
3853         pll->config.crtc_mask &= ~(1 << crtc->pipe);
3854         if (pll->config.crtc_mask == 0) {
3855                 WARN_ON(pll->on);
3856                 WARN_ON(pll->active);
3857         }
3858
3859         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3860 }
3861
3862 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3863 {
3864         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3865         struct intel_shared_dpll *pll;
3866         enum intel_dpll_id i;
3867
3868         if (HAS_PCH_IBX(dev_priv->dev)) {
3869                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3870                 i = (enum intel_dpll_id) crtc->pipe;
3871                 pll = &dev_priv->shared_dplls[i];
3872
3873                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3874                               crtc->base.base.id, pll->name);
3875
3876                 WARN_ON(pll->new_config->crtc_mask);
3877
3878                 goto found;
3879         }
3880
3881         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3882                 pll = &dev_priv->shared_dplls[i];
3883
3884                 /* Only want to check enabled timings first */
3885                 if (pll->new_config->crtc_mask == 0)
3886                         continue;
3887
3888                 if (memcmp(&crtc->new_config->dpll_hw_state,
3889                            &pll->new_config->hw_state,
3890                            sizeof(pll->new_config->hw_state)) == 0) {
3891                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3892                                       crtc->base.base.id, pll->name,
3893                                       pll->new_config->crtc_mask,
3894                                       pll->active);
3895                         goto found;
3896                 }
3897         }
3898
3899         /* Ok no matching timings, maybe there's a free one? */
3900         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3901                 pll = &dev_priv->shared_dplls[i];
3902                 if (pll->new_config->crtc_mask == 0) {
3903                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3904                                       crtc->base.base.id, pll->name);
3905                         goto found;
3906                 }
3907         }
3908
3909         return NULL;
3910
3911 found:
3912         if (pll->new_config->crtc_mask == 0)
3913                 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3914
3915         crtc->new_config->shared_dpll = i;
3916         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3917                          pipe_name(crtc->pipe));
3918
3919         pll->new_config->crtc_mask |= 1 << crtc->pipe;
3920
3921         return pll;
3922 }
3923
3924 /**
3925  * intel_shared_dpll_start_config - start a new PLL staged config
3926  * @dev_priv: DRM device
3927  * @clear_pipes: mask of pipes that will have their PLLs freed
3928  *
3929  * Starts a new PLL staged config, copying the current config but
3930  * releasing the references of pipes specified in clear_pipes.
3931  */
3932 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3933                                           unsigned clear_pipes)
3934 {
3935         struct intel_shared_dpll *pll;
3936         enum intel_dpll_id i;
3937
3938         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3939                 pll = &dev_priv->shared_dplls[i];
3940
3941                 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3942                                           GFP_KERNEL);
3943                 if (!pll->new_config)
3944                         goto cleanup;
3945
3946                 pll->new_config->crtc_mask &= ~clear_pipes;
3947         }
3948
3949         return 0;
3950
3951 cleanup:
3952         while (--i >= 0) {
3953                 pll = &dev_priv->shared_dplls[i];
3954                 kfree(pll->new_config);
3955                 pll->new_config = NULL;
3956         }
3957
3958         return -ENOMEM;
3959 }
3960
3961 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3962 {
3963         struct intel_shared_dpll *pll;
3964         enum intel_dpll_id i;
3965
3966         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3967                 pll = &dev_priv->shared_dplls[i];
3968
3969                 WARN_ON(pll->new_config == &pll->config);
3970
3971                 pll->config = *pll->new_config;
3972                 kfree(pll->new_config);
3973                 pll->new_config = NULL;
3974         }
3975 }
3976
3977 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3978 {
3979         struct intel_shared_dpll *pll;
3980         enum intel_dpll_id i;
3981
3982         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3983                 pll = &dev_priv->shared_dplls[i];
3984
3985                 WARN_ON(pll->new_config == &pll->config);
3986
3987                 kfree(pll->new_config);
3988                 pll->new_config = NULL;
3989         }
3990 }
3991
3992 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3993 {
3994         struct drm_i915_private *dev_priv = dev->dev_private;
3995         int dslreg = PIPEDSL(pipe);
3996         u32 temp;
3997
3998         temp = I915_READ(dslreg);
3999         udelay(500);
4000         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4001                 if (wait_for(I915_READ(dslreg) != temp, 5))
4002                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4003         }
4004 }
4005
4006 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4007 {
4008         struct drm_device *dev = crtc->base.dev;
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         int pipe = crtc->pipe;
4011
4012         if (crtc->config.pch_pfit.enabled) {
4013                 /* Force use of hard-coded filter coefficients
4014                  * as some pre-programmed values are broken,
4015                  * e.g. x201.
4016                  */
4017                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4018                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4019                                                  PF_PIPE_SEL_IVB(pipe));
4020                 else
4021                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4022                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4023                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4024         }
4025 }
4026
4027 static void intel_enable_planes(struct drm_crtc *crtc)
4028 {
4029         struct drm_device *dev = crtc->dev;
4030         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4031         struct drm_plane *plane;
4032         struct intel_plane *intel_plane;
4033
4034         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4035                 intel_plane = to_intel_plane(plane);
4036                 if (intel_plane->pipe == pipe)
4037                         intel_plane_restore(&intel_plane->base);
4038         }
4039 }
4040
4041 static void intel_disable_planes(struct drm_crtc *crtc)
4042 {
4043         struct drm_device *dev = crtc->dev;
4044         enum pipe pipe = to_intel_crtc(crtc)->pipe;
4045         struct drm_plane *plane;
4046         struct intel_plane *intel_plane;
4047
4048         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4049                 intel_plane = to_intel_plane(plane);
4050                 if (intel_plane->pipe == pipe)
4051                         intel_plane_disable(&intel_plane->base);
4052         }
4053 }
4054
4055 void hsw_enable_ips(struct intel_crtc *crtc)
4056 {
4057         struct drm_device *dev = crtc->base.dev;
4058         struct drm_i915_private *dev_priv = dev->dev_private;
4059
4060         if (!crtc->config.ips_enabled)
4061                 return;
4062
4063         /* We can only enable IPS after we enable a plane and wait for a vblank */
4064         intel_wait_for_vblank(dev, crtc->pipe);
4065
4066         assert_plane_enabled(dev_priv, crtc->plane);
4067         if (IS_BROADWELL(dev)) {
4068                 mutex_lock(&dev_priv->rps.hw_lock);
4069                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4070                 mutex_unlock(&dev_priv->rps.hw_lock);
4071                 /* Quoting Art Runyan: "its not safe to expect any particular
4072                  * value in IPS_CTL bit 31 after enabling IPS through the
4073                  * mailbox." Moreover, the mailbox may return a bogus state,
4074                  * so we need to just enable it and continue on.
4075                  */
4076         } else {
4077                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4078                 /* The bit only becomes 1 in the next vblank, so this wait here
4079                  * is essentially intel_wait_for_vblank. If we don't have this
4080                  * and don't wait for vblanks until the end of crtc_enable, then
4081                  * the HW state readout code will complain that the expected
4082                  * IPS_CTL value is not the one we read. */
4083                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4084                         DRM_ERROR("Timed out waiting for IPS enable\n");
4085         }
4086 }
4087
4088 void hsw_disable_ips(struct intel_crtc *crtc)
4089 {
4090         struct drm_device *dev = crtc->base.dev;
4091         struct drm_i915_private *dev_priv = dev->dev_private;
4092
4093         if (!crtc->config.ips_enabled)
4094                 return;
4095
4096         assert_plane_enabled(dev_priv, crtc->plane);
4097         if (IS_BROADWELL(dev)) {
4098                 mutex_lock(&dev_priv->rps.hw_lock);
4099                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4100                 mutex_unlock(&dev_priv->rps.hw_lock);
4101                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4102                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4103                         DRM_ERROR("Timed out waiting for IPS disable\n");
4104         } else {
4105                 I915_WRITE(IPS_CTL, 0);
4106                 POSTING_READ(IPS_CTL);
4107         }
4108
4109         /* We need to wait for a vblank before we can disable the plane. */
4110         intel_wait_for_vblank(dev, crtc->pipe);
4111 }
4112
4113 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4114 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4115 {
4116         struct drm_device *dev = crtc->dev;
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4119         enum pipe pipe = intel_crtc->pipe;
4120         int palreg = PALETTE(pipe);
4121         int i;
4122         bool reenable_ips = false;
4123
4124         /* The clocks have to be on to load the palette. */
4125         if (!crtc->enabled || !intel_crtc->active)
4126                 return;
4127
4128         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4129                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4130                         assert_dsi_pll_enabled(dev_priv);
4131                 else
4132                         assert_pll_enabled(dev_priv, pipe);
4133         }
4134
4135         /* use legacy palette for Ironlake */
4136         if (!HAS_GMCH_DISPLAY(dev))
4137                 palreg = LGC_PALETTE(pipe);
4138
4139         /* Workaround : Do not read or write the pipe palette/gamma data while
4140          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4141          */
4142         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4143             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4144              GAMMA_MODE_MODE_SPLIT)) {
4145                 hsw_disable_ips(intel_crtc);
4146                 reenable_ips = true;
4147         }
4148
4149         for (i = 0; i < 256; i++) {
4150                 I915_WRITE(palreg + 4 * i,
4151                            (intel_crtc->lut_r[i] << 16) |
4152                            (intel_crtc->lut_g[i] << 8) |
4153                            intel_crtc->lut_b[i]);
4154         }
4155
4156         if (reenable_ips)
4157                 hsw_enable_ips(intel_crtc);
4158 }
4159
4160 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4161 {
4162         if (!enable && intel_crtc->overlay) {
4163                 struct drm_device *dev = intel_crtc->base.dev;
4164                 struct drm_i915_private *dev_priv = dev->dev_private;
4165
4166                 mutex_lock(&dev->struct_mutex);
4167                 dev_priv->mm.interruptible = false;
4168                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4169                 dev_priv->mm.interruptible = true;
4170                 mutex_unlock(&dev->struct_mutex);
4171         }
4172
4173         /* Let userspace switch the overlay on again. In most cases userspace
4174          * has to recompute where to put it anyway.
4175          */
4176 }
4177
4178 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4179 {
4180         struct drm_device *dev = crtc->dev;
4181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182         int pipe = intel_crtc->pipe;
4183
4184         intel_enable_primary_hw_plane(crtc->primary, crtc);
4185         intel_enable_planes(crtc);
4186         intel_crtc_update_cursor(crtc, true);
4187         intel_crtc_dpms_overlay(intel_crtc, true);
4188
4189         hsw_enable_ips(intel_crtc);
4190
4191         mutex_lock(&dev->struct_mutex);
4192         intel_update_fbc(dev);
4193         mutex_unlock(&dev->struct_mutex);
4194
4195         /*
4196          * FIXME: Once we grow proper nuclear flip support out of this we need
4197          * to compute the mask of flip planes precisely. For the time being
4198          * consider this a flip from a NULL plane.
4199          */
4200         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4201 }
4202
4203 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208         int pipe = intel_crtc->pipe;
4209         int plane = intel_crtc->plane;
4210
4211         intel_crtc_wait_for_pending_flips(crtc);
4212
4213         if (dev_priv->fbc.plane == plane)
4214                 intel_disable_fbc(dev);
4215
4216         hsw_disable_ips(intel_crtc);
4217
4218         intel_crtc_dpms_overlay(intel_crtc, false);
4219         intel_crtc_update_cursor(crtc, false);
4220         intel_disable_planes(crtc);
4221         intel_disable_primary_hw_plane(crtc->primary, crtc);
4222
4223         /*
4224          * FIXME: Once we grow proper nuclear flip support out of this we need
4225          * to compute the mask of flip planes precisely. For the time being
4226          * consider this a flip to a NULL plane.
4227          */
4228         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4229 }
4230
4231 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4232 {
4233         struct drm_device *dev = crtc->dev;
4234         struct drm_i915_private *dev_priv = dev->dev_private;
4235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236         struct intel_encoder *encoder;
4237         int pipe = intel_crtc->pipe;
4238
4239         WARN_ON(!crtc->enabled);
4240
4241         if (intel_crtc->active)
4242                 return;
4243
4244         if (intel_crtc->config.has_pch_encoder)
4245                 intel_prepare_shared_dpll(intel_crtc);
4246
4247         if (intel_crtc->config.has_dp_encoder)
4248                 intel_dp_set_m_n(intel_crtc);
4249
4250         intel_set_pipe_timings(intel_crtc);
4251
4252         if (intel_crtc->config.has_pch_encoder) {
4253                 intel_cpu_transcoder_set_m_n(intel_crtc,
4254                                      &intel_crtc->config.fdi_m_n, NULL);
4255         }
4256
4257         ironlake_set_pipeconf(crtc);
4258
4259         intel_crtc->active = true;
4260
4261         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4262         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4263
4264         for_each_encoder_on_crtc(dev, crtc, encoder)
4265                 if (encoder->pre_enable)
4266                         encoder->pre_enable(encoder);
4267
4268         if (intel_crtc->config.has_pch_encoder) {
4269                 /* Note: FDI PLL enabling _must_ be done before we enable the
4270                  * cpu pipes, hence this is separate from all the other fdi/pch
4271                  * enabling. */
4272                 ironlake_fdi_pll_enable(intel_crtc);
4273         } else {
4274                 assert_fdi_tx_disabled(dev_priv, pipe);
4275                 assert_fdi_rx_disabled(dev_priv, pipe);
4276         }
4277
4278         ironlake_pfit_enable(intel_crtc);
4279
4280         /*
4281          * On ILK+ LUT must be loaded before the pipe is running but with
4282          * clocks enabled
4283          */
4284         intel_crtc_load_lut(crtc);
4285
4286         intel_update_watermarks(crtc);
4287         intel_enable_pipe(intel_crtc);
4288
4289         if (intel_crtc->config.has_pch_encoder)
4290                 ironlake_pch_enable(crtc);
4291
4292         for_each_encoder_on_crtc(dev, crtc, encoder)
4293                 encoder->enable(encoder);
4294
4295         if (HAS_PCH_CPT(dev))
4296                 cpt_verify_modeset(dev, intel_crtc->pipe);
4297
4298         assert_vblank_disabled(crtc);
4299         drm_crtc_vblank_on(crtc);
4300
4301         intel_crtc_enable_planes(crtc);
4302 }
4303
4304 /* IPS only exists on ULT machines and is tied to pipe A. */
4305 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4306 {
4307         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4308 }
4309
4310 /*
4311  * This implements the workaround described in the "notes" section of the mode
4312  * set sequence documentation. When going from no pipes or single pipe to
4313  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4314  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4315  */
4316 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4317 {
4318         struct drm_device *dev = crtc->base.dev;
4319         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4320
4321         /* We want to get the other_active_crtc only if there's only 1 other
4322          * active crtc. */
4323         for_each_intel_crtc(dev, crtc_it) {
4324                 if (!crtc_it->active || crtc_it == crtc)
4325                         continue;
4326
4327                 if (other_active_crtc)
4328                         return;
4329
4330                 other_active_crtc = crtc_it;
4331         }
4332         if (!other_active_crtc)
4333                 return;
4334
4335         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4336         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337 }
4338
4339 static void haswell_crtc_enable(struct drm_crtc *crtc)
4340 {
4341         struct drm_device *dev = crtc->dev;
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4344         struct intel_encoder *encoder;
4345         int pipe = intel_crtc->pipe;
4346
4347         WARN_ON(!crtc->enabled);
4348
4349         if (intel_crtc->active)
4350                 return;
4351
4352         if (intel_crtc_to_shared_dpll(intel_crtc))
4353                 intel_enable_shared_dpll(intel_crtc);
4354
4355         if (intel_crtc->config.has_dp_encoder)
4356                 intel_dp_set_m_n(intel_crtc);
4357
4358         intel_set_pipe_timings(intel_crtc);
4359
4360         if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4361                 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4362                            intel_crtc->config.pixel_multiplier - 1);
4363         }
4364
4365         if (intel_crtc->config.has_pch_encoder) {
4366                 intel_cpu_transcoder_set_m_n(intel_crtc,
4367                                      &intel_crtc->config.fdi_m_n, NULL);
4368         }
4369
4370         haswell_set_pipeconf(crtc);
4371
4372         intel_set_pipe_csc(crtc);
4373
4374         intel_crtc->active = true;
4375
4376         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4377         for_each_encoder_on_crtc(dev, crtc, encoder)
4378                 if (encoder->pre_enable)
4379                         encoder->pre_enable(encoder);
4380
4381         if (intel_crtc->config.has_pch_encoder) {
4382                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4383                                                       true);
4384                 dev_priv->display.fdi_link_train(crtc);
4385         }
4386
4387         intel_ddi_enable_pipe_clock(intel_crtc);
4388
4389         ironlake_pfit_enable(intel_crtc);
4390
4391         /*
4392          * On ILK+ LUT must be loaded before the pipe is running but with
4393          * clocks enabled
4394          */
4395         intel_crtc_load_lut(crtc);
4396
4397         intel_ddi_set_pipe_settings(crtc);
4398         intel_ddi_enable_transcoder_func(crtc);
4399
4400         intel_update_watermarks(crtc);
4401         intel_enable_pipe(intel_crtc);
4402
4403         if (intel_crtc->config.has_pch_encoder)
4404                 lpt_pch_enable(crtc);
4405
4406         if (intel_crtc->config.dp_encoder_is_mst)
4407                 intel_ddi_set_vc_payload_alloc(crtc, true);
4408
4409         for_each_encoder_on_crtc(dev, crtc, encoder) {
4410                 encoder->enable(encoder);
4411                 intel_opregion_notify_encoder(encoder, true);
4412         }
4413
4414         assert_vblank_disabled(crtc);
4415         drm_crtc_vblank_on(crtc);
4416
4417         /* If we change the relative order between pipe/planes enabling, we need
4418          * to change the workaround. */
4419         haswell_mode_set_planes_workaround(intel_crtc);
4420         intel_crtc_enable_planes(crtc);
4421 }
4422
4423 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4424 {
4425         struct drm_device *dev = crtc->base.dev;
4426         struct drm_i915_private *dev_priv = dev->dev_private;
4427         int pipe = crtc->pipe;
4428
4429         /* To avoid upsetting the power well on haswell only disable the pfit if
4430          * it's in use. The hw state code will make sure we get this right. */
4431         if (crtc->config.pch_pfit.enabled) {
4432                 I915_WRITE(PF_CTL(pipe), 0);
4433                 I915_WRITE(PF_WIN_POS(pipe), 0);
4434                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4435         }
4436 }
4437
4438 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4439 {
4440         struct drm_device *dev = crtc->dev;
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4443         struct intel_encoder *encoder;
4444         int pipe = intel_crtc->pipe;
4445         u32 reg, temp;
4446
4447         if (!intel_crtc->active)
4448                 return;
4449
4450         intel_crtc_disable_planes(crtc);
4451
4452         drm_crtc_vblank_off(crtc);
4453         assert_vblank_disabled(crtc);
4454
4455         for_each_encoder_on_crtc(dev, crtc, encoder)
4456                 encoder->disable(encoder);
4457
4458         if (intel_crtc->config.has_pch_encoder)
4459                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4460
4461         intel_disable_pipe(intel_crtc);
4462
4463         ironlake_pfit_disable(intel_crtc);
4464
4465         for_each_encoder_on_crtc(dev, crtc, encoder)
4466                 if (encoder->post_disable)
4467                         encoder->post_disable(encoder);
4468
4469         if (intel_crtc->config.has_pch_encoder) {
4470                 ironlake_fdi_disable(crtc);
4471
4472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4473                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4474
4475                 if (HAS_PCH_CPT(dev)) {
4476                         /* disable TRANS_DP_CTL */
4477                         reg = TRANS_DP_CTL(pipe);
4478                         temp = I915_READ(reg);
4479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4480                                   TRANS_DP_PORT_SEL_MASK);
4481                         temp |= TRANS_DP_PORT_SEL_NONE;
4482                         I915_WRITE(reg, temp);
4483
4484                         /* disable DPLL_SEL */
4485                         temp = I915_READ(PCH_DPLL_SEL);
4486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4487                         I915_WRITE(PCH_DPLL_SEL, temp);
4488                 }
4489
4490                 /* disable PCH DPLL */
4491                 intel_disable_shared_dpll(intel_crtc);
4492
4493                 ironlake_fdi_pll_disable(intel_crtc);
4494         }
4495
4496         intel_crtc->active = false;
4497         intel_update_watermarks(crtc);
4498
4499         mutex_lock(&dev->struct_mutex);
4500         intel_update_fbc(dev);
4501         mutex_unlock(&dev->struct_mutex);
4502 }
4503
4504 static void haswell_crtc_disable(struct drm_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509         struct intel_encoder *encoder;
4510         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4511
4512         if (!intel_crtc->active)
4513                 return;
4514
4515         intel_crtc_disable_planes(crtc);
4516
4517         drm_crtc_vblank_off(crtc);
4518         assert_vblank_disabled(crtc);
4519
4520         for_each_encoder_on_crtc(dev, crtc, encoder) {
4521                 intel_opregion_notify_encoder(encoder, false);
4522                 encoder->disable(encoder);
4523         }
4524
4525         if (intel_crtc->config.has_pch_encoder)
4526                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4527                                                       false);
4528         intel_disable_pipe(intel_crtc);
4529
4530         if (intel_crtc->config.dp_encoder_is_mst)
4531                 intel_ddi_set_vc_payload_alloc(crtc, false);
4532
4533         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4534
4535         ironlake_pfit_disable(intel_crtc);
4536
4537         intel_ddi_disable_pipe_clock(intel_crtc);
4538
4539         if (intel_crtc->config.has_pch_encoder) {
4540                 lpt_disable_pch_transcoder(dev_priv);
4541                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4542                                                       true);
4543                 intel_ddi_fdi_disable(crtc);
4544         }
4545
4546         for_each_encoder_on_crtc(dev, crtc, encoder)
4547                 if (encoder->post_disable)
4548                         encoder->post_disable(encoder);
4549
4550         intel_crtc->active = false;
4551         intel_update_watermarks(crtc);
4552
4553         mutex_lock(&dev->struct_mutex);
4554         intel_update_fbc(dev);
4555         mutex_unlock(&dev->struct_mutex);
4556
4557         if (intel_crtc_to_shared_dpll(intel_crtc))
4558                 intel_disable_shared_dpll(intel_crtc);
4559 }
4560
4561 static void ironlake_crtc_off(struct drm_crtc *crtc)
4562 {
4563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4564         intel_put_shared_dpll(intel_crtc);
4565 }
4566
4567
4568 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4569 {
4570         struct drm_device *dev = crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572         struct intel_crtc_config *pipe_config = &crtc->config;
4573
4574         if (!crtc->config.gmch_pfit.control)
4575                 return;
4576
4577         /*
4578          * The panel fitter should only be adjusted whilst the pipe is disabled,
4579          * according to register description and PRM.
4580          */
4581         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4582         assert_pipe_disabled(dev_priv, crtc->pipe);
4583
4584         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4585         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4586
4587         /* Border color in case we don't scale up to the full screen. Black by
4588          * default, change to something else for debugging. */
4589         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4590 }
4591
4592 static enum intel_display_power_domain port_to_power_domain(enum port port)
4593 {
4594         switch (port) {
4595         case PORT_A:
4596                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4597         case PORT_B:
4598                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4599         case PORT_C:
4600                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4601         case PORT_D:
4602                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4603         default:
4604                 WARN_ON_ONCE(1);
4605                 return POWER_DOMAIN_PORT_OTHER;
4606         }
4607 }
4608
4609 #define for_each_power_domain(domain, mask)                             \
4610         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4611                 if ((1 << (domain)) & (mask))
4612
4613 enum intel_display_power_domain
4614 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4615 {
4616         struct drm_device *dev = intel_encoder->base.dev;
4617         struct intel_digital_port *intel_dig_port;
4618
4619         switch (intel_encoder->type) {
4620         case INTEL_OUTPUT_UNKNOWN:
4621                 /* Only DDI platforms should ever use this output type */
4622                 WARN_ON_ONCE(!HAS_DDI(dev));
4623         case INTEL_OUTPUT_DISPLAYPORT:
4624         case INTEL_OUTPUT_HDMI:
4625         case INTEL_OUTPUT_EDP:
4626                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4627                 return port_to_power_domain(intel_dig_port->port);
4628         case INTEL_OUTPUT_DP_MST:
4629                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4630                 return port_to_power_domain(intel_dig_port->port);
4631         case INTEL_OUTPUT_ANALOG:
4632                 return POWER_DOMAIN_PORT_CRT;
4633         case INTEL_OUTPUT_DSI:
4634                 return POWER_DOMAIN_PORT_DSI;
4635         default:
4636                 return POWER_DOMAIN_PORT_OTHER;
4637         }
4638 }
4639
4640 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4641 {
4642         struct drm_device *dev = crtc->dev;
4643         struct intel_encoder *intel_encoder;
4644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4645         enum pipe pipe = intel_crtc->pipe;
4646         unsigned long mask;
4647         enum transcoder transcoder;
4648
4649         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4650
4651         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4652         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4653         if (intel_crtc->config.pch_pfit.enabled ||
4654             intel_crtc->config.pch_pfit.force_thru)
4655                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4656
4657         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4658                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4659
4660         return mask;
4661 }
4662
4663 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4664 {
4665         struct drm_i915_private *dev_priv = dev->dev_private;
4666         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4667         struct intel_crtc *crtc;
4668
4669         /*
4670          * First get all needed power domains, then put all unneeded, to avoid
4671          * any unnecessary toggling of the power wells.
4672          */
4673         for_each_intel_crtc(dev, crtc) {
4674                 enum intel_display_power_domain domain;
4675
4676                 if (!crtc->base.enabled)
4677                         continue;
4678
4679                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4680
4681                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4682                         intel_display_power_get(dev_priv, domain);
4683         }
4684
4685         if (dev_priv->display.modeset_global_resources)
4686                 dev_priv->display.modeset_global_resources(dev);
4687
4688         for_each_intel_crtc(dev, crtc) {
4689                 enum intel_display_power_domain domain;
4690
4691                 for_each_power_domain(domain, crtc->enabled_power_domains)
4692                         intel_display_power_put(dev_priv, domain);
4693
4694                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4695         }
4696
4697         intel_display_set_init_power(dev_priv, false);
4698 }
4699
4700 /* returns HPLL frequency in kHz */
4701 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4702 {
4703         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4704
4705         /* Obtain SKU information */
4706         mutex_lock(&dev_priv->dpio_lock);
4707         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4708                 CCK_FUSE_HPLL_FREQ_MASK;
4709         mutex_unlock(&dev_priv->dpio_lock);
4710
4711         return vco_freq[hpll_freq] * 1000;
4712 }
4713
4714 static void vlv_update_cdclk(struct drm_device *dev)
4715 {
4716         struct drm_i915_private *dev_priv = dev->dev_private;
4717
4718         dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4719         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4720                          dev_priv->vlv_cdclk_freq);
4721
4722         /*
4723          * Program the gmbus_freq based on the cdclk frequency.
4724          * BSpec erroneously claims we should aim for 4MHz, but
4725          * in fact 1MHz is the correct frequency.
4726          */
4727         I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4728 }
4729
4730 /* Adjust CDclk dividers to allow high res or save power if possible */
4731 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4732 {
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734         u32 val, cmd;
4735
4736         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4737
4738         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4739                 cmd = 2;
4740         else if (cdclk == 266667)
4741                 cmd = 1;
4742         else
4743                 cmd = 0;
4744
4745         mutex_lock(&dev_priv->rps.hw_lock);
4746         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4747         val &= ~DSPFREQGUAR_MASK;
4748         val |= (cmd << DSPFREQGUAR_SHIFT);
4749         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4750         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4751                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4752                      50)) {
4753                 DRM_ERROR("timed out waiting for CDclk change\n");
4754         }
4755         mutex_unlock(&dev_priv->rps.hw_lock);
4756
4757         if (cdclk == 400000) {
4758                 u32 divider;
4759
4760                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4761
4762                 mutex_lock(&dev_priv->dpio_lock);
4763                 /* adjust cdclk divider */
4764                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4765                 val &= ~DISPLAY_FREQUENCY_VALUES;
4766                 val |= divider;
4767                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4768
4769                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4770                               DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4771                              50))
4772                         DRM_ERROR("timed out waiting for CDclk change\n");
4773                 mutex_unlock(&dev_priv->dpio_lock);
4774         }
4775
4776         mutex_lock(&dev_priv->dpio_lock);
4777         /* adjust self-refresh exit latency value */
4778         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4779         val &= ~0x7f;
4780
4781         /*
4782          * For high bandwidth configs, we set a higher latency in the bunit
4783          * so that the core display fetch happens in time to avoid underruns.
4784          */
4785         if (cdclk == 400000)
4786                 val |= 4500 / 250; /* 4.5 usec */
4787         else
4788                 val |= 3000 / 250; /* 3.0 usec */
4789         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4790         mutex_unlock(&dev_priv->dpio_lock);
4791
4792         vlv_update_cdclk(dev);
4793 }
4794
4795 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4796 {
4797         struct drm_i915_private *dev_priv = dev->dev_private;
4798         u32 val, cmd;
4799
4800         WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4801
4802         switch (cdclk) {
4803         case 400000:
4804                 cmd = 3;
4805                 break;
4806         case 333333:
4807         case 320000:
4808                 cmd = 2;
4809                 break;
4810         case 266667:
4811                 cmd = 1;
4812                 break;
4813         case 200000:
4814                 cmd = 0;
4815                 break;
4816         default:
4817                 WARN_ON(1);
4818                 return;
4819         }
4820
4821         mutex_lock(&dev_priv->rps.hw_lock);
4822         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4823         val &= ~DSPFREQGUAR_MASK_CHV;
4824         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4825         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4826         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4827                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4828                      50)) {
4829                 DRM_ERROR("timed out waiting for CDclk change\n");
4830         }
4831         mutex_unlock(&dev_priv->rps.hw_lock);
4832
4833         vlv_update_cdclk(dev);
4834 }
4835
4836 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4837                                  int max_pixclk)
4838 {
4839         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
4840
4841         /* FIXME: Punit isn't quite ready yet */
4842         if (IS_CHERRYVIEW(dev_priv->dev))
4843                 return 400000;
4844
4845         /*
4846          * Really only a few cases to deal with, as only 4 CDclks are supported:
4847          *   200MHz
4848          *   267MHz
4849          *   320/333MHz (depends on HPLL freq)
4850          *   400MHz
4851          * So we check to see whether we're above 90% of the lower bin and
4852          * adjust if needed.
4853          *
4854          * We seem to get an unstable or solid color picture at 200MHz.
4855          * Not sure what's wrong. For now use 200MHz only when all pipes
4856          * are off.
4857          */
4858         if (max_pixclk > freq_320*9/10)
4859                 return 400000;
4860         else if (max_pixclk > 266667*9/10)
4861                 return freq_320;
4862         else if (max_pixclk > 0)
4863                 return 266667;
4864         else
4865                 return 200000;
4866 }
4867
4868 /* compute the max pixel clock for new configuration */
4869 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4870 {
4871         struct drm_device *dev = dev_priv->dev;
4872         struct intel_crtc *intel_crtc;
4873         int max_pixclk = 0;
4874
4875         for_each_intel_crtc(dev, intel_crtc) {
4876                 if (intel_crtc->new_enabled)
4877                         max_pixclk = max(max_pixclk,
4878                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4879         }
4880
4881         return max_pixclk;
4882 }
4883
4884 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4885                                             unsigned *prepare_pipes)
4886 {
4887         struct drm_i915_private *dev_priv = dev->dev_private;
4888         struct intel_crtc *intel_crtc;
4889         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4890
4891         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4892             dev_priv->vlv_cdclk_freq)
4893                 return;
4894
4895         /* disable/enable all currently active pipes while we change cdclk */
4896         for_each_intel_crtc(dev, intel_crtc)
4897                 if (intel_crtc->base.enabled)
4898                         *prepare_pipes |= (1 << intel_crtc->pipe);
4899 }
4900
4901 static void valleyview_modeset_global_resources(struct drm_device *dev)
4902 {
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4905         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4906
4907         if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4908                 if (IS_CHERRYVIEW(dev))
4909                         cherryview_set_cdclk(dev, req_cdclk);
4910                 else
4911                         valleyview_set_cdclk(dev, req_cdclk);
4912         }
4913 }
4914
4915 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4916 {
4917         struct drm_device *dev = crtc->dev;
4918         struct drm_i915_private *dev_priv = to_i915(dev);
4919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4920         struct intel_encoder *encoder;
4921         int pipe = intel_crtc->pipe;
4922         bool is_dsi;
4923
4924         WARN_ON(!crtc->enabled);
4925
4926         if (intel_crtc->active)
4927                 return;
4928
4929         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4930
4931         if (!is_dsi) {
4932                 if (IS_CHERRYVIEW(dev))
4933                         chv_prepare_pll(intel_crtc, &intel_crtc->config);
4934                 else
4935                         vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4936         }
4937
4938         if (intel_crtc->config.has_dp_encoder)
4939                 intel_dp_set_m_n(intel_crtc);
4940
4941         intel_set_pipe_timings(intel_crtc);
4942
4943         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4944                 struct drm_i915_private *dev_priv = dev->dev_private;
4945
4946                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4947                 I915_WRITE(CHV_CANVAS(pipe), 0);
4948         }
4949
4950         i9xx_set_pipeconf(intel_crtc);
4951
4952         intel_crtc->active = true;
4953
4954         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4955
4956         for_each_encoder_on_crtc(dev, crtc, encoder)
4957                 if (encoder->pre_pll_enable)
4958                         encoder->pre_pll_enable(encoder);
4959
4960         if (!is_dsi) {
4961                 if (IS_CHERRYVIEW(dev))
4962                         chv_enable_pll(intel_crtc, &intel_crtc->config);
4963                 else
4964                         vlv_enable_pll(intel_crtc, &intel_crtc->config);
4965         }
4966
4967         for_each_encoder_on_crtc(dev, crtc, encoder)
4968                 if (encoder->pre_enable)
4969                         encoder->pre_enable(encoder);
4970
4971         i9xx_pfit_enable(intel_crtc);
4972
4973         intel_crtc_load_lut(crtc);
4974
4975         intel_update_watermarks(crtc);
4976         intel_enable_pipe(intel_crtc);
4977
4978         for_each_encoder_on_crtc(dev, crtc, encoder)
4979                 encoder->enable(encoder);
4980
4981         assert_vblank_disabled(crtc);
4982         drm_crtc_vblank_on(crtc);
4983
4984         intel_crtc_enable_planes(crtc);
4985
4986         /* Underruns don't raise interrupts, so check manually. */
4987         i9xx_check_fifo_underruns(dev_priv);
4988 }
4989
4990 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4991 {
4992         struct drm_device *dev = crtc->base.dev;
4993         struct drm_i915_private *dev_priv = dev->dev_private;
4994
4995         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4996         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4997 }
4998
4999 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5000 {
5001         struct drm_device *dev = crtc->dev;
5002         struct drm_i915_private *dev_priv = to_i915(dev);
5003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5004         struct intel_encoder *encoder;
5005         int pipe = intel_crtc->pipe;
5006
5007         WARN_ON(!crtc->enabled);
5008
5009         if (intel_crtc->active)
5010                 return;
5011
5012         i9xx_set_pll_dividers(intel_crtc);
5013
5014         if (intel_crtc->config.has_dp_encoder)
5015                 intel_dp_set_m_n(intel_crtc);
5016
5017         intel_set_pipe_timings(intel_crtc);
5018
5019         i9xx_set_pipeconf(intel_crtc);
5020
5021         intel_crtc->active = true;
5022
5023         if (!IS_GEN2(dev))
5024                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025
5026         for_each_encoder_on_crtc(dev, crtc, encoder)
5027                 if (encoder->pre_enable)
5028                         encoder->pre_enable(encoder);
5029
5030         i9xx_enable_pll(intel_crtc);
5031
5032         i9xx_pfit_enable(intel_crtc);
5033
5034         intel_crtc_load_lut(crtc);
5035
5036         intel_update_watermarks(crtc);
5037         intel_enable_pipe(intel_crtc);
5038
5039         for_each_encoder_on_crtc(dev, crtc, encoder)
5040                 encoder->enable(encoder);
5041
5042         assert_vblank_disabled(crtc);
5043         drm_crtc_vblank_on(crtc);
5044
5045         intel_crtc_enable_planes(crtc);
5046
5047         /*
5048          * Gen2 reports pipe underruns whenever all planes are disabled.
5049          * So don't enable underrun reporting before at least some planes
5050          * are enabled.
5051          * FIXME: Need to fix the logic to work when we turn off all planes
5052          * but leave the pipe running.
5053          */
5054         if (IS_GEN2(dev))
5055                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5056
5057         /* Underruns don't raise interrupts, so check manually. */
5058         i9xx_check_fifo_underruns(dev_priv);
5059 }
5060
5061 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5062 {
5063         struct drm_device *dev = crtc->base.dev;
5064         struct drm_i915_private *dev_priv = dev->dev_private;
5065
5066         if (!crtc->config.gmch_pfit.control)
5067                 return;
5068
5069         assert_pipe_disabled(dev_priv, crtc->pipe);
5070
5071         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5072                          I915_READ(PFIT_CONTROL));
5073         I915_WRITE(PFIT_CONTROL, 0);
5074 }
5075
5076 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5077 {
5078         struct drm_device *dev = crtc->dev;
5079         struct drm_i915_private *dev_priv = dev->dev_private;
5080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5081         struct intel_encoder *encoder;
5082         int pipe = intel_crtc->pipe;
5083
5084         if (!intel_crtc->active)
5085                 return;
5086
5087         /*
5088          * Gen2 reports pipe underruns whenever all planes are disabled.
5089          * So diasble underrun reporting before all the planes get disabled.
5090          * FIXME: Need to fix the logic to work when we turn off all planes
5091          * but leave the pipe running.
5092          */
5093         if (IS_GEN2(dev))
5094                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5095
5096         /*
5097          * Vblank time updates from the shadow to live plane control register
5098          * are blocked if the memory self-refresh mode is active at that
5099          * moment. So to make sure the plane gets truly disabled, disable
5100          * first the self-refresh mode. The self-refresh enable bit in turn
5101          * will be checked/applied by the HW only at the next frame start
5102          * event which is after the vblank start event, so we need to have a
5103          * wait-for-vblank between disabling the plane and the pipe.
5104          */
5105         intel_set_memory_cxsr(dev_priv, false);
5106         intel_crtc_disable_planes(crtc);
5107
5108         /*
5109          * On gen2 planes are double buffered but the pipe isn't, so we must
5110          * wait for planes to fully turn off before disabling the pipe.
5111          * We also need to wait on all gmch platforms because of the
5112          * self-refresh mode constraint explained above.
5113          */
5114         intel_wait_for_vblank(dev, pipe);
5115
5116         drm_crtc_vblank_off(crtc);
5117         assert_vblank_disabled(crtc);
5118
5119         for_each_encoder_on_crtc(dev, crtc, encoder)
5120                 encoder->disable(encoder);
5121
5122         intel_disable_pipe(intel_crtc);
5123
5124         i9xx_pfit_disable(intel_crtc);
5125
5126         for_each_encoder_on_crtc(dev, crtc, encoder)
5127                 if (encoder->post_disable)
5128                         encoder->post_disable(encoder);
5129
5130         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5131                 if (IS_CHERRYVIEW(dev))
5132                         chv_disable_pll(dev_priv, pipe);
5133                 else if (IS_VALLEYVIEW(dev))
5134                         vlv_disable_pll(dev_priv, pipe);
5135                 else
5136                         i9xx_disable_pll(intel_crtc);
5137         }
5138
5139         if (!IS_GEN2(dev))
5140                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5141
5142         intel_crtc->active = false;
5143         intel_update_watermarks(crtc);
5144
5145         mutex_lock(&dev->struct_mutex);
5146         intel_update_fbc(dev);
5147         mutex_unlock(&dev->struct_mutex);
5148 }
5149
5150 static void i9xx_crtc_off(struct drm_crtc *crtc)
5151 {
5152 }
5153
5154 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5155                                     bool enabled)
5156 {
5157         struct drm_device *dev = crtc->dev;
5158         struct drm_i915_master_private *master_priv;
5159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5160         int pipe = intel_crtc->pipe;
5161
5162         if (!dev->primary->master)
5163                 return;
5164
5165         master_priv = dev->primary->master->driver_priv;
5166         if (!master_priv->sarea_priv)
5167                 return;
5168
5169         switch (pipe) {
5170         case 0:
5171                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5172                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5173                 break;
5174         case 1:
5175                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5176                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5177                 break;
5178         default:
5179                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5180                 break;
5181         }
5182 }
5183
5184 /* Master function to enable/disable CRTC and corresponding power wells */
5185 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5186 {
5187         struct drm_device *dev = crtc->dev;
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5190         enum intel_display_power_domain domain;
5191         unsigned long domains;
5192
5193         if (enable) {
5194                 if (!intel_crtc->active) {
5195                         domains = get_crtc_power_domains(crtc);
5196                         for_each_power_domain(domain, domains)
5197                                 intel_display_power_get(dev_priv, domain);
5198                         intel_crtc->enabled_power_domains = domains;
5199
5200                         dev_priv->display.crtc_enable(crtc);
5201                 }
5202         } else {
5203                 if (intel_crtc->active) {
5204                         dev_priv->display.crtc_disable(crtc);
5205
5206                         domains = intel_crtc->enabled_power_domains;
5207                         for_each_power_domain(domain, domains)
5208                                 intel_display_power_put(dev_priv, domain);
5209                         intel_crtc->enabled_power_domains = 0;
5210                 }
5211         }
5212 }
5213
5214 /**
5215  * Sets the power management mode of the pipe and plane.
5216  */
5217 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5218 {
5219         struct drm_device *dev = crtc->dev;
5220         struct intel_encoder *intel_encoder;
5221         bool enable = false;
5222
5223         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5224                 enable |= intel_encoder->connectors_active;
5225
5226         intel_crtc_control(crtc, enable);
5227
5228         intel_crtc_update_sarea(crtc, enable);
5229 }
5230
5231 static void intel_crtc_disable(struct drm_crtc *crtc)
5232 {
5233         struct drm_device *dev = crtc->dev;
5234         struct drm_connector *connector;
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5237         enum pipe pipe = to_intel_crtc(crtc)->pipe;
5238
5239         /* crtc should still be enabled when we disable it. */
5240         WARN_ON(!crtc->enabled);
5241
5242         dev_priv->display.crtc_disable(crtc);
5243         intel_crtc_update_sarea(crtc, false);
5244         dev_priv->display.off(crtc);
5245
5246         if (crtc->primary->fb) {
5247                 mutex_lock(&dev->struct_mutex);
5248                 intel_unpin_fb_obj(old_obj);
5249                 i915_gem_track_fb(old_obj, NULL,
5250                                   INTEL_FRONTBUFFER_PRIMARY(pipe));
5251                 mutex_unlock(&dev->struct_mutex);
5252                 crtc->primary->fb = NULL;
5253         }
5254
5255         /* Update computed state. */
5256         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5257                 if (!connector->encoder || !connector->encoder->crtc)
5258                         continue;
5259
5260                 if (connector->encoder->crtc != crtc)
5261                         continue;
5262
5263                 connector->dpms = DRM_MODE_DPMS_OFF;
5264                 to_intel_encoder(connector->encoder)->connectors_active = false;
5265         }
5266 }
5267
5268 void intel_encoder_destroy(struct drm_encoder *encoder)
5269 {
5270         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5271
5272         drm_encoder_cleanup(encoder);
5273         kfree(intel_encoder);
5274 }
5275
5276 /* Simple dpms helper for encoders with just one connector, no cloning and only
5277  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5278  * state of the entire output pipe. */
5279 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5280 {
5281         if (mode == DRM_MODE_DPMS_ON) {
5282                 encoder->connectors_active = true;
5283
5284                 intel_crtc_update_dpms(encoder->base.crtc);
5285         } else {
5286                 encoder->connectors_active = false;
5287
5288                 intel_crtc_update_dpms(encoder->base.crtc);
5289         }
5290 }
5291
5292 /* Cross check the actual hw state with our own modeset state tracking (and it's
5293  * internal consistency). */
5294 static void intel_connector_check_state(struct intel_connector *connector)
5295 {
5296         if (connector->get_hw_state(connector)) {
5297                 struct intel_encoder *encoder = connector->encoder;
5298                 struct drm_crtc *crtc;
5299                 bool encoder_enabled;
5300                 enum pipe pipe;
5301
5302                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5303                               connector->base.base.id,
5304                               connector->base.name);
5305
5306                 /* there is no real hw state for MST connectors */
5307                 if (connector->mst_port)
5308                         return;
5309
5310                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5311                      "wrong connector dpms state\n");
5312                 WARN(connector->base.encoder != &encoder->base,
5313                      "active connector not linked to encoder\n");
5314
5315                 if (encoder) {
5316                         WARN(!encoder->connectors_active,
5317                              "encoder->connectors_active not set\n");
5318
5319                         encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5320                         WARN(!encoder_enabled, "encoder not enabled\n");
5321                         if (WARN_ON(!encoder->base.crtc))
5322                                 return;
5323
5324                         crtc = encoder->base.crtc;
5325
5326                         WARN(!crtc->enabled, "crtc not enabled\n");
5327                         WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5328                         WARN(pipe != to_intel_crtc(crtc)->pipe,
5329                              "encoder active on the wrong pipe\n");
5330                 }
5331         }
5332 }
5333
5334 /* Even simpler default implementation, if there's really no special case to
5335  * consider. */
5336 void intel_connector_dpms(struct drm_connector *connector, int mode)
5337 {
5338         /* All the simple cases only support two dpms states. */
5339         if (mode != DRM_MODE_DPMS_ON)
5340                 mode = DRM_MODE_DPMS_OFF;
5341
5342         if (mode == connector->dpms)
5343                 return;
5344
5345         connector->dpms = mode;
5346
5347         /* Only need to change hw state when actually enabled */
5348         if (connector->encoder)
5349                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5350
5351         intel_modeset_check_state(connector->dev);
5352 }
5353
5354 /* Simple connector->get_hw_state implementation for encoders that support only
5355  * one connector and no cloning and hence the encoder state determines the state
5356  * of the connector. */
5357 bool intel_connector_get_hw_state(struct intel_connector *connector)
5358 {
5359         enum pipe pipe = 0;
5360         struct intel_encoder *encoder = connector->encoder;
5361
5362         return encoder->get_hw_state(encoder, &pipe);
5363 }
5364
5365 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5366                                      struct intel_crtc_config *pipe_config)
5367 {
5368         struct drm_i915_private *dev_priv = dev->dev_private;
5369         struct intel_crtc *pipe_B_crtc =
5370                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5371
5372         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5373                       pipe_name(pipe), pipe_config->fdi_lanes);
5374         if (pipe_config->fdi_lanes > 4) {
5375                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5376                               pipe_name(pipe), pipe_config->fdi_lanes);
5377                 return false;
5378         }
5379
5380         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5381                 if (pipe_config->fdi_lanes > 2) {
5382                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5383                                       pipe_config->fdi_lanes);
5384                         return false;
5385                 } else {
5386                         return true;
5387                 }
5388         }
5389
5390         if (INTEL_INFO(dev)->num_pipes == 2)
5391                 return true;
5392
5393         /* Ivybridge 3 pipe is really complicated */
5394         switch (pipe) {
5395         case PIPE_A:
5396                 return true;
5397         case PIPE_B:
5398                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5399                     pipe_config->fdi_lanes > 2) {
5400                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5401                                       pipe_name(pipe), pipe_config->fdi_lanes);
5402                         return false;
5403                 }
5404                 return true;
5405         case PIPE_C:
5406                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5407                     pipe_B_crtc->config.fdi_lanes <= 2) {
5408                         if (pipe_config->fdi_lanes > 2) {
5409                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5410                                               pipe_name(pipe), pipe_config->fdi_lanes);
5411                                 return false;
5412                         }
5413                 } else {
5414                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5415                         return false;
5416                 }
5417                 return true;
5418         default:
5419                 BUG();
5420         }
5421 }
5422
5423 #define RETRY 1
5424 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5425                                        struct intel_crtc_config *pipe_config)
5426 {
5427         struct drm_device *dev = intel_crtc->base.dev;
5428         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5429         int lane, link_bw, fdi_dotclock;
5430         bool setup_ok, needs_recompute = false;
5431
5432 retry:
5433         /* FDI is a binary signal running at ~2.7GHz, encoding
5434          * each output octet as 10 bits. The actual frequency
5435          * is stored as a divider into a 100MHz clock, and the
5436          * mode pixel clock is stored in units of 1KHz.
5437          * Hence the bw of each lane in terms of the mode signal
5438          * is:
5439          */
5440         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5441
5442         fdi_dotclock = adjusted_mode->crtc_clock;
5443
5444         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5445                                            pipe_config->pipe_bpp);
5446
5447         pipe_config->fdi_lanes = lane;
5448
5449         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5450                                link_bw, &pipe_config->fdi_m_n);
5451
5452         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5453                                             intel_crtc->pipe, pipe_config);
5454         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5455                 pipe_config->pipe_bpp -= 2*3;
5456                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5457                               pipe_config->pipe_bpp);
5458                 needs_recompute = true;
5459                 pipe_config->bw_constrained = true;
5460
5461                 goto retry;
5462         }
5463
5464         if (needs_recompute)
5465                 return RETRY;
5466
5467         return setup_ok ? 0 : -EINVAL;
5468 }
5469
5470 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5471                                    struct intel_crtc_config *pipe_config)
5472 {
5473         pipe_config->ips_enabled = i915.enable_ips &&
5474                                    hsw_crtc_supports_ips(crtc) &&
5475                                    pipe_config->pipe_bpp <= 24;
5476 }
5477
5478 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5479                                      struct intel_crtc_config *pipe_config)
5480 {
5481         struct drm_device *dev = crtc->base.dev;
5482         struct drm_i915_private *dev_priv = dev->dev_private;
5483         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5484
5485         /* FIXME should check pixel clock limits on all platforms */
5486         if (INTEL_INFO(dev)->gen < 4) {
5487                 int clock_limit =
5488                         dev_priv->display.get_display_clock_speed(dev);
5489
5490                 /*
5491                  * Enable pixel doubling when the dot clock
5492                  * is > 90% of the (display) core speed.
5493                  *
5494                  * GDG double wide on either pipe,
5495                  * otherwise pipe A only.
5496                  */
5497                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5498                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5499                         clock_limit *= 2;
5500                         pipe_config->double_wide = true;
5501                 }
5502
5503                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5504                         return -EINVAL;
5505         }
5506
5507         /*
5508          * Pipe horizontal size must be even in:
5509          * - DVO ganged mode
5510          * - LVDS dual channel mode
5511          * - Double wide pipe
5512          */
5513         if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5514              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5515                 pipe_config->pipe_src_w &= ~1;
5516
5517         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5518          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5519          */
5520         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5521                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5522                 return -EINVAL;
5523
5524         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5525                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5526         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5527                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5528                  * for lvds. */
5529                 pipe_config->pipe_bpp = 8*3;
5530         }
5531
5532         if (HAS_IPS(dev))
5533                 hsw_compute_ips_config(crtc, pipe_config);
5534
5535         if (pipe_config->has_pch_encoder)
5536                 return ironlake_fdi_compute_config(crtc, pipe_config);
5537
5538         return 0;
5539 }
5540
5541 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5542 {
5543         struct drm_i915_private *dev_priv = dev->dev_private;
5544         u32 val;
5545         int divider;
5546
5547         /* FIXME: Punit isn't quite ready yet */
5548         if (IS_CHERRYVIEW(dev))
5549                 return 400000;
5550
5551         if (dev_priv->hpll_freq == 0)
5552                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5553
5554         mutex_lock(&dev_priv->dpio_lock);
5555         val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5556         mutex_unlock(&dev_priv->dpio_lock);
5557
5558         divider = val & DISPLAY_FREQUENCY_VALUES;
5559
5560         WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5561              (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5562              "cdclk change in progress\n");
5563
5564         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5565 }
5566
5567 static int i945_get_display_clock_speed(struct drm_device *dev)
5568 {
5569         return 400000;
5570 }
5571
5572 static int i915_get_display_clock_speed(struct drm_device *dev)
5573 {
5574         return 333000;
5575 }
5576
5577 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5578 {
5579         return 200000;
5580 }
5581
5582 static int pnv_get_display_clock_speed(struct drm_device *dev)
5583 {
5584         u16 gcfgc = 0;
5585
5586         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5587
5588         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5589         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5590                 return 267000;
5591         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5592                 return 333000;
5593         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5594                 return 444000;
5595         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5596                 return 200000;
5597         default:
5598                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5599         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5600                 return 133000;
5601         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5602                 return 167000;
5603         }
5604 }
5605
5606 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5607 {
5608         u16 gcfgc = 0;
5609
5610         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5611
5612         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5613                 return 133000;
5614         else {
5615                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5616                 case GC_DISPLAY_CLOCK_333_MHZ:
5617                         return 333000;
5618                 default:
5619                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5620                         return 190000;
5621                 }
5622         }
5623 }
5624
5625 static int i865_get_display_clock_speed(struct drm_device *dev)
5626 {
5627         return 266000;
5628 }
5629
5630 static int i855_get_display_clock_speed(struct drm_device *dev)
5631 {
5632         u16 hpllcc = 0;
5633         /* Assume that the hardware is in the high speed state.  This
5634          * should be the default.
5635          */
5636         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5637         case GC_CLOCK_133_200:
5638         case GC_CLOCK_100_200:
5639                 return 200000;
5640         case GC_CLOCK_166_250:
5641                 return 250000;
5642         case GC_CLOCK_100_133:
5643                 return 133000;
5644         }
5645
5646         /* Shouldn't happen */
5647         return 0;
5648 }
5649
5650 static int i830_get_display_clock_speed(struct drm_device *dev)
5651 {
5652         return 133000;
5653 }
5654
5655 static void
5656 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5657 {
5658         while (*num > DATA_LINK_M_N_MASK ||
5659                *den > DATA_LINK_M_N_MASK) {
5660                 *num >>= 1;
5661                 *den >>= 1;
5662         }
5663 }
5664
5665 static void compute_m_n(unsigned int m, unsigned int n,
5666                         uint32_t *ret_m, uint32_t *ret_n)
5667 {
5668         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5669         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5670         intel_reduce_m_n_ratio(ret_m, ret_n);
5671 }
5672
5673 void
5674 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5675                        int pixel_clock, int link_clock,
5676                        struct intel_link_m_n *m_n)
5677 {
5678         m_n->tu = 64;
5679
5680         compute_m_n(bits_per_pixel * pixel_clock,
5681                     link_clock * nlanes * 8,
5682                     &m_n->gmch_m, &m_n->gmch_n);
5683
5684         compute_m_n(pixel_clock, link_clock,
5685                     &m_n->link_m, &m_n->link_n);
5686 }
5687
5688 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5689 {
5690         if (i915.panel_use_ssc >= 0)
5691                 return i915.panel_use_ssc != 0;
5692         return dev_priv->vbt.lvds_use_ssc
5693                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5694 }
5695
5696 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5697 {
5698         struct drm_device *dev = crtc->base.dev;
5699         struct drm_i915_private *dev_priv = dev->dev_private;
5700         int refclk;
5701
5702         if (IS_VALLEYVIEW(dev)) {
5703                 refclk = 100000;
5704         } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5705             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5706                 refclk = dev_priv->vbt.lvds_ssc_freq;
5707                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5708         } else if (!IS_GEN2(dev)) {
5709                 refclk = 96000;
5710         } else {
5711                 refclk = 48000;
5712         }
5713
5714         return refclk;
5715 }
5716
5717 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5718 {
5719         return (1 << dpll->n) << 16 | dpll->m2;
5720 }
5721
5722 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5723 {
5724         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5725 }
5726
5727 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5728                                      intel_clock_t *reduced_clock)
5729 {
5730         struct drm_device *dev = crtc->base.dev;
5731         u32 fp, fp2 = 0;
5732
5733         if (IS_PINEVIEW(dev)) {
5734                 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5735                 if (reduced_clock)
5736                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5737         } else {
5738                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5739                 if (reduced_clock)
5740                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5741         }
5742
5743         crtc->new_config->dpll_hw_state.fp0 = fp;
5744
5745         crtc->lowfreq_avail = false;
5746         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5747             reduced_clock && i915.powersave) {
5748                 crtc->new_config->dpll_hw_state.fp1 = fp2;
5749                 crtc->lowfreq_avail = true;
5750         } else {
5751                 crtc->new_config->dpll_hw_state.fp1 = fp;
5752         }
5753 }
5754
5755 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5756                 pipe)
5757 {
5758         u32 reg_val;
5759
5760         /*
5761          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5762          * and set it to a reasonable value instead.
5763          */
5764         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5765         reg_val &= 0xffffff00;
5766         reg_val |= 0x00000030;
5767         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5768
5769         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5770         reg_val &= 0x8cffffff;
5771         reg_val = 0x8c000000;
5772         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5773
5774         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5775         reg_val &= 0xffffff00;
5776         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5777
5778         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5779         reg_val &= 0x00ffffff;
5780         reg_val |= 0xb0000000;
5781         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5782 }
5783
5784 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5785                                          struct intel_link_m_n *m_n)
5786 {
5787         struct drm_device *dev = crtc->base.dev;
5788         struct drm_i915_private *dev_priv = dev->dev_private;
5789         int pipe = crtc->pipe;
5790
5791         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5792         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5793         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5794         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5795 }
5796
5797 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5798                                          struct intel_link_m_n *m_n,
5799                                          struct intel_link_m_n *m2_n2)
5800 {
5801         struct drm_device *dev = crtc->base.dev;
5802         struct drm_i915_private *dev_priv = dev->dev_private;
5803         int pipe = crtc->pipe;
5804         enum transcoder transcoder = crtc->config.cpu_transcoder;
5805
5806         if (INTEL_INFO(dev)->gen >= 5) {
5807                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5808                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5809                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5810                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5811                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5812                  * for gen < 8) and if DRRS is supported (to make sure the
5813                  * registers are not unnecessarily accessed).
5814                  */
5815                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5816                         crtc->config.has_drrs) {
5817                         I915_WRITE(PIPE_DATA_M2(transcoder),
5818                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5819                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5820                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5821                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5822                 }
5823         } else {
5824                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5825                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5826                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5827                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5828         }
5829 }
5830
5831 void intel_dp_set_m_n(struct intel_crtc *crtc)
5832 {
5833         if (crtc->config.has_pch_encoder)
5834                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5835         else
5836                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5837                                                    &crtc->config.dp_m2_n2);
5838 }
5839
5840 static void vlv_update_pll(struct intel_crtc *crtc,
5841                            struct intel_crtc_config *pipe_config)
5842 {
5843         u32 dpll, dpll_md;
5844
5845         /*
5846          * Enable DPIO clock input. We should never disable the reference
5847          * clock for pipe B, since VGA hotplug / manual detection depends
5848          * on it.
5849          */
5850         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5851                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5852         /* We should never disable this, set it here for state tracking */
5853         if (crtc->pipe == PIPE_B)
5854                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5855         dpll |= DPLL_VCO_ENABLE;
5856         pipe_config->dpll_hw_state.dpll = dpll;
5857
5858         dpll_md = (pipe_config->pixel_multiplier - 1)
5859                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5860         pipe_config->dpll_hw_state.dpll_md = dpll_md;
5861 }
5862
5863 static void vlv_prepare_pll(struct intel_crtc *crtc,
5864                             const struct intel_crtc_config *pipe_config)
5865 {
5866         struct drm_device *dev = crtc->base.dev;
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         int pipe = crtc->pipe;
5869         u32 mdiv;
5870         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5871         u32 coreclk, reg_val;
5872
5873         mutex_lock(&dev_priv->dpio_lock);
5874
5875         bestn = pipe_config->dpll.n;
5876         bestm1 = pipe_config->dpll.m1;
5877         bestm2 = pipe_config->dpll.m2;
5878         bestp1 = pipe_config->dpll.p1;
5879         bestp2 = pipe_config->dpll.p2;
5880
5881         /* See eDP HDMI DPIO driver vbios notes doc */
5882
5883         /* PLL B needs special handling */
5884         if (pipe == PIPE_B)
5885                 vlv_pllb_recal_opamp(dev_priv, pipe);
5886
5887         /* Set up Tx target for periodic Rcomp update */
5888         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5889
5890         /* Disable target IRef on PLL */
5891         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5892         reg_val &= 0x00ffffff;
5893         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5894
5895         /* Disable fast lock */
5896         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5897
5898         /* Set idtafcrecal before PLL is enabled */
5899         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5900         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5901         mdiv |= ((bestn << DPIO_N_SHIFT));
5902         mdiv |= (1 << DPIO_K_SHIFT);
5903
5904         /*
5905          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5906          * but we don't support that).
5907          * Note: don't use the DAC post divider as it seems unstable.
5908          */
5909         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5910         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5911
5912         mdiv |= DPIO_ENABLE_CALIBRATION;
5913         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5914
5915         /* Set HBR and RBR LPF coefficients */
5916         if (pipe_config->port_clock == 162000 ||
5917             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5918             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5919                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5920                                  0x009f0003);
5921         else
5922                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5923                                  0x00d0000f);
5924
5925         if (crtc->config.has_dp_encoder) {
5926                 /* Use SSC source */
5927                 if (pipe == PIPE_A)
5928                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5929                                          0x0df40000);
5930                 else
5931                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5932                                          0x0df70000);
5933         } else { /* HDMI or VGA */
5934                 /* Use bend source */
5935                 if (pipe == PIPE_A)
5936                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5937                                          0x0df70000);
5938                 else
5939                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5940                                          0x0df40000);
5941         }
5942
5943         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5944         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5945         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5946             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5947                 coreclk |= 0x01000000;
5948         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5949
5950         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5951         mutex_unlock(&dev_priv->dpio_lock);
5952 }
5953
5954 static void chv_update_pll(struct intel_crtc *crtc,
5955                            struct intel_crtc_config *pipe_config)
5956 {
5957         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5958                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5959                 DPLL_VCO_ENABLE;
5960         if (crtc->pipe != PIPE_A)
5961                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5962
5963         pipe_config->dpll_hw_state.dpll_md =
5964                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5965 }
5966
5967 static void chv_prepare_pll(struct intel_crtc *crtc,
5968                             const struct intel_crtc_config *pipe_config)
5969 {
5970         struct drm_device *dev = crtc->base.dev;
5971         struct drm_i915_private *dev_priv = dev->dev_private;
5972         int pipe = crtc->pipe;
5973         int dpll_reg = DPLL(crtc->pipe);
5974         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5975         u32 loopfilter, intcoeff;
5976         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5977         int refclk;
5978
5979         bestn = pipe_config->dpll.n;
5980         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5981         bestm1 = pipe_config->dpll.m1;
5982         bestm2 = pipe_config->dpll.m2 >> 22;
5983         bestp1 = pipe_config->dpll.p1;
5984         bestp2 = pipe_config->dpll.p2;
5985
5986         /*
5987          * Enable Refclk and SSC
5988          */
5989         I915_WRITE(dpll_reg,
5990                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5991
5992         mutex_lock(&dev_priv->dpio_lock);
5993
5994         /* p1 and p2 divider */
5995         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5996                         5 << DPIO_CHV_S1_DIV_SHIFT |
5997                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5998                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5999                         1 << DPIO_CHV_K_DIV_SHIFT);
6000
6001         /* Feedback post-divider - m2 */
6002         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6003
6004         /* Feedback refclk divider - n and m1 */
6005         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6006                         DPIO_CHV_M1_DIV_BY_2 |
6007                         1 << DPIO_CHV_N_DIV_SHIFT);
6008
6009         /* M2 fraction division */
6010         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6011
6012         /* M2 fraction division enable */
6013         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6014                        DPIO_CHV_FRAC_DIV_EN |
6015                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6016
6017         /* Loop filter */
6018         refclk = i9xx_get_refclk(crtc, 0);
6019         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6020                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6021         if (refclk == 100000)
6022                 intcoeff = 11;
6023         else if (refclk == 38400)
6024                 intcoeff = 10;
6025         else
6026                 intcoeff = 9;
6027         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6028         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6029
6030         /* AFC Recal */
6031         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6032                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6033                         DPIO_AFC_RECAL);
6034
6035         mutex_unlock(&dev_priv->dpio_lock);
6036 }
6037
6038 /**
6039  * vlv_force_pll_on - forcibly enable just the PLL
6040  * @dev_priv: i915 private structure
6041  * @pipe: pipe PLL to enable
6042  * @dpll: PLL configuration
6043  *
6044  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6045  * in cases where we need the PLL enabled even when @pipe is not going to
6046  * be enabled.
6047  */
6048 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6049                       const struct dpll *dpll)
6050 {
6051         struct intel_crtc *crtc =
6052                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6053         struct intel_crtc_config pipe_config = {
6054                 .pixel_multiplier = 1,
6055                 .dpll = *dpll,
6056         };
6057
6058         if (IS_CHERRYVIEW(dev)) {
6059                 chv_update_pll(crtc, &pipe_config);
6060                 chv_prepare_pll(crtc, &pipe_config);
6061                 chv_enable_pll(crtc, &pipe_config);
6062         } else {
6063                 vlv_update_pll(crtc, &pipe_config);
6064                 vlv_prepare_pll(crtc, &pipe_config);
6065                 vlv_enable_pll(crtc, &pipe_config);
6066         }
6067 }
6068
6069 /**
6070  * vlv_force_pll_off - forcibly disable just the PLL
6071  * @dev_priv: i915 private structure
6072  * @pipe: pipe PLL to disable
6073  *
6074  * Disable the PLL for @pipe. To be used in cases where we need
6075  * the PLL enabled even when @pipe is not going to be enabled.
6076  */
6077 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6078 {
6079         if (IS_CHERRYVIEW(dev))
6080                 chv_disable_pll(to_i915(dev), pipe);
6081         else
6082                 vlv_disable_pll(to_i915(dev), pipe);
6083 }
6084
6085 static void i9xx_update_pll(struct intel_crtc *crtc,
6086                             intel_clock_t *reduced_clock,
6087                             int num_connectors)
6088 {
6089         struct drm_device *dev = crtc->base.dev;
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091         u32 dpll;
6092         bool is_sdvo;
6093         struct dpll *clock = &crtc->new_config->dpll;
6094
6095         i9xx_update_pll_dividers(crtc, reduced_clock);
6096
6097         is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6098                 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6099
6100         dpll = DPLL_VGA_MODE_DIS;
6101
6102         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6103                 dpll |= DPLLB_MODE_LVDS;
6104         else
6105                 dpll |= DPLLB_MODE_DAC_SERIAL;
6106
6107         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6108                 dpll |= (crtc->new_config->pixel_multiplier - 1)
6109                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6110         }
6111
6112         if (is_sdvo)
6113                 dpll |= DPLL_SDVO_HIGH_SPEED;
6114
6115         if (crtc->new_config->has_dp_encoder)
6116                 dpll |= DPLL_SDVO_HIGH_SPEED;
6117
6118         /* compute bitmask from p1 value */
6119         if (IS_PINEVIEW(dev))
6120                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6121         else {
6122                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6123                 if (IS_G4X(dev) && reduced_clock)
6124                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6125         }
6126         switch (clock->p2) {
6127         case 5:
6128                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6129                 break;
6130         case 7:
6131                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6132                 break;
6133         case 10:
6134                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6135                 break;
6136         case 14:
6137                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6138                 break;
6139         }
6140         if (INTEL_INFO(dev)->gen >= 4)
6141                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6142
6143         if (crtc->new_config->sdvo_tv_clock)
6144                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6145         else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6146                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6147                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6148         else
6149                 dpll |= PLL_REF_INPUT_DREFCLK;
6150
6151         dpll |= DPLL_VCO_ENABLE;
6152         crtc->new_config->dpll_hw_state.dpll = dpll;
6153
6154         if (INTEL_INFO(dev)->gen >= 4) {
6155                 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6156                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6157                 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6158         }
6159 }
6160
6161 static void i8xx_update_pll(struct intel_crtc *crtc,
6162                             intel_clock_t *reduced_clock,
6163                             int num_connectors)
6164 {
6165         struct drm_device *dev = crtc->base.dev;
6166         struct drm_i915_private *dev_priv = dev->dev_private;
6167         u32 dpll;
6168         struct dpll *clock = &crtc->new_config->dpll;
6169
6170         i9xx_update_pll_dividers(crtc, reduced_clock);
6171
6172         dpll = DPLL_VGA_MODE_DIS;
6173
6174         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6175                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6176         } else {
6177                 if (clock->p1 == 2)
6178                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6179                 else
6180                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6181                 if (clock->p2 == 4)
6182                         dpll |= PLL_P2_DIVIDE_BY_4;
6183         }
6184
6185         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6186                 dpll |= DPLL_DVO_2X_MODE;
6187
6188         if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6189                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6190                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6191         else
6192                 dpll |= PLL_REF_INPUT_DREFCLK;
6193
6194         dpll |= DPLL_VCO_ENABLE;
6195         crtc->new_config->dpll_hw_state.dpll = dpll;
6196 }
6197
6198 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6199 {
6200         struct drm_device *dev = intel_crtc->base.dev;
6201         struct drm_i915_private *dev_priv = dev->dev_private;
6202         enum pipe pipe = intel_crtc->pipe;
6203         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6204         struct drm_display_mode *adjusted_mode =
6205                 &intel_crtc->config.adjusted_mode;
6206         uint32_t crtc_vtotal, crtc_vblank_end;
6207         int vsyncshift = 0;
6208
6209         /* We need to be careful not to changed the adjusted mode, for otherwise
6210          * the hw state checker will get angry at the mismatch. */
6211         crtc_vtotal = adjusted_mode->crtc_vtotal;
6212         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6213
6214         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6215                 /* the chip adds 2 halflines automatically */
6216                 crtc_vtotal -= 1;
6217                 crtc_vblank_end -= 1;
6218
6219                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6220                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6221                 else
6222                         vsyncshift = adjusted_mode->crtc_hsync_start -
6223                                 adjusted_mode->crtc_htotal / 2;
6224                 if (vsyncshift < 0)
6225                         vsyncshift += adjusted_mode->crtc_htotal;
6226         }
6227
6228         if (INTEL_INFO(dev)->gen > 3)
6229                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6230
6231         I915_WRITE(HTOTAL(cpu_transcoder),
6232                    (adjusted_mode->crtc_hdisplay - 1) |
6233                    ((adjusted_mode->crtc_htotal - 1) << 16));
6234         I915_WRITE(HBLANK(cpu_transcoder),
6235                    (adjusted_mode->crtc_hblank_start - 1) |
6236                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6237         I915_WRITE(HSYNC(cpu_transcoder),
6238                    (adjusted_mode->crtc_hsync_start - 1) |
6239                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6240
6241         I915_WRITE(VTOTAL(cpu_transcoder),
6242                    (adjusted_mode->crtc_vdisplay - 1) |
6243                    ((crtc_vtotal - 1) << 16));
6244         I915_WRITE(VBLANK(cpu_transcoder),
6245                    (adjusted_mode->crtc_vblank_start - 1) |
6246                    ((crtc_vblank_end - 1) << 16));
6247         I915_WRITE(VSYNC(cpu_transcoder),
6248                    (adjusted_mode->crtc_vsync_start - 1) |
6249                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6250
6251         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6252          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6253          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6254          * bits. */
6255         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6256             (pipe == PIPE_B || pipe == PIPE_C))
6257                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6258
6259         /* pipesrc controls the size that is scaled from, which should
6260          * always be the user's requested size.
6261          */
6262         I915_WRITE(PIPESRC(pipe),
6263                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
6264                    (intel_crtc->config.pipe_src_h - 1));
6265 }
6266
6267 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6268                                    struct intel_crtc_config *pipe_config)
6269 {
6270         struct drm_device *dev = crtc->base.dev;
6271         struct drm_i915_private *dev_priv = dev->dev_private;
6272         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6273         uint32_t tmp;
6274
6275         tmp = I915_READ(HTOTAL(cpu_transcoder));
6276         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6277         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6278         tmp = I915_READ(HBLANK(cpu_transcoder));
6279         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6280         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6281         tmp = I915_READ(HSYNC(cpu_transcoder));
6282         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6283         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6284
6285         tmp = I915_READ(VTOTAL(cpu_transcoder));
6286         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6287         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6288         tmp = I915_READ(VBLANK(cpu_transcoder));
6289         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6290         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6291         tmp = I915_READ(VSYNC(cpu_transcoder));
6292         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6293         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6294
6295         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6296                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6297                 pipe_config->adjusted_mode.crtc_vtotal += 1;
6298                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6299         }
6300
6301         tmp = I915_READ(PIPESRC(crtc->pipe));
6302         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6303         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6304
6305         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6306         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6307 }
6308
6309 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6310                                  struct intel_crtc_config *pipe_config)
6311 {
6312         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6313         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6314         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6315         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6316
6317         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6318         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6319         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6320         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6321
6322         mode->flags = pipe_config->adjusted_mode.flags;
6323
6324         mode->clock = pipe_config->adjusted_mode.crtc_clock;
6325         mode->flags |= pipe_config->adjusted_mode.flags;
6326 }
6327
6328 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6329 {
6330         struct drm_device *dev = intel_crtc->base.dev;
6331         struct drm_i915_private *dev_priv = dev->dev_private;
6332         uint32_t pipeconf;
6333
6334         pipeconf = 0;
6335
6336         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6337             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6338                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6339
6340         if (intel_crtc->config.double_wide)
6341                 pipeconf |= PIPECONF_DOUBLE_WIDE;
6342
6343         /* only g4x and later have fancy bpc/dither controls */
6344         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6345                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6346                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6347                         pipeconf |= PIPECONF_DITHER_EN |
6348                                     PIPECONF_DITHER_TYPE_SP;
6349
6350                 switch (intel_crtc->config.pipe_bpp) {
6351                 case 18:
6352                         pipeconf |= PIPECONF_6BPC;
6353                         break;
6354                 case 24:
6355                         pipeconf |= PIPECONF_8BPC;
6356                         break;
6357                 case 30:
6358                         pipeconf |= PIPECONF_10BPC;
6359                         break;
6360                 default:
6361                         /* Case prevented by intel_choose_pipe_bpp_dither. */
6362                         BUG();
6363                 }
6364         }
6365
6366         if (HAS_PIPE_CXSR(dev)) {
6367                 if (intel_crtc->lowfreq_avail) {
6368                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6369                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6370                 } else {
6371                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6372                 }
6373         }
6374
6375         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6376                 if (INTEL_INFO(dev)->gen < 4 ||
6377                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6378                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6379                 else
6380                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6381         } else
6382                 pipeconf |= PIPECONF_PROGRESSIVE;
6383
6384         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6385                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6386
6387         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6388         POSTING_READ(PIPECONF(intel_crtc->pipe));
6389 }
6390
6391 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6392 {
6393         struct drm_device *dev = crtc->base.dev;
6394         struct drm_i915_private *dev_priv = dev->dev_private;
6395         int refclk, num_connectors = 0;
6396         intel_clock_t clock, reduced_clock;
6397         bool ok, has_reduced_clock = false;
6398         bool is_lvds = false, is_dsi = false;
6399         struct intel_encoder *encoder;
6400         const intel_limit_t *limit;
6401
6402         for_each_intel_encoder(dev, encoder) {
6403                 if (encoder->new_crtc != crtc)
6404                         continue;
6405
6406                 switch (encoder->type) {
6407                 case INTEL_OUTPUT_LVDS:
6408                         is_lvds = true;
6409                         break;
6410                 case INTEL_OUTPUT_DSI:
6411                         is_dsi = true;
6412                         break;
6413                 default:
6414                         break;
6415                 }
6416
6417                 num_connectors++;
6418         }
6419
6420         if (is_dsi)
6421                 return 0;
6422
6423         if (!crtc->new_config->clock_set) {
6424                 refclk = i9xx_get_refclk(crtc, num_connectors);
6425
6426                 /*
6427                  * Returns a set of divisors for the desired target clock with
6428                  * the given refclk, or FALSE.  The returned values represent
6429                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6430                  * 2) / p1 / p2.
6431                  */
6432                 limit = intel_limit(crtc, refclk);
6433                 ok = dev_priv->display.find_dpll(limit, crtc,
6434                                                  crtc->new_config->port_clock,
6435                                                  refclk, NULL, &clock);
6436                 if (!ok) {
6437                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
6438                         return -EINVAL;
6439                 }
6440
6441                 if (is_lvds && dev_priv->lvds_downclock_avail) {
6442                         /*
6443                          * Ensure we match the reduced clock's P to the target
6444                          * clock.  If the clocks don't match, we can't switch
6445                          * the display clock by using the FP0/FP1. In such case
6446                          * we will disable the LVDS downclock feature.
6447                          */
6448                         has_reduced_clock =
6449                                 dev_priv->display.find_dpll(limit, crtc,
6450                                                             dev_priv->lvds_downclock,
6451                                                             refclk, &clock,
6452                                                             &reduced_clock);
6453                 }
6454                 /* Compat-code for transition, will disappear. */
6455                 crtc->new_config->dpll.n = clock.n;
6456                 crtc->new_config->dpll.m1 = clock.m1;
6457                 crtc->new_config->dpll.m2 = clock.m2;
6458                 crtc->new_config->dpll.p1 = clock.p1;
6459                 crtc->new_config->dpll.p2 = clock.p2;
6460         }
6461
6462         if (IS_GEN2(dev)) {
6463                 i8xx_update_pll(crtc,
6464                                 has_reduced_clock ? &reduced_clock : NULL,
6465                                 num_connectors);
6466         } else if (IS_CHERRYVIEW(dev)) {
6467                 chv_update_pll(crtc, crtc->new_config);
6468         } else if (IS_VALLEYVIEW(dev)) {
6469                 vlv_update_pll(crtc, crtc->new_config);
6470         } else {
6471                 i9xx_update_pll(crtc,
6472                                 has_reduced_clock ? &reduced_clock : NULL,
6473                                 num_connectors);
6474         }
6475
6476         return 0;
6477 }
6478
6479 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6480                                  struct intel_crtc_config *pipe_config)
6481 {
6482         struct drm_device *dev = crtc->base.dev;
6483         struct drm_i915_private *dev_priv = dev->dev_private;
6484         uint32_t tmp;
6485
6486         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6487                 return;
6488
6489         tmp = I915_READ(PFIT_CONTROL);
6490         if (!(tmp & PFIT_ENABLE))
6491                 return;
6492
6493         /* Check whether the pfit is attached to our pipe. */
6494         if (INTEL_INFO(dev)->gen < 4) {
6495                 if (crtc->pipe != PIPE_B)
6496                         return;
6497         } else {
6498                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6499                         return;
6500         }
6501
6502         pipe_config->gmch_pfit.control = tmp;
6503         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6504         if (INTEL_INFO(dev)->gen < 5)
6505                 pipe_config->gmch_pfit.lvds_border_bits =
6506                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6507 }
6508
6509 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6510                                struct intel_crtc_config *pipe_config)
6511 {
6512         struct drm_device *dev = crtc->base.dev;
6513         struct drm_i915_private *dev_priv = dev->dev_private;
6514         int pipe = pipe_config->cpu_transcoder;
6515         intel_clock_t clock;
6516         u32 mdiv;
6517         int refclk = 100000;
6518
6519         /* In case of MIPI DPLL will not even be used */
6520         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6521                 return;
6522
6523         mutex_lock(&dev_priv->dpio_lock);
6524         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6525         mutex_unlock(&dev_priv->dpio_lock);
6526
6527         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6528         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6529         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6530         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6531         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6532
6533         vlv_clock(refclk, &clock);
6534
6535         /* clock.dot is the fast clock */
6536         pipe_config->port_clock = clock.dot / 5;
6537 }
6538
6539 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6540                                   struct intel_plane_config *plane_config)
6541 {
6542         struct drm_device *dev = crtc->base.dev;
6543         struct drm_i915_private *dev_priv = dev->dev_private;
6544         u32 val, base, offset;
6545         int pipe = crtc->pipe, plane = crtc->plane;
6546         int fourcc, pixel_format;
6547         int aligned_height;
6548
6549         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6550         if (!crtc->base.primary->fb) {
6551                 DRM_DEBUG_KMS("failed to alloc fb\n");
6552                 return;
6553         }
6554
6555         val = I915_READ(DSPCNTR(plane));
6556
6557         if (INTEL_INFO(dev)->gen >= 4)
6558                 if (val & DISPPLANE_TILED)
6559                         plane_config->tiled = true;
6560
6561         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6562         fourcc = intel_format_to_fourcc(pixel_format);
6563         crtc->base.primary->fb->pixel_format = fourcc;
6564         crtc->base.primary->fb->bits_per_pixel =
6565                 drm_format_plane_cpp(fourcc, 0) * 8;
6566
6567         if (INTEL_INFO(dev)->gen >= 4) {
6568                 if (plane_config->tiled)
6569                         offset = I915_READ(DSPTILEOFF(plane));
6570                 else
6571                         offset = I915_READ(DSPLINOFF(plane));
6572                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6573         } else {
6574                 base = I915_READ(DSPADDR(plane));
6575         }
6576         plane_config->base = base;
6577
6578         val = I915_READ(PIPESRC(pipe));
6579         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6580         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6581
6582         val = I915_READ(DSPSTRIDE(pipe));
6583         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6584
6585         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6586                                             plane_config->tiled);
6587
6588         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6589                                         aligned_height);
6590
6591         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6592                       pipe, plane, crtc->base.primary->fb->width,
6593                       crtc->base.primary->fb->height,
6594                       crtc->base.primary->fb->bits_per_pixel, base,
6595                       crtc->base.primary->fb->pitches[0],
6596                       plane_config->size);
6597
6598 }
6599
6600 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6601                                struct intel_crtc_config *pipe_config)
6602 {
6603         struct drm_device *dev = crtc->base.dev;
6604         struct drm_i915_private *dev_priv = dev->dev_private;
6605         int pipe = pipe_config->cpu_transcoder;
6606         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6607         intel_clock_t clock;
6608         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6609         int refclk = 100000;
6610
6611         mutex_lock(&dev_priv->dpio_lock);
6612         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6613         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6614         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6615         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6616         mutex_unlock(&dev_priv->dpio_lock);
6617
6618         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6619         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6620         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6621         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6622         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6623
6624         chv_clock(refclk, &clock);
6625
6626         /* clock.dot is the fast clock */
6627         pipe_config->port_clock = clock.dot / 5;
6628 }
6629
6630 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6631                                  struct intel_crtc_config *pipe_config)
6632 {
6633         struct drm_device *dev = crtc->base.dev;
6634         struct drm_i915_private *dev_priv = dev->dev_private;
6635         uint32_t tmp;
6636
6637         if (!intel_display_power_is_enabled(dev_priv,
6638                                             POWER_DOMAIN_PIPE(crtc->pipe)))
6639                 return false;
6640
6641         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6642         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6643
6644         tmp = I915_READ(PIPECONF(crtc->pipe));
6645         if (!(tmp & PIPECONF_ENABLE))
6646                 return false;
6647
6648         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6649                 switch (tmp & PIPECONF_BPC_MASK) {
6650                 case PIPECONF_6BPC:
6651                         pipe_config->pipe_bpp = 18;
6652                         break;
6653                 case PIPECONF_8BPC:
6654                         pipe_config->pipe_bpp = 24;
6655                         break;
6656                 case PIPECONF_10BPC:
6657                         pipe_config->pipe_bpp = 30;
6658                         break;
6659                 default:
6660                         break;
6661                 }
6662         }
6663
6664         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6665                 pipe_config->limited_color_range = true;
6666
6667         if (INTEL_INFO(dev)->gen < 4)
6668                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6669
6670         intel_get_pipe_timings(crtc, pipe_config);
6671
6672         i9xx_get_pfit_config(crtc, pipe_config);
6673
6674         if (INTEL_INFO(dev)->gen >= 4) {
6675                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6676                 pipe_config->pixel_multiplier =
6677                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6678                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6679                 pipe_config->dpll_hw_state.dpll_md = tmp;
6680         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6681                 tmp = I915_READ(DPLL(crtc->pipe));
6682                 pipe_config->pixel_multiplier =
6683                         ((tmp & SDVO_MULTIPLIER_MASK)
6684                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6685         } else {
6686                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6687                  * port and will be fixed up in the encoder->get_config
6688                  * function. */
6689                 pipe_config->pixel_multiplier = 1;
6690         }
6691         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6692         if (!IS_VALLEYVIEW(dev)) {
6693                 /*
6694                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6695                  * on 830. Filter it out here so that we don't
6696                  * report errors due to that.
6697                  */
6698                 if (IS_I830(dev))
6699                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6700
6701                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6702                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6703         } else {
6704                 /* Mask out read-only status bits. */
6705                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6706                                                      DPLL_PORTC_READY_MASK |
6707                                                      DPLL_PORTB_READY_MASK);
6708         }
6709
6710         if (IS_CHERRYVIEW(dev))
6711                 chv_crtc_clock_get(crtc, pipe_config);
6712         else if (IS_VALLEYVIEW(dev))
6713                 vlv_crtc_clock_get(crtc, pipe_config);
6714         else
6715                 i9xx_crtc_clock_get(crtc, pipe_config);
6716
6717         return true;
6718 }
6719
6720 static void ironlake_init_pch_refclk(struct drm_device *dev)
6721 {
6722         struct drm_i915_private *dev_priv = dev->dev_private;
6723         struct intel_encoder *encoder;
6724         u32 val, final;
6725         bool has_lvds = false;
6726         bool has_cpu_edp = false;
6727         bool has_panel = false;
6728         bool has_ck505 = false;
6729         bool can_ssc = false;
6730
6731         /* We need to take the global config into account */
6732         for_each_intel_encoder(dev, encoder) {
6733                 switch (encoder->type) {
6734                 case INTEL_OUTPUT_LVDS:
6735                         has_panel = true;
6736                         has_lvds = true;
6737                         break;
6738                 case INTEL_OUTPUT_EDP:
6739                         has_panel = true;
6740                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6741                                 has_cpu_edp = true;
6742                         break;
6743                 default:
6744                         break;
6745                 }
6746         }
6747
6748         if (HAS_PCH_IBX(dev)) {
6749                 has_ck505 = dev_priv->vbt.display_clock_mode;
6750                 can_ssc = has_ck505;
6751         } else {
6752                 has_ck505 = false;
6753                 can_ssc = true;
6754         }
6755
6756         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6757                       has_panel, has_lvds, has_ck505);
6758
6759         /* Ironlake: try to setup display ref clock before DPLL
6760          * enabling. This is only under driver's control after
6761          * PCH B stepping, previous chipset stepping should be
6762          * ignoring this setting.
6763          */
6764         val = I915_READ(PCH_DREF_CONTROL);
6765
6766         /* As we must carefully and slowly disable/enable each source in turn,
6767          * compute the final state we want first and check if we need to
6768          * make any changes at all.
6769          */
6770         final = val;
6771         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6772         if (has_ck505)
6773                 final |= DREF_NONSPREAD_CK505_ENABLE;
6774         else
6775                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6776
6777         final &= ~DREF_SSC_SOURCE_MASK;
6778         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6779         final &= ~DREF_SSC1_ENABLE;
6780
6781         if (has_panel) {
6782                 final |= DREF_SSC_SOURCE_ENABLE;
6783
6784                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6785                         final |= DREF_SSC1_ENABLE;
6786
6787                 if (has_cpu_edp) {
6788                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6789                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6790                         else
6791                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6792                 } else
6793                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6794         } else {
6795                 final |= DREF_SSC_SOURCE_DISABLE;
6796                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6797         }
6798
6799         if (final == val)
6800                 return;
6801
6802         /* Always enable nonspread source */
6803         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6804
6805         if (has_ck505)
6806                 val |= DREF_NONSPREAD_CK505_ENABLE;
6807         else
6808                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6809
6810         if (has_panel) {
6811                 val &= ~DREF_SSC_SOURCE_MASK;
6812                 val |= DREF_SSC_SOURCE_ENABLE;
6813
6814                 /* SSC must be turned on before enabling the CPU output  */
6815                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6816                         DRM_DEBUG_KMS("Using SSC on panel\n");
6817                         val |= DREF_SSC1_ENABLE;
6818                 } else
6819                         val &= ~DREF_SSC1_ENABLE;
6820
6821                 /* Get SSC going before enabling the outputs */
6822                 I915_WRITE(PCH_DREF_CONTROL, val);
6823                 POSTING_READ(PCH_DREF_CONTROL);
6824                 udelay(200);
6825
6826                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6827
6828                 /* Enable CPU source on CPU attached eDP */
6829                 if (has_cpu_edp) {
6830                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6831                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6832                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6833                         } else
6834                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6835                 } else
6836                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6837
6838                 I915_WRITE(PCH_DREF_CONTROL, val);
6839                 POSTING_READ(PCH_DREF_CONTROL);
6840                 udelay(200);
6841         } else {
6842                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6843
6844                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6845
6846                 /* Turn off CPU output */
6847                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6848
6849                 I915_WRITE(PCH_DREF_CONTROL, val);
6850                 POSTING_READ(PCH_DREF_CONTROL);
6851                 udelay(200);
6852
6853                 /* Turn off the SSC source */
6854                 val &= ~DREF_SSC_SOURCE_MASK;
6855                 val |= DREF_SSC_SOURCE_DISABLE;
6856
6857                 /* Turn off SSC1 */
6858                 val &= ~DREF_SSC1_ENABLE;
6859
6860                 I915_WRITE(PCH_DREF_CONTROL, val);
6861                 POSTING_READ(PCH_DREF_CONTROL);
6862                 udelay(200);
6863         }
6864
6865         BUG_ON(val != final);
6866 }
6867
6868 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6869 {
6870         uint32_t tmp;
6871
6872         tmp = I915_READ(SOUTH_CHICKEN2);
6873         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6874         I915_WRITE(SOUTH_CHICKEN2, tmp);
6875
6876         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6877                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6878                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6879
6880         tmp = I915_READ(SOUTH_CHICKEN2);
6881         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6882         I915_WRITE(SOUTH_CHICKEN2, tmp);
6883
6884         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6885                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6886                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6887 }
6888
6889 /* WaMPhyProgramming:hsw */
6890 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6891 {
6892         uint32_t tmp;
6893
6894         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6895         tmp &= ~(0xFF << 24);
6896         tmp |= (0x12 << 24);
6897         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6898
6899         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6900         tmp |= (1 << 11);
6901         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6902
6903         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6904         tmp |= (1 << 11);
6905         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6906
6907         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6908         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6909         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6910
6911         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6912         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6913         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6914
6915         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6916         tmp &= ~(7 << 13);
6917         tmp |= (5 << 13);
6918         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6919
6920         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6921         tmp &= ~(7 << 13);
6922         tmp |= (5 << 13);
6923         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6924
6925         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6926         tmp &= ~0xFF;
6927         tmp |= 0x1C;
6928         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6929
6930         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6931         tmp &= ~0xFF;
6932         tmp |= 0x1C;
6933         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6934
6935         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6936         tmp &= ~(0xFF << 16);
6937         tmp |= (0x1C << 16);
6938         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6939
6940         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6941         tmp &= ~(0xFF << 16);
6942         tmp |= (0x1C << 16);
6943         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6944
6945         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6946         tmp |= (1 << 27);
6947         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6948
6949         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6950         tmp |= (1 << 27);
6951         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6952
6953         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6954         tmp &= ~(0xF << 28);
6955         tmp |= (4 << 28);
6956         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6957
6958         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6959         tmp &= ~(0xF << 28);
6960         tmp |= (4 << 28);
6961         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6962 }
6963
6964 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6965  * Programming" based on the parameters passed:
6966  * - Sequence to enable CLKOUT_DP
6967  * - Sequence to enable CLKOUT_DP without spread
6968  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6969  */
6970 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6971                                  bool with_fdi)
6972 {
6973         struct drm_i915_private *dev_priv = dev->dev_private;
6974         uint32_t reg, tmp;
6975
6976         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6977                 with_spread = true;
6978         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6979                  with_fdi, "LP PCH doesn't have FDI\n"))
6980                 with_fdi = false;
6981
6982         mutex_lock(&dev_priv->dpio_lock);
6983
6984         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6985         tmp &= ~SBI_SSCCTL_DISABLE;
6986         tmp |= SBI_SSCCTL_PATHALT;
6987         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6988
6989         udelay(24);
6990
6991         if (with_spread) {
6992                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6993                 tmp &= ~SBI_SSCCTL_PATHALT;
6994                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6995
6996                 if (with_fdi) {
6997                         lpt_reset_fdi_mphy(dev_priv);
6998                         lpt_program_fdi_mphy(dev_priv);
6999                 }
7000         }
7001
7002         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7003                SBI_GEN0 : SBI_DBUFF0;
7004         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7005         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7006         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7007
7008         mutex_unlock(&dev_priv->dpio_lock);
7009 }
7010
7011 /* Sequence to disable CLKOUT_DP */
7012 static void lpt_disable_clkout_dp(struct drm_device *dev)
7013 {
7014         struct drm_i915_private *dev_priv = dev->dev_private;
7015         uint32_t reg, tmp;
7016
7017         mutex_lock(&dev_priv->dpio_lock);
7018
7019         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7020                SBI_GEN0 : SBI_DBUFF0;
7021         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7022         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7023         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7024
7025         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7026         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7027                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7028                         tmp |= SBI_SSCCTL_PATHALT;
7029                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7030                         udelay(32);
7031                 }
7032                 tmp |= SBI_SSCCTL_DISABLE;
7033                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7034         }
7035
7036         mutex_unlock(&dev_priv->dpio_lock);
7037 }
7038
7039 static void lpt_init_pch_refclk(struct drm_device *dev)
7040 {
7041         struct intel_encoder *encoder;
7042         bool has_vga = false;
7043
7044         for_each_intel_encoder(dev, encoder) {
7045                 switch (encoder->type) {
7046                 case INTEL_OUTPUT_ANALOG:
7047                         has_vga = true;
7048                         break;
7049                 default:
7050                         break;
7051                 }
7052         }
7053
7054         if (has_vga)
7055                 lpt_enable_clkout_dp(dev, true, true);
7056         else
7057                 lpt_disable_clkout_dp(dev);
7058 }
7059
7060 /*
7061  * Initialize reference clocks when the driver loads
7062  */
7063 void intel_init_pch_refclk(struct drm_device *dev)
7064 {
7065         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7066                 ironlake_init_pch_refclk(dev);
7067         else if (HAS_PCH_LPT(dev))
7068                 lpt_init_pch_refclk(dev);
7069 }
7070
7071 static int ironlake_get_refclk(struct drm_crtc *crtc)
7072 {
7073         struct drm_device *dev = crtc->dev;
7074         struct drm_i915_private *dev_priv = dev->dev_private;
7075         struct intel_encoder *encoder;
7076         int num_connectors = 0;
7077         bool is_lvds = false;
7078
7079         for_each_intel_encoder(dev, encoder) {
7080                 if (encoder->new_crtc != to_intel_crtc(crtc))
7081                         continue;
7082
7083                 switch (encoder->type) {
7084                 case INTEL_OUTPUT_LVDS:
7085                         is_lvds = true;
7086                         break;
7087                 default:
7088                         break;
7089                 }
7090                 num_connectors++;
7091         }
7092
7093         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7094                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7095                               dev_priv->vbt.lvds_ssc_freq);
7096                 return dev_priv->vbt.lvds_ssc_freq;
7097         }
7098
7099         return 120000;
7100 }
7101
7102 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7103 {
7104         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7105         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7106         int pipe = intel_crtc->pipe;
7107         uint32_t val;
7108
7109         val = 0;
7110
7111         switch (intel_crtc->config.pipe_bpp) {
7112         case 18:
7113                 val |= PIPECONF_6BPC;
7114                 break;
7115         case 24:
7116                 val |= PIPECONF_8BPC;
7117                 break;
7118         case 30:
7119                 val |= PIPECONF_10BPC;
7120                 break;
7121         case 36:
7122                 val |= PIPECONF_12BPC;
7123                 break;
7124         default:
7125                 /* Case prevented by intel_choose_pipe_bpp_dither. */
7126                 BUG();
7127         }
7128
7129         if (intel_crtc->config.dither)
7130                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7131
7132         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7133                 val |= PIPECONF_INTERLACED_ILK;
7134         else
7135                 val |= PIPECONF_PROGRESSIVE;
7136
7137         if (intel_crtc->config.limited_color_range)
7138                 val |= PIPECONF_COLOR_RANGE_SELECT;
7139
7140         I915_WRITE(PIPECONF(pipe), val);
7141         POSTING_READ(PIPECONF(pipe));
7142 }
7143
7144 /*
7145  * Set up the pipe CSC unit.
7146  *
7147  * Currently only full range RGB to limited range RGB conversion
7148  * is supported, but eventually this should handle various
7149  * RGB<->YCbCr scenarios as well.
7150  */
7151 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7152 {
7153         struct drm_device *dev = crtc->dev;
7154         struct drm_i915_private *dev_priv = dev->dev_private;
7155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7156         int pipe = intel_crtc->pipe;
7157         uint16_t coeff = 0x7800; /* 1.0 */
7158
7159         /*
7160          * TODO: Check what kind of values actually come out of the pipe
7161          * with these coeff/postoff values and adjust to get the best
7162          * accuracy. Perhaps we even need to take the bpc value into
7163          * consideration.
7164          */
7165
7166         if (intel_crtc->config.limited_color_range)
7167                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7168
7169         /*
7170          * GY/GU and RY/RU should be the other way around according
7171          * to BSpec, but reality doesn't agree. Just set them up in
7172          * a way that results in the correct picture.
7173          */
7174         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7175         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7176
7177         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7178         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7179
7180         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7181         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7182
7183         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7184         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7185         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7186
7187         if (INTEL_INFO(dev)->gen > 6) {
7188                 uint16_t postoff = 0;
7189
7190                 if (intel_crtc->config.limited_color_range)
7191                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
7192
7193                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7194                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7195                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7196
7197                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7198         } else {
7199                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7200
7201                 if (intel_crtc->config.limited_color_range)
7202                         mode |= CSC_BLACK_SCREEN_OFFSET;
7203
7204                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7205         }
7206 }
7207
7208 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7209 {
7210         struct drm_device *dev = crtc->dev;
7211         struct drm_i915_private *dev_priv = dev->dev_private;
7212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7213         enum pipe pipe = intel_crtc->pipe;
7214         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7215         uint32_t val;
7216
7217         val = 0;
7218
7219         if (IS_HASWELL(dev) && intel_crtc->config.dither)
7220                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7221
7222         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7223                 val |= PIPECONF_INTERLACED_ILK;
7224         else
7225                 val |= PIPECONF_PROGRESSIVE;
7226
7227         I915_WRITE(PIPECONF(cpu_transcoder), val);
7228         POSTING_READ(PIPECONF(cpu_transcoder));
7229
7230         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7231         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7232
7233         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7234                 val = 0;
7235
7236                 switch (intel_crtc->config.pipe_bpp) {
7237                 case 18:
7238                         val |= PIPEMISC_DITHER_6_BPC;
7239                         break;
7240                 case 24:
7241                         val |= PIPEMISC_DITHER_8_BPC;
7242                         break;
7243                 case 30:
7244                         val |= PIPEMISC_DITHER_10_BPC;
7245                         break;
7246                 case 36:
7247                         val |= PIPEMISC_DITHER_12_BPC;
7248                         break;
7249                 default:
7250                         /* Case prevented by pipe_config_set_bpp. */
7251                         BUG();
7252                 }
7253
7254                 if (intel_crtc->config.dither)
7255                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7256
7257                 I915_WRITE(PIPEMISC(pipe), val);
7258         }
7259 }
7260
7261 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7262                                     intel_clock_t *clock,
7263                                     bool *has_reduced_clock,
7264                                     intel_clock_t *reduced_clock)
7265 {
7266         struct drm_device *dev = crtc->dev;
7267         struct drm_i915_private *dev_priv = dev->dev_private;
7268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7269         int refclk;
7270         const intel_limit_t *limit;
7271         bool ret, is_lvds = false;
7272
7273         is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7274
7275         refclk = ironlake_get_refclk(crtc);
7276
7277         /*
7278          * Returns a set of divisors for the desired target clock with the given
7279          * refclk, or FALSE.  The returned values represent the clock equation:
7280          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7281          */
7282         limit = intel_limit(intel_crtc, refclk);
7283         ret = dev_priv->display.find_dpll(limit, intel_crtc,
7284                                           intel_crtc->new_config->port_clock,
7285                                           refclk, NULL, clock);
7286         if (!ret)
7287                 return false;
7288
7289         if (is_lvds && dev_priv->lvds_downclock_avail) {
7290                 /*
7291                  * Ensure we match the reduced clock's P to the target clock.
7292                  * If the clocks don't match, we can't switch the display clock
7293                  * by using the FP0/FP1. In such case we will disable the LVDS
7294                  * downclock feature.
7295                 */
7296                 *has_reduced_clock =
7297                         dev_priv->display.find_dpll(limit, intel_crtc,
7298                                                     dev_priv->lvds_downclock,
7299                                                     refclk, clock,
7300                                                     reduced_clock);
7301         }
7302
7303         return true;
7304 }
7305
7306 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7307 {
7308         /*
7309          * Account for spread spectrum to avoid
7310          * oversubscribing the link. Max center spread
7311          * is 2.5%; use 5% for safety's sake.
7312          */
7313         u32 bps = target_clock * bpp * 21 / 20;
7314         return DIV_ROUND_UP(bps, link_bw * 8);
7315 }
7316
7317 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7318 {
7319         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7320 }
7321
7322 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7323                                       u32 *fp,
7324                                       intel_clock_t *reduced_clock, u32 *fp2)
7325 {
7326         struct drm_crtc *crtc = &intel_crtc->base;
7327         struct drm_device *dev = crtc->dev;
7328         struct drm_i915_private *dev_priv = dev->dev_private;
7329         struct intel_encoder *intel_encoder;
7330         uint32_t dpll;
7331         int factor, num_connectors = 0;
7332         bool is_lvds = false, is_sdvo = false;
7333
7334         for_each_intel_encoder(dev, intel_encoder) {
7335                 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7336                         continue;
7337
7338                 switch (intel_encoder->type) {
7339                 case INTEL_OUTPUT_LVDS:
7340                         is_lvds = true;
7341                         break;
7342                 case INTEL_OUTPUT_SDVO:
7343                 case INTEL_OUTPUT_HDMI:
7344                         is_sdvo = true;
7345                         break;
7346                 default:
7347                         break;
7348                 }
7349
7350                 num_connectors++;
7351         }
7352
7353         /* Enable autotuning of the PLL clock (if permissible) */
7354         factor = 21;
7355         if (is_lvds) {
7356                 if ((intel_panel_use_ssc(dev_priv) &&
7357                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
7358                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7359                         factor = 25;
7360         } else if (intel_crtc->new_config->sdvo_tv_clock)
7361                 factor = 20;
7362
7363         if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7364                 *fp |= FP_CB_TUNE;
7365
7366         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7367                 *fp2 |= FP_CB_TUNE;
7368
7369         dpll = 0;
7370
7371         if (is_lvds)
7372                 dpll |= DPLLB_MODE_LVDS;
7373         else
7374                 dpll |= DPLLB_MODE_DAC_SERIAL;
7375
7376         dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7377                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7378
7379         if (is_sdvo)
7380                 dpll |= DPLL_SDVO_HIGH_SPEED;
7381         if (intel_crtc->new_config->has_dp_encoder)
7382                 dpll |= DPLL_SDVO_HIGH_SPEED;
7383
7384         /* compute bitmask from p1 value */
7385         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7386         /* also FPA1 */
7387         dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7388
7389         switch (intel_crtc->new_config->dpll.p2) {
7390         case 5:
7391                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7392                 break;
7393         case 7:
7394                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7395                 break;
7396         case 10:
7397                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7398                 break;
7399         case 14:
7400                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7401                 break;
7402         }
7403
7404         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7405                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7406         else
7407                 dpll |= PLL_REF_INPUT_DREFCLK;
7408
7409         return dpll | DPLL_VCO_ENABLE;
7410 }
7411
7412 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7413 {
7414         struct drm_device *dev = crtc->base.dev;
7415         intel_clock_t clock, reduced_clock;
7416         u32 dpll = 0, fp = 0, fp2 = 0;
7417         bool ok, has_reduced_clock = false;
7418         bool is_lvds = false;
7419         struct intel_shared_dpll *pll;
7420
7421         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7422
7423         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7424              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7425
7426         ok = ironlake_compute_clocks(&crtc->base, &clock,
7427                                      &has_reduced_clock, &reduced_clock);
7428         if (!ok && !crtc->new_config->clock_set) {
7429                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7430                 return -EINVAL;
7431         }
7432         /* Compat-code for transition, will disappear. */
7433         if (!crtc->new_config->clock_set) {
7434                 crtc->new_config->dpll.n = clock.n;
7435                 crtc->new_config->dpll.m1 = clock.m1;
7436                 crtc->new_config->dpll.m2 = clock.m2;
7437                 crtc->new_config->dpll.p1 = clock.p1;
7438                 crtc->new_config->dpll.p2 = clock.p2;
7439         }
7440
7441         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7442         if (crtc->new_config->has_pch_encoder) {
7443                 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7444                 if (has_reduced_clock)
7445                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7446
7447                 dpll = ironlake_compute_dpll(crtc,
7448                                              &fp, &reduced_clock,
7449                                              has_reduced_clock ? &fp2 : NULL);
7450
7451                 crtc->new_config->dpll_hw_state.dpll = dpll;
7452                 crtc->new_config->dpll_hw_state.fp0 = fp;
7453                 if (has_reduced_clock)
7454                         crtc->new_config->dpll_hw_state.fp1 = fp2;
7455                 else
7456                         crtc->new_config->dpll_hw_state.fp1 = fp;
7457
7458                 pll = intel_get_shared_dpll(crtc);
7459                 if (pll == NULL) {
7460                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7461                                          pipe_name(crtc->pipe));
7462                         return -EINVAL;
7463                 }
7464         }
7465
7466         if (is_lvds && has_reduced_clock && i915.powersave)
7467                 crtc->lowfreq_avail = true;
7468         else
7469                 crtc->lowfreq_avail = false;
7470
7471         return 0;
7472 }
7473
7474 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7475                                          struct intel_link_m_n *m_n)
7476 {
7477         struct drm_device *dev = crtc->base.dev;
7478         struct drm_i915_private *dev_priv = dev->dev_private;
7479         enum pipe pipe = crtc->pipe;
7480
7481         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7482         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7483         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7484                 & ~TU_SIZE_MASK;
7485         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7486         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7487                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7488 }
7489
7490 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7491                                          enum transcoder transcoder,
7492                                          struct intel_link_m_n *m_n,
7493                                          struct intel_link_m_n *m2_n2)
7494 {
7495         struct drm_device *dev = crtc->base.dev;
7496         struct drm_i915_private *dev_priv = dev->dev_private;
7497         enum pipe pipe = crtc->pipe;
7498
7499         if (INTEL_INFO(dev)->gen >= 5) {
7500                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7501                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7502                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7503                         & ~TU_SIZE_MASK;
7504                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7505                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7506                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7507                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7508                  * gen < 8) and if DRRS is supported (to make sure the
7509                  * registers are not unnecessarily read).
7510                  */
7511                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7512                         crtc->config.has_drrs) {
7513                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7514                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7515                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7516                                         & ~TU_SIZE_MASK;
7517                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7518                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7519                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7520                 }
7521         } else {
7522                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7523                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7524                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7525                         & ~TU_SIZE_MASK;
7526                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7527                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7528                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7529         }
7530 }
7531
7532 void intel_dp_get_m_n(struct intel_crtc *crtc,
7533                       struct intel_crtc_config *pipe_config)
7534 {
7535         if (crtc->config.has_pch_encoder)
7536                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7537         else
7538                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7539                                              &pipe_config->dp_m_n,
7540                                              &pipe_config->dp_m2_n2);
7541 }
7542
7543 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7544                                         struct intel_crtc_config *pipe_config)
7545 {
7546         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7547                                      &pipe_config->fdi_m_n, NULL);
7548 }
7549
7550 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7551                                      struct intel_crtc_config *pipe_config)
7552 {
7553         struct drm_device *dev = crtc->base.dev;
7554         struct drm_i915_private *dev_priv = dev->dev_private;
7555         uint32_t tmp;
7556
7557         tmp = I915_READ(PF_CTL(crtc->pipe));
7558
7559         if (tmp & PF_ENABLE) {
7560                 pipe_config->pch_pfit.enabled = true;
7561                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7562                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7563
7564                 /* We currently do not free assignements of panel fitters on
7565                  * ivb/hsw (since we don't use the higher upscaling modes which
7566                  * differentiates them) so just WARN about this case for now. */
7567                 if (IS_GEN7(dev)) {
7568                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7569                                 PF_PIPE_SEL_IVB(crtc->pipe));
7570                 }
7571         }
7572 }
7573
7574 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7575                                       struct intel_plane_config *plane_config)
7576 {
7577         struct drm_device *dev = crtc->base.dev;
7578         struct drm_i915_private *dev_priv = dev->dev_private;
7579         u32 val, base, offset;
7580         int pipe = crtc->pipe, plane = crtc->plane;
7581         int fourcc, pixel_format;
7582         int aligned_height;
7583
7584         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7585         if (!crtc->base.primary->fb) {
7586                 DRM_DEBUG_KMS("failed to alloc fb\n");
7587                 return;
7588         }
7589
7590         val = I915_READ(DSPCNTR(plane));
7591
7592         if (INTEL_INFO(dev)->gen >= 4)
7593                 if (val & DISPPLANE_TILED)
7594                         plane_config->tiled = true;
7595
7596         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7597         fourcc = intel_format_to_fourcc(pixel_format);
7598         crtc->base.primary->fb->pixel_format = fourcc;
7599         crtc->base.primary->fb->bits_per_pixel =
7600                 drm_format_plane_cpp(fourcc, 0) * 8;
7601
7602         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7603         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7604                 offset = I915_READ(DSPOFFSET(plane));
7605         } else {
7606                 if (plane_config->tiled)
7607                         offset = I915_READ(DSPTILEOFF(plane));
7608                 else
7609                         offset = I915_READ(DSPLINOFF(plane));
7610         }
7611         plane_config->base = base;
7612
7613         val = I915_READ(PIPESRC(pipe));
7614         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7615         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7616
7617         val = I915_READ(DSPSTRIDE(pipe));
7618         crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7619
7620         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7621                                             plane_config->tiled);
7622
7623         plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7624                                         aligned_height);
7625
7626         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7627                       pipe, plane, crtc->base.primary->fb->width,
7628                       crtc->base.primary->fb->height,
7629                       crtc->base.primary->fb->bits_per_pixel, base,
7630                       crtc->base.primary->fb->pitches[0],
7631                       plane_config->size);
7632 }
7633
7634 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7635                                      struct intel_crtc_config *pipe_config)
7636 {
7637         struct drm_device *dev = crtc->base.dev;
7638         struct drm_i915_private *dev_priv = dev->dev_private;
7639         uint32_t tmp;
7640
7641         if (!intel_display_power_is_enabled(dev_priv,
7642                                             POWER_DOMAIN_PIPE(crtc->pipe)))
7643                 return false;
7644
7645         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7646         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7647
7648         tmp = I915_READ(PIPECONF(crtc->pipe));
7649         if (!(tmp & PIPECONF_ENABLE))
7650                 return false;
7651
7652         switch (tmp & PIPECONF_BPC_MASK) {
7653         case PIPECONF_6BPC:
7654                 pipe_config->pipe_bpp = 18;
7655                 break;
7656         case PIPECONF_8BPC:
7657                 pipe_config->pipe_bpp = 24;
7658                 break;
7659         case PIPECONF_10BPC:
7660                 pipe_config->pipe_bpp = 30;
7661                 break;
7662         case PIPECONF_12BPC:
7663                 pipe_config->pipe_bpp = 36;
7664                 break;
7665         default:
7666                 break;
7667         }
7668
7669         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7670                 pipe_config->limited_color_range = true;
7671
7672         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7673                 struct intel_shared_dpll *pll;
7674
7675                 pipe_config->has_pch_encoder = true;
7676
7677                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7678                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7679                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7680
7681                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7682
7683                 if (HAS_PCH_IBX(dev_priv->dev)) {
7684                         pipe_config->shared_dpll =
7685                                 (enum intel_dpll_id) crtc->pipe;
7686                 } else {
7687                         tmp = I915_READ(PCH_DPLL_SEL);
7688                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7689                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7690                         else
7691                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7692                 }
7693
7694                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7695
7696                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7697                                            &pipe_config->dpll_hw_state));
7698
7699                 tmp = pipe_config->dpll_hw_state.dpll;
7700                 pipe_config->pixel_multiplier =
7701                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7702                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7703
7704                 ironlake_pch_clock_get(crtc, pipe_config);
7705         } else {
7706                 pipe_config->pixel_multiplier = 1;
7707         }
7708
7709         intel_get_pipe_timings(crtc, pipe_config);
7710
7711         ironlake_get_pfit_config(crtc, pipe_config);
7712
7713         return true;
7714 }
7715
7716 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7717 {
7718         struct drm_device *dev = dev_priv->dev;
7719         struct intel_crtc *crtc;
7720
7721         for_each_intel_crtc(dev, crtc)
7722                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7723                      pipe_name(crtc->pipe));
7724
7725         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7726         WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7727         WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7728         WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7729         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7730         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7731              "CPU PWM1 enabled\n");
7732         if (IS_HASWELL(dev))
7733                 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7734                      "CPU PWM2 enabled\n");
7735         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7736              "PCH PWM1 enabled\n");
7737         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7738              "Utility pin enabled\n");
7739         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7740
7741         /*
7742          * In theory we can still leave IRQs enabled, as long as only the HPD
7743          * interrupts remain enabled. We used to check for that, but since it's
7744          * gen-specific and since we only disable LCPLL after we fully disable
7745          * the interrupts, the check below should be enough.
7746          */
7747         WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7748 }
7749
7750 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7751 {
7752         struct drm_device *dev = dev_priv->dev;
7753
7754         if (IS_HASWELL(dev))
7755                 return I915_READ(D_COMP_HSW);
7756         else
7757                 return I915_READ(D_COMP_BDW);
7758 }
7759
7760 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7761 {
7762         struct drm_device *dev = dev_priv->dev;
7763
7764         if (IS_HASWELL(dev)) {
7765                 mutex_lock(&dev_priv->rps.hw_lock);
7766                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7767                                             val))
7768                         DRM_ERROR("Failed to write to D_COMP\n");
7769                 mutex_unlock(&dev_priv->rps.hw_lock);
7770         } else {
7771                 I915_WRITE(D_COMP_BDW, val);
7772                 POSTING_READ(D_COMP_BDW);
7773         }
7774 }
7775
7776 /*
7777  * This function implements pieces of two sequences from BSpec:
7778  * - Sequence for display software to disable LCPLL
7779  * - Sequence for display software to allow package C8+
7780  * The steps implemented here are just the steps that actually touch the LCPLL
7781  * register. Callers should take care of disabling all the display engine
7782  * functions, doing the mode unset, fixing interrupts, etc.
7783  */
7784 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7785                               bool switch_to_fclk, bool allow_power_down)
7786 {
7787         uint32_t val;
7788
7789         assert_can_disable_lcpll(dev_priv);
7790
7791         val = I915_READ(LCPLL_CTL);
7792
7793         if (switch_to_fclk) {
7794                 val |= LCPLL_CD_SOURCE_FCLK;
7795                 I915_WRITE(LCPLL_CTL, val);
7796
7797                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7798                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7799                         DRM_ERROR("Switching to FCLK failed\n");
7800
7801                 val = I915_READ(LCPLL_CTL);
7802         }
7803
7804         val |= LCPLL_PLL_DISABLE;
7805         I915_WRITE(LCPLL_CTL, val);
7806         POSTING_READ(LCPLL_CTL);
7807
7808         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7809                 DRM_ERROR("LCPLL still locked\n");
7810
7811         val = hsw_read_dcomp(dev_priv);
7812         val |= D_COMP_COMP_DISABLE;
7813         hsw_write_dcomp(dev_priv, val);
7814         ndelay(100);
7815
7816         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7817                      1))
7818                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7819
7820         if (allow_power_down) {
7821                 val = I915_READ(LCPLL_CTL);
7822                 val |= LCPLL_POWER_DOWN_ALLOW;
7823                 I915_WRITE(LCPLL_CTL, val);
7824                 POSTING_READ(LCPLL_CTL);
7825         }
7826 }
7827
7828 /*
7829  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7830  * source.
7831  */
7832 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7833 {
7834         uint32_t val;
7835
7836         val = I915_READ(LCPLL_CTL);
7837
7838         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7839                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7840                 return;
7841
7842         /*
7843          * Make sure we're not on PC8 state before disabling PC8, otherwise
7844          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7845          *
7846          * The other problem is that hsw_restore_lcpll() is called as part of
7847          * the runtime PM resume sequence, so we can't just call
7848          * gen6_gt_force_wake_get() because that function calls
7849          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7850          * while we are on the resume sequence. So to solve this problem we have
7851          * to call special forcewake code that doesn't touch runtime PM and
7852          * doesn't enable the forcewake delayed work.
7853          */
7854         spin_lock_irq(&dev_priv->uncore.lock);
7855         if (dev_priv->uncore.forcewake_count++ == 0)
7856                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7857         spin_unlock_irq(&dev_priv->uncore.lock);
7858
7859         if (val & LCPLL_POWER_DOWN_ALLOW) {
7860                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7861                 I915_WRITE(LCPLL_CTL, val);
7862                 POSTING_READ(LCPLL_CTL);
7863         }
7864
7865         val = hsw_read_dcomp(dev_priv);
7866         val |= D_COMP_COMP_FORCE;
7867         val &= ~D_COMP_COMP_DISABLE;
7868         hsw_write_dcomp(dev_priv, val);
7869
7870         val = I915_READ(LCPLL_CTL);
7871         val &= ~LCPLL_PLL_DISABLE;
7872         I915_WRITE(LCPLL_CTL, val);
7873
7874         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7875                 DRM_ERROR("LCPLL not locked yet\n");
7876
7877         if (val & LCPLL_CD_SOURCE_FCLK) {
7878                 val = I915_READ(LCPLL_CTL);
7879                 val &= ~LCPLL_CD_SOURCE_FCLK;
7880                 I915_WRITE(LCPLL_CTL, val);
7881
7882                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7883                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7884                         DRM_ERROR("Switching back to LCPLL failed\n");
7885         }
7886
7887         /* See the big comment above. */
7888         spin_lock_irq(&dev_priv->uncore.lock);
7889         if (--dev_priv->uncore.forcewake_count == 0)
7890                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7891         spin_unlock_irq(&dev_priv->uncore.lock);
7892 }
7893
7894 /*
7895  * Package states C8 and deeper are really deep PC states that can only be
7896  * reached when all the devices on the system allow it, so even if the graphics
7897  * device allows PC8+, it doesn't mean the system will actually get to these
7898  * states. Our driver only allows PC8+ when going into runtime PM.
7899  *
7900  * The requirements for PC8+ are that all the outputs are disabled, the power
7901  * well is disabled and most interrupts are disabled, and these are also
7902  * requirements for runtime PM. When these conditions are met, we manually do
7903  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7904  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7905  * hang the machine.
7906  *
7907  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7908  * the state of some registers, so when we come back from PC8+ we need to
7909  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7910  * need to take care of the registers kept by RC6. Notice that this happens even
7911  * if we don't put the device in PCI D3 state (which is what currently happens
7912  * because of the runtime PM support).
7913  *
7914  * For more, read "Display Sequences for Package C8" on the hardware
7915  * documentation.
7916  */
7917 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7918 {
7919         struct drm_device *dev = dev_priv->dev;
7920         uint32_t val;
7921
7922         DRM_DEBUG_KMS("Enabling package C8+\n");
7923
7924         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7925                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7926                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7927                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7928         }
7929
7930         lpt_disable_clkout_dp(dev);
7931         hsw_disable_lcpll(dev_priv, true, true);
7932 }
7933
7934 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7935 {
7936         struct drm_device *dev = dev_priv->dev;
7937         uint32_t val;
7938
7939         DRM_DEBUG_KMS("Disabling package C8+\n");
7940
7941         hsw_restore_lcpll(dev_priv);
7942         lpt_init_pch_refclk(dev);
7943
7944         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7945                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7946                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7947                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7948         }
7949
7950         intel_prepare_ddi(dev);
7951 }
7952
7953 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7954 {
7955         if (!intel_ddi_pll_select(crtc))
7956                 return -EINVAL;
7957
7958         crtc->lowfreq_avail = false;
7959
7960         return 0;
7961 }
7962
7963 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7964                                 enum port port,
7965                                 struct intel_crtc_config *pipe_config)
7966 {
7967         u32 temp;
7968
7969         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7970         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7971
7972         switch (pipe_config->ddi_pll_sel) {
7973         case SKL_DPLL1:
7974                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
7975                 break;
7976         case SKL_DPLL2:
7977                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
7978                 break;
7979         case SKL_DPLL3:
7980                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
7981                 break;
7982         default:
7983                 WARN(1, "Unknown DPLL programmed\n");
7984         }
7985 }
7986
7987 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7988                                 enum port port,
7989                                 struct intel_crtc_config *pipe_config)
7990 {
7991         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7992
7993         switch (pipe_config->ddi_pll_sel) {
7994         case PORT_CLK_SEL_WRPLL1:
7995                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7996                 break;
7997         case PORT_CLK_SEL_WRPLL2:
7998                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7999                 break;
8000         }
8001 }
8002
8003 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8004                                        struct intel_crtc_config *pipe_config)
8005 {
8006         struct drm_device *dev = crtc->base.dev;
8007         struct drm_i915_private *dev_priv = dev->dev_private;
8008         struct intel_shared_dpll *pll;
8009         enum port port;
8010         uint32_t tmp;
8011
8012         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8013
8014         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8015
8016         if (IS_SKYLAKE(dev))
8017                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8018         else
8019                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8020
8021         if (pipe_config->shared_dpll >= 0) {
8022                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8023
8024                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8025                                            &pipe_config->dpll_hw_state));
8026         }
8027
8028         /*
8029          * Haswell has only FDI/PCH transcoder A. It is which is connected to
8030          * DDI E. So just check whether this pipe is wired to DDI E and whether
8031          * the PCH transcoder is on.
8032          */
8033         if (INTEL_INFO(dev)->gen < 9 &&
8034             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8035                 pipe_config->has_pch_encoder = true;
8036
8037                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8038                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8039                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8040
8041                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8042         }
8043 }
8044
8045 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8046                                     struct intel_crtc_config *pipe_config)
8047 {
8048         struct drm_device *dev = crtc->base.dev;
8049         struct drm_i915_private *dev_priv = dev->dev_private;
8050         enum intel_display_power_domain pfit_domain;
8051         uint32_t tmp;
8052
8053         if (!intel_display_power_is_enabled(dev_priv,
8054                                          POWER_DOMAIN_PIPE(crtc->pipe)))
8055                 return false;
8056
8057         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8058         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8059
8060         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8061         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8062                 enum pipe trans_edp_pipe;
8063                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8064                 default:
8065                         WARN(1, "unknown pipe linked to edp transcoder\n");
8066                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8067                 case TRANS_DDI_EDP_INPUT_A_ON:
8068                         trans_edp_pipe = PIPE_A;
8069                         break;
8070                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8071                         trans_edp_pipe = PIPE_B;
8072                         break;
8073                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8074                         trans_edp_pipe = PIPE_C;
8075                         break;
8076                 }
8077
8078                 if (trans_edp_pipe == crtc->pipe)
8079                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8080         }
8081
8082         if (!intel_display_power_is_enabled(dev_priv,
8083                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8084                 return false;
8085
8086         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8087         if (!(tmp & PIPECONF_ENABLE))
8088                 return false;
8089
8090         haswell_get_ddi_port_state(crtc, pipe_config);
8091
8092         intel_get_pipe_timings(crtc, pipe_config);
8093
8094         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8095         if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8096                 ironlake_get_pfit_config(crtc, pipe_config);
8097
8098         if (IS_HASWELL(dev))
8099                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8100                         (I915_READ(IPS_CTL) & IPS_ENABLE);
8101
8102         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8103                 pipe_config->pixel_multiplier =
8104                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8105         } else {
8106                 pipe_config->pixel_multiplier = 1;
8107         }
8108
8109         return true;
8110 }
8111
8112 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8113 {
8114         struct drm_device *dev = crtc->dev;
8115         struct drm_i915_private *dev_priv = dev->dev_private;
8116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8117         uint32_t cntl = 0, size = 0;
8118
8119         if (base) {
8120                 unsigned int width = intel_crtc->cursor_width;
8121                 unsigned int height = intel_crtc->cursor_height;
8122                 unsigned int stride = roundup_pow_of_two(width) * 4;
8123
8124                 switch (stride) {
8125                 default:
8126                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8127                                   width, stride);
8128                         stride = 256;
8129                         /* fallthrough */
8130                 case 256:
8131                 case 512:
8132                 case 1024:
8133                 case 2048:
8134                         break;
8135                 }
8136
8137                 cntl |= CURSOR_ENABLE |
8138                         CURSOR_GAMMA_ENABLE |
8139                         CURSOR_FORMAT_ARGB |
8140                         CURSOR_STRIDE(stride);
8141
8142                 size = (height << 12) | width;
8143         }
8144
8145         if (intel_crtc->cursor_cntl != 0 &&
8146             (intel_crtc->cursor_base != base ||
8147              intel_crtc->cursor_size != size ||
8148              intel_crtc->cursor_cntl != cntl)) {
8149                 /* On these chipsets we can only modify the base/size/stride
8150                  * whilst the cursor is disabled.
8151                  */
8152                 I915_WRITE(_CURACNTR, 0);
8153                 POSTING_READ(_CURACNTR);
8154                 intel_crtc->cursor_cntl = 0;
8155         }
8156
8157         if (intel_crtc->cursor_base != base) {
8158                 I915_WRITE(_CURABASE, base);
8159                 intel_crtc->cursor_base = base;
8160         }
8161
8162         if (intel_crtc->cursor_size != size) {
8163                 I915_WRITE(CURSIZE, size);
8164                 intel_crtc->cursor_size = size;
8165         }
8166
8167         if (intel_crtc->cursor_cntl != cntl) {
8168                 I915_WRITE(_CURACNTR, cntl);
8169                 POSTING_READ(_CURACNTR);
8170                 intel_crtc->cursor_cntl = cntl;
8171         }
8172 }
8173
8174 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8175 {
8176         struct drm_device *dev = crtc->dev;
8177         struct drm_i915_private *dev_priv = dev->dev_private;
8178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8179         int pipe = intel_crtc->pipe;
8180         uint32_t cntl;
8181
8182         cntl = 0;
8183         if (base) {
8184                 cntl = MCURSOR_GAMMA_ENABLE;
8185                 switch (intel_crtc->cursor_width) {
8186                         case 64:
8187                                 cntl |= CURSOR_MODE_64_ARGB_AX;
8188                                 break;
8189                         case 128:
8190                                 cntl |= CURSOR_MODE_128_ARGB_AX;
8191                                 break;
8192                         case 256:
8193                                 cntl |= CURSOR_MODE_256_ARGB_AX;
8194                                 break;
8195                         default:
8196                                 WARN_ON(1);
8197                                 return;
8198                 }
8199                 cntl |= pipe << 28; /* Connect to correct pipe */
8200
8201                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8202                         cntl |= CURSOR_PIPE_CSC_ENABLE;
8203         }
8204
8205         if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8206                 cntl |= CURSOR_ROTATE_180;
8207
8208         if (intel_crtc->cursor_cntl != cntl) {
8209                 I915_WRITE(CURCNTR(pipe), cntl);
8210                 POSTING_READ(CURCNTR(pipe));
8211                 intel_crtc->cursor_cntl = cntl;
8212         }
8213
8214         /* and commit changes on next vblank */
8215         I915_WRITE(CURBASE(pipe), base);
8216         POSTING_READ(CURBASE(pipe));
8217
8218         intel_crtc->cursor_base = base;
8219 }
8220
8221 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8222 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8223                                      bool on)
8224 {
8225         struct drm_device *dev = crtc->dev;
8226         struct drm_i915_private *dev_priv = dev->dev_private;
8227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8228         int pipe = intel_crtc->pipe;
8229         int x = crtc->cursor_x;
8230         int y = crtc->cursor_y;
8231         u32 base = 0, pos = 0;
8232
8233         if (on)
8234                 base = intel_crtc->cursor_addr;
8235
8236         if (x >= intel_crtc->config.pipe_src_w)
8237                 base = 0;
8238
8239         if (y >= intel_crtc->config.pipe_src_h)
8240                 base = 0;
8241
8242         if (x < 0) {
8243                 if (x + intel_crtc->cursor_width <= 0)
8244                         base = 0;
8245
8246                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8247                 x = -x;
8248         }
8249         pos |= x << CURSOR_X_SHIFT;
8250
8251         if (y < 0) {
8252                 if (y + intel_crtc->cursor_height <= 0)
8253                         base = 0;
8254
8255                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8256                 y = -y;
8257         }
8258         pos |= y << CURSOR_Y_SHIFT;
8259
8260         if (base == 0 && intel_crtc->cursor_base == 0)
8261                 return;
8262
8263         I915_WRITE(CURPOS(pipe), pos);
8264
8265         /* ILK+ do this automagically */
8266         if (HAS_GMCH_DISPLAY(dev) &&
8267                 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8268                 base += (intel_crtc->cursor_height *
8269                         intel_crtc->cursor_width - 1) * 4;
8270         }
8271
8272         if (IS_845G(dev) || IS_I865G(dev))
8273                 i845_update_cursor(crtc, base);
8274         else
8275                 i9xx_update_cursor(crtc, base);
8276 }
8277
8278 static bool cursor_size_ok(struct drm_device *dev,
8279                            uint32_t width, uint32_t height)
8280 {
8281         if (width == 0 || height == 0)
8282                 return false;
8283
8284         /*
8285          * 845g/865g are special in that they are only limited by
8286          * the width of their cursors, the height is arbitrary up to
8287          * the precision of the register. Everything else requires
8288          * square cursors, limited to a few power-of-two sizes.
8289          */
8290         if (IS_845G(dev) || IS_I865G(dev)) {
8291                 if ((width & 63) != 0)
8292                         return false;
8293
8294                 if (width > (IS_845G(dev) ? 64 : 512))
8295                         return false;
8296
8297                 if (height > 1023)
8298                         return false;
8299         } else {
8300                 switch (width | height) {
8301                 case 256:
8302                 case 128:
8303                         if (IS_GEN2(dev))
8304                                 return false;
8305                 case 64:
8306                         break;
8307                 default:
8308                         return false;
8309                 }
8310         }
8311
8312         return true;
8313 }
8314
8315 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8316                                      struct drm_i915_gem_object *obj,
8317                                      uint32_t width, uint32_t height)
8318 {
8319         struct drm_device *dev = crtc->dev;
8320         struct drm_i915_private *dev_priv = dev->dev_private;
8321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8322         enum pipe pipe = intel_crtc->pipe;
8323         unsigned old_width;
8324         uint32_t addr;
8325         int ret;
8326
8327         /* if we want to turn off the cursor ignore width and height */
8328         if (!obj) {
8329                 DRM_DEBUG_KMS("cursor off\n");
8330                 addr = 0;
8331                 mutex_lock(&dev->struct_mutex);
8332                 goto finish;
8333         }
8334
8335         /* we only need to pin inside GTT if cursor is non-phy */
8336         mutex_lock(&dev->struct_mutex);
8337         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8338                 unsigned alignment;
8339
8340                 /*
8341                  * Global gtt pte registers are special registers which actually
8342                  * forward writes to a chunk of system memory. Which means that
8343                  * there is no risk that the register values disappear as soon
8344                  * as we call intel_runtime_pm_put(), so it is correct to wrap
8345                  * only the pin/unpin/fence and not more.
8346                  */
8347                 intel_runtime_pm_get(dev_priv);
8348
8349                 /* Note that the w/a also requires 2 PTE of padding following
8350                  * the bo. We currently fill all unused PTE with the shadow
8351                  * page and so we should always have valid PTE following the
8352                  * cursor preventing the VT-d warning.
8353                  */
8354                 alignment = 0;
8355                 if (need_vtd_wa(dev))
8356                         alignment = 64*1024;
8357
8358                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8359                 if (ret) {
8360                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8361                         intel_runtime_pm_put(dev_priv);
8362                         goto fail_locked;
8363                 }
8364
8365                 ret = i915_gem_object_put_fence(obj);
8366                 if (ret) {
8367                         DRM_DEBUG_KMS("failed to release fence for cursor");
8368                         intel_runtime_pm_put(dev_priv);
8369                         goto fail_unpin;
8370                 }
8371
8372                 addr = i915_gem_obj_ggtt_offset(obj);
8373
8374                 intel_runtime_pm_put(dev_priv);
8375         } else {
8376                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8377                 ret = i915_gem_object_attach_phys(obj, align);
8378                 if (ret) {
8379                         DRM_DEBUG_KMS("failed to attach phys object\n");
8380                         goto fail_locked;
8381                 }
8382                 addr = obj->phys_handle->busaddr;
8383         }
8384
8385  finish:
8386         if (intel_crtc->cursor_bo) {
8387                 if (!INTEL_INFO(dev)->cursor_needs_physical)
8388                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8389         }
8390
8391         i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8392                           INTEL_FRONTBUFFER_CURSOR(pipe));
8393         mutex_unlock(&dev->struct_mutex);
8394
8395         old_width = intel_crtc->cursor_width;
8396
8397         intel_crtc->cursor_addr = addr;
8398         intel_crtc->cursor_bo = obj;
8399         intel_crtc->cursor_width = width;
8400         intel_crtc->cursor_height = height;
8401
8402         if (intel_crtc->active) {
8403                 if (old_width != width)
8404                         intel_update_watermarks(crtc);
8405                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8406
8407                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8408         }
8409
8410         return 0;
8411 fail_unpin:
8412         i915_gem_object_unpin_from_display_plane(obj);
8413 fail_locked:
8414         mutex_unlock(&dev->struct_mutex);
8415         return ret;
8416 }
8417
8418 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8419                                  u16 *blue, uint32_t start, uint32_t size)
8420 {
8421         int end = (start + size > 256) ? 256 : start + size, i;
8422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8423
8424         for (i = start; i < end; i++) {
8425                 intel_crtc->lut_r[i] = red[i] >> 8;
8426                 intel_crtc->lut_g[i] = green[i] >> 8;
8427                 intel_crtc->lut_b[i] = blue[i] >> 8;
8428         }
8429
8430         intel_crtc_load_lut(crtc);
8431 }
8432
8433 /* VESA 640x480x72Hz mode to set on the pipe */
8434 static struct drm_display_mode load_detect_mode = {
8435         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8436                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8437 };
8438
8439 struct drm_framebuffer *
8440 __intel_framebuffer_create(struct drm_device *dev,
8441                            struct drm_mode_fb_cmd2 *mode_cmd,
8442                            struct drm_i915_gem_object *obj)
8443 {
8444         struct intel_framebuffer *intel_fb;
8445         int ret;
8446
8447         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8448         if (!intel_fb) {
8449                 drm_gem_object_unreference(&obj->base);
8450                 return ERR_PTR(-ENOMEM);
8451         }
8452
8453         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8454         if (ret)
8455                 goto err;
8456
8457         return &intel_fb->base;
8458 err:
8459         drm_gem_object_unreference(&obj->base);
8460         kfree(intel_fb);
8461
8462         return ERR_PTR(ret);
8463 }
8464
8465 static struct drm_framebuffer *
8466 intel_framebuffer_create(struct drm_device *dev,
8467                          struct drm_mode_fb_cmd2 *mode_cmd,
8468                          struct drm_i915_gem_object *obj)
8469 {
8470         struct drm_framebuffer *fb;
8471         int ret;
8472
8473         ret = i915_mutex_lock_interruptible(dev);
8474         if (ret)
8475                 return ERR_PTR(ret);
8476         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8477         mutex_unlock(&dev->struct_mutex);
8478
8479         return fb;
8480 }
8481
8482 static u32
8483 intel_framebuffer_pitch_for_width(int width, int bpp)
8484 {
8485         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8486         return ALIGN(pitch, 64);
8487 }
8488
8489 static u32
8490 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8491 {
8492         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8493         return PAGE_ALIGN(pitch * mode->vdisplay);
8494 }
8495
8496 static struct drm_framebuffer *
8497 intel_framebuffer_create_for_mode(struct drm_device *dev,
8498                                   struct drm_display_mode *mode,
8499                                   int depth, int bpp)
8500 {
8501         struct drm_i915_gem_object *obj;
8502         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8503
8504         obj = i915_gem_alloc_object(dev,
8505                                     intel_framebuffer_size_for_mode(mode, bpp));
8506         if (obj == NULL)
8507                 return ERR_PTR(-ENOMEM);
8508
8509         mode_cmd.width = mode->hdisplay;
8510         mode_cmd.height = mode->vdisplay;
8511         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8512                                                                 bpp);
8513         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8514
8515         return intel_framebuffer_create(dev, &mode_cmd, obj);
8516 }
8517
8518 static struct drm_framebuffer *
8519 mode_fits_in_fbdev(struct drm_device *dev,
8520                    struct drm_display_mode *mode)
8521 {
8522 #ifdef CONFIG_DRM_I915_FBDEV
8523         struct drm_i915_private *dev_priv = dev->dev_private;
8524         struct drm_i915_gem_object *obj;
8525         struct drm_framebuffer *fb;
8526
8527         if (!dev_priv->fbdev)
8528                 return NULL;
8529
8530         if (!dev_priv->fbdev->fb)
8531                 return NULL;
8532
8533         obj = dev_priv->fbdev->fb->obj;
8534         BUG_ON(!obj);
8535
8536         fb = &dev_priv->fbdev->fb->base;
8537         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8538                                                                fb->bits_per_pixel))
8539                 return NULL;
8540
8541         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8542                 return NULL;
8543
8544         return fb;
8545 #else
8546         return NULL;
8547 #endif
8548 }
8549
8550 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8551                                 struct drm_display_mode *mode,
8552                                 struct intel_load_detect_pipe *old,
8553                                 struct drm_modeset_acquire_ctx *ctx)
8554 {
8555         struct intel_crtc *intel_crtc;
8556         struct intel_encoder *intel_encoder =
8557                 intel_attached_encoder(connector);
8558         struct drm_crtc *possible_crtc;
8559         struct drm_encoder *encoder = &intel_encoder->base;
8560         struct drm_crtc *crtc = NULL;
8561         struct drm_device *dev = encoder->dev;
8562         struct drm_framebuffer *fb;
8563         struct drm_mode_config *config = &dev->mode_config;
8564         int ret, i = -1;
8565
8566         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8567                       connector->base.id, connector->name,
8568                       encoder->base.id, encoder->name);
8569
8570 retry:
8571         ret = drm_modeset_lock(&config->connection_mutex, ctx);
8572         if (ret)
8573                 goto fail_unlock;
8574
8575         /*
8576          * Algorithm gets a little messy:
8577          *
8578          *   - if the connector already has an assigned crtc, use it (but make
8579          *     sure it's on first)
8580          *
8581          *   - try to find the first unused crtc that can drive this connector,
8582          *     and use that if we find one
8583          */
8584
8585         /* See if we already have a CRTC for this connector */
8586         if (encoder->crtc) {
8587                 crtc = encoder->crtc;
8588
8589                 ret = drm_modeset_lock(&crtc->mutex, ctx);
8590                 if (ret)
8591                         goto fail_unlock;
8592
8593                 old->dpms_mode = connector->dpms;
8594                 old->load_detect_temp = false;
8595
8596                 /* Make sure the crtc and connector are running */
8597                 if (connector->dpms != DRM_MODE_DPMS_ON)
8598                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8599
8600                 return true;
8601         }
8602
8603         /* Find an unused one (if possible) */
8604         for_each_crtc(dev, possible_crtc) {
8605                 i++;
8606                 if (!(encoder->possible_crtcs & (1 << i)))
8607                         continue;
8608                 if (possible_crtc->enabled)
8609                         continue;
8610                 /* This can occur when applying the pipe A quirk on resume. */
8611                 if (to_intel_crtc(possible_crtc)->new_enabled)
8612                         continue;
8613
8614                 crtc = possible_crtc;
8615                 break;
8616         }
8617
8618         /*
8619          * If we didn't find an unused CRTC, don't use any.
8620          */
8621         if (!crtc) {
8622                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8623                 goto fail_unlock;
8624         }
8625
8626         ret = drm_modeset_lock(&crtc->mutex, ctx);
8627         if (ret)
8628                 goto fail_unlock;
8629         intel_encoder->new_crtc = to_intel_crtc(crtc);
8630         to_intel_connector(connector)->new_encoder = intel_encoder;
8631
8632         intel_crtc = to_intel_crtc(crtc);
8633         intel_crtc->new_enabled = true;
8634         intel_crtc->new_config = &intel_crtc->config;
8635         old->dpms_mode = connector->dpms;
8636         old->load_detect_temp = true;
8637         old->release_fb = NULL;
8638
8639         if (!mode)
8640                 mode = &load_detect_mode;
8641
8642         /* We need a framebuffer large enough to accommodate all accesses
8643          * that the plane may generate whilst we perform load detection.
8644          * We can not rely on the fbcon either being present (we get called
8645          * during its initialisation to detect all boot displays, or it may
8646          * not even exist) or that it is large enough to satisfy the
8647          * requested mode.
8648          */
8649         fb = mode_fits_in_fbdev(dev, mode);
8650         if (fb == NULL) {
8651                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8652                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8653                 old->release_fb = fb;
8654         } else
8655                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8656         if (IS_ERR(fb)) {
8657                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8658                 goto fail;
8659         }
8660
8661         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8662                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8663                 if (old->release_fb)
8664                         old->release_fb->funcs->destroy(old->release_fb);
8665                 goto fail;
8666         }
8667
8668         /* let the connector get through one full cycle before testing */
8669         intel_wait_for_vblank(dev, intel_crtc->pipe);
8670         return true;
8671
8672  fail:
8673         intel_crtc->new_enabled = crtc->enabled;
8674         if (intel_crtc->new_enabled)
8675                 intel_crtc->new_config = &intel_crtc->config;
8676         else
8677                 intel_crtc->new_config = NULL;
8678 fail_unlock:
8679         if (ret == -EDEADLK) {
8680                 drm_modeset_backoff(ctx);
8681                 goto retry;
8682         }
8683
8684         return false;
8685 }
8686
8687 void intel_release_load_detect_pipe(struct drm_connector *connector,
8688                                     struct intel_load_detect_pipe *old)
8689 {
8690         struct intel_encoder *intel_encoder =
8691                 intel_attached_encoder(connector);
8692         struct drm_encoder *encoder = &intel_encoder->base;
8693         struct drm_crtc *crtc = encoder->crtc;
8694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8695
8696         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8697                       connector->base.id, connector->name,
8698                       encoder->base.id, encoder->name);
8699
8700         if (old->load_detect_temp) {
8701                 to_intel_connector(connector)->new_encoder = NULL;
8702                 intel_encoder->new_crtc = NULL;
8703                 intel_crtc->new_enabled = false;
8704                 intel_crtc->new_config = NULL;
8705                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8706
8707                 if (old->release_fb) {
8708                         drm_framebuffer_unregister_private(old->release_fb);
8709                         drm_framebuffer_unreference(old->release_fb);
8710                 }
8711
8712                 return;
8713         }
8714
8715         /* Switch crtc and encoder back off if necessary */
8716         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8717                 connector->funcs->dpms(connector, old->dpms_mode);
8718 }
8719
8720 static int i9xx_pll_refclk(struct drm_device *dev,
8721                            const struct intel_crtc_config *pipe_config)
8722 {
8723         struct drm_i915_private *dev_priv = dev->dev_private;
8724         u32 dpll = pipe_config->dpll_hw_state.dpll;
8725
8726         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8727                 return dev_priv->vbt.lvds_ssc_freq;
8728         else if (HAS_PCH_SPLIT(dev))
8729                 return 120000;
8730         else if (!IS_GEN2(dev))
8731                 return 96000;
8732         else
8733                 return 48000;
8734 }
8735
8736 /* Returns the clock of the currently programmed mode of the given pipe. */
8737 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8738                                 struct intel_crtc_config *pipe_config)
8739 {
8740         struct drm_device *dev = crtc->base.dev;
8741         struct drm_i915_private *dev_priv = dev->dev_private;
8742         int pipe = pipe_config->cpu_transcoder;
8743         u32 dpll = pipe_config->dpll_hw_state.dpll;
8744         u32 fp;
8745         intel_clock_t clock;
8746         int refclk = i9xx_pll_refclk(dev, pipe_config);
8747
8748         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8749                 fp = pipe_config->dpll_hw_state.fp0;
8750         else
8751                 fp = pipe_config->dpll_hw_state.fp1;
8752
8753         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8754         if (IS_PINEVIEW(dev)) {
8755                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8756                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8757         } else {
8758                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8759                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8760         }
8761
8762         if (!IS_GEN2(dev)) {
8763                 if (IS_PINEVIEW(dev))
8764                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8765                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8766                 else
8767                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8768                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8769
8770                 switch (dpll & DPLL_MODE_MASK) {
8771                 case DPLLB_MODE_DAC_SERIAL:
8772                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8773                                 5 : 10;
8774                         break;
8775                 case DPLLB_MODE_LVDS:
8776                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8777                                 7 : 14;
8778                         break;
8779                 default:
8780                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8781                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8782                         return;
8783                 }
8784
8785                 if (IS_PINEVIEW(dev))
8786                         pineview_clock(refclk, &clock);
8787                 else
8788                         i9xx_clock(refclk, &clock);
8789         } else {
8790                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8791                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8792
8793                 if (is_lvds) {
8794                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8795                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8796
8797                         if (lvds & LVDS_CLKB_POWER_UP)
8798                                 clock.p2 = 7;
8799                         else
8800                                 clock.p2 = 14;
8801                 } else {
8802                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8803                                 clock.p1 = 2;
8804                         else {
8805                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8806                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8807                         }
8808                         if (dpll & PLL_P2_DIVIDE_BY_4)
8809                                 clock.p2 = 4;
8810                         else
8811                                 clock.p2 = 2;
8812                 }
8813
8814                 i9xx_clock(refclk, &clock);
8815         }
8816
8817         /*
8818          * This value includes pixel_multiplier. We will use
8819          * port_clock to compute adjusted_mode.crtc_clock in the
8820          * encoder's get_config() function.
8821          */
8822         pipe_config->port_clock = clock.dot;
8823 }
8824
8825 int intel_dotclock_calculate(int link_freq,
8826                              const struct intel_link_m_n *m_n)
8827 {
8828         /*
8829          * The calculation for the data clock is:
8830          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8831          * But we want to avoid losing precison if possible, so:
8832          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8833          *
8834          * and the link clock is simpler:
8835          * link_clock = (m * link_clock) / n
8836          */
8837
8838         if (!m_n->link_n)
8839                 return 0;
8840
8841         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8842 }
8843
8844 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8845                                    struct intel_crtc_config *pipe_config)
8846 {
8847         struct drm_device *dev = crtc->base.dev;
8848
8849         /* read out port_clock from the DPLL */
8850         i9xx_crtc_clock_get(crtc, pipe_config);
8851
8852         /*
8853          * This value does not include pixel_multiplier.
8854          * We will check that port_clock and adjusted_mode.crtc_clock
8855          * agree once we know their relationship in the encoder's
8856          * get_config() function.
8857          */
8858         pipe_config->adjusted_mode.crtc_clock =
8859                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8860                                          &pipe_config->fdi_m_n);
8861 }
8862
8863 /** Returns the currently programmed mode of the given pipe. */
8864 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8865                                              struct drm_crtc *crtc)
8866 {
8867         struct drm_i915_private *dev_priv = dev->dev_private;
8868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8869         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8870         struct drm_display_mode *mode;
8871         struct intel_crtc_config pipe_config;
8872         int htot = I915_READ(HTOTAL(cpu_transcoder));
8873         int hsync = I915_READ(HSYNC(cpu_transcoder));
8874         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8875         int vsync = I915_READ(VSYNC(cpu_transcoder));
8876         enum pipe pipe = intel_crtc->pipe;
8877
8878         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8879         if (!mode)
8880                 return NULL;
8881
8882         /*
8883          * Construct a pipe_config sufficient for getting the clock info
8884          * back out of crtc_clock_get.
8885          *
8886          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8887          * to use a real value here instead.
8888          */
8889         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8890         pipe_config.pixel_multiplier = 1;
8891         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8892         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8893         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8894         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8895
8896         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8897         mode->hdisplay = (htot & 0xffff) + 1;
8898         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8899         mode->hsync_start = (hsync & 0xffff) + 1;
8900         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8901         mode->vdisplay = (vtot & 0xffff) + 1;
8902         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8903         mode->vsync_start = (vsync & 0xffff) + 1;
8904         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8905
8906         drm_mode_set_name(mode);
8907
8908         return mode;
8909 }
8910
8911 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8912 {
8913         struct drm_device *dev = crtc->dev;
8914         struct drm_i915_private *dev_priv = dev->dev_private;
8915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8916
8917         if (!HAS_GMCH_DISPLAY(dev))
8918                 return;
8919
8920         if (!dev_priv->lvds_downclock_avail)
8921                 return;
8922
8923         /*
8924          * Since this is called by a timer, we should never get here in
8925          * the manual case.
8926          */
8927         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8928                 int pipe = intel_crtc->pipe;
8929                 int dpll_reg = DPLL(pipe);
8930                 int dpll;
8931
8932                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8933
8934                 assert_panel_unlocked(dev_priv, pipe);
8935
8936                 dpll = I915_READ(dpll_reg);
8937                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8938                 I915_WRITE(dpll_reg, dpll);
8939                 intel_wait_for_vblank(dev, pipe);
8940                 dpll = I915_READ(dpll_reg);
8941                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8942                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8943         }
8944
8945 }
8946
8947 void intel_mark_busy(struct drm_device *dev)
8948 {
8949         struct drm_i915_private *dev_priv = dev->dev_private;
8950
8951         if (dev_priv->mm.busy)
8952                 return;
8953
8954         intel_runtime_pm_get(dev_priv);
8955         i915_update_gfx_val(dev_priv);
8956         dev_priv->mm.busy = true;
8957 }
8958
8959 void intel_mark_idle(struct drm_device *dev)
8960 {
8961         struct drm_i915_private *dev_priv = dev->dev_private;
8962         struct drm_crtc *crtc;
8963
8964         if (!dev_priv->mm.busy)
8965                 return;
8966
8967         dev_priv->mm.busy = false;
8968
8969         if (!i915.powersave)
8970                 goto out;
8971
8972         for_each_crtc(dev, crtc) {
8973                 if (!crtc->primary->fb)
8974                         continue;
8975
8976                 intel_decrease_pllclock(crtc);
8977         }
8978
8979         if (INTEL_INFO(dev)->gen >= 6)
8980                 gen6_rps_idle(dev->dev_private);
8981
8982 out:
8983         intel_runtime_pm_put(dev_priv);
8984 }
8985
8986 static void intel_crtc_destroy(struct drm_crtc *crtc)
8987 {
8988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8989         struct drm_device *dev = crtc->dev;
8990         struct intel_unpin_work *work;
8991
8992         spin_lock_irq(&dev->event_lock);
8993         work = intel_crtc->unpin_work;
8994         intel_crtc->unpin_work = NULL;
8995         spin_unlock_irq(&dev->event_lock);
8996
8997         if (work) {
8998                 cancel_work_sync(&work->work);
8999                 kfree(work);
9000         }
9001
9002         drm_crtc_cleanup(crtc);
9003
9004         kfree(intel_crtc);
9005 }
9006
9007 static void intel_unpin_work_fn(struct work_struct *__work)
9008 {
9009         struct intel_unpin_work *work =
9010                 container_of(__work, struct intel_unpin_work, work);
9011         struct drm_device *dev = work->crtc->dev;
9012         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9013
9014         mutex_lock(&dev->struct_mutex);
9015         intel_unpin_fb_obj(work->old_fb_obj);
9016         drm_gem_object_unreference(&work->pending_flip_obj->base);
9017         drm_gem_object_unreference(&work->old_fb_obj->base);
9018
9019         intel_update_fbc(dev);
9020         mutex_unlock(&dev->struct_mutex);
9021
9022         intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9023
9024         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9025         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9026
9027         kfree(work);
9028 }
9029
9030 static void do_intel_finish_page_flip(struct drm_device *dev,
9031                                       struct drm_crtc *crtc)
9032 {
9033         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9034         struct intel_unpin_work *work;
9035         unsigned long flags;
9036
9037         /* Ignore early vblank irqs */
9038         if (intel_crtc == NULL)
9039                 return;
9040
9041         /*
9042          * This is called both by irq handlers and the reset code (to complete
9043          * lost pageflips) so needs the full irqsave spinlocks.
9044          */
9045         spin_lock_irqsave(&dev->event_lock, flags);
9046         work = intel_crtc->unpin_work;
9047
9048         /* Ensure we don't miss a work->pending update ... */
9049         smp_rmb();
9050
9051         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9052                 spin_unlock_irqrestore(&dev->event_lock, flags);
9053                 return;
9054         }
9055
9056         page_flip_completed(intel_crtc);
9057
9058         spin_unlock_irqrestore(&dev->event_lock, flags);
9059 }
9060
9061 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9062 {
9063         struct drm_i915_private *dev_priv = dev->dev_private;
9064         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9065
9066         do_intel_finish_page_flip(dev, crtc);
9067 }
9068
9069 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9070 {
9071         struct drm_i915_private *dev_priv = dev->dev_private;
9072         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9073
9074         do_intel_finish_page_flip(dev, crtc);
9075 }
9076
9077 /* Is 'a' after or equal to 'b'? */
9078 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9079 {
9080         return !((a - b) & 0x80000000);
9081 }
9082
9083 static bool page_flip_finished(struct intel_crtc *crtc)
9084 {
9085         struct drm_device *dev = crtc->base.dev;
9086         struct drm_i915_private *dev_priv = dev->dev_private;
9087
9088         /*
9089          * The relevant registers doen't exist on pre-ctg.
9090          * As the flip done interrupt doesn't trigger for mmio
9091          * flips on gmch platforms, a flip count check isn't
9092          * really needed there. But since ctg has the registers,
9093          * include it in the check anyway.
9094          */
9095         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9096                 return true;
9097
9098         /*
9099          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9100          * used the same base address. In that case the mmio flip might
9101          * have completed, but the CS hasn't even executed the flip yet.
9102          *
9103          * A flip count check isn't enough as the CS might have updated
9104          * the base address just after start of vblank, but before we
9105          * managed to process the interrupt. This means we'd complete the
9106          * CS flip too soon.
9107          *
9108          * Combining both checks should get us a good enough result. It may
9109          * still happen that the CS flip has been executed, but has not
9110          * yet actually completed. But in case the base address is the same
9111          * anyway, we don't really care.
9112          */
9113         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9114                 crtc->unpin_work->gtt_offset &&
9115                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9116                                     crtc->unpin_work->flip_count);
9117 }
9118
9119 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9120 {
9121         struct drm_i915_private *dev_priv = dev->dev_private;
9122         struct intel_crtc *intel_crtc =
9123                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9124         unsigned long flags;
9125
9126
9127         /*
9128          * This is called both by irq handlers and the reset code (to complete
9129          * lost pageflips) so needs the full irqsave spinlocks.
9130          *
9131          * NB: An MMIO update of the plane base pointer will also
9132          * generate a page-flip completion irq, i.e. every modeset
9133          * is also accompanied by a spurious intel_prepare_page_flip().
9134          */
9135         spin_lock_irqsave(&dev->event_lock, flags);
9136         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9137                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9138         spin_unlock_irqrestore(&dev->event_lock, flags);
9139 }
9140
9141 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9142 {
9143         /* Ensure that the work item is consistent when activating it ... */
9144         smp_wmb();
9145         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9146         /* and that it is marked active as soon as the irq could fire. */
9147         smp_wmb();
9148 }
9149
9150 static int intel_gen2_queue_flip(struct drm_device *dev,
9151                                  struct drm_crtc *crtc,
9152                                  struct drm_framebuffer *fb,
9153                                  struct drm_i915_gem_object *obj,
9154                                  struct intel_engine_cs *ring,
9155                                  uint32_t flags)
9156 {
9157         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9158         u32 flip_mask;
9159         int ret;
9160
9161         ret = intel_ring_begin(ring, 6);
9162         if (ret)
9163                 return ret;
9164
9165         /* Can't queue multiple flips, so wait for the previous
9166          * one to finish before executing the next.
9167          */
9168         if (intel_crtc->plane)
9169                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9170         else
9171                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9172         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9173         intel_ring_emit(ring, MI_NOOP);
9174         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9175                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9176         intel_ring_emit(ring, fb->pitches[0]);
9177         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9178         intel_ring_emit(ring, 0); /* aux display base address, unused */
9179
9180         intel_mark_page_flip_active(intel_crtc);
9181         __intel_ring_advance(ring);
9182         return 0;
9183 }
9184
9185 static int intel_gen3_queue_flip(struct drm_device *dev,
9186                                  struct drm_crtc *crtc,
9187                                  struct drm_framebuffer *fb,
9188                                  struct drm_i915_gem_object *obj,
9189                                  struct intel_engine_cs *ring,
9190                                  uint32_t flags)
9191 {
9192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9193         u32 flip_mask;
9194         int ret;
9195
9196         ret = intel_ring_begin(ring, 6);
9197         if (ret)
9198                 return ret;
9199
9200         if (intel_crtc->plane)
9201                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9202         else
9203                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9204         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9205         intel_ring_emit(ring, MI_NOOP);
9206         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9207                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9208         intel_ring_emit(ring, fb->pitches[0]);
9209         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9210         intel_ring_emit(ring, MI_NOOP);
9211
9212         intel_mark_page_flip_active(intel_crtc);
9213         __intel_ring_advance(ring);
9214         return 0;
9215 }
9216
9217 static int intel_gen4_queue_flip(struct drm_device *dev,
9218                                  struct drm_crtc *crtc,
9219                                  struct drm_framebuffer *fb,
9220                                  struct drm_i915_gem_object *obj,
9221                                  struct intel_engine_cs *ring,
9222                                  uint32_t flags)
9223 {
9224         struct drm_i915_private *dev_priv = dev->dev_private;
9225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9226         uint32_t pf, pipesrc;
9227         int ret;
9228
9229         ret = intel_ring_begin(ring, 4);
9230         if (ret)
9231                 return ret;
9232
9233         /* i965+ uses the linear or tiled offsets from the
9234          * Display Registers (which do not change across a page-flip)
9235          * so we need only reprogram the base address.
9236          */
9237         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9238                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9239         intel_ring_emit(ring, fb->pitches[0]);
9240         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9241                         obj->tiling_mode);
9242
9243         /* XXX Enabling the panel-fitter across page-flip is so far
9244          * untested on non-native modes, so ignore it for now.
9245          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9246          */
9247         pf = 0;
9248         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9249         intel_ring_emit(ring, pf | pipesrc);
9250
9251         intel_mark_page_flip_active(intel_crtc);
9252         __intel_ring_advance(ring);
9253         return 0;
9254 }
9255
9256 static int intel_gen6_queue_flip(struct drm_device *dev,
9257                                  struct drm_crtc *crtc,
9258                                  struct drm_framebuffer *fb,
9259                                  struct drm_i915_gem_object *obj,
9260                                  struct intel_engine_cs *ring,
9261                                  uint32_t flags)
9262 {
9263         struct drm_i915_private *dev_priv = dev->dev_private;
9264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9265         uint32_t pf, pipesrc;
9266         int ret;
9267
9268         ret = intel_ring_begin(ring, 4);
9269         if (ret)
9270                 return ret;
9271
9272         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9273                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9274         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9275         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9276
9277         /* Contrary to the suggestions in the documentation,
9278          * "Enable Panel Fitter" does not seem to be required when page
9279          * flipping with a non-native mode, and worse causes a normal
9280          * modeset to fail.
9281          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9282          */
9283         pf = 0;
9284         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9285         intel_ring_emit(ring, pf | pipesrc);
9286
9287         intel_mark_page_flip_active(intel_crtc);
9288         __intel_ring_advance(ring);
9289         return 0;
9290 }
9291
9292 static int intel_gen7_queue_flip(struct drm_device *dev,
9293                                  struct drm_crtc *crtc,
9294                                  struct drm_framebuffer *fb,
9295                                  struct drm_i915_gem_object *obj,
9296                                  struct intel_engine_cs *ring,
9297                                  uint32_t flags)
9298 {
9299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9300         uint32_t plane_bit = 0;
9301         int len, ret;
9302
9303         switch (intel_crtc->plane) {
9304         case PLANE_A:
9305                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9306                 break;
9307         case PLANE_B:
9308                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9309                 break;
9310         case PLANE_C:
9311                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9312                 break;
9313         default:
9314                 WARN_ONCE(1, "unknown plane in flip command\n");
9315                 return -ENODEV;
9316         }
9317
9318         len = 4;
9319         if (ring->id == RCS) {
9320                 len += 6;
9321                 /*
9322                  * On Gen 8, SRM is now taking an extra dword to accommodate
9323                  * 48bits addresses, and we need a NOOP for the batch size to
9324                  * stay even.
9325                  */
9326                 if (IS_GEN8(dev))
9327                         len += 2;
9328         }
9329
9330         /*
9331          * BSpec MI_DISPLAY_FLIP for IVB:
9332          * "The full packet must be contained within the same cache line."
9333          *
9334          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9335          * cacheline, if we ever start emitting more commands before
9336          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9337          * then do the cacheline alignment, and finally emit the
9338          * MI_DISPLAY_FLIP.
9339          */
9340         ret = intel_ring_cacheline_align(ring);
9341         if (ret)
9342                 return ret;
9343
9344         ret = intel_ring_begin(ring, len);
9345         if (ret)
9346                 return ret;
9347
9348         /* Unmask the flip-done completion message. Note that the bspec says that
9349          * we should do this for both the BCS and RCS, and that we must not unmask
9350          * more than one flip event at any time (or ensure that one flip message
9351          * can be sent by waiting for flip-done prior to queueing new flips).
9352          * Experimentation says that BCS works despite DERRMR masking all
9353          * flip-done completion events and that unmasking all planes at once
9354          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9355          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9356          */
9357         if (ring->id == RCS) {
9358                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9359                 intel_ring_emit(ring, DERRMR);
9360                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9361                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9362                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9363                 if (IS_GEN8(dev))
9364                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9365                                               MI_SRM_LRM_GLOBAL_GTT);
9366                 else
9367                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9368                                               MI_SRM_LRM_GLOBAL_GTT);
9369                 intel_ring_emit(ring, DERRMR);
9370                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9371                 if (IS_GEN8(dev)) {
9372                         intel_ring_emit(ring, 0);
9373                         intel_ring_emit(ring, MI_NOOP);
9374                 }
9375         }
9376
9377         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9378         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9379         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9380         intel_ring_emit(ring, (MI_NOOP));
9381
9382         intel_mark_page_flip_active(intel_crtc);
9383         __intel_ring_advance(ring);
9384         return 0;
9385 }
9386
9387 static bool use_mmio_flip(struct intel_engine_cs *ring,
9388                           struct drm_i915_gem_object *obj)
9389 {
9390         /*
9391          * This is not being used for older platforms, because
9392          * non-availability of flip done interrupt forces us to use
9393          * CS flips. Older platforms derive flip done using some clever
9394          * tricks involving the flip_pending status bits and vblank irqs.
9395          * So using MMIO flips there would disrupt this mechanism.
9396          */
9397
9398         if (ring == NULL)
9399                 return true;
9400
9401         if (INTEL_INFO(ring->dev)->gen < 5)
9402                 return false;
9403
9404         if (i915.use_mmio_flip < 0)
9405                 return false;
9406         else if (i915.use_mmio_flip > 0)
9407                 return true;
9408         else if (i915.enable_execlists)
9409                 return true;
9410         else
9411                 return ring != obj->ring;
9412 }
9413
9414 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9415 {
9416         struct drm_device *dev = intel_crtc->base.dev;
9417         struct drm_i915_private *dev_priv = dev->dev_private;
9418         struct intel_framebuffer *intel_fb =
9419                 to_intel_framebuffer(intel_crtc->base.primary->fb);
9420         struct drm_i915_gem_object *obj = intel_fb->obj;
9421         bool atomic_update;
9422         u32 start_vbl_count;
9423         u32 dspcntr;
9424         u32 reg;
9425
9426         intel_mark_page_flip_active(intel_crtc);
9427
9428         atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9429
9430         reg = DSPCNTR(intel_crtc->plane);
9431         dspcntr = I915_READ(reg);
9432
9433         if (obj->tiling_mode != I915_TILING_NONE)
9434                 dspcntr |= DISPPLANE_TILED;
9435         else
9436                 dspcntr &= ~DISPPLANE_TILED;
9437
9438         I915_WRITE(reg, dspcntr);
9439
9440         I915_WRITE(DSPSURF(intel_crtc->plane),
9441                    intel_crtc->unpin_work->gtt_offset);
9442         POSTING_READ(DSPSURF(intel_crtc->plane));
9443
9444         if (atomic_update)
9445                 intel_pipe_update_end(intel_crtc, start_vbl_count);
9446 }
9447
9448 static void intel_mmio_flip_work_func(struct work_struct *work)
9449 {
9450         struct intel_crtc *intel_crtc =
9451                 container_of(work, struct intel_crtc, mmio_flip.work);
9452         struct intel_engine_cs *ring;
9453         uint32_t seqno;
9454
9455         seqno = intel_crtc->mmio_flip.seqno;
9456         ring = intel_crtc->mmio_flip.ring;
9457
9458         if (seqno)
9459                 WARN_ON(__i915_wait_seqno(ring, seqno,
9460                                           intel_crtc->reset_counter,
9461                                           false, NULL, NULL) != 0);
9462
9463         intel_do_mmio_flip(intel_crtc);
9464 }
9465
9466 static int intel_queue_mmio_flip(struct drm_device *dev,
9467                                  struct drm_crtc *crtc,
9468                                  struct drm_framebuffer *fb,
9469                                  struct drm_i915_gem_object *obj,
9470                                  struct intel_engine_cs *ring,
9471                                  uint32_t flags)
9472 {
9473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9474
9475         intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9476         intel_crtc->mmio_flip.ring = obj->ring;
9477
9478         schedule_work(&intel_crtc->mmio_flip.work);
9479
9480         return 0;
9481 }
9482
9483 static int intel_gen9_queue_flip(struct drm_device *dev,
9484                                  struct drm_crtc *crtc,
9485                                  struct drm_framebuffer *fb,
9486                                  struct drm_i915_gem_object *obj,
9487                                  struct intel_engine_cs *ring,
9488                                  uint32_t flags)
9489 {
9490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9491         uint32_t plane = 0, stride;
9492         int ret;
9493
9494         switch(intel_crtc->pipe) {
9495         case PIPE_A:
9496                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9497                 break;
9498         case PIPE_B:
9499                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9500                 break;
9501         case PIPE_C:
9502                 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9503                 break;
9504         default:
9505                 WARN_ONCE(1, "unknown plane in flip command\n");
9506                 return -ENODEV;
9507         }
9508
9509         switch (obj->tiling_mode) {
9510         case I915_TILING_NONE:
9511                 stride = fb->pitches[0] >> 6;
9512                 break;
9513         case I915_TILING_X:
9514                 stride = fb->pitches[0] >> 9;
9515                 break;
9516         default:
9517                 WARN_ONCE(1, "unknown tiling in flip command\n");
9518                 return -ENODEV;
9519         }
9520
9521         ret = intel_ring_begin(ring, 10);
9522         if (ret)
9523                 return ret;
9524
9525         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9526         intel_ring_emit(ring, DERRMR);
9527         intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9528                                 DERRMR_PIPEB_PRI_FLIP_DONE |
9529                                 DERRMR_PIPEC_PRI_FLIP_DONE));
9530         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9531                               MI_SRM_LRM_GLOBAL_GTT);
9532         intel_ring_emit(ring, DERRMR);
9533         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9534         intel_ring_emit(ring, 0);
9535
9536         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9537         intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9538         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9539
9540         intel_mark_page_flip_active(intel_crtc);
9541         __intel_ring_advance(ring);
9542
9543         return 0;
9544 }
9545
9546 static int intel_default_queue_flip(struct drm_device *dev,
9547                                     struct drm_crtc *crtc,
9548                                     struct drm_framebuffer *fb,
9549                                     struct drm_i915_gem_object *obj,
9550                                     struct intel_engine_cs *ring,
9551                                     uint32_t flags)
9552 {
9553         return -ENODEV;
9554 }
9555
9556 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9557                                          struct drm_crtc *crtc)
9558 {
9559         struct drm_i915_private *dev_priv = dev->dev_private;
9560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9561         struct intel_unpin_work *work = intel_crtc->unpin_work;
9562         u32 addr;
9563
9564         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9565                 return true;
9566
9567         if (!work->enable_stall_check)
9568                 return false;
9569
9570         if (work->flip_ready_vblank == 0) {
9571                 if (work->flip_queued_ring &&
9572                     !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9573                                        work->flip_queued_seqno))
9574                         return false;
9575
9576                 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9577         }
9578
9579         if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9580                 return false;
9581
9582         /* Potential stall - if we see that the flip has happened,
9583          * assume a missed interrupt. */
9584         if (INTEL_INFO(dev)->gen >= 4)
9585                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9586         else
9587                 addr = I915_READ(DSPADDR(intel_crtc->plane));
9588
9589         /* There is a potential issue here with a false positive after a flip
9590          * to the same address. We could address this by checking for a
9591          * non-incrementing frame counter.
9592          */
9593         return addr == work->gtt_offset;
9594 }
9595
9596 void intel_check_page_flip(struct drm_device *dev, int pipe)
9597 {
9598         struct drm_i915_private *dev_priv = dev->dev_private;
9599         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9601
9602         WARN_ON(!in_irq());
9603
9604         if (crtc == NULL)
9605                 return;
9606
9607         spin_lock(&dev->event_lock);
9608         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9609                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9610                          intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9611                 page_flip_completed(intel_crtc);
9612         }
9613         spin_unlock(&dev->event_lock);
9614 }
9615
9616 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9617                                 struct drm_framebuffer *fb,
9618                                 struct drm_pending_vblank_event *event,
9619                                 uint32_t page_flip_flags)
9620 {
9621         struct drm_device *dev = crtc->dev;
9622         struct drm_i915_private *dev_priv = dev->dev_private;
9623         struct drm_framebuffer *old_fb = crtc->primary->fb;
9624         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9626         enum pipe pipe = intel_crtc->pipe;
9627         struct intel_unpin_work *work;
9628         struct intel_engine_cs *ring;
9629         int ret;
9630
9631         /*
9632          * drm_mode_page_flip_ioctl() should already catch this, but double
9633          * check to be safe.  In the future we may enable pageflipping from
9634          * a disabled primary plane.
9635          */
9636         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9637                 return -EBUSY;
9638
9639         /* Can't change pixel format via MI display flips. */
9640         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9641                 return -EINVAL;
9642
9643         /*
9644          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9645          * Note that pitch changes could also affect these register.
9646          */
9647         if (INTEL_INFO(dev)->gen > 3 &&
9648             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9649              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9650                 return -EINVAL;
9651
9652         if (i915_terminally_wedged(&dev_priv->gpu_error))
9653                 goto out_hang;
9654
9655         work = kzalloc(sizeof(*work), GFP_KERNEL);
9656         if (work == NULL)
9657                 return -ENOMEM;
9658
9659         work->event = event;
9660         work->crtc = crtc;
9661         work->old_fb_obj = intel_fb_obj(old_fb);
9662         INIT_WORK(&work->work, intel_unpin_work_fn);
9663
9664         ret = drm_crtc_vblank_get(crtc);
9665         if (ret)
9666                 goto free_work;
9667
9668         /* We borrow the event spin lock for protecting unpin_work */
9669         spin_lock_irq(&dev->event_lock);
9670         if (intel_crtc->unpin_work) {
9671                 /* Before declaring the flip queue wedged, check if
9672                  * the hardware completed the operation behind our backs.
9673                  */
9674                 if (__intel_pageflip_stall_check(dev, crtc)) {
9675                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9676                         page_flip_completed(intel_crtc);
9677                 } else {
9678                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9679                         spin_unlock_irq(&dev->event_lock);
9680
9681                         drm_crtc_vblank_put(crtc);
9682                         kfree(work);
9683                         return -EBUSY;
9684                 }
9685         }
9686         intel_crtc->unpin_work = work;
9687         spin_unlock_irq(&dev->event_lock);
9688
9689         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9690                 flush_workqueue(dev_priv->wq);
9691
9692         ret = i915_mutex_lock_interruptible(dev);
9693         if (ret)
9694                 goto cleanup;
9695
9696         /* Reference the objects for the scheduled work. */
9697         drm_gem_object_reference(&work->old_fb_obj->base);
9698         drm_gem_object_reference(&obj->base);
9699
9700         crtc->primary->fb = fb;
9701
9702         work->pending_flip_obj = obj;
9703
9704         atomic_inc(&intel_crtc->unpin_work_count);
9705         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9706
9707         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9708                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9709
9710         if (IS_VALLEYVIEW(dev)) {
9711                 ring = &dev_priv->ring[BCS];
9712                 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9713                         /* vlv: DISPLAY_FLIP fails to change tiling */
9714                         ring = NULL;
9715         } else if (IS_IVYBRIDGE(dev)) {
9716                 ring = &dev_priv->ring[BCS];
9717         } else if (INTEL_INFO(dev)->gen >= 7) {
9718                 ring = obj->ring;
9719                 if (ring == NULL || ring->id != RCS)
9720                         ring = &dev_priv->ring[BCS];
9721         } else {
9722                 ring = &dev_priv->ring[RCS];
9723         }
9724
9725         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9726         if (ret)
9727                 goto cleanup_pending;
9728
9729         work->gtt_offset =
9730                 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9731
9732         if (use_mmio_flip(ring, obj)) {
9733                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9734                                             page_flip_flags);
9735                 if (ret)
9736                         goto cleanup_unpin;
9737
9738                 work->flip_queued_seqno = obj->last_write_seqno;
9739                 work->flip_queued_ring = obj->ring;
9740         } else {
9741                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9742                                                    page_flip_flags);
9743                 if (ret)
9744                         goto cleanup_unpin;
9745
9746                 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9747                 work->flip_queued_ring = ring;
9748         }
9749
9750         work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9751         work->enable_stall_check = true;
9752
9753         i915_gem_track_fb(work->old_fb_obj, obj,
9754                           INTEL_FRONTBUFFER_PRIMARY(pipe));
9755
9756         intel_disable_fbc(dev);
9757         intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9758         mutex_unlock(&dev->struct_mutex);
9759
9760         trace_i915_flip_request(intel_crtc->plane, obj);
9761
9762         return 0;
9763
9764 cleanup_unpin:
9765         intel_unpin_fb_obj(obj);
9766 cleanup_pending:
9767         atomic_dec(&intel_crtc->unpin_work_count);
9768         crtc->primary->fb = old_fb;
9769         drm_gem_object_unreference(&work->old_fb_obj->base);
9770         drm_gem_object_unreference(&obj->base);
9771         mutex_unlock(&dev->struct_mutex);
9772
9773 cleanup:
9774         spin_lock_irq(&dev->event_lock);
9775         intel_crtc->unpin_work = NULL;
9776         spin_unlock_irq(&dev->event_lock);
9777
9778         drm_crtc_vblank_put(crtc);
9779 free_work:
9780         kfree(work);
9781
9782         if (ret == -EIO) {
9783 out_hang:
9784                 intel_crtc_wait_for_pending_flips(crtc);
9785                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9786                 if (ret == 0 && event) {
9787                         spin_lock_irq(&dev->event_lock);
9788                         drm_send_vblank_event(dev, pipe, event);
9789                         spin_unlock_irq(&dev->event_lock);
9790                 }
9791         }
9792         return ret;
9793 }
9794
9795 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9796         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9797         .load_lut = intel_crtc_load_lut,
9798 };
9799
9800 /**
9801  * intel_modeset_update_staged_output_state
9802  *
9803  * Updates the staged output configuration state, e.g. after we've read out the
9804  * current hw state.
9805  */
9806 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9807 {
9808         struct intel_crtc *crtc;
9809         struct intel_encoder *encoder;
9810         struct intel_connector *connector;
9811
9812         list_for_each_entry(connector, &dev->mode_config.connector_list,
9813                             base.head) {
9814                 connector->new_encoder =
9815                         to_intel_encoder(connector->base.encoder);
9816         }
9817
9818         for_each_intel_encoder(dev, encoder) {
9819                 encoder->new_crtc =
9820                         to_intel_crtc(encoder->base.crtc);
9821         }
9822
9823         for_each_intel_crtc(dev, crtc) {
9824                 crtc->new_enabled = crtc->base.enabled;
9825
9826                 if (crtc->new_enabled)
9827                         crtc->new_config = &crtc->config;
9828                 else
9829                         crtc->new_config = NULL;
9830         }
9831 }
9832
9833 /**
9834  * intel_modeset_commit_output_state
9835  *
9836  * This function copies the stage display pipe configuration to the real one.
9837  */
9838 static void intel_modeset_commit_output_state(struct drm_device *dev)
9839 {
9840         struct intel_crtc *crtc;
9841         struct intel_encoder *encoder;
9842         struct intel_connector *connector;
9843
9844         list_for_each_entry(connector, &dev->mode_config.connector_list,
9845                             base.head) {
9846                 connector->base.encoder = &connector->new_encoder->base;
9847         }
9848
9849         for_each_intel_encoder(dev, encoder) {
9850                 encoder->base.crtc = &encoder->new_crtc->base;
9851         }
9852
9853         for_each_intel_crtc(dev, crtc) {
9854                 crtc->base.enabled = crtc->new_enabled;
9855         }
9856 }
9857
9858 static void
9859 connected_sink_compute_bpp(struct intel_connector *connector,
9860                            struct intel_crtc_config *pipe_config)
9861 {
9862         int bpp = pipe_config->pipe_bpp;
9863
9864         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9865                 connector->base.base.id,
9866                 connector->base.name);
9867
9868         /* Don't use an invalid EDID bpc value */
9869         if (connector->base.display_info.bpc &&
9870             connector->base.display_info.bpc * 3 < bpp) {
9871                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9872                               bpp, connector->base.display_info.bpc*3);
9873                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9874         }
9875
9876         /* Clamp bpp to 8 on screens without EDID 1.4 */
9877         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9878                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9879                               bpp);
9880                 pipe_config->pipe_bpp = 24;
9881         }
9882 }
9883
9884 static int
9885 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9886                           struct drm_framebuffer *fb,
9887                           struct intel_crtc_config *pipe_config)
9888 {
9889         struct drm_device *dev = crtc->base.dev;
9890         struct intel_connector *connector;
9891         int bpp;
9892
9893         switch (fb->pixel_format) {
9894         case DRM_FORMAT_C8:
9895                 bpp = 8*3; /* since we go through a colormap */
9896                 break;
9897         case DRM_FORMAT_XRGB1555:
9898         case DRM_FORMAT_ARGB1555:
9899                 /* checked in intel_framebuffer_init already */
9900                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9901                         return -EINVAL;
9902         case DRM_FORMAT_RGB565:
9903                 bpp = 6*3; /* min is 18bpp */
9904                 break;
9905         case DRM_FORMAT_XBGR8888:
9906         case DRM_FORMAT_ABGR8888:
9907                 /* checked in intel_framebuffer_init already */
9908                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9909                         return -EINVAL;
9910         case DRM_FORMAT_XRGB8888:
9911         case DRM_FORMAT_ARGB8888:
9912                 bpp = 8*3;
9913                 break;
9914         case DRM_FORMAT_XRGB2101010:
9915         case DRM_FORMAT_ARGB2101010:
9916         case DRM_FORMAT_XBGR2101010:
9917         case DRM_FORMAT_ABGR2101010:
9918                 /* checked in intel_framebuffer_init already */
9919                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9920                         return -EINVAL;
9921                 bpp = 10*3;
9922                 break;
9923         /* TODO: gen4+ supports 16 bpc floating point, too. */
9924         default:
9925                 DRM_DEBUG_KMS("unsupported depth\n");
9926                 return -EINVAL;
9927         }
9928
9929         pipe_config->pipe_bpp = bpp;
9930
9931         /* Clamp display bpp to EDID value */
9932         list_for_each_entry(connector, &dev->mode_config.connector_list,
9933                             base.head) {
9934                 if (!connector->new_encoder ||
9935                     connector->new_encoder->new_crtc != crtc)
9936                         continue;
9937
9938                 connected_sink_compute_bpp(connector, pipe_config);
9939         }
9940
9941         return bpp;
9942 }
9943
9944 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9945 {
9946         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9947                         "type: 0x%x flags: 0x%x\n",
9948                 mode->crtc_clock,
9949                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9950                 mode->crtc_hsync_end, mode->crtc_htotal,
9951                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9952                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9953 }
9954
9955 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9956                                    struct intel_crtc_config *pipe_config,
9957                                    const char *context)
9958 {
9959         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9960                       context, pipe_name(crtc->pipe));
9961
9962         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9963         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9964                       pipe_config->pipe_bpp, pipe_config->dither);
9965         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9966                       pipe_config->has_pch_encoder,
9967                       pipe_config->fdi_lanes,
9968                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9969                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9970                       pipe_config->fdi_m_n.tu);
9971         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9972                       pipe_config->has_dp_encoder,
9973                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9974                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9975                       pipe_config->dp_m_n.tu);
9976
9977         DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9978                       pipe_config->has_dp_encoder,
9979                       pipe_config->dp_m2_n2.gmch_m,
9980                       pipe_config->dp_m2_n2.gmch_n,
9981                       pipe_config->dp_m2_n2.link_m,
9982                       pipe_config->dp_m2_n2.link_n,
9983                       pipe_config->dp_m2_n2.tu);
9984
9985         DRM_DEBUG_KMS("requested mode:\n");
9986         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9987         DRM_DEBUG_KMS("adjusted mode:\n");
9988         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9989         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9990         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9991         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9992                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9993         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9994                       pipe_config->gmch_pfit.control,
9995                       pipe_config->gmch_pfit.pgm_ratios,
9996                       pipe_config->gmch_pfit.lvds_border_bits);
9997         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9998                       pipe_config->pch_pfit.pos,
9999                       pipe_config->pch_pfit.size,
10000                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10001         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10002         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10003 }
10004
10005 static bool encoders_cloneable(const struct intel_encoder *a,
10006                                const struct intel_encoder *b)
10007 {
10008         /* masks could be asymmetric, so check both ways */
10009         return a == b || (a->cloneable & (1 << b->type) &&
10010                           b->cloneable & (1 << a->type));
10011 }
10012
10013 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10014                                          struct intel_encoder *encoder)
10015 {
10016         struct drm_device *dev = crtc->base.dev;
10017         struct intel_encoder *source_encoder;
10018
10019         for_each_intel_encoder(dev, source_encoder) {
10020                 if (source_encoder->new_crtc != crtc)
10021                         continue;
10022
10023                 if (!encoders_cloneable(encoder, source_encoder))
10024                         return false;
10025         }
10026
10027         return true;
10028 }
10029
10030 static bool check_encoder_cloning(struct intel_crtc *crtc)
10031 {
10032         struct drm_device *dev = crtc->base.dev;
10033         struct intel_encoder *encoder;
10034
10035         for_each_intel_encoder(dev, encoder) {
10036                 if (encoder->new_crtc != crtc)
10037                         continue;
10038
10039                 if (!check_single_encoder_cloning(crtc, encoder))
10040                         return false;
10041         }
10042
10043         return true;
10044 }
10045
10046 static struct intel_crtc_config *
10047 intel_modeset_pipe_config(struct drm_crtc *crtc,
10048                           struct drm_framebuffer *fb,
10049                           struct drm_display_mode *mode)
10050 {
10051         struct drm_device *dev = crtc->dev;
10052         struct intel_encoder *encoder;
10053         struct intel_crtc_config *pipe_config;
10054         int plane_bpp, ret = -EINVAL;
10055         bool retry = true;
10056
10057         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10058                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10059                 return ERR_PTR(-EINVAL);
10060         }
10061
10062         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10063         if (!pipe_config)
10064                 return ERR_PTR(-ENOMEM);
10065
10066         drm_mode_copy(&pipe_config->adjusted_mode, mode);
10067         drm_mode_copy(&pipe_config->requested_mode, mode);
10068
10069         pipe_config->cpu_transcoder =
10070                 (enum transcoder) to_intel_crtc(crtc)->pipe;
10071         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10072
10073         /*
10074          * Sanitize sync polarity flags based on requested ones. If neither
10075          * positive or negative polarity is requested, treat this as meaning
10076          * negative polarity.
10077          */
10078         if (!(pipe_config->adjusted_mode.flags &
10079               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10080                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10081
10082         if (!(pipe_config->adjusted_mode.flags &
10083               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10084                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10085
10086         /* Compute a starting value for pipe_config->pipe_bpp taking the source
10087          * plane pixel format and any sink constraints into account. Returns the
10088          * source plane bpp so that dithering can be selected on mismatches
10089          * after encoders and crtc also have had their say. */
10090         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10091                                               fb, pipe_config);
10092         if (plane_bpp < 0)
10093                 goto fail;
10094
10095         /*
10096          * Determine the real pipe dimensions. Note that stereo modes can
10097          * increase the actual pipe size due to the frame doubling and
10098          * insertion of additional space for blanks between the frame. This
10099          * is stored in the crtc timings. We use the requested mode to do this
10100          * computation to clearly distinguish it from the adjusted mode, which
10101          * can be changed by the connectors in the below retry loop.
10102          */
10103         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10104         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10105         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10106
10107 encoder_retry:
10108         /* Ensure the port clock defaults are reset when retrying. */
10109         pipe_config->port_clock = 0;
10110         pipe_config->pixel_multiplier = 1;
10111
10112         /* Fill in default crtc timings, allow encoders to overwrite them. */
10113         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10114
10115         /* Pass our mode to the connectors and the CRTC to give them a chance to
10116          * adjust it according to limitations or connector properties, and also
10117          * a chance to reject the mode entirely.
10118          */
10119         for_each_intel_encoder(dev, encoder) {
10120
10121                 if (&encoder->new_crtc->base != crtc)
10122                         continue;
10123
10124                 if (!(encoder->compute_config(encoder, pipe_config))) {
10125                         DRM_DEBUG_KMS("Encoder config failure\n");
10126                         goto fail;
10127                 }
10128         }
10129
10130         /* Set default port clock if not overwritten by the encoder. Needs to be
10131          * done afterwards in case the encoder adjusts the mode. */
10132         if (!pipe_config->port_clock)
10133                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10134                         * pipe_config->pixel_multiplier;
10135
10136         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10137         if (ret < 0) {
10138                 DRM_DEBUG_KMS("CRTC fixup failed\n");
10139                 goto fail;
10140         }
10141
10142         if (ret == RETRY) {
10143                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10144                         ret = -EINVAL;
10145                         goto fail;
10146                 }
10147
10148                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10149                 retry = false;
10150                 goto encoder_retry;
10151         }
10152
10153         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10154         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10155                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10156
10157         return pipe_config;
10158 fail:
10159         kfree(pipe_config);
10160         return ERR_PTR(ret);
10161 }
10162
10163 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10164  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10165 static void
10166 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10167                              unsigned *prepare_pipes, unsigned *disable_pipes)
10168 {
10169         struct intel_crtc *intel_crtc;
10170         struct drm_device *dev = crtc->dev;
10171         struct intel_encoder *encoder;
10172         struct intel_connector *connector;
10173         struct drm_crtc *tmp_crtc;
10174
10175         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10176
10177         /* Check which crtcs have changed outputs connected to them, these need
10178          * to be part of the prepare_pipes mask. We don't (yet) support global
10179          * modeset across multiple crtcs, so modeset_pipes will only have one
10180          * bit set at most. */
10181         list_for_each_entry(connector, &dev->mode_config.connector_list,
10182                             base.head) {
10183                 if (connector->base.encoder == &connector->new_encoder->base)
10184                         continue;
10185
10186                 if (connector->base.encoder) {
10187                         tmp_crtc = connector->base.encoder->crtc;
10188
10189                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10190                 }
10191
10192                 if (connector->new_encoder)
10193                         *prepare_pipes |=
10194                                 1 << connector->new_encoder->new_crtc->pipe;
10195         }
10196
10197         for_each_intel_encoder(dev, encoder) {
10198                 if (encoder->base.crtc == &encoder->new_crtc->base)
10199                         continue;
10200
10201                 if (encoder->base.crtc) {
10202                         tmp_crtc = encoder->base.crtc;
10203
10204                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10205                 }
10206
10207                 if (encoder->new_crtc)
10208                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10209         }
10210
10211         /* Check for pipes that will be enabled/disabled ... */
10212         for_each_intel_crtc(dev, intel_crtc) {
10213                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10214                         continue;
10215
10216                 if (!intel_crtc->new_enabled)
10217                         *disable_pipes |= 1 << intel_crtc->pipe;
10218                 else
10219                         *prepare_pipes |= 1 << intel_crtc->pipe;
10220         }
10221
10222
10223         /* set_mode is also used to update properties on life display pipes. */
10224         intel_crtc = to_intel_crtc(crtc);
10225         if (intel_crtc->new_enabled)
10226                 *prepare_pipes |= 1 << intel_crtc->pipe;
10227
10228         /*
10229          * For simplicity do a full modeset on any pipe where the output routing
10230          * changed. We could be more clever, but that would require us to be
10231          * more careful with calling the relevant encoder->mode_set functions.
10232          */
10233         if (*prepare_pipes)
10234                 *modeset_pipes = *prepare_pipes;
10235
10236         /* ... and mask these out. */
10237         *modeset_pipes &= ~(*disable_pipes);
10238         *prepare_pipes &= ~(*disable_pipes);
10239
10240         /*
10241          * HACK: We don't (yet) fully support global modesets. intel_set_config
10242          * obies this rule, but the modeset restore mode of
10243          * intel_modeset_setup_hw_state does not.
10244          */
10245         *modeset_pipes &= 1 << intel_crtc->pipe;
10246         *prepare_pipes &= 1 << intel_crtc->pipe;
10247
10248         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10249                       *modeset_pipes, *prepare_pipes, *disable_pipes);
10250 }
10251
10252 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10253 {
10254         struct drm_encoder *encoder;
10255         struct drm_device *dev = crtc->dev;
10256
10257         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10258                 if (encoder->crtc == crtc)
10259                         return true;
10260
10261         return false;
10262 }
10263
10264 static void
10265 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10266 {
10267         struct drm_i915_private *dev_priv = dev->dev_private;
10268         struct intel_encoder *intel_encoder;
10269         struct intel_crtc *intel_crtc;
10270         struct drm_connector *connector;
10271
10272         intel_shared_dpll_commit(dev_priv);
10273
10274         for_each_intel_encoder(dev, intel_encoder) {
10275                 if (!intel_encoder->base.crtc)
10276                         continue;
10277
10278                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10279
10280                 if (prepare_pipes & (1 << intel_crtc->pipe))
10281                         intel_encoder->connectors_active = false;
10282         }
10283
10284         intel_modeset_commit_output_state(dev);
10285
10286         /* Double check state. */
10287         for_each_intel_crtc(dev, intel_crtc) {
10288                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10289                 WARN_ON(intel_crtc->new_config &&
10290                         intel_crtc->new_config != &intel_crtc->config);
10291                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10292         }
10293
10294         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10295                 if (!connector->encoder || !connector->encoder->crtc)
10296                         continue;
10297
10298                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10299
10300                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10301                         struct drm_property *dpms_property =
10302                                 dev->mode_config.dpms_property;
10303
10304                         connector->dpms = DRM_MODE_DPMS_ON;
10305                         drm_object_property_set_value(&connector->base,
10306                                                          dpms_property,
10307                                                          DRM_MODE_DPMS_ON);
10308
10309                         intel_encoder = to_intel_encoder(connector->encoder);
10310                         intel_encoder->connectors_active = true;
10311                 }
10312         }
10313
10314 }
10315
10316 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10317 {
10318         int diff;
10319
10320         if (clock1 == clock2)
10321                 return true;
10322
10323         if (!clock1 || !clock2)
10324                 return false;
10325
10326         diff = abs(clock1 - clock2);
10327
10328         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10329                 return true;
10330
10331         return false;
10332 }
10333
10334 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10335         list_for_each_entry((intel_crtc), \
10336                             &(dev)->mode_config.crtc_list, \
10337                             base.head) \
10338                 if (mask & (1 <<(intel_crtc)->pipe))
10339
10340 static bool
10341 intel_pipe_config_compare(struct drm_device *dev,
10342                           struct intel_crtc_config *current_config,
10343                           struct intel_crtc_config *pipe_config)
10344 {
10345 #define PIPE_CONF_CHECK_X(name) \
10346         if (current_config->name != pipe_config->name) { \
10347                 DRM_ERROR("mismatch in " #name " " \
10348                           "(expected 0x%08x, found 0x%08x)\n", \
10349                           current_config->name, \
10350                           pipe_config->name); \
10351                 return false; \
10352         }
10353
10354 #define PIPE_CONF_CHECK_I(name) \
10355         if (current_config->name != pipe_config->name) { \
10356                 DRM_ERROR("mismatch in " #name " " \
10357                           "(expected %i, found %i)\n", \
10358                           current_config->name, \
10359                           pipe_config->name); \
10360                 return false; \
10361         }
10362
10363 /* This is required for BDW+ where there is only one set of registers for
10364  * switching between high and low RR.
10365  * This macro can be used whenever a comparison has to be made between one
10366  * hw state and multiple sw state variables.
10367  */
10368 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10369         if ((current_config->name != pipe_config->name) && \
10370                 (current_config->alt_name != pipe_config->name)) { \
10371                         DRM_ERROR("mismatch in " #name " " \
10372                                   "(expected %i or %i, found %i)\n", \
10373                                   current_config->name, \
10374                                   current_config->alt_name, \
10375                                   pipe_config->name); \
10376                         return false; \
10377         }
10378
10379 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
10380         if ((current_config->name ^ pipe_config->name) & (mask)) { \
10381                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
10382                           "(expected %i, found %i)\n", \
10383                           current_config->name & (mask), \
10384                           pipe_config->name & (mask)); \
10385                 return false; \
10386         }
10387
10388 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10389         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10390                 DRM_ERROR("mismatch in " #name " " \
10391                           "(expected %i, found %i)\n", \
10392                           current_config->name, \
10393                           pipe_config->name); \
10394                 return false; \
10395         }
10396
10397 #define PIPE_CONF_QUIRK(quirk)  \
10398         ((current_config->quirks | pipe_config->quirks) & (quirk))
10399
10400         PIPE_CONF_CHECK_I(cpu_transcoder);
10401
10402         PIPE_CONF_CHECK_I(has_pch_encoder);
10403         PIPE_CONF_CHECK_I(fdi_lanes);
10404         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10405         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10406         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10407         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10408         PIPE_CONF_CHECK_I(fdi_m_n.tu);
10409
10410         PIPE_CONF_CHECK_I(has_dp_encoder);
10411
10412         if (INTEL_INFO(dev)->gen < 8) {
10413                 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10414                 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10415                 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10416                 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10417                 PIPE_CONF_CHECK_I(dp_m_n.tu);
10418
10419                 if (current_config->has_drrs) {
10420                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10421                         PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10422                         PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10423                         PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10424                         PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10425                 }
10426         } else {
10427                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10428                 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10429                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10430                 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10431                 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10432         }
10433
10434         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10435         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10436         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10437         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10438         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10439         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10440
10441         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10442         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10443         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10444         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10445         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10446         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10447
10448         PIPE_CONF_CHECK_I(pixel_multiplier);
10449         PIPE_CONF_CHECK_I(has_hdmi_sink);
10450         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10451             IS_VALLEYVIEW(dev))
10452                 PIPE_CONF_CHECK_I(limited_color_range);
10453         PIPE_CONF_CHECK_I(has_infoframe);
10454
10455         PIPE_CONF_CHECK_I(has_audio);
10456
10457         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10458                               DRM_MODE_FLAG_INTERLACE);
10459
10460         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10461                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10462                                       DRM_MODE_FLAG_PHSYNC);
10463                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10464                                       DRM_MODE_FLAG_NHSYNC);
10465                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10466                                       DRM_MODE_FLAG_PVSYNC);
10467                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10468                                       DRM_MODE_FLAG_NVSYNC);
10469         }
10470
10471         PIPE_CONF_CHECK_I(pipe_src_w);
10472         PIPE_CONF_CHECK_I(pipe_src_h);
10473
10474         /*
10475          * FIXME: BIOS likes to set up a cloned config with lvds+external
10476          * screen. Since we don't yet re-compute the pipe config when moving
10477          * just the lvds port away to another pipe the sw tracking won't match.
10478          *
10479          * Proper atomic modesets with recomputed global state will fix this.
10480          * Until then just don't check gmch state for inherited modes.
10481          */
10482         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10483                 PIPE_CONF_CHECK_I(gmch_pfit.control);
10484                 /* pfit ratios are autocomputed by the hw on gen4+ */
10485                 if (INTEL_INFO(dev)->gen < 4)
10486                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10487                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10488         }
10489
10490         PIPE_CONF_CHECK_I(pch_pfit.enabled);
10491         if (current_config->pch_pfit.enabled) {
10492                 PIPE_CONF_CHECK_I(pch_pfit.pos);
10493                 PIPE_CONF_CHECK_I(pch_pfit.size);
10494         }
10495
10496         /* BDW+ don't expose a synchronous way to read the state */
10497         if (IS_HASWELL(dev))
10498                 PIPE_CONF_CHECK_I(ips_enabled);
10499
10500         PIPE_CONF_CHECK_I(double_wide);
10501
10502         PIPE_CONF_CHECK_X(ddi_pll_sel);
10503
10504         PIPE_CONF_CHECK_I(shared_dpll);
10505         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10506         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10507         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10508         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10509         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10510         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10511         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10512         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10513
10514         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10515                 PIPE_CONF_CHECK_I(pipe_bpp);
10516
10517         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10518         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10519
10520 #undef PIPE_CONF_CHECK_X
10521 #undef PIPE_CONF_CHECK_I
10522 #undef PIPE_CONF_CHECK_I_ALT
10523 #undef PIPE_CONF_CHECK_FLAGS
10524 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10525 #undef PIPE_CONF_QUIRK
10526
10527         return true;
10528 }
10529
10530 static void check_wm_state(struct drm_device *dev)
10531 {
10532         struct drm_i915_private *dev_priv = dev->dev_private;
10533         struct skl_ddb_allocation hw_ddb, *sw_ddb;
10534         struct intel_crtc *intel_crtc;
10535         int plane;
10536
10537         if (INTEL_INFO(dev)->gen < 9)
10538                 return;
10539
10540         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10541         sw_ddb = &dev_priv->wm.skl_hw.ddb;
10542
10543         for_each_intel_crtc(dev, intel_crtc) {
10544                 struct skl_ddb_entry *hw_entry, *sw_entry;
10545                 const enum pipe pipe = intel_crtc->pipe;
10546
10547                 if (!intel_crtc->active)
10548                         continue;
10549
10550                 /* planes */
10551                 for_each_plane(pipe, plane) {
10552                         hw_entry = &hw_ddb.plane[pipe][plane];
10553                         sw_entry = &sw_ddb->plane[pipe][plane];
10554
10555                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
10556                                 continue;
10557
10558                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10559                                   "(expected (%u,%u), found (%u,%u))\n",
10560                                   pipe_name(pipe), plane + 1,
10561                                   sw_entry->start, sw_entry->end,
10562                                   hw_entry->start, hw_entry->end);
10563                 }
10564
10565                 /* cursor */
10566                 hw_entry = &hw_ddb.cursor[pipe];
10567                 sw_entry = &sw_ddb->cursor[pipe];
10568
10569                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10570                         continue;
10571
10572                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10573                           "(expected (%u,%u), found (%u,%u))\n",
10574                           pipe_name(pipe),
10575                           sw_entry->start, sw_entry->end,
10576                           hw_entry->start, hw_entry->end);
10577         }
10578 }
10579
10580 static void
10581 check_connector_state(struct drm_device *dev)
10582 {
10583         struct intel_connector *connector;
10584
10585         list_for_each_entry(connector, &dev->mode_config.connector_list,
10586                             base.head) {
10587                 /* This also checks the encoder/connector hw state with the
10588                  * ->get_hw_state callbacks. */
10589                 intel_connector_check_state(connector);
10590
10591                 WARN(&connector->new_encoder->base != connector->base.encoder,
10592                      "connector's staged encoder doesn't match current encoder\n");
10593         }
10594 }
10595
10596 static void
10597 check_encoder_state(struct drm_device *dev)
10598 {
10599         struct intel_encoder *encoder;
10600         struct intel_connector *connector;
10601
10602         for_each_intel_encoder(dev, encoder) {
10603                 bool enabled = false;
10604                 bool active = false;
10605                 enum pipe pipe, tracked_pipe;
10606
10607                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10608                               encoder->base.base.id,
10609                               encoder->base.name);
10610
10611                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10612                      "encoder's stage crtc doesn't match current crtc\n");
10613                 WARN(encoder->connectors_active && !encoder->base.crtc,
10614                      "encoder's active_connectors set, but no crtc\n");
10615
10616                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10617                                     base.head) {
10618                         if (connector->base.encoder != &encoder->base)
10619                                 continue;
10620                         enabled = true;
10621                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10622                                 active = true;
10623                 }
10624                 /*
10625                  * for MST connectors if we unplug the connector is gone
10626                  * away but the encoder is still connected to a crtc
10627                  * until a modeset happens in response to the hotplug.
10628                  */
10629                 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10630                         continue;
10631
10632                 WARN(!!encoder->base.crtc != enabled,
10633                      "encoder's enabled state mismatch "
10634                      "(expected %i, found %i)\n",
10635                      !!encoder->base.crtc, enabled);
10636                 WARN(active && !encoder->base.crtc,
10637                      "active encoder with no crtc\n");
10638
10639                 WARN(encoder->connectors_active != active,
10640                      "encoder's computed active state doesn't match tracked active state "
10641                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10642
10643                 active = encoder->get_hw_state(encoder, &pipe);
10644                 WARN(active != encoder->connectors_active,
10645                      "encoder's hw state doesn't match sw tracking "
10646                      "(expected %i, found %i)\n",
10647                      encoder->connectors_active, active);
10648
10649                 if (!encoder->base.crtc)
10650                         continue;
10651
10652                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10653                 WARN(active && pipe != tracked_pipe,
10654                      "active encoder's pipe doesn't match"
10655                      "(expected %i, found %i)\n",
10656                      tracked_pipe, pipe);
10657
10658         }
10659 }
10660
10661 static void
10662 check_crtc_state(struct drm_device *dev)
10663 {
10664         struct drm_i915_private *dev_priv = dev->dev_private;
10665         struct intel_crtc *crtc;
10666         struct intel_encoder *encoder;
10667         struct intel_crtc_config pipe_config;
10668
10669         for_each_intel_crtc(dev, crtc) {
10670                 bool enabled = false;
10671                 bool active = false;
10672
10673                 memset(&pipe_config, 0, sizeof(pipe_config));
10674
10675                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10676                               crtc->base.base.id);
10677
10678                 WARN(crtc->active && !crtc->base.enabled,
10679                      "active crtc, but not enabled in sw tracking\n");
10680
10681                 for_each_intel_encoder(dev, encoder) {
10682                         if (encoder->base.crtc != &crtc->base)
10683                                 continue;
10684                         enabled = true;
10685                         if (encoder->connectors_active)
10686                                 active = true;
10687                 }
10688
10689                 WARN(active != crtc->active,
10690                      "crtc's computed active state doesn't match tracked active state "
10691                      "(expected %i, found %i)\n", active, crtc->active);
10692                 WARN(enabled != crtc->base.enabled,
10693                      "crtc's computed enabled state doesn't match tracked enabled state "
10694                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10695
10696                 active = dev_priv->display.get_pipe_config(crtc,
10697                                                            &pipe_config);
10698
10699                 /* hw state is inconsistent with the pipe quirk */
10700                 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10701                     (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10702                         active = crtc->active;
10703
10704                 for_each_intel_encoder(dev, encoder) {
10705                         enum pipe pipe;
10706                         if (encoder->base.crtc != &crtc->base)
10707                                 continue;
10708                         if (encoder->get_hw_state(encoder, &pipe))
10709                                 encoder->get_config(encoder, &pipe_config);
10710                 }
10711
10712                 WARN(crtc->active != active,
10713                      "crtc active state doesn't match with hw state "
10714                      "(expected %i, found %i)\n", crtc->active, active);
10715
10716                 if (active &&
10717                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10718                         WARN(1, "pipe state doesn't match!\n");
10719                         intel_dump_pipe_config(crtc, &pipe_config,
10720                                                "[hw state]");
10721                         intel_dump_pipe_config(crtc, &crtc->config,
10722                                                "[sw state]");
10723                 }
10724         }
10725 }
10726
10727 static void
10728 check_shared_dpll_state(struct drm_device *dev)
10729 {
10730         struct drm_i915_private *dev_priv = dev->dev_private;
10731         struct intel_crtc *crtc;
10732         struct intel_dpll_hw_state dpll_hw_state;
10733         int i;
10734
10735         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10736                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10737                 int enabled_crtcs = 0, active_crtcs = 0;
10738                 bool active;
10739
10740                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10741
10742                 DRM_DEBUG_KMS("%s\n", pll->name);
10743
10744                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10745
10746                 WARN(pll->active > hweight32(pll->config.crtc_mask),
10747                      "more active pll users than references: %i vs %i\n",
10748                      pll->active, hweight32(pll->config.crtc_mask));
10749                 WARN(pll->active && !pll->on,
10750                      "pll in active use but not on in sw tracking\n");
10751                 WARN(pll->on && !pll->active,
10752                      "pll in on but not on in use in sw tracking\n");
10753                 WARN(pll->on != active,
10754                      "pll on state mismatch (expected %i, found %i)\n",
10755                      pll->on, active);
10756
10757                 for_each_intel_crtc(dev, crtc) {
10758                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10759                                 enabled_crtcs++;
10760                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10761                                 active_crtcs++;
10762                 }
10763                 WARN(pll->active != active_crtcs,
10764                      "pll active crtcs mismatch (expected %i, found %i)\n",
10765                      pll->active, active_crtcs);
10766                 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10767                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10768                      hweight32(pll->config.crtc_mask), enabled_crtcs);
10769
10770                 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10771                                        sizeof(dpll_hw_state)),
10772                      "pll hw state mismatch\n");
10773         }
10774 }
10775
10776 void
10777 intel_modeset_check_state(struct drm_device *dev)
10778 {
10779         check_wm_state(dev);
10780         check_connector_state(dev);
10781         check_encoder_state(dev);
10782         check_crtc_state(dev);
10783         check_shared_dpll_state(dev);
10784 }
10785
10786 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10787                                      int dotclock)
10788 {
10789         /*
10790          * FDI already provided one idea for the dotclock.
10791          * Yell if the encoder disagrees.
10792          */
10793         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10794              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10795              pipe_config->adjusted_mode.crtc_clock, dotclock);
10796 }
10797
10798 static void update_scanline_offset(struct intel_crtc *crtc)
10799 {
10800         struct drm_device *dev = crtc->base.dev;
10801
10802         /*
10803          * The scanline counter increments at the leading edge of hsync.
10804          *
10805          * On most platforms it starts counting from vtotal-1 on the
10806          * first active line. That means the scanline counter value is
10807          * always one less than what we would expect. Ie. just after
10808          * start of vblank, which also occurs at start of hsync (on the
10809          * last active line), the scanline counter will read vblank_start-1.
10810          *
10811          * On gen2 the scanline counter starts counting from 1 instead
10812          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10813          * to keep the value positive), instead of adding one.
10814          *
10815          * On HSW+ the behaviour of the scanline counter depends on the output
10816          * type. For DP ports it behaves like most other platforms, but on HDMI
10817          * there's an extra 1 line difference. So we need to add two instead of
10818          * one to the value.
10819          */
10820         if (IS_GEN2(dev)) {
10821                 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10822                 int vtotal;
10823
10824                 vtotal = mode->crtc_vtotal;
10825                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10826                         vtotal /= 2;
10827
10828                 crtc->scanline_offset = vtotal - 1;
10829         } else if (HAS_DDI(dev) &&
10830                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10831                 crtc->scanline_offset = 2;
10832         } else
10833                 crtc->scanline_offset = 1;
10834 }
10835
10836 static struct intel_crtc_config *
10837 intel_modeset_compute_config(struct drm_crtc *crtc,
10838                              struct drm_display_mode *mode,
10839                              struct drm_framebuffer *fb,
10840                              unsigned *modeset_pipes,
10841                              unsigned *prepare_pipes,
10842                              unsigned *disable_pipes)
10843 {
10844         struct intel_crtc_config *pipe_config = NULL;
10845
10846         intel_modeset_affected_pipes(crtc, modeset_pipes,
10847                                      prepare_pipes, disable_pipes);
10848
10849         if ((*modeset_pipes) == 0)
10850                 goto out;
10851
10852         /*
10853          * Note this needs changes when we start tracking multiple modes
10854          * and crtcs.  At that point we'll need to compute the whole config
10855          * (i.e. one pipe_config for each crtc) rather than just the one
10856          * for this crtc.
10857          */
10858         pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10859         if (IS_ERR(pipe_config)) {
10860                 goto out;
10861         }
10862         intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10863                                "[modeset]");
10864         to_intel_crtc(crtc)->new_config = pipe_config;
10865
10866 out:
10867         return pipe_config;
10868 }
10869
10870 static int __intel_set_mode(struct drm_crtc *crtc,
10871                             struct drm_display_mode *mode,
10872                             int x, int y, struct drm_framebuffer *fb,
10873                             struct intel_crtc_config *pipe_config,
10874                             unsigned modeset_pipes,
10875                             unsigned prepare_pipes,
10876                             unsigned disable_pipes)
10877 {
10878         struct drm_device *dev = crtc->dev;
10879         struct drm_i915_private *dev_priv = dev->dev_private;
10880         struct drm_display_mode *saved_mode;
10881         struct intel_crtc *intel_crtc;
10882         int ret = 0;
10883
10884         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10885         if (!saved_mode)
10886                 return -ENOMEM;
10887
10888         *saved_mode = crtc->mode;
10889
10890         /*
10891          * See if the config requires any additional preparation, e.g.
10892          * to adjust global state with pipes off.  We need to do this
10893          * here so we can get the modeset_pipe updated config for the new
10894          * mode set on this crtc.  For other crtcs we need to use the
10895          * adjusted_mode bits in the crtc directly.
10896          */
10897         if (IS_VALLEYVIEW(dev)) {
10898                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10899
10900                 /* may have added more to prepare_pipes than we should */
10901                 prepare_pipes &= ~disable_pipes;
10902         }
10903
10904         if (dev_priv->display.crtc_compute_clock) {
10905                 unsigned clear_pipes = modeset_pipes | disable_pipes;
10906
10907                 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10908                 if (ret)
10909                         goto done;
10910
10911                 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10912                         ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10913                         if (ret) {
10914                                 intel_shared_dpll_abort_config(dev_priv);
10915                                 goto done;
10916                         }
10917                 }
10918         }
10919
10920         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10921                 intel_crtc_disable(&intel_crtc->base);
10922
10923         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10924                 if (intel_crtc->base.enabled)
10925                         dev_priv->display.crtc_disable(&intel_crtc->base);
10926         }
10927
10928         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10929          * to set it here already despite that we pass it down the callchain.
10930          *
10931          * Note we'll need to fix this up when we start tracking multiple
10932          * pipes; here we assume a single modeset_pipe and only track the
10933          * single crtc and mode.
10934          */
10935         if (modeset_pipes) {
10936                 crtc->mode = *mode;
10937                 /* mode_set/enable/disable functions rely on a correct pipe
10938                  * config. */
10939                 to_intel_crtc(crtc)->config = *pipe_config;
10940                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10941
10942                 /*
10943                  * Calculate and store various constants which
10944                  * are later needed by vblank and swap-completion
10945                  * timestamping. They are derived from true hwmode.
10946                  */
10947                 drm_calc_timestamping_constants(crtc,
10948                                                 &pipe_config->adjusted_mode);
10949         }
10950
10951         /* Only after disabling all output pipelines that will be changed can we
10952          * update the the output configuration. */
10953         intel_modeset_update_state(dev, prepare_pipes);
10954
10955         modeset_update_crtc_power_domains(dev);
10956
10957         /* Set up the DPLL and any encoders state that needs to adjust or depend
10958          * on the DPLL.
10959          */
10960         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10961                 struct drm_framebuffer *old_fb = crtc->primary->fb;
10962                 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10963                 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10964
10965                 mutex_lock(&dev->struct_mutex);
10966                 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10967                 if (ret != 0) {
10968                         DRM_ERROR("pin & fence failed\n");
10969                         mutex_unlock(&dev->struct_mutex);
10970                         goto done;
10971                 }
10972                 if (old_fb)
10973                         intel_unpin_fb_obj(old_obj);
10974                 i915_gem_track_fb(old_obj, obj,
10975                                   INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10976                 mutex_unlock(&dev->struct_mutex);
10977
10978                 crtc->primary->fb = fb;
10979                 crtc->x = x;
10980                 crtc->y = y;
10981         }
10982
10983         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10984         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10985                 update_scanline_offset(intel_crtc);
10986
10987                 dev_priv->display.crtc_enable(&intel_crtc->base);
10988         }
10989
10990         /* FIXME: add subpixel order */
10991 done:
10992         if (ret && crtc->enabled)
10993                 crtc->mode = *saved_mode;
10994
10995         kfree(pipe_config);
10996         kfree(saved_mode);
10997         return ret;
10998 }
10999
11000 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11001                                 struct drm_display_mode *mode,
11002                                 int x, int y, struct drm_framebuffer *fb,
11003                                 struct intel_crtc_config *pipe_config,
11004                                 unsigned modeset_pipes,
11005                                 unsigned prepare_pipes,
11006                                 unsigned disable_pipes)
11007 {
11008         int ret;
11009
11010         ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11011                                prepare_pipes, disable_pipes);
11012
11013         if (ret == 0)
11014                 intel_modeset_check_state(crtc->dev);
11015
11016         return ret;
11017 }
11018
11019 static int intel_set_mode(struct drm_crtc *crtc,
11020                           struct drm_display_mode *mode,
11021                           int x, int y, struct drm_framebuffer *fb)
11022 {
11023         struct intel_crtc_config *pipe_config;
11024         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11025
11026         pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11027                                                    &modeset_pipes,
11028                                                    &prepare_pipes,
11029                                                    &disable_pipes);
11030
11031         if (IS_ERR(pipe_config))
11032                 return PTR_ERR(pipe_config);
11033
11034         return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11035                                     modeset_pipes, prepare_pipes,
11036                                     disable_pipes);
11037 }
11038
11039 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11040 {
11041         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11042 }
11043
11044 #undef for_each_intel_crtc_masked
11045
11046 static void intel_set_config_free(struct intel_set_config *config)
11047 {
11048         if (!config)
11049                 return;
11050
11051         kfree(config->save_connector_encoders);
11052         kfree(config->save_encoder_crtcs);
11053         kfree(config->save_crtc_enabled);
11054         kfree(config);
11055 }
11056
11057 static int intel_set_config_save_state(struct drm_device *dev,
11058                                        struct intel_set_config *config)
11059 {
11060         struct drm_crtc *crtc;
11061         struct drm_encoder *encoder;
11062         struct drm_connector *connector;
11063         int count;
11064
11065         config->save_crtc_enabled =
11066                 kcalloc(dev->mode_config.num_crtc,
11067                         sizeof(bool), GFP_KERNEL);
11068         if (!config->save_crtc_enabled)
11069                 return -ENOMEM;
11070
11071         config->save_encoder_crtcs =
11072                 kcalloc(dev->mode_config.num_encoder,
11073                         sizeof(struct drm_crtc *), GFP_KERNEL);
11074         if (!config->save_encoder_crtcs)
11075                 return -ENOMEM;
11076
11077         config->save_connector_encoders =
11078                 kcalloc(dev->mode_config.num_connector,
11079                         sizeof(struct drm_encoder *), GFP_KERNEL);
11080         if (!config->save_connector_encoders)
11081                 return -ENOMEM;
11082
11083         /* Copy data. Note that driver private data is not affected.
11084          * Should anything bad happen only the expected state is
11085          * restored, not the drivers personal bookkeeping.
11086          */
11087         count = 0;
11088         for_each_crtc(dev, crtc) {
11089                 config->save_crtc_enabled[count++] = crtc->enabled;
11090         }
11091
11092         count = 0;
11093         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11094                 config->save_encoder_crtcs[count++] = encoder->crtc;
11095         }
11096
11097         count = 0;
11098         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11099                 config->save_connector_encoders[count++] = connector->encoder;
11100         }
11101
11102         return 0;
11103 }
11104
11105 static void intel_set_config_restore_state(struct drm_device *dev,
11106                                            struct intel_set_config *config)
11107 {
11108         struct intel_crtc *crtc;
11109         struct intel_encoder *encoder;
11110         struct intel_connector *connector;
11111         int count;
11112
11113         count = 0;
11114         for_each_intel_crtc(dev, crtc) {
11115                 crtc->new_enabled = config->save_crtc_enabled[count++];
11116
11117                 if (crtc->new_enabled)
11118                         crtc->new_config = &crtc->config;
11119                 else
11120                         crtc->new_config = NULL;
11121         }
11122
11123         count = 0;
11124         for_each_intel_encoder(dev, encoder) {
11125                 encoder->new_crtc =
11126                         to_intel_crtc(config->save_encoder_crtcs[count++]);
11127         }
11128
11129         count = 0;
11130         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11131                 connector->new_encoder =
11132                         to_intel_encoder(config->save_connector_encoders[count++]);
11133         }
11134 }
11135
11136 static bool
11137 is_crtc_connector_off(struct drm_mode_set *set)
11138 {
11139         int i;
11140
11141         if (set->num_connectors == 0)
11142                 return false;
11143
11144         if (WARN_ON(set->connectors == NULL))
11145                 return false;
11146
11147         for (i = 0; i < set->num_connectors; i++)
11148                 if (set->connectors[i]->encoder &&
11149                     set->connectors[i]->encoder->crtc == set->crtc &&
11150                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11151                         return true;
11152
11153         return false;
11154 }
11155
11156 static void
11157 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11158                                       struct intel_set_config *config)
11159 {
11160
11161         /* We should be able to check here if the fb has the same properties
11162          * and then just flip_or_move it */
11163         if (is_crtc_connector_off(set)) {
11164                 config->mode_changed = true;
11165         } else if (set->crtc->primary->fb != set->fb) {
11166                 /*
11167                  * If we have no fb, we can only flip as long as the crtc is
11168                  * active, otherwise we need a full mode set.  The crtc may
11169                  * be active if we've only disabled the primary plane, or
11170                  * in fastboot situations.
11171                  */
11172                 if (set->crtc->primary->fb == NULL) {
11173                         struct intel_crtc *intel_crtc =
11174                                 to_intel_crtc(set->crtc);
11175
11176                         if (intel_crtc->active) {
11177                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11178                                 config->fb_changed = true;
11179                         } else {
11180                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11181                                 config->mode_changed = true;
11182                         }
11183                 } else if (set->fb == NULL) {
11184                         config->mode_changed = true;
11185                 } else if (set->fb->pixel_format !=
11186                            set->crtc->primary->fb->pixel_format) {
11187                         config->mode_changed = true;
11188                 } else {
11189                         config->fb_changed = true;
11190                 }
11191         }
11192
11193         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11194                 config->fb_changed = true;
11195
11196         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11197                 DRM_DEBUG_KMS("modes are different, full mode set\n");
11198                 drm_mode_debug_printmodeline(&set->crtc->mode);
11199                 drm_mode_debug_printmodeline(set->mode);
11200                 config->mode_changed = true;
11201         }
11202
11203         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11204                         set->crtc->base.id, config->mode_changed, config->fb_changed);
11205 }
11206
11207 static int
11208 intel_modeset_stage_output_state(struct drm_device *dev,
11209                                  struct drm_mode_set *set,
11210                                  struct intel_set_config *config)
11211 {
11212         struct intel_connector *connector;
11213         struct intel_encoder *encoder;
11214         struct intel_crtc *crtc;
11215         int ro;
11216
11217         /* The upper layers ensure that we either disable a crtc or have a list
11218          * of connectors. For paranoia, double-check this. */
11219         WARN_ON(!set->fb && (set->num_connectors != 0));
11220         WARN_ON(set->fb && (set->num_connectors == 0));
11221
11222         list_for_each_entry(connector, &dev->mode_config.connector_list,
11223                             base.head) {
11224                 /* Otherwise traverse passed in connector list and get encoders
11225                  * for them. */
11226                 for (ro = 0; ro < set->num_connectors; ro++) {
11227                         if (set->connectors[ro] == &connector->base) {
11228                                 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11229                                 break;
11230                         }
11231                 }
11232
11233                 /* If we disable the crtc, disable all its connectors. Also, if
11234                  * the connector is on the changing crtc but not on the new
11235                  * connector list, disable it. */
11236                 if ((!set->fb || ro == set->num_connectors) &&
11237                     connector->base.encoder &&
11238                     connector->base.encoder->crtc == set->crtc) {
11239                         connector->new_encoder = NULL;
11240
11241                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11242                                 connector->base.base.id,
11243                                 connector->base.name);
11244                 }
11245
11246
11247                 if (&connector->new_encoder->base != connector->base.encoder) {
11248                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11249                         config->mode_changed = true;
11250                 }
11251         }
11252         /* connector->new_encoder is now updated for all connectors. */
11253
11254         /* Update crtc of enabled connectors. */
11255         list_for_each_entry(connector, &dev->mode_config.connector_list,
11256                             base.head) {
11257                 struct drm_crtc *new_crtc;
11258
11259                 if (!connector->new_encoder)
11260                         continue;
11261
11262                 new_crtc = connector->new_encoder->base.crtc;
11263
11264                 for (ro = 0; ro < set->num_connectors; ro++) {
11265                         if (set->connectors[ro] == &connector->base)
11266                                 new_crtc = set->crtc;
11267                 }
11268
11269                 /* Make sure the new CRTC will work with the encoder */
11270                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11271                                          new_crtc)) {
11272                         return -EINVAL;
11273                 }
11274                 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11275
11276                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11277                         connector->base.base.id,
11278                         connector->base.name,
11279                         new_crtc->base.id);
11280         }
11281
11282         /* Check for any encoders that needs to be disabled. */
11283         for_each_intel_encoder(dev, encoder) {
11284                 int num_connectors = 0;
11285                 list_for_each_entry(connector,
11286                                     &dev->mode_config.connector_list,
11287                                     base.head) {
11288                         if (connector->new_encoder == encoder) {
11289                                 WARN_ON(!connector->new_encoder->new_crtc);
11290                                 num_connectors++;
11291                         }
11292                 }
11293
11294                 if (num_connectors == 0)
11295                         encoder->new_crtc = NULL;
11296                 else if (num_connectors > 1)
11297                         return -EINVAL;
11298
11299                 /* Only now check for crtc changes so we don't miss encoders
11300                  * that will be disabled. */
11301                 if (&encoder->new_crtc->base != encoder->base.crtc) {
11302                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11303                         config->mode_changed = true;
11304                 }
11305         }
11306         /* Now we've also updated encoder->new_crtc for all encoders. */
11307         list_for_each_entry(connector, &dev->mode_config.connector_list,
11308                             base.head) {
11309                 if (connector->new_encoder)
11310                         if (connector->new_encoder != connector->encoder)
11311                                 connector->encoder = connector->new_encoder;
11312         }
11313         for_each_intel_crtc(dev, crtc) {
11314                 crtc->new_enabled = false;
11315
11316                 for_each_intel_encoder(dev, encoder) {
11317                         if (encoder->new_crtc == crtc) {
11318                                 crtc->new_enabled = true;
11319                                 break;
11320                         }
11321                 }
11322
11323                 if (crtc->new_enabled != crtc->base.enabled) {
11324                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11325                                       crtc->new_enabled ? "en" : "dis");
11326                         config->mode_changed = true;
11327                 }
11328
11329                 if (crtc->new_enabled)
11330                         crtc->new_config = &crtc->config;
11331                 else
11332                         crtc->new_config = NULL;
11333         }
11334
11335         return 0;
11336 }
11337
11338 static void disable_crtc_nofb(struct intel_crtc *crtc)
11339 {
11340         struct drm_device *dev = crtc->base.dev;
11341         struct intel_encoder *encoder;
11342         struct intel_connector *connector;
11343
11344         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11345                       pipe_name(crtc->pipe));
11346
11347         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11348                 if (connector->new_encoder &&
11349                     connector->new_encoder->new_crtc == crtc)
11350                         connector->new_encoder = NULL;
11351         }
11352
11353         for_each_intel_encoder(dev, encoder) {
11354                 if (encoder->new_crtc == crtc)
11355                         encoder->new_crtc = NULL;
11356         }
11357
11358         crtc->new_enabled = false;
11359         crtc->new_config = NULL;
11360 }
11361
11362 static int intel_crtc_set_config(struct drm_mode_set *set)
11363 {
11364         struct drm_device *dev;
11365         struct drm_mode_set save_set;
11366         struct intel_set_config *config;
11367         struct intel_crtc_config *pipe_config;
11368         unsigned modeset_pipes, prepare_pipes, disable_pipes;
11369         int ret;
11370
11371         BUG_ON(!set);
11372         BUG_ON(!set->crtc);
11373         BUG_ON(!set->crtc->helper_private);
11374
11375         /* Enforce sane interface api - has been abused by the fb helper. */
11376         BUG_ON(!set->mode && set->fb);
11377         BUG_ON(set->fb && set->num_connectors == 0);
11378
11379         if (set->fb) {
11380                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11381                                 set->crtc->base.id, set->fb->base.id,
11382                                 (int)set->num_connectors, set->x, set->y);
11383         } else {
11384                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11385         }
11386
11387         dev = set->crtc->dev;
11388
11389         ret = -ENOMEM;
11390         config = kzalloc(sizeof(*config), GFP_KERNEL);
11391         if (!config)
11392                 goto out_config;
11393
11394         ret = intel_set_config_save_state(dev, config);
11395         if (ret)
11396                 goto out_config;
11397
11398         save_set.crtc = set->crtc;
11399         save_set.mode = &set->crtc->mode;
11400         save_set.x = set->crtc->x;
11401         save_set.y = set->crtc->y;
11402         save_set.fb = set->crtc->primary->fb;
11403
11404         /* Compute whether we need a full modeset, only an fb base update or no
11405          * change at all. In the future we might also check whether only the
11406          * mode changed, e.g. for LVDS where we only change the panel fitter in
11407          * such cases. */
11408         intel_set_config_compute_mode_changes(set, config);
11409
11410         ret = intel_modeset_stage_output_state(dev, set, config);
11411         if (ret)
11412                 goto fail;
11413
11414         pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11415                                                    set->fb,
11416                                                    &modeset_pipes,
11417                                                    &prepare_pipes,
11418                                                    &disable_pipes);
11419         if (IS_ERR(pipe_config)) {
11420                 goto fail;
11421         } else if (pipe_config) {
11422                 if (to_intel_crtc(set->crtc)->new_config->has_audio !=
11423                     to_intel_crtc(set->crtc)->config.has_audio)
11424                         config->mode_changed = true;
11425
11426                 /* Force mode sets for any infoframe stuff */
11427                 if (to_intel_crtc(set->crtc)->new_config->has_infoframe ||
11428                     to_intel_crtc(set->crtc)->config.has_infoframe)
11429                         config->mode_changed = true;
11430         }
11431
11432         /* set_mode will free it in the mode_changed case */
11433         if (!config->mode_changed)
11434                 kfree(pipe_config);
11435
11436         intel_update_pipe_size(to_intel_crtc(set->crtc));
11437
11438         if (config->mode_changed) {
11439                 ret = intel_set_mode_pipes(set->crtc, set->mode,
11440                                            set->x, set->y, set->fb, pipe_config,
11441                                            modeset_pipes, prepare_pipes,
11442                                            disable_pipes);
11443         } else if (config->fb_changed) {
11444                 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11445
11446                 intel_crtc_wait_for_pending_flips(set->crtc);
11447
11448                 ret = intel_pipe_set_base(set->crtc,
11449                                           set->x, set->y, set->fb);
11450
11451                 /*
11452                  * We need to make sure the primary plane is re-enabled if it
11453                  * has previously been turned off.
11454                  */
11455                 if (!intel_crtc->primary_enabled && ret == 0) {
11456                         WARN_ON(!intel_crtc->active);
11457                         intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11458                 }
11459
11460                 /*
11461                  * In the fastboot case this may be our only check of the
11462                  * state after boot.  It would be better to only do it on
11463                  * the first update, but we don't have a nice way of doing that
11464                  * (and really, set_config isn't used much for high freq page
11465                  * flipping, so increasing its cost here shouldn't be a big
11466                  * deal).
11467                  */
11468                 if (i915.fastboot && ret == 0)
11469                         intel_modeset_check_state(set->crtc->dev);
11470         }
11471
11472         if (ret) {
11473                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11474                               set->crtc->base.id, ret);
11475 fail:
11476                 intel_set_config_restore_state(dev, config);
11477
11478                 /*
11479                  * HACK: if the pipe was on, but we didn't have a framebuffer,
11480                  * force the pipe off to avoid oopsing in the modeset code
11481                  * due to fb==NULL. This should only happen during boot since
11482                  * we don't yet reconstruct the FB from the hardware state.
11483                  */
11484                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11485                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11486
11487                 /* Try to restore the config */
11488                 if (config->mode_changed &&
11489                     intel_set_mode(save_set.crtc, save_set.mode,
11490                                    save_set.x, save_set.y, save_set.fb))
11491                         DRM_ERROR("failed to restore config after modeset failure\n");
11492         }
11493
11494 out_config:
11495         intel_set_config_free(config);
11496         return ret;
11497 }
11498
11499 static const struct drm_crtc_funcs intel_crtc_funcs = {
11500         .gamma_set = intel_crtc_gamma_set,
11501         .set_config = intel_crtc_set_config,
11502         .destroy = intel_crtc_destroy,
11503         .page_flip = intel_crtc_page_flip,
11504 };
11505
11506 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11507                                       struct intel_shared_dpll *pll,
11508                                       struct intel_dpll_hw_state *hw_state)
11509 {
11510         uint32_t val;
11511
11512         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11513                 return false;
11514
11515         val = I915_READ(PCH_DPLL(pll->id));
11516         hw_state->dpll = val;
11517         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11518         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11519
11520         return val & DPLL_VCO_ENABLE;
11521 }
11522
11523 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11524                                   struct intel_shared_dpll *pll)
11525 {
11526         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11527         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11528 }
11529
11530 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11531                                 struct intel_shared_dpll *pll)
11532 {
11533         /* PCH refclock must be enabled first */
11534         ibx_assert_pch_refclk_enabled(dev_priv);
11535
11536         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11537
11538         /* Wait for the clocks to stabilize. */
11539         POSTING_READ(PCH_DPLL(pll->id));
11540         udelay(150);
11541
11542         /* The pixel multiplier can only be updated once the
11543          * DPLL is enabled and the clocks are stable.
11544          *
11545          * So write it again.
11546          */
11547         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11548         POSTING_READ(PCH_DPLL(pll->id));
11549         udelay(200);
11550 }
11551
11552 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11553                                  struct intel_shared_dpll *pll)
11554 {
11555         struct drm_device *dev = dev_priv->dev;
11556         struct intel_crtc *crtc;
11557
11558         /* Make sure no transcoder isn't still depending on us. */
11559         for_each_intel_crtc(dev, crtc) {
11560                 if (intel_crtc_to_shared_dpll(crtc) == pll)
11561                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11562         }
11563
11564         I915_WRITE(PCH_DPLL(pll->id), 0);
11565         POSTING_READ(PCH_DPLL(pll->id));
11566         udelay(200);
11567 }
11568
11569 static char *ibx_pch_dpll_names[] = {
11570         "PCH DPLL A",
11571         "PCH DPLL B",
11572 };
11573
11574 static void ibx_pch_dpll_init(struct drm_device *dev)
11575 {
11576         struct drm_i915_private *dev_priv = dev->dev_private;
11577         int i;
11578
11579         dev_priv->num_shared_dpll = 2;
11580
11581         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11582                 dev_priv->shared_dplls[i].id = i;
11583                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11584                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11585                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11586                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11587                 dev_priv->shared_dplls[i].get_hw_state =
11588                         ibx_pch_dpll_get_hw_state;
11589         }
11590 }
11591
11592 static void intel_shared_dpll_init(struct drm_device *dev)
11593 {
11594         struct drm_i915_private *dev_priv = dev->dev_private;
11595
11596         if (HAS_DDI(dev))
11597                 intel_ddi_pll_init(dev);
11598         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11599                 ibx_pch_dpll_init(dev);
11600         else
11601                 dev_priv->num_shared_dpll = 0;
11602
11603         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11604 }
11605
11606 static int
11607 intel_primary_plane_disable(struct drm_plane *plane)
11608 {
11609         struct drm_device *dev = plane->dev;
11610         struct intel_crtc *intel_crtc;
11611
11612         if (!plane->fb)
11613                 return 0;
11614
11615         BUG_ON(!plane->crtc);
11616
11617         intel_crtc = to_intel_crtc(plane->crtc);
11618
11619         /*
11620          * Even though we checked plane->fb above, it's still possible that
11621          * the primary plane has been implicitly disabled because the crtc
11622          * coordinates given weren't visible, or because we detected
11623          * that it was 100% covered by a sprite plane.  Or, the CRTC may be
11624          * off and we've set a fb, but haven't actually turned on the CRTC yet.
11625          * In either case, we need to unpin the FB and let the fb pointer get
11626          * updated, but otherwise we don't need to touch the hardware.
11627          */
11628         if (!intel_crtc->primary_enabled)
11629                 goto disable_unpin;
11630
11631         intel_crtc_wait_for_pending_flips(plane->crtc);
11632         intel_disable_primary_hw_plane(plane, plane->crtc);
11633
11634 disable_unpin:
11635         mutex_lock(&dev->struct_mutex);
11636         i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11637                           INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11638         intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11639         mutex_unlock(&dev->struct_mutex);
11640         plane->fb = NULL;
11641
11642         return 0;
11643 }
11644
11645 static int
11646 intel_check_primary_plane(struct drm_plane *plane,
11647                           struct intel_plane_state *state)
11648 {
11649         struct drm_crtc *crtc = state->crtc;
11650         struct drm_framebuffer *fb = state->fb;
11651         struct drm_rect *dest = &state->dst;
11652         struct drm_rect *src = &state->src;
11653         const struct drm_rect *clip = &state->clip;
11654
11655         return drm_plane_helper_check_update(plane, crtc, fb,
11656                                              src, dest, clip,
11657                                              DRM_PLANE_HELPER_NO_SCALING,
11658                                              DRM_PLANE_HELPER_NO_SCALING,
11659                                              false, true, &state->visible);
11660 }
11661
11662 static int
11663 intel_prepare_primary_plane(struct drm_plane *plane,
11664                             struct intel_plane_state *state)
11665 {
11666         struct drm_crtc *crtc = state->crtc;
11667         struct drm_framebuffer *fb = state->fb;
11668         struct drm_device *dev = crtc->dev;
11669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11670         enum pipe pipe = intel_crtc->pipe;
11671         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11672         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11673         int ret;
11674
11675         intel_crtc_wait_for_pending_flips(crtc);
11676
11677         if (intel_crtc_has_pending_flip(crtc)) {
11678                 DRM_ERROR("pipe is still busy with an old pageflip\n");
11679                 return -EBUSY;
11680         }
11681
11682         if (old_obj != obj) {
11683                 mutex_lock(&dev->struct_mutex);
11684                 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11685                 if (ret == 0)
11686                         i915_gem_track_fb(old_obj, obj,
11687                                           INTEL_FRONTBUFFER_PRIMARY(pipe));
11688                 mutex_unlock(&dev->struct_mutex);
11689                 if (ret != 0) {
11690                         DRM_DEBUG_KMS("pin & fence failed\n");
11691                         return ret;
11692                 }
11693         }
11694
11695         return 0;
11696 }
11697
11698 static void
11699 intel_commit_primary_plane(struct drm_plane *plane,
11700                            struct intel_plane_state *state)
11701 {
11702         struct drm_crtc *crtc = state->crtc;
11703         struct drm_framebuffer *fb = state->fb;
11704         struct drm_device *dev = crtc->dev;
11705         struct drm_i915_private *dev_priv = dev->dev_private;
11706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11707         enum pipe pipe = intel_crtc->pipe;
11708         struct drm_framebuffer *old_fb = plane->fb;
11709         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11710         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11711         struct intel_plane *intel_plane = to_intel_plane(plane);
11712         struct drm_rect *src = &state->src;
11713
11714         crtc->primary->fb = fb;
11715         crtc->x = src->x1;
11716         crtc->y = src->y1;
11717
11718         intel_plane->crtc_x = state->orig_dst.x1;
11719         intel_plane->crtc_y = state->orig_dst.y1;
11720         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11721         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11722         intel_plane->src_x = state->orig_src.x1;
11723         intel_plane->src_y = state->orig_src.y1;
11724         intel_plane->src_w = drm_rect_width(&state->orig_src);
11725         intel_plane->src_h = drm_rect_height(&state->orig_src);
11726         intel_plane->obj = obj;
11727
11728         if (intel_crtc->active) {
11729                 /*
11730                  * FBC does not work on some platforms for rotated
11731                  * planes, so disable it when rotation is not 0 and
11732                  * update it when rotation is set back to 0.
11733                  *
11734                  * FIXME: This is redundant with the fbc update done in
11735                  * the primary plane enable function except that that
11736                  * one is done too late. We eventually need to unify
11737                  * this.
11738                  */
11739                 if (intel_crtc->primary_enabled &&
11740                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11741                     dev_priv->fbc.plane == intel_crtc->plane &&
11742                     intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11743                         intel_disable_fbc(dev);
11744                 }
11745
11746                 if (state->visible) {
11747                         bool was_enabled = intel_crtc->primary_enabled;
11748
11749                         /* FIXME: kill this fastboot hack */
11750                         intel_update_pipe_size(intel_crtc);
11751
11752                         intel_crtc->primary_enabled = true;
11753
11754                         dev_priv->display.update_primary_plane(crtc, plane->fb,
11755                                         crtc->x, crtc->y);
11756
11757                         /*
11758                          * BDW signals flip done immediately if the plane
11759                          * is disabled, even if the plane enable is already
11760                          * armed to occur at the next vblank :(
11761                          */
11762                         if (IS_BROADWELL(dev) && !was_enabled)
11763                                 intel_wait_for_vblank(dev, intel_crtc->pipe);
11764                 } else {
11765                         /*
11766                          * If clipping results in a non-visible primary plane,
11767                          * we'll disable the primary plane.  Note that this is
11768                          * a bit different than what happens if userspace
11769                          * explicitly disables the plane by passing fb=0
11770                          * because plane->fb still gets set and pinned.
11771                          */
11772                         intel_disable_primary_hw_plane(plane, crtc);
11773                 }
11774
11775                 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11776
11777                 mutex_lock(&dev->struct_mutex);
11778                 intel_update_fbc(dev);
11779                 mutex_unlock(&dev->struct_mutex);
11780         }
11781
11782         if (old_fb && old_fb != fb) {
11783                 if (intel_crtc->active)
11784                         intel_wait_for_vblank(dev, intel_crtc->pipe);
11785
11786                 mutex_lock(&dev->struct_mutex);
11787                 intel_unpin_fb_obj(old_obj);
11788                 mutex_unlock(&dev->struct_mutex);
11789         }
11790 }
11791
11792 static int
11793 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11794                              struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11795                              unsigned int crtc_w, unsigned int crtc_h,
11796                              uint32_t src_x, uint32_t src_y,
11797                              uint32_t src_w, uint32_t src_h)
11798 {
11799         struct intel_plane_state state;
11800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11801         int ret;
11802
11803         state.crtc = crtc;
11804         state.fb = fb;
11805
11806         /* sample coordinates in 16.16 fixed point */
11807         state.src.x1 = src_x;
11808         state.src.x2 = src_x + src_w;
11809         state.src.y1 = src_y;
11810         state.src.y2 = src_y + src_h;
11811
11812         /* integer pixels */
11813         state.dst.x1 = crtc_x;
11814         state.dst.x2 = crtc_x + crtc_w;
11815         state.dst.y1 = crtc_y;
11816         state.dst.y2 = crtc_y + crtc_h;
11817
11818         state.clip.x1 = 0;
11819         state.clip.y1 = 0;
11820         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11821         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11822
11823         state.orig_src = state.src;
11824         state.orig_dst = state.dst;
11825
11826         ret = intel_check_primary_plane(plane, &state);
11827         if (ret)
11828                 return ret;
11829
11830         ret = intel_prepare_primary_plane(plane, &state);
11831         if (ret)
11832                 return ret;
11833
11834         intel_commit_primary_plane(plane, &state);
11835
11836         return 0;
11837 }
11838
11839 /* Common destruction function for both primary and cursor planes */
11840 static void intel_plane_destroy(struct drm_plane *plane)
11841 {
11842         struct intel_plane *intel_plane = to_intel_plane(plane);
11843         drm_plane_cleanup(plane);
11844         kfree(intel_plane);
11845 }
11846
11847 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11848         .update_plane = intel_primary_plane_setplane,
11849         .disable_plane = intel_primary_plane_disable,
11850         .destroy = intel_plane_destroy,
11851         .set_property = intel_plane_set_property
11852 };
11853
11854 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11855                                                     int pipe)
11856 {
11857         struct intel_plane *primary;
11858         const uint32_t *intel_primary_formats;
11859         int num_formats;
11860
11861         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11862         if (primary == NULL)
11863                 return NULL;
11864
11865         primary->can_scale = false;
11866         primary->max_downscale = 1;
11867         primary->pipe = pipe;
11868         primary->plane = pipe;
11869         primary->rotation = BIT(DRM_ROTATE_0);
11870         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11871                 primary->plane = !pipe;
11872
11873         if (INTEL_INFO(dev)->gen <= 3) {
11874                 intel_primary_formats = intel_primary_formats_gen2;
11875                 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11876         } else {
11877                 intel_primary_formats = intel_primary_formats_gen4;
11878                 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11879         }
11880
11881         drm_universal_plane_init(dev, &primary->base, 0,
11882                                  &intel_primary_plane_funcs,
11883                                  intel_primary_formats, num_formats,
11884                                  DRM_PLANE_TYPE_PRIMARY);
11885
11886         if (INTEL_INFO(dev)->gen >= 4) {
11887                 if (!dev->mode_config.rotation_property)
11888                         dev->mode_config.rotation_property =
11889                                 drm_mode_create_rotation_property(dev,
11890                                                         BIT(DRM_ROTATE_0) |
11891                                                         BIT(DRM_ROTATE_180));
11892                 if (dev->mode_config.rotation_property)
11893                         drm_object_attach_property(&primary->base.base,
11894                                 dev->mode_config.rotation_property,
11895                                 primary->rotation);
11896         }
11897
11898         return &primary->base;
11899 }
11900
11901 static int
11902 intel_cursor_plane_disable(struct drm_plane *plane)
11903 {
11904         if (!plane->fb)
11905                 return 0;
11906
11907         BUG_ON(!plane->crtc);
11908
11909         return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11910 }
11911
11912 static int
11913 intel_check_cursor_plane(struct drm_plane *plane,
11914                          struct intel_plane_state *state)
11915 {
11916         struct drm_crtc *crtc = state->crtc;
11917         struct drm_device *dev = crtc->dev;
11918         struct drm_framebuffer *fb = state->fb;
11919         struct drm_rect *dest = &state->dst;
11920         struct drm_rect *src = &state->src;
11921         const struct drm_rect *clip = &state->clip;
11922         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11923         int crtc_w, crtc_h;
11924         unsigned stride;
11925         int ret;
11926
11927         ret = drm_plane_helper_check_update(plane, crtc, fb,
11928                                             src, dest, clip,
11929                                             DRM_PLANE_HELPER_NO_SCALING,
11930                                             DRM_PLANE_HELPER_NO_SCALING,
11931                                             true, true, &state->visible);
11932         if (ret)
11933                 return ret;
11934
11935
11936         /* if we want to turn off the cursor ignore width and height */
11937         if (!obj)
11938                 return 0;
11939
11940         /* Check for which cursor types we support */
11941         crtc_w = drm_rect_width(&state->orig_dst);
11942         crtc_h = drm_rect_height(&state->orig_dst);
11943         if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11944                 DRM_DEBUG("Cursor dimension not supported\n");
11945                 return -EINVAL;
11946         }
11947
11948         stride = roundup_pow_of_two(crtc_w) * 4;
11949         if (obj->base.size < stride * crtc_h) {
11950                 DRM_DEBUG_KMS("buffer is too small\n");
11951                 return -ENOMEM;
11952         }
11953
11954         if (fb == crtc->cursor->fb)
11955                 return 0;
11956
11957         /* we only need to pin inside GTT if cursor is non-phy */
11958         mutex_lock(&dev->struct_mutex);
11959         if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11960                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11961                 ret = -EINVAL;
11962         }
11963         mutex_unlock(&dev->struct_mutex);
11964
11965         return ret;
11966 }
11967
11968 static int
11969 intel_commit_cursor_plane(struct drm_plane *plane,
11970                           struct intel_plane_state *state)
11971 {
11972         struct drm_crtc *crtc = state->crtc;
11973         struct drm_framebuffer *fb = state->fb;
11974         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11975         struct intel_plane *intel_plane = to_intel_plane(plane);
11976         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11977         struct drm_i915_gem_object *obj = intel_fb->obj;
11978         int crtc_w, crtc_h;
11979
11980         crtc->cursor_x = state->orig_dst.x1;
11981         crtc->cursor_y = state->orig_dst.y1;
11982
11983         intel_plane->crtc_x = state->orig_dst.x1;
11984         intel_plane->crtc_y = state->orig_dst.y1;
11985         intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11986         intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11987         intel_plane->src_x = state->orig_src.x1;
11988         intel_plane->src_y = state->orig_src.y1;
11989         intel_plane->src_w = drm_rect_width(&state->orig_src);
11990         intel_plane->src_h = drm_rect_height(&state->orig_src);
11991         intel_plane->obj = obj;
11992
11993         if (fb != crtc->cursor->fb) {
11994                 crtc_w = drm_rect_width(&state->orig_dst);
11995                 crtc_h = drm_rect_height(&state->orig_dst);
11996                 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11997         } else {
11998                 intel_crtc_update_cursor(crtc, state->visible);
11999
12000                 intel_frontbuffer_flip(crtc->dev,
12001                                        INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12002
12003                 return 0;
12004         }
12005 }
12006
12007 static int
12008 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12009                           struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12010                           unsigned int crtc_w, unsigned int crtc_h,
12011                           uint32_t src_x, uint32_t src_y,
12012                           uint32_t src_w, uint32_t src_h)
12013 {
12014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12015         struct intel_plane_state state;
12016         int ret;
12017
12018         state.crtc = crtc;
12019         state.fb = fb;
12020
12021         /* sample coordinates in 16.16 fixed point */
12022         state.src.x1 = src_x;
12023         state.src.x2 = src_x + src_w;
12024         state.src.y1 = src_y;
12025         state.src.y2 = src_y + src_h;
12026
12027         /* integer pixels */
12028         state.dst.x1 = crtc_x;
12029         state.dst.x2 = crtc_x + crtc_w;
12030         state.dst.y1 = crtc_y;
12031         state.dst.y2 = crtc_y + crtc_h;
12032
12033         state.clip.x1 = 0;
12034         state.clip.y1 = 0;
12035         state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12036         state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12037
12038         state.orig_src = state.src;
12039         state.orig_dst = state.dst;
12040
12041         ret = intel_check_cursor_plane(plane, &state);
12042         if (ret)
12043                 return ret;
12044
12045         return intel_commit_cursor_plane(plane, &state);
12046 }
12047
12048 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12049         .update_plane = intel_cursor_plane_update,
12050         .disable_plane = intel_cursor_plane_disable,
12051         .destroy = intel_plane_destroy,
12052         .set_property = intel_plane_set_property,
12053 };
12054
12055 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12056                                                    int pipe)
12057 {
12058         struct intel_plane *cursor;
12059
12060         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12061         if (cursor == NULL)
12062                 return NULL;
12063
12064         cursor->can_scale = false;
12065         cursor->max_downscale = 1;
12066         cursor->pipe = pipe;
12067         cursor->plane = pipe;
12068         cursor->rotation = BIT(DRM_ROTATE_0);
12069
12070         drm_universal_plane_init(dev, &cursor->base, 0,
12071                                  &intel_cursor_plane_funcs,
12072                                  intel_cursor_formats,
12073                                  ARRAY_SIZE(intel_cursor_formats),
12074                                  DRM_PLANE_TYPE_CURSOR);
12075
12076         if (INTEL_INFO(dev)->gen >= 4) {
12077                 if (!dev->mode_config.rotation_property)
12078                         dev->mode_config.rotation_property =
12079                                 drm_mode_create_rotation_property(dev,
12080                                                         BIT(DRM_ROTATE_0) |
12081                                                         BIT(DRM_ROTATE_180));
12082                 if (dev->mode_config.rotation_property)
12083                         drm_object_attach_property(&cursor->base.base,
12084                                 dev->mode_config.rotation_property,
12085                                 cursor->rotation);
12086         }
12087
12088         return &cursor->base;
12089 }
12090
12091 static void intel_crtc_init(struct drm_device *dev, int pipe)
12092 {
12093         struct drm_i915_private *dev_priv = dev->dev_private;
12094         struct intel_crtc *intel_crtc;
12095         struct drm_plane *primary = NULL;
12096         struct drm_plane *cursor = NULL;
12097         int i, ret;
12098
12099         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12100         if (intel_crtc == NULL)
12101                 return;
12102
12103         primary = intel_primary_plane_create(dev, pipe);
12104         if (!primary)
12105                 goto fail;
12106
12107         cursor = intel_cursor_plane_create(dev, pipe);
12108         if (!cursor)
12109                 goto fail;
12110
12111         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12112                                         cursor, &intel_crtc_funcs);
12113         if (ret)
12114                 goto fail;
12115
12116         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12117         for (i = 0; i < 256; i++) {
12118                 intel_crtc->lut_r[i] = i;
12119                 intel_crtc->lut_g[i] = i;
12120                 intel_crtc->lut_b[i] = i;
12121         }
12122
12123         /*
12124          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12125          * is hooked to pipe B. Hence we want plane A feeding pipe B.
12126          */
12127         intel_crtc->pipe = pipe;
12128         intel_crtc->plane = pipe;
12129         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12130                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12131                 intel_crtc->plane = !pipe;
12132         }
12133
12134         intel_crtc->cursor_base = ~0;
12135         intel_crtc->cursor_cntl = ~0;
12136         intel_crtc->cursor_size = ~0;
12137
12138         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12139                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12140         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12141         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12142
12143         INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12144
12145         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12146
12147         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12148         return;
12149
12150 fail:
12151         if (primary)
12152                 drm_plane_cleanup(primary);
12153         if (cursor)
12154                 drm_plane_cleanup(cursor);
12155         kfree(intel_crtc);
12156 }
12157
12158 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12159 {
12160         struct drm_encoder *encoder = connector->base.encoder;
12161         struct drm_device *dev = connector->base.dev;
12162
12163         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12164
12165         if (!encoder || WARN_ON(!encoder->crtc))
12166                 return INVALID_PIPE;
12167
12168         return to_intel_crtc(encoder->crtc)->pipe;
12169 }
12170
12171 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12172                                 struct drm_file *file)
12173 {
12174         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12175         struct drm_crtc *drmmode_crtc;
12176         struct intel_crtc *crtc;
12177
12178         if (!drm_core_check_feature(dev, DRIVER_MODESET))
12179                 return -ENODEV;
12180
12181         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12182
12183         if (!drmmode_crtc) {
12184                 DRM_ERROR("no such CRTC id\n");
12185                 return -ENOENT;
12186         }
12187
12188         crtc = to_intel_crtc(drmmode_crtc);
12189         pipe_from_crtc_id->pipe = crtc->pipe;
12190
12191         return 0;
12192 }
12193
12194 static int intel_encoder_clones(struct intel_encoder *encoder)
12195 {
12196         struct drm_device *dev = encoder->base.dev;
12197         struct intel_encoder *source_encoder;
12198         int index_mask = 0;
12199         int entry = 0;
12200
12201         for_each_intel_encoder(dev, source_encoder) {
12202                 if (encoders_cloneable(encoder, source_encoder))
12203                         index_mask |= (1 << entry);
12204
12205                 entry++;
12206         }
12207
12208         return index_mask;
12209 }
12210
12211 static bool has_edp_a(struct drm_device *dev)
12212 {
12213         struct drm_i915_private *dev_priv = dev->dev_private;
12214
12215         if (!IS_MOBILE(dev))
12216                 return false;
12217
12218         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12219                 return false;
12220
12221         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12222                 return false;
12223
12224         return true;
12225 }
12226
12227 const char *intel_output_name(int output)
12228 {
12229         static const char *names[] = {
12230                 [INTEL_OUTPUT_UNUSED] = "Unused",
12231                 [INTEL_OUTPUT_ANALOG] = "Analog",
12232                 [INTEL_OUTPUT_DVO] = "DVO",
12233                 [INTEL_OUTPUT_SDVO] = "SDVO",
12234                 [INTEL_OUTPUT_LVDS] = "LVDS",
12235                 [INTEL_OUTPUT_TVOUT] = "TV",
12236                 [INTEL_OUTPUT_HDMI] = "HDMI",
12237                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12238                 [INTEL_OUTPUT_EDP] = "eDP",
12239                 [INTEL_OUTPUT_DSI] = "DSI",
12240                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12241         };
12242
12243         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12244                 return "Invalid";
12245
12246         return names[output];
12247 }
12248
12249 static bool intel_crt_present(struct drm_device *dev)
12250 {
12251         struct drm_i915_private *dev_priv = dev->dev_private;
12252
12253         if (INTEL_INFO(dev)->gen >= 9)
12254                 return false;
12255
12256         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12257                 return false;
12258
12259         if (IS_CHERRYVIEW(dev))
12260                 return false;
12261
12262         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12263                 return false;
12264
12265         return true;
12266 }
12267
12268 static void intel_setup_outputs(struct drm_device *dev)
12269 {
12270         struct drm_i915_private *dev_priv = dev->dev_private;
12271         struct intel_encoder *encoder;
12272         bool dpd_is_edp = false;
12273
12274         intel_lvds_init(dev);
12275
12276         if (intel_crt_present(dev))
12277                 intel_crt_init(dev);
12278
12279         if (HAS_DDI(dev)) {
12280                 int found;
12281
12282                 /* Haswell uses DDI functions to detect digital outputs */
12283                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12284                 /* DDI A only supports eDP */
12285                 if (found)
12286                         intel_ddi_init(dev, PORT_A);
12287
12288                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12289                  * register */
12290                 found = I915_READ(SFUSE_STRAP);
12291
12292                 if (found & SFUSE_STRAP_DDIB_DETECTED)
12293                         intel_ddi_init(dev, PORT_B);
12294                 if (found & SFUSE_STRAP_DDIC_DETECTED)
12295                         intel_ddi_init(dev, PORT_C);
12296                 if (found & SFUSE_STRAP_DDID_DETECTED)
12297                         intel_ddi_init(dev, PORT_D);
12298         } else if (HAS_PCH_SPLIT(dev)) {
12299                 int found;
12300                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12301
12302                 if (has_edp_a(dev))
12303                         intel_dp_init(dev, DP_A, PORT_A);
12304
12305                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12306                         /* PCH SDVOB multiplex with HDMIB */
12307                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
12308                         if (!found)
12309                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12310                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12311                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
12312                 }
12313
12314                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12315                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12316
12317                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12318                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12319
12320                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12321                         intel_dp_init(dev, PCH_DP_C, PORT_C);
12322
12323                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12324                         intel_dp_init(dev, PCH_DP_D, PORT_D);
12325         } else if (IS_VALLEYVIEW(dev)) {
12326                 /*
12327                  * The DP_DETECTED bit is the latched state of the DDC
12328                  * SDA pin at boot. However since eDP doesn't require DDC
12329                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
12330                  * eDP ports may have been muxed to an alternate function.
12331                  * Thus we can't rely on the DP_DETECTED bit alone to detect
12332                  * eDP ports. Consult the VBT as well as DP_DETECTED to
12333                  * detect eDP ports.
12334                  */
12335                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12336                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12337                                         PORT_B);
12338                 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12339                     intel_dp_is_edp(dev, PORT_B))
12340                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12341
12342                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12343                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12344                                         PORT_C);
12345                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12346                     intel_dp_is_edp(dev, PORT_C))
12347                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12348
12349                 if (IS_CHERRYVIEW(dev)) {
12350                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12351                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12352                                                 PORT_D);
12353                         /* eDP not supported on port D, so don't check VBT */
12354                         if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12355                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12356                 }
12357
12358                 intel_dsi_init(dev);
12359         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12360                 bool found = false;
12361
12362                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12363                         DRM_DEBUG_KMS("probing SDVOB\n");
12364                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12365                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12366                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12367                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12368                         }
12369
12370                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
12371                                 intel_dp_init(dev, DP_B, PORT_B);
12372                 }
12373
12374                 /* Before G4X SDVOC doesn't have its own detect register */
12375
12376                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12377                         DRM_DEBUG_KMS("probing SDVOC\n");
12378                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12379                 }
12380
12381                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12382
12383                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12384                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12385                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12386                         }
12387                         if (SUPPORTS_INTEGRATED_DP(dev))
12388                                 intel_dp_init(dev, DP_C, PORT_C);
12389                 }
12390
12391                 if (SUPPORTS_INTEGRATED_DP(dev) &&
12392                     (I915_READ(DP_D) & DP_DETECTED))
12393                         intel_dp_init(dev, DP_D, PORT_D);
12394         } else if (IS_GEN2(dev))
12395                 intel_dvo_init(dev);
12396
12397         if (SUPPORTS_TV(dev))
12398                 intel_tv_init(dev);
12399
12400         intel_edp_psr_init(dev);
12401
12402         for_each_intel_encoder(dev, encoder) {
12403                 encoder->base.possible_crtcs = encoder->crtc_mask;
12404                 encoder->base.possible_clones =
12405                         intel_encoder_clones(encoder);
12406         }
12407
12408         intel_init_pch_refclk(dev);
12409
12410         drm_helper_move_panel_connectors_to_head(dev);
12411 }
12412
12413 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12414 {
12415         struct drm_device *dev = fb->dev;
12416         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12417
12418         drm_framebuffer_cleanup(fb);
12419         mutex_lock(&dev->struct_mutex);
12420         WARN_ON(!intel_fb->obj->framebuffer_references--);
12421         drm_gem_object_unreference(&intel_fb->obj->base);
12422         mutex_unlock(&dev->struct_mutex);
12423         kfree(intel_fb);
12424 }
12425
12426 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12427                                                 struct drm_file *file,
12428                                                 unsigned int *handle)
12429 {
12430         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12431         struct drm_i915_gem_object *obj = intel_fb->obj;
12432
12433         return drm_gem_handle_create(file, &obj->base, handle);
12434 }
12435
12436 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12437         .destroy = intel_user_framebuffer_destroy,
12438         .create_handle = intel_user_framebuffer_create_handle,
12439 };
12440
12441 static int intel_framebuffer_init(struct drm_device *dev,
12442                                   struct intel_framebuffer *intel_fb,
12443                                   struct drm_mode_fb_cmd2 *mode_cmd,
12444                                   struct drm_i915_gem_object *obj)
12445 {
12446         int aligned_height;
12447         int pitch_limit;
12448         int ret;
12449
12450         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12451
12452         if (obj->tiling_mode == I915_TILING_Y) {
12453                 DRM_DEBUG("hardware does not support tiling Y\n");
12454                 return -EINVAL;
12455         }
12456
12457         if (mode_cmd->pitches[0] & 63) {
12458                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12459                           mode_cmd->pitches[0]);
12460                 return -EINVAL;
12461         }
12462
12463         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12464                 pitch_limit = 32*1024;
12465         } else if (INTEL_INFO(dev)->gen >= 4) {
12466                 if (obj->tiling_mode)
12467                         pitch_limit = 16*1024;
12468                 else
12469                         pitch_limit = 32*1024;
12470         } else if (INTEL_INFO(dev)->gen >= 3) {
12471                 if (obj->tiling_mode)
12472                         pitch_limit = 8*1024;
12473                 else
12474                         pitch_limit = 16*1024;
12475         } else
12476                 /* XXX DSPC is limited to 4k tiled */
12477                 pitch_limit = 8*1024;
12478
12479         if (mode_cmd->pitches[0] > pitch_limit) {
12480                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12481                           obj->tiling_mode ? "tiled" : "linear",
12482                           mode_cmd->pitches[0], pitch_limit);
12483                 return -EINVAL;
12484         }
12485
12486         if (obj->tiling_mode != I915_TILING_NONE &&
12487             mode_cmd->pitches[0] != obj->stride) {
12488                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12489                           mode_cmd->pitches[0], obj->stride);
12490                 return -EINVAL;
12491         }
12492
12493         /* Reject formats not supported by any plane early. */
12494         switch (mode_cmd->pixel_format) {
12495         case DRM_FORMAT_C8:
12496         case DRM_FORMAT_RGB565:
12497         case DRM_FORMAT_XRGB8888:
12498         case DRM_FORMAT_ARGB8888:
12499                 break;
12500         case DRM_FORMAT_XRGB1555:
12501         case DRM_FORMAT_ARGB1555:
12502                 if (INTEL_INFO(dev)->gen > 3) {
12503                         DRM_DEBUG("unsupported pixel format: %s\n",
12504                                   drm_get_format_name(mode_cmd->pixel_format));
12505                         return -EINVAL;
12506                 }
12507                 break;
12508         case DRM_FORMAT_XBGR8888:
12509         case DRM_FORMAT_ABGR8888:
12510         case DRM_FORMAT_XRGB2101010:
12511         case DRM_FORMAT_ARGB2101010:
12512         case DRM_FORMAT_XBGR2101010:
12513         case DRM_FORMAT_ABGR2101010:
12514                 if (INTEL_INFO(dev)->gen < 4) {
12515                         DRM_DEBUG("unsupported pixel format: %s\n",
12516                                   drm_get_format_name(mode_cmd->pixel_format));
12517                         return -EINVAL;
12518                 }
12519                 break;
12520         case DRM_FORMAT_YUYV:
12521         case DRM_FORMAT_UYVY:
12522         case DRM_FORMAT_YVYU:
12523         case DRM_FORMAT_VYUY:
12524                 if (INTEL_INFO(dev)->gen < 5) {
12525                         DRM_DEBUG("unsupported pixel format: %s\n",
12526                                   drm_get_format_name(mode_cmd->pixel_format));
12527                         return -EINVAL;
12528                 }
12529                 break;
12530         default:
12531                 DRM_DEBUG("unsupported pixel format: %s\n",
12532                           drm_get_format_name(mode_cmd->pixel_format));
12533                 return -EINVAL;
12534         }
12535
12536         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12537         if (mode_cmd->offsets[0] != 0)
12538                 return -EINVAL;
12539
12540         aligned_height = intel_align_height(dev, mode_cmd->height,
12541                                             obj->tiling_mode);
12542         /* FIXME drm helper for size checks (especially planar formats)? */
12543         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12544                 return -EINVAL;
12545
12546         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12547         intel_fb->obj = obj;
12548         intel_fb->obj->framebuffer_references++;
12549
12550         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12551         if (ret) {
12552                 DRM_ERROR("framebuffer init failed %d\n", ret);
12553                 return ret;
12554         }
12555
12556         return 0;
12557 }
12558
12559 static struct drm_framebuffer *
12560 intel_user_framebuffer_create(struct drm_device *dev,
12561                               struct drm_file *filp,
12562                               struct drm_mode_fb_cmd2 *mode_cmd)
12563 {
12564         struct drm_i915_gem_object *obj;
12565
12566         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12567                                                 mode_cmd->handles[0]));
12568         if (&obj->base == NULL)
12569                 return ERR_PTR(-ENOENT);
12570
12571         return intel_framebuffer_create(dev, mode_cmd, obj);
12572 }
12573
12574 #ifndef CONFIG_DRM_I915_FBDEV
12575 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12576 {
12577 }
12578 #endif
12579
12580 static const struct drm_mode_config_funcs intel_mode_funcs = {
12581         .fb_create = intel_user_framebuffer_create,
12582         .output_poll_changed = intel_fbdev_output_poll_changed,
12583 };
12584
12585 /* Set up chip specific display functions */
12586 static void intel_init_display(struct drm_device *dev)
12587 {
12588         struct drm_i915_private *dev_priv = dev->dev_private;
12589
12590         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12591                 dev_priv->display.find_dpll = g4x_find_best_dpll;
12592         else if (IS_CHERRYVIEW(dev))
12593                 dev_priv->display.find_dpll = chv_find_best_dpll;
12594         else if (IS_VALLEYVIEW(dev))
12595                 dev_priv->display.find_dpll = vlv_find_best_dpll;
12596         else if (IS_PINEVIEW(dev))
12597                 dev_priv->display.find_dpll = pnv_find_best_dpll;
12598         else
12599                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12600
12601         if (HAS_DDI(dev)) {
12602                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12603                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12604                 dev_priv->display.crtc_compute_clock =
12605                         haswell_crtc_compute_clock;
12606                 dev_priv->display.crtc_enable = haswell_crtc_enable;
12607                 dev_priv->display.crtc_disable = haswell_crtc_disable;
12608                 dev_priv->display.off = ironlake_crtc_off;
12609                 if (INTEL_INFO(dev)->gen >= 9)
12610                         dev_priv->display.update_primary_plane =
12611                                 skylake_update_primary_plane;
12612                 else
12613                         dev_priv->display.update_primary_plane =
12614                                 ironlake_update_primary_plane;
12615         } else if (HAS_PCH_SPLIT(dev)) {
12616                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12617                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12618                 dev_priv->display.crtc_compute_clock =
12619                         ironlake_crtc_compute_clock;
12620                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12621                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12622                 dev_priv->display.off = ironlake_crtc_off;
12623                 dev_priv->display.update_primary_plane =
12624                         ironlake_update_primary_plane;
12625         } else if (IS_VALLEYVIEW(dev)) {
12626                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12627                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12628                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12629                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12630                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12631                 dev_priv->display.off = i9xx_crtc_off;
12632                 dev_priv->display.update_primary_plane =
12633                         i9xx_update_primary_plane;
12634         } else {
12635                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12636                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12637                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12638                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12639                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12640                 dev_priv->display.off = i9xx_crtc_off;
12641                 dev_priv->display.update_primary_plane =
12642                         i9xx_update_primary_plane;
12643         }
12644
12645         /* Returns the core display clock speed */
12646         if (IS_VALLEYVIEW(dev))
12647                 dev_priv->display.get_display_clock_speed =
12648                         valleyview_get_display_clock_speed;
12649         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12650                 dev_priv->display.get_display_clock_speed =
12651                         i945_get_display_clock_speed;
12652         else if (IS_I915G(dev))
12653                 dev_priv->display.get_display_clock_speed =
12654                         i915_get_display_clock_speed;
12655         else if (IS_I945GM(dev) || IS_845G(dev))
12656                 dev_priv->display.get_display_clock_speed =
12657                         i9xx_misc_get_display_clock_speed;
12658         else if (IS_PINEVIEW(dev))
12659                 dev_priv->display.get_display_clock_speed =
12660                         pnv_get_display_clock_speed;
12661         else if (IS_I915GM(dev))
12662                 dev_priv->display.get_display_clock_speed =
12663                         i915gm_get_display_clock_speed;
12664         else if (IS_I865G(dev))
12665                 dev_priv->display.get_display_clock_speed =
12666                         i865_get_display_clock_speed;
12667         else if (IS_I85X(dev))
12668                 dev_priv->display.get_display_clock_speed =
12669                         i855_get_display_clock_speed;
12670         else /* 852, 830 */
12671                 dev_priv->display.get_display_clock_speed =
12672                         i830_get_display_clock_speed;
12673
12674         if (IS_GEN5(dev)) {
12675                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12676         } else if (IS_GEN6(dev)) {
12677                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12678         } else if (IS_IVYBRIDGE(dev)) {
12679                 /* FIXME: detect B0+ stepping and use auto training */
12680                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12681                 dev_priv->display.modeset_global_resources =
12682                         ivb_modeset_global_resources;
12683         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12684                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12685         } else if (IS_VALLEYVIEW(dev)) {
12686                 dev_priv->display.modeset_global_resources =
12687                         valleyview_modeset_global_resources;
12688         }
12689
12690         /* Default just returns -ENODEV to indicate unsupported */
12691         dev_priv->display.queue_flip = intel_default_queue_flip;
12692
12693         switch (INTEL_INFO(dev)->gen) {
12694         case 2:
12695                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12696                 break;
12697
12698         case 3:
12699                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12700                 break;
12701
12702         case 4:
12703         case 5:
12704                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12705                 break;
12706
12707         case 6:
12708                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12709                 break;
12710         case 7:
12711         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12712                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12713                 break;
12714         case 9:
12715                 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12716                 break;
12717         }
12718
12719         intel_panel_init_backlight_funcs(dev);
12720
12721         mutex_init(&dev_priv->pps_mutex);
12722 }
12723
12724 /*
12725  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12726  * resume, or other times.  This quirk makes sure that's the case for
12727  * affected systems.
12728  */
12729 static void quirk_pipea_force(struct drm_device *dev)
12730 {
12731         struct drm_i915_private *dev_priv = dev->dev_private;
12732
12733         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12734         DRM_INFO("applying pipe a force quirk\n");
12735 }
12736
12737 static void quirk_pipeb_force(struct drm_device *dev)
12738 {
12739         struct drm_i915_private *dev_priv = dev->dev_private;
12740
12741         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12742         DRM_INFO("applying pipe b force quirk\n");
12743 }
12744
12745 /*
12746  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12747  */
12748 static void quirk_ssc_force_disable(struct drm_device *dev)
12749 {
12750         struct drm_i915_private *dev_priv = dev->dev_private;
12751         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12752         DRM_INFO("applying lvds SSC disable quirk\n");
12753 }
12754
12755 /*
12756  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12757  * brightness value
12758  */
12759 static void quirk_invert_brightness(struct drm_device *dev)
12760 {
12761         struct drm_i915_private *dev_priv = dev->dev_private;
12762         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12763         DRM_INFO("applying inverted panel brightness quirk\n");
12764 }
12765
12766 /* Some VBT's incorrectly indicate no backlight is present */
12767 static void quirk_backlight_present(struct drm_device *dev)
12768 {
12769         struct drm_i915_private *dev_priv = dev->dev_private;
12770         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12771         DRM_INFO("applying backlight present quirk\n");
12772 }
12773
12774 struct intel_quirk {
12775         int device;
12776         int subsystem_vendor;
12777         int subsystem_device;
12778         void (*hook)(struct drm_device *dev);
12779 };
12780
12781 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12782 struct intel_dmi_quirk {
12783         void (*hook)(struct drm_device *dev);
12784         const struct dmi_system_id (*dmi_id_list)[];
12785 };
12786
12787 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12788 {
12789         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12790         return 1;
12791 }
12792
12793 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12794         {
12795                 .dmi_id_list = &(const struct dmi_system_id[]) {
12796                         {
12797                                 .callback = intel_dmi_reverse_brightness,
12798                                 .ident = "NCR Corporation",
12799                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12800                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
12801                                 },
12802                         },
12803                         { }  /* terminating entry */
12804                 },
12805                 .hook = quirk_invert_brightness,
12806         },
12807 };
12808
12809 static struct intel_quirk intel_quirks[] = {
12810         /* HP Mini needs pipe A force quirk (LP: #322104) */
12811         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12812
12813         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12814         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12815
12816         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12817         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12818
12819         /* 830 needs to leave pipe A & dpll A up */
12820         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12821
12822         /* 830 needs to leave pipe B & dpll B up */
12823         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12824
12825         /* Lenovo U160 cannot use SSC on LVDS */
12826         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12827
12828         /* Sony Vaio Y cannot use SSC on LVDS */
12829         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12830
12831         /* Acer Aspire 5734Z must invert backlight brightness */
12832         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12833
12834         /* Acer/eMachines G725 */
12835         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12836
12837         /* Acer/eMachines e725 */
12838         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12839
12840         /* Acer/Packard Bell NCL20 */
12841         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12842
12843         /* Acer Aspire 4736Z */
12844         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12845
12846         /* Acer Aspire 5336 */
12847         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12848
12849         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12850         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12851
12852         /* Acer C720 Chromebook (Core i3 4005U) */
12853         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12854
12855         /* Toshiba CB35 Chromebook (Celeron 2955U) */
12856         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12857
12858         /* HP Chromebook 14 (Celeron 2955U) */
12859         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12860 };
12861
12862 static void intel_init_quirks(struct drm_device *dev)
12863 {
12864         struct pci_dev *d = dev->pdev;
12865         int i;
12866
12867         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12868                 struct intel_quirk *q = &intel_quirks[i];
12869
12870                 if (d->device == q->device &&
12871                     (d->subsystem_vendor == q->subsystem_vendor ||
12872                      q->subsystem_vendor == PCI_ANY_ID) &&
12873                     (d->subsystem_device == q->subsystem_device ||
12874                      q->subsystem_device == PCI_ANY_ID))
12875                         q->hook(dev);
12876         }
12877         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12878                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12879                         intel_dmi_quirks[i].hook(dev);
12880         }
12881 }
12882
12883 /* Disable the VGA plane that we never use */
12884 static void i915_disable_vga(struct drm_device *dev)
12885 {
12886         struct drm_i915_private *dev_priv = dev->dev_private;
12887         u8 sr1;
12888         u32 vga_reg = i915_vgacntrl_reg(dev);
12889
12890         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12891         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12892         outb(SR01, VGA_SR_INDEX);
12893         sr1 = inb(VGA_SR_DATA);
12894         outb(sr1 | 1<<5, VGA_SR_DATA);
12895         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12896         udelay(300);
12897
12898         /*
12899          * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12900          * from S3 without preserving (some of?) the other bits.
12901          */
12902         I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12903         POSTING_READ(vga_reg);
12904 }
12905
12906 void intel_modeset_init_hw(struct drm_device *dev)
12907 {
12908         intel_prepare_ddi(dev);
12909
12910         if (IS_VALLEYVIEW(dev))
12911                 vlv_update_cdclk(dev);
12912
12913         intel_init_clock_gating(dev);
12914
12915         intel_enable_gt_powersave(dev);
12916 }
12917
12918 void intel_modeset_init(struct drm_device *dev)
12919 {
12920         struct drm_i915_private *dev_priv = dev->dev_private;
12921         int sprite, ret;
12922         enum pipe pipe;
12923         struct intel_crtc *crtc;
12924
12925         drm_mode_config_init(dev);
12926
12927         dev->mode_config.min_width = 0;
12928         dev->mode_config.min_height = 0;
12929
12930         dev->mode_config.preferred_depth = 24;
12931         dev->mode_config.prefer_shadow = 1;
12932
12933         dev->mode_config.funcs = &intel_mode_funcs;
12934
12935         intel_init_quirks(dev);
12936
12937         intel_init_pm(dev);
12938
12939         if (INTEL_INFO(dev)->num_pipes == 0)
12940                 return;
12941
12942         intel_init_display(dev);
12943         intel_init_audio(dev);
12944
12945         if (IS_GEN2(dev)) {
12946                 dev->mode_config.max_width = 2048;
12947                 dev->mode_config.max_height = 2048;
12948         } else if (IS_GEN3(dev)) {
12949                 dev->mode_config.max_width = 4096;
12950                 dev->mode_config.max_height = 4096;
12951         } else {
12952                 dev->mode_config.max_width = 8192;
12953                 dev->mode_config.max_height = 8192;
12954         }
12955
12956         if (IS_845G(dev) || IS_I865G(dev)) {
12957                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12958                 dev->mode_config.cursor_height = 1023;
12959         } else if (IS_GEN2(dev)) {
12960                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12961                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12962         } else {
12963                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12964                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12965         }
12966
12967         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12968
12969         DRM_DEBUG_KMS("%d display pipe%s available.\n",
12970                       INTEL_INFO(dev)->num_pipes,
12971                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12972
12973         for_each_pipe(dev_priv, pipe) {
12974                 intel_crtc_init(dev, pipe);
12975                 for_each_sprite(pipe, sprite) {
12976                         ret = intel_plane_init(dev, pipe, sprite);
12977                         if (ret)
12978                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12979                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
12980                 }
12981         }
12982
12983         intel_init_dpio(dev);
12984
12985         intel_shared_dpll_init(dev);
12986
12987         /* save the BIOS value before clobbering it */
12988         dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12989         /* Just disable it once at startup */
12990         i915_disable_vga(dev);
12991         intel_setup_outputs(dev);
12992
12993         /* Just in case the BIOS is doing something questionable. */
12994         intel_disable_fbc(dev);
12995
12996         drm_modeset_lock_all(dev);
12997         intel_modeset_setup_hw_state(dev, false);
12998         drm_modeset_unlock_all(dev);
12999
13000         for_each_intel_crtc(dev, crtc) {
13001                 if (!crtc->active)
13002                         continue;
13003
13004                 /*
13005                  * Note that reserving the BIOS fb up front prevents us
13006                  * from stuffing other stolen allocations like the ring
13007                  * on top.  This prevents some ugliness at boot time, and
13008                  * can even allow for smooth boot transitions if the BIOS
13009                  * fb is large enough for the active pipe configuration.
13010                  */
13011                 if (dev_priv->display.get_plane_config) {
13012                         dev_priv->display.get_plane_config(crtc,
13013                                                            &crtc->plane_config);
13014                         /*
13015                          * If the fb is shared between multiple heads, we'll
13016                          * just get the first one.
13017                          */
13018                         intel_find_plane_obj(crtc, &crtc->plane_config);
13019                 }
13020         }
13021 }
13022
13023 static void intel_enable_pipe_a(struct drm_device *dev)
13024 {
13025         struct intel_connector *connector;
13026         struct drm_connector *crt = NULL;
13027         struct intel_load_detect_pipe load_detect_temp;
13028         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13029
13030         /* We can't just switch on the pipe A, we need to set things up with a
13031          * proper mode and output configuration. As a gross hack, enable pipe A
13032          * by enabling the load detect pipe once. */
13033         list_for_each_entry(connector,
13034                             &dev->mode_config.connector_list,
13035                             base.head) {
13036                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13037                         crt = &connector->base;
13038                         break;
13039                 }
13040         }
13041
13042         if (!crt)
13043                 return;
13044
13045         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13046                 intel_release_load_detect_pipe(crt, &load_detect_temp);
13047 }
13048
13049 static bool
13050 intel_check_plane_mapping(struct intel_crtc *crtc)
13051 {
13052         struct drm_device *dev = crtc->base.dev;
13053         struct drm_i915_private *dev_priv = dev->dev_private;
13054         u32 reg, val;
13055
13056         if (INTEL_INFO(dev)->num_pipes == 1)
13057                 return true;
13058
13059         reg = DSPCNTR(!crtc->plane);
13060         val = I915_READ(reg);
13061
13062         if ((val & DISPLAY_PLANE_ENABLE) &&
13063             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13064                 return false;
13065
13066         return true;
13067 }
13068
13069 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13070 {
13071         struct drm_device *dev = crtc->base.dev;
13072         struct drm_i915_private *dev_priv = dev->dev_private;
13073         u32 reg;
13074
13075         /* Clear any frame start delays used for debugging left by the BIOS */
13076         reg = PIPECONF(crtc->config.cpu_transcoder);
13077         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13078
13079         /* restore vblank interrupts to correct state */
13080         if (crtc->active) {
13081                 update_scanline_offset(crtc);
13082                 drm_vblank_on(dev, crtc->pipe);
13083         } else
13084                 drm_vblank_off(dev, crtc->pipe);
13085
13086         /* We need to sanitize the plane -> pipe mapping first because this will
13087          * disable the crtc (and hence change the state) if it is wrong. Note
13088          * that gen4+ has a fixed plane -> pipe mapping.  */
13089         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13090                 struct intel_connector *connector;
13091                 bool plane;
13092
13093                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13094                               crtc->base.base.id);
13095
13096                 /* Pipe has the wrong plane attached and the plane is active.
13097                  * Temporarily change the plane mapping and disable everything
13098                  * ...  */
13099                 plane = crtc->plane;
13100                 crtc->plane = !plane;
13101                 crtc->primary_enabled = true;
13102                 dev_priv->display.crtc_disable(&crtc->base);
13103                 crtc->plane = plane;
13104
13105                 /* ... and break all links. */
13106                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13107                                     base.head) {
13108                         if (connector->encoder->base.crtc != &crtc->base)
13109                                 continue;
13110
13111                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13112                         connector->base.encoder = NULL;
13113                 }
13114                 /* multiple connectors may have the same encoder:
13115                  *  handle them and break crtc link separately */
13116                 list_for_each_entry(connector, &dev->mode_config.connector_list,
13117                                     base.head)
13118                         if (connector->encoder->base.crtc == &crtc->base) {
13119                                 connector->encoder->base.crtc = NULL;
13120                                 connector->encoder->connectors_active = false;
13121                         }
13122
13123                 WARN_ON(crtc->active);
13124                 crtc->base.enabled = false;
13125         }
13126
13127         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13128             crtc->pipe == PIPE_A && !crtc->active) {
13129                 /* BIOS forgot to enable pipe A, this mostly happens after
13130                  * resume. Force-enable the pipe to fix this, the update_dpms
13131                  * call below we restore the pipe to the right state, but leave
13132                  * the required bits on. */
13133                 intel_enable_pipe_a(dev);
13134         }
13135
13136         /* Adjust the state of the output pipe according to whether we
13137          * have active connectors/encoders. */
13138         intel_crtc_update_dpms(&crtc->base);
13139
13140         if (crtc->active != crtc->base.enabled) {
13141                 struct intel_encoder *encoder;
13142
13143                 /* This can happen either due to bugs in the get_hw_state
13144                  * functions or because the pipe is force-enabled due to the
13145                  * pipe A quirk. */
13146                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13147                               crtc->base.base.id,
13148                               crtc->base.enabled ? "enabled" : "disabled",
13149                               crtc->active ? "enabled" : "disabled");
13150
13151                 crtc->base.enabled = crtc->active;
13152
13153                 /* Because we only establish the connector -> encoder ->
13154                  * crtc links if something is active, this means the
13155                  * crtc is now deactivated. Break the links. connector
13156                  * -> encoder links are only establish when things are
13157                  *  actually up, hence no need to break them. */
13158                 WARN_ON(crtc->active);
13159
13160                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13161                         WARN_ON(encoder->connectors_active);
13162                         encoder->base.crtc = NULL;
13163                 }
13164         }
13165
13166         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13167                 /*
13168                  * We start out with underrun reporting disabled to avoid races.
13169                  * For correct bookkeeping mark this on active crtcs.
13170                  *
13171                  * Also on gmch platforms we dont have any hardware bits to
13172                  * disable the underrun reporting. Which means we need to start
13173                  * out with underrun reporting disabled also on inactive pipes,
13174                  * since otherwise we'll complain about the garbage we read when
13175                  * e.g. coming up after runtime pm.
13176                  *
13177                  * No protection against concurrent access is required - at
13178                  * worst a fifo underrun happens which also sets this to false.
13179                  */
13180                 crtc->cpu_fifo_underrun_disabled = true;
13181                 crtc->pch_fifo_underrun_disabled = true;
13182         }
13183 }
13184
13185 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13186 {
13187         struct intel_connector *connector;
13188         struct drm_device *dev = encoder->base.dev;
13189
13190         /* We need to check both for a crtc link (meaning that the
13191          * encoder is active and trying to read from a pipe) and the
13192          * pipe itself being active. */
13193         bool has_active_crtc = encoder->base.crtc &&
13194                 to_intel_crtc(encoder->base.crtc)->active;
13195
13196         if (encoder->connectors_active && !has_active_crtc) {
13197                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13198                               encoder->base.base.id,
13199                               encoder->base.name);
13200
13201                 /* Connector is active, but has no active pipe. This is
13202                  * fallout from our resume register restoring. Disable
13203                  * the encoder manually again. */
13204                 if (encoder->base.crtc) {
13205                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13206                                       encoder->base.base.id,
13207                                       encoder->base.name);
13208                         encoder->disable(encoder);
13209                         if (encoder->post_disable)
13210                                 encoder->post_disable(encoder);
13211                 }
13212                 encoder->base.crtc = NULL;
13213                 encoder->connectors_active = false;
13214
13215                 /* Inconsistent output/port/pipe state happens presumably due to
13216                  * a bug in one of the get_hw_state functions. Or someplace else
13217                  * in our code, like the register restore mess on resume. Clamp
13218                  * things to off as a safer default. */
13219                 list_for_each_entry(connector,
13220                                     &dev->mode_config.connector_list,
13221                                     base.head) {
13222                         if (connector->encoder != encoder)
13223                                 continue;
13224                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13225                         connector->base.encoder = NULL;
13226                 }
13227         }
13228         /* Enabled encoders without active connectors will be fixed in
13229          * the crtc fixup. */
13230 }
13231
13232 void i915_redisable_vga_power_on(struct drm_device *dev)
13233 {
13234         struct drm_i915_private *dev_priv = dev->dev_private;
13235         u32 vga_reg = i915_vgacntrl_reg(dev);
13236
13237         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13238                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13239                 i915_disable_vga(dev);
13240         }
13241 }
13242
13243 void i915_redisable_vga(struct drm_device *dev)
13244 {
13245         struct drm_i915_private *dev_priv = dev->dev_private;
13246
13247         /* This function can be called both from intel_modeset_setup_hw_state or
13248          * at a very early point in our resume sequence, where the power well
13249          * structures are not yet restored. Since this function is at a very
13250          * paranoid "someone might have enabled VGA while we were not looking"
13251          * level, just check if the power well is enabled instead of trying to
13252          * follow the "don't touch the power well if we don't need it" policy
13253          * the rest of the driver uses. */
13254         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13255                 return;
13256
13257         i915_redisable_vga_power_on(dev);
13258 }
13259
13260 static bool primary_get_hw_state(struct intel_crtc *crtc)
13261 {
13262         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13263
13264         if (!crtc->active)
13265                 return false;
13266
13267         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13268 }
13269
13270 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13271 {
13272         struct drm_i915_private *dev_priv = dev->dev_private;
13273         enum pipe pipe;
13274         struct intel_crtc *crtc;
13275         struct intel_encoder *encoder;
13276         struct intel_connector *connector;
13277         int i;
13278
13279         for_each_intel_crtc(dev, crtc) {
13280                 memset(&crtc->config, 0, sizeof(crtc->config));
13281
13282                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13283
13284                 crtc->active = dev_priv->display.get_pipe_config(crtc,
13285                                                                  &crtc->config);
13286
13287                 crtc->base.enabled = crtc->active;
13288                 crtc->primary_enabled = primary_get_hw_state(crtc);
13289
13290                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13291                               crtc->base.base.id,
13292                               crtc->active ? "enabled" : "disabled");
13293         }
13294
13295         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13296                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13297
13298                 pll->on = pll->get_hw_state(dev_priv, pll,
13299                                             &pll->config.hw_state);
13300                 pll->active = 0;
13301                 pll->config.crtc_mask = 0;
13302                 for_each_intel_crtc(dev, crtc) {
13303                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13304                                 pll->active++;
13305                                 pll->config.crtc_mask |= 1 << crtc->pipe;
13306                         }
13307                 }
13308
13309                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13310                               pll->name, pll->config.crtc_mask, pll->on);
13311
13312                 if (pll->config.crtc_mask)
13313                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13314         }
13315
13316         for_each_intel_encoder(dev, encoder) {
13317                 pipe = 0;
13318
13319                 if (encoder->get_hw_state(encoder, &pipe)) {
13320                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13321                         encoder->base.crtc = &crtc->base;
13322                         encoder->get_config(encoder, &crtc->config);
13323                 } else {
13324                         encoder->base.crtc = NULL;
13325                 }
13326
13327                 encoder->connectors_active = false;
13328                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13329                               encoder->base.base.id,
13330                               encoder->base.name,
13331                               encoder->base.crtc ? "enabled" : "disabled",
13332                               pipe_name(pipe));
13333         }
13334
13335         list_for_each_entry(connector, &dev->mode_config.connector_list,
13336                             base.head) {
13337                 if (connector->get_hw_state(connector)) {
13338                         connector->base.dpms = DRM_MODE_DPMS_ON;
13339                         connector->encoder->connectors_active = true;
13340                         connector->base.encoder = &connector->encoder->base;
13341                 } else {
13342                         connector->base.dpms = DRM_MODE_DPMS_OFF;
13343                         connector->base.encoder = NULL;
13344                 }
13345                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13346                               connector->base.base.id,
13347                               connector->base.name,
13348                               connector->base.encoder ? "enabled" : "disabled");
13349         }
13350 }
13351
13352 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13353  * and i915 state tracking structures. */
13354 void intel_modeset_setup_hw_state(struct drm_device *dev,
13355                                   bool force_restore)
13356 {
13357         struct drm_i915_private *dev_priv = dev->dev_private;
13358         enum pipe pipe;
13359         struct intel_crtc *crtc;
13360         struct intel_encoder *encoder;
13361         int i;
13362
13363         intel_modeset_readout_hw_state(dev);
13364
13365         /*
13366          * Now that we have the config, copy it to each CRTC struct
13367          * Note that this could go away if we move to using crtc_config
13368          * checking everywhere.
13369          */
13370         for_each_intel_crtc(dev, crtc) {
13371                 if (crtc->active && i915.fastboot) {
13372                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13373                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13374                                       crtc->base.base.id);
13375                         drm_mode_debug_printmodeline(&crtc->base.mode);
13376                 }
13377         }
13378
13379         /* HW state is read out, now we need to sanitize this mess. */
13380         for_each_intel_encoder(dev, encoder) {
13381                 intel_sanitize_encoder(encoder);
13382         }
13383
13384         for_each_pipe(dev_priv, pipe) {
13385                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13386                 intel_sanitize_crtc(crtc);
13387                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13388         }
13389
13390         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13391                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13392
13393                 if (!pll->on || pll->active)
13394                         continue;
13395
13396                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13397
13398                 pll->disable(dev_priv, pll);
13399                 pll->on = false;
13400         }
13401
13402         if (IS_GEN9(dev))
13403                 skl_wm_get_hw_state(dev);
13404         else if (HAS_PCH_SPLIT(dev))
13405                 ilk_wm_get_hw_state(dev);
13406
13407         if (force_restore) {
13408                 i915_redisable_vga(dev);
13409
13410                 /*
13411                  * We need to use raw interfaces for restoring state to avoid
13412                  * checking (bogus) intermediate states.
13413                  */
13414                 for_each_pipe(dev_priv, pipe) {
13415                         struct drm_crtc *crtc =
13416                                 dev_priv->pipe_to_crtc_mapping[pipe];
13417
13418                         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13419                                        crtc->primary->fb);
13420                 }
13421         } else {
13422                 intel_modeset_update_staged_output_state(dev);
13423         }
13424
13425         intel_modeset_check_state(dev);
13426 }
13427
13428 void intel_modeset_gem_init(struct drm_device *dev)
13429 {
13430         struct drm_i915_private *dev_priv = dev->dev_private;
13431         struct drm_crtc *c;
13432         struct drm_i915_gem_object *obj;
13433
13434         mutex_lock(&dev->struct_mutex);
13435         intel_init_gt_powersave(dev);
13436         mutex_unlock(&dev->struct_mutex);
13437
13438         /*
13439          * There may be no VBT; and if the BIOS enabled SSC we can
13440          * just keep using it to avoid unnecessary flicker.  Whereas if the
13441          * BIOS isn't using it, don't assume it will work even if the VBT
13442          * indicates as much.
13443          */
13444         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13445                 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13446                                                 DREF_SSC1_ENABLE);
13447
13448         intel_modeset_init_hw(dev);
13449
13450         intel_setup_overlay(dev);
13451
13452         /*
13453          * Make sure any fbs we allocated at startup are properly
13454          * pinned & fenced.  When we do the allocation it's too early
13455          * for this.
13456          */
13457         mutex_lock(&dev->struct_mutex);
13458         for_each_crtc(dev, c) {
13459                 obj = intel_fb_obj(c->primary->fb);
13460                 if (obj == NULL)
13461                         continue;
13462
13463                 if (intel_pin_and_fence_fb_obj(c->primary,
13464                                                c->primary->fb,
13465                                                NULL)) {
13466                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
13467                                   to_intel_crtc(c)->pipe);
13468                         drm_framebuffer_unreference(c->primary->fb);
13469                         c->primary->fb = NULL;
13470                 }
13471         }
13472         mutex_unlock(&dev->struct_mutex);
13473
13474         intel_backlight_register(dev);
13475 }
13476
13477 void intel_connector_unregister(struct intel_connector *intel_connector)
13478 {
13479         struct drm_connector *connector = &intel_connector->base;
13480
13481         intel_panel_destroy_backlight(connector);
13482         drm_connector_unregister(connector);
13483 }
13484
13485 void intel_modeset_cleanup(struct drm_device *dev)
13486 {
13487         struct drm_i915_private *dev_priv = dev->dev_private;
13488         struct drm_connector *connector;
13489
13490         intel_backlight_unregister(dev);
13491
13492         /*
13493          * Interrupts and polling as the first thing to avoid creating havoc.
13494          * Too much stuff here (turning of rps, connectors, ...) would
13495          * experience fancy races otherwise.
13496          */
13497         intel_irq_uninstall(dev_priv);
13498
13499         /*
13500          * Due to the hpd irq storm handling the hotplug work can re-arm the
13501          * poll handlers. Hence disable polling after hpd handling is shut down.
13502          */
13503         drm_kms_helper_poll_fini(dev);
13504
13505         mutex_lock(&dev->struct_mutex);
13506
13507         intel_unregister_dsm_handler();
13508
13509         intel_disable_fbc(dev);
13510
13511         intel_disable_gt_powersave(dev);
13512
13513         ironlake_teardown_rc6(dev);
13514
13515         mutex_unlock(&dev->struct_mutex);
13516
13517         /* flush any delayed tasks or pending work */
13518         flush_scheduled_work();
13519
13520         /* destroy the backlight and sysfs files before encoders/connectors */
13521         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13522                 struct intel_connector *intel_connector;
13523
13524                 intel_connector = to_intel_connector(connector);
13525                 intel_connector->unregister(intel_connector);
13526         }
13527
13528         drm_mode_config_cleanup(dev);
13529
13530         intel_cleanup_overlay(dev);
13531
13532         mutex_lock(&dev->struct_mutex);
13533         intel_cleanup_gt_powersave(dev);
13534         mutex_unlock(&dev->struct_mutex);
13535 }
13536
13537 /*
13538  * Return which encoder is currently attached for connector.
13539  */
13540 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13541 {
13542         return &intel_attached_encoder(connector)->base;
13543 }
13544
13545 void intel_connector_attach_encoder(struct intel_connector *connector,
13546                                     struct intel_encoder *encoder)
13547 {
13548         connector->encoder = encoder;
13549         drm_mode_connector_attach_encoder(&connector->base,
13550                                           &encoder->base);
13551 }
13552
13553 /*
13554  * set vga decode state - true == enable VGA decode
13555  */
13556 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13557 {
13558         struct drm_i915_private *dev_priv = dev->dev_private;
13559         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13560         u16 gmch_ctrl;
13561
13562         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13563                 DRM_ERROR("failed to read control word\n");
13564                 return -EIO;
13565         }
13566
13567         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13568                 return 0;
13569
13570         if (state)
13571                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13572         else
13573                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13574
13575         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13576                 DRM_ERROR("failed to write control word\n");
13577                 return -EIO;
13578         }
13579
13580         return 0;
13581 }
13582
13583 struct intel_display_error_state {
13584
13585         u32 power_well_driver;
13586
13587         int num_transcoders;
13588
13589         struct intel_cursor_error_state {
13590                 u32 control;
13591                 u32 position;
13592                 u32 base;
13593                 u32 size;
13594         } cursor[I915_MAX_PIPES];
13595
13596         struct intel_pipe_error_state {
13597                 bool power_domain_on;
13598                 u32 source;
13599                 u32 stat;
13600         } pipe[I915_MAX_PIPES];
13601
13602         struct intel_plane_error_state {
13603                 u32 control;
13604                 u32 stride;
13605                 u32 size;
13606                 u32 pos;
13607                 u32 addr;
13608                 u32 surface;
13609                 u32 tile_offset;
13610         } plane[I915_MAX_PIPES];
13611
13612         struct intel_transcoder_error_state {
13613                 bool power_domain_on;
13614                 enum transcoder cpu_transcoder;
13615
13616                 u32 conf;
13617
13618                 u32 htotal;
13619                 u32 hblank;
13620                 u32 hsync;
13621                 u32 vtotal;
13622                 u32 vblank;
13623                 u32 vsync;
13624         } transcoder[4];
13625 };
13626
13627 struct intel_display_error_state *
13628 intel_display_capture_error_state(struct drm_device *dev)
13629 {
13630         struct drm_i915_private *dev_priv = dev->dev_private;
13631         struct intel_display_error_state *error;
13632         int transcoders[] = {
13633                 TRANSCODER_A,
13634                 TRANSCODER_B,
13635                 TRANSCODER_C,
13636                 TRANSCODER_EDP,
13637         };
13638         int i;
13639
13640         if (INTEL_INFO(dev)->num_pipes == 0)
13641                 return NULL;
13642
13643         error = kzalloc(sizeof(*error), GFP_ATOMIC);
13644         if (error == NULL)
13645                 return NULL;
13646
13647         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13648                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13649
13650         for_each_pipe(dev_priv, i) {
13651                 error->pipe[i].power_domain_on =
13652                         __intel_display_power_is_enabled(dev_priv,
13653                                                          POWER_DOMAIN_PIPE(i));
13654                 if (!error->pipe[i].power_domain_on)
13655                         continue;
13656
13657                 error->cursor[i].control = I915_READ(CURCNTR(i));
13658                 error->cursor[i].position = I915_READ(CURPOS(i));
13659                 error->cursor[i].base = I915_READ(CURBASE(i));
13660
13661                 error->plane[i].control = I915_READ(DSPCNTR(i));
13662                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13663                 if (INTEL_INFO(dev)->gen <= 3) {
13664                         error->plane[i].size = I915_READ(DSPSIZE(i));
13665                         error->plane[i].pos = I915_READ(DSPPOS(i));
13666                 }
13667                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13668                         error->plane[i].addr = I915_READ(DSPADDR(i));
13669                 if (INTEL_INFO(dev)->gen >= 4) {
13670                         error->plane[i].surface = I915_READ(DSPSURF(i));
13671                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13672                 }
13673
13674                 error->pipe[i].source = I915_READ(PIPESRC(i));
13675
13676                 if (HAS_GMCH_DISPLAY(dev))
13677                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
13678         }
13679
13680         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13681         if (HAS_DDI(dev_priv->dev))
13682                 error->num_transcoders++; /* Account for eDP. */
13683
13684         for (i = 0; i < error->num_transcoders; i++) {
13685                 enum transcoder cpu_transcoder = transcoders[i];
13686
13687                 error->transcoder[i].power_domain_on =
13688                         __intel_display_power_is_enabled(dev_priv,
13689                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13690                 if (!error->transcoder[i].power_domain_on)
13691                         continue;
13692
13693                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13694
13695                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13696                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13697                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13698                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13699                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13700                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13701                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13702         }
13703
13704         return error;
13705 }
13706
13707 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13708
13709 void
13710 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13711                                 struct drm_device *dev,
13712                                 struct intel_display_error_state *error)
13713 {
13714         struct drm_i915_private *dev_priv = dev->dev_private;
13715         int i;
13716
13717         if (!error)
13718                 return;
13719
13720         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13721         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13722                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13723                            error->power_well_driver);
13724         for_each_pipe(dev_priv, i) {
13725                 err_printf(m, "Pipe [%d]:\n", i);
13726                 err_printf(m, "  Power: %s\n",
13727                            error->pipe[i].power_domain_on ? "on" : "off");
13728                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
13729                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
13730
13731                 err_printf(m, "Plane [%d]:\n", i);
13732                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
13733                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
13734                 if (INTEL_INFO(dev)->gen <= 3) {
13735                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
13736                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
13737                 }
13738                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13739                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
13740                 if (INTEL_INFO(dev)->gen >= 4) {
13741                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
13742                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
13743                 }
13744
13745                 err_printf(m, "Cursor [%d]:\n", i);
13746                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
13747                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
13748                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
13749         }
13750
13751         for (i = 0; i < error->num_transcoders; i++) {
13752                 err_printf(m, "CPU transcoder: %c\n",
13753                            transcoder_name(error->transcoder[i].cpu_transcoder));
13754                 err_printf(m, "  Power: %s\n",
13755                            error->transcoder[i].power_domain_on ? "on" : "off");
13756                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
13757                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
13758                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
13759                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
13760                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
13761                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
13762                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
13763         }
13764 }
13765
13766 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13767 {
13768         struct intel_crtc *crtc;
13769
13770         for_each_intel_crtc(dev, crtc) {
13771                 struct intel_unpin_work *work;
13772
13773                 spin_lock_irq(&dev->event_lock);
13774
13775                 work = crtc->unpin_work;
13776
13777                 if (work && work->event &&
13778                     work->event->base.file_priv == file) {
13779                         kfree(work->event);
13780                         work->event = NULL;
13781                 }
13782
13783                 spin_unlock_irq(&dev->event_lock);
13784         }
13785 }