drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  45         ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  46
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  51                                 struct intel_crtc_config *pipe_config);
  52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  53                                    struct intel_crtc_config *pipe_config);
  54
  55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  56                           int x, int y, struct drm_framebuffer *old_fb);
  57 static int intel_framebuffer_init(struct drm_device *dev,
  58                                   struct intel_framebuffer *ifb,
  59                                   struct drm_mode_fb_cmd2 *mode_cmd,
  60                                   struct drm_i915_gem_object *obj);
  61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
  62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  65                                          struct intel_link_m_n *m_n);
  66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
  68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
  69 static void vlv_prepare_pll(struct intel_crtc *crtc);
  70
  71 typedef struct {
  72         int     min, max;
  73 } intel_range_t;
  74
  75 typedef struct {
  76         int     dot_limit;
  77         int     p2_slow, p2_fast;
  78 } intel_p2_t;
  79
  80 typedef struct intel_limit intel_limit_t;
  81 struct intel_limit {
  82         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  83         intel_p2_t          p2;
  84 };
  85
  86 int
  87 intel_pch_rawclk(struct drm_device *dev)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90
  91         WARN_ON(!HAS_PCH_SPLIT(dev));
  92
  93         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  94 }
  95
  96 static inline u32 /* units of 100MHz */
  97 intel_fdi_link_freq(struct drm_device *dev)
  98 {
  99         if (IS_GEN5(dev)) {
 100                 struct drm_i915_private *dev_priv = dev->dev_private;
 101                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 102         } else
 103                 return 27;
 104 }
 105
 106 static const intel_limit_t intel_limits_i8xx_dac = {
 107         .dot = { .min = 25000, .max = 350000 },
 108         .vco = { .min = 908000, .max = 1512000 },
 109         .n = { .min = 2, .max = 16 },
 110         .m = { .min = 96, .max = 140 },
 111         .m1 = { .min = 18, .max = 26 },
 112         .m2 = { .min = 6, .max = 16 },
 113         .p = { .min = 4, .max = 128 },
 114         .p1 = { .min = 2, .max = 33 },
 115         .p2 = { .dot_limit = 165000,
 116                 .p2_slow = 4, .p2_fast = 2 },
 117 };
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 908000, .max = 1512000 },
 122         .n = { .min = 2, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 4 },
 130 };
 131
 132 static const intel_limit_t intel_limits_i8xx_lvds = {
 133         .dot = { .min = 25000, .max = 350000 },
 134         .vco = { .min = 908000, .max = 1512000 },
 135         .n = { .min = 2, .max = 16 },
 136         .m = { .min = 96, .max = 140 },
 137         .m1 = { .min = 18, .max = 26 },
 138         .m2 = { .min = 6, .max = 16 },
 139         .p = { .min = 4, .max = 128 },
 140         .p1 = { .min = 1, .max = 6 },
 141         .p2 = { .dot_limit = 165000,
 142                 .p2_slow = 14, .p2_fast = 7 },
 143 };
 144
 145 static const intel_limit_t intel_limits_i9xx_sdvo = {
 146         .dot = { .min = 20000, .max = 400000 },
 147         .vco = { .min = 1400000, .max = 2800000 },
 148         .n = { .min = 1, .max = 6 },
 149         .m = { .min = 70, .max = 120 },
 150         .m1 = { .min = 8, .max = 18 },
 151         .m2 = { .min = 3, .max = 7 },
 152         .p = { .min = 5, .max = 80 },
 153         .p1 = { .min = 1, .max = 8 },
 154         .p2 = { .dot_limit = 200000,
 155                 .p2_slow = 10, .p2_fast = 5 },
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 8, .max = 18 },
 164         .m2 = { .min = 3, .max = 7 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169 };
 170
 171
 172 static const intel_limit_t intel_limits_g4x_sdvo = {
 173         .dot = { .min = 25000, .max = 270000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 17, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 10, .max = 30 },
 180         .p1 = { .min = 1, .max = 3},
 181         .p2 = { .dot_limit = 270000,
 182                 .p2_slow = 10,
 183                 .p2_fast = 10
 184         },
 185 };
 186
 187 static const intel_limit_t intel_limits_g4x_hdmi = {
 188         .dot = { .min = 22000, .max = 400000 },
 189         .vco = { .min = 1750000, .max = 3500000},
 190         .n = { .min = 1, .max = 4 },
 191         .m = { .min = 104, .max = 138 },
 192         .m1 = { .min = 16, .max = 23 },
 193         .m2 = { .min = 5, .max = 11 },
 194         .p = { .min = 5, .max = 80 },
 195         .p1 = { .min = 1, .max = 8},
 196         .p2 = { .dot_limit = 165000,
 197                 .p2_slow = 10, .p2_fast = 5 },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 201         .dot = { .min = 20000, .max = 115000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 28, .max = 112 },
 208         .p1 = { .min = 2, .max = 8 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 14, .p2_fast = 14
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 215         .dot = { .min = 80000, .max = 224000 },
 216         .vco = { .min = 1750000, .max = 3500000 },
 217         .n = { .min = 1, .max = 3 },
 218         .m = { .min = 104, .max = 138 },
 219         .m1 = { .min = 17, .max = 23 },
 220         .m2 = { .min = 5, .max = 11 },
 221         .p = { .min = 14, .max = 42 },
 222         .p1 = { .min = 2, .max = 6 },
 223         .p2 = { .dot_limit = 0,
 224                 .p2_slow = 7, .p2_fast = 7
 225         },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_sdvo = {
 229         .dot = { .min = 20000, .max = 400000},
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         /* Pineview's Ncounter is a ring counter */
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         /* Pineview only has one combined m divider, which we treat as m2. */
 235         .m1 = { .min = 0, .max = 0 },
 236         .m2 = { .min = 0, .max = 254 },
 237         .p = { .min = 5, .max = 80 },
 238         .p1 = { .min = 1, .max = 8 },
 239         .p2 = { .dot_limit = 200000,
 240                 .p2_slow = 10, .p2_fast = 5 },
 241 };
 242
 243 static const intel_limit_t intel_limits_pineview_lvds = {
 244         .dot = { .min = 20000, .max = 400000 },
 245         .vco = { .min = 1700000, .max = 3500000 },
 246         .n = { .min = 3, .max = 6 },
 247         .m = { .min = 2, .max = 256 },
 248         .m1 = { .min = 0, .max = 0 },
 249         .m2 = { .min = 0, .max = 254 },
 250         .p = { .min = 7, .max = 112 },
 251         .p1 = { .min = 1, .max = 8 },
 252         .p2 = { .dot_limit = 112000,
 253                 .p2_slow = 14, .p2_fast = 14 },
 254 };
 255
 256 /* Ironlake / Sandybridge
 257  *
 258  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 259  * the range value for them is (actual_value - 2).
 260  */
 261 static const intel_limit_t intel_limits_ironlake_dac = {
 262         .dot = { .min = 25000, .max = 350000 },
 263         .vco = { .min = 1760000, .max = 3510000 },
 264         .n = { .min = 1, .max = 5 },
 265         .m = { .min = 79, .max = 127 },
 266         .m1 = { .min = 12, .max = 22 },
 267         .m2 = { .min = 5, .max = 9 },
 268         .p = { .min = 5, .max = 80 },
 269         .p1 = { .min = 1, .max = 8 },
 270         .p2 = { .dot_limit = 225000,
 271                 .p2_slow = 10, .p2_fast = 5 },
 272 };
 273
 274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 275         .dot = { .min = 25000, .max = 350000 },
 276         .vco = { .min = 1760000, .max = 3510000 },
 277         .n = { .min = 1, .max = 3 },
 278         .m = { .min = 79, .max = 118 },
 279         .m1 = { .min = 12, .max = 22 },
 280         .m2 = { .min = 5, .max = 9 },
 281         .p = { .min = 28, .max = 112 },
 282         .p1 = { .min = 2, .max = 8 },
 283         .p2 = { .dot_limit = 225000,
 284                 .p2_slow = 14, .p2_fast = 14 },
 285 };
 286
 287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 3 },
 291         .m = { .min = 79, .max = 127 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 14, .max = 56 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 7, .p2_fast = 7 },
 298 };
 299
 300 /* LVDS 100mhz refclk limits. */
 301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 302         .dot = { .min = 25000, .max = 350000 },
 303         .vco = { .min = 1760000, .max = 3510000 },
 304         .n = { .min = 1, .max = 2 },
 305         .m = { .min = 79, .max = 126 },
 306         .m1 = { .min = 12, .max = 22 },
 307         .m2 = { .min = 5, .max = 9 },
 308         .p = { .min = 28, .max = 112 },
 309         .p1 = { .min = 2, .max = 8 },
 310         .p2 = { .dot_limit = 225000,
 311                 .p2_slow = 14, .p2_fast = 14 },
 312 };
 313
 314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 3 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 14, .max = 42 },
 322         .p1 = { .min = 2, .max = 6 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 7, .p2_fast = 7 },
 325 };
 326
 327 static const intel_limit_t intel_limits_vlv = {
 328          /*
 329           * These are the data rate limits (measured in fast clocks)
 330           * since those are the strictest limits we have. The fast
 331           * clock and actual rate limits are more relaxed, so checking
 332           * them would make no difference.
 333           */
 334         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 335         .vco = { .min = 4000000, .max = 6000000 },
 336         .n = { .min = 1, .max = 7 },
 337         .m1 = { .min = 2, .max = 3 },
 338         .m2 = { .min = 11, .max = 156 },
 339         .p1 = { .min = 2, .max = 3 },
 340         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 341 };
 342
 343 static const intel_limit_t intel_limits_chv = {
 344         /*
 345          * These are the data rate limits (measured in fast clocks)
 346          * since those are the strictest limits we have.  The fast
 347          * clock and actual rate limits are more relaxed, so checking
 348          * them would make no difference.
 349          */
 350         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 351         .vco = { .min = 4860000, .max = 6700000 },
 352         .n = { .min = 1, .max = 1 },
 353         .m1 = { .min = 2, .max = 2 },
 354         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 355         .p1 = { .min = 2, .max = 4 },
 356         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 357 };
 358
 359 static void vlv_clock(int refclk, intel_clock_t *clock)
 360 {
 361         clock->m = clock->m1 * clock->m2;
 362         clock->p = clock->p1 * clock->p2;
 363         if (WARN_ON(clock->n == 0 || clock->p == 0))
 364                 return;
 365         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 366         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 367 }
 368
 369 /**
 370  * Returns whether any output on the specified pipe is of the specified type
 371  */
 372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 373 {
 374         struct drm_device *dev = crtc->dev;
 375         struct intel_encoder *encoder;
 376
 377         for_each_encoder_on_crtc(dev, crtc, encoder)
 378                 if (encoder->type == type)
 379                         return true;
 380
 381         return false;
 382 }
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_CHERRYVIEW(dev)) {
 444                 limit = &intel_limits_chv;
 445         } else if (IS_VALLEYVIEW(dev)) {
 446                 limit = &intel_limits_vlv;
 447         } else if (!IS_GEN2(dev)) {
 448                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 449                         limit = &intel_limits_i9xx_lvds;
 450                 else
 451                         limit = &intel_limits_i9xx_sdvo;
 452         } else {
 453                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 454                         limit = &intel_limits_i8xx_lvds;
 455                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 456                         limit = &intel_limits_i8xx_dvo;
 457                 else
 458                         limit = &intel_limits_i8xx_dac;
 459         }
 460         return limit;
 461 }
 462
 463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 464 static void pineview_clock(int refclk, intel_clock_t *clock)
 465 {
 466         clock->m = clock->m2 + 2;
 467         clock->p = clock->p1 * clock->p2;
 468         if (WARN_ON(clock->n == 0 || clock->p == 0))
 469                 return;
 470         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 471         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 472 }
 473
 474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 475 {
 476         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 477 }
 478
 479 static void i9xx_clock(int refclk, intel_clock_t *clock)
 480 {
 481         clock->m = i9xx_dpll_compute_m(clock);
 482         clock->p = clock->p1 * clock->p2;
 483         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 484                 return;
 485         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 486         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 487 }
 488
 489 static void chv_clock(int refclk, intel_clock_t *clock)
 490 {
 491         clock->m = clock->m1 * clock->m2;
 492         clock->p = clock->p1 * clock->p2;
 493         if (WARN_ON(clock->n == 0 || clock->p == 0))
 494                 return;
 495         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 496                         clock->n << 22);
 497         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 498 }
 499
 500 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 501 /**
 502  * Returns whether the given set of divisors are valid for a given refclk with
 503  * the given connectors.
 504  */
 505
 506 static bool intel_PLL_is_valid(struct drm_device *dev,
 507                                const intel_limit_t *limit,
 508                                const intel_clock_t *clock)
 509 {
 510         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 511                 INTELPllInvalid("n out of range\n");
 512         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 513                 INTELPllInvalid("p1 out of range\n");
 514         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 515                 INTELPllInvalid("m2 out of range\n");
 516         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 517                 INTELPllInvalid("m1 out of range\n");
 518
 519         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 520                 if (clock->m1 <= clock->m2)
 521                         INTELPllInvalid("m1 <= m2\n");
 522
 523         if (!IS_VALLEYVIEW(dev)) {
 524                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 525                         INTELPllInvalid("p out of range\n");
 526                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 527                         INTELPllInvalid("m out of range\n");
 528         }
 529
 530         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 531                 INTELPllInvalid("vco out of range\n");
 532         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 533          * connector, etc., rather than just a single range.
 534          */
 535         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 536                 INTELPllInvalid("dot out of range\n");
 537
 538         return true;
 539 }
 540
 541 static bool
 542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 543                     int target, int refclk, intel_clock_t *match_clock,
 544                     intel_clock_t *best_clock)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         if (clock.m2 >= clock.m1)
 574                                 break;
 575                         for (clock.n = limit->n.min;
 576                              clock.n <= limit->n.max; clock.n++) {
 577                                 for (clock.p1 = limit->p1.min;
 578                                         clock.p1 <= limit->p1.max; clock.p1++) {
 579                                         int this_err;
 580
 581                                         i9xx_clock(refclk, &clock);
 582                                         if (!intel_PLL_is_valid(dev, limit,
 583                                                                 &clock))
 584                                                 continue;
 585                                         if (match_clock &&
 586                                             clock.p != match_clock->p)
 587                                                 continue;
 588
 589                                         this_err = abs(clock.dot - target);
 590                                         if (this_err < err) {
 591                                                 *best_clock = clock;
 592                                                 err = this_err;
 593                                         }
 594                                 }
 595                         }
 596                 }
 597         }
 598
 599         return (err != target);
 600 }
 601
 602 static bool
 603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 604                    int target, int refclk, intel_clock_t *match_clock,
 605                    intel_clock_t *best_clock)
 606 {
 607         struct drm_device *dev = crtc->dev;
 608         intel_clock_t clock;
 609         int err = target;
 610
 611         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 612                 /*
 613                  * For LVDS just rely on its current settings for dual-channel.
 614                  * We haven't figured out how to reliably set up different
 615                  * single/dual channel state, if we even can.
 616                  */
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629
 630         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 631              clock.m1++) {
 632                 for (clock.m2 = limit->m2.min;
 633                      clock.m2 <= limit->m2.max; clock.m2++) {
 634                         for (clock.n = limit->n.min;
 635                              clock.n <= limit->n.max; clock.n++) {
 636                                 for (clock.p1 = limit->p1.min;
 637                                         clock.p1 <= limit->p1.max; clock.p1++) {
 638                                         int this_err;
 639
 640                                         pineview_clock(refclk, &clock);
 641                                         if (!intel_PLL_is_valid(dev, limit,
 642                                                                 &clock))
 643                                                 continue;
 644                                         if (match_clock &&
 645                                             clock.p != match_clock->p)
 646                                                 continue;
 647
 648                                         this_err = abs(clock.dot - target);
 649                                         if (this_err < err) {
 650                                                 *best_clock = clock;
 651                                                 err = this_err;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657
 658         return (err != target);
 659 }
 660
 661 static bool
 662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 663                    int target, int refclk, intel_clock_t *match_clock,
 664                    intel_clock_t *best_clock)
 665 {
 666         struct drm_device *dev = crtc->dev;
 667         intel_clock_t clock;
 668         int max_n;
 669         bool found;
 670         /* approximately equals target * 0.00585 */
 671         int err_most = (target >> 8) + (target >> 9);
 672         found = false;
 673
 674         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 675                 if (intel_is_dual_link_lvds(dev))
 676                         clock.p2 = limit->p2.p2_fast;
 677                 else
 678                         clock.p2 = limit->p2.p2_slow;
 679         } else {
 680                 if (target < limit->p2.dot_limit)
 681                         clock.p2 = limit->p2.p2_slow;
 682                 else
 683                         clock.p2 = limit->p2.p2_fast;
 684         }
 685
 686         memset(best_clock, 0, sizeof(*best_clock));
 687         max_n = limit->n.max;
 688         /* based on hardware requirement, prefer smaller n to precision */
 689         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 690                 /* based on hardware requirement, prefere larger m1,m2 */
 691                 for (clock.m1 = limit->m1.max;
 692                      clock.m1 >= limit->m1.min; clock.m1--) {
 693                         for (clock.m2 = limit->m2.max;
 694                              clock.m2 >= limit->m2.min; clock.m2--) {
 695                                 for (clock.p1 = limit->p1.max;
 696                                      clock.p1 >= limit->p1.min; clock.p1--) {
 697                                         int this_err;
 698
 699                                         i9xx_clock(refclk, &clock);
 700                                         if (!intel_PLL_is_valid(dev, limit,
 701                                                                 &clock))
 702                                                 continue;
 703
 704                                         this_err = abs(clock.dot - target);
 705                                         if (this_err < err_most) {
 706                                                 *best_clock = clock;
 707                                                 err_most = this_err;
 708                                                 max_n = clock.n;
 709                                                 found = true;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715         return found;
 716 }
 717
 718 static bool
 719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 720                    int target, int refclk, intel_clock_t *match_clock,
 721                    intel_clock_t *best_clock)
 722 {
 723         struct drm_device *dev = crtc->dev;
 724         intel_clock_t clock;
 725         unsigned int bestppm = 1000000;
 726         /* min update 19.2 MHz */
 727         int max_n = min(limit->n.max, refclk / 19200);
 728         bool found = false;
 729
 730         target *= 5; /* fast clock */
 731
 732         memset(best_clock, 0, sizeof(*best_clock));
 733
 734         /* based on hardware requirement, prefer smaller n to precision */
 735         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 736                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 737                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 738                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 739                                 clock.p = clock.p1 * clock.p2;
 740                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 741                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 742                                         unsigned int ppm, diff;
 743
 744                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 745                                                                      refclk * clock.m1);
 746
 747                                         vlv_clock(refclk, &clock);
 748
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752
 753                                         diff = abs(clock.dot - target);
 754                                         ppm = div_u64(1000000ULL * diff, target);
 755
 756                                         if (ppm < 100 && clock.p > best_clock->p) {
 757                                                 bestppm = 0;
 758                                                 *best_clock = clock;
 759                                                 found = true;
 760                                         }
 761
 762                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 763                                                 bestppm = ppm;
 764                                                 *best_clock = clock;
 765                                                 found = true;
 766                                         }
 767                                 }
 768                         }
 769                 }
 770         }
 771
 772         return found;
 773 }
 774
 775 static bool
 776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 777                    int target, int refclk, intel_clock_t *match_clock,
 778                    intel_clock_t *best_clock)
 779 {
 780         struct drm_device *dev = crtc->dev;
 781         intel_clock_t clock;
 782         uint64_t m2;
 783         int found = false;
 784
 785         memset(best_clock, 0, sizeof(*best_clock));
 786
 787         /*
 788          * Based on hardware doc, the n always set to 1, and m1 always
 789          * set to 2.  If requires to support 200Mhz refclk, we need to
 790          * revisit this because n may not 1 anymore.
 791          */
 792         clock.n = 1, clock.m1 = 2;
 793         target *= 5;    /* fast clock */
 794
 795         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 796                 for (clock.p2 = limit->p2.p2_fast;
 797                                 clock.p2 >= limit->p2.p2_slow;
 798                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 799
 800                         clock.p = clock.p1 * clock.p2;
 801
 802                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 803                                         clock.n) << 22, refclk * clock.m1);
 804
 805                         if (m2 > INT_MAX/clock.m1)
 806                                 continue;
 807
 808                         clock.m2 = m2;
 809
 810                         chv_clock(refclk, &clock);
 811
 812                         if (!intel_PLL_is_valid(dev, limit, &clock))
 813                                 continue;
 814
 815                         /* based on hardware requirement, prefer bigger p
 816                          */
 817                         if (clock.p > best_clock->p) {
 818                                 *best_clock = clock;
 819                                 found = true;
 820                         }
 821                 }
 822         }
 823
 824         return found;
 825 }
 826
 827 bool intel_crtc_active(struct drm_crtc *crtc)
 828 {
 829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 830
 831         /* Be paranoid as we can arrive here with only partial
 832          * state retrieved from the hardware during setup.
 833          *
 834          * We can ditch the adjusted_mode.crtc_clock check as soon
 835          * as Haswell has gained clock readout/fastboot support.
 836          *
 837          * We can ditch the crtc->primary->fb check as soon as we can
 838          * properly reconstruct framebuffers.
 839          */
 840         return intel_crtc->active && crtc->primary->fb &&
 841                 intel_crtc->config.adjusted_mode.crtc_clock;
 842 }
 843
 844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 845                                              enum pipe pipe)
 846 {
 847         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 848         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 849
 850         return intel_crtc->config.cpu_transcoder;
 851 }
 852
 853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 854 {
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856         u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 857
 858         frame = I915_READ(frame_reg);
 859
 860         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 861                 WARN(1, "vblank wait timed out\n");
 862 }
 863
 864 /**
 865  * intel_wait_for_vblank - wait for vblank on a given pipe
 866  * @dev: drm device
 867  * @pipe: pipe to wait for
 868  *
 869  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 870  * mode setting code.
 871  */
 872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         int pipestat_reg = PIPESTAT(pipe);
 876
 877         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 878                 g4x_wait_for_vblank(dev, pipe);
 879                 return;
 880         }
 881
 882         /* Clear existing vblank status. Note this will clear any other
 883          * sticky status fields as well.
 884          *
 885          * This races with i915_driver_irq_handler() with the result
 886          * that either function could miss a vblank event.  Here it is not
 887          * fatal, as we will either wait upon the next vblank interrupt or
 888          * timeout.  Generally speaking intel_wait_for_vblank() is only
 889          * called during modeset at which time the GPU should be idle and
 890          * should *not* be performing page flips and thus not waiting on
 891          * vblanks...
 892          * Currently, the result of us stealing a vblank from the irq
 893          * handler is that a single frame will be skipped during swapbuffers.
 894          */
 895         I915_WRITE(pipestat_reg,
 896                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 897
 898         /* Wait for vblank interrupt bit to set */
 899         if (wait_for(I915_READ(pipestat_reg) &
 900                      PIPE_VBLANK_INTERRUPT_STATUS,
 901                      50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         u32 reg = PIPEDSL(pipe);
 909         u32 line1, line2;
 910         u32 line_mask;
 911
 912         if (IS_GEN2(dev))
 913                 line_mask = DSL_LINEMASK_GEN2;
 914         else
 915                 line_mask = DSL_LINEMASK_GEN3;
 916
 917         line1 = I915_READ(reg) & line_mask;
 918         mdelay(5);
 919         line2 = I915_READ(reg) & line_mask;
 920
 921         return line1 == line2;
 922 }
 923
 924 /*
 925  * intel_wait_for_pipe_off - wait for pipe to turn off
 926  * @dev: drm device
 927  * @pipe: pipe to wait for
 928  *
 929  * After disabling a pipe, we can't wait for vblank in the usual way,
 930  * spinning on the vblank interrupt status bit, since we won't actually
 931  * see an interrupt when the pipe is disabled.
 932  *
 933  * On Gen4 and above:
 934  *   wait for the pipe register state bit to turn off
 935  *
 936  * Otherwise:
 937  *   wait for the display line value to settle (it usually
 938  *   ends up stopping at the start of the next frame).
 939  *
 940  */
 941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 942 {
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 945                                                                       pipe);
 946
 947         if (INTEL_INFO(dev)->gen >= 4) {
 948                 int reg = PIPECONF(cpu_transcoder);
 949
 950                 /* Wait for the Pipe State to go off */
 951                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 952                              100))
 953                         WARN(1, "pipe_off wait timed out\n");
 954         } else {
 955                 /* Wait for the display line to settle */
 956                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 957                         WARN(1, "pipe_off wait timed out\n");
 958         }
 959 }
 960
 961 /*
 962  * ibx_digital_port_connected - is the specified port connected?
 963  * @dev_priv: i915 private structure
 964  * @port: the port to test
 965  *
 966  * Returns true if @port is connected, false otherwise.
 967  */
 968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 969                                 struct intel_digital_port *port)
 970 {
 971         u32 bit;
 972
 973         if (HAS_PCH_IBX(dev_priv->dev)) {
 974                 switch (port->port) {
 975                 case PORT_B:
 976                         bit = SDE_PORTB_HOTPLUG;
 977                         break;
 978                 case PORT_C:
 979                         bit = SDE_PORTC_HOTPLUG;
 980                         break;
 981                 case PORT_D:
 982                         bit = SDE_PORTD_HOTPLUG;
 983                         break;
 984                 default:
 985                         return true;
 986                 }
 987         } else {
 988                 switch (port->port) {
 989                 case PORT_B:
 990                         bit = SDE_PORTB_HOTPLUG_CPT;
 991                         break;
 992                 case PORT_C:
 993                         bit = SDE_PORTC_HOTPLUG_CPT;
 994                         break;
 995                 case PORT_D:
 996                         bit = SDE_PORTD_HOTPLUG_CPT;
 997                         break;
 998                 default:
 999                         return true;
1000                 }
1001         }
1002
1003         return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008         return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013                 enum pipe pipe, bool state)
1014 {
1015         int reg;
1016         u32 val;
1017         bool cur_state;
1018
1019         reg = DPLL(pipe);
1020         val = I915_READ(reg);
1021         cur_state = !!(val & DPLL_VCO_ENABLE);
1022         WARN(cur_state != state,
1023              "PLL state assertion failure (expected %s, current %s)\n",
1024              state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030         u32 val;
1031         bool cur_state;
1032
1033         mutex_lock(&dev_priv->dpio_lock);
1034         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035         mutex_unlock(&dev_priv->dpio_lock);
1036
1037         cur_state = val & DSI_PLL_VCO_EN;
1038         WARN(cur_state != state,
1039              "DSI PLL state assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050         if (crtc->config.shared_dpll < 0)
1051                 return NULL;
1052
1053         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058                         struct intel_shared_dpll *pll,
1059                         bool state)
1060 {
1061         bool cur_state;
1062         struct intel_dpll_hw_state hw_state;
1063
1064         if (HAS_PCH_LPT(dev_priv->dev)) {
1065                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066                 return;
1067         }
1068
1069         if (WARN (!pll,
1070                   "asserting DPLL %s with no DPLL\n", state_string(state)))
1071                 return;
1072
1073         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074         WARN(cur_state != state,
1075              "%s assertion failure (expected %s, current %s)\n",
1076              pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080                           enum pipe pipe, bool state)
1081 {
1082         int reg;
1083         u32 val;
1084         bool cur_state;
1085         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086                                                                       pipe);
1087
1088         if (HAS_DDI(dev_priv->dev)) {
1089                 /* DDI does not have a specific FDI_TX register */
1090                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091                 val = I915_READ(reg);
1092                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093         } else {
1094                 reg = FDI_TX_CTL(pipe);
1095                 val = I915_READ(reg);
1096                 cur_state = !!(val & FDI_TX_ENABLE);
1097         }
1098         WARN(cur_state != state,
1099              "FDI TX state assertion failure (expected %s, current %s)\n",
1100              state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106                           enum pipe pipe, bool state)
1107 {
1108         int reg;
1109         u32 val;
1110         bool cur_state;
1111
1112         reg = FDI_RX_CTL(pipe);
1113         val = I915_READ(reg);
1114         cur_state = !!(val & FDI_RX_ENABLE);
1115         WARN(cur_state != state,
1116              "FDI RX state assertion failure (expected %s, current %s)\n",
1117              state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123                                       enum pipe pipe)
1124 {
1125         int reg;
1126         u32 val;
1127
1128         /* ILK FDI PLL is always enabled */
1129         if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130                 return;
1131
1132         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133         if (HAS_DDI(dev_priv->dev))
1134                 return;
1135
1136         reg = FDI_TX_CTL(pipe);
1137         val = I915_READ(reg);
1138         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142                        enum pipe pipe, bool state)
1143 {
1144         int reg;
1145         u32 val;
1146         bool cur_state;
1147
1148         reg = FDI_RX_CTL(pipe);
1149         val = I915_READ(reg);
1150         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151         WARN(cur_state != state,
1152              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153              state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157                                   enum pipe pipe)
1158 {
1159         int pp_reg, lvds_reg;
1160         u32 val;
1161         enum pipe panel_pipe = PIPE_A;
1162         bool locked = true;
1163
1164         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165                 pp_reg = PCH_PP_CONTROL;
1166                 lvds_reg = PCH_LVDS;
1167         } else {
1168                 pp_reg = PP_CONTROL;
1169                 lvds_reg = LVDS;
1170         }
1171
1172         val = I915_READ(pp_reg);
1173         if (!(val & PANEL_POWER_ON) ||
1174             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175                 locked = false;
1176
1177         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178                 panel_pipe = PIPE_B;
1179
1180         WARN(panel_pipe == pipe && locked,
1181              "panel assertion failure, pipe %c regs locked\n",
1182              pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186                           enum pipe pipe, bool state)
1187 {
1188         struct drm_device *dev = dev_priv->dev;
1189         bool cur_state;
1190
1191         if (IS_845G(dev) || IS_I865G(dev))
1192                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193         else
1194                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196         WARN(cur_state != state,
1197              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198              pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204                  enum pipe pipe, bool state)
1205 {
1206         int reg;
1207         u32 val;
1208         bool cur_state;
1209         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210                                                                       pipe);
1211
1212         /* if we need the pipe A quirk it must be always on */
1213         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214                 state = true;
1215
1216         if (!intel_display_power_enabled(dev_priv,
1217                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218                 cur_state = false;
1219         } else {
1220                 reg = PIPECONF(cpu_transcoder);
1221                 val = I915_READ(reg);
1222                 cur_state = !!(val & PIPECONF_ENABLE);
1223         }
1224
1225         WARN(cur_state != state,
1226              "pipe %c assertion failure (expected %s, current %s)\n",
1227              pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231                          enum plane plane, bool state)
1232 {
1233         int reg;
1234         u32 val;
1235         bool cur_state;
1236
1237         reg = DSPCNTR(plane);
1238         val = I915_READ(reg);
1239         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240         WARN(cur_state != state,
1241              "plane %c assertion failure (expected %s, current %s)\n",
1242              plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249                                    enum pipe pipe)
1250 {
1251         struct drm_device *dev = dev_priv->dev;
1252         int reg, i;
1253         u32 val;
1254         int cur_pipe;
1255
1256         /* Primary planes are fixed to pipes on gen4+ */
1257         if (INTEL_INFO(dev)->gen >= 4) {
1258                 reg = DSPCNTR(pipe);
1259                 val = I915_READ(reg);
1260                 WARN(val & DISPLAY_PLANE_ENABLE,
1261                      "plane %c assertion failure, should be disabled but not\n",
1262                      plane_name(pipe));
1263                 return;
1264         }
1265
1266         /* Need to check both planes against the pipe */
1267         for_each_pipe(i) {
1268                 reg = DSPCNTR(i);
1269                 val = I915_READ(reg);
1270                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271                         DISPPLANE_SEL_PIPE_SHIFT;
1272                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274                      plane_name(i), pipe_name(pipe));
1275         }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279                                     enum pipe pipe)
1280 {
1281         struct drm_device *dev = dev_priv->dev;
1282         int reg, sprite;
1283         u32 val;
1284
1285         if (IS_VALLEYVIEW(dev)) {
1286                 for_each_sprite(pipe, sprite) {
1287                         reg = SPCNTR(pipe, sprite);
1288                         val = I915_READ(reg);
1289                         WARN(val & SP_ENABLE,
1290                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291                              sprite_name(pipe, sprite), pipe_name(pipe));
1292                 }
1293         } else if (INTEL_INFO(dev)->gen >= 7) {
1294                 reg = SPRCTL(pipe);
1295                 val = I915_READ(reg);
1296                 WARN(val & SPRITE_ENABLE,
1297                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298                      plane_name(pipe), pipe_name(pipe));
1299         } else if (INTEL_INFO(dev)->gen >= 5) {
1300                 reg = DVSCNTR(pipe);
1301                 val = I915_READ(reg);
1302                 WARN(val & DVS_ENABLE,
1303                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304                      plane_name(pipe), pipe_name(pipe));
1305         }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310         u32 val;
1311         bool enabled;
1312
1313         WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315         val = I915_READ(PCH_DREF_CONTROL);
1316         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317                             DREF_SUPERSPREAD_SOURCE_MASK));
1318         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322                                            enum pipe pipe)
1323 {
1324         int reg;
1325         u32 val;
1326         bool enabled;
1327
1328         reg = PCH_TRANSCONF(pipe);
1329         val = I915_READ(reg);
1330         enabled = !!(val & TRANS_ENABLE);
1331         WARN(enabled,
1332              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333              pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337                             enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339         if ((val & DP_PORT_EN) == 0)
1340                 return false;
1341
1342         if (HAS_PCH_CPT(dev_priv->dev)) {
1343                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346                         return false;
1347         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349                         return false;
1350         } else {
1351                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352                         return false;
1353         }
1354         return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358                               enum pipe pipe, u32 val)
1359 {
1360         if ((val & SDVO_ENABLE) == 0)
1361                 return false;
1362
1363         if (HAS_PCH_CPT(dev_priv->dev)) {
1364                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365                         return false;
1366         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368                         return false;
1369         } else {
1370                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371                         return false;
1372         }
1373         return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377                               enum pipe pipe, u32 val)
1378 {
1379         if ((val & LVDS_PORT_EN) == 0)
1380                 return false;
1381
1382         if (HAS_PCH_CPT(dev_priv->dev)) {
1383                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384                         return false;
1385         } else {
1386                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387                         return false;
1388         }
1389         return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393                               enum pipe pipe, u32 val)
1394 {
1395         if ((val & ADPA_DAC_ENABLE) == 0)
1396                 return false;
1397         if (HAS_PCH_CPT(dev_priv->dev)) {
1398                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399                         return false;
1400         } else {
1401                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402                         return false;
1403         }
1404         return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408                                    enum pipe pipe, int reg, u32 port_sel)
1409 {
1410         u32 val = I915_READ(reg);
1411         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413              reg, pipe_name(pipe));
1414
1415         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416              && (val & DP_PIPEB_SELECT),
1417              "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421                                      enum pipe pipe, int reg)
1422 {
1423         u32 val = I915_READ(reg);
1424         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426              reg, pipe_name(pipe));
1427
1428         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429              && (val & SDVO_PIPE_B_SELECT),
1430              "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434                                       enum pipe pipe)
1435 {
1436         int reg;
1437         u32 val;
1438
1439         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443         reg = PCH_ADPA;
1444         val = I915_READ(reg);
1445         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446              "PCH VGA enabled on transcoder %c, should be disabled\n",
1447              pipe_name(pipe));
1448
1449         reg = PCH_LVDS;
1450         val = I915_READ(reg);
1451         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453              pipe_name(pipe));
1454
1455         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462         struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464         if (!IS_VALLEYVIEW(dev))
1465                 return;
1466
1467         /*
1468          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469          * CHV x1 PHY (DP/HDMI D)
1470          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471          */
1472         if (IS_CHERRYVIEW(dev)) {
1473                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475         } else {
1476                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477         }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484         if (!IS_VALLEYVIEW(dev))
1485                 return;
1486
1487         /*
1488          * Enable the CRI clock source so we can get at the display and the
1489          * reference clock for VGA hotplug / manual detection.
1490          */
1491         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1492                    DPLL_REFA_CLK_ENABLE_VLV |
1493                    DPLL_INTEGRATED_CRI_CLK_VLV);
1494
1495         if (IS_CHERRYVIEW(dev)) {
1496                 enum dpio_phy phy;
1497                 u32 val;
1498
1499                 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1500                         /* Poll for phypwrgood signal */
1501                         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1502                                                 PHY_POWERGOOD(phy), 1))
1503                                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1504
1505                         /*
1506                          * Deassert common lane reset for PHY.
1507                          *
1508                          * This should only be done on init and resume from S3
1509                          * with both PLLs disabled, or we risk losing DPIO and
1510                          * PLL synchronization.
1511                          */
1512                         val = I915_READ(DISPLAY_PHY_CONTROL);
1513                         I915_WRITE(DISPLAY_PHY_CONTROL,
1514                                 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1515                 }
1516
1517         } else {
1518                 /*
1519                  * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1520                  *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1521                  *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522                  *   b. The other bits such as sfr settings / modesel may all
1523                  *      be set to 0.
1524                  *
1525                  * This should only be done on init and resume from S3 with
1526                  * both PLLs disabled, or we risk losing DPIO and PLL
1527                  * synchronization.
1528                  */
1529                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1530         }
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc)
1534 {
1535         struct drm_device *dev = crtc->base.dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         int reg = DPLL(crtc->pipe);
1538         u32 dpll = crtc->config.dpll_hw_state.dpll;
1539
1540         assert_pipe_disabled(dev_priv, crtc->pipe);
1541
1542         /* No really, not for ILK+ */
1543         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545         /* PLL is protected by panel, make sure we can write it */
1546         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1547                 assert_panel_unlocked(dev_priv, crtc->pipe);
1548
1549         I915_WRITE(reg, dpll);
1550         POSTING_READ(reg);
1551         udelay(150);
1552
1553         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557         POSTING_READ(DPLL_MD(crtc->pipe));
1558
1559         /* We do this three times for luck */
1560         I915_WRITE(reg, dpll);
1561         POSTING_READ(reg);
1562         udelay(150); /* wait for warmup */
1563         I915_WRITE(reg, dpll);
1564         POSTING_READ(reg);
1565         udelay(150); /* wait for warmup */
1566         I915_WRITE(reg, dpll);
1567         POSTING_READ(reg);
1568         udelay(150); /* wait for warmup */
1569 }
1570
1571 static void chv_enable_pll(struct intel_crtc *crtc)
1572 {
1573         struct drm_device *dev = crtc->base.dev;
1574         struct drm_i915_private *dev_priv = dev->dev_private;
1575         int pipe = crtc->pipe;
1576         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1577         u32 tmp;
1578
1579         assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583         mutex_lock(&dev_priv->dpio_lock);
1584
1585         /* Enable back the 10bit clock to display controller */
1586         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587         tmp |= DPIO_DCLKP_EN;
1588         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590         /*
1591          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592          */
1593         udelay(1);
1594
1595         /* Enable PLL */
1596         I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1597
1598         /* Check PLL is locked */
1599         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1600                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
1602         /* not sure when this should be written */
1603         I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604         POSTING_READ(DPLL_MD(pipe));
1605
1606         mutex_unlock(&dev_priv->dpio_lock);
1607 }
1608
1609 static void i9xx_enable_pll(struct intel_crtc *crtc)
1610 {
1611         struct drm_device *dev = crtc->base.dev;
1612         struct drm_i915_private *dev_priv = dev->dev_private;
1613         int reg = DPLL(crtc->pipe);
1614         u32 dpll = crtc->config.dpll_hw_state.dpll;
1615
1616         assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618         /* No really, not for ILK+ */
1619         BUG_ON(INTEL_INFO(dev)->gen >= 5);
1620
1621         /* PLL is protected by panel, make sure we can write it */
1622         if (IS_MOBILE(dev) && !IS_I830(dev))
1623                 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625         I915_WRITE(reg, dpll);
1626
1627         /* Wait for the clocks to stabilize. */
1628         POSTING_READ(reg);
1629         udelay(150);
1630
1631         if (INTEL_INFO(dev)->gen >= 4) {
1632                 I915_WRITE(DPLL_MD(crtc->pipe),
1633                            crtc->config.dpll_hw_state.dpll_md);
1634         } else {
1635                 /* The pixel multiplier can only be updated once the
1636                  * DPLL is enabled and the clocks are stable.
1637                  *
1638                  * So write it again.
1639                  */
1640                 I915_WRITE(reg, dpll);
1641         }
1642
1643         /* We do this three times for luck */
1644         I915_WRITE(reg, dpll);
1645         POSTING_READ(reg);
1646         udelay(150); /* wait for warmup */
1647         I915_WRITE(reg, dpll);
1648         POSTING_READ(reg);
1649         udelay(150); /* wait for warmup */
1650         I915_WRITE(reg, dpll);
1651         POSTING_READ(reg);
1652         udelay(150); /* wait for warmup */
1653 }
1654
1655 /**
1656  * i9xx_disable_pll - disable a PLL
1657  * @dev_priv: i915 private structure
1658  * @pipe: pipe PLL to disable
1659  *
1660  * Disable the PLL for @pipe, making sure the pipe is off first.
1661  *
1662  * Note!  This is for pre-ILK only.
1663  */
1664 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1665 {
1666         /* Don't disable pipe A or pipe A PLLs if needed */
1667         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668                 return;
1669
1670         /* Make sure the pipe isn't still relying on us */
1671         assert_pipe_disabled(dev_priv, pipe);
1672
1673         I915_WRITE(DPLL(pipe), 0);
1674         POSTING_READ(DPLL(pipe));
1675 }
1676
1677 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1678 {
1679         u32 val = 0;
1680
1681         /* Make sure the pipe isn't still relying on us */
1682         assert_pipe_disabled(dev_priv, pipe);
1683
1684         /*
1685          * Leave integrated clock source and reference clock enabled for pipe B.
1686          * The latter is needed for VGA hotplug / manual detection.
1687          */
1688         if (pipe == PIPE_B)
1689                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1690         I915_WRITE(DPLL(pipe), val);
1691         POSTING_READ(DPLL(pipe));
1692
1693 }
1694
1695 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697         u32 val;
1698
1699         /* Make sure the pipe isn't still relying on us */
1700         assert_pipe_disabled(dev_priv, pipe);
1701
1702         /* Set PLL en = 0 */
1703         val = DPLL_SSC_REF_CLOCK_CHV;
1704         if (pipe != PIPE_A)
1705                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1706         I915_WRITE(DPLL(pipe), val);
1707         POSTING_READ(DPLL(pipe));
1708 }
1709
1710 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1711                 struct intel_digital_port *dport)
1712 {
1713         u32 port_mask;
1714         int dpll_reg;
1715
1716         switch (dport->port) {
1717         case PORT_B:
1718                 port_mask = DPLL_PORTB_READY_MASK;
1719                 dpll_reg = DPLL(0);
1720                 break;
1721         case PORT_C:
1722                 port_mask = DPLL_PORTC_READY_MASK;
1723                 dpll_reg = DPLL(0);
1724                 break;
1725         case PORT_D:
1726                 port_mask = DPLL_PORTD_READY_MASK;
1727                 dpll_reg = DPIO_PHY_STATUS;
1728                 break;
1729         default:
1730                 BUG();
1731         }
1732
1733         if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1734                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1735                      port_name(dport->port), I915_READ(dpll_reg));
1736 }
1737
1738 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1739 {
1740         struct drm_device *dev = crtc->base.dev;
1741         struct drm_i915_private *dev_priv = dev->dev_private;
1742         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1743
1744         WARN_ON(!pll->refcount);
1745         if (pll->active == 0) {
1746                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1747                 WARN_ON(pll->on);
1748                 assert_shared_dpll_disabled(dev_priv, pll);
1749
1750                 pll->mode_set(dev_priv, pll);
1751         }
1752 }
1753
1754 /**
1755  * intel_enable_shared_dpll - enable PCH PLL
1756  * @dev_priv: i915 private structure
1757  * @pipe: pipe PLL to enable
1758  *
1759  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1760  * drives the transcoder clock.
1761  */
1762 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->base.dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1767
1768         if (WARN_ON(pll == NULL))
1769                 return;
1770
1771         if (WARN_ON(pll->refcount == 0))
1772                 return;
1773
1774         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1775                       pll->name, pll->active, pll->on,
1776                       crtc->base.base.id);
1777
1778         if (pll->active++) {
1779                 WARN_ON(!pll->on);
1780                 assert_shared_dpll_enabled(dev_priv, pll);
1781                 return;
1782         }
1783         WARN_ON(pll->on);
1784
1785         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1786         pll->enable(dev_priv, pll);
1787         pll->on = true;
1788 }
1789
1790 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1791 {
1792         struct drm_device *dev = crtc->base.dev;
1793         struct drm_i915_private *dev_priv = dev->dev_private;
1794         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1795
1796         /* PCH only available on ILK+ */
1797         BUG_ON(INTEL_INFO(dev)->gen < 5);
1798         if (WARN_ON(pll == NULL))
1799                return;
1800
1801         if (WARN_ON(pll->refcount == 0))
1802                 return;
1803
1804         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1805                       pll->name, pll->active, pll->on,
1806                       crtc->base.base.id);
1807
1808         if (WARN_ON(pll->active == 0)) {
1809                 assert_shared_dpll_disabled(dev_priv, pll);
1810                 return;
1811         }
1812
1813         assert_shared_dpll_enabled(dev_priv, pll);
1814         WARN_ON(!pll->on);
1815         if (--pll->active)
1816                 return;
1817
1818         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1819         pll->disable(dev_priv, pll);
1820         pll->on = false;
1821 }
1822
1823 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1824                                            enum pipe pipe)
1825 {
1826         struct drm_device *dev = dev_priv->dev;
1827         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1829         uint32_t reg, val, pipeconf_val;
1830
1831         /* PCH only available on ILK+ */
1832         BUG_ON(INTEL_INFO(dev)->gen < 5);
1833
1834         /* Make sure PCH DPLL is enabled */
1835         assert_shared_dpll_enabled(dev_priv,
1836                                    intel_crtc_to_shared_dpll(intel_crtc));
1837
1838         /* FDI must be feeding us bits for PCH ports */
1839         assert_fdi_tx_enabled(dev_priv, pipe);
1840         assert_fdi_rx_enabled(dev_priv, pipe);
1841
1842         if (HAS_PCH_CPT(dev)) {
1843                 /* Workaround: Set the timing override bit before enabling the
1844                  * pch transcoder. */
1845                 reg = TRANS_CHICKEN2(pipe);
1846                 val = I915_READ(reg);
1847                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1848                 I915_WRITE(reg, val);
1849         }
1850
1851         reg = PCH_TRANSCONF(pipe);
1852         val = I915_READ(reg);
1853         pipeconf_val = I915_READ(PIPECONF(pipe));
1854
1855         if (HAS_PCH_IBX(dev_priv->dev)) {
1856                 /*
1857                  * make the BPC in transcoder be consistent with
1858                  * that in pipeconf reg.
1859                  */
1860                 val &= ~PIPECONF_BPC_MASK;
1861                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1862         }
1863
1864         val &= ~TRANS_INTERLACE_MASK;
1865         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1866                 if (HAS_PCH_IBX(dev_priv->dev) &&
1867                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1868                         val |= TRANS_LEGACY_INTERLACED_ILK;
1869                 else
1870                         val |= TRANS_INTERLACED;
1871         else
1872                 val |= TRANS_PROGRESSIVE;
1873
1874         I915_WRITE(reg, val | TRANS_ENABLE);
1875         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1876                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1877 }
1878
1879 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1880                                       enum transcoder cpu_transcoder)
1881 {
1882         u32 val, pipeconf_val;
1883
1884         /* PCH only available on ILK+ */
1885         BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1886
1887         /* FDI must be feeding us bits for PCH ports */
1888         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1889         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1890
1891         /* Workaround: set timing override bit. */
1892         val = I915_READ(_TRANSA_CHICKEN2);
1893         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1894         I915_WRITE(_TRANSA_CHICKEN2, val);
1895
1896         val = TRANS_ENABLE;
1897         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1898
1899         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1900             PIPECONF_INTERLACED_ILK)
1901                 val |= TRANS_INTERLACED;
1902         else
1903                 val |= TRANS_PROGRESSIVE;
1904
1905         I915_WRITE(LPT_TRANSCONF, val);
1906         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1907                 DRM_ERROR("Failed to enable PCH transcoder\n");
1908 }
1909
1910 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1911                                             enum pipe pipe)
1912 {
1913         struct drm_device *dev = dev_priv->dev;
1914         uint32_t reg, val;
1915
1916         /* FDI relies on the transcoder */
1917         assert_fdi_tx_disabled(dev_priv, pipe);
1918         assert_fdi_rx_disabled(dev_priv, pipe);
1919
1920         /* Ports must be off as well */
1921         assert_pch_ports_disabled(dev_priv, pipe);
1922
1923         reg = PCH_TRANSCONF(pipe);
1924         val = I915_READ(reg);
1925         val &= ~TRANS_ENABLE;
1926         I915_WRITE(reg, val);
1927         /* wait for PCH transcoder off, transcoder state */
1928         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1929                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1930
1931         if (!HAS_PCH_IBX(dev)) {
1932                 /* Workaround: Clear the timing override chicken bit again. */
1933                 reg = TRANS_CHICKEN2(pipe);
1934                 val = I915_READ(reg);
1935                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1936                 I915_WRITE(reg, val);
1937         }
1938 }
1939
1940 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1941 {
1942         u32 val;
1943
1944         val = I915_READ(LPT_TRANSCONF);
1945         val &= ~TRANS_ENABLE;
1946         I915_WRITE(LPT_TRANSCONF, val);
1947         /* wait for PCH transcoder off, transcoder state */
1948         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1949                 DRM_ERROR("Failed to disable PCH transcoder\n");
1950
1951         /* Workaround: clear timing override bit. */
1952         val = I915_READ(_TRANSA_CHICKEN2);
1953         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1954         I915_WRITE(_TRANSA_CHICKEN2, val);
1955 }
1956
1957 /**
1958  * intel_enable_pipe - enable a pipe, asserting requirements
1959  * @crtc: crtc responsible for the pipe
1960  *
1961  * Enable @crtc's pipe, making sure that various hardware specific requirements
1962  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1963  */
1964 static void intel_enable_pipe(struct intel_crtc *crtc)
1965 {
1966         struct drm_device *dev = crtc->base.dev;
1967         struct drm_i915_private *dev_priv = dev->dev_private;
1968         enum pipe pipe = crtc->pipe;
1969         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1970                                                                       pipe);
1971         enum pipe pch_transcoder;
1972         int reg;
1973         u32 val;
1974
1975         assert_planes_disabled(dev_priv, pipe);
1976         assert_cursor_disabled(dev_priv, pipe);
1977         assert_sprites_disabled(dev_priv, pipe);
1978
1979         if (HAS_PCH_LPT(dev_priv->dev))
1980                 pch_transcoder = TRANSCODER_A;
1981         else
1982                 pch_transcoder = pipe;
1983
1984         /*
1985          * A pipe without a PLL won't actually be able to drive bits from
1986          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1987          * need the check.
1988          */
1989         if (!HAS_PCH_SPLIT(dev_priv->dev))
1990                 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1991                         assert_dsi_pll_enabled(dev_priv);
1992                 else
1993                         assert_pll_enabled(dev_priv, pipe);
1994         else {
1995                 if (crtc->config.has_pch_encoder) {
1996                         /* if driving the PCH, we need FDI enabled */
1997                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1998                         assert_fdi_tx_pll_enabled(dev_priv,
1999                                                   (enum pipe) cpu_transcoder);
2000                 }
2001                 /* FIXME: assert CPU port conditions for SNB+ */
2002         }
2003
2004         reg = PIPECONF(cpu_transcoder);
2005         val = I915_READ(reg);
2006         if (val & PIPECONF_ENABLE) {
2007                 WARN_ON(!(pipe == PIPE_A &&
2008                           dev_priv->quirks & QUIRK_PIPEA_FORCE));
2009                 return;
2010         }
2011
2012         I915_WRITE(reg, val | PIPECONF_ENABLE);
2013         POSTING_READ(reg);
2014 }
2015
2016 /**
2017  * intel_disable_pipe - disable a pipe, asserting requirements
2018  * @dev_priv: i915 private structure
2019  * @pipe: pipe to disable
2020  *
2021  * Disable @pipe, making sure that various hardware specific requirements
2022  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2023  *
2024  * @pipe should be %PIPE_A or %PIPE_B.
2025  *
2026  * Will wait until the pipe has shut down before returning.
2027  */
2028 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2029                                enum pipe pipe)
2030 {
2031         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2032                                                                       pipe);
2033         int reg;
2034         u32 val;
2035
2036         /*
2037          * Make sure planes won't keep trying to pump pixels to us,
2038          * or we might hang the display.
2039          */
2040         assert_planes_disabled(dev_priv, pipe);
2041         assert_cursor_disabled(dev_priv, pipe);
2042         assert_sprites_disabled(dev_priv, pipe);
2043
2044         /* Don't disable pipe A or pipe A PLLs if needed */
2045         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2046                 return;
2047
2048         reg = PIPECONF(cpu_transcoder);
2049         val = I915_READ(reg);
2050         if ((val & PIPECONF_ENABLE) == 0)
2051                 return;
2052
2053         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2054         intel_wait_for_pipe_off(dev_priv->dev, pipe);
2055 }
2056
2057 /*
2058  * Plane regs are double buffered, going from enabled->disabled needs a
2059  * trigger in order to latch.  The display address reg provides this.
2060  */
2061 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2062                                enum plane plane)
2063 {
2064         struct drm_device *dev = dev_priv->dev;
2065         u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2066
2067         I915_WRITE(reg, I915_READ(reg));
2068         POSTING_READ(reg);
2069 }
2070
2071 /**
2072  * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2073  * @dev_priv: i915 private structure
2074  * @plane: plane to enable
2075  * @pipe: pipe being fed
2076  *
2077  * Enable @plane on @pipe, making sure that @pipe is running first.
2078  */
2079 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2080                                           enum plane plane, enum pipe pipe)
2081 {
2082         struct intel_crtc *intel_crtc =
2083                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2084         int reg;
2085         u32 val;
2086
2087         /* If the pipe isn't enabled, we can't pump pixels and may hang */
2088         assert_pipe_enabled(dev_priv, pipe);
2089
2090         if (intel_crtc->primary_enabled)
2091                 return;
2092
2093         intel_crtc->primary_enabled = true;
2094
2095         reg = DSPCNTR(plane);
2096         val = I915_READ(reg);
2097         WARN_ON(val & DISPLAY_PLANE_ENABLE);
2098
2099         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2100         intel_flush_primary_plane(dev_priv, plane);
2101         intel_wait_for_vblank(dev_priv->dev, pipe);
2102 }
2103
2104 /**
2105  * intel_disable_primary_hw_plane - disable the primary hardware plane
2106  * @dev_priv: i915 private structure
2107  * @plane: plane to disable
2108  * @pipe: pipe consuming the data
2109  *
2110  * Disable @plane; should be an independent operation.
2111  */
2112 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2113                                            enum plane plane, enum pipe pipe)
2114 {
2115         struct intel_crtc *intel_crtc =
2116                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2117         int reg;
2118         u32 val;
2119
2120         if (!intel_crtc->primary_enabled)
2121                 return;
2122
2123         intel_crtc->primary_enabled = false;
2124
2125         reg = DSPCNTR(plane);
2126         val = I915_READ(reg);
2127         WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2128
2129         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2130         intel_flush_primary_plane(dev_priv, plane);
2131         intel_wait_for_vblank(dev_priv->dev, pipe);
2132 }
2133
2134 static bool need_vtd_wa(struct drm_device *dev)
2135 {
2136 #ifdef CONFIG_INTEL_IOMMU
2137         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2138                 return true;
2139 #endif
2140         return false;
2141 }
2142
2143 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2144 {
2145         int tile_height;
2146
2147         tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2148         return ALIGN(height, tile_height);
2149 }
2150
2151 int
2152 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2153                            struct drm_i915_gem_object *obj,
2154                            struct intel_ring_buffer *pipelined)
2155 {
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         u32 alignment;
2158         int ret;
2159
2160         switch (obj->tiling_mode) {
2161         case I915_TILING_NONE:
2162                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2163                         alignment = 128 * 1024;
2164                 else if (INTEL_INFO(dev)->gen >= 4)
2165                         alignment = 4 * 1024;
2166                 else
2167                         alignment = 64 * 1024;
2168                 break;
2169         case I915_TILING_X:
2170                 /* pin() will align the object as required by fence */
2171                 alignment = 0;
2172                 break;
2173         case I915_TILING_Y:
2174                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2175                 return -EINVAL;
2176         default:
2177                 BUG();
2178         }
2179
2180         /* Note that the w/a also requires 64 PTE of padding following the
2181          * bo. We currently fill all unused PTE with the shadow page and so
2182          * we should always have valid PTE following the scanout preventing
2183          * the VT-d warning.
2184          */
2185         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2186                 alignment = 256 * 1024;
2187
2188         dev_priv->mm.interruptible = false;
2189         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2190         if (ret)
2191                 goto err_interruptible;
2192
2193         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2194          * fence, whereas 965+ only requires a fence if using
2195          * framebuffer compression.  For simplicity, we always install
2196          * a fence as the cost is not that onerous.
2197          */
2198         ret = i915_gem_object_get_fence(obj);
2199         if (ret)
2200                 goto err_unpin;
2201
2202         i915_gem_object_pin_fence(obj);
2203
2204         dev_priv->mm.interruptible = true;
2205         return 0;
2206
2207 err_unpin:
2208         i915_gem_object_unpin_from_display_plane(obj);
2209 err_interruptible:
2210         dev_priv->mm.interruptible = true;
2211         return ret;
2212 }
2213
2214 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2215 {
2216         i915_gem_object_unpin_fence(obj);
2217         i915_gem_object_unpin_from_display_plane(obj);
2218 }
2219
2220 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2221  * is assumed to be a power-of-two. */
2222 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2223                                              unsigned int tiling_mode,
2224                                              unsigned int cpp,
2225                                              unsigned int pitch)
2226 {
2227         if (tiling_mode != I915_TILING_NONE) {
2228                 unsigned int tile_rows, tiles;
2229
2230                 tile_rows = *y / 8;
2231                 *y %= 8;
2232
2233                 tiles = *x / (512/cpp);
2234                 *x %= 512/cpp;
2235
2236                 return tile_rows * pitch * 8 + tiles * 4096;
2237         } else {
2238                 unsigned int offset;
2239
2240                 offset = *y * pitch + *x * cpp;
2241                 *y = 0;
2242                 *x = (offset & 4095) / cpp;
2243                 return offset & -4096;
2244         }
2245 }
2246
2247 int intel_format_to_fourcc(int format)
2248 {
2249         switch (format) {
2250         case DISPPLANE_8BPP:
2251                 return DRM_FORMAT_C8;
2252         case DISPPLANE_BGRX555:
2253                 return DRM_FORMAT_XRGB1555;
2254         case DISPPLANE_BGRX565:
2255                 return DRM_FORMAT_RGB565;
2256         default:
2257         case DISPPLANE_BGRX888:
2258                 return DRM_FORMAT_XRGB8888;
2259         case DISPPLANE_RGBX888:
2260                 return DRM_FORMAT_XBGR8888;
2261         case DISPPLANE_BGRX101010:
2262                 return DRM_FORMAT_XRGB2101010;
2263         case DISPPLANE_RGBX101010:
2264                 return DRM_FORMAT_XBGR2101010;
2265         }
2266 }
2267
2268 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2269                                   struct intel_plane_config *plane_config)
2270 {
2271         struct drm_device *dev = crtc->base.dev;
2272         struct drm_i915_gem_object *obj = NULL;
2273         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2274         u32 base = plane_config->base;
2275
2276         if (plane_config->size == 0)
2277                 return false;
2278
2279         obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2280                                                              plane_config->size);
2281         if (!obj)
2282                 return false;
2283
2284         if (plane_config->tiled) {
2285                 obj->tiling_mode = I915_TILING_X;
2286                 obj->stride = crtc->base.primary->fb->pitches[0];
2287         }
2288
2289         mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2290         mode_cmd.width = crtc->base.primary->fb->width;
2291         mode_cmd.height = crtc->base.primary->fb->height;
2292         mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2293
2294         mutex_lock(&dev->struct_mutex);
2295
2296         if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2297                                    &mode_cmd, obj)) {
2298                 DRM_DEBUG_KMS("intel fb init failed\n");
2299                 goto out_unref_obj;
2300         }
2301
2302         mutex_unlock(&dev->struct_mutex);
2303
2304         DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2305         return true;
2306
2307 out_unref_obj:
2308         drm_gem_object_unreference(&obj->base);
2309         mutex_unlock(&dev->struct_mutex);
2310         return false;
2311 }
2312
2313 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2314                                  struct intel_plane_config *plane_config)
2315 {
2316         struct drm_device *dev = intel_crtc->base.dev;
2317         struct drm_crtc *c;
2318         struct intel_crtc *i;
2319         struct intel_framebuffer *fb;
2320
2321         if (!intel_crtc->base.primary->fb)
2322                 return;
2323
2324         if (intel_alloc_plane_obj(intel_crtc, plane_config))
2325                 return;
2326
2327         kfree(intel_crtc->base.primary->fb);
2328         intel_crtc->base.primary->fb = NULL;
2329
2330         /*
2331          * Failed to alloc the obj, check to see if we should share
2332          * an fb with another CRTC instead
2333          */
2334         for_each_crtc(dev, c) {
2335                 i = to_intel_crtc(c);
2336
2337                 if (c == &intel_crtc->base)
2338                         continue;
2339
2340                 if (!i->active || !c->primary->fb)
2341                         continue;
2342
2343                 fb = to_intel_framebuffer(c->primary->fb);
2344                 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2345                         drm_framebuffer_reference(c->primary->fb);
2346                         intel_crtc->base.primary->fb = c->primary->fb;
2347                         break;
2348                 }
2349         }
2350 }
2351
2352 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2353                                       struct drm_framebuffer *fb,
2354                                       int x, int y)
2355 {
2356         struct drm_device *dev = crtc->dev;
2357         struct drm_i915_private *dev_priv = dev->dev_private;
2358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2359         struct intel_framebuffer *intel_fb;
2360         struct drm_i915_gem_object *obj;
2361         int plane = intel_crtc->plane;
2362         unsigned long linear_offset;
2363         u32 dspcntr;
2364         u32 reg;
2365
2366         intel_fb = to_intel_framebuffer(fb);
2367         obj = intel_fb->obj;
2368
2369         reg = DSPCNTR(plane);
2370         dspcntr = I915_READ(reg);
2371         /* Mask out pixel format bits in case we change it */
2372         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2373         switch (fb->pixel_format) {
2374         case DRM_FORMAT_C8:
2375                 dspcntr |= DISPPLANE_8BPP;
2376                 break;
2377         case DRM_FORMAT_XRGB1555:
2378         case DRM_FORMAT_ARGB1555:
2379                 dspcntr |= DISPPLANE_BGRX555;
2380                 break;
2381         case DRM_FORMAT_RGB565:
2382                 dspcntr |= DISPPLANE_BGRX565;
2383                 break;
2384         case DRM_FORMAT_XRGB8888:
2385         case DRM_FORMAT_ARGB8888:
2386                 dspcntr |= DISPPLANE_BGRX888;
2387                 break;
2388         case DRM_FORMAT_XBGR8888:
2389         case DRM_FORMAT_ABGR8888:
2390                 dspcntr |= DISPPLANE_RGBX888;
2391                 break;
2392         case DRM_FORMAT_XRGB2101010:
2393         case DRM_FORMAT_ARGB2101010:
2394                 dspcntr |= DISPPLANE_BGRX101010;
2395                 break;
2396         case DRM_FORMAT_XBGR2101010:
2397         case DRM_FORMAT_ABGR2101010:
2398                 dspcntr |= DISPPLANE_RGBX101010;
2399                 break;
2400         default:
2401                 BUG();
2402         }
2403
2404         if (INTEL_INFO(dev)->gen >= 4) {
2405                 if (obj->tiling_mode != I915_TILING_NONE)
2406                         dspcntr |= DISPPLANE_TILED;
2407                 else
2408                         dspcntr &= ~DISPPLANE_TILED;
2409         }
2410
2411         if (IS_G4X(dev))
2412                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2413
2414         I915_WRITE(reg, dspcntr);
2415
2416         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2417
2418         if (INTEL_INFO(dev)->gen >= 4) {
2419                 intel_crtc->dspaddr_offset =
2420                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2421                                                        fb->bits_per_pixel / 8,
2422                                                        fb->pitches[0]);
2423                 linear_offset -= intel_crtc->dspaddr_offset;
2424         } else {
2425                 intel_crtc->dspaddr_offset = linear_offset;
2426         }
2427
2428         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2429                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2430                       fb->pitches[0]);
2431         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2432         if (INTEL_INFO(dev)->gen >= 4) {
2433                 I915_WRITE(DSPSURF(plane),
2434                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2435                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2436                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2437         } else
2438                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2439         POSTING_READ(reg);
2440 }
2441
2442 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2443                                           struct drm_framebuffer *fb,
2444                                           int x, int y)
2445 {
2446         struct drm_device *dev = crtc->dev;
2447         struct drm_i915_private *dev_priv = dev->dev_private;
2448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2449         struct intel_framebuffer *intel_fb;
2450         struct drm_i915_gem_object *obj;
2451         int plane = intel_crtc->plane;
2452         unsigned long linear_offset;
2453         u32 dspcntr;
2454         u32 reg;
2455
2456         intel_fb = to_intel_framebuffer(fb);
2457         obj = intel_fb->obj;
2458
2459         reg = DSPCNTR(plane);
2460         dspcntr = I915_READ(reg);
2461         /* Mask out pixel format bits in case we change it */
2462         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2463         switch (fb->pixel_format) {
2464         case DRM_FORMAT_C8:
2465                 dspcntr |= DISPPLANE_8BPP;
2466                 break;
2467         case DRM_FORMAT_RGB565:
2468                 dspcntr |= DISPPLANE_BGRX565;
2469                 break;
2470         case DRM_FORMAT_XRGB8888:
2471         case DRM_FORMAT_ARGB8888:
2472                 dspcntr |= DISPPLANE_BGRX888;
2473                 break;
2474         case DRM_FORMAT_XBGR8888:
2475         case DRM_FORMAT_ABGR8888:
2476                 dspcntr |= DISPPLANE_RGBX888;
2477                 break;
2478         case DRM_FORMAT_XRGB2101010:
2479         case DRM_FORMAT_ARGB2101010:
2480                 dspcntr |= DISPPLANE_BGRX101010;
2481                 break;
2482         case DRM_FORMAT_XBGR2101010:
2483         case DRM_FORMAT_ABGR2101010:
2484                 dspcntr |= DISPPLANE_RGBX101010;
2485                 break;
2486         default:
2487                 BUG();
2488         }
2489
2490         if (obj->tiling_mode != I915_TILING_NONE)
2491                 dspcntr |= DISPPLANE_TILED;
2492         else
2493                 dspcntr &= ~DISPPLANE_TILED;
2494
2495         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2496                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2497         else
2498                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2499
2500         I915_WRITE(reg, dspcntr);
2501
2502         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2503         intel_crtc->dspaddr_offset =
2504                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2505                                                fb->bits_per_pixel / 8,
2506                                                fb->pitches[0]);
2507         linear_offset -= intel_crtc->dspaddr_offset;
2508
2509         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2510                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2511                       fb->pitches[0]);
2512         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2513         I915_WRITE(DSPSURF(plane),
2514                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2515         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2516                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2517         } else {
2518                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2519                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2520         }
2521         POSTING_READ(reg);
2522 }
2523
2524 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2525 static int
2526 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2527                            int x, int y, enum mode_set_atomic state)
2528 {
2529         struct drm_device *dev = crtc->dev;
2530         struct drm_i915_private *dev_priv = dev->dev_private;
2531
2532         if (dev_priv->display.disable_fbc)
2533                 dev_priv->display.disable_fbc(dev);
2534         intel_increase_pllclock(crtc);
2535
2536         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2537
2538         return 0;
2539 }
2540
2541 void intel_display_handle_reset(struct drm_device *dev)
2542 {
2543         struct drm_i915_private *dev_priv = dev->dev_private;
2544         struct drm_crtc *crtc;
2545
2546         /*
2547          * Flips in the rings have been nuked by the reset,
2548          * so complete all pending flips so that user space
2549          * will get its events and not get stuck.
2550          *
2551          * Also update the base address of all primary
2552          * planes to the the last fb to make sure we're
2553          * showing the correct fb after a reset.
2554          *
2555          * Need to make two loops over the crtcs so that we
2556          * don't try to grab a crtc mutex before the
2557          * pending_flip_queue really got woken up.
2558          */
2559
2560         for_each_crtc(dev, crtc) {
2561                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2562                 enum plane plane = intel_crtc->plane;
2563
2564                 intel_prepare_page_flip(dev, plane);
2565                 intel_finish_page_flip_plane(dev, plane);
2566         }
2567
2568         for_each_crtc(dev, crtc) {
2569                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570
2571                 mutex_lock(&crtc->mutex);
2572                 /*
2573                  * FIXME: Once we have proper support for primary planes (and
2574                  * disabling them without disabling the entire crtc) allow again
2575                  * a NULL crtc->primary->fb.
2576                  */
2577                 if (intel_crtc->active && crtc->primary->fb)
2578                         dev_priv->display.update_primary_plane(crtc,
2579                                                                crtc->primary->fb,
2580                                                                crtc->x,
2581                                                                crtc->y);
2582                 mutex_unlock(&crtc->mutex);
2583         }
2584 }
2585
2586 static int
2587 intel_finish_fb(struct drm_framebuffer *old_fb)
2588 {
2589         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2590         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2591         bool was_interruptible = dev_priv->mm.interruptible;
2592         int ret;
2593
2594         /* Big Hammer, we also need to ensure that any pending
2595          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2596          * current scanout is retired before unpinning the old
2597          * framebuffer.
2598          *
2599          * This should only fail upon a hung GPU, in which case we
2600          * can safely continue.
2601          */
2602         dev_priv->mm.interruptible = false;
2603         ret = i915_gem_object_finish_gpu(obj);
2604         dev_priv->mm.interruptible = was_interruptible;
2605
2606         return ret;
2607 }
2608
2609 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2610 {
2611         struct drm_device *dev = crtc->dev;
2612         struct drm_i915_private *dev_priv = dev->dev_private;
2613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614         unsigned long flags;
2615         bool pending;
2616
2617         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2618             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2619                 return false;
2620
2621         spin_lock_irqsave(&dev->event_lock, flags);
2622         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2623         spin_unlock_irqrestore(&dev->event_lock, flags);
2624
2625         return pending;
2626 }
2627
2628 static int
2629 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2630                     struct drm_framebuffer *fb)
2631 {
2632         struct drm_device *dev = crtc->dev;
2633         struct drm_i915_private *dev_priv = dev->dev_private;
2634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635         struct drm_framebuffer *old_fb;
2636         int ret;
2637
2638         if (intel_crtc_has_pending_flip(crtc)) {
2639                 DRM_ERROR("pipe is still busy with an old pageflip\n");
2640                 return -EBUSY;
2641         }
2642
2643         /* no fb bound */
2644         if (!fb) {
2645                 DRM_ERROR("No FB bound\n");
2646                 return 0;
2647         }
2648
2649         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2650                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2651                           plane_name(intel_crtc->plane),
2652                           INTEL_INFO(dev)->num_pipes);
2653                 return -EINVAL;
2654         }
2655
2656         mutex_lock(&dev->struct_mutex);
2657         ret = intel_pin_and_fence_fb_obj(dev,
2658                                          to_intel_framebuffer(fb)->obj,
2659                                          NULL);
2660         mutex_unlock(&dev->struct_mutex);
2661         if (ret != 0) {
2662                 DRM_ERROR("pin & fence failed\n");
2663                 return ret;
2664         }
2665
2666         /*
2667          * Update pipe size and adjust fitter if needed: the reason for this is
2668          * that in compute_mode_changes we check the native mode (not the pfit
2669          * mode) to see if we can flip rather than do a full mode set. In the
2670          * fastboot case, we'll flip, but if we don't update the pipesrc and
2671          * pfit state, we'll end up with a big fb scanned out into the wrong
2672          * sized surface.
2673          *
2674          * To fix this properly, we need to hoist the checks up into
2675          * compute_mode_changes (or above), check the actual pfit state and
2676          * whether the platform allows pfit disable with pipe active, and only
2677          * then update the pipesrc and pfit state, even on the flip path.
2678          */
2679         if (i915.fastboot) {
2680                 const struct drm_display_mode *adjusted_mode =
2681                         &intel_crtc->config.adjusted_mode;
2682
2683                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2684                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2685                            (adjusted_mode->crtc_vdisplay - 1));
2686                 if (!intel_crtc->config.pch_pfit.enabled &&
2687                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2688                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2689                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2690                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2691                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2692                 }
2693                 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2694                 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2695         }
2696
2697         dev_priv->display.update_primary_plane(crtc, fb, x, y);
2698
2699         old_fb = crtc->primary->fb;
2700         crtc->primary->fb = fb;
2701         crtc->x = x;
2702         crtc->y = y;
2703
2704         if (old_fb) {
2705                 if (intel_crtc->active && old_fb != fb)
2706                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2707                 mutex_lock(&dev->struct_mutex);
2708                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2709                 mutex_unlock(&dev->struct_mutex);
2710         }
2711
2712         mutex_lock(&dev->struct_mutex);
2713         intel_update_fbc(dev);
2714         intel_edp_psr_update(dev);
2715         mutex_unlock(&dev->struct_mutex);
2716
2717         return 0;
2718 }
2719
2720 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2721 {
2722         struct drm_device *dev = crtc->dev;
2723         struct drm_i915_private *dev_priv = dev->dev_private;
2724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* enable normal train */
2729         reg = FDI_TX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         if (IS_IVYBRIDGE(dev)) {
2732                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2733                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2734         } else {
2735                 temp &= ~FDI_LINK_TRAIN_NONE;
2736                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2737         }
2738         I915_WRITE(reg, temp);
2739
2740         reg = FDI_RX_CTL(pipe);
2741         temp = I915_READ(reg);
2742         if (HAS_PCH_CPT(dev)) {
2743                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2744                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2745         } else {
2746                 temp &= ~FDI_LINK_TRAIN_NONE;
2747                 temp |= FDI_LINK_TRAIN_NONE;
2748         }
2749         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2750
2751         /* wait one idle pattern time */
2752         POSTING_READ(reg);
2753         udelay(1000);
2754
2755         /* IVB wants error correction enabled */
2756         if (IS_IVYBRIDGE(dev))
2757                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2758                            FDI_FE_ERRC_ENABLE);
2759 }
2760
2761 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2762 {
2763         return crtc->base.enabled && crtc->active &&
2764                 crtc->config.has_pch_encoder;
2765 }
2766
2767 static void ivb_modeset_global_resources(struct drm_device *dev)
2768 {
2769         struct drm_i915_private *dev_priv = dev->dev_private;
2770         struct intel_crtc *pipe_B_crtc =
2771                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2772         struct intel_crtc *pipe_C_crtc =
2773                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2774         uint32_t temp;
2775
2776         /*
2777          * When everything is off disable fdi C so that we could enable fdi B
2778          * with all lanes. Note that we don't care about enabled pipes without
2779          * an enabled pch encoder.
2780          */
2781         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2782             !pipe_has_enabled_pch(pipe_C_crtc)) {
2783                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2784                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2785
2786                 temp = I915_READ(SOUTH_CHICKEN1);
2787                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2788                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2789                 I915_WRITE(SOUTH_CHICKEN1, temp);
2790         }
2791 }
2792
2793 /* The FDI link training functions for ILK/Ibexpeak. */
2794 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2795 {
2796         struct drm_device *dev = crtc->dev;
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799         int pipe = intel_crtc->pipe;
2800         u32 reg, temp, tries;
2801
2802         /* FDI needs bits from pipe first */
2803         assert_pipe_enabled(dev_priv, pipe);
2804
2805         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2806            for train result */
2807         reg = FDI_RX_IMR(pipe);
2808         temp = I915_READ(reg);
2809         temp &= ~FDI_RX_SYMBOL_LOCK;
2810         temp &= ~FDI_RX_BIT_LOCK;
2811         I915_WRITE(reg, temp);
2812         I915_READ(reg);
2813         udelay(150);
2814
2815         /* enable CPU FDI TX and PCH FDI RX */
2816         reg = FDI_TX_CTL(pipe);
2817         temp = I915_READ(reg);
2818         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2819         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2820         temp &= ~FDI_LINK_TRAIN_NONE;
2821         temp |= FDI_LINK_TRAIN_PATTERN_1;
2822         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2823
2824         reg = FDI_RX_CTL(pipe);
2825         temp = I915_READ(reg);
2826         temp &= ~FDI_LINK_TRAIN_NONE;
2827         temp |= FDI_LINK_TRAIN_PATTERN_1;
2828         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2829
2830         POSTING_READ(reg);
2831         udelay(150);
2832
2833         /* Ironlake workaround, enable clock pointer after FDI enable*/
2834         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2835         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2836                    FDI_RX_PHASE_SYNC_POINTER_EN);
2837
2838         reg = FDI_RX_IIR(pipe);
2839         for (tries = 0; tries < 5; tries++) {
2840                 temp = I915_READ(reg);
2841                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2842
2843                 if ((temp & FDI_RX_BIT_LOCK)) {
2844                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2845                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2846                         break;
2847                 }
2848         }
2849         if (tries == 5)
2850                 DRM_ERROR("FDI train 1 fail!\n");
2851
2852         /* Train 2 */
2853         reg = FDI_TX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         temp &= ~FDI_LINK_TRAIN_NONE;
2856         temp |= FDI_LINK_TRAIN_PATTERN_2;
2857         I915_WRITE(reg, temp);
2858
2859         reg = FDI_RX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         temp &= ~FDI_LINK_TRAIN_NONE;
2862         temp |= FDI_LINK_TRAIN_PATTERN_2;
2863         I915_WRITE(reg, temp);
2864
2865         POSTING_READ(reg);
2866         udelay(150);
2867
2868         reg = FDI_RX_IIR(pipe);
2869         for (tries = 0; tries < 5; tries++) {
2870                 temp = I915_READ(reg);
2871                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2872
2873                 if (temp & FDI_RX_SYMBOL_LOCK) {
2874                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2875                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2876                         break;
2877                 }
2878         }
2879         if (tries == 5)
2880                 DRM_ERROR("FDI train 2 fail!\n");
2881
2882         DRM_DEBUG_KMS("FDI train done\n");
2883
2884 }
2885
2886 static const int snb_b_fdi_train_param[] = {
2887         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2888         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2889         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2890         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2891 };
2892
2893 /* The FDI link training functions for SNB/Cougarpoint. */
2894 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2895 {
2896         struct drm_device *dev = crtc->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2899         int pipe = intel_crtc->pipe;
2900         u32 reg, temp, i, retry;
2901
2902         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2903            for train result */
2904         reg = FDI_RX_IMR(pipe);
2905         temp = I915_READ(reg);
2906         temp &= ~FDI_RX_SYMBOL_LOCK;
2907         temp &= ~FDI_RX_BIT_LOCK;
2908         I915_WRITE(reg, temp);
2909
2910         POSTING_READ(reg);
2911         udelay(150);
2912
2913         /* enable CPU FDI TX and PCH FDI RX */
2914         reg = FDI_TX_CTL(pipe);
2915         temp = I915_READ(reg);
2916         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2917         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2918         temp &= ~FDI_LINK_TRAIN_NONE;
2919         temp |= FDI_LINK_TRAIN_PATTERN_1;
2920         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2921         /* SNB-B */
2922         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2923         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2924
2925         I915_WRITE(FDI_RX_MISC(pipe),
2926                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2927
2928         reg = FDI_RX_CTL(pipe);
2929         temp = I915_READ(reg);
2930         if (HAS_PCH_CPT(dev)) {
2931                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2932                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2933         } else {
2934                 temp &= ~FDI_LINK_TRAIN_NONE;
2935                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2936         }
2937         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2938
2939         POSTING_READ(reg);
2940         udelay(150);
2941
2942         for (i = 0; i < 4; i++) {
2943                 reg = FDI_TX_CTL(pipe);
2944                 temp = I915_READ(reg);
2945                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2946                 temp |= snb_b_fdi_train_param[i];
2947                 I915_WRITE(reg, temp);
2948
2949                 POSTING_READ(reg);
2950                 udelay(500);
2951
2952                 for (retry = 0; retry < 5; retry++) {
2953                         reg = FDI_RX_IIR(pipe);
2954                         temp = I915_READ(reg);
2955                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2956                         if (temp & FDI_RX_BIT_LOCK) {
2957                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2958                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2959                                 break;
2960                         }
2961                         udelay(50);
2962                 }
2963                 if (retry < 5)
2964                         break;
2965         }
2966         if (i == 4)
2967                 DRM_ERROR("FDI train 1 fail!\n");
2968
2969         /* Train 2 */
2970         reg = FDI_TX_CTL(pipe);
2971         temp = I915_READ(reg);
2972         temp &= ~FDI_LINK_TRAIN_NONE;
2973         temp |= FDI_LINK_TRAIN_PATTERN_2;
2974         if (IS_GEN6(dev)) {
2975                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2976                 /* SNB-B */
2977                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2978         }
2979         I915_WRITE(reg, temp);
2980
2981         reg = FDI_RX_CTL(pipe);
2982         temp = I915_READ(reg);
2983         if (HAS_PCH_CPT(dev)) {
2984                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2985                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2986         } else {
2987                 temp &= ~FDI_LINK_TRAIN_NONE;
2988                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2989         }
2990         I915_WRITE(reg, temp);
2991
2992         POSTING_READ(reg);
2993         udelay(150);
2994
2995         for (i = 0; i < 4; i++) {
2996                 reg = FDI_TX_CTL(pipe);
2997                 temp = I915_READ(reg);
2998                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2999                 temp |= snb_b_fdi_train_param[i];
3000                 I915_WRITE(reg, temp);
3001
3002                 POSTING_READ(reg);
3003                 udelay(500);
3004
3005                 for (retry = 0; retry < 5; retry++) {
3006                         reg = FDI_RX_IIR(pipe);
3007                         temp = I915_READ(reg);
3008                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3009                         if (temp & FDI_RX_SYMBOL_LOCK) {
3010                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3011                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3012                                 break;
3013                         }
3014                         udelay(50);
3015                 }
3016                 if (retry < 5)
3017                         break;
3018         }
3019         if (i == 4)
3020                 DRM_ERROR("FDI train 2 fail!\n");
3021
3022         DRM_DEBUG_KMS("FDI train done.\n");
3023 }
3024
3025 /* Manual link training for Ivy Bridge A0 parts */
3026 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3027 {
3028         struct drm_device *dev = crtc->dev;
3029         struct drm_i915_private *dev_priv = dev->dev_private;
3030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031         int pipe = intel_crtc->pipe;
3032         u32 reg, temp, i, j;
3033
3034         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3035            for train result */
3036         reg = FDI_RX_IMR(pipe);
3037         temp = I915_READ(reg);
3038         temp &= ~FDI_RX_SYMBOL_LOCK;
3039         temp &= ~FDI_RX_BIT_LOCK;
3040         I915_WRITE(reg, temp);
3041
3042         POSTING_READ(reg);
3043         udelay(150);
3044
3045         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3046                       I915_READ(FDI_RX_IIR(pipe)));
3047
3048         /* Try each vswing and preemphasis setting twice before moving on */
3049         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3050                 /* disable first in case we need to retry */
3051                 reg = FDI_TX_CTL(pipe);
3052                 temp = I915_READ(reg);
3053                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3054                 temp &= ~FDI_TX_ENABLE;
3055                 I915_WRITE(reg, temp);
3056
3057                 reg = FDI_RX_CTL(pipe);
3058                 temp = I915_READ(reg);
3059                 temp &= ~FDI_LINK_TRAIN_AUTO;
3060                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3061                 temp &= ~FDI_RX_ENABLE;
3062                 I915_WRITE(reg, temp);
3063
3064                 /* enable CPU FDI TX and PCH FDI RX */
3065                 reg = FDI_TX_CTL(pipe);
3066                 temp = I915_READ(reg);
3067                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3068                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3069                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3070                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3071                 temp |= snb_b_fdi_train_param[j/2];
3072                 temp |= FDI_COMPOSITE_SYNC;
3073                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3074
3075                 I915_WRITE(FDI_RX_MISC(pipe),
3076                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3077
3078                 reg = FDI_RX_CTL(pipe);
3079                 temp = I915_READ(reg);
3080                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3081                 temp |= FDI_COMPOSITE_SYNC;
3082                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3083
3084                 POSTING_READ(reg);
3085                 udelay(1); /* should be 0.5us */
3086
3087                 for (i = 0; i < 4; i++) {
3088                         reg = FDI_RX_IIR(pipe);
3089                         temp = I915_READ(reg);
3090                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3091
3092                         if (temp & FDI_RX_BIT_LOCK ||
3093                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3094                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3095                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3096                                               i);
3097                                 break;
3098                         }
3099                         udelay(1); /* should be 0.5us */
3100                 }
3101                 if (i == 4) {
3102                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3103                         continue;
3104                 }
3105
3106                 /* Train 2 */
3107                 reg = FDI_TX_CTL(pipe);
3108                 temp = I915_READ(reg);
3109                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3110                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3111                 I915_WRITE(reg, temp);
3112
3113                 reg = FDI_RX_CTL(pipe);
3114                 temp = I915_READ(reg);
3115                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3116                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3117                 I915_WRITE(reg, temp);
3118
3119                 POSTING_READ(reg);
3120                 udelay(2); /* should be 1.5us */
3121
3122                 for (i = 0; i < 4; i++) {
3123                         reg = FDI_RX_IIR(pipe);
3124                         temp = I915_READ(reg);
3125                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3126
3127                         if (temp & FDI_RX_SYMBOL_LOCK ||
3128                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3129                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3130                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3131                                               i);
3132                                 goto train_done;
3133                         }
3134                         udelay(2); /* should be 1.5us */
3135                 }
3136                 if (i == 4)
3137                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3138         }
3139
3140 train_done:
3141         DRM_DEBUG_KMS("FDI train done.\n");
3142 }
3143
3144 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3145 {
3146         struct drm_device *dev = intel_crtc->base.dev;
3147         struct drm_i915_private *dev_priv = dev->dev_private;
3148         int pipe = intel_crtc->pipe;
3149         u32 reg, temp;
3150
3151
3152         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3153         reg = FDI_RX_CTL(pipe);
3154         temp = I915_READ(reg);
3155         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3156         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3157         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3158         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3159
3160         POSTING_READ(reg);
3161         udelay(200);
3162
3163         /* Switch from Rawclk to PCDclk */
3164         temp = I915_READ(reg);
3165         I915_WRITE(reg, temp | FDI_PCDCLK);
3166
3167         POSTING_READ(reg);
3168         udelay(200);
3169
3170         /* Enable CPU FDI TX PLL, always on for Ironlake */
3171         reg = FDI_TX_CTL(pipe);
3172         temp = I915_READ(reg);
3173         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3174                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3175
3176                 POSTING_READ(reg);
3177                 udelay(100);
3178         }
3179 }
3180
3181 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3182 {
3183         struct drm_device *dev = intel_crtc->base.dev;
3184         struct drm_i915_private *dev_priv = dev->dev_private;
3185         int pipe = intel_crtc->pipe;
3186         u32 reg, temp;
3187
3188         /* Switch from PCDclk to Rawclk */
3189         reg = FDI_RX_CTL(pipe);
3190         temp = I915_READ(reg);
3191         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3192
3193         /* Disable CPU FDI TX PLL */
3194         reg = FDI_TX_CTL(pipe);
3195         temp = I915_READ(reg);
3196         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3197
3198         POSTING_READ(reg);
3199         udelay(100);
3200
3201         reg = FDI_RX_CTL(pipe);
3202         temp = I915_READ(reg);
3203         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3204
3205         /* Wait for the clocks to turn off. */
3206         POSTING_READ(reg);
3207         udelay(100);
3208 }
3209
3210 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3211 {
3212         struct drm_device *dev = crtc->dev;
3213         struct drm_i915_private *dev_priv = dev->dev_private;
3214         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215         int pipe = intel_crtc->pipe;
3216         u32 reg, temp;
3217
3218         /* disable CPU FDI tx and PCH FDI rx */
3219         reg = FDI_TX_CTL(pipe);
3220         temp = I915_READ(reg);
3221         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3222         POSTING_READ(reg);
3223
3224         reg = FDI_RX_CTL(pipe);
3225         temp = I915_READ(reg);
3226         temp &= ~(0x7 << 16);
3227         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3228         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3229
3230         POSTING_READ(reg);
3231         udelay(100);
3232
3233         /* Ironlake workaround, disable clock pointer after downing FDI */
3234         if (HAS_PCH_IBX(dev))
3235                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3236
3237         /* still set train pattern 1 */
3238         reg = FDI_TX_CTL(pipe);
3239         temp = I915_READ(reg);
3240         temp &= ~FDI_LINK_TRAIN_NONE;
3241         temp |= FDI_LINK_TRAIN_PATTERN_1;
3242         I915_WRITE(reg, temp);
3243
3244         reg = FDI_RX_CTL(pipe);
3245         temp = I915_READ(reg);
3246         if (HAS_PCH_CPT(dev)) {
3247                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3248                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3249         } else {
3250                 temp &= ~FDI_LINK_TRAIN_NONE;
3251                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3252         }
3253         /* BPC in FDI rx is consistent with that in PIPECONF */
3254         temp &= ~(0x07 << 16);
3255         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3256         I915_WRITE(reg, temp);
3257
3258         POSTING_READ(reg);
3259         udelay(100);
3260 }
3261
3262 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3263 {
3264         struct intel_crtc *crtc;
3265
3266         /* Note that we don't need to be called with mode_config.lock here
3267          * as our list of CRTC objects is static for the lifetime of the
3268          * device and so cannot disappear as we iterate. Similarly, we can
3269          * happily treat the predicates as racy, atomic checks as userspace
3270          * cannot claim and pin a new fb without at least acquring the
3271          * struct_mutex and so serialising with us.
3272          */
3273         for_each_intel_crtc(dev, crtc) {
3274                 if (atomic_read(&crtc->unpin_work_count) == 0)
3275                         continue;
3276
3277                 if (crtc->unpin_work)
3278                         intel_wait_for_vblank(dev, crtc->pipe);
3279
3280                 return true;
3281         }
3282
3283         return false;
3284 }
3285
3286 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3287 {
3288         struct drm_device *dev = crtc->dev;
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290
3291         if (crtc->primary->fb == NULL)
3292                 return;
3293
3294         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3295
3296         WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3297                                    !intel_crtc_has_pending_flip(crtc),
3298                                    60*HZ) == 0);
3299
3300         mutex_lock(&dev->struct_mutex);
3301         intel_finish_fb(crtc->primary->fb);
3302         mutex_unlock(&dev->struct_mutex);
3303 }
3304
3305 /* Program iCLKIP clock to the desired frequency */
3306 static void lpt_program_iclkip(struct drm_crtc *crtc)
3307 {
3308         struct drm_device *dev = crtc->dev;
3309         struct drm_i915_private *dev_priv = dev->dev_private;
3310         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3311         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3312         u32 temp;
3313
3314         mutex_lock(&dev_priv->dpio_lock);
3315
3316         /* It is necessary to ungate the pixclk gate prior to programming
3317          * the divisors, and gate it back when it is done.
3318          */
3319         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3320
3321         /* Disable SSCCTL */
3322         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3323                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3324                                 SBI_SSCCTL_DISABLE,
3325                         SBI_ICLK);
3326
3327         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3328         if (clock == 20000) {
3329                 auxdiv = 1;
3330                 divsel = 0x41;
3331                 phaseinc = 0x20;
3332         } else {
3333                 /* The iCLK virtual clock root frequency is in MHz,
3334                  * but the adjusted_mode->crtc_clock in in KHz. To get the
3335                  * divisors, it is necessary to divide one by another, so we
3336                  * convert the virtual clock precision to KHz here for higher
3337                  * precision.
3338                  */
3339                 u32 iclk_virtual_root_freq = 172800 * 1000;
3340                 u32 iclk_pi_range = 64;
3341                 u32 desired_divisor, msb_divisor_value, pi_value;
3342
3343                 desired_divisor = (iclk_virtual_root_freq / clock);
3344                 msb_divisor_value = desired_divisor / iclk_pi_range;
3345                 pi_value = desired_divisor % iclk_pi_range;
3346
3347                 auxdiv = 0;
3348                 divsel = msb_divisor_value - 2;
3349                 phaseinc = pi_value;
3350         }
3351
3352         /* This should not happen with any sane values */
3353         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3354                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3355         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3356                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3357
3358         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3359                         clock,
3360                         auxdiv,
3361                         divsel,
3362                         phasedir,
3363                         phaseinc);
3364
3365         /* Program SSCDIVINTPHASE6 */
3366         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3367         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3368         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3369         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3370         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3371         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3372         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3373         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3374
3375         /* Program SSCAUXDIV */
3376         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3377         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3378         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3379         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3380
3381         /* Enable modulator and associated divider */
3382         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3383         temp &= ~SBI_SSCCTL_DISABLE;
3384         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3385
3386         /* Wait for initialization time */
3387         udelay(24);
3388
3389         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3390
3391         mutex_unlock(&dev_priv->dpio_lock);
3392 }
3393
3394 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3395                                                 enum pipe pch_transcoder)
3396 {
3397         struct drm_device *dev = crtc->base.dev;
3398         struct drm_i915_private *dev_priv = dev->dev_private;
3399         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3400
3401         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3402                    I915_READ(HTOTAL(cpu_transcoder)));
3403         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3404                    I915_READ(HBLANK(cpu_transcoder)));
3405         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3406                    I915_READ(HSYNC(cpu_transcoder)));
3407
3408         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3409                    I915_READ(VTOTAL(cpu_transcoder)));
3410         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3411                    I915_READ(VBLANK(cpu_transcoder)));
3412         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3413                    I915_READ(VSYNC(cpu_transcoder)));
3414         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3415                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3416 }
3417
3418 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3419 {
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         uint32_t temp;
3422
3423         temp = I915_READ(SOUTH_CHICKEN1);
3424         if (temp & FDI_BC_BIFURCATION_SELECT)
3425                 return;
3426
3427         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3428         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3429
3430         temp |= FDI_BC_BIFURCATION_SELECT;
3431         DRM_DEBUG_KMS("enabling fdi C rx\n");
3432         I915_WRITE(SOUTH_CHICKEN1, temp);
3433         POSTING_READ(SOUTH_CHICKEN1);
3434 }
3435
3436 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3437 {
3438         struct drm_device *dev = intel_crtc->base.dev;
3439         struct drm_i915_private *dev_priv = dev->dev_private;
3440
3441         switch (intel_crtc->pipe) {
3442         case PIPE_A:
3443                 break;
3444         case PIPE_B:
3445                 if (intel_crtc->config.fdi_lanes > 2)
3446                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3447                 else
3448                         cpt_enable_fdi_bc_bifurcation(dev);
3449
3450                 break;
3451         case PIPE_C:
3452                 cpt_enable_fdi_bc_bifurcation(dev);
3453
3454                 break;
3455         default:
3456                 BUG();
3457         }
3458 }
3459
3460 /*
3461  * Enable PCH resources required for PCH ports:
3462  *   - PCH PLLs
3463  *   - FDI training & RX/TX
3464  *   - update transcoder timings
3465  *   - DP transcoding bits
3466  *   - transcoder
3467  */
3468 static void ironlake_pch_enable(struct drm_crtc *crtc)
3469 {
3470         struct drm_device *dev = crtc->dev;
3471         struct drm_i915_private *dev_priv = dev->dev_private;
3472         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3473         int pipe = intel_crtc->pipe;
3474         u32 reg, temp;
3475
3476         assert_pch_transcoder_disabled(dev_priv, pipe);
3477
3478         if (IS_IVYBRIDGE(dev))
3479                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3480
3481         /* Write the TU size bits before fdi link training, so that error
3482          * detection works. */
3483         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3484                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3485
3486         /* For PCH output, training FDI link */
3487         dev_priv->display.fdi_link_train(crtc);
3488
3489         /* We need to program the right clock selection before writing the pixel
3490          * mutliplier into the DPLL. */
3491         if (HAS_PCH_CPT(dev)) {
3492                 u32 sel;
3493
3494                 temp = I915_READ(PCH_DPLL_SEL);
3495                 temp |= TRANS_DPLL_ENABLE(pipe);
3496                 sel = TRANS_DPLLB_SEL(pipe);
3497                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3498                         temp |= sel;
3499                 else
3500                         temp &= ~sel;
3501                 I915_WRITE(PCH_DPLL_SEL, temp);
3502         }
3503
3504         /* XXX: pch pll's can be enabled any time before we enable the PCH
3505          * transcoder, and we actually should do this to not upset any PCH
3506          * transcoder that already use the clock when we share it.
3507          *
3508          * Note that enable_shared_dpll tries to do the right thing, but
3509          * get_shared_dpll unconditionally resets the pll - we need that to have
3510          * the right LVDS enable sequence. */
3511         intel_enable_shared_dpll(intel_crtc);
3512
3513         /* set transcoder timing, panel must allow it */
3514         assert_panel_unlocked(dev_priv, pipe);
3515         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3516
3517         intel_fdi_normal_train(crtc);
3518
3519         /* For PCH DP, enable TRANS_DP_CTL */
3520         if (HAS_PCH_CPT(dev) &&
3521             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3522              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3523                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3524                 reg = TRANS_DP_CTL(pipe);
3525                 temp = I915_READ(reg);
3526                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3527                           TRANS_DP_SYNC_MASK |
3528                           TRANS_DP_BPC_MASK);
3529                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3530                          TRANS_DP_ENH_FRAMING);
3531                 temp |= bpc << 9; /* same format but at 11:9 */
3532
3533                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3534                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3535                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3536                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3537
3538                 switch (intel_trans_dp_port_sel(crtc)) {
3539                 case PCH_DP_B:
3540                         temp |= TRANS_DP_PORT_SEL_B;
3541                         break;
3542                 case PCH_DP_C:
3543                         temp |= TRANS_DP_PORT_SEL_C;
3544                         break;
3545                 case PCH_DP_D:
3546                         temp |= TRANS_DP_PORT_SEL_D;
3547                         break;
3548                 default:
3549                         BUG();
3550                 }
3551
3552                 I915_WRITE(reg, temp);
3553         }
3554
3555         ironlake_enable_pch_transcoder(dev_priv, pipe);
3556 }
3557
3558 static void lpt_pch_enable(struct drm_crtc *crtc)
3559 {
3560         struct drm_device *dev = crtc->dev;
3561         struct drm_i915_private *dev_priv = dev->dev_private;
3562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3564
3565         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3566
3567         lpt_program_iclkip(crtc);
3568
3569         /* Set transcoder timing. */
3570         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3571
3572         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3573 }
3574
3575 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3576 {
3577         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3578
3579         if (pll == NULL)
3580                 return;
3581
3582         if (pll->refcount == 0) {
3583                 WARN(1, "bad %s refcount\n", pll->name);
3584                 return;
3585         }
3586
3587         if (--pll->refcount == 0) {
3588                 WARN_ON(pll->on);
3589                 WARN_ON(pll->active);
3590         }
3591
3592         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3593 }
3594
3595 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3596 {
3597         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3598         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3599         enum intel_dpll_id i;
3600
3601         if (pll) {
3602                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3603                               crtc->base.base.id, pll->name);
3604                 intel_put_shared_dpll(crtc);
3605         }
3606
3607         if (HAS_PCH_IBX(dev_priv->dev)) {
3608                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3609                 i = (enum intel_dpll_id) crtc->pipe;
3610                 pll = &dev_priv->shared_dplls[i];
3611
3612                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3613                               crtc->base.base.id, pll->name);
3614
3615                 WARN_ON(pll->refcount);
3616
3617                 goto found;
3618         }
3619
3620         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3621                 pll = &dev_priv->shared_dplls[i];
3622
3623                 /* Only want to check enabled timings first */
3624                 if (pll->refcount == 0)
3625                         continue;
3626
3627                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3628                            sizeof(pll->hw_state)) == 0) {
3629                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3630                                       crtc->base.base.id,
3631                                       pll->name, pll->refcount, pll->active);
3632
3633                         goto found;
3634                 }
3635         }
3636
3637         /* Ok no matching timings, maybe there's a free one? */
3638         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3639                 pll = &dev_priv->shared_dplls[i];
3640                 if (pll->refcount == 0) {
3641                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3642                                       crtc->base.base.id, pll->name);
3643                         goto found;
3644                 }
3645         }
3646
3647         return NULL;
3648
3649 found:
3650         if (pll->refcount == 0)
3651                 pll->hw_state = crtc->config.dpll_hw_state;
3652
3653         crtc->config.shared_dpll = i;
3654         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3655                          pipe_name(crtc->pipe));
3656
3657         pll->refcount++;
3658
3659         return pll;
3660 }
3661
3662 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3663 {
3664         struct drm_i915_private *dev_priv = dev->dev_private;
3665         int dslreg = PIPEDSL(pipe);
3666         u32 temp;
3667
3668         temp = I915_READ(dslreg);
3669         udelay(500);
3670         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3671                 if (wait_for(I915_READ(dslreg) != temp, 5))
3672                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3673         }
3674 }
3675
3676 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3677 {
3678         struct drm_device *dev = crtc->base.dev;
3679         struct drm_i915_private *dev_priv = dev->dev_private;
3680         int pipe = crtc->pipe;
3681
3682         if (crtc->config.pch_pfit.enabled) {
3683                 /* Force use of hard-coded filter coefficients
3684                  * as some pre-programmed values are broken,
3685                  * e.g. x201.
3686                  */
3687                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3688                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3689                                                  PF_PIPE_SEL_IVB(pipe));
3690                 else
3691                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3692                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3693                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3694         }
3695 }
3696
3697 static void intel_enable_planes(struct drm_crtc *crtc)
3698 {
3699         struct drm_device *dev = crtc->dev;
3700         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3701         struct drm_plane *plane;
3702         struct intel_plane *intel_plane;
3703
3704         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3705                 intel_plane = to_intel_plane(plane);
3706                 if (intel_plane->pipe == pipe)
3707                         intel_plane_restore(&intel_plane->base);
3708         }
3709 }
3710
3711 static void intel_disable_planes(struct drm_crtc *crtc)
3712 {
3713         struct drm_device *dev = crtc->dev;
3714         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3715         struct drm_plane *plane;
3716         struct intel_plane *intel_plane;
3717
3718         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3719                 intel_plane = to_intel_plane(plane);
3720                 if (intel_plane->pipe == pipe)
3721                         intel_plane_disable(&intel_plane->base);
3722         }
3723 }
3724
3725 void hsw_enable_ips(struct intel_crtc *crtc)
3726 {
3727         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3728
3729         if (!crtc->config.ips_enabled)
3730                 return;
3731
3732         /* We can only enable IPS after we enable a plane and wait for a vblank.
3733          * We guarantee that the plane is enabled by calling intel_enable_ips
3734          * only after intel_enable_plane. And intel_enable_plane already waits
3735          * for a vblank, so all we need to do here is to enable the IPS bit. */
3736         assert_plane_enabled(dev_priv, crtc->plane);
3737         if (IS_BROADWELL(crtc->base.dev)) {
3738                 mutex_lock(&dev_priv->rps.hw_lock);
3739                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3740                 mutex_unlock(&dev_priv->rps.hw_lock);
3741                 /* Quoting Art Runyan: "its not safe to expect any particular
3742                  * value in IPS_CTL bit 31 after enabling IPS through the
3743                  * mailbox." Moreover, the mailbox may return a bogus state,
3744                  * so we need to just enable it and continue on.
3745                  */
3746         } else {
3747                 I915_WRITE(IPS_CTL, IPS_ENABLE);
3748                 /* The bit only becomes 1 in the next vblank, so this wait here
3749                  * is essentially intel_wait_for_vblank. If we don't have this
3750                  * and don't wait for vblanks until the end of crtc_enable, then
3751                  * the HW state readout code will complain that the expected
3752                  * IPS_CTL value is not the one we read. */
3753                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3754                         DRM_ERROR("Timed out waiting for IPS enable\n");
3755         }
3756 }
3757
3758 void hsw_disable_ips(struct intel_crtc *crtc)
3759 {
3760         struct drm_device *dev = crtc->base.dev;
3761         struct drm_i915_private *dev_priv = dev->dev_private;
3762
3763         if (!crtc->config.ips_enabled)
3764                 return;
3765
3766         assert_plane_enabled(dev_priv, crtc->plane);
3767         if (IS_BROADWELL(dev)) {
3768                 mutex_lock(&dev_priv->rps.hw_lock);
3769                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3770                 mutex_unlock(&dev_priv->rps.hw_lock);
3771                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3772                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3773                         DRM_ERROR("Timed out waiting for IPS disable\n");
3774         } else {
3775                 I915_WRITE(IPS_CTL, 0);
3776                 POSTING_READ(IPS_CTL);
3777         }
3778
3779         /* We need to wait for a vblank before we can disable the plane. */
3780         intel_wait_for_vblank(dev, crtc->pipe);
3781 }
3782
3783 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3784 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3785 {
3786         struct drm_device *dev = crtc->dev;
3787         struct drm_i915_private *dev_priv = dev->dev_private;
3788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789         enum pipe pipe = intel_crtc->pipe;
3790         int palreg = PALETTE(pipe);
3791         int i;
3792         bool reenable_ips = false;
3793
3794         /* The clocks have to be on to load the palette. */
3795         if (!crtc->enabled || !intel_crtc->active)
3796                 return;
3797
3798         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3799                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3800                         assert_dsi_pll_enabled(dev_priv);
3801                 else
3802                         assert_pll_enabled(dev_priv, pipe);
3803         }
3804
3805         /* use legacy palette for Ironlake */
3806         if (HAS_PCH_SPLIT(dev))
3807                 palreg = LGC_PALETTE(pipe);
3808
3809         /* Workaround : Do not read or write the pipe palette/gamma data while
3810          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3811          */
3812         if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3813             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3814              GAMMA_MODE_MODE_SPLIT)) {
3815                 hsw_disable_ips(intel_crtc);
3816                 reenable_ips = true;
3817         }
3818
3819         for (i = 0; i < 256; i++) {
3820                 I915_WRITE(palreg + 4 * i,
3821                            (intel_crtc->lut_r[i] << 16) |
3822                            (intel_crtc->lut_g[i] << 8) |
3823                            intel_crtc->lut_b[i]);
3824         }
3825
3826         if (reenable_ips)
3827                 hsw_enable_ips(intel_crtc);
3828 }
3829
3830 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3831 {
3832         if (!enable && intel_crtc->overlay) {
3833                 struct drm_device *dev = intel_crtc->base.dev;
3834                 struct drm_i915_private *dev_priv = dev->dev_private;
3835
3836                 mutex_lock(&dev->struct_mutex);
3837                 dev_priv->mm.interruptible = false;
3838                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3839                 dev_priv->mm.interruptible = true;
3840                 mutex_unlock(&dev->struct_mutex);
3841         }
3842
3843         /* Let userspace switch the overlay on again. In most cases userspace
3844          * has to recompute where to put it anyway.
3845          */
3846 }
3847
3848 /**
3849  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3850  * cursor plane briefly if not already running after enabling the display
3851  * plane.
3852  * This workaround avoids occasional blank screens when self refresh is
3853  * enabled.
3854  */
3855 static void
3856 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3857 {
3858         u32 cntl = I915_READ(CURCNTR(pipe));
3859
3860         if ((cntl & CURSOR_MODE) == 0) {
3861                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3862
3863                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3864                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3865                 intel_wait_for_vblank(dev_priv->dev, pipe);
3866                 I915_WRITE(CURCNTR(pipe), cntl);
3867                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3868                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3869         }
3870 }
3871
3872 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3873 {
3874         struct drm_device *dev = crtc->dev;
3875         struct drm_i915_private *dev_priv = dev->dev_private;
3876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3877         int pipe = intel_crtc->pipe;
3878         int plane = intel_crtc->plane;
3879
3880         intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3881         intel_enable_planes(crtc);
3882         /* The fixup needs to happen before cursor is enabled */
3883         if (IS_G4X(dev))
3884                 g4x_fixup_plane(dev_priv, pipe);
3885         intel_crtc_update_cursor(crtc, true);
3886         intel_crtc_dpms_overlay(intel_crtc, true);
3887
3888         hsw_enable_ips(intel_crtc);
3889
3890         mutex_lock(&dev->struct_mutex);
3891         intel_update_fbc(dev);
3892         intel_edp_psr_update(dev);
3893         mutex_unlock(&dev->struct_mutex);
3894 }
3895
3896 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3897 {
3898         struct drm_device *dev = crtc->dev;
3899         struct drm_i915_private *dev_priv = dev->dev_private;
3900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3901         int pipe = intel_crtc->pipe;
3902         int plane = intel_crtc->plane;
3903
3904         intel_crtc_wait_for_pending_flips(crtc);
3905         drm_vblank_off(dev, pipe);
3906
3907         if (dev_priv->fbc.plane == plane)
3908                 intel_disable_fbc(dev);
3909
3910         hsw_disable_ips(intel_crtc);
3911
3912         intel_crtc_dpms_overlay(intel_crtc, false);
3913         intel_crtc_update_cursor(crtc, false);
3914         intel_disable_planes(crtc);
3915         intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3916 }
3917
3918 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3919 {
3920         struct drm_device *dev = crtc->dev;
3921         struct drm_i915_private *dev_priv = dev->dev_private;
3922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3923         struct intel_encoder *encoder;
3924         int pipe = intel_crtc->pipe;
3925         enum plane plane = intel_crtc->plane;
3926
3927         WARN_ON(!crtc->enabled);
3928
3929         if (intel_crtc->active)
3930                 return;
3931
3932         if (intel_crtc->config.has_pch_encoder)
3933                 intel_prepare_shared_dpll(intel_crtc);
3934
3935         if (intel_crtc->config.has_dp_encoder)
3936                 intel_dp_set_m_n(intel_crtc);
3937
3938         intel_set_pipe_timings(intel_crtc);
3939
3940         if (intel_crtc->config.has_pch_encoder) {
3941                 intel_cpu_transcoder_set_m_n(intel_crtc,
3942                                              &intel_crtc->config.fdi_m_n);
3943         }
3944
3945         ironlake_set_pipeconf(crtc);
3946
3947         /* Set up the display plane register */
3948         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3949         POSTING_READ(DSPCNTR(plane));
3950
3951         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3952                                                crtc->x, crtc->y);
3953
3954         intel_crtc->active = true;
3955
3956         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3957         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3958
3959         for_each_encoder_on_crtc(dev, crtc, encoder)
3960                 if (encoder->pre_enable)
3961                         encoder->pre_enable(encoder);
3962
3963         if (intel_crtc->config.has_pch_encoder) {
3964                 /* Note: FDI PLL enabling _must_ be done before we enable the
3965                  * cpu pipes, hence this is separate from all the other fdi/pch
3966                  * enabling. */
3967                 ironlake_fdi_pll_enable(intel_crtc);
3968         } else {
3969                 assert_fdi_tx_disabled(dev_priv, pipe);
3970                 assert_fdi_rx_disabled(dev_priv, pipe);
3971         }
3972
3973         ironlake_pfit_enable(intel_crtc);
3974
3975         /*
3976          * On ILK+ LUT must be loaded before the pipe is running but with
3977          * clocks enabled
3978          */
3979         intel_crtc_load_lut(crtc);
3980
3981         intel_update_watermarks(crtc);
3982         intel_enable_pipe(intel_crtc);
3983
3984         if (intel_crtc->config.has_pch_encoder)
3985                 ironlake_pch_enable(crtc);
3986
3987         for_each_encoder_on_crtc(dev, crtc, encoder)
3988                 encoder->enable(encoder);
3989
3990         if (HAS_PCH_CPT(dev))
3991                 cpt_verify_modeset(dev, intel_crtc->pipe);
3992
3993         intel_crtc_enable_planes(crtc);
3994
3995         /*
3996          * There seems to be a race in PCH platform hw (at least on some
3997          * outputs) where an enabled pipe still completes any pageflip right
3998          * away (as if the pipe is off) instead of waiting for vblank. As soon
3999          * as the first vblank happend, everything works as expected. Hence just
4000          * wait for one vblank before returning to avoid strange things
4001          * happening.
4002          */
4003         intel_wait_for_vblank(dev, intel_crtc->pipe);
4004 }
4005
4006 /* IPS only exists on ULT machines and is tied to pipe A. */
4007 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4008 {
4009         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4010 }
4011
4012 /*
4013  * This implements the workaround described in the "notes" section of the mode
4014  * set sequence documentation. When going from no pipes or single pipe to
4015  * multiple pipes, and planes are enabled after the pipe, we need to wait at
4016  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4017  */
4018 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4019 {
4020         struct drm_device *dev = crtc->base.dev;
4021         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4022
4023         /* We want to get the other_active_crtc only if there's only 1 other
4024          * active crtc. */
4025         for_each_intel_crtc(dev, crtc_it) {
4026                 if (!crtc_it->active || crtc_it == crtc)
4027                         continue;
4028
4029                 if (other_active_crtc)
4030                         return;
4031
4032                 other_active_crtc = crtc_it;
4033         }
4034         if (!other_active_crtc)
4035                 return;
4036
4037         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4038         intel_wait_for_vblank(dev, other_active_crtc->pipe);
4039 }
4040
4041 static void haswell_crtc_enable(struct drm_crtc *crtc)
4042 {
4043         struct drm_device *dev = crtc->dev;
4044         struct drm_i915_private *dev_priv = dev->dev_private;
4045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046         struct intel_encoder *encoder;
4047         int pipe = intel_crtc->pipe;
4048         enum plane plane = intel_crtc->plane;
4049
4050         WARN_ON(!crtc->enabled);
4051
4052         if (intel_crtc->active)
4053                 return;
4054
4055         if (intel_crtc->config.has_dp_encoder)
4056                 intel_dp_set_m_n(intel_crtc);
4057
4058         intel_set_pipe_timings(intel_crtc);
4059
4060         if (intel_crtc->config.has_pch_encoder) {
4061                 intel_cpu_transcoder_set_m_n(intel_crtc,
4062                                              &intel_crtc->config.fdi_m_n);
4063         }
4064
4065         haswell_set_pipeconf(crtc);
4066
4067         intel_set_pipe_csc(crtc);
4068
4069         /* Set up the display plane register */
4070         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4071         POSTING_READ(DSPCNTR(plane));
4072
4073         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4074                                                crtc->x, crtc->y);
4075
4076         intel_crtc->active = true;
4077
4078         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4079         if (intel_crtc->config.has_pch_encoder)
4080                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4081
4082         if (intel_crtc->config.has_pch_encoder)
4083                 dev_priv->display.fdi_link_train(crtc);
4084
4085         for_each_encoder_on_crtc(dev, crtc, encoder)
4086                 if (encoder->pre_enable)
4087                         encoder->pre_enable(encoder);
4088
4089         intel_ddi_enable_pipe_clock(intel_crtc);
4090
4091         ironlake_pfit_enable(intel_crtc);
4092
4093         /*
4094          * On ILK+ LUT must be loaded before the pipe is running but with
4095          * clocks enabled
4096          */
4097         intel_crtc_load_lut(crtc);
4098
4099         intel_ddi_set_pipe_settings(crtc);
4100         intel_ddi_enable_transcoder_func(crtc);
4101
4102         intel_update_watermarks(crtc);
4103         intel_enable_pipe(intel_crtc);
4104
4105         if (intel_crtc->config.has_pch_encoder)
4106                 lpt_pch_enable(crtc);
4107
4108         for_each_encoder_on_crtc(dev, crtc, encoder) {
4109                 encoder->enable(encoder);
4110                 intel_opregion_notify_encoder(encoder, true);
4111         }
4112
4113         /* If we change the relative order between pipe/planes enabling, we need
4114          * to change the workaround. */
4115         haswell_mode_set_planes_workaround(intel_crtc);
4116         intel_crtc_enable_planes(crtc);
4117 }
4118
4119 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4120 {
4121         struct drm_device *dev = crtc->base.dev;
4122         struct drm_i915_private *dev_priv = dev->dev_private;
4123         int pipe = crtc->pipe;
4124
4125         /* To avoid upsetting the power well on haswell only disable the pfit if
4126          * it's in use. The hw state code will make sure we get this right. */
4127         if (crtc->config.pch_pfit.enabled) {
4128                 I915_WRITE(PF_CTL(pipe), 0);
4129                 I915_WRITE(PF_WIN_POS(pipe), 0);
4130                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4131         }
4132 }
4133
4134 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4135 {
4136         struct drm_device *dev = crtc->dev;
4137         struct drm_i915_private *dev_priv = dev->dev_private;
4138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139         struct intel_encoder *encoder;
4140         int pipe = intel_crtc->pipe;
4141         u32 reg, temp;
4142
4143         if (!intel_crtc->active)
4144                 return;
4145
4146         intel_crtc_disable_planes(crtc);
4147
4148         for_each_encoder_on_crtc(dev, crtc, encoder)
4149                 encoder->disable(encoder);
4150
4151         if (intel_crtc->config.has_pch_encoder)
4152                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4153
4154         intel_disable_pipe(dev_priv, pipe);
4155
4156         ironlake_pfit_disable(intel_crtc);
4157
4158         for_each_encoder_on_crtc(dev, crtc, encoder)
4159                 if (encoder->post_disable)
4160                         encoder->post_disable(encoder);
4161
4162         if (intel_crtc->config.has_pch_encoder) {
4163                 ironlake_fdi_disable(crtc);
4164
4165                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4166                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4167
4168                 if (HAS_PCH_CPT(dev)) {
4169                         /* disable TRANS_DP_CTL */
4170                         reg = TRANS_DP_CTL(pipe);
4171                         temp = I915_READ(reg);
4172                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4173                                   TRANS_DP_PORT_SEL_MASK);
4174                         temp |= TRANS_DP_PORT_SEL_NONE;
4175                         I915_WRITE(reg, temp);
4176
4177                         /* disable DPLL_SEL */
4178                         temp = I915_READ(PCH_DPLL_SEL);
4179                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4180                         I915_WRITE(PCH_DPLL_SEL, temp);
4181                 }
4182
4183                 /* disable PCH DPLL */
4184                 intel_disable_shared_dpll(intel_crtc);
4185
4186                 ironlake_fdi_pll_disable(intel_crtc);
4187         }
4188
4189         intel_crtc->active = false;
4190         intel_update_watermarks(crtc);
4191
4192         mutex_lock(&dev->struct_mutex);
4193         intel_update_fbc(dev);
4194         intel_edp_psr_update(dev);
4195         mutex_unlock(&dev->struct_mutex);
4196 }
4197
4198 static void haswell_crtc_disable(struct drm_crtc *crtc)
4199 {
4200         struct drm_device *dev = crtc->dev;
4201         struct drm_i915_private *dev_priv = dev->dev_private;
4202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203         struct intel_encoder *encoder;
4204         int pipe = intel_crtc->pipe;
4205         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4206
4207         if (!intel_crtc->active)
4208                 return;
4209
4210         intel_crtc_disable_planes(crtc);
4211
4212         for_each_encoder_on_crtc(dev, crtc, encoder) {
4213                 intel_opregion_notify_encoder(encoder, false);
4214                 encoder->disable(encoder);
4215         }
4216
4217         if (intel_crtc->config.has_pch_encoder)
4218                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4219         intel_disable_pipe(dev_priv, pipe);
4220
4221         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4222
4223         ironlake_pfit_disable(intel_crtc);
4224
4225         intel_ddi_disable_pipe_clock(intel_crtc);
4226
4227         for_each_encoder_on_crtc(dev, crtc, encoder)
4228                 if (encoder->post_disable)
4229                         encoder->post_disable(encoder);
4230
4231         if (intel_crtc->config.has_pch_encoder) {
4232                 lpt_disable_pch_transcoder(dev_priv);
4233                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4234                 intel_ddi_fdi_disable(crtc);
4235         }
4236
4237         intel_crtc->active = false;
4238         intel_update_watermarks(crtc);
4239
4240         mutex_lock(&dev->struct_mutex);
4241         intel_update_fbc(dev);
4242         intel_edp_psr_update(dev);
4243         mutex_unlock(&dev->struct_mutex);
4244 }
4245
4246 static void ironlake_crtc_off(struct drm_crtc *crtc)
4247 {
4248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249         intel_put_shared_dpll(intel_crtc);
4250 }
4251
4252 static void haswell_crtc_off(struct drm_crtc *crtc)
4253 {
4254         intel_ddi_put_crtc_pll(crtc);
4255 }
4256
4257 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4258 {
4259         struct drm_device *dev = crtc->base.dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         struct intel_crtc_config *pipe_config = &crtc->config;
4262
4263         if (!crtc->config.gmch_pfit.control)
4264                 return;
4265
4266         /*
4267          * The panel fitter should only be adjusted whilst the pipe is disabled,
4268          * according to register description and PRM.
4269          */
4270         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4271         assert_pipe_disabled(dev_priv, crtc->pipe);
4272
4273         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4274         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4275
4276         /* Border color in case we don't scale up to the full screen. Black by
4277          * default, change to something else for debugging. */
4278         I915_WRITE(BCLRPAT(crtc->pipe), 0);
4279 }
4280
4281 #define for_each_power_domain(domain, mask)                             \
4282         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
4283                 if ((1 << (domain)) & (mask))
4284
4285 enum intel_display_power_domain
4286 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4287 {
4288         struct drm_device *dev = intel_encoder->base.dev;
4289         struct intel_digital_port *intel_dig_port;
4290
4291         switch (intel_encoder->type) {
4292         case INTEL_OUTPUT_UNKNOWN:
4293                 /* Only DDI platforms should ever use this output type */
4294                 WARN_ON_ONCE(!HAS_DDI(dev));
4295         case INTEL_OUTPUT_DISPLAYPORT:
4296         case INTEL_OUTPUT_HDMI:
4297         case INTEL_OUTPUT_EDP:
4298                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4299                 switch (intel_dig_port->port) {
4300                 case PORT_A:
4301                         return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4302                 case PORT_B:
4303                         return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4304                 case PORT_C:
4305                         return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4306                 case PORT_D:
4307                         return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4308                 default:
4309                         WARN_ON_ONCE(1);
4310                         return POWER_DOMAIN_PORT_OTHER;
4311                 }
4312         case INTEL_OUTPUT_ANALOG:
4313                 return POWER_DOMAIN_PORT_CRT;
4314         case INTEL_OUTPUT_DSI:
4315                 return POWER_DOMAIN_PORT_DSI;
4316         default:
4317                 return POWER_DOMAIN_PORT_OTHER;
4318         }
4319 }
4320
4321 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4322 {
4323         struct drm_device *dev = crtc->dev;
4324         struct intel_encoder *intel_encoder;
4325         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326         enum pipe pipe = intel_crtc->pipe;
4327         bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4328         unsigned long mask;
4329         enum transcoder transcoder;
4330
4331         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4332
4333         mask = BIT(POWER_DOMAIN_PIPE(pipe));
4334         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4335         if (pfit_enabled)
4336                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4337
4338         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4339                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4340
4341         return mask;
4342 }
4343
4344 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4345                                   bool enable)
4346 {
4347         if (dev_priv->power_domains.init_power_on == enable)
4348                 return;
4349
4350         if (enable)
4351                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4352         else
4353                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4354
4355         dev_priv->power_domains.init_power_on = enable;
4356 }
4357
4358 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4359 {
4360         struct drm_i915_private *dev_priv = dev->dev_private;
4361         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4362         struct intel_crtc *crtc;
4363
4364         /*
4365          * First get all needed power domains, then put all unneeded, to avoid
4366          * any unnecessary toggling of the power wells.
4367          */
4368         for_each_intel_crtc(dev, crtc) {
4369                 enum intel_display_power_domain domain;
4370
4371                 if (!crtc->base.enabled)
4372                         continue;
4373
4374                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4375
4376                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4377                         intel_display_power_get(dev_priv, domain);
4378         }
4379
4380         for_each_intel_crtc(dev, crtc) {
4381                 enum intel_display_power_domain domain;
4382
4383                 for_each_power_domain(domain, crtc->enabled_power_domains)
4384                         intel_display_power_put(dev_priv, domain);
4385
4386                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4387         }
4388
4389         intel_display_set_init_power(dev_priv, false);
4390 }
4391
4392 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4393 {
4394         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4395
4396         /* Obtain SKU information */
4397         mutex_lock(&dev_priv->dpio_lock);
4398         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4399                 CCK_FUSE_HPLL_FREQ_MASK;
4400         mutex_unlock(&dev_priv->dpio_lock);
4401
4402         return vco_freq[hpll_freq];
4403 }
4404
4405 /* Adjust CDclk dividers to allow high res or save power if possible */
4406 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4407 {
4408         struct drm_i915_private *dev_priv = dev->dev_private;
4409         u32 val, cmd;
4410
4411         WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4412         dev_priv->vlv_cdclk_freq = cdclk;
4413
4414         if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4415                 cmd = 2;
4416         else if (cdclk == 266)
4417                 cmd = 1;
4418         else
4419                 cmd = 0;
4420
4421         mutex_lock(&dev_priv->rps.hw_lock);
4422         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4423         val &= ~DSPFREQGUAR_MASK;
4424         val |= (cmd << DSPFREQGUAR_SHIFT);
4425         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4426         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4427                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4428                      50)) {
4429                 DRM_ERROR("timed out waiting for CDclk change\n");
4430         }
4431         mutex_unlock(&dev_priv->rps.hw_lock);
4432
4433         if (cdclk == 400) {
4434                 u32 divider, vco;
4435
4436                 vco = valleyview_get_vco(dev_priv);
4437                 divider = ((vco << 1) / cdclk) - 1;
4438
4439                 mutex_lock(&dev_priv->dpio_lock);
4440                 /* adjust cdclk divider */
4441                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4442                 val &= ~0xf;
4443                 val |= divider;
4444                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4445                 mutex_unlock(&dev_priv->dpio_lock);
4446         }
4447
4448         mutex_lock(&dev_priv->dpio_lock);
4449         /* adjust self-refresh exit latency value */
4450         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4451         val &= ~0x7f;
4452
4453         /*
4454          * For high bandwidth configs, we set a higher latency in the bunit
4455          * so that the core display fetch happens in time to avoid underruns.
4456          */
4457         if (cdclk == 400)
4458                 val |= 4500 / 250; /* 4.5 usec */
4459         else
4460                 val |= 3000 / 250; /* 3.0 usec */
4461         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4462         mutex_unlock(&dev_priv->dpio_lock);
4463
4464         /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4465         intel_i2c_reset(dev);
4466 }
4467
4468 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4469 {
4470         int cur_cdclk, vco;
4471         int divider;
4472
4473         vco = valleyview_get_vco(dev_priv);
4474
4475         mutex_lock(&dev_priv->dpio_lock);
4476         divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4477         mutex_unlock(&dev_priv->dpio_lock);
4478
4479         divider &= 0xf;
4480
4481         cur_cdclk = (vco << 1) / (divider + 1);
4482
4483         return cur_cdclk;
4484 }
4485
4486 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4487                                  int max_pixclk)
4488 {
4489         /*
4490          * Really only a few cases to deal with, as only 4 CDclks are supported:
4491          *   200MHz
4492          *   267MHz
4493          *   320MHz
4494          *   400MHz
4495          * So we check to see whether we're above 90% of the lower bin and
4496          * adjust if needed.
4497          */
4498         if (max_pixclk > 288000) {
4499                 return 400;
4500         } else if (max_pixclk > 240000) {
4501                 return 320;
4502         } else
4503                 return 266;
4504         /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4505 }
4506
4507 /* compute the max pixel clock for new configuration */
4508 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4509 {
4510         struct drm_device *dev = dev_priv->dev;
4511         struct intel_crtc *intel_crtc;
4512         int max_pixclk = 0;
4513
4514         for_each_intel_crtc(dev, intel_crtc) {
4515                 if (intel_crtc->new_enabled)
4516                         max_pixclk = max(max_pixclk,
4517                                          intel_crtc->new_config->adjusted_mode.crtc_clock);
4518         }
4519
4520         return max_pixclk;
4521 }
4522
4523 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4524                                             unsigned *prepare_pipes)
4525 {
4526         struct drm_i915_private *dev_priv = dev->dev_private;
4527         struct intel_crtc *intel_crtc;
4528         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4529
4530         if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4531             dev_priv->vlv_cdclk_freq)
4532                 return;
4533
4534         /* disable/enable all currently active pipes while we change cdclk */
4535         for_each_intel_crtc(dev, intel_crtc)
4536                 if (intel_crtc->base.enabled)
4537                         *prepare_pipes |= (1 << intel_crtc->pipe);
4538 }
4539
4540 static void valleyview_modeset_global_resources(struct drm_device *dev)
4541 {
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         int max_pixclk = intel_mode_max_pixclk(dev_priv);
4544         int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4545
4546         if (req_cdclk != dev_priv->vlv_cdclk_freq)
4547                 valleyview_set_cdclk(dev, req_cdclk);
4548         modeset_update_crtc_power_domains(dev);
4549 }
4550
4551 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4552 {
4553         struct drm_device *dev = crtc->dev;
4554         struct drm_i915_private *dev_priv = dev->dev_private;
4555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556         struct intel_encoder *encoder;
4557         int pipe = intel_crtc->pipe;
4558         int plane = intel_crtc->plane;
4559         bool is_dsi;
4560         u32 dspcntr;
4561
4562         WARN_ON(!crtc->enabled);
4563
4564         if (intel_crtc->active)
4565                 return;
4566
4567         vlv_prepare_pll(intel_crtc);
4568
4569         /* Set up the display plane register */
4570         dspcntr = DISPPLANE_GAMMA_ENABLE;
4571
4572         if (intel_crtc->config.has_dp_encoder)
4573                 intel_dp_set_m_n(intel_crtc);
4574
4575         intel_set_pipe_timings(intel_crtc);
4576
4577         /* pipesrc and dspsize control the size that is scaled from,
4578          * which should always be the user's requested size.
4579          */
4580         I915_WRITE(DSPSIZE(plane),
4581                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4582                    (intel_crtc->config.pipe_src_w - 1));
4583         I915_WRITE(DSPPOS(plane), 0);
4584
4585         i9xx_set_pipeconf(intel_crtc);
4586
4587         I915_WRITE(DSPCNTR(plane), dspcntr);
4588         POSTING_READ(DSPCNTR(plane));
4589
4590         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4591                                                crtc->x, crtc->y);
4592
4593         intel_crtc->active = true;
4594
4595         for_each_encoder_on_crtc(dev, crtc, encoder)
4596                 if (encoder->pre_pll_enable)
4597                         encoder->pre_pll_enable(encoder);
4598
4599         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4600
4601         if (!is_dsi) {
4602                 if (IS_CHERRYVIEW(dev))
4603                         chv_enable_pll(intel_crtc);
4604                 else
4605                         vlv_enable_pll(intel_crtc);
4606         }
4607
4608         for_each_encoder_on_crtc(dev, crtc, encoder)
4609                 if (encoder->pre_enable)
4610                         encoder->pre_enable(encoder);
4611
4612         i9xx_pfit_enable(intel_crtc);
4613
4614         intel_crtc_load_lut(crtc);
4615
4616         intel_update_watermarks(crtc);
4617         intel_enable_pipe(intel_crtc);
4618         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4619
4620         for_each_encoder_on_crtc(dev, crtc, encoder)
4621                 encoder->enable(encoder);
4622
4623         intel_crtc_enable_planes(crtc);
4624 }
4625
4626 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4627 {
4628         struct drm_device *dev = crtc->base.dev;
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630
4631         I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4632         I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4633 }
4634
4635 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4636 {
4637         struct drm_device *dev = crtc->dev;
4638         struct drm_i915_private *dev_priv = dev->dev_private;
4639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4640         struct intel_encoder *encoder;
4641         int pipe = intel_crtc->pipe;
4642         int plane = intel_crtc->plane;
4643         u32 dspcntr;
4644
4645         WARN_ON(!crtc->enabled);
4646
4647         if (intel_crtc->active)
4648                 return;
4649
4650         i9xx_set_pll_dividers(intel_crtc);
4651
4652         /* Set up the display plane register */
4653         dspcntr = DISPPLANE_GAMMA_ENABLE;
4654
4655         if (pipe == 0)
4656                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4657         else
4658                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4659
4660         if (intel_crtc->config.has_dp_encoder)
4661                 intel_dp_set_m_n(intel_crtc);
4662
4663         intel_set_pipe_timings(intel_crtc);
4664
4665         /* pipesrc and dspsize control the size that is scaled from,
4666          * which should always be the user's requested size.
4667          */
4668         I915_WRITE(DSPSIZE(plane),
4669                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
4670                    (intel_crtc->config.pipe_src_w - 1));
4671         I915_WRITE(DSPPOS(plane), 0);
4672
4673         i9xx_set_pipeconf(intel_crtc);
4674
4675         I915_WRITE(DSPCNTR(plane), dspcntr);
4676         POSTING_READ(DSPCNTR(plane));
4677
4678         dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4679                                                crtc->x, crtc->y);
4680
4681         intel_crtc->active = true;
4682
4683         for_each_encoder_on_crtc(dev, crtc, encoder)
4684                 if (encoder->pre_enable)
4685                         encoder->pre_enable(encoder);
4686
4687         i9xx_enable_pll(intel_crtc);
4688
4689         i9xx_pfit_enable(intel_crtc);
4690
4691         intel_crtc_load_lut(crtc);
4692
4693         intel_update_watermarks(crtc);
4694         intel_enable_pipe(intel_crtc);
4695         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4696
4697         for_each_encoder_on_crtc(dev, crtc, encoder)
4698                 encoder->enable(encoder);
4699
4700         intel_crtc_enable_planes(crtc);
4701 }
4702
4703 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4704 {
4705         struct drm_device *dev = crtc->base.dev;
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707
4708         if (!crtc->config.gmch_pfit.control)
4709                 return;
4710
4711         assert_pipe_disabled(dev_priv, crtc->pipe);
4712
4713         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4714                          I915_READ(PFIT_CONTROL));
4715         I915_WRITE(PFIT_CONTROL, 0);
4716 }
4717
4718 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4719 {
4720         struct drm_device *dev = crtc->dev;
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723         struct intel_encoder *encoder;
4724         int pipe = intel_crtc->pipe;
4725
4726         if (!intel_crtc->active)
4727                 return;
4728
4729         intel_crtc_disable_planes(crtc);
4730
4731         for_each_encoder_on_crtc(dev, crtc, encoder)
4732                 encoder->disable(encoder);
4733
4734         intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4735         intel_disable_pipe(dev_priv, pipe);
4736
4737         i9xx_pfit_disable(intel_crtc);
4738
4739         for_each_encoder_on_crtc(dev, crtc, encoder)
4740                 if (encoder->post_disable)
4741                         encoder->post_disable(encoder);
4742
4743         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4744                 if (IS_CHERRYVIEW(dev))
4745                         chv_disable_pll(dev_priv, pipe);
4746                 else if (IS_VALLEYVIEW(dev))
4747                         vlv_disable_pll(dev_priv, pipe);
4748                 else
4749                         i9xx_disable_pll(dev_priv, pipe);
4750         }
4751
4752         intel_crtc->active = false;
4753         intel_update_watermarks(crtc);
4754
4755         mutex_lock(&dev->struct_mutex);
4756         intel_update_fbc(dev);
4757         intel_edp_psr_update(dev);
4758         mutex_unlock(&dev->struct_mutex);
4759 }
4760
4761 static void i9xx_crtc_off(struct drm_crtc *crtc)
4762 {
4763 }
4764
4765 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4766                                     bool enabled)
4767 {
4768         struct drm_device *dev = crtc->dev;
4769         struct drm_i915_master_private *master_priv;
4770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771         int pipe = intel_crtc->pipe;
4772
4773         if (!dev->primary->master)
4774                 return;
4775
4776         master_priv = dev->primary->master->driver_priv;
4777         if (!master_priv->sarea_priv)
4778                 return;
4779
4780         switch (pipe) {
4781         case 0:
4782                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4783                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4784                 break;
4785         case 1:
4786                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4787                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4788                 break;
4789         default:
4790                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4791                 break;
4792         }
4793 }
4794
4795 /**
4796  * Sets the power management mode of the pipe and plane.
4797  */
4798 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4799 {
4800         struct drm_device *dev = crtc->dev;
4801         struct drm_i915_private *dev_priv = dev->dev_private;
4802         struct intel_encoder *intel_encoder;
4803         bool enable = false;
4804
4805         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4806                 enable |= intel_encoder->connectors_active;
4807
4808         if (enable)
4809                 dev_priv->display.crtc_enable(crtc);
4810         else
4811                 dev_priv->display.crtc_disable(crtc);
4812
4813         intel_crtc_update_sarea(crtc, enable);
4814 }
4815
4816 static void intel_crtc_disable(struct drm_crtc *crtc)
4817 {
4818         struct drm_device *dev = crtc->dev;
4819         struct drm_connector *connector;
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821
4822         /* crtc should still be enabled when we disable it. */
4823         WARN_ON(!crtc->enabled);
4824
4825         dev_priv->display.crtc_disable(crtc);
4826         intel_crtc_update_sarea(crtc, false);
4827         dev_priv->display.off(crtc);
4828
4829         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4830         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4831         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4832
4833         if (crtc->primary->fb) {
4834                 mutex_lock(&dev->struct_mutex);
4835                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4836                 mutex_unlock(&dev->struct_mutex);
4837                 crtc->primary->fb = NULL;
4838         }
4839
4840         /* Update computed state. */
4841         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4842                 if (!connector->encoder || !connector->encoder->crtc)
4843                         continue;
4844
4845                 if (connector->encoder->crtc != crtc)
4846                         continue;
4847
4848                 connector->dpms = DRM_MODE_DPMS_OFF;
4849                 to_intel_encoder(connector->encoder)->connectors_active = false;
4850         }
4851 }
4852
4853 void intel_encoder_destroy(struct drm_encoder *encoder)
4854 {
4855         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4856
4857         drm_encoder_cleanup(encoder);
4858         kfree(intel_encoder);
4859 }
4860
4861 /* Simple dpms helper for encoders with just one connector, no cloning and only
4862  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4863  * state of the entire output pipe. */
4864 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4865 {
4866         if (mode == DRM_MODE_DPMS_ON) {
4867                 encoder->connectors_active = true;
4868
4869                 intel_crtc_update_dpms(encoder->base.crtc);
4870         } else {
4871                 encoder->connectors_active = false;
4872
4873                 intel_crtc_update_dpms(encoder->base.crtc);
4874         }
4875 }
4876
4877 /* Cross check the actual hw state with our own modeset state tracking (and it's
4878  * internal consistency). */
4879 static void intel_connector_check_state(struct intel_connector *connector)
4880 {
4881         if (connector->get_hw_state(connector)) {
4882                 struct intel_encoder *encoder = connector->encoder;
4883                 struct drm_crtc *crtc;
4884                 bool encoder_enabled;
4885                 enum pipe pipe;
4886
4887                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4888                               connector->base.base.id,
4889                               drm_get_connector_name(&connector->base));
4890
4891                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4892                      "wrong connector dpms state\n");
4893                 WARN(connector->base.encoder != &encoder->base,
4894                      "active connector not linked to encoder\n");
4895                 WARN(!encoder->connectors_active,
4896                      "encoder->connectors_active not set\n");
4897
4898                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4899                 WARN(!encoder_enabled, "encoder not enabled\n");
4900                 if (WARN_ON(!encoder->base.crtc))
4901                         return;
4902
4903                 crtc = encoder->base.crtc;
4904
4905                 WARN(!crtc->enabled, "crtc not enabled\n");
4906                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4907                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4908                      "encoder active on the wrong pipe\n");
4909         }
4910 }
4911
4912 /* Even simpler default implementation, if there's really no special case to
4913  * consider. */
4914 void intel_connector_dpms(struct drm_connector *connector, int mode)
4915 {
4916         /* All the simple cases only support two dpms states. */
4917         if (mode != DRM_MODE_DPMS_ON)
4918                 mode = DRM_MODE_DPMS_OFF;
4919
4920         if (mode == connector->dpms)
4921                 return;
4922
4923         connector->dpms = mode;
4924
4925         /* Only need to change hw state when actually enabled */
4926         if (connector->encoder)
4927                 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4928
4929         intel_modeset_check_state(connector->dev);
4930 }
4931
4932 /* Simple connector->get_hw_state implementation for encoders that support only
4933  * one connector and no cloning and hence the encoder state determines the state
4934  * of the connector. */
4935 bool intel_connector_get_hw_state(struct intel_connector *connector)
4936 {
4937         enum pipe pipe = 0;
4938         struct intel_encoder *encoder = connector->encoder;
4939
4940         return encoder->get_hw_state(encoder, &pipe);
4941 }
4942
4943 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4944                                      struct intel_crtc_config *pipe_config)
4945 {
4946         struct drm_i915_private *dev_priv = dev->dev_private;
4947         struct intel_crtc *pipe_B_crtc =
4948                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4949
4950         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4951                       pipe_name(pipe), pipe_config->fdi_lanes);
4952         if (pipe_config->fdi_lanes > 4) {
4953                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4954                               pipe_name(pipe), pipe_config->fdi_lanes);
4955                 return false;
4956         }
4957
4958         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4959                 if (pipe_config->fdi_lanes > 2) {
4960                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4961                                       pipe_config->fdi_lanes);
4962                         return false;
4963                 } else {
4964                         return true;
4965                 }
4966         }
4967
4968         if (INTEL_INFO(dev)->num_pipes == 2)
4969                 return true;
4970
4971         /* Ivybridge 3 pipe is really complicated */
4972         switch (pipe) {
4973         case PIPE_A:
4974                 return true;
4975         case PIPE_B:
4976                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4977                     pipe_config->fdi_lanes > 2) {
4978                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4979                                       pipe_name(pipe), pipe_config->fdi_lanes);
4980                         return false;
4981                 }
4982                 return true;
4983         case PIPE_C:
4984                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4985                     pipe_B_crtc->config.fdi_lanes <= 2) {
4986                         if (pipe_config->fdi_lanes > 2) {
4987                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4988                                               pipe_name(pipe), pipe_config->fdi_lanes);
4989                                 return false;
4990                         }
4991                 } else {
4992                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4993                         return false;
4994                 }
4995                 return true;
4996         default:
4997                 BUG();
4998         }
4999 }
5000
5001 #define RETRY 1
5002 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5003                                        struct intel_crtc_config *pipe_config)
5004 {
5005         struct drm_device *dev = intel_crtc->base.dev;
5006         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5007         int lane, link_bw, fdi_dotclock;
5008         bool setup_ok, needs_recompute = false;
5009
5010 retry:
5011         /* FDI is a binary signal running at ~2.7GHz, encoding
5012          * each output octet as 10 bits. The actual frequency
5013          * is stored as a divider into a 100MHz clock, and the
5014          * mode pixel clock is stored in units of 1KHz.
5015          * Hence the bw of each lane in terms of the mode signal
5016          * is:
5017          */
5018         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5019
5020         fdi_dotclock = adjusted_mode->crtc_clock;
5021
5022         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5023                                            pipe_config->pipe_bpp);
5024
5025         pipe_config->fdi_lanes = lane;
5026
5027         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5028                                link_bw, &pipe_config->fdi_m_n);
5029
5030         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5031                                             intel_crtc->pipe, pipe_config);
5032         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5033                 pipe_config->pipe_bpp -= 2*3;
5034                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5035                               pipe_config->pipe_bpp);
5036                 needs_recompute = true;
5037                 pipe_config->bw_constrained = true;
5038
5039                 goto retry;
5040         }
5041
5042         if (needs_recompute)
5043                 return RETRY;
5044
5045         return setup_ok ? 0 : -EINVAL;
5046 }
5047
5048 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5049                                    struct intel_crtc_config *pipe_config)
5050 {
5051         pipe_config->ips_enabled = i915.enable_ips &&
5052                                    hsw_crtc_supports_ips(crtc) &&
5053                                    pipe_config->pipe_bpp <= 24;
5054 }
5055
5056 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5057                                      struct intel_crtc_config *pipe_config)
5058 {
5059         struct drm_device *dev = crtc->base.dev;
5060         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5061
5062         /* FIXME should check pixel clock limits on all platforms */
5063         if (INTEL_INFO(dev)->gen < 4) {
5064                 struct drm_i915_private *dev_priv = dev->dev_private;
5065                 int clock_limit =
5066                         dev_priv->display.get_display_clock_speed(dev);
5067
5068                 /*
5069                  * Enable pixel doubling when the dot clock
5070                  * is > 90% of the (display) core speed.
5071                  *
5072                  * GDG double wide on either pipe,
5073                  * otherwise pipe A only.
5074                  */
5075                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5076                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5077                         clock_limit *= 2;
5078                         pipe_config->double_wide = true;
5079                 }
5080
5081                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5082                         return -EINVAL;
5083         }
5084
5085         /*
5086          * Pipe horizontal size must be even in:
5087          * - DVO ganged mode
5088          * - LVDS dual channel mode
5089          * - Double wide pipe
5090          */
5091         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5092              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5093                 pipe_config->pipe_src_w &= ~1;
5094
5095         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5096          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5097          */
5098         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5099                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5100                 return -EINVAL;
5101
5102         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5103                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5104         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5105                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5106                  * for lvds. */
5107                 pipe_config->pipe_bpp = 8*3;
5108         }
5109
5110         if (HAS_IPS(dev))
5111                 hsw_compute_ips_config(crtc, pipe_config);
5112
5113         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5114          * clock survives for now. */
5115         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5116                 pipe_config->shared_dpll = crtc->config.shared_dpll;
5117
5118         if (pipe_config->has_pch_encoder)
5119                 return ironlake_fdi_compute_config(crtc, pipe_config);
5120
5121         return 0;
5122 }
5123
5124 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5125 {
5126         return 400000; /* FIXME */
5127 }
5128
5129 static int i945_get_display_clock_speed(struct drm_device *dev)
5130 {
5131         return 400000;
5132 }
5133
5134 static int i915_get_display_clock_speed(struct drm_device *dev)
5135 {
5136         return 333000;
5137 }
5138
5139 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5140 {
5141         return 200000;
5142 }
5143
5144 static int pnv_get_display_clock_speed(struct drm_device *dev)
5145 {
5146         u16 gcfgc = 0;
5147
5148         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5149
5150         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5151         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5152                 return 267000;
5153         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5154                 return 333000;
5155         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5156                 return 444000;
5157         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5158                 return 200000;
5159         default:
5160                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5161         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5162                 return 133000;
5163         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5164                 return 167000;
5165         }
5166 }
5167
5168 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5169 {
5170         u16 gcfgc = 0;
5171
5172         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5173
5174         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5175                 return 133000;
5176         else {
5177                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5178                 case GC_DISPLAY_CLOCK_333_MHZ:
5179                         return 333000;
5180                 default:
5181                 case GC_DISPLAY_CLOCK_190_200_MHZ:
5182                         return 190000;
5183                 }
5184         }
5185 }
5186
5187 static int i865_get_display_clock_speed(struct drm_device *dev)
5188 {
5189         return 266000;
5190 }
5191
5192 static int i855_get_display_clock_speed(struct drm_device *dev)
5193 {
5194         u16 hpllcc = 0;
5195         /* Assume that the hardware is in the high speed state.  This
5196          * should be the default.
5197          */
5198         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5199         case GC_CLOCK_133_200:
5200         case GC_CLOCK_100_200:
5201                 return 200000;
5202         case GC_CLOCK_166_250:
5203                 return 250000;
5204         case GC_CLOCK_100_133:
5205                 return 133000;
5206         }
5207
5208         /* Shouldn't happen */
5209         return 0;
5210 }
5211
5212 static int i830_get_display_clock_speed(struct drm_device *dev)
5213 {
5214         return 133000;
5215 }
5216
5217 static void
5218 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5219 {
5220         while (*num > DATA_LINK_M_N_MASK ||
5221                *den > DATA_LINK_M_N_MASK) {
5222                 *num >>= 1;
5223                 *den >>= 1;
5224         }
5225 }
5226
5227 static void compute_m_n(unsigned int m, unsigned int n,
5228                         uint32_t *ret_m, uint32_t *ret_n)
5229 {
5230         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5231         *ret_m = div_u64((uint64_t) m * *ret_n, n);
5232         intel_reduce_m_n_ratio(ret_m, ret_n);
5233 }
5234
5235 void
5236 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5237                        int pixel_clock, int link_clock,
5238                        struct intel_link_m_n *m_n)
5239 {
5240         m_n->tu = 64;
5241
5242         compute_m_n(bits_per_pixel * pixel_clock,
5243                     link_clock * nlanes * 8,
5244                     &m_n->gmch_m, &m_n->gmch_n);
5245
5246         compute_m_n(pixel_clock, link_clock,
5247                     &m_n->link_m, &m_n->link_n);
5248 }
5249
5250 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5251 {
5252         if (i915.panel_use_ssc >= 0)
5253                 return i915.panel_use_ssc != 0;
5254         return dev_priv->vbt.lvds_use_ssc
5255                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5256 }
5257
5258 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5259 {
5260         struct drm_device *dev = crtc->dev;
5261         struct drm_i915_private *dev_priv = dev->dev_private;
5262         int refclk;
5263
5264         if (IS_VALLEYVIEW(dev)) {
5265                 refclk = 100000;
5266         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5267             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5268                 refclk = dev_priv->vbt.lvds_ssc_freq;
5269                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5270         } else if (!IS_GEN2(dev)) {
5271                 refclk = 96000;
5272         } else {
5273                 refclk = 48000;
5274         }
5275
5276         return refclk;
5277 }
5278
5279 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5280 {
5281         return (1 << dpll->n) << 16 | dpll->m2;
5282 }
5283
5284 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5285 {
5286         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5287 }
5288
5289 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5290                                      intel_clock_t *reduced_clock)
5291 {
5292         struct drm_device *dev = crtc->base.dev;
5293         u32 fp, fp2 = 0;
5294
5295         if (IS_PINEVIEW(dev)) {
5296                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5297                 if (reduced_clock)
5298                         fp2 = pnv_dpll_compute_fp(reduced_clock);
5299         } else {
5300                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5301                 if (reduced_clock)
5302                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
5303         }
5304
5305         crtc->config.dpll_hw_state.fp0 = fp;
5306
5307         crtc->lowfreq_avail = false;
5308         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5309             reduced_clock && i915.powersave) {
5310                 crtc->config.dpll_hw_state.fp1 = fp2;
5311                 crtc->lowfreq_avail = true;
5312         } else {
5313                 crtc->config.dpll_hw_state.fp1 = fp;
5314         }
5315 }
5316
5317 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5318                 pipe)
5319 {
5320         u32 reg_val;
5321
5322         /*
5323          * PLLB opamp always calibrates to max value of 0x3f, force enable it
5324          * and set it to a reasonable value instead.
5325          */
5326         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5327         reg_val &= 0xffffff00;
5328         reg_val |= 0x00000030;
5329         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5330
5331         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5332         reg_val &= 0x8cffffff;
5333         reg_val = 0x8c000000;
5334         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5335
5336         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5337         reg_val &= 0xffffff00;
5338         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5339
5340         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5341         reg_val &= 0x00ffffff;
5342         reg_val |= 0xb0000000;
5343         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5344 }
5345
5346 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5347                                          struct intel_link_m_n *m_n)
5348 {
5349         struct drm_device *dev = crtc->base.dev;
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351         int pipe = crtc->pipe;
5352
5353         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5354         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5355         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5356         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5357 }
5358
5359 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5360                                          struct intel_link_m_n *m_n)
5361 {
5362         struct drm_device *dev = crtc->base.dev;
5363         struct drm_i915_private *dev_priv = dev->dev_private;
5364         int pipe = crtc->pipe;
5365         enum transcoder transcoder = crtc->config.cpu_transcoder;
5366
5367         if (INTEL_INFO(dev)->gen >= 5) {
5368                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5369                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5370                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5371                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5372         } else {
5373                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5374                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5375                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5376                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5377         }
5378 }
5379
5380 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5381 {
5382         if (crtc->config.has_pch_encoder)
5383                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5384         else
5385                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5386 }
5387
5388 static void vlv_update_pll(struct intel_crtc *crtc)
5389 {
5390         u32 dpll, dpll_md;
5391
5392         /*
5393          * Enable DPIO clock input. We should never disable the reference
5394          * clock for pipe B, since VGA hotplug / manual detection depends
5395          * on it.
5396          */
5397         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5398                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5399         /* We should never disable this, set it here for state tracking */
5400         if (crtc->pipe == PIPE_B)
5401                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5402         dpll |= DPLL_VCO_ENABLE;
5403         crtc->config.dpll_hw_state.dpll = dpll;
5404
5405         dpll_md = (crtc->config.pixel_multiplier - 1)
5406                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5407         crtc->config.dpll_hw_state.dpll_md = dpll_md;
5408 }
5409
5410 static void vlv_prepare_pll(struct intel_crtc *crtc)
5411 {
5412         struct drm_device *dev = crtc->base.dev;
5413         struct drm_i915_private *dev_priv = dev->dev_private;
5414         int pipe = crtc->pipe;
5415         u32 mdiv;
5416         u32 bestn, bestm1, bestm2, bestp1, bestp2;
5417         u32 coreclk, reg_val;
5418
5419         mutex_lock(&dev_priv->dpio_lock);
5420
5421         bestn = crtc->config.dpll.n;
5422         bestm1 = crtc->config.dpll.m1;
5423         bestm2 = crtc->config.dpll.m2;
5424         bestp1 = crtc->config.dpll.p1;
5425         bestp2 = crtc->config.dpll.p2;
5426
5427         /* See eDP HDMI DPIO driver vbios notes doc */
5428
5429         /* PLL B needs special handling */
5430         if (pipe == PIPE_B)
5431                 vlv_pllb_recal_opamp(dev_priv, pipe);
5432
5433         /* Set up Tx target for periodic Rcomp update */
5434         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5435
5436         /* Disable target IRef on PLL */
5437         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5438         reg_val &= 0x00ffffff;
5439         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5440
5441         /* Disable fast lock */
5442         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5443
5444         /* Set idtafcrecal before PLL is enabled */
5445         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5446         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5447         mdiv |= ((bestn << DPIO_N_SHIFT));
5448         mdiv |= (1 << DPIO_K_SHIFT);
5449
5450         /*
5451          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5452          * but we don't support that).
5453          * Note: don't use the DAC post divider as it seems unstable.
5454          */
5455         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5456         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5457
5458         mdiv |= DPIO_ENABLE_CALIBRATION;
5459         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5460
5461         /* Set HBR and RBR LPF coefficients */
5462         if (crtc->config.port_clock == 162000 ||
5463             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5464             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5465                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5466                                  0x009f0003);
5467         else
5468                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5469                                  0x00d0000f);
5470
5471         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5472             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5473                 /* Use SSC source */
5474                 if (pipe == PIPE_A)
5475                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5476                                          0x0df40000);
5477                 else
5478                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5479                                          0x0df70000);
5480         } else { /* HDMI or VGA */
5481                 /* Use bend source */
5482                 if (pipe == PIPE_A)
5483                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5484                                          0x0df70000);
5485                 else
5486                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5487                                          0x0df40000);
5488         }
5489
5490         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5491         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5492         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5493             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5494                 coreclk |= 0x01000000;
5495         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5496
5497         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5498         mutex_unlock(&dev_priv->dpio_lock);
5499 }
5500
5501 static void chv_update_pll(struct intel_crtc *crtc)
5502 {
5503         struct drm_device *dev = crtc->base.dev;
5504         struct drm_i915_private *dev_priv = dev->dev_private;
5505         int pipe = crtc->pipe;
5506         int dpll_reg = DPLL(crtc->pipe);
5507         enum dpio_channel port = vlv_pipe_to_channel(pipe);
5508         u32 val, loopfilter, intcoeff;
5509         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5510         int refclk;
5511
5512         crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5513                 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5514                 DPLL_VCO_ENABLE;
5515         if (pipe != PIPE_A)
5516                 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5517
5518         crtc->config.dpll_hw_state.dpll_md =
5519                 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5520
5521         bestn = crtc->config.dpll.n;
5522         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5523         bestm1 = crtc->config.dpll.m1;
5524         bestm2 = crtc->config.dpll.m2 >> 22;
5525         bestp1 = crtc->config.dpll.p1;
5526         bestp2 = crtc->config.dpll.p2;
5527
5528         /*
5529          * Enable Refclk and SSC
5530          */
5531         I915_WRITE(dpll_reg,
5532                    crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5533
5534         mutex_lock(&dev_priv->dpio_lock);
5535
5536         /* Propagate soft reset to data lane reset */
5537         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
5538         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
5539         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
5540
5541         /* Disable 10bit clock to display controller */
5542         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
5543         val &= ~DPIO_DCLKP_EN;
5544         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
5545
5546         /* p1 and p2 divider */
5547         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5548                         5 << DPIO_CHV_S1_DIV_SHIFT |
5549                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5550                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5551                         1 << DPIO_CHV_K_DIV_SHIFT);
5552
5553         /* Feedback post-divider - m2 */
5554         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5555
5556         /* Feedback refclk divider - n and m1 */
5557         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5558                         DPIO_CHV_M1_DIV_BY_2 |
5559                         1 << DPIO_CHV_N_DIV_SHIFT);
5560
5561         /* M2 fraction division */
5562         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5563
5564         /* M2 fraction division enable */
5565         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5566                        DPIO_CHV_FRAC_DIV_EN |
5567                        (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5568
5569         /* Loop filter */
5570         refclk = i9xx_get_refclk(&crtc->base, 0);
5571         loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5572                 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5573         if (refclk == 100000)
5574                 intcoeff = 11;
5575         else if (refclk == 38400)
5576                 intcoeff = 10;
5577         else
5578                 intcoeff = 9;
5579         loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5580         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5581
5582         /* AFC Recal */
5583         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5584                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5585                         DPIO_AFC_RECAL);
5586
5587         mutex_unlock(&dev_priv->dpio_lock);
5588 }
5589
5590 static void i9xx_update_pll(struct intel_crtc *crtc,
5591                             intel_clock_t *reduced_clock,
5592                             int num_connectors)
5593 {
5594         struct drm_device *dev = crtc->base.dev;
5595         struct drm_i915_private *dev_priv = dev->dev_private;
5596         u32 dpll;
5597         bool is_sdvo;
5598         struct dpll *clock = &crtc->config.dpll;
5599
5600         i9xx_update_pll_dividers(crtc, reduced_clock);
5601
5602         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5603                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5604
5605         dpll = DPLL_VGA_MODE_DIS;
5606
5607         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5608                 dpll |= DPLLB_MODE_LVDS;
5609         else
5610                 dpll |= DPLLB_MODE_DAC_SERIAL;
5611
5612         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5613                 dpll |= (crtc->config.pixel_multiplier - 1)
5614                         << SDVO_MULTIPLIER_SHIFT_HIRES;
5615         }
5616
5617         if (is_sdvo)
5618                 dpll |= DPLL_SDVO_HIGH_SPEED;
5619
5620         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5621                 dpll |= DPLL_SDVO_HIGH_SPEED;
5622
5623         /* compute bitmask from p1 value */
5624         if (IS_PINEVIEW(dev))
5625                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5626         else {
5627                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5628                 if (IS_G4X(dev) && reduced_clock)
5629                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5630         }
5631         switch (clock->p2) {
5632         case 5:
5633                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5634                 break;
5635         case 7:
5636                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5637                 break;
5638         case 10:
5639                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5640                 break;
5641         case 14:
5642                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5643                 break;
5644         }
5645         if (INTEL_INFO(dev)->gen >= 4)
5646                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5647
5648         if (crtc->config.sdvo_tv_clock)
5649                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5650         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5651                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5652                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5653         else
5654                 dpll |= PLL_REF_INPUT_DREFCLK;
5655
5656         dpll |= DPLL_VCO_ENABLE;
5657         crtc->config.dpll_hw_state.dpll = dpll;
5658
5659         if (INTEL_INFO(dev)->gen >= 4) {
5660                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5661                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5662                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5663         }
5664 }
5665
5666 static void i8xx_update_pll(struct intel_crtc *crtc,
5667                             intel_clock_t *reduced_clock,
5668                             int num_connectors)
5669 {
5670         struct drm_device *dev = crtc->base.dev;
5671         struct drm_i915_private *dev_priv = dev->dev_private;
5672         u32 dpll;
5673         struct dpll *clock = &crtc->config.dpll;
5674
5675         i9xx_update_pll_dividers(crtc, reduced_clock);
5676
5677         dpll = DPLL_VGA_MODE_DIS;
5678
5679         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5680                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5681         } else {
5682                 if (clock->p1 == 2)
5683                         dpll |= PLL_P1_DIVIDE_BY_TWO;
5684                 else
5685                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5686                 if (clock->p2 == 4)
5687                         dpll |= PLL_P2_DIVIDE_BY_4;
5688         }
5689
5690         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5691                 dpll |= DPLL_DVO_2X_MODE;
5692
5693         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5694                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5695                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5696         else
5697                 dpll |= PLL_REF_INPUT_DREFCLK;
5698
5699         dpll |= DPLL_VCO_ENABLE;
5700         crtc->config.dpll_hw_state.dpll = dpll;
5701 }
5702
5703 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5704 {
5705         struct drm_device *dev = intel_crtc->base.dev;
5706         struct drm_i915_private *dev_priv = dev->dev_private;
5707         enum pipe pipe = intel_crtc->pipe;
5708         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5709         struct drm_display_mode *adjusted_mode =
5710                 &intel_crtc->config.adjusted_mode;
5711         uint32_t crtc_vtotal, crtc_vblank_end;
5712         int vsyncshift = 0;
5713
5714         /* We need to be careful not to changed the adjusted mode, for otherwise
5715          * the hw state checker will get angry at the mismatch. */
5716         crtc_vtotal = adjusted_mode->crtc_vtotal;
5717         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5718
5719         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5720                 /* the chip adds 2 halflines automatically */
5721                 crtc_vtotal -= 1;
5722                 crtc_vblank_end -= 1;
5723
5724                 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5725                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5726                 else
5727                         vsyncshift = adjusted_mode->crtc_hsync_start -
5728                                 adjusted_mode->crtc_htotal / 2;
5729                 if (vsyncshift < 0)
5730                         vsyncshift += adjusted_mode->crtc_htotal;
5731         }
5732
5733         if (INTEL_INFO(dev)->gen > 3)
5734                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5735
5736         I915_WRITE(HTOTAL(cpu_transcoder),
5737                    (adjusted_mode->crtc_hdisplay - 1) |
5738                    ((adjusted_mode->crtc_htotal - 1) << 16));
5739         I915_WRITE(HBLANK(cpu_transcoder),
5740                    (adjusted_mode->crtc_hblank_start - 1) |
5741                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
5742         I915_WRITE(HSYNC(cpu_transcoder),
5743                    (adjusted_mode->crtc_hsync_start - 1) |
5744                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
5745
5746         I915_WRITE(VTOTAL(cpu_transcoder),
5747                    (adjusted_mode->crtc_vdisplay - 1) |
5748                    ((crtc_vtotal - 1) << 16));
5749         I915_WRITE(VBLANK(cpu_transcoder),
5750                    (adjusted_mode->crtc_vblank_start - 1) |
5751                    ((crtc_vblank_end - 1) << 16));
5752         I915_WRITE(VSYNC(cpu_transcoder),
5753                    (adjusted_mode->crtc_vsync_start - 1) |
5754                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
5755
5756         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5757          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5758          * documented on the DDI_FUNC_CTL register description, EDP Input Select
5759          * bits. */
5760         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5761             (pipe == PIPE_B || pipe == PIPE_C))
5762                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5763
5764         /* pipesrc controls the size that is scaled from, which should
5765          * always be the user's requested size.
5766          */
5767         I915_WRITE(PIPESRC(pipe),
5768                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
5769                    (intel_crtc->config.pipe_src_h - 1));
5770 }
5771
5772 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5773                                    struct intel_crtc_config *pipe_config)
5774 {
5775         struct drm_device *dev = crtc->base.dev;
5776         struct drm_i915_private *dev_priv = dev->dev_private;
5777         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5778         uint32_t tmp;
5779
5780         tmp = I915_READ(HTOTAL(cpu_transcoder));
5781         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5782         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5783         tmp = I915_READ(HBLANK(cpu_transcoder));
5784         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5785         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5786         tmp = I915_READ(HSYNC(cpu_transcoder));
5787         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5788         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5789
5790         tmp = I915_READ(VTOTAL(cpu_transcoder));
5791         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5792         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5793         tmp = I915_READ(VBLANK(cpu_transcoder));
5794         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5795         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5796         tmp = I915_READ(VSYNC(cpu_transcoder));
5797         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5798         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5799
5800         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5801                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5802                 pipe_config->adjusted_mode.crtc_vtotal += 1;
5803                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5804         }
5805
5806         tmp = I915_READ(PIPESRC(crtc->pipe));
5807         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5808         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5809
5810         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5811         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5812 }
5813
5814 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5815                                  struct intel_crtc_config *pipe_config)
5816 {
5817         mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5818         mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5819         mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5820         mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5821
5822         mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5823         mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5824         mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5825         mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5826
5827         mode->flags = pipe_config->adjusted_mode.flags;
5828
5829         mode->clock = pipe_config->adjusted_mode.crtc_clock;
5830         mode->flags |= pipe_config->adjusted_mode.flags;
5831 }
5832
5833 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5834 {
5835         struct drm_device *dev = intel_crtc->base.dev;
5836         struct drm_i915_private *dev_priv = dev->dev_private;
5837         uint32_t pipeconf;
5838
5839         pipeconf = 0;
5840
5841         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5842             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5843                 pipeconf |= PIPECONF_ENABLE;
5844
5845         if (intel_crtc->config.double_wide)
5846                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5847
5848         /* only g4x and later have fancy bpc/dither controls */
5849         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5850                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5851                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5852                         pipeconf |= PIPECONF_DITHER_EN |
5853                                     PIPECONF_DITHER_TYPE_SP;
5854
5855                 switch (intel_crtc->config.pipe_bpp) {
5856                 case 18:
5857                         pipeconf |= PIPECONF_6BPC;
5858                         break;
5859                 case 24:
5860                         pipeconf |= PIPECONF_8BPC;
5861                         break;
5862                 case 30:
5863                         pipeconf |= PIPECONF_10BPC;
5864                         break;
5865                 default:
5866                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5867                         BUG();
5868                 }
5869         }
5870
5871         if (HAS_PIPE_CXSR(dev)) {
5872                 if (intel_crtc->lowfreq_avail) {
5873                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5874                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5875                 } else {
5876                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5877                 }
5878         }
5879
5880         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5881                 if (INTEL_INFO(dev)->gen < 4 ||
5882                     intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5883                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5884                 else
5885                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5886         } else
5887                 pipeconf |= PIPECONF_PROGRESSIVE;
5888
5889         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5890                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5891
5892         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5893         POSTING_READ(PIPECONF(intel_crtc->pipe));
5894 }
5895
5896 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5897                               int x, int y,
5898                               struct drm_framebuffer *fb)
5899 {
5900         struct drm_device *dev = crtc->dev;
5901         struct drm_i915_private *dev_priv = dev->dev_private;
5902         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5903         int refclk, num_connectors = 0;
5904         intel_clock_t clock, reduced_clock;
5905         bool ok, has_reduced_clock = false;
5906         bool is_lvds = false, is_dsi = false;
5907         struct intel_encoder *encoder;
5908         const intel_limit_t *limit;
5909
5910         for_each_encoder_on_crtc(dev, crtc, encoder) {
5911                 switch (encoder->type) {
5912                 case INTEL_OUTPUT_LVDS:
5913                         is_lvds = true;
5914                         break;
5915                 case INTEL_OUTPUT_DSI:
5916                         is_dsi = true;
5917                         break;
5918                 }
5919
5920                 num_connectors++;
5921         }
5922
5923         if (is_dsi)
5924                 return 0;
5925
5926         if (!intel_crtc->config.clock_set) {
5927                 refclk = i9xx_get_refclk(crtc, num_connectors);
5928
5929                 /*
5930                  * Returns a set of divisors for the desired target clock with
5931                  * the given refclk, or FALSE.  The returned values represent
5932                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5933                  * 2) / p1 / p2.
5934                  */
5935                 limit = intel_limit(crtc, refclk);
5936                 ok = dev_priv->display.find_dpll(limit, crtc,
5937                                                  intel_crtc->config.port_clock,
5938                                                  refclk, NULL, &clock);
5939                 if (!ok) {
5940                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5941                         return -EINVAL;
5942                 }
5943
5944                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5945                         /*
5946                          * Ensure we match the reduced clock's P to the target
5947                          * clock.  If the clocks don't match, we can't switch
5948                          * the display clock by using the FP0/FP1. In such case
5949                          * we will disable the LVDS downclock feature.
5950                          */
5951                         has_reduced_clock =
5952                                 dev_priv->display.find_dpll(limit, crtc,
5953                                                             dev_priv->lvds_downclock,
5954                                                             refclk, &clock,
5955                                                             &reduced_clock);
5956                 }
5957                 /* Compat-code for transition, will disappear. */
5958                 intel_crtc->config.dpll.n = clock.n;
5959                 intel_crtc->config.dpll.m1 = clock.m1;
5960                 intel_crtc->config.dpll.m2 = clock.m2;
5961                 intel_crtc->config.dpll.p1 = clock.p1;
5962                 intel_crtc->config.dpll.p2 = clock.p2;
5963         }
5964
5965         if (IS_GEN2(dev)) {
5966                 i8xx_update_pll(intel_crtc,
5967                                 has_reduced_clock ? &reduced_clock : NULL,
5968                                 num_connectors);
5969         } else if (IS_CHERRYVIEW(dev)) {
5970                 chv_update_pll(intel_crtc);
5971         } else if (IS_VALLEYVIEW(dev)) {
5972                 vlv_update_pll(intel_crtc);
5973         } else {
5974                 i9xx_update_pll(intel_crtc,
5975                                 has_reduced_clock ? &reduced_clock : NULL,
5976                                 num_connectors);
5977         }
5978
5979         return 0;
5980 }
5981
5982 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5983                                  struct intel_crtc_config *pipe_config)
5984 {
5985         struct drm_device *dev = crtc->base.dev;
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987         uint32_t tmp;
5988
5989         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5990                 return;
5991
5992         tmp = I915_READ(PFIT_CONTROL);
5993         if (!(tmp & PFIT_ENABLE))
5994                 return;
5995
5996         /* Check whether the pfit is attached to our pipe. */
5997         if (INTEL_INFO(dev)->gen < 4) {
5998                 if (crtc->pipe != PIPE_B)
5999                         return;
6000         } else {
6001                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6002                         return;
6003         }
6004
6005         pipe_config->gmch_pfit.control = tmp;
6006         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6007         if (INTEL_INFO(dev)->gen < 5)
6008                 pipe_config->gmch_pfit.lvds_border_bits =
6009                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6010 }
6011
6012 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6013                                struct intel_crtc_config *pipe_config)
6014 {
6015         struct drm_device *dev = crtc->base.dev;
6016         struct drm_i915_private *dev_priv = dev->dev_private;
6017         int pipe = pipe_config->cpu_transcoder;
6018         intel_clock_t clock;
6019         u32 mdiv;
6020         int refclk = 100000;
6021
6022         mutex_lock(&dev_priv->dpio_lock);
6023         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6024         mutex_unlock(&dev_priv->dpio_lock);
6025
6026         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6027         clock.m2 = mdiv & DPIO_M2DIV_MASK;
6028         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6029         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6030         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6031
6032         vlv_clock(refclk, &clock);
6033
6034         /* clock.dot is the fast clock */
6035         pipe_config->port_clock = clock.dot / 5;
6036 }
6037
6038 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6039                                   struct intel_plane_config *plane_config)
6040 {
6041         struct drm_device *dev = crtc->base.dev;
6042         struct drm_i915_private *dev_priv = dev->dev_private;
6043         u32 val, base, offset;
6044         int pipe = crtc->pipe, plane = crtc->plane;
6045         int fourcc, pixel_format;
6046         int aligned_height;
6047
6048         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6049         if (!crtc->base.primary->fb) {
6050                 DRM_DEBUG_KMS("failed to alloc fb\n");
6051                 return;
6052         }
6053
6054         val = I915_READ(DSPCNTR(plane));
6055
6056         if (INTEL_INFO(dev)->gen >= 4)
6057                 if (val & DISPPLANE_TILED)
6058                         plane_config->tiled = true;
6059
6060         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6061         fourcc = intel_format_to_fourcc(pixel_format);
6062         crtc->base.primary->fb->pixel_format = fourcc;
6063         crtc->base.primary->fb->bits_per_pixel =
6064                 drm_format_plane_cpp(fourcc, 0) * 8;
6065
6066         if (INTEL_INFO(dev)->gen >= 4) {
6067                 if (plane_config->tiled)
6068                         offset = I915_READ(DSPTILEOFF(plane));
6069                 else
6070                         offset = I915_READ(DSPLINOFF(plane));
6071                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6072         } else {
6073                 base = I915_READ(DSPADDR(plane));
6074         }
6075         plane_config->base = base;
6076
6077         val = I915_READ(PIPESRC(pipe));
6078         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6079         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6080
6081         val = I915_READ(DSPSTRIDE(pipe));
6082         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6083
6084         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6085                                             plane_config->tiled);
6086
6087         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6088                                    aligned_height, PAGE_SIZE);
6089
6090         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6091                       pipe, plane, crtc->base.primary->fb->width,
6092                       crtc->base.primary->fb->height,
6093                       crtc->base.primary->fb->bits_per_pixel, base,
6094                       crtc->base.primary->fb->pitches[0],
6095                       plane_config->size);
6096
6097 }
6098
6099 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6100                                struct intel_crtc_config *pipe_config)
6101 {
6102         struct drm_device *dev = crtc->base.dev;
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         int pipe = pipe_config->cpu_transcoder;
6105         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6106         intel_clock_t clock;
6107         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6108         int refclk = 100000;
6109
6110         mutex_lock(&dev_priv->dpio_lock);
6111         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6112         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6113         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6114         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6115         mutex_unlock(&dev_priv->dpio_lock);
6116
6117         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6118         clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6119         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6120         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6121         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6122
6123         chv_clock(refclk, &clock);
6124
6125         /* clock.dot is the fast clock */
6126         pipe_config->port_clock = clock.dot / 5;
6127 }
6128
6129 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6130                                  struct intel_crtc_config *pipe_config)
6131 {
6132         struct drm_device *dev = crtc->base.dev;
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134         uint32_t tmp;
6135
6136         if (!intel_display_power_enabled(dev_priv,
6137                                          POWER_DOMAIN_PIPE(crtc->pipe)))
6138                 return false;
6139
6140         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6141         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6142
6143         tmp = I915_READ(PIPECONF(crtc->pipe));
6144         if (!(tmp & PIPECONF_ENABLE))
6145                 return false;
6146
6147         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6148                 switch (tmp & PIPECONF_BPC_MASK) {
6149                 case PIPECONF_6BPC:
6150                         pipe_config->pipe_bpp = 18;
6151                         break;
6152                 case PIPECONF_8BPC:
6153                         pipe_config->pipe_bpp = 24;
6154                         break;
6155                 case PIPECONF_10BPC:
6156                         pipe_config->pipe_bpp = 30;
6157                         break;
6158                 default:
6159                         break;
6160                 }
6161         }
6162
6163         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6164                 pipe_config->limited_color_range = true;
6165
6166         if (INTEL_INFO(dev)->gen < 4)
6167                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6168
6169         intel_get_pipe_timings(crtc, pipe_config);
6170
6171         i9xx_get_pfit_config(crtc, pipe_config);
6172
6173         if (INTEL_INFO(dev)->gen >= 4) {
6174                 tmp = I915_READ(DPLL_MD(crtc->pipe));
6175                 pipe_config->pixel_multiplier =
6176                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6177                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6178                 pipe_config->dpll_hw_state.dpll_md = tmp;
6179         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6180                 tmp = I915_READ(DPLL(crtc->pipe));
6181                 pipe_config->pixel_multiplier =
6182                         ((tmp & SDVO_MULTIPLIER_MASK)
6183                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6184         } else {
6185                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6186                  * port and will be fixed up in the encoder->get_config
6187                  * function. */
6188                 pipe_config->pixel_multiplier = 1;
6189         }
6190         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6191         if (!IS_VALLEYVIEW(dev)) {
6192                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6193                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6194         } else {
6195                 /* Mask out read-only status bits. */
6196                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6197                                                      DPLL_PORTC_READY_MASK |
6198                                                      DPLL_PORTB_READY_MASK);
6199         }
6200
6201         if (IS_CHERRYVIEW(dev))
6202                 chv_crtc_clock_get(crtc, pipe_config);
6203         else if (IS_VALLEYVIEW(dev))
6204                 vlv_crtc_clock_get(crtc, pipe_config);
6205         else
6206                 i9xx_crtc_clock_get(crtc, pipe_config);
6207
6208         return true;
6209 }
6210
6211 static void ironlake_init_pch_refclk(struct drm_device *dev)
6212 {
6213         struct drm_i915_private *dev_priv = dev->dev_private;
6214         struct drm_mode_config *mode_config = &dev->mode_config;
6215         struct intel_encoder *encoder;
6216         u32 val, final;
6217         bool has_lvds = false;
6218         bool has_cpu_edp = false;
6219         bool has_panel = false;
6220         bool has_ck505 = false;
6221         bool can_ssc = false;
6222
6223         /* We need to take the global config into account */
6224         list_for_each_entry(encoder, &mode_config->encoder_list,
6225                             base.head) {
6226                 switch (encoder->type) {
6227                 case INTEL_OUTPUT_LVDS:
6228                         has_panel = true;
6229                         has_lvds = true;
6230                         break;
6231                 case INTEL_OUTPUT_EDP:
6232                         has_panel = true;
6233                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6234                                 has_cpu_edp = true;
6235                         break;
6236                 }
6237         }
6238
6239         if (HAS_PCH_IBX(dev)) {
6240                 has_ck505 = dev_priv->vbt.display_clock_mode;
6241                 can_ssc = has_ck505;
6242         } else {
6243                 has_ck505 = false;
6244                 can_ssc = true;
6245         }
6246
6247         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6248                       has_panel, has_lvds, has_ck505);
6249
6250         /* Ironlake: try to setup display ref clock before DPLL
6251          * enabling. This is only under driver's control after
6252          * PCH B stepping, previous chipset stepping should be
6253          * ignoring this setting.
6254          */
6255         val = I915_READ(PCH_DREF_CONTROL);
6256
6257         /* As we must carefully and slowly disable/enable each source in turn,
6258          * compute the final state we want first and check if we need to
6259          * make any changes at all.
6260          */
6261         final = val;
6262         final &= ~DREF_NONSPREAD_SOURCE_MASK;
6263         if (has_ck505)
6264                 final |= DREF_NONSPREAD_CK505_ENABLE;
6265         else
6266                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6267
6268         final &= ~DREF_SSC_SOURCE_MASK;
6269         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6270         final &= ~DREF_SSC1_ENABLE;
6271
6272         if (has_panel) {
6273                 final |= DREF_SSC_SOURCE_ENABLE;
6274
6275                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6276                         final |= DREF_SSC1_ENABLE;
6277
6278                 if (has_cpu_edp) {
6279                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
6280                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6281                         else
6282                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6283                 } else
6284                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6285         } else {
6286                 final |= DREF_SSC_SOURCE_DISABLE;
6287                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6288         }
6289
6290         if (final == val)
6291                 return;
6292
6293         /* Always enable nonspread source */
6294         val &= ~DREF_NONSPREAD_SOURCE_MASK;
6295
6296         if (has_ck505)
6297                 val |= DREF_NONSPREAD_CK505_ENABLE;
6298         else
6299                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6300
6301         if (has_panel) {
6302                 val &= ~DREF_SSC_SOURCE_MASK;
6303                 val |= DREF_SSC_SOURCE_ENABLE;
6304
6305                 /* SSC must be turned on before enabling the CPU output  */
6306                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6307                         DRM_DEBUG_KMS("Using SSC on panel\n");
6308                         val |= DREF_SSC1_ENABLE;
6309                 } else
6310                         val &= ~DREF_SSC1_ENABLE;
6311
6312                 /* Get SSC going before enabling the outputs */
6313                 I915_WRITE(PCH_DREF_CONTROL, val);
6314                 POSTING_READ(PCH_DREF_CONTROL);
6315                 udelay(200);
6316
6317                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6318
6319                 /* Enable CPU source on CPU attached eDP */
6320                 if (has_cpu_edp) {
6321                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6322                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
6323                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6324                         } else
6325                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6326                 } else
6327                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6328
6329                 I915_WRITE(PCH_DREF_CONTROL, val);
6330                 POSTING_READ(PCH_DREF_CONTROL);
6331                 udelay(200);
6332         } else {
6333                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6334
6335                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6336
6337                 /* Turn off CPU output */
6338                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6339
6340                 I915_WRITE(PCH_DREF_CONTROL, val);
6341                 POSTING_READ(PCH_DREF_CONTROL);
6342                 udelay(200);
6343
6344                 /* Turn off the SSC source */
6345                 val &= ~DREF_SSC_SOURCE_MASK;
6346                 val |= DREF_SSC_SOURCE_DISABLE;
6347
6348                 /* Turn off SSC1 */
6349                 val &= ~DREF_SSC1_ENABLE;
6350
6351                 I915_WRITE(PCH_DREF_CONTROL, val);
6352                 POSTING_READ(PCH_DREF_CONTROL);
6353                 udelay(200);
6354         }
6355
6356         BUG_ON(val != final);
6357 }
6358
6359 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6360 {
6361         uint32_t tmp;
6362
6363         tmp = I915_READ(SOUTH_CHICKEN2);
6364         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6365         I915_WRITE(SOUTH_CHICKEN2, tmp);
6366
6367         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6368                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6369                 DRM_ERROR("FDI mPHY reset assert timeout\n");
6370
6371         tmp = I915_READ(SOUTH_CHICKEN2);
6372         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6373         I915_WRITE(SOUTH_CHICKEN2, tmp);
6374
6375         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6376                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6377                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6378 }
6379
6380 /* WaMPhyProgramming:hsw */
6381 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6382 {
6383         uint32_t tmp;
6384
6385         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6386         tmp &= ~(0xFF << 24);
6387         tmp |= (0x12 << 24);
6388         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6389
6390         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6391         tmp |= (1 << 11);
6392         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6393
6394         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6395         tmp |= (1 << 11);
6396         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6397
6398         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6399         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6400         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6401
6402         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6403         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6404         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6405
6406         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6407         tmp &= ~(7 << 13);
6408         tmp |= (5 << 13);
6409         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6410
6411         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6412         tmp &= ~(7 << 13);
6413         tmp |= (5 << 13);
6414         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6415
6416         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6417         tmp &= ~0xFF;
6418         tmp |= 0x1C;
6419         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6420
6421         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6422         tmp &= ~0xFF;
6423         tmp |= 0x1C;
6424         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6425
6426         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6427         tmp &= ~(0xFF << 16);
6428         tmp |= (0x1C << 16);
6429         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6430
6431         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6432         tmp &= ~(0xFF << 16);
6433         tmp |= (0x1C << 16);
6434         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6435
6436         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6437         tmp |= (1 << 27);
6438         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6439
6440         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6441         tmp |= (1 << 27);
6442         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6443
6444         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6445         tmp &= ~(0xF << 28);
6446         tmp |= (4 << 28);
6447         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6448
6449         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6450         tmp &= ~(0xF << 28);
6451         tmp |= (4 << 28);
6452         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6453 }
6454
6455 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6456  * Programming" based on the parameters passed:
6457  * - Sequence to enable CLKOUT_DP
6458  * - Sequence to enable CLKOUT_DP without spread
6459  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6460  */
6461 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6462                                  bool with_fdi)
6463 {
6464         struct drm_i915_private *dev_priv = dev->dev_private;
6465         uint32_t reg, tmp;
6466
6467         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6468                 with_spread = true;
6469         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6470                  with_fdi, "LP PCH doesn't have FDI\n"))
6471                 with_fdi = false;
6472
6473         mutex_lock(&dev_priv->dpio_lock);
6474
6475         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6476         tmp &= ~SBI_SSCCTL_DISABLE;
6477         tmp |= SBI_SSCCTL_PATHALT;
6478         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6479
6480         udelay(24);
6481
6482         if (with_spread) {
6483                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6484                 tmp &= ~SBI_SSCCTL_PATHALT;
6485                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6486
6487                 if (with_fdi) {
6488                         lpt_reset_fdi_mphy(dev_priv);
6489                         lpt_program_fdi_mphy(dev_priv);
6490                 }
6491         }
6492
6493         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6494                SBI_GEN0 : SBI_DBUFF0;
6495         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6496         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6497         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6498
6499         mutex_unlock(&dev_priv->dpio_lock);
6500 }
6501
6502 /* Sequence to disable CLKOUT_DP */
6503 static void lpt_disable_clkout_dp(struct drm_device *dev)
6504 {
6505         struct drm_i915_private *dev_priv = dev->dev_private;
6506         uint32_t reg, tmp;
6507
6508         mutex_lock(&dev_priv->dpio_lock);
6509
6510         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6511                SBI_GEN0 : SBI_DBUFF0;
6512         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6513         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6514         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6515
6516         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6517         if (!(tmp & SBI_SSCCTL_DISABLE)) {
6518                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6519                         tmp |= SBI_SSCCTL_PATHALT;
6520                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6521                         udelay(32);
6522                 }
6523                 tmp |= SBI_SSCCTL_DISABLE;
6524                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6525         }
6526
6527         mutex_unlock(&dev_priv->dpio_lock);
6528 }
6529
6530 static void lpt_init_pch_refclk(struct drm_device *dev)
6531 {
6532         struct drm_mode_config *mode_config = &dev->mode_config;
6533         struct intel_encoder *encoder;
6534         bool has_vga = false;
6535
6536         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6537                 switch (encoder->type) {
6538                 case INTEL_OUTPUT_ANALOG:
6539                         has_vga = true;
6540                         break;
6541                 }
6542         }
6543
6544         if (has_vga)
6545                 lpt_enable_clkout_dp(dev, true, true);
6546         else
6547                 lpt_disable_clkout_dp(dev);
6548 }
6549
6550 /*
6551  * Initialize reference clocks when the driver loads
6552  */
6553 void intel_init_pch_refclk(struct drm_device *dev)
6554 {
6555         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6556                 ironlake_init_pch_refclk(dev);
6557         else if (HAS_PCH_LPT(dev))
6558                 lpt_init_pch_refclk(dev);
6559 }
6560
6561 static int ironlake_get_refclk(struct drm_crtc *crtc)
6562 {
6563         struct drm_device *dev = crtc->dev;
6564         struct drm_i915_private *dev_priv = dev->dev_private;
6565         struct intel_encoder *encoder;
6566         int num_connectors = 0;
6567         bool is_lvds = false;
6568
6569         for_each_encoder_on_crtc(dev, crtc, encoder) {
6570                 switch (encoder->type) {
6571                 case INTEL_OUTPUT_LVDS:
6572                         is_lvds = true;
6573                         break;
6574                 }
6575                 num_connectors++;
6576         }
6577
6578         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6579                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6580                               dev_priv->vbt.lvds_ssc_freq);
6581                 return dev_priv->vbt.lvds_ssc_freq;
6582         }
6583
6584         return 120000;
6585 }
6586
6587 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6588 {
6589         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591         int pipe = intel_crtc->pipe;
6592         uint32_t val;
6593
6594         val = 0;
6595
6596         switch (intel_crtc->config.pipe_bpp) {
6597         case 18:
6598                 val |= PIPECONF_6BPC;
6599                 break;
6600         case 24:
6601                 val |= PIPECONF_8BPC;
6602                 break;
6603         case 30:
6604                 val |= PIPECONF_10BPC;
6605                 break;
6606         case 36:
6607                 val |= PIPECONF_12BPC;
6608                 break;
6609         default:
6610                 /* Case prevented by intel_choose_pipe_bpp_dither. */
6611                 BUG();
6612         }
6613
6614         if (intel_crtc->config.dither)
6615                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6616
6617         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6618                 val |= PIPECONF_INTERLACED_ILK;
6619         else
6620                 val |= PIPECONF_PROGRESSIVE;
6621
6622         if (intel_crtc->config.limited_color_range)
6623                 val |= PIPECONF_COLOR_RANGE_SELECT;
6624
6625         I915_WRITE(PIPECONF(pipe), val);
6626         POSTING_READ(PIPECONF(pipe));
6627 }
6628
6629 /*
6630  * Set up the pipe CSC unit.
6631  *
6632  * Currently only full range RGB to limited range RGB conversion
6633  * is supported, but eventually this should handle various
6634  * RGB<->YCbCr scenarios as well.
6635  */
6636 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6637 {
6638         struct drm_device *dev = crtc->dev;
6639         struct drm_i915_private *dev_priv = dev->dev_private;
6640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6641         int pipe = intel_crtc->pipe;
6642         uint16_t coeff = 0x7800; /* 1.0 */
6643
6644         /*
6645          * TODO: Check what kind of values actually come out of the pipe
6646          * with these coeff/postoff values and adjust to get the best
6647          * accuracy. Perhaps we even need to take the bpc value into
6648          * consideration.
6649          */
6650
6651         if (intel_crtc->config.limited_color_range)
6652                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6653
6654         /*
6655          * GY/GU and RY/RU should be the other way around according
6656          * to BSpec, but reality doesn't agree. Just set them up in
6657          * a way that results in the correct picture.
6658          */
6659         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6660         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6661
6662         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6663         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6664
6665         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6666         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6667
6668         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6669         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6670         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6671
6672         if (INTEL_INFO(dev)->gen > 6) {
6673                 uint16_t postoff = 0;
6674
6675                 if (intel_crtc->config.limited_color_range)
6676                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
6677
6678                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6679                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6680                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6681
6682                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6683         } else {
6684                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6685
6686                 if (intel_crtc->config.limited_color_range)
6687                         mode |= CSC_BLACK_SCREEN_OFFSET;
6688
6689                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6690         }
6691 }
6692
6693 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6694 {
6695         struct drm_device *dev = crtc->dev;
6696         struct drm_i915_private *dev_priv = dev->dev_private;
6697         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6698         enum pipe pipe = intel_crtc->pipe;
6699         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6700         uint32_t val;
6701
6702         val = 0;
6703
6704         if (IS_HASWELL(dev) && intel_crtc->config.dither)
6705                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6706
6707         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6708                 val |= PIPECONF_INTERLACED_ILK;
6709         else
6710                 val |= PIPECONF_PROGRESSIVE;
6711
6712         I915_WRITE(PIPECONF(cpu_transcoder), val);
6713         POSTING_READ(PIPECONF(cpu_transcoder));
6714
6715         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6716         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6717
6718         if (IS_BROADWELL(dev)) {
6719                 val = 0;
6720
6721                 switch (intel_crtc->config.pipe_bpp) {
6722                 case 18:
6723                         val |= PIPEMISC_DITHER_6_BPC;
6724                         break;
6725                 case 24:
6726                         val |= PIPEMISC_DITHER_8_BPC;
6727                         break;
6728                 case 30:
6729                         val |= PIPEMISC_DITHER_10_BPC;
6730                         break;
6731                 case 36:
6732                         val |= PIPEMISC_DITHER_12_BPC;
6733                         break;
6734                 default:
6735                         /* Case prevented by pipe_config_set_bpp. */
6736                         BUG();
6737                 }
6738
6739                 if (intel_crtc->config.dither)
6740                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6741
6742                 I915_WRITE(PIPEMISC(pipe), val);
6743         }
6744 }
6745
6746 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6747                                     intel_clock_t *clock,
6748                                     bool *has_reduced_clock,
6749                                     intel_clock_t *reduced_clock)
6750 {
6751         struct drm_device *dev = crtc->dev;
6752         struct drm_i915_private *dev_priv = dev->dev_private;
6753         struct intel_encoder *intel_encoder;
6754         int refclk;
6755         const intel_limit_t *limit;
6756         bool ret, is_lvds = false;
6757
6758         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6759                 switch (intel_encoder->type) {
6760                 case INTEL_OUTPUT_LVDS:
6761                         is_lvds = true;
6762                         break;
6763                 }
6764         }
6765
6766         refclk = ironlake_get_refclk(crtc);
6767
6768         /*
6769          * Returns a set of divisors for the desired target clock with the given
6770          * refclk, or FALSE.  The returned values represent the clock equation:
6771          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6772          */
6773         limit = intel_limit(crtc, refclk);
6774         ret = dev_priv->display.find_dpll(limit, crtc,
6775                                           to_intel_crtc(crtc)->config.port_clock,
6776                                           refclk, NULL, clock);
6777         if (!ret)
6778                 return false;
6779
6780         if (is_lvds && dev_priv->lvds_downclock_avail) {
6781                 /*
6782                  * Ensure we match the reduced clock's P to the target clock.
6783                  * If the clocks don't match, we can't switch the display clock
6784                  * by using the FP0/FP1. In such case we will disable the LVDS
6785                  * downclock feature.
6786                 */
6787                 *has_reduced_clock =
6788                         dev_priv->display.find_dpll(limit, crtc,
6789                                                     dev_priv->lvds_downclock,
6790                                                     refclk, clock,
6791                                                     reduced_clock);
6792         }
6793
6794         return true;
6795 }
6796
6797 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6798 {
6799         /*
6800          * Account for spread spectrum to avoid
6801          * oversubscribing the link. Max center spread
6802          * is 2.5%; use 5% for safety's sake.
6803          */
6804         u32 bps = target_clock * bpp * 21 / 20;
6805         return DIV_ROUND_UP(bps, link_bw * 8);
6806 }
6807
6808 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6809 {
6810         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6811 }
6812
6813 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6814                                       u32 *fp,
6815                                       intel_clock_t *reduced_clock, u32 *fp2)
6816 {
6817         struct drm_crtc *crtc = &intel_crtc->base;
6818         struct drm_device *dev = crtc->dev;
6819         struct drm_i915_private *dev_priv = dev->dev_private;
6820         struct intel_encoder *intel_encoder;
6821         uint32_t dpll;
6822         int factor, num_connectors = 0;
6823         bool is_lvds = false, is_sdvo = false;
6824
6825         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6826                 switch (intel_encoder->type) {
6827                 case INTEL_OUTPUT_LVDS:
6828                         is_lvds = true;
6829                         break;
6830                 case INTEL_OUTPUT_SDVO:
6831                 case INTEL_OUTPUT_HDMI:
6832                         is_sdvo = true;
6833                         break;
6834                 }
6835
6836                 num_connectors++;
6837         }
6838
6839         /* Enable autotuning of the PLL clock (if permissible) */
6840         factor = 21;
6841         if (is_lvds) {
6842                 if ((intel_panel_use_ssc(dev_priv) &&
6843                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
6844                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6845                         factor = 25;
6846         } else if (intel_crtc->config.sdvo_tv_clock)
6847                 factor = 20;
6848
6849         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6850                 *fp |= FP_CB_TUNE;
6851
6852         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6853                 *fp2 |= FP_CB_TUNE;
6854
6855         dpll = 0;
6856
6857         if (is_lvds)
6858                 dpll |= DPLLB_MODE_LVDS;
6859         else
6860                 dpll |= DPLLB_MODE_DAC_SERIAL;
6861
6862         dpll |= (intel_crtc->config.pixel_multiplier - 1)
6863                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6864
6865         if (is_sdvo)
6866                 dpll |= DPLL_SDVO_HIGH_SPEED;
6867         if (intel_crtc->config.has_dp_encoder)
6868                 dpll |= DPLL_SDVO_HIGH_SPEED;
6869
6870         /* compute bitmask from p1 value */
6871         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6872         /* also FPA1 */
6873         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6874
6875         switch (intel_crtc->config.dpll.p2) {
6876         case 5:
6877                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6878                 break;
6879         case 7:
6880                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6881                 break;
6882         case 10:
6883                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6884                 break;
6885         case 14:
6886                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6887                 break;
6888         }
6889
6890         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6891                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6892         else
6893                 dpll |= PLL_REF_INPUT_DREFCLK;
6894
6895         return dpll | DPLL_VCO_ENABLE;
6896 }
6897
6898 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6899                                   int x, int y,
6900                                   struct drm_framebuffer *fb)
6901 {
6902         struct drm_device *dev = crtc->dev;
6903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6904         int num_connectors = 0;
6905         intel_clock_t clock, reduced_clock;
6906         u32 dpll = 0, fp = 0, fp2 = 0;
6907         bool ok, has_reduced_clock = false;
6908         bool is_lvds = false;
6909         struct intel_encoder *encoder;
6910         struct intel_shared_dpll *pll;
6911
6912         for_each_encoder_on_crtc(dev, crtc, encoder) {
6913                 switch (encoder->type) {
6914                 case INTEL_OUTPUT_LVDS:
6915                         is_lvds = true;
6916                         break;
6917                 }
6918
6919                 num_connectors++;
6920         }
6921
6922         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6923              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6924
6925         ok = ironlake_compute_clocks(crtc, &clock,
6926                                      &has_reduced_clock, &reduced_clock);
6927         if (!ok && !intel_crtc->config.clock_set) {
6928                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6929                 return -EINVAL;
6930         }
6931         /* Compat-code for transition, will disappear. */
6932         if (!intel_crtc->config.clock_set) {
6933                 intel_crtc->config.dpll.n = clock.n;
6934                 intel_crtc->config.dpll.m1 = clock.m1;
6935                 intel_crtc->config.dpll.m2 = clock.m2;
6936                 intel_crtc->config.dpll.p1 = clock.p1;
6937                 intel_crtc->config.dpll.p2 = clock.p2;
6938         }
6939
6940         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6941         if (intel_crtc->config.has_pch_encoder) {
6942                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6943                 if (has_reduced_clock)
6944                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6945
6946                 dpll = ironlake_compute_dpll(intel_crtc,
6947                                              &fp, &reduced_clock,
6948                                              has_reduced_clock ? &fp2 : NULL);
6949
6950                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6951                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6952                 if (has_reduced_clock)
6953                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6954                 else
6955                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6956
6957                 pll = intel_get_shared_dpll(intel_crtc);
6958                 if (pll == NULL) {
6959                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6960                                          pipe_name(intel_crtc->pipe));
6961                         return -EINVAL;
6962                 }
6963         } else
6964                 intel_put_shared_dpll(intel_crtc);
6965
6966         if (is_lvds && has_reduced_clock && i915.powersave)
6967                 intel_crtc->lowfreq_avail = true;
6968         else
6969                 intel_crtc->lowfreq_avail = false;
6970
6971         return 0;
6972 }
6973
6974 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6975                                          struct intel_link_m_n *m_n)
6976 {
6977         struct drm_device *dev = crtc->base.dev;
6978         struct drm_i915_private *dev_priv = dev->dev_private;
6979         enum pipe pipe = crtc->pipe;
6980
6981         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6982         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6983         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6984                 & ~TU_SIZE_MASK;
6985         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6986         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6987                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6988 }
6989
6990 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6991                                          enum transcoder transcoder,
6992                                          struct intel_link_m_n *m_n)
6993 {
6994         struct drm_device *dev = crtc->base.dev;
6995         struct drm_i915_private *dev_priv = dev->dev_private;
6996         enum pipe pipe = crtc->pipe;
6997
6998         if (INTEL_INFO(dev)->gen >= 5) {
6999                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7000                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7001                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7002                         & ~TU_SIZE_MASK;
7003                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7004                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7005                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7006         } else {
7007                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7008                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7009                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7010                         & ~TU_SIZE_MASK;
7011                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7012                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7013                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7014         }
7015 }
7016
7017 void intel_dp_get_m_n(struct intel_crtc *crtc,
7018                       struct intel_crtc_config *pipe_config)
7019 {
7020         if (crtc->config.has_pch_encoder)
7021                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7022         else
7023                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7024                                              &pipe_config->dp_m_n);
7025 }
7026
7027 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7028                                         struct intel_crtc_config *pipe_config)
7029 {
7030         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7031                                      &pipe_config->fdi_m_n);
7032 }
7033
7034 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7035                                      struct intel_crtc_config *pipe_config)
7036 {
7037         struct drm_device *dev = crtc->base.dev;
7038         struct drm_i915_private *dev_priv = dev->dev_private;
7039         uint32_t tmp;
7040
7041         tmp = I915_READ(PF_CTL(crtc->pipe));
7042
7043         if (tmp & PF_ENABLE) {
7044                 pipe_config->pch_pfit.enabled = true;
7045                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7046                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7047
7048                 /* We currently do not free assignements of panel fitters on
7049                  * ivb/hsw (since we don't use the higher upscaling modes which
7050                  * differentiates them) so just WARN about this case for now. */
7051                 if (IS_GEN7(dev)) {
7052                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7053                                 PF_PIPE_SEL_IVB(crtc->pipe));
7054                 }
7055         }
7056 }
7057
7058 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7059                                       struct intel_plane_config *plane_config)
7060 {
7061         struct drm_device *dev = crtc->base.dev;
7062         struct drm_i915_private *dev_priv = dev->dev_private;
7063         u32 val, base, offset;
7064         int pipe = crtc->pipe, plane = crtc->plane;
7065         int fourcc, pixel_format;
7066         int aligned_height;
7067
7068         crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7069         if (!crtc->base.primary->fb) {
7070                 DRM_DEBUG_KMS("failed to alloc fb\n");
7071                 return;
7072         }
7073
7074         val = I915_READ(DSPCNTR(plane));
7075
7076         if (INTEL_INFO(dev)->gen >= 4)
7077                 if (val & DISPPLANE_TILED)
7078                         plane_config->tiled = true;
7079
7080         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7081         fourcc = intel_format_to_fourcc(pixel_format);
7082         crtc->base.primary->fb->pixel_format = fourcc;
7083         crtc->base.primary->fb->bits_per_pixel =
7084                 drm_format_plane_cpp(fourcc, 0) * 8;
7085
7086         base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7087         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7088                 offset = I915_READ(DSPOFFSET(plane));
7089         } else {
7090                 if (plane_config->tiled)
7091                         offset = I915_READ(DSPTILEOFF(plane));
7092                 else
7093                         offset = I915_READ(DSPLINOFF(plane));
7094         }
7095         plane_config->base = base;
7096
7097         val = I915_READ(PIPESRC(pipe));
7098         crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7099         crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7100
7101         val = I915_READ(DSPSTRIDE(pipe));
7102         crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7103
7104         aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7105                                             plane_config->tiled);
7106
7107         plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7108                                    aligned_height, PAGE_SIZE);
7109
7110         DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7111                       pipe, plane, crtc->base.primary->fb->width,
7112                       crtc->base.primary->fb->height,
7113                       crtc->base.primary->fb->bits_per_pixel, base,
7114                       crtc->base.primary->fb->pitches[0],
7115                       plane_config->size);
7116 }
7117
7118 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7119                                      struct intel_crtc_config *pipe_config)
7120 {
7121         struct drm_device *dev = crtc->base.dev;
7122         struct drm_i915_private *dev_priv = dev->dev_private;
7123         uint32_t tmp;
7124
7125         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7126         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7127
7128         tmp = I915_READ(PIPECONF(crtc->pipe));
7129         if (!(tmp & PIPECONF_ENABLE))
7130                 return false;
7131
7132         switch (tmp & PIPECONF_BPC_MASK) {
7133         case PIPECONF_6BPC:
7134                 pipe_config->pipe_bpp = 18;
7135                 break;
7136         case PIPECONF_8BPC:
7137                 pipe_config->pipe_bpp = 24;
7138                 break;
7139         case PIPECONF_10BPC:
7140                 pipe_config->pipe_bpp = 30;
7141                 break;
7142         case PIPECONF_12BPC:
7143                 pipe_config->pipe_bpp = 36;
7144                 break;
7145         default:
7146                 break;
7147         }
7148
7149         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7150                 pipe_config->limited_color_range = true;
7151
7152         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7153                 struct intel_shared_dpll *pll;
7154
7155                 pipe_config->has_pch_encoder = true;
7156
7157                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7158                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7159                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7160
7161                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7162
7163                 if (HAS_PCH_IBX(dev_priv->dev)) {
7164                         pipe_config->shared_dpll =
7165                                 (enum intel_dpll_id) crtc->pipe;
7166                 } else {
7167                         tmp = I915_READ(PCH_DPLL_SEL);
7168                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7169                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7170                         else
7171                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7172                 }
7173
7174                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7175
7176                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7177                                            &pipe_config->dpll_hw_state));
7178
7179                 tmp = pipe_config->dpll_hw_state.dpll;
7180                 pipe_config->pixel_multiplier =
7181                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7182                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7183
7184                 ironlake_pch_clock_get(crtc, pipe_config);
7185         } else {
7186                 pipe_config->pixel_multiplier = 1;
7187         }
7188
7189         intel_get_pipe_timings(crtc, pipe_config);
7190
7191         ironlake_get_pfit_config(crtc, pipe_config);
7192
7193         return true;
7194 }
7195
7196 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7197 {
7198         struct drm_device *dev = dev_priv->dev;
7199         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7200         struct intel_crtc *crtc;
7201
7202         for_each_intel_crtc(dev, crtc)
7203                 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7204                      pipe_name(crtc->pipe));
7205
7206         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7207         WARN(plls->spll_refcount, "SPLL enabled\n");
7208         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7209         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7210         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7211         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7212              "CPU PWM1 enabled\n");
7213         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7214              "CPU PWM2 enabled\n");
7215         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7216              "PCH PWM1 enabled\n");
7217         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7218              "Utility pin enabled\n");
7219         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7220
7221         /*
7222          * In theory we can still leave IRQs enabled, as long as only the HPD
7223          * interrupts remain enabled. We used to check for that, but since it's
7224          * gen-specific and since we only disable LCPLL after we fully disable
7225          * the interrupts, the check below should be enough.
7226          */
7227         WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7228 }
7229
7230 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7231 {
7232         struct drm_device *dev = dev_priv->dev;
7233
7234         if (IS_HASWELL(dev)) {
7235                 mutex_lock(&dev_priv->rps.hw_lock);
7236                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7237                                             val))
7238                         DRM_ERROR("Failed to disable D_COMP\n");
7239                 mutex_unlock(&dev_priv->rps.hw_lock);
7240         } else {
7241                 I915_WRITE(D_COMP, val);
7242         }
7243         POSTING_READ(D_COMP);
7244 }
7245
7246 /*
7247  * This function implements pieces of two sequences from BSpec:
7248  * - Sequence for display software to disable LCPLL
7249  * - Sequence for display software to allow package C8+
7250  * The steps implemented here are just the steps that actually touch the LCPLL
7251  * register. Callers should take care of disabling all the display engine
7252  * functions, doing the mode unset, fixing interrupts, etc.
7253  */
7254 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7255                               bool switch_to_fclk, bool allow_power_down)
7256 {
7257         uint32_t val;
7258
7259         assert_can_disable_lcpll(dev_priv);
7260
7261         val = I915_READ(LCPLL_CTL);
7262
7263         if (switch_to_fclk) {
7264                 val |= LCPLL_CD_SOURCE_FCLK;
7265                 I915_WRITE(LCPLL_CTL, val);
7266
7267                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7268                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
7269                         DRM_ERROR("Switching to FCLK failed\n");
7270
7271                 val = I915_READ(LCPLL_CTL);
7272         }
7273
7274         val |= LCPLL_PLL_DISABLE;
7275         I915_WRITE(LCPLL_CTL, val);
7276         POSTING_READ(LCPLL_CTL);
7277
7278         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7279                 DRM_ERROR("LCPLL still locked\n");
7280
7281         val = I915_READ(D_COMP);
7282         val |= D_COMP_COMP_DISABLE;
7283         hsw_write_dcomp(dev_priv, val);
7284         ndelay(100);
7285
7286         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7287                 DRM_ERROR("D_COMP RCOMP still in progress\n");
7288
7289         if (allow_power_down) {
7290                 val = I915_READ(LCPLL_CTL);
7291                 val |= LCPLL_POWER_DOWN_ALLOW;
7292                 I915_WRITE(LCPLL_CTL, val);
7293                 POSTING_READ(LCPLL_CTL);
7294         }
7295 }
7296
7297 /*
7298  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7299  * source.
7300  */
7301 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7302 {
7303         uint32_t val;
7304         unsigned long irqflags;
7305
7306         val = I915_READ(LCPLL_CTL);
7307
7308         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7309                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7310                 return;
7311
7312         /*
7313          * Make sure we're not on PC8 state before disabling PC8, otherwise
7314          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7315          *
7316          * The other problem is that hsw_restore_lcpll() is called as part of
7317          * the runtime PM resume sequence, so we can't just call
7318          * gen6_gt_force_wake_get() because that function calls
7319          * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7320          * while we are on the resume sequence. So to solve this problem we have
7321          * to call special forcewake code that doesn't touch runtime PM and
7322          * doesn't enable the forcewake delayed work.
7323          */
7324         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7325         if (dev_priv->uncore.forcewake_count++ == 0)
7326                 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7327         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7328
7329         if (val & LCPLL_POWER_DOWN_ALLOW) {
7330                 val &= ~LCPLL_POWER_DOWN_ALLOW;
7331                 I915_WRITE(LCPLL_CTL, val);
7332                 POSTING_READ(LCPLL_CTL);
7333         }
7334
7335         val = I915_READ(D_COMP);
7336         val |= D_COMP_COMP_FORCE;
7337         val &= ~D_COMP_COMP_DISABLE;
7338         hsw_write_dcomp(dev_priv, val);
7339
7340         val = I915_READ(LCPLL_CTL);
7341         val &= ~LCPLL_PLL_DISABLE;
7342         I915_WRITE(LCPLL_CTL, val);
7343
7344         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7345                 DRM_ERROR("LCPLL not locked yet\n");
7346
7347         if (val & LCPLL_CD_SOURCE_FCLK) {
7348                 val = I915_READ(LCPLL_CTL);
7349                 val &= ~LCPLL_CD_SOURCE_FCLK;
7350                 I915_WRITE(LCPLL_CTL, val);
7351
7352                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7353                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7354                         DRM_ERROR("Switching back to LCPLL failed\n");
7355         }
7356
7357         /* See the big comment above. */
7358         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7359         if (--dev_priv->uncore.forcewake_count == 0)
7360                 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7361         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7362 }
7363
7364 /*
7365  * Package states C8 and deeper are really deep PC states that can only be
7366  * reached when all the devices on the system allow it, so even if the graphics
7367  * device allows PC8+, it doesn't mean the system will actually get to these
7368  * states. Our driver only allows PC8+ when going into runtime PM.
7369  *
7370  * The requirements for PC8+ are that all the outputs are disabled, the power
7371  * well is disabled and most interrupts are disabled, and these are also
7372  * requirements for runtime PM. When these conditions are met, we manually do
7373  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7374  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7375  * hang the machine.
7376  *
7377  * When we really reach PC8 or deeper states (not just when we allow it) we lose
7378  * the state of some registers, so when we come back from PC8+ we need to
7379  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7380  * need to take care of the registers kept by RC6. Notice that this happens even
7381  * if we don't put the device in PCI D3 state (which is what currently happens
7382  * because of the runtime PM support).
7383  *
7384  * For more, read "Display Sequences for Package C8" on the hardware
7385  * documentation.
7386  */
7387 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7388 {
7389         struct drm_device *dev = dev_priv->dev;
7390         uint32_t val;
7391
7392         DRM_DEBUG_KMS("Enabling package C8+\n");
7393
7394         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7395                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7396                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7397                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7398         }
7399
7400         lpt_disable_clkout_dp(dev);
7401         hsw_disable_lcpll(dev_priv, true, true);
7402 }
7403
7404 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7405 {
7406         struct drm_device *dev = dev_priv->dev;
7407         uint32_t val;
7408
7409         DRM_DEBUG_KMS("Disabling package C8+\n");
7410
7411         hsw_restore_lcpll(dev_priv);
7412         lpt_init_pch_refclk(dev);
7413
7414         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7415                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7416                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7417                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7418         }
7419
7420         intel_prepare_ddi(dev);
7421 }
7422
7423 static void snb_modeset_global_resources(struct drm_device *dev)
7424 {
7425         modeset_update_crtc_power_domains(dev);
7426 }
7427
7428 static void haswell_modeset_global_resources(struct drm_device *dev)
7429 {
7430         modeset_update_crtc_power_domains(dev);
7431 }
7432
7433 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7434                                  int x, int y,
7435                                  struct drm_framebuffer *fb)
7436 {
7437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7438
7439         if (!intel_ddi_pll_select(intel_crtc))
7440                 return -EINVAL;
7441         intel_ddi_pll_enable(intel_crtc);
7442
7443         intel_crtc->lowfreq_avail = false;
7444
7445         return 0;
7446 }
7447
7448 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7449                                     struct intel_crtc_config *pipe_config)
7450 {
7451         struct drm_device *dev = crtc->base.dev;
7452         struct drm_i915_private *dev_priv = dev->dev_private;
7453         enum intel_display_power_domain pfit_domain;
7454         uint32_t tmp;
7455
7456         if (!intel_display_power_enabled(dev_priv,
7457                                          POWER_DOMAIN_PIPE(crtc->pipe)))
7458                 return false;
7459
7460         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7461         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7462
7463         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7464         if (tmp & TRANS_DDI_FUNC_ENABLE) {
7465                 enum pipe trans_edp_pipe;
7466                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7467                 default:
7468                         WARN(1, "unknown pipe linked to edp transcoder\n");
7469                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7470                 case TRANS_DDI_EDP_INPUT_A_ON:
7471                         trans_edp_pipe = PIPE_A;
7472                         break;
7473                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7474                         trans_edp_pipe = PIPE_B;
7475                         break;
7476                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7477                         trans_edp_pipe = PIPE_C;
7478                         break;
7479                 }
7480
7481                 if (trans_edp_pipe == crtc->pipe)
7482                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
7483         }
7484
7485         if (!intel_display_power_enabled(dev_priv,
7486                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7487                 return false;
7488
7489         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7490         if (!(tmp & PIPECONF_ENABLE))
7491                 return false;
7492
7493         /*
7494          * Haswell has only FDI/PCH transcoder A. It is which is connected to
7495          * DDI E. So just check whether this pipe is wired to DDI E and whether
7496          * the PCH transcoder is on.
7497          */
7498         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7499         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7500             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7501                 pipe_config->has_pch_encoder = true;
7502
7503                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7504                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7505                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
7506
7507                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7508         }
7509
7510         intel_get_pipe_timings(crtc, pipe_config);
7511
7512         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7513         if (intel_display_power_enabled(dev_priv, pfit_domain))
7514                 ironlake_get_pfit_config(crtc, pipe_config);
7515
7516         if (IS_HASWELL(dev))
7517                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7518                         (I915_READ(IPS_CTL) & IPS_ENABLE);
7519
7520         pipe_config->pixel_multiplier = 1;
7521
7522         return true;
7523 }
7524
7525 static struct {
7526         int clock;
7527         u32 config;
7528 } hdmi_audio_clock[] = {
7529         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7530         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7531         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7532         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7533         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7534         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7535         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7536         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7537         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7538         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7539 };
7540
7541 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7542 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7543 {
7544         int i;
7545
7546         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7547                 if (mode->clock == hdmi_audio_clock[i].clock)
7548                         break;
7549         }
7550
7551         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7552                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7553                 i = 1;
7554         }
7555
7556         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7557                       hdmi_audio_clock[i].clock,
7558                       hdmi_audio_clock[i].config);
7559
7560         return hdmi_audio_clock[i].config;
7561 }
7562
7563 static bool intel_eld_uptodate(struct drm_connector *connector,
7564                                int reg_eldv, uint32_t bits_eldv,
7565                                int reg_elda, uint32_t bits_elda,
7566                                int reg_edid)
7567 {
7568         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7569         uint8_t *eld = connector->eld;
7570         uint32_t i;
7571
7572         i = I915_READ(reg_eldv);
7573         i &= bits_eldv;
7574
7575         if (!eld[0])
7576                 return !i;
7577
7578         if (!i)
7579                 return false;
7580
7581         i = I915_READ(reg_elda);
7582         i &= ~bits_elda;
7583         I915_WRITE(reg_elda, i);
7584
7585         for (i = 0; i < eld[2]; i++)
7586                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7587                         return false;
7588
7589         return true;
7590 }
7591
7592 static void g4x_write_eld(struct drm_connector *connector,
7593                           struct drm_crtc *crtc,
7594                           struct drm_display_mode *mode)
7595 {
7596         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7597         uint8_t *eld = connector->eld;
7598         uint32_t eldv;
7599         uint32_t len;
7600         uint32_t i;
7601
7602         i = I915_READ(G4X_AUD_VID_DID);
7603
7604         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7605                 eldv = G4X_ELDV_DEVCL_DEVBLC;
7606         else
7607                 eldv = G4X_ELDV_DEVCTG;
7608
7609         if (intel_eld_uptodate(connector,
7610                                G4X_AUD_CNTL_ST, eldv,
7611                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7612                                G4X_HDMIW_HDMIEDID))
7613                 return;
7614
7615         i = I915_READ(G4X_AUD_CNTL_ST);
7616         i &= ~(eldv | G4X_ELD_ADDR);
7617         len = (i >> 9) & 0x1f;          /* ELD buffer size */
7618         I915_WRITE(G4X_AUD_CNTL_ST, i);
7619
7620         if (!eld[0])
7621                 return;
7622
7623         len = min_t(uint8_t, eld[2], len);
7624         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7625         for (i = 0; i < len; i++)
7626                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7627
7628         i = I915_READ(G4X_AUD_CNTL_ST);
7629         i |= eldv;
7630         I915_WRITE(G4X_AUD_CNTL_ST, i);
7631 }
7632
7633 static void haswell_write_eld(struct drm_connector *connector,
7634                               struct drm_crtc *crtc,
7635                               struct drm_display_mode *mode)
7636 {
7637         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7638         uint8_t *eld = connector->eld;
7639         uint32_t eldv;
7640         uint32_t i;
7641         int len;
7642         int pipe = to_intel_crtc(crtc)->pipe;
7643         int tmp;
7644
7645         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7646         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7647         int aud_config = HSW_AUD_CFG(pipe);
7648         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7649
7650         /* Audio output enable */
7651         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7652         tmp = I915_READ(aud_cntrl_st2);
7653         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7654         I915_WRITE(aud_cntrl_st2, tmp);
7655         POSTING_READ(aud_cntrl_st2);
7656
7657         assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7658
7659         /* Set ELD valid state */
7660         tmp = I915_READ(aud_cntrl_st2);
7661         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7662         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7663         I915_WRITE(aud_cntrl_st2, tmp);
7664         tmp = I915_READ(aud_cntrl_st2);
7665         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7666
7667         /* Enable HDMI mode */
7668         tmp = I915_READ(aud_config);
7669         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7670         /* clear N_programing_enable and N_value_index */
7671         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7672         I915_WRITE(aud_config, tmp);
7673
7674         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7675
7676         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7677
7678         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7679                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7680                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7681                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7682         } else {
7683                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7684         }
7685
7686         if (intel_eld_uptodate(connector,
7687                                aud_cntrl_st2, eldv,
7688                                aud_cntl_st, IBX_ELD_ADDRESS,
7689                                hdmiw_hdmiedid))
7690                 return;
7691
7692         i = I915_READ(aud_cntrl_st2);
7693         i &= ~eldv;
7694         I915_WRITE(aud_cntrl_st2, i);
7695
7696         if (!eld[0])
7697                 return;
7698
7699         i = I915_READ(aud_cntl_st);
7700         i &= ~IBX_ELD_ADDRESS;
7701         I915_WRITE(aud_cntl_st, i);
7702         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7703         DRM_DEBUG_DRIVER("port num:%d\n", i);
7704
7705         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7706         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7707         for (i = 0; i < len; i++)
7708                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7709
7710         i = I915_READ(aud_cntrl_st2);
7711         i |= eldv;
7712         I915_WRITE(aud_cntrl_st2, i);
7713
7714 }
7715
7716 static void ironlake_write_eld(struct drm_connector *connector,
7717                                struct drm_crtc *crtc,
7718                                struct drm_display_mode *mode)
7719 {
7720         struct drm_i915_private *dev_priv = connector->dev->dev_private;
7721         uint8_t *eld = connector->eld;
7722         uint32_t eldv;
7723         uint32_t i;
7724         int len;
7725         int hdmiw_hdmiedid;
7726         int aud_config;
7727         int aud_cntl_st;
7728         int aud_cntrl_st2;
7729         int pipe = to_intel_crtc(crtc)->pipe;
7730
7731         if (HAS_PCH_IBX(connector->dev)) {
7732                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7733                 aud_config = IBX_AUD_CFG(pipe);
7734                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7735                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7736         } else if (IS_VALLEYVIEW(connector->dev)) {
7737                 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7738                 aud_config = VLV_AUD_CFG(pipe);
7739                 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7740                 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7741         } else {
7742                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7743                 aud_config = CPT_AUD_CFG(pipe);
7744                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7745                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7746         }
7747
7748         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7749
7750         if (IS_VALLEYVIEW(connector->dev))  {
7751                 struct intel_encoder *intel_encoder;
7752                 struct intel_digital_port *intel_dig_port;
7753
7754                 intel_encoder = intel_attached_encoder(connector);
7755                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7756                 i = intel_dig_port->port;
7757         } else {
7758                 i = I915_READ(aud_cntl_st);
7759                 i = (i >> 29) & DIP_PORT_SEL_MASK;
7760                 /* DIP_Port_Select, 0x1 = PortB */
7761         }
7762
7763         if (!i) {
7764                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7765                 /* operate blindly on all ports */
7766                 eldv = IBX_ELD_VALIDB;
7767                 eldv |= IBX_ELD_VALIDB << 4;
7768                 eldv |= IBX_ELD_VALIDB << 8;
7769         } else {
7770                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7771                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7772         }
7773
7774         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7775                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7776                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7777                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7778         } else {
7779                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7780         }
7781
7782         if (intel_eld_uptodate(connector,
7783                                aud_cntrl_st2, eldv,
7784                                aud_cntl_st, IBX_ELD_ADDRESS,
7785                                hdmiw_hdmiedid))
7786                 return;
7787
7788         i = I915_READ(aud_cntrl_st2);
7789         i &= ~eldv;
7790         I915_WRITE(aud_cntrl_st2, i);
7791
7792         if (!eld[0])
7793                 return;
7794
7795         i = I915_READ(aud_cntl_st);
7796         i &= ~IBX_ELD_ADDRESS;
7797         I915_WRITE(aud_cntl_st, i);
7798
7799         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7800         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7801         for (i = 0; i < len; i++)
7802                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7803
7804         i = I915_READ(aud_cntrl_st2);
7805         i |= eldv;
7806         I915_WRITE(aud_cntrl_st2, i);
7807 }
7808
7809 void intel_write_eld(struct drm_encoder *encoder,
7810                      struct drm_display_mode *mode)
7811 {
7812         struct drm_crtc *crtc = encoder->crtc;
7813         struct drm_connector *connector;
7814         struct drm_device *dev = encoder->dev;
7815         struct drm_i915_private *dev_priv = dev->dev_private;
7816
7817         connector = drm_select_eld(encoder, mode);
7818         if (!connector)
7819                 return;
7820
7821         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7822                          connector->base.id,
7823                          drm_get_connector_name(connector),
7824                          connector->encoder->base.id,
7825                          drm_get_encoder_name(connector->encoder));
7826
7827         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7828
7829         if (dev_priv->display.write_eld)
7830                 dev_priv->display.write_eld(connector, crtc, mode);
7831 }
7832
7833 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7834 {
7835         struct drm_device *dev = crtc->dev;
7836         struct drm_i915_private *dev_priv = dev->dev_private;
7837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7838         bool visible = base != 0;
7839         u32 cntl;
7840
7841         if (intel_crtc->cursor_visible == visible)
7842                 return;
7843
7844         cntl = I915_READ(_CURACNTR);
7845         if (visible) {
7846                 /* On these chipsets we can only modify the base whilst
7847                  * the cursor is disabled.
7848                  */
7849                 I915_WRITE(_CURABASE, base);
7850
7851                 cntl &= ~(CURSOR_FORMAT_MASK);
7852                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7853                 cntl |= CURSOR_ENABLE |
7854                         CURSOR_GAMMA_ENABLE |
7855                         CURSOR_FORMAT_ARGB;
7856         } else
7857                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7858         I915_WRITE(_CURACNTR, cntl);
7859
7860         intel_crtc->cursor_visible = visible;
7861 }
7862
7863 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7864 {
7865         struct drm_device *dev = crtc->dev;
7866         struct drm_i915_private *dev_priv = dev->dev_private;
7867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7868         int pipe = intel_crtc->pipe;
7869         bool visible = base != 0;
7870
7871         if (intel_crtc->cursor_visible != visible) {
7872                 int16_t width = intel_crtc->cursor_width;
7873                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7874                 if (base) {
7875                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7876                         cntl |= MCURSOR_GAMMA_ENABLE;
7877
7878                         switch (width) {
7879                         case 64:
7880                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7881                                 break;
7882                         case 128:
7883                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7884                                 break;
7885                         case 256:
7886                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7887                                 break;
7888                         default:
7889                                 WARN_ON(1);
7890                                 return;
7891                         }
7892                         cntl |= pipe << 28; /* Connect to correct pipe */
7893                 } else {
7894                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7895                         cntl |= CURSOR_MODE_DISABLE;
7896                 }
7897                 I915_WRITE(CURCNTR(pipe), cntl);
7898
7899                 intel_crtc->cursor_visible = visible;
7900         }
7901         /* and commit changes on next vblank */
7902         POSTING_READ(CURCNTR(pipe));
7903         I915_WRITE(CURBASE(pipe), base);
7904         POSTING_READ(CURBASE(pipe));
7905 }
7906
7907 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7908 {
7909         struct drm_device *dev = crtc->dev;
7910         struct drm_i915_private *dev_priv = dev->dev_private;
7911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7912         int pipe = intel_crtc->pipe;
7913         bool visible = base != 0;
7914
7915         if (intel_crtc->cursor_visible != visible) {
7916                 int16_t width = intel_crtc->cursor_width;
7917                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7918                 if (base) {
7919                         cntl &= ~CURSOR_MODE;
7920                         cntl |= MCURSOR_GAMMA_ENABLE;
7921                         switch (width) {
7922                         case 64:
7923                                 cntl |= CURSOR_MODE_64_ARGB_AX;
7924                                 break;
7925                         case 128:
7926                                 cntl |= CURSOR_MODE_128_ARGB_AX;
7927                                 break;
7928                         case 256:
7929                                 cntl |= CURSOR_MODE_256_ARGB_AX;
7930                                 break;
7931                         default:
7932                                 WARN_ON(1);
7933                                 return;
7934                         }
7935                 } else {
7936                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7937                         cntl |= CURSOR_MODE_DISABLE;
7938                 }
7939                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7940                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7941                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7942                 }
7943                 I915_WRITE(CURCNTR(pipe), cntl);
7944
7945                 intel_crtc->cursor_visible = visible;
7946         }
7947         /* and commit changes on next vblank */
7948         POSTING_READ(CURCNTR(pipe));
7949         I915_WRITE(CURBASE(pipe), base);
7950         POSTING_READ(CURBASE(pipe));
7951 }
7952
7953 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7954 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7955                                      bool on)
7956 {
7957         struct drm_device *dev = crtc->dev;
7958         struct drm_i915_private *dev_priv = dev->dev_private;
7959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7960         int pipe = intel_crtc->pipe;
7961         int x = intel_crtc->cursor_x;
7962         int y = intel_crtc->cursor_y;
7963         u32 base = 0, pos = 0;
7964         bool visible;
7965
7966         if (on)
7967                 base = intel_crtc->cursor_addr;
7968
7969         if (x >= intel_crtc->config.pipe_src_w)
7970                 base = 0;
7971
7972         if (y >= intel_crtc->config.pipe_src_h)
7973                 base = 0;
7974
7975         if (x < 0) {
7976                 if (x + intel_crtc->cursor_width <= 0)
7977                         base = 0;
7978
7979                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7980                 x = -x;
7981         }
7982         pos |= x << CURSOR_X_SHIFT;
7983
7984         if (y < 0) {
7985                 if (y + intel_crtc->cursor_height <= 0)
7986                         base = 0;
7987
7988                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7989                 y = -y;
7990         }
7991         pos |= y << CURSOR_Y_SHIFT;
7992
7993         visible = base != 0;
7994         if (!visible && !intel_crtc->cursor_visible)
7995                 return;
7996
7997         I915_WRITE(CURPOS(pipe), pos);
7998
7999         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8000                 ivb_update_cursor(crtc, base);
8001         else if (IS_845G(dev) || IS_I865G(dev))
8002                 i845_update_cursor(crtc, base);
8003         else
8004                 i9xx_update_cursor(crtc, base);
8005 }
8006
8007 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8008                                  struct drm_file *file,
8009                                  uint32_t handle,
8010                                  uint32_t width, uint32_t height)
8011 {
8012         struct drm_device *dev = crtc->dev;
8013         struct drm_i915_private *dev_priv = dev->dev_private;
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         struct drm_i915_gem_object *obj;
8016         unsigned old_width;
8017         uint32_t addr;
8018         int ret;
8019
8020         /* if we want to turn off the cursor ignore width and height */
8021         if (!handle) {
8022                 DRM_DEBUG_KMS("cursor off\n");
8023                 addr = 0;
8024                 obj = NULL;
8025                 mutex_lock(&dev->struct_mutex);
8026                 goto finish;
8027         }
8028
8029         /* Check for which cursor types we support */
8030         if (!((width == 64 && height == 64) ||
8031                         (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8032                         (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8033                 DRM_DEBUG("Cursor dimension not supported\n");
8034                 return -EINVAL;
8035         }
8036
8037         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8038         if (&obj->base == NULL)
8039                 return -ENOENT;
8040
8041         if (obj->base.size < width * height * 4) {
8042                 DRM_DEBUG_KMS("buffer is to small\n");
8043                 ret = -ENOMEM;
8044                 goto fail;
8045         }
8046
8047         /* we only need to pin inside GTT if cursor is non-phy */
8048         mutex_lock(&dev->struct_mutex);
8049         if (!INTEL_INFO(dev)->cursor_needs_physical) {
8050                 unsigned alignment;
8051
8052                 if (obj->tiling_mode) {
8053                         DRM_DEBUG_KMS("cursor cannot be tiled\n");
8054                         ret = -EINVAL;
8055                         goto fail_locked;
8056                 }
8057
8058                 /* Note that the w/a also requires 2 PTE of padding following
8059                  * the bo. We currently fill all unused PTE with the shadow
8060                  * page and so we should always have valid PTE following the
8061                  * cursor preventing the VT-d warning.
8062                  */
8063                 alignment = 0;
8064                 if (need_vtd_wa(dev))
8065                         alignment = 64*1024;
8066
8067                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8068                 if (ret) {
8069                         DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8070                         goto fail_locked;
8071                 }
8072
8073                 ret = i915_gem_object_put_fence(obj);
8074                 if (ret) {
8075                         DRM_DEBUG_KMS("failed to release fence for cursor");
8076                         goto fail_unpin;
8077                 }
8078
8079                 addr = i915_gem_obj_ggtt_offset(obj);
8080         } else {
8081                 int align = IS_I830(dev) ? 16 * 1024 : 256;
8082                 ret = i915_gem_attach_phys_object(dev, obj,
8083                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8084                                                   align);
8085                 if (ret) {
8086                         DRM_DEBUG_KMS("failed to attach phys object\n");
8087                         goto fail_locked;
8088                 }
8089                 addr = obj->phys_obj->handle->busaddr;
8090         }
8091
8092         if (IS_GEN2(dev))
8093                 I915_WRITE(CURSIZE, (height << 12) | width);
8094
8095  finish:
8096         if (intel_crtc->cursor_bo) {
8097                 if (INTEL_INFO(dev)->cursor_needs_physical) {
8098                         if (intel_crtc->cursor_bo != obj)
8099                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8100                 } else
8101                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8102                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8103         }
8104
8105         mutex_unlock(&dev->struct_mutex);
8106
8107         old_width = intel_crtc->cursor_width;
8108
8109         intel_crtc->cursor_addr = addr;
8110         intel_crtc->cursor_bo = obj;
8111         intel_crtc->cursor_width = width;
8112         intel_crtc->cursor_height = height;
8113
8114         if (intel_crtc->active) {
8115                 if (old_width != width)
8116                         intel_update_watermarks(crtc);
8117                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8118         }
8119
8120         return 0;
8121 fail_unpin:
8122         i915_gem_object_unpin_from_display_plane(obj);
8123 fail_locked:
8124         mutex_unlock(&dev->struct_mutex);
8125 fail:
8126         drm_gem_object_unreference_unlocked(&obj->base);
8127         return ret;
8128 }
8129
8130 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8131 {
8132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8133
8134         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8135         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8136
8137         if (intel_crtc->active)
8138                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8139
8140         return 0;
8141 }
8142
8143 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8144                                  u16 *blue, uint32_t start, uint32_t size)
8145 {
8146         int end = (start + size > 256) ? 256 : start + size, i;
8147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8148
8149         for (i = start; i < end; i++) {
8150                 intel_crtc->lut_r[i] = red[i] >> 8;
8151                 intel_crtc->lut_g[i] = green[i] >> 8;
8152                 intel_crtc->lut_b[i] = blue[i] >> 8;
8153         }
8154
8155         intel_crtc_load_lut(crtc);
8156 }
8157
8158 /* VESA 640x480x72Hz mode to set on the pipe */
8159 static struct drm_display_mode load_detect_mode = {
8160         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8161                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8162 };
8163
8164 struct drm_framebuffer *
8165 __intel_framebuffer_create(struct drm_device *dev,
8166                            struct drm_mode_fb_cmd2 *mode_cmd,
8167                            struct drm_i915_gem_object *obj)
8168 {
8169         struct intel_framebuffer *intel_fb;
8170         int ret;
8171
8172         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8173         if (!intel_fb) {
8174                 drm_gem_object_unreference_unlocked(&obj->base);
8175                 return ERR_PTR(-ENOMEM);
8176         }
8177
8178         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8179         if (ret)
8180                 goto err;
8181
8182         return &intel_fb->base;
8183 err:
8184         drm_gem_object_unreference_unlocked(&obj->base);
8185         kfree(intel_fb);
8186
8187         return ERR_PTR(ret);
8188 }
8189
8190 static struct drm_framebuffer *
8191 intel_framebuffer_create(struct drm_device *dev,
8192                          struct drm_mode_fb_cmd2 *mode_cmd,
8193                          struct drm_i915_gem_object *obj)
8194 {
8195         struct drm_framebuffer *fb;
8196         int ret;
8197
8198         ret = i915_mutex_lock_interruptible(dev);
8199         if (ret)
8200                 return ERR_PTR(ret);
8201         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8202         mutex_unlock(&dev->struct_mutex);
8203
8204         return fb;
8205 }
8206
8207 static u32
8208 intel_framebuffer_pitch_for_width(int width, int bpp)
8209 {
8210         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8211         return ALIGN(pitch, 64);
8212 }
8213
8214 static u32
8215 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8216 {
8217         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8218         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8219 }
8220
8221 static struct drm_framebuffer *
8222 intel_framebuffer_create_for_mode(struct drm_device *dev,
8223                                   struct drm_display_mode *mode,
8224                                   int depth, int bpp)
8225 {
8226         struct drm_i915_gem_object *obj;
8227         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8228
8229         obj = i915_gem_alloc_object(dev,
8230                                     intel_framebuffer_size_for_mode(mode, bpp));
8231         if (obj == NULL)
8232                 return ERR_PTR(-ENOMEM);
8233
8234         mode_cmd.width = mode->hdisplay;
8235         mode_cmd.height = mode->vdisplay;
8236         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8237                                                                 bpp);
8238         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8239
8240         return intel_framebuffer_create(dev, &mode_cmd, obj);
8241 }
8242
8243 static struct drm_framebuffer *
8244 mode_fits_in_fbdev(struct drm_device *dev,
8245                    struct drm_display_mode *mode)
8246 {
8247 #ifdef CONFIG_DRM_I915_FBDEV
8248         struct drm_i915_private *dev_priv = dev->dev_private;
8249         struct drm_i915_gem_object *obj;
8250         struct drm_framebuffer *fb;
8251
8252         if (!dev_priv->fbdev)
8253                 return NULL;
8254
8255         if (!dev_priv->fbdev->fb)
8256                 return NULL;
8257
8258         obj = dev_priv->fbdev->fb->obj;
8259         BUG_ON(!obj);
8260
8261         fb = &dev_priv->fbdev->fb->base;
8262         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8263                                                                fb->bits_per_pixel))
8264                 return NULL;
8265
8266         if (obj->base.size < mode->vdisplay * fb->pitches[0])
8267                 return NULL;
8268
8269         return fb;
8270 #else
8271         return NULL;
8272 #endif
8273 }
8274
8275 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8276                                 struct drm_display_mode *mode,
8277                                 struct intel_load_detect_pipe *old)
8278 {
8279         struct intel_crtc *intel_crtc;
8280         struct intel_encoder *intel_encoder =
8281                 intel_attached_encoder(connector);
8282         struct drm_crtc *possible_crtc;
8283         struct drm_encoder *encoder = &intel_encoder->base;
8284         struct drm_crtc *crtc = NULL;
8285         struct drm_device *dev = encoder->dev;
8286         struct drm_framebuffer *fb;
8287         int i = -1;
8288
8289         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8290                       connector->base.id, drm_get_connector_name(connector),
8291                       encoder->base.id, drm_get_encoder_name(encoder));
8292
8293         /*
8294          * Algorithm gets a little messy:
8295          *
8296          *   - if the connector already has an assigned crtc, use it (but make
8297          *     sure it's on first)
8298          *
8299          *   - try to find the first unused crtc that can drive this connector,
8300          *     and use that if we find one
8301          */
8302
8303         /* See if we already have a CRTC for this connector */
8304         if (encoder->crtc) {
8305                 crtc = encoder->crtc;
8306
8307                 mutex_lock(&crtc->mutex);
8308
8309                 old->dpms_mode = connector->dpms;
8310                 old->load_detect_temp = false;
8311
8312                 /* Make sure the crtc and connector are running */
8313                 if (connector->dpms != DRM_MODE_DPMS_ON)
8314                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8315
8316                 return true;
8317         }
8318
8319         /* Find an unused one (if possible) */
8320         for_each_crtc(dev, possible_crtc) {
8321                 i++;
8322                 if (!(encoder->possible_crtcs & (1 << i)))
8323                         continue;
8324                 if (!possible_crtc->enabled) {
8325                         crtc = possible_crtc;
8326                         break;
8327                 }
8328         }
8329
8330         /*
8331          * If we didn't find an unused CRTC, don't use any.
8332          */
8333         if (!crtc) {
8334                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8335                 return false;
8336         }
8337
8338         mutex_lock(&crtc->mutex);
8339         intel_encoder->new_crtc = to_intel_crtc(crtc);
8340         to_intel_connector(connector)->new_encoder = intel_encoder;
8341
8342         intel_crtc = to_intel_crtc(crtc);
8343         intel_crtc->new_enabled = true;
8344         intel_crtc->new_config = &intel_crtc->config;
8345         old->dpms_mode = connector->dpms;
8346         old->load_detect_temp = true;
8347         old->release_fb = NULL;
8348
8349         if (!mode)
8350                 mode = &load_detect_mode;
8351
8352         /* We need a framebuffer large enough to accommodate all accesses
8353          * that the plane may generate whilst we perform load detection.
8354          * We can not rely on the fbcon either being present (we get called
8355          * during its initialisation to detect all boot displays, or it may
8356          * not even exist) or that it is large enough to satisfy the
8357          * requested mode.
8358          */
8359         fb = mode_fits_in_fbdev(dev, mode);
8360         if (fb == NULL) {
8361                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8362                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8363                 old->release_fb = fb;
8364         } else
8365                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8366         if (IS_ERR(fb)) {
8367                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8368                 goto fail;
8369         }
8370
8371         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8372                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8373                 if (old->release_fb)
8374                         old->release_fb->funcs->destroy(old->release_fb);
8375                 goto fail;
8376         }
8377
8378         /* let the connector get through one full cycle before testing */
8379         intel_wait_for_vblank(dev, intel_crtc->pipe);
8380         return true;
8381
8382  fail:
8383         intel_crtc->new_enabled = crtc->enabled;
8384         if (intel_crtc->new_enabled)
8385                 intel_crtc->new_config = &intel_crtc->config;
8386         else
8387                 intel_crtc->new_config = NULL;
8388         mutex_unlock(&crtc->mutex);
8389         return false;
8390 }
8391
8392 void intel_release_load_detect_pipe(struct drm_connector *connector,
8393                                     struct intel_load_detect_pipe *old)
8394 {
8395         struct intel_encoder *intel_encoder =
8396                 intel_attached_encoder(connector);
8397         struct drm_encoder *encoder = &intel_encoder->base;
8398         struct drm_crtc *crtc = encoder->crtc;
8399         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8400
8401         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8402                       connector->base.id, drm_get_connector_name(connector),
8403                       encoder->base.id, drm_get_encoder_name(encoder));
8404
8405         if (old->load_detect_temp) {
8406                 to_intel_connector(connector)->new_encoder = NULL;
8407                 intel_encoder->new_crtc = NULL;
8408                 intel_crtc->new_enabled = false;
8409                 intel_crtc->new_config = NULL;
8410                 intel_set_mode(crtc, NULL, 0, 0, NULL);
8411
8412                 if (old->release_fb) {
8413                         drm_framebuffer_unregister_private(old->release_fb);
8414                         drm_framebuffer_unreference(old->release_fb);
8415                 }
8416
8417                 mutex_unlock(&crtc->mutex);
8418                 return;
8419         }
8420
8421         /* Switch crtc and encoder back off if necessary */
8422         if (old->dpms_mode != DRM_MODE_DPMS_ON)
8423                 connector->funcs->dpms(connector, old->dpms_mode);
8424
8425         mutex_unlock(&crtc->mutex);
8426 }
8427
8428 static int i9xx_pll_refclk(struct drm_device *dev,
8429                            const struct intel_crtc_config *pipe_config)
8430 {
8431         struct drm_i915_private *dev_priv = dev->dev_private;
8432         u32 dpll = pipe_config->dpll_hw_state.dpll;
8433
8434         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8435                 return dev_priv->vbt.lvds_ssc_freq;
8436         else if (HAS_PCH_SPLIT(dev))
8437                 return 120000;
8438         else if (!IS_GEN2(dev))
8439                 return 96000;
8440         else
8441                 return 48000;
8442 }
8443
8444 /* Returns the clock of the currently programmed mode of the given pipe. */
8445 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8446                                 struct intel_crtc_config *pipe_config)
8447 {
8448         struct drm_device *dev = crtc->base.dev;
8449         struct drm_i915_private *dev_priv = dev->dev_private;
8450         int pipe = pipe_config->cpu_transcoder;
8451         u32 dpll = pipe_config->dpll_hw_state.dpll;
8452         u32 fp;
8453         intel_clock_t clock;
8454         int refclk = i9xx_pll_refclk(dev, pipe_config);
8455
8456         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8457                 fp = pipe_config->dpll_hw_state.fp0;
8458         else
8459                 fp = pipe_config->dpll_hw_state.fp1;
8460
8461         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8462         if (IS_PINEVIEW(dev)) {
8463                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8464                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8465         } else {
8466                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8467                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8468         }
8469
8470         if (!IS_GEN2(dev)) {
8471                 if (IS_PINEVIEW(dev))
8472                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8473                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8474                 else
8475                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8476                                DPLL_FPA01_P1_POST_DIV_SHIFT);
8477
8478                 switch (dpll & DPLL_MODE_MASK) {
8479                 case DPLLB_MODE_DAC_SERIAL:
8480                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8481                                 5 : 10;
8482                         break;
8483                 case DPLLB_MODE_LVDS:
8484                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8485                                 7 : 14;
8486                         break;
8487                 default:
8488                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8489                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
8490                         return;
8491                 }
8492
8493                 if (IS_PINEVIEW(dev))
8494                         pineview_clock(refclk, &clock);
8495                 else
8496                         i9xx_clock(refclk, &clock);
8497         } else {
8498                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8499                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8500
8501                 if (is_lvds) {
8502                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8503                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
8504
8505                         if (lvds & LVDS_CLKB_POWER_UP)
8506                                 clock.p2 = 7;
8507                         else
8508                                 clock.p2 = 14;
8509                 } else {
8510                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
8511                                 clock.p1 = 2;
8512                         else {
8513                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8514                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8515                         }
8516                         if (dpll & PLL_P2_DIVIDE_BY_4)
8517                                 clock.p2 = 4;
8518                         else
8519                                 clock.p2 = 2;
8520                 }
8521
8522                 i9xx_clock(refclk, &clock);
8523         }
8524
8525         /*
8526          * This value includes pixel_multiplier. We will use
8527          * port_clock to compute adjusted_mode.crtc_clock in the
8528          * encoder's get_config() function.
8529          */
8530         pipe_config->port_clock = clock.dot;
8531 }
8532
8533 int intel_dotclock_calculate(int link_freq,
8534                              const struct intel_link_m_n *m_n)
8535 {
8536         /*
8537          * The calculation for the data clock is:
8538          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8539          * But we want to avoid losing precison if possible, so:
8540          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8541          *
8542          * and the link clock is simpler:
8543          * link_clock = (m * link_clock) / n
8544          */
8545
8546         if (!m_n->link_n)
8547                 return 0;
8548
8549         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8550 }
8551
8552 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8553                                    struct intel_crtc_config *pipe_config)
8554 {
8555         struct drm_device *dev = crtc->base.dev;
8556
8557         /* read out port_clock from the DPLL */
8558         i9xx_crtc_clock_get(crtc, pipe_config);
8559
8560         /*
8561          * This value does not include pixel_multiplier.
8562          * We will check that port_clock and adjusted_mode.crtc_clock
8563          * agree once we know their relationship in the encoder's
8564          * get_config() function.
8565          */
8566         pipe_config->adjusted_mode.crtc_clock =
8567                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8568                                          &pipe_config->fdi_m_n);
8569 }
8570
8571 /** Returns the currently programmed mode of the given pipe. */
8572 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8573                                              struct drm_crtc *crtc)
8574 {
8575         struct drm_i915_private *dev_priv = dev->dev_private;
8576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8577         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8578         struct drm_display_mode *mode;
8579         struct intel_crtc_config pipe_config;
8580         int htot = I915_READ(HTOTAL(cpu_transcoder));
8581         int hsync = I915_READ(HSYNC(cpu_transcoder));
8582         int vtot = I915_READ(VTOTAL(cpu_transcoder));
8583         int vsync = I915_READ(VSYNC(cpu_transcoder));
8584         enum pipe pipe = intel_crtc->pipe;
8585
8586         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8587         if (!mode)
8588                 return NULL;
8589
8590         /*
8591          * Construct a pipe_config sufficient for getting the clock info
8592          * back out of crtc_clock_get.
8593          *
8594          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8595          * to use a real value here instead.
8596          */
8597         pipe_config.cpu_transcoder = (enum transcoder) pipe;
8598         pipe_config.pixel_multiplier = 1;
8599         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8600         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8601         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8602         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8603
8604         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8605         mode->hdisplay = (htot & 0xffff) + 1;
8606         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8607         mode->hsync_start = (hsync & 0xffff) + 1;
8608         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8609         mode->vdisplay = (vtot & 0xffff) + 1;
8610         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8611         mode->vsync_start = (vsync & 0xffff) + 1;
8612         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8613
8614         drm_mode_set_name(mode);
8615
8616         return mode;
8617 }
8618
8619 static void intel_increase_pllclock(struct drm_crtc *crtc)
8620 {
8621         struct drm_device *dev = crtc->dev;
8622         struct drm_i915_private *dev_priv = dev->dev_private;
8623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8624         int pipe = intel_crtc->pipe;
8625         int dpll_reg = DPLL(pipe);
8626         int dpll;
8627
8628         if (HAS_PCH_SPLIT(dev))
8629                 return;
8630
8631         if (!dev_priv->lvds_downclock_avail)
8632                 return;
8633
8634         dpll = I915_READ(dpll_reg);
8635         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8636                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8637
8638                 assert_panel_unlocked(dev_priv, pipe);
8639
8640                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8641                 I915_WRITE(dpll_reg, dpll);
8642                 intel_wait_for_vblank(dev, pipe);
8643
8644                 dpll = I915_READ(dpll_reg);
8645                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8646                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8647         }
8648 }
8649
8650 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8651 {
8652         struct drm_device *dev = crtc->dev;
8653         struct drm_i915_private *dev_priv = dev->dev_private;
8654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8655
8656         if (HAS_PCH_SPLIT(dev))
8657                 return;
8658
8659         if (!dev_priv->lvds_downclock_avail)
8660                 return;
8661
8662         /*
8663          * Since this is called by a timer, we should never get here in
8664          * the manual case.
8665          */
8666         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8667                 int pipe = intel_crtc->pipe;
8668                 int dpll_reg = DPLL(pipe);
8669                 int dpll;
8670
8671                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8672
8673                 assert_panel_unlocked(dev_priv, pipe);
8674
8675                 dpll = I915_READ(dpll_reg);
8676                 dpll |= DISPLAY_RATE_SELECT_FPA1;
8677                 I915_WRITE(dpll_reg, dpll);
8678                 intel_wait_for_vblank(dev, pipe);
8679                 dpll = I915_READ(dpll_reg);
8680                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8681                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8682         }
8683
8684 }
8685
8686 void intel_mark_busy(struct drm_device *dev)
8687 {
8688         struct drm_i915_private *dev_priv = dev->dev_private;
8689
8690         if (dev_priv->mm.busy)
8691                 return;
8692
8693         intel_runtime_pm_get(dev_priv);
8694         i915_update_gfx_val(dev_priv);
8695         dev_priv->mm.busy = true;
8696 }
8697
8698 void intel_mark_idle(struct drm_device *dev)
8699 {
8700         struct drm_i915_private *dev_priv = dev->dev_private;
8701         struct drm_crtc *crtc;
8702
8703         if (!dev_priv->mm.busy)
8704                 return;
8705
8706         dev_priv->mm.busy = false;
8707
8708         if (!i915.powersave)
8709                 goto out;
8710
8711         for_each_crtc(dev, crtc) {
8712                 if (!crtc->primary->fb)
8713                         continue;
8714
8715                 intel_decrease_pllclock(crtc);
8716         }
8717
8718         if (INTEL_INFO(dev)->gen >= 6)
8719                 gen6_rps_idle(dev->dev_private);
8720
8721 out:
8722         intel_runtime_pm_put(dev_priv);
8723 }
8724
8725 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8726                         struct intel_ring_buffer *ring)
8727 {
8728         struct drm_device *dev = obj->base.dev;
8729         struct drm_crtc *crtc;
8730
8731         if (!i915.powersave)
8732                 return;
8733
8734         for_each_crtc(dev, crtc) {
8735                 if (!crtc->primary->fb)
8736                         continue;
8737
8738                 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8739                         continue;
8740
8741                 intel_increase_pllclock(crtc);
8742                 if (ring && intel_fbc_enabled(dev))
8743                         ring->fbc_dirty = true;
8744         }
8745 }
8746
8747 static void intel_crtc_destroy(struct drm_crtc *crtc)
8748 {
8749         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8750         struct drm_device *dev = crtc->dev;
8751         struct intel_unpin_work *work;
8752         unsigned long flags;
8753
8754         spin_lock_irqsave(&dev->event_lock, flags);
8755         work = intel_crtc->unpin_work;
8756         intel_crtc->unpin_work = NULL;
8757         spin_unlock_irqrestore(&dev->event_lock, flags);
8758
8759         if (work) {
8760                 cancel_work_sync(&work->work);
8761                 kfree(work);
8762         }
8763
8764         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8765
8766         drm_crtc_cleanup(crtc);
8767
8768         kfree(intel_crtc);
8769 }
8770
8771 static void intel_unpin_work_fn(struct work_struct *__work)
8772 {
8773         struct intel_unpin_work *work =
8774                 container_of(__work, struct intel_unpin_work, work);
8775         struct drm_device *dev = work->crtc->dev;
8776
8777         mutex_lock(&dev->struct_mutex);
8778         intel_unpin_fb_obj(work->old_fb_obj);
8779         drm_gem_object_unreference(&work->pending_flip_obj->base);
8780         drm_gem_object_unreference(&work->old_fb_obj->base);
8781
8782         intel_update_fbc(dev);
8783         mutex_unlock(&dev->struct_mutex);
8784
8785         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8786         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8787
8788         kfree(work);
8789 }
8790
8791 static void do_intel_finish_page_flip(struct drm_device *dev,
8792                                       struct drm_crtc *crtc)
8793 {
8794         struct drm_i915_private *dev_priv = dev->dev_private;
8795         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8796         struct intel_unpin_work *work;
8797         unsigned long flags;
8798
8799         /* Ignore early vblank irqs */
8800         if (intel_crtc == NULL)
8801                 return;
8802
8803         spin_lock_irqsave(&dev->event_lock, flags);
8804         work = intel_crtc->unpin_work;
8805
8806         /* Ensure we don't miss a work->pending update ... */
8807         smp_rmb();
8808
8809         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8810                 spin_unlock_irqrestore(&dev->event_lock, flags);
8811                 return;
8812         }
8813
8814         /* and that the unpin work is consistent wrt ->pending. */
8815         smp_rmb();
8816
8817         intel_crtc->unpin_work = NULL;
8818
8819         if (work->event)
8820                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8821
8822         drm_vblank_put(dev, intel_crtc->pipe);
8823
8824         spin_unlock_irqrestore(&dev->event_lock, flags);
8825
8826         wake_up_all(&dev_priv->pending_flip_queue);
8827
8828         queue_work(dev_priv->wq, &work->work);
8829
8830         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8831 }
8832
8833 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8834 {
8835         struct drm_i915_private *dev_priv = dev->dev_private;
8836         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8837
8838         do_intel_finish_page_flip(dev, crtc);
8839 }
8840
8841 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8842 {
8843         struct drm_i915_private *dev_priv = dev->dev_private;
8844         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8845
8846         do_intel_finish_page_flip(dev, crtc);
8847 }
8848
8849 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8850 {
8851         struct drm_i915_private *dev_priv = dev->dev_private;
8852         struct intel_crtc *intel_crtc =
8853                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8854         unsigned long flags;
8855
8856         /* NB: An MMIO update of the plane base pointer will also
8857          * generate a page-flip completion irq, i.e. every modeset
8858          * is also accompanied by a spurious intel_prepare_page_flip().
8859          */
8860         spin_lock_irqsave(&dev->event_lock, flags);
8861         if (intel_crtc->unpin_work)
8862                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8863         spin_unlock_irqrestore(&dev->event_lock, flags);
8864 }
8865
8866 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8867 {
8868         /* Ensure that the work item is consistent when activating it ... */
8869         smp_wmb();
8870         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8871         /* and that it is marked active as soon as the irq could fire. */
8872         smp_wmb();
8873 }
8874
8875 static int intel_gen2_queue_flip(struct drm_device *dev,
8876                                  struct drm_crtc *crtc,
8877                                  struct drm_framebuffer *fb,
8878                                  struct drm_i915_gem_object *obj,
8879                                  uint32_t flags)
8880 {
8881         struct drm_i915_private *dev_priv = dev->dev_private;
8882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883         u32 flip_mask;
8884         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8885         int ret;
8886
8887         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8888         if (ret)
8889                 goto err;
8890
8891         ret = intel_ring_begin(ring, 6);
8892         if (ret)
8893                 goto err_unpin;
8894
8895         /* Can't queue multiple flips, so wait for the previous
8896          * one to finish before executing the next.
8897          */
8898         if (intel_crtc->plane)
8899                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8900         else
8901                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8902         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8903         intel_ring_emit(ring, MI_NOOP);
8904         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8905                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8906         intel_ring_emit(ring, fb->pitches[0]);
8907         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8908         intel_ring_emit(ring, 0); /* aux display base address, unused */
8909
8910         intel_mark_page_flip_active(intel_crtc);
8911         __intel_ring_advance(ring);
8912         return 0;
8913
8914 err_unpin:
8915         intel_unpin_fb_obj(obj);
8916 err:
8917         return ret;
8918 }
8919
8920 static int intel_gen3_queue_flip(struct drm_device *dev,
8921                                  struct drm_crtc *crtc,
8922                                  struct drm_framebuffer *fb,
8923                                  struct drm_i915_gem_object *obj,
8924                                  uint32_t flags)
8925 {
8926         struct drm_i915_private *dev_priv = dev->dev_private;
8927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8928         u32 flip_mask;
8929         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8930         int ret;
8931
8932         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8933         if (ret)
8934                 goto err;
8935
8936         ret = intel_ring_begin(ring, 6);
8937         if (ret)
8938                 goto err_unpin;
8939
8940         if (intel_crtc->plane)
8941                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8942         else
8943                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8944         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8945         intel_ring_emit(ring, MI_NOOP);
8946         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8947                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8948         intel_ring_emit(ring, fb->pitches[0]);
8949         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8950         intel_ring_emit(ring, MI_NOOP);
8951
8952         intel_mark_page_flip_active(intel_crtc);
8953         __intel_ring_advance(ring);
8954         return 0;
8955
8956 err_unpin:
8957         intel_unpin_fb_obj(obj);
8958 err:
8959         return ret;
8960 }
8961
8962 static int intel_gen4_queue_flip(struct drm_device *dev,
8963                                  struct drm_crtc *crtc,
8964                                  struct drm_framebuffer *fb,
8965                                  struct drm_i915_gem_object *obj,
8966                                  uint32_t flags)
8967 {
8968         struct drm_i915_private *dev_priv = dev->dev_private;
8969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8970         uint32_t pf, pipesrc;
8971         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8972         int ret;
8973
8974         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8975         if (ret)
8976                 goto err;
8977
8978         ret = intel_ring_begin(ring, 4);
8979         if (ret)
8980                 goto err_unpin;
8981
8982         /* i965+ uses the linear or tiled offsets from the
8983          * Display Registers (which do not change across a page-flip)
8984          * so we need only reprogram the base address.
8985          */
8986         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8987                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8988         intel_ring_emit(ring, fb->pitches[0]);
8989         intel_ring_emit(ring,
8990                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8991                         obj->tiling_mode);
8992
8993         /* XXX Enabling the panel-fitter across page-flip is so far
8994          * untested on non-native modes, so ignore it for now.
8995          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8996          */
8997         pf = 0;
8998         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8999         intel_ring_emit(ring, pf | pipesrc);
9000
9001         intel_mark_page_flip_active(intel_crtc);
9002         __intel_ring_advance(ring);
9003         return 0;
9004
9005 err_unpin:
9006         intel_unpin_fb_obj(obj);
9007 err:
9008         return ret;
9009 }
9010
9011 static int intel_gen6_queue_flip(struct drm_device *dev,
9012                                  struct drm_crtc *crtc,
9013                                  struct drm_framebuffer *fb,
9014                                  struct drm_i915_gem_object *obj,
9015                                  uint32_t flags)
9016 {
9017         struct drm_i915_private *dev_priv = dev->dev_private;
9018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9019         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
9020         uint32_t pf, pipesrc;
9021         int ret;
9022
9023         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9024         if (ret)
9025                 goto err;
9026
9027         ret = intel_ring_begin(ring, 4);
9028         if (ret)
9029                 goto err_unpin;
9030
9031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
9032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9033         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9034         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9035
9036         /* Contrary to the suggestions in the documentation,
9037          * "Enable Panel Fitter" does not seem to be required when page
9038          * flipping with a non-native mode, and worse causes a normal
9039          * modeset to fail.
9040          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9041          */
9042         pf = 0;
9043         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9044         intel_ring_emit(ring, pf | pipesrc);
9045
9046         intel_mark_page_flip_active(intel_crtc);
9047         __intel_ring_advance(ring);
9048         return 0;
9049
9050 err_unpin:
9051         intel_unpin_fb_obj(obj);
9052 err:
9053         return ret;
9054 }
9055
9056 static int intel_gen7_queue_flip(struct drm_device *dev,
9057                                  struct drm_crtc *crtc,
9058                                  struct drm_framebuffer *fb,
9059                                  struct drm_i915_gem_object *obj,
9060                                  uint32_t flags)
9061 {
9062         struct drm_i915_private *dev_priv = dev->dev_private;
9063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9064         struct intel_ring_buffer *ring;
9065         uint32_t plane_bit = 0;
9066         int len, ret;
9067
9068         ring = obj->ring;
9069         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
9070                 ring = &dev_priv->ring[BCS];
9071
9072         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9073         if (ret)
9074                 goto err;
9075
9076         switch (intel_crtc->plane) {
9077         case PLANE_A:
9078                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9079                 break;
9080         case PLANE_B:
9081                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9082                 break;
9083         case PLANE_C:
9084                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9085                 break;
9086         default:
9087                 WARN_ONCE(1, "unknown plane in flip command\n");
9088                 ret = -ENODEV;
9089                 goto err_unpin;
9090         }
9091
9092         len = 4;
9093         if (ring->id == RCS) {
9094                 len += 6;
9095                 /*
9096                  * On Gen 8, SRM is now taking an extra dword to accommodate
9097                  * 48bits addresses, and we need a NOOP for the batch size to
9098                  * stay even.
9099                  */
9100                 if (IS_GEN8(dev))
9101                         len += 2;
9102         }
9103
9104         /*
9105          * BSpec MI_DISPLAY_FLIP for IVB:
9106          * "The full packet must be contained within the same cache line."
9107          *
9108          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9109          * cacheline, if we ever start emitting more commands before
9110          * the MI_DISPLAY_FLIP we may need to first emit everything else,
9111          * then do the cacheline alignment, and finally emit the
9112          * MI_DISPLAY_FLIP.
9113          */
9114         ret = intel_ring_cacheline_align(ring);
9115         if (ret)
9116                 goto err_unpin;
9117
9118         ret = intel_ring_begin(ring, len);
9119         if (ret)
9120                 goto err_unpin;
9121
9122         /* Unmask the flip-done completion message. Note that the bspec says that
9123          * we should do this for both the BCS and RCS, and that we must not unmask
9124          * more than one flip event at any time (or ensure that one flip message
9125          * can be sent by waiting for flip-done prior to queueing new flips).
9126          * Experimentation says that BCS works despite DERRMR masking all
9127          * flip-done completion events and that unmasking all planes at once
9128          * for the RCS also doesn't appear to drop events. Setting the DERRMR
9129          * to zero does lead to lockups within MI_DISPLAY_FLIP.
9130          */
9131         if (ring->id == RCS) {
9132                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9133                 intel_ring_emit(ring, DERRMR);
9134                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9135                                         DERRMR_PIPEB_PRI_FLIP_DONE |
9136                                         DERRMR_PIPEC_PRI_FLIP_DONE));
9137                 if (IS_GEN8(dev))
9138                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9139                                               MI_SRM_LRM_GLOBAL_GTT);
9140                 else
9141                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9142                                               MI_SRM_LRM_GLOBAL_GTT);
9143                 intel_ring_emit(ring, DERRMR);
9144                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9145                 if (IS_GEN8(dev)) {
9146                         intel_ring_emit(ring, 0);
9147                         intel_ring_emit(ring, MI_NOOP);
9148                 }
9149         }
9150
9151         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9152         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9153         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
9154         intel_ring_emit(ring, (MI_NOOP));
9155
9156         intel_mark_page_flip_active(intel_crtc);
9157         __intel_ring_advance(ring);
9158         return 0;
9159
9160 err_unpin:
9161         intel_unpin_fb_obj(obj);
9162 err:
9163         return ret;
9164 }
9165
9166 static int intel_default_queue_flip(struct drm_device *dev,
9167                                     struct drm_crtc *crtc,
9168                                     struct drm_framebuffer *fb,
9169                                     struct drm_i915_gem_object *obj,
9170                                     uint32_t flags)
9171 {
9172         return -ENODEV;
9173 }
9174
9175 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9176                                 struct drm_framebuffer *fb,
9177                                 struct drm_pending_vblank_event *event,
9178                                 uint32_t page_flip_flags)
9179 {
9180         struct drm_device *dev = crtc->dev;
9181         struct drm_i915_private *dev_priv = dev->dev_private;
9182         struct drm_framebuffer *old_fb = crtc->primary->fb;
9183         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9185         struct intel_unpin_work *work;
9186         unsigned long flags;
9187         int ret;
9188
9189         /* Can't change pixel format via MI display flips. */
9190         if (fb->pixel_format != crtc->primary->fb->pixel_format)
9191                 return -EINVAL;
9192
9193         /*
9194          * TILEOFF/LINOFF registers can't be changed via MI display flips.
9195          * Note that pitch changes could also affect these register.
9196          */
9197         if (INTEL_INFO(dev)->gen > 3 &&
9198             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9199              fb->pitches[0] != crtc->primary->fb->pitches[0]))
9200                 return -EINVAL;
9201
9202         if (i915_terminally_wedged(&dev_priv->gpu_error))
9203                 goto out_hang;
9204
9205         work = kzalloc(sizeof(*work), GFP_KERNEL);
9206         if (work == NULL)
9207                 return -ENOMEM;
9208
9209         work->event = event;
9210         work->crtc = crtc;
9211         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9212         INIT_WORK(&work->work, intel_unpin_work_fn);
9213
9214         ret = drm_vblank_get(dev, intel_crtc->pipe);
9215         if (ret)
9216                 goto free_work;
9217
9218         /* We borrow the event spin lock for protecting unpin_work */
9219         spin_lock_irqsave(&dev->event_lock, flags);
9220         if (intel_crtc->unpin_work) {
9221                 spin_unlock_irqrestore(&dev->event_lock, flags);
9222                 kfree(work);
9223                 drm_vblank_put(dev, intel_crtc->pipe);
9224
9225                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9226                 return -EBUSY;
9227         }
9228         intel_crtc->unpin_work = work;
9229         spin_unlock_irqrestore(&dev->event_lock, flags);
9230
9231         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9232                 flush_workqueue(dev_priv->wq);
9233
9234         ret = i915_mutex_lock_interruptible(dev);
9235         if (ret)
9236                 goto cleanup;
9237
9238         /* Reference the objects for the scheduled work. */
9239         drm_gem_object_reference(&work->old_fb_obj->base);
9240         drm_gem_object_reference(&obj->base);
9241
9242         crtc->primary->fb = fb;
9243
9244         work->pending_flip_obj = obj;
9245
9246         work->enable_stall_check = true;
9247
9248         atomic_inc(&intel_crtc->unpin_work_count);
9249         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9250
9251         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
9252         if (ret)
9253                 goto cleanup_pending;
9254
9255         intel_disable_fbc(dev);
9256         intel_mark_fb_busy(obj, NULL);
9257         mutex_unlock(&dev->struct_mutex);
9258
9259         trace_i915_flip_request(intel_crtc->plane, obj);
9260
9261         return 0;
9262
9263 cleanup_pending:
9264         atomic_dec(&intel_crtc->unpin_work_count);
9265         crtc->primary->fb = old_fb;
9266         drm_gem_object_unreference(&work->old_fb_obj->base);
9267         drm_gem_object_unreference(&obj->base);
9268         mutex_unlock(&dev->struct_mutex);
9269
9270 cleanup:
9271         spin_lock_irqsave(&dev->event_lock, flags);
9272         intel_crtc->unpin_work = NULL;
9273         spin_unlock_irqrestore(&dev->event_lock, flags);
9274
9275         drm_vblank_put(dev, intel_crtc->pipe);
9276 free_work:
9277         kfree(work);
9278
9279         if (ret == -EIO) {
9280 out_hang:
9281                 intel_crtc_wait_for_pending_flips(crtc);
9282                 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9283                 if (ret == 0 && event)
9284                         drm_send_vblank_event(dev, intel_crtc->pipe, event);
9285         }
9286         return ret;
9287 }
9288
9289 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9290         .mode_set_base_atomic = intel_pipe_set_base_atomic,
9291         .load_lut = intel_crtc_load_lut,
9292 };
9293
9294 /**
9295  * intel_modeset_update_staged_output_state
9296  *
9297  * Updates the staged output configuration state, e.g. after we've read out the
9298  * current hw state.
9299  */
9300 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9301 {
9302         struct intel_crtc *crtc;
9303         struct intel_encoder *encoder;
9304         struct intel_connector *connector;
9305
9306         list_for_each_entry(connector, &dev->mode_config.connector_list,
9307                             base.head) {
9308                 connector->new_encoder =
9309                         to_intel_encoder(connector->base.encoder);
9310         }
9311
9312         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9313                             base.head) {
9314                 encoder->new_crtc =
9315                         to_intel_crtc(encoder->base.crtc);
9316         }
9317
9318         for_each_intel_crtc(dev, crtc) {
9319                 crtc->new_enabled = crtc->base.enabled;
9320
9321                 if (crtc->new_enabled)
9322                         crtc->new_config = &crtc->config;
9323                 else
9324                         crtc->new_config = NULL;
9325         }
9326 }
9327
9328 /**
9329  * intel_modeset_commit_output_state
9330  *
9331  * This function copies the stage display pipe configuration to the real one.
9332  */
9333 static void intel_modeset_commit_output_state(struct drm_device *dev)
9334 {
9335         struct intel_crtc *crtc;
9336         struct intel_encoder *encoder;
9337         struct intel_connector *connector;
9338
9339         list_for_each_entry(connector, &dev->mode_config.connector_list,
9340                             base.head) {
9341                 connector->base.encoder = &connector->new_encoder->base;
9342         }
9343
9344         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9345                             base.head) {
9346                 encoder->base.crtc = &encoder->new_crtc->base;
9347         }
9348
9349         for_each_intel_crtc(dev, crtc) {
9350                 crtc->base.enabled = crtc->new_enabled;
9351         }
9352 }
9353
9354 static void
9355 connected_sink_compute_bpp(struct intel_connector *connector,
9356                            struct intel_crtc_config *pipe_config)
9357 {
9358         int bpp = pipe_config->pipe_bpp;
9359
9360         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9361                 connector->base.base.id,
9362                 drm_get_connector_name(&connector->base));
9363
9364         /* Don't use an invalid EDID bpc value */
9365         if (connector->base.display_info.bpc &&
9366             connector->base.display_info.bpc * 3 < bpp) {
9367                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9368                               bpp, connector->base.display_info.bpc*3);
9369                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9370         }
9371
9372         /* Clamp bpp to 8 on screens without EDID 1.4 */
9373         if (connector->base.display_info.bpc == 0 && bpp > 24) {
9374                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9375                               bpp);
9376                 pipe_config->pipe_bpp = 24;
9377         }
9378 }
9379
9380 static int
9381 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9382                           struct drm_framebuffer *fb,
9383                           struct intel_crtc_config *pipe_config)
9384 {
9385         struct drm_device *dev = crtc->base.dev;
9386         struct intel_connector *connector;
9387         int bpp;
9388
9389         switch (fb->pixel_format) {
9390         case DRM_FORMAT_C8:
9391                 bpp = 8*3; /* since we go through a colormap */
9392                 break;
9393         case DRM_FORMAT_XRGB1555:
9394         case DRM_FORMAT_ARGB1555:
9395                 /* checked in intel_framebuffer_init already */
9396                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9397                         return -EINVAL;
9398         case DRM_FORMAT_RGB565:
9399                 bpp = 6*3; /* min is 18bpp */
9400                 break;
9401         case DRM_FORMAT_XBGR8888:
9402         case DRM_FORMAT_ABGR8888:
9403                 /* checked in intel_framebuffer_init already */
9404                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9405                         return -EINVAL;
9406         case DRM_FORMAT_XRGB8888:
9407         case DRM_FORMAT_ARGB8888:
9408                 bpp = 8*3;
9409                 break;
9410         case DRM_FORMAT_XRGB2101010:
9411         case DRM_FORMAT_ARGB2101010:
9412         case DRM_FORMAT_XBGR2101010:
9413         case DRM_FORMAT_ABGR2101010:
9414                 /* checked in intel_framebuffer_init already */
9415                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9416                         return -EINVAL;
9417                 bpp = 10*3;
9418                 break;
9419         /* TODO: gen4+ supports 16 bpc floating point, too. */
9420         default:
9421                 DRM_DEBUG_KMS("unsupported depth\n");
9422                 return -EINVAL;
9423         }
9424
9425         pipe_config->pipe_bpp = bpp;
9426
9427         /* Clamp display bpp to EDID value */
9428         list_for_each_entry(connector, &dev->mode_config.connector_list,
9429                             base.head) {
9430                 if (!connector->new_encoder ||
9431                     connector->new_encoder->new_crtc != crtc)
9432                         continue;
9433
9434                 connected_sink_compute_bpp(connector, pipe_config);
9435         }
9436
9437         return bpp;
9438 }
9439
9440 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9441 {
9442         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9443                         "type: 0x%x flags: 0x%x\n",
9444                 mode->crtc_clock,
9445                 mode->crtc_hdisplay, mode->crtc_hsync_start,
9446                 mode->crtc_hsync_end, mode->crtc_htotal,
9447                 mode->crtc_vdisplay, mode->crtc_vsync_start,
9448                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9449 }
9450
9451 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9452                                    struct intel_crtc_config *pipe_config,
9453                                    const char *context)
9454 {
9455         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9456                       context, pipe_name(crtc->pipe));
9457
9458         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9459         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9460                       pipe_config->pipe_bpp, pipe_config->dither);
9461         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9462                       pipe_config->has_pch_encoder,
9463                       pipe_config->fdi_lanes,
9464                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9465                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9466                       pipe_config->fdi_m_n.tu);
9467         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9468                       pipe_config->has_dp_encoder,
9469                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9470                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9471                       pipe_config->dp_m_n.tu);
9472         DRM_DEBUG_KMS("requested mode:\n");
9473         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9474         DRM_DEBUG_KMS("adjusted mode:\n");
9475         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9476         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9477         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9478         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9479                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9480         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9481                       pipe_config->gmch_pfit.control,
9482                       pipe_config->gmch_pfit.pgm_ratios,
9483                       pipe_config->gmch_pfit.lvds_border_bits);
9484         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9485                       pipe_config->pch_pfit.pos,
9486                       pipe_config->pch_pfit.size,
9487                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9488         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9489         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9490 }
9491
9492 static bool encoders_cloneable(const struct intel_encoder *a,
9493                                const struct intel_encoder *b)
9494 {
9495         /* masks could be asymmetric, so check both ways */
9496         return a == b || (a->cloneable & (1 << b->type) &&
9497                           b->cloneable & (1 << a->type));
9498 }
9499
9500 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9501                                          struct intel_encoder *encoder)
9502 {
9503         struct drm_device *dev = crtc->base.dev;
9504         struct intel_encoder *source_encoder;
9505
9506         list_for_each_entry(source_encoder,
9507                             &dev->mode_config.encoder_list, base.head) {
9508                 if (source_encoder->new_crtc != crtc)
9509                         continue;
9510
9511                 if (!encoders_cloneable(encoder, source_encoder))
9512                         return false;
9513         }
9514
9515         return true;
9516 }
9517
9518 static bool check_encoder_cloning(struct intel_crtc *crtc)
9519 {
9520         struct drm_device *dev = crtc->base.dev;
9521         struct intel_encoder *encoder;
9522
9523         list_for_each_entry(encoder,
9524                             &dev->mode_config.encoder_list, base.head) {
9525                 if (encoder->new_crtc != crtc)
9526                         continue;
9527
9528                 if (!check_single_encoder_cloning(crtc, encoder))
9529                         return false;
9530         }
9531
9532         return true;
9533 }
9534
9535 static struct intel_crtc_config *
9536 intel_modeset_pipe_config(struct drm_crtc *crtc,
9537                           struct drm_framebuffer *fb,
9538                           struct drm_display_mode *mode)
9539 {
9540         struct drm_device *dev = crtc->dev;
9541         struct intel_encoder *encoder;
9542         struct intel_crtc_config *pipe_config;
9543         int plane_bpp, ret = -EINVAL;
9544         bool retry = true;
9545
9546         if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9547                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9548                 return ERR_PTR(-EINVAL);
9549         }
9550
9551         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9552         if (!pipe_config)
9553                 return ERR_PTR(-ENOMEM);
9554
9555         drm_mode_copy(&pipe_config->adjusted_mode, mode);
9556         drm_mode_copy(&pipe_config->requested_mode, mode);
9557
9558         pipe_config->cpu_transcoder =
9559                 (enum transcoder) to_intel_crtc(crtc)->pipe;
9560         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9561
9562         /*
9563          * Sanitize sync polarity flags based on requested ones. If neither
9564          * positive or negative polarity is requested, treat this as meaning
9565          * negative polarity.
9566          */
9567         if (!(pipe_config->adjusted_mode.flags &
9568               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9569                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9570
9571         if (!(pipe_config->adjusted_mode.flags &
9572               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9573                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9574
9575         /* Compute a starting value for pipe_config->pipe_bpp taking the source
9576          * plane pixel format and any sink constraints into account. Returns the
9577          * source plane bpp so that dithering can be selected on mismatches
9578          * after encoders and crtc also have had their say. */
9579         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9580                                               fb, pipe_config);
9581         if (plane_bpp < 0)
9582                 goto fail;
9583
9584         /*
9585          * Determine the real pipe dimensions. Note that stereo modes can
9586          * increase the actual pipe size due to the frame doubling and
9587          * insertion of additional space for blanks between the frame. This
9588          * is stored in the crtc timings. We use the requested mode to do this
9589          * computation to clearly distinguish it from the adjusted mode, which
9590          * can be changed by the connectors in the below retry loop.
9591          */
9592         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9593         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9594         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9595
9596 encoder_retry:
9597         /* Ensure the port clock defaults are reset when retrying. */
9598         pipe_config->port_clock = 0;
9599         pipe_config->pixel_multiplier = 1;
9600
9601         /* Fill in default crtc timings, allow encoders to overwrite them. */
9602         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9603
9604         /* Pass our mode to the connectors and the CRTC to give them a chance to
9605          * adjust it according to limitations or connector properties, and also
9606          * a chance to reject the mode entirely.
9607          */
9608         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9609                             base.head) {
9610
9611                 if (&encoder->new_crtc->base != crtc)
9612                         continue;
9613
9614                 if (!(encoder->compute_config(encoder, pipe_config))) {
9615                         DRM_DEBUG_KMS("Encoder config failure\n");
9616                         goto fail;
9617                 }
9618         }
9619
9620         /* Set default port clock if not overwritten by the encoder. Needs to be
9621          * done afterwards in case the encoder adjusts the mode. */
9622         if (!pipe_config->port_clock)
9623                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9624                         * pipe_config->pixel_multiplier;
9625
9626         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9627         if (ret < 0) {
9628                 DRM_DEBUG_KMS("CRTC fixup failed\n");
9629                 goto fail;
9630         }
9631
9632         if (ret == RETRY) {
9633                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9634                         ret = -EINVAL;
9635                         goto fail;
9636                 }
9637
9638                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9639                 retry = false;
9640                 goto encoder_retry;
9641         }
9642
9643         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9644         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9645                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9646
9647         return pipe_config;
9648 fail:
9649         kfree(pipe_config);
9650         return ERR_PTR(ret);
9651 }
9652
9653 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9654  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9655 static void
9656 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9657                              unsigned *prepare_pipes, unsigned *disable_pipes)
9658 {
9659         struct intel_crtc *intel_crtc;
9660         struct drm_device *dev = crtc->dev;
9661         struct intel_encoder *encoder;
9662         struct intel_connector *connector;
9663         struct drm_crtc *tmp_crtc;
9664
9665         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9666
9667         /* Check which crtcs have changed outputs connected to them, these need
9668          * to be part of the prepare_pipes mask. We don't (yet) support global
9669          * modeset across multiple crtcs, so modeset_pipes will only have one
9670          * bit set at most. */
9671         list_for_each_entry(connector, &dev->mode_config.connector_list,
9672                             base.head) {
9673                 if (connector->base.encoder == &connector->new_encoder->base)
9674                         continue;
9675
9676                 if (connector->base.encoder) {
9677                         tmp_crtc = connector->base.encoder->crtc;
9678
9679                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9680                 }
9681
9682                 if (connector->new_encoder)
9683                         *prepare_pipes |=
9684                                 1 << connector->new_encoder->new_crtc->pipe;
9685         }
9686
9687         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9688                             base.head) {
9689                 if (encoder->base.crtc == &encoder->new_crtc->base)
9690                         continue;
9691
9692                 if (encoder->base.crtc) {
9693                         tmp_crtc = encoder->base.crtc;
9694
9695                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9696                 }
9697
9698                 if (encoder->new_crtc)
9699                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9700         }
9701
9702         /* Check for pipes that will be enabled/disabled ... */
9703         for_each_intel_crtc(dev, intel_crtc) {
9704                 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9705                         continue;
9706
9707                 if (!intel_crtc->new_enabled)
9708                         *disable_pipes |= 1 << intel_crtc->pipe;
9709                 else
9710                         *prepare_pipes |= 1 << intel_crtc->pipe;
9711         }
9712
9713
9714         /* set_mode is also used to update properties on life display pipes. */
9715         intel_crtc = to_intel_crtc(crtc);
9716         if (intel_crtc->new_enabled)
9717                 *prepare_pipes |= 1 << intel_crtc->pipe;
9718
9719         /*
9720          * For simplicity do a full modeset on any pipe where the output routing
9721          * changed. We could be more clever, but that would require us to be
9722          * more careful with calling the relevant encoder->mode_set functions.
9723          */
9724         if (*prepare_pipes)
9725                 *modeset_pipes = *prepare_pipes;
9726
9727         /* ... and mask these out. */
9728         *modeset_pipes &= ~(*disable_pipes);
9729         *prepare_pipes &= ~(*disable_pipes);
9730
9731         /*
9732          * HACK: We don't (yet) fully support global modesets. intel_set_config
9733          * obies this rule, but the modeset restore mode of
9734          * intel_modeset_setup_hw_state does not.
9735          */
9736         *modeset_pipes &= 1 << intel_crtc->pipe;
9737         *prepare_pipes &= 1 << intel_crtc->pipe;
9738
9739         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9740                       *modeset_pipes, *prepare_pipes, *disable_pipes);
9741 }
9742
9743 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9744 {
9745         struct drm_encoder *encoder;
9746         struct drm_device *dev = crtc->dev;
9747
9748         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9749                 if (encoder->crtc == crtc)
9750                         return true;
9751
9752         return false;
9753 }
9754
9755 static void
9756 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9757 {
9758         struct intel_encoder *intel_encoder;
9759         struct intel_crtc *intel_crtc;
9760         struct drm_connector *connector;
9761
9762         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9763                             base.head) {
9764                 if (!intel_encoder->base.crtc)
9765                         continue;
9766
9767                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9768
9769                 if (prepare_pipes & (1 << intel_crtc->pipe))
9770                         intel_encoder->connectors_active = false;
9771         }
9772
9773         intel_modeset_commit_output_state(dev);
9774
9775         /* Double check state. */
9776         for_each_intel_crtc(dev, intel_crtc) {
9777                 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9778                 WARN_ON(intel_crtc->new_config &&
9779                         intel_crtc->new_config != &intel_crtc->config);
9780                 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9781         }
9782
9783         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9784                 if (!connector->encoder || !connector->encoder->crtc)
9785                         continue;
9786
9787                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9788
9789                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9790                         struct drm_property *dpms_property =
9791                                 dev->mode_config.dpms_property;
9792
9793                         connector->dpms = DRM_MODE_DPMS_ON;
9794                         drm_object_property_set_value(&connector->base,
9795                                                          dpms_property,
9796                                                          DRM_MODE_DPMS_ON);
9797
9798                         intel_encoder = to_intel_encoder(connector->encoder);
9799                         intel_encoder->connectors_active = true;
9800                 }
9801         }
9802
9803 }
9804
9805 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9806 {
9807         int diff;
9808
9809         if (clock1 == clock2)
9810                 return true;
9811
9812         if (!clock1 || !clock2)
9813                 return false;
9814
9815         diff = abs(clock1 - clock2);
9816
9817         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9818                 return true;
9819
9820         return false;
9821 }
9822
9823 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9824         list_for_each_entry((intel_crtc), \
9825                             &(dev)->mode_config.crtc_list, \
9826                             base.head) \
9827                 if (mask & (1 <<(intel_crtc)->pipe))
9828
9829 static bool
9830 intel_pipe_config_compare(struct drm_device *dev,
9831                           struct intel_crtc_config *current_config,
9832                           struct intel_crtc_config *pipe_config)
9833 {
9834 #define PIPE_CONF_CHECK_X(name) \
9835         if (current_config->name != pipe_config->name) { \
9836                 DRM_ERROR("mismatch in " #name " " \
9837                           "(expected 0x%08x, found 0x%08x)\n", \
9838                           current_config->name, \
9839                           pipe_config->name); \
9840                 return false; \
9841         }
9842
9843 #define PIPE_CONF_CHECK_I(name) \
9844         if (current_config->name != pipe_config->name) { \
9845                 DRM_ERROR("mismatch in " #name " " \
9846                           "(expected %i, found %i)\n", \
9847                           current_config->name, \
9848                           pipe_config->name); \
9849                 return false; \
9850         }
9851
9852 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
9853         if ((current_config->name ^ pipe_config->name) & (mask)) { \
9854                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
9855                           "(expected %i, found %i)\n", \
9856                           current_config->name & (mask), \
9857                           pipe_config->name & (mask)); \
9858                 return false; \
9859         }
9860
9861 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9862         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9863                 DRM_ERROR("mismatch in " #name " " \
9864                           "(expected %i, found %i)\n", \
9865                           current_config->name, \
9866                           pipe_config->name); \
9867                 return false; \
9868         }
9869
9870 #define PIPE_CONF_QUIRK(quirk)  \
9871         ((current_config->quirks | pipe_config->quirks) & (quirk))
9872
9873         PIPE_CONF_CHECK_I(cpu_transcoder);
9874
9875         PIPE_CONF_CHECK_I(has_pch_encoder);
9876         PIPE_CONF_CHECK_I(fdi_lanes);
9877         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9878         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9879         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9880         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9881         PIPE_CONF_CHECK_I(fdi_m_n.tu);
9882
9883         PIPE_CONF_CHECK_I(has_dp_encoder);
9884         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9885         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9886         PIPE_CONF_CHECK_I(dp_m_n.link_m);
9887         PIPE_CONF_CHECK_I(dp_m_n.link_n);
9888         PIPE_CONF_CHECK_I(dp_m_n.tu);
9889
9890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9896
9897         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9898         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9899         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9900         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9901         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9902         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9903
9904         PIPE_CONF_CHECK_I(pixel_multiplier);
9905         PIPE_CONF_CHECK_I(has_hdmi_sink);
9906         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9907             IS_VALLEYVIEW(dev))
9908                 PIPE_CONF_CHECK_I(limited_color_range);
9909
9910         PIPE_CONF_CHECK_I(has_audio);
9911
9912         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9913                               DRM_MODE_FLAG_INTERLACE);
9914
9915         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9916                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9917                                       DRM_MODE_FLAG_PHSYNC);
9918                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9919                                       DRM_MODE_FLAG_NHSYNC);
9920                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9921                                       DRM_MODE_FLAG_PVSYNC);
9922                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9923                                       DRM_MODE_FLAG_NVSYNC);
9924         }
9925
9926         PIPE_CONF_CHECK_I(pipe_src_w);
9927         PIPE_CONF_CHECK_I(pipe_src_h);
9928
9929         /*
9930          * FIXME: BIOS likes to set up a cloned config with lvds+external
9931          * screen. Since we don't yet re-compute the pipe config when moving
9932          * just the lvds port away to another pipe the sw tracking won't match.
9933          *
9934          * Proper atomic modesets with recomputed global state will fix this.
9935          * Until then just don't check gmch state for inherited modes.
9936          */
9937         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9938                 PIPE_CONF_CHECK_I(gmch_pfit.control);
9939                 /* pfit ratios are autocomputed by the hw on gen4+ */
9940                 if (INTEL_INFO(dev)->gen < 4)
9941                         PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9942                 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9943         }
9944
9945         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9946         if (current_config->pch_pfit.enabled) {
9947                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9948                 PIPE_CONF_CHECK_I(pch_pfit.size);
9949         }
9950
9951         /* BDW+ don't expose a synchronous way to read the state */
9952         if (IS_HASWELL(dev))
9953                 PIPE_CONF_CHECK_I(ips_enabled);
9954
9955         PIPE_CONF_CHECK_I(double_wide);
9956
9957         PIPE_CONF_CHECK_I(shared_dpll);
9958         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9959         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9960         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9961         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9962
9963         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9964                 PIPE_CONF_CHECK_I(pipe_bpp);
9965
9966         PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9967         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9968
9969 #undef PIPE_CONF_CHECK_X
9970 #undef PIPE_CONF_CHECK_I
9971 #undef PIPE_CONF_CHECK_FLAGS
9972 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9973 #undef PIPE_CONF_QUIRK
9974
9975         return true;
9976 }
9977
9978 static void
9979 check_connector_state(struct drm_device *dev)
9980 {
9981         struct intel_connector *connector;
9982
9983         list_for_each_entry(connector, &dev->mode_config.connector_list,
9984                             base.head) {
9985                 /* This also checks the encoder/connector hw state with the
9986                  * ->get_hw_state callbacks. */
9987                 intel_connector_check_state(connector);
9988
9989                 WARN(&connector->new_encoder->base != connector->base.encoder,
9990                      "connector's staged encoder doesn't match current encoder\n");
9991         }
9992 }
9993
9994 static void
9995 check_encoder_state(struct drm_device *dev)
9996 {
9997         struct intel_encoder *encoder;
9998         struct intel_connector *connector;
9999
10000         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10001                             base.head) {
10002                 bool enabled = false;
10003                 bool active = false;
10004                 enum pipe pipe, tracked_pipe;
10005
10006                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10007                               encoder->base.base.id,
10008                               drm_get_encoder_name(&encoder->base));
10009
10010                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10011                      "encoder's stage crtc doesn't match current crtc\n");
10012                 WARN(encoder->connectors_active && !encoder->base.crtc,
10013                      "encoder's active_connectors set, but no crtc\n");
10014
10015                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10016                                     base.head) {
10017                         if (connector->base.encoder != &encoder->base)
10018                                 continue;
10019                         enabled = true;
10020                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10021                                 active = true;
10022                 }
10023                 WARN(!!encoder->base.crtc != enabled,
10024                      "encoder's enabled state mismatch "
10025                      "(expected %i, found %i)\n",
10026                      !!encoder->base.crtc, enabled);
10027                 WARN(active && !encoder->base.crtc,
10028                      "active encoder with no crtc\n");
10029
10030                 WARN(encoder->connectors_active != active,
10031                      "encoder's computed active state doesn't match tracked active state "
10032                      "(expected %i, found %i)\n", active, encoder->connectors_active);
10033
10034                 active = encoder->get_hw_state(encoder, &pipe);
10035                 WARN(active != encoder->connectors_active,
10036                      "encoder's hw state doesn't match sw tracking "
10037                      "(expected %i, found %i)\n",
10038                      encoder->connectors_active, active);
10039
10040                 if (!encoder->base.crtc)
10041                         continue;
10042
10043                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10044                 WARN(active && pipe != tracked_pipe,
10045                      "active encoder's pipe doesn't match"
10046                      "(expected %i, found %i)\n",
10047                      tracked_pipe, pipe);
10048
10049         }
10050 }
10051
10052 static void
10053 check_crtc_state(struct drm_device *dev)
10054 {
10055         struct drm_i915_private *dev_priv = dev->dev_private;
10056         struct intel_crtc *crtc;
10057         struct intel_encoder *encoder;
10058         struct intel_crtc_config pipe_config;
10059
10060         for_each_intel_crtc(dev, crtc) {
10061                 bool enabled = false;
10062                 bool active = false;
10063
10064                 memset(&pipe_config, 0, sizeof(pipe_config));
10065
10066                 DRM_DEBUG_KMS("[CRTC:%d]\n",
10067                               crtc->base.base.id);
10068
10069                 WARN(crtc->active && !crtc->base.enabled,
10070                      "active crtc, but not enabled in sw tracking\n");
10071
10072                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10073                                     base.head) {
10074                         if (encoder->base.crtc != &crtc->base)
10075                                 continue;
10076                         enabled = true;
10077                         if (encoder->connectors_active)
10078                                 active = true;
10079                 }
10080
10081                 WARN(active != crtc->active,
10082                      "crtc's computed active state doesn't match tracked active state "
10083                      "(expected %i, found %i)\n", active, crtc->active);
10084                 WARN(enabled != crtc->base.enabled,
10085                      "crtc's computed enabled state doesn't match tracked enabled state "
10086                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10087
10088                 active = dev_priv->display.get_pipe_config(crtc,
10089                                                            &pipe_config);
10090
10091                 /* hw state is inconsistent with the pipe A quirk */
10092                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10093                         active = crtc->active;
10094
10095                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10096                                     base.head) {
10097                         enum pipe pipe;
10098                         if (encoder->base.crtc != &crtc->base)
10099                                 continue;
10100                         if (encoder->get_hw_state(encoder, &pipe))
10101                                 encoder->get_config(encoder, &pipe_config);
10102                 }
10103
10104                 WARN(crtc->active != active,
10105                      "crtc active state doesn't match with hw state "
10106                      "(expected %i, found %i)\n", crtc->active, active);
10107
10108                 if (active &&
10109                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10110                         WARN(1, "pipe state doesn't match!\n");
10111                         intel_dump_pipe_config(crtc, &pipe_config,
10112                                                "[hw state]");
10113                         intel_dump_pipe_config(crtc, &crtc->config,
10114                                                "[sw state]");
10115                 }
10116         }
10117 }
10118
10119 static void
10120 check_shared_dpll_state(struct drm_device *dev)
10121 {
10122         struct drm_i915_private *dev_priv = dev->dev_private;
10123         struct intel_crtc *crtc;
10124         struct intel_dpll_hw_state dpll_hw_state;
10125         int i;
10126
10127         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10128                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10129                 int enabled_crtcs = 0, active_crtcs = 0;
10130                 bool active;
10131
10132                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10133
10134                 DRM_DEBUG_KMS("%s\n", pll->name);
10135
10136                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10137
10138                 WARN(pll->active > pll->refcount,
10139                      "more active pll users than references: %i vs %i\n",
10140                      pll->active, pll->refcount);
10141                 WARN(pll->active && !pll->on,
10142                      "pll in active use but not on in sw tracking\n");
10143                 WARN(pll->on && !pll->active,
10144                      "pll in on but not on in use in sw tracking\n");
10145                 WARN(pll->on != active,
10146                      "pll on state mismatch (expected %i, found %i)\n",
10147                      pll->on, active);
10148
10149                 for_each_intel_crtc(dev, crtc) {
10150                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10151                                 enabled_crtcs++;
10152                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10153                                 active_crtcs++;
10154                 }
10155                 WARN(pll->active != active_crtcs,
10156                      "pll active crtcs mismatch (expected %i, found %i)\n",
10157                      pll->active, active_crtcs);
10158                 WARN(pll->refcount != enabled_crtcs,
10159                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
10160                      pll->refcount, enabled_crtcs);
10161
10162                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10163                                        sizeof(dpll_hw_state)),
10164                      "pll hw state mismatch\n");
10165         }
10166 }
10167
10168 void
10169 intel_modeset_check_state(struct drm_device *dev)
10170 {
10171         check_connector_state(dev);
10172         check_encoder_state(dev);
10173         check_crtc_state(dev);
10174         check_shared_dpll_state(dev);
10175 }
10176
10177 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10178                                      int dotclock)
10179 {
10180         /*
10181          * FDI already provided one idea for the dotclock.
10182          * Yell if the encoder disagrees.
10183          */
10184         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10185              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10186              pipe_config->adjusted_mode.crtc_clock, dotclock);
10187 }
10188
10189 static int __intel_set_mode(struct drm_crtc *crtc,
10190                             struct drm_display_mode *mode,
10191                             int x, int y, struct drm_framebuffer *fb)
10192 {
10193         struct drm_device *dev = crtc->dev;
10194         struct drm_i915_private *dev_priv = dev->dev_private;
10195         struct drm_display_mode *saved_mode;
10196         struct intel_crtc_config *pipe_config = NULL;
10197         struct intel_crtc *intel_crtc;
10198         unsigned disable_pipes, prepare_pipes, modeset_pipes;
10199         int ret = 0;
10200
10201         saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10202         if (!saved_mode)
10203                 return -ENOMEM;
10204
10205         intel_modeset_affected_pipes(crtc, &modeset_pipes,
10206                                      &prepare_pipes, &disable_pipes);
10207
10208         *saved_mode = crtc->mode;
10209
10210         /* Hack: Because we don't (yet) support global modeset on multiple
10211          * crtcs, we don't keep track of the new mode for more than one crtc.
10212          * Hence simply check whether any bit is set in modeset_pipes in all the
10213          * pieces of code that are not yet converted to deal with mutliple crtcs
10214          * changing their mode at the same time. */
10215         if (modeset_pipes) {
10216                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10217                 if (IS_ERR(pipe_config)) {
10218                         ret = PTR_ERR(pipe_config);
10219                         pipe_config = NULL;
10220
10221                         goto out;
10222                 }
10223                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10224                                        "[modeset]");
10225                 to_intel_crtc(crtc)->new_config = pipe_config;
10226         }
10227
10228         /*
10229          * See if the config requires any additional preparation, e.g.
10230          * to adjust global state with pipes off.  We need to do this
10231          * here so we can get the modeset_pipe updated config for the new
10232          * mode set on this crtc.  For other crtcs we need to use the
10233          * adjusted_mode bits in the crtc directly.
10234          */
10235         if (IS_VALLEYVIEW(dev)) {
10236                 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10237
10238                 /* may have added more to prepare_pipes than we should */
10239                 prepare_pipes &= ~disable_pipes;
10240         }
10241
10242         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10243                 intel_crtc_disable(&intel_crtc->base);
10244
10245         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10246                 if (intel_crtc->base.enabled)
10247                         dev_priv->display.crtc_disable(&intel_crtc->base);
10248         }
10249
10250         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10251          * to set it here already despite that we pass it down the callchain.
10252          */
10253         if (modeset_pipes) {
10254                 crtc->mode = *mode;
10255                 /* mode_set/enable/disable functions rely on a correct pipe
10256                  * config. */
10257                 to_intel_crtc(crtc)->config = *pipe_config;
10258                 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10259
10260                 /*
10261                  * Calculate and store various constants which
10262                  * are later needed by vblank and swap-completion
10263                  * timestamping. They are derived from true hwmode.
10264                  */
10265                 drm_calc_timestamping_constants(crtc,
10266                                                 &pipe_config->adjusted_mode);
10267         }
10268
10269         /* Only after disabling all output pipelines that will be changed can we
10270          * update the the output configuration. */
10271         intel_modeset_update_state(dev, prepare_pipes);
10272
10273         if (dev_priv->display.modeset_global_resources)
10274                 dev_priv->display.modeset_global_resources(dev);
10275
10276         /* Set up the DPLL and any encoders state that needs to adjust or depend
10277          * on the DPLL.
10278          */
10279         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10280                 struct drm_framebuffer *old_fb;
10281
10282                 mutex_lock(&dev->struct_mutex);
10283                 ret = intel_pin_and_fence_fb_obj(dev,
10284                                                  to_intel_framebuffer(fb)->obj,
10285                                                  NULL);
10286                 if (ret != 0) {
10287                         DRM_ERROR("pin & fence failed\n");
10288                         mutex_unlock(&dev->struct_mutex);
10289                         goto done;
10290                 }
10291                 old_fb = crtc->primary->fb;
10292                 if (old_fb)
10293                         intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10294                 mutex_unlock(&dev->struct_mutex);
10295
10296                 crtc->primary->fb = fb;
10297                 crtc->x = x;
10298                 crtc->y = y;
10299
10300                 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10301                                                       x, y, fb);
10302                 if (ret)
10303                         goto done;
10304         }
10305
10306         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10307         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
10308                 dev_priv->display.crtc_enable(&intel_crtc->base);
10309
10310         /* FIXME: add subpixel order */
10311 done:
10312         if (ret && crtc->enabled)
10313                 crtc->mode = *saved_mode;
10314
10315 out:
10316         kfree(pipe_config);
10317         kfree(saved_mode);
10318         return ret;
10319 }
10320
10321 static int intel_set_mode(struct drm_crtc *crtc,
10322                           struct drm_display_mode *mode,
10323                           int x, int y, struct drm_framebuffer *fb)
10324 {
10325         int ret;
10326
10327         ret = __intel_set_mode(crtc, mode, x, y, fb);
10328
10329         if (ret == 0)
10330                 intel_modeset_check_state(crtc->dev);
10331
10332         return ret;
10333 }
10334
10335 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10336 {
10337         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10338 }
10339
10340 #undef for_each_intel_crtc_masked
10341
10342 static void intel_set_config_free(struct intel_set_config *config)
10343 {
10344         if (!config)
10345                 return;
10346
10347         kfree(config->save_connector_encoders);
10348         kfree(config->save_encoder_crtcs);
10349         kfree(config->save_crtc_enabled);
10350         kfree(config);
10351 }
10352
10353 static int intel_set_config_save_state(struct drm_device *dev,
10354                                        struct intel_set_config *config)
10355 {
10356         struct drm_crtc *crtc;
10357         struct drm_encoder *encoder;
10358         struct drm_connector *connector;
10359         int count;
10360
10361         config->save_crtc_enabled =
10362                 kcalloc(dev->mode_config.num_crtc,
10363                         sizeof(bool), GFP_KERNEL);
10364         if (!config->save_crtc_enabled)
10365                 return -ENOMEM;
10366
10367         config->save_encoder_crtcs =
10368                 kcalloc(dev->mode_config.num_encoder,
10369                         sizeof(struct drm_crtc *), GFP_KERNEL);
10370         if (!config->save_encoder_crtcs)
10371                 return -ENOMEM;
10372
10373         config->save_connector_encoders =
10374                 kcalloc(dev->mode_config.num_connector,
10375                         sizeof(struct drm_encoder *), GFP_KERNEL);
10376         if (!config->save_connector_encoders)
10377                 return -ENOMEM;
10378
10379         /* Copy data. Note that driver private data is not affected.
10380          * Should anything bad happen only the expected state is
10381          * restored, not the drivers personal bookkeeping.
10382          */
10383         count = 0;
10384         for_each_crtc(dev, crtc) {
10385                 config->save_crtc_enabled[count++] = crtc->enabled;
10386         }
10387
10388         count = 0;
10389         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10390                 config->save_encoder_crtcs[count++] = encoder->crtc;
10391         }
10392
10393         count = 0;
10394         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10395                 config->save_connector_encoders[count++] = connector->encoder;
10396         }
10397
10398         return 0;
10399 }
10400
10401 static void intel_set_config_restore_state(struct drm_device *dev,
10402                                            struct intel_set_config *config)
10403 {
10404         struct intel_crtc *crtc;
10405         struct intel_encoder *encoder;
10406         struct intel_connector *connector;
10407         int count;
10408
10409         count = 0;
10410         for_each_intel_crtc(dev, crtc) {
10411                 crtc->new_enabled = config->save_crtc_enabled[count++];
10412
10413                 if (crtc->new_enabled)
10414                         crtc->new_config = &crtc->config;
10415                 else
10416                         crtc->new_config = NULL;
10417         }
10418
10419         count = 0;
10420         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10421                 encoder->new_crtc =
10422                         to_intel_crtc(config->save_encoder_crtcs[count++]);
10423         }
10424
10425         count = 0;
10426         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10427                 connector->new_encoder =
10428                         to_intel_encoder(config->save_connector_encoders[count++]);
10429         }
10430 }
10431
10432 static bool
10433 is_crtc_connector_off(struct drm_mode_set *set)
10434 {
10435         int i;
10436
10437         if (set->num_connectors == 0)
10438                 return false;
10439
10440         if (WARN_ON(set->connectors == NULL))
10441                 return false;
10442
10443         for (i = 0; i < set->num_connectors; i++)
10444                 if (set->connectors[i]->encoder &&
10445                     set->connectors[i]->encoder->crtc == set->crtc &&
10446                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10447                         return true;
10448
10449         return false;
10450 }
10451
10452 static void
10453 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10454                                       struct intel_set_config *config)
10455 {
10456
10457         /* We should be able to check here if the fb has the same properties
10458          * and then just flip_or_move it */
10459         if (is_crtc_connector_off(set)) {
10460                 config->mode_changed = true;
10461         } else if (set->crtc->primary->fb != set->fb) {
10462                 /* If we have no fb then treat it as a full mode set */
10463                 if (set->crtc->primary->fb == NULL) {
10464                         struct intel_crtc *intel_crtc =
10465                                 to_intel_crtc(set->crtc);
10466
10467                         if (intel_crtc->active && i915.fastboot) {
10468                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10469                                 config->fb_changed = true;
10470                         } else {
10471                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10472                                 config->mode_changed = true;
10473                         }
10474                 } else if (set->fb == NULL) {
10475                         config->mode_changed = true;
10476                 } else if (set->fb->pixel_format !=
10477                            set->crtc->primary->fb->pixel_format) {
10478                         config->mode_changed = true;
10479                 } else {
10480                         config->fb_changed = true;
10481                 }
10482         }
10483
10484         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10485                 config->fb_changed = true;
10486
10487         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10488                 DRM_DEBUG_KMS("modes are different, full mode set\n");
10489                 drm_mode_debug_printmodeline(&set->crtc->mode);
10490                 drm_mode_debug_printmodeline(set->mode);
10491                 config->mode_changed = true;
10492         }
10493
10494         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10495                         set->crtc->base.id, config->mode_changed, config->fb_changed);
10496 }
10497
10498 static int
10499 intel_modeset_stage_output_state(struct drm_device *dev,
10500                                  struct drm_mode_set *set,
10501                                  struct intel_set_config *config)
10502 {
10503         struct intel_connector *connector;
10504         struct intel_encoder *encoder;
10505         struct intel_crtc *crtc;
10506         int ro;
10507
10508         /* The upper layers ensure that we either disable a crtc or have a list
10509          * of connectors. For paranoia, double-check this. */
10510         WARN_ON(!set->fb && (set->num_connectors != 0));
10511         WARN_ON(set->fb && (set->num_connectors == 0));
10512
10513         list_for_each_entry(connector, &dev->mode_config.connector_list,
10514                             base.head) {
10515                 /* Otherwise traverse passed in connector list and get encoders
10516                  * for them. */
10517                 for (ro = 0; ro < set->num_connectors; ro++) {
10518                         if (set->connectors[ro] == &connector->base) {
10519                                 connector->new_encoder = connector->encoder;
10520                                 break;
10521                         }
10522                 }
10523
10524                 /* If we disable the crtc, disable all its connectors. Also, if
10525                  * the connector is on the changing crtc but not on the new
10526                  * connector list, disable it. */
10527                 if ((!set->fb || ro == set->num_connectors) &&
10528                     connector->base.encoder &&
10529                     connector->base.encoder->crtc == set->crtc) {
10530                         connector->new_encoder = NULL;
10531
10532                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10533                                 connector->base.base.id,
10534                                 drm_get_connector_name(&connector->base));
10535                 }
10536
10537
10538                 if (&connector->new_encoder->base != connector->base.encoder) {
10539                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10540                         config->mode_changed = true;
10541                 }
10542         }
10543         /* connector->new_encoder is now updated for all connectors. */
10544
10545         /* Update crtc of enabled connectors. */
10546         list_for_each_entry(connector, &dev->mode_config.connector_list,
10547                             base.head) {
10548                 struct drm_crtc *new_crtc;
10549
10550                 if (!connector->new_encoder)
10551                         continue;
10552
10553                 new_crtc = connector->new_encoder->base.crtc;
10554
10555                 for (ro = 0; ro < set->num_connectors; ro++) {
10556                         if (set->connectors[ro] == &connector->base)
10557                                 new_crtc = set->crtc;
10558                 }
10559
10560                 /* Make sure the new CRTC will work with the encoder */
10561                 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10562                                          new_crtc)) {
10563                         return -EINVAL;
10564                 }
10565                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10566
10567                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10568                         connector->base.base.id,
10569                         drm_get_connector_name(&connector->base),
10570                         new_crtc->base.id);
10571         }
10572
10573         /* Check for any encoders that needs to be disabled. */
10574         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10575                             base.head) {
10576                 int num_connectors = 0;
10577                 list_for_each_entry(connector,
10578                                     &dev->mode_config.connector_list,
10579                                     base.head) {
10580                         if (connector->new_encoder == encoder) {
10581                                 WARN_ON(!connector->new_encoder->new_crtc);
10582                                 num_connectors++;
10583                         }
10584                 }
10585
10586                 if (num_connectors == 0)
10587                         encoder->new_crtc = NULL;
10588                 else if (num_connectors > 1)
10589                         return -EINVAL;
10590
10591                 /* Only now check for crtc changes so we don't miss encoders
10592                  * that will be disabled. */
10593                 if (&encoder->new_crtc->base != encoder->base.crtc) {
10594                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10595                         config->mode_changed = true;
10596                 }
10597         }
10598         /* Now we've also updated encoder->new_crtc for all encoders. */
10599
10600         for_each_intel_crtc(dev, crtc) {
10601                 crtc->new_enabled = false;
10602
10603                 list_for_each_entry(encoder,
10604                                     &dev->mode_config.encoder_list,
10605                                     base.head) {
10606                         if (encoder->new_crtc == crtc) {
10607                                 crtc->new_enabled = true;
10608                                 break;
10609                         }
10610                 }
10611
10612                 if (crtc->new_enabled != crtc->base.enabled) {
10613                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10614                                       crtc->new_enabled ? "en" : "dis");
10615                         config->mode_changed = true;
10616                 }
10617
10618                 if (crtc->new_enabled)
10619                         crtc->new_config = &crtc->config;
10620                 else
10621                         crtc->new_config = NULL;
10622         }
10623
10624         return 0;
10625 }
10626
10627 static void disable_crtc_nofb(struct intel_crtc *crtc)
10628 {
10629         struct drm_device *dev = crtc->base.dev;
10630         struct intel_encoder *encoder;
10631         struct intel_connector *connector;
10632
10633         DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10634                       pipe_name(crtc->pipe));
10635
10636         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10637                 if (connector->new_encoder &&
10638                     connector->new_encoder->new_crtc == crtc)
10639                         connector->new_encoder = NULL;
10640         }
10641
10642         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10643                 if (encoder->new_crtc == crtc)
10644                         encoder->new_crtc = NULL;
10645         }
10646
10647         crtc->new_enabled = false;
10648         crtc->new_config = NULL;
10649 }
10650
10651 static int intel_crtc_set_config(struct drm_mode_set *set)
10652 {
10653         struct drm_device *dev;
10654         struct drm_mode_set save_set;
10655         struct intel_set_config *config;
10656         int ret;
10657
10658         BUG_ON(!set);
10659         BUG_ON(!set->crtc);
10660         BUG_ON(!set->crtc->helper_private);
10661
10662         /* Enforce sane interface api - has been abused by the fb helper. */
10663         BUG_ON(!set->mode && set->fb);
10664         BUG_ON(set->fb && set->num_connectors == 0);
10665
10666         if (set->fb) {
10667                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10668                                 set->crtc->base.id, set->fb->base.id,
10669                                 (int)set->num_connectors, set->x, set->y);
10670         } else {
10671                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10672         }
10673
10674         dev = set->crtc->dev;
10675
10676         ret = -ENOMEM;
10677         config = kzalloc(sizeof(*config), GFP_KERNEL);
10678         if (!config)
10679                 goto out_config;
10680
10681         ret = intel_set_config_save_state(dev, config);
10682         if (ret)
10683                 goto out_config;
10684
10685         save_set.crtc = set->crtc;
10686         save_set.mode = &set->crtc->mode;
10687         save_set.x = set->crtc->x;
10688         save_set.y = set->crtc->y;
10689         save_set.fb = set->crtc->primary->fb;
10690
10691         /* Compute whether we need a full modeset, only an fb base update or no
10692          * change at all. In the future we might also check whether only the
10693          * mode changed, e.g. for LVDS where we only change the panel fitter in
10694          * such cases. */
10695         intel_set_config_compute_mode_changes(set, config);
10696
10697         ret = intel_modeset_stage_output_state(dev, set, config);
10698         if (ret)
10699                 goto fail;
10700
10701         if (config->mode_changed) {
10702                 ret = intel_set_mode(set->crtc, set->mode,
10703                                      set->x, set->y, set->fb);
10704         } else if (config->fb_changed) {
10705                 intel_crtc_wait_for_pending_flips(set->crtc);
10706
10707                 ret = intel_pipe_set_base(set->crtc,
10708                                           set->x, set->y, set->fb);
10709                 /*
10710                  * In the fastboot case this may be our only check of the
10711                  * state after boot.  It would be better to only do it on
10712                  * the first update, but we don't have a nice way of doing that
10713                  * (and really, set_config isn't used much for high freq page
10714                  * flipping, so increasing its cost here shouldn't be a big
10715                  * deal).
10716                  */
10717                 if (i915.fastboot && ret == 0)
10718                         intel_modeset_check_state(set->crtc->dev);
10719         }
10720
10721         if (ret) {
10722                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10723                               set->crtc->base.id, ret);
10724 fail:
10725                 intel_set_config_restore_state(dev, config);
10726
10727                 /*
10728                  * HACK: if the pipe was on, but we didn't have a framebuffer,
10729                  * force the pipe off to avoid oopsing in the modeset code
10730                  * due to fb==NULL. This should only happen during boot since
10731                  * we don't yet reconstruct the FB from the hardware state.
10732                  */
10733                 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10734                         disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10735
10736                 /* Try to restore the config */
10737                 if (config->mode_changed &&
10738                     intel_set_mode(save_set.crtc, save_set.mode,
10739                                    save_set.x, save_set.y, save_set.fb))
10740                         DRM_ERROR("failed to restore config after modeset failure\n");
10741         }
10742
10743 out_config:
10744         intel_set_config_free(config);
10745         return ret;
10746 }
10747
10748 static const struct drm_crtc_funcs intel_crtc_funcs = {
10749         .cursor_set = intel_crtc_cursor_set,
10750         .cursor_move = intel_crtc_cursor_move,
10751         .gamma_set = intel_crtc_gamma_set,
10752         .set_config = intel_crtc_set_config,
10753         .destroy = intel_crtc_destroy,
10754         .page_flip = intel_crtc_page_flip,
10755 };
10756
10757 static void intel_cpu_pll_init(struct drm_device *dev)
10758 {
10759         if (HAS_DDI(dev))
10760                 intel_ddi_pll_init(dev);
10761 }
10762
10763 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10764                                       struct intel_shared_dpll *pll,
10765                                       struct intel_dpll_hw_state *hw_state)
10766 {
10767         uint32_t val;
10768
10769         val = I915_READ(PCH_DPLL(pll->id));
10770         hw_state->dpll = val;
10771         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10772         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10773
10774         return val & DPLL_VCO_ENABLE;
10775 }
10776
10777 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10778                                   struct intel_shared_dpll *pll)
10779 {
10780         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10781         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10782 }
10783
10784 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10785                                 struct intel_shared_dpll *pll)
10786 {
10787         /* PCH refclock must be enabled first */
10788         ibx_assert_pch_refclk_enabled(dev_priv);
10789
10790         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10791
10792         /* Wait for the clocks to stabilize. */
10793         POSTING_READ(PCH_DPLL(pll->id));
10794         udelay(150);
10795
10796         /* The pixel multiplier can only be updated once the
10797          * DPLL is enabled and the clocks are stable.
10798          *
10799          * So write it again.
10800          */
10801         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10802         POSTING_READ(PCH_DPLL(pll->id));
10803         udelay(200);
10804 }
10805
10806 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10807                                  struct intel_shared_dpll *pll)
10808 {
10809         struct drm_device *dev = dev_priv->dev;
10810         struct intel_crtc *crtc;
10811
10812         /* Make sure no transcoder isn't still depending on us. */
10813         for_each_intel_crtc(dev, crtc) {
10814                 if (intel_crtc_to_shared_dpll(crtc) == pll)
10815                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10816         }
10817
10818         I915_WRITE(PCH_DPLL(pll->id), 0);
10819         POSTING_READ(PCH_DPLL(pll->id));
10820         udelay(200);
10821 }
10822
10823 static char *ibx_pch_dpll_names[] = {
10824         "PCH DPLL A",
10825         "PCH DPLL B",
10826 };
10827
10828 static void ibx_pch_dpll_init(struct drm_device *dev)
10829 {
10830         struct drm_i915_private *dev_priv = dev->dev_private;
10831         int i;
10832
10833         dev_priv->num_shared_dpll = 2;
10834
10835         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10836                 dev_priv->shared_dplls[i].id = i;
10837                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10838                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10839                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10840                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10841                 dev_priv->shared_dplls[i].get_hw_state =
10842                         ibx_pch_dpll_get_hw_state;
10843         }
10844 }
10845
10846 static void intel_shared_dpll_init(struct drm_device *dev)
10847 {
10848         struct drm_i915_private *dev_priv = dev->dev_private;
10849
10850         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10851                 ibx_pch_dpll_init(dev);
10852         else
10853                 dev_priv->num_shared_dpll = 0;
10854
10855         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10856 }
10857
10858 static void intel_crtc_init(struct drm_device *dev, int pipe)
10859 {
10860         struct drm_i915_private *dev_priv = dev->dev_private;
10861         struct intel_crtc *intel_crtc;
10862         int i;
10863
10864         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10865         if (intel_crtc == NULL)
10866                 return;
10867
10868         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10869
10870         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10871         for (i = 0; i < 256; i++) {
10872                 intel_crtc->lut_r[i] = i;
10873                 intel_crtc->lut_g[i] = i;
10874                 intel_crtc->lut_b[i] = i;
10875         }
10876
10877         /*
10878          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10879          * is hooked to plane B. Hence we want plane A feeding pipe B.
10880          */
10881         intel_crtc->pipe = pipe;
10882         intel_crtc->plane = pipe;
10883         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10884                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10885                 intel_crtc->plane = !pipe;
10886         }
10887
10888         init_waitqueue_head(&intel_crtc->vbl_wait);
10889
10890         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10891                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10892         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10893         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10894
10895         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10896 }
10897
10898 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10899 {
10900         struct drm_encoder *encoder = connector->base.encoder;
10901
10902         WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10903
10904         if (!encoder)
10905                 return INVALID_PIPE;
10906
10907         return to_intel_crtc(encoder->crtc)->pipe;
10908 }
10909
10910 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10911                                 struct drm_file *file)
10912 {
10913         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10914         struct drm_mode_object *drmmode_obj;
10915         struct intel_crtc *crtc;
10916
10917         if (!drm_core_check_feature(dev, DRIVER_MODESET))
10918                 return -ENODEV;
10919
10920         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10921                         DRM_MODE_OBJECT_CRTC);
10922
10923         if (!drmmode_obj) {
10924                 DRM_ERROR("no such CRTC id\n");
10925                 return -ENOENT;
10926         }
10927
10928         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10929         pipe_from_crtc_id->pipe = crtc->pipe;
10930
10931         return 0;
10932 }
10933
10934 static int intel_encoder_clones(struct intel_encoder *encoder)
10935 {
10936         struct drm_device *dev = encoder->base.dev;
10937         struct intel_encoder *source_encoder;
10938         int index_mask = 0;
10939         int entry = 0;
10940
10941         list_for_each_entry(source_encoder,
10942                             &dev->mode_config.encoder_list, base.head) {
10943                 if (encoders_cloneable(encoder, source_encoder))
10944                         index_mask |= (1 << entry);
10945
10946                 entry++;
10947         }
10948
10949         return index_mask;
10950 }
10951
10952 static bool has_edp_a(struct drm_device *dev)
10953 {
10954         struct drm_i915_private *dev_priv = dev->dev_private;
10955
10956         if (!IS_MOBILE(dev))
10957                 return false;
10958
10959         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10960                 return false;
10961
10962         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10963                 return false;
10964
10965         return true;
10966 }
10967
10968 const char *intel_output_name(int output)
10969 {
10970         static const char *names[] = {
10971                 [INTEL_OUTPUT_UNUSED] = "Unused",
10972                 [INTEL_OUTPUT_ANALOG] = "Analog",
10973                 [INTEL_OUTPUT_DVO] = "DVO",
10974                 [INTEL_OUTPUT_SDVO] = "SDVO",
10975                 [INTEL_OUTPUT_LVDS] = "LVDS",
10976                 [INTEL_OUTPUT_TVOUT] = "TV",
10977                 [INTEL_OUTPUT_HDMI] = "HDMI",
10978                 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10979                 [INTEL_OUTPUT_EDP] = "eDP",
10980                 [INTEL_OUTPUT_DSI] = "DSI",
10981                 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10982         };
10983
10984         if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10985                 return "Invalid";
10986
10987         return names[output];
10988 }
10989
10990 static void intel_setup_outputs(struct drm_device *dev)
10991 {
10992         struct drm_i915_private *dev_priv = dev->dev_private;
10993         struct intel_encoder *encoder;
10994         bool dpd_is_edp = false;
10995
10996         intel_lvds_init(dev);
10997
10998         if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
10999                 intel_crt_init(dev);
11000
11001         if (HAS_DDI(dev)) {
11002                 int found;
11003
11004                 /* Haswell uses DDI functions to detect digital outputs */
11005                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11006                 /* DDI A only supports eDP */
11007                 if (found)
11008                         intel_ddi_init(dev, PORT_A);
11009
11010                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11011                  * register */
11012                 found = I915_READ(SFUSE_STRAP);
11013
11014                 if (found & SFUSE_STRAP_DDIB_DETECTED)
11015                         intel_ddi_init(dev, PORT_B);
11016                 if (found & SFUSE_STRAP_DDIC_DETECTED)
11017                         intel_ddi_init(dev, PORT_C);
11018                 if (found & SFUSE_STRAP_DDID_DETECTED)
11019                         intel_ddi_init(dev, PORT_D);
11020         } else if (HAS_PCH_SPLIT(dev)) {
11021                 int found;
11022                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11023
11024                 if (has_edp_a(dev))
11025                         intel_dp_init(dev, DP_A, PORT_A);
11026
11027                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11028                         /* PCH SDVOB multiplex with HDMIB */
11029                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
11030                         if (!found)
11031                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11032                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11033                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
11034                 }
11035
11036                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11037                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11038
11039                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11040                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11041
11042                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11043                         intel_dp_init(dev, PCH_DP_C, PORT_C);
11044
11045                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11046                         intel_dp_init(dev, PCH_DP_D, PORT_D);
11047         } else if (IS_VALLEYVIEW(dev)) {
11048                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11049                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11050                                         PORT_B);
11051                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11052                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11053                 }
11054
11055                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11056                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11057                                         PORT_C);
11058                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11059                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11060                 }
11061
11062                 if (IS_CHERRYVIEW(dev)) {
11063                         if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11064                                 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11065                                                 PORT_D);
11066                                 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11067                                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11068                         }
11069                 }
11070
11071                 intel_dsi_init(dev);
11072         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11073                 bool found = false;
11074
11075                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11076                         DRM_DEBUG_KMS("probing SDVOB\n");
11077                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11078                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11079                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11080                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11081                         }
11082
11083                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
11084                                 intel_dp_init(dev, DP_B, PORT_B);
11085                 }
11086
11087                 /* Before G4X SDVOC doesn't have its own detect register */
11088
11089                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11090                         DRM_DEBUG_KMS("probing SDVOC\n");
11091                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11092                 }
11093
11094                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11095
11096                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11097                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11098                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11099                         }
11100                         if (SUPPORTS_INTEGRATED_DP(dev))
11101                                 intel_dp_init(dev, DP_C, PORT_C);
11102                 }
11103
11104                 if (SUPPORTS_INTEGRATED_DP(dev) &&
11105                     (I915_READ(DP_D) & DP_DETECTED))
11106                         intel_dp_init(dev, DP_D, PORT_D);
11107         } else if (IS_GEN2(dev))
11108                 intel_dvo_init(dev);
11109
11110         if (SUPPORTS_TV(dev))
11111                 intel_tv_init(dev);
11112
11113         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11114                 encoder->base.possible_crtcs = encoder->crtc_mask;
11115                 encoder->base.possible_clones =
11116                         intel_encoder_clones(encoder);
11117         }
11118
11119         intel_init_pch_refclk(dev);
11120
11121         drm_helper_move_panel_connectors_to_head(dev);
11122 }
11123
11124 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11125 {
11126         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11127
11128         drm_framebuffer_cleanup(fb);
11129         WARN_ON(!intel_fb->obj->framebuffer_references--);
11130         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11131         kfree(intel_fb);
11132 }
11133
11134 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11135                                                 struct drm_file *file,
11136                                                 unsigned int *handle)
11137 {
11138         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11139         struct drm_i915_gem_object *obj = intel_fb->obj;
11140
11141         return drm_gem_handle_create(file, &obj->base, handle);
11142 }
11143
11144 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11145         .destroy = intel_user_framebuffer_destroy,
11146         .create_handle = intel_user_framebuffer_create_handle,
11147 };
11148
11149 static int intel_framebuffer_init(struct drm_device *dev,
11150                                   struct intel_framebuffer *intel_fb,
11151                                   struct drm_mode_fb_cmd2 *mode_cmd,
11152                                   struct drm_i915_gem_object *obj)
11153 {
11154         int aligned_height;
11155         int pitch_limit;
11156         int ret;
11157
11158         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11159
11160         if (obj->tiling_mode == I915_TILING_Y) {
11161                 DRM_DEBUG("hardware does not support tiling Y\n");
11162                 return -EINVAL;
11163         }
11164
11165         if (mode_cmd->pitches[0] & 63) {
11166                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11167                           mode_cmd->pitches[0]);
11168                 return -EINVAL;
11169         }
11170
11171         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11172                 pitch_limit = 32*1024;
11173         } else if (INTEL_INFO(dev)->gen >= 4) {
11174                 if (obj->tiling_mode)
11175                         pitch_limit = 16*1024;
11176                 else
11177                         pitch_limit = 32*1024;
11178         } else if (INTEL_INFO(dev)->gen >= 3) {
11179                 if (obj->tiling_mode)
11180                         pitch_limit = 8*1024;
11181                 else
11182                         pitch_limit = 16*1024;
11183         } else
11184                 /* XXX DSPC is limited to 4k tiled */
11185                 pitch_limit = 8*1024;
11186
11187         if (mode_cmd->pitches[0] > pitch_limit) {
11188                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11189                           obj->tiling_mode ? "tiled" : "linear",
11190                           mode_cmd->pitches[0], pitch_limit);
11191                 return -EINVAL;
11192         }
11193
11194         if (obj->tiling_mode != I915_TILING_NONE &&
11195             mode_cmd->pitches[0] != obj->stride) {
11196                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11197                           mode_cmd->pitches[0], obj->stride);
11198                 return -EINVAL;
11199         }
11200
11201         /* Reject formats not supported by any plane early. */
11202         switch (mode_cmd->pixel_format) {
11203         case DRM_FORMAT_C8:
11204         case DRM_FORMAT_RGB565:
11205         case DRM_FORMAT_XRGB8888:
11206         case DRM_FORMAT_ARGB8888:
11207                 break;
11208         case DRM_FORMAT_XRGB1555:
11209         case DRM_FORMAT_ARGB1555:
11210                 if (INTEL_INFO(dev)->gen > 3) {
11211                         DRM_DEBUG("unsupported pixel format: %s\n",
11212                                   drm_get_format_name(mode_cmd->pixel_format));
11213                         return -EINVAL;
11214                 }
11215                 break;
11216         case DRM_FORMAT_XBGR8888:
11217         case DRM_FORMAT_ABGR8888:
11218         case DRM_FORMAT_XRGB2101010:
11219         case DRM_FORMAT_ARGB2101010:
11220         case DRM_FORMAT_XBGR2101010:
11221         case DRM_FORMAT_ABGR2101010:
11222                 if (INTEL_INFO(dev)->gen < 4) {
11223                         DRM_DEBUG("unsupported pixel format: %s\n",
11224                                   drm_get_format_name(mode_cmd->pixel_format));
11225                         return -EINVAL;
11226                 }
11227                 break;
11228         case DRM_FORMAT_YUYV:
11229         case DRM_FORMAT_UYVY:
11230         case DRM_FORMAT_YVYU:
11231         case DRM_FORMAT_VYUY:
11232                 if (INTEL_INFO(dev)->gen < 5) {
11233                         DRM_DEBUG("unsupported pixel format: %s\n",
11234                                   drm_get_format_name(mode_cmd->pixel_format));
11235                         return -EINVAL;
11236                 }
11237                 break;
11238         default:
11239                 DRM_DEBUG("unsupported pixel format: %s\n",
11240                           drm_get_format_name(mode_cmd->pixel_format));
11241                 return -EINVAL;
11242         }
11243
11244         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11245         if (mode_cmd->offsets[0] != 0)
11246                 return -EINVAL;
11247
11248         aligned_height = intel_align_height(dev, mode_cmd->height,
11249                                             obj->tiling_mode);
11250         /* FIXME drm helper for size checks (especially planar formats)? */
11251         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11252                 return -EINVAL;
11253
11254         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11255         intel_fb->obj = obj;
11256         intel_fb->obj->framebuffer_references++;
11257
11258         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11259         if (ret) {
11260                 DRM_ERROR("framebuffer init failed %d\n", ret);
11261                 return ret;
11262         }
11263
11264         return 0;
11265 }
11266
11267 static struct drm_framebuffer *
11268 intel_user_framebuffer_create(struct drm_device *dev,
11269                               struct drm_file *filp,
11270                               struct drm_mode_fb_cmd2 *mode_cmd)
11271 {
11272         struct drm_i915_gem_object *obj;
11273
11274         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11275                                                 mode_cmd->handles[0]));
11276         if (&obj->base == NULL)
11277                 return ERR_PTR(-ENOENT);
11278
11279         return intel_framebuffer_create(dev, mode_cmd, obj);
11280 }
11281
11282 #ifndef CONFIG_DRM_I915_FBDEV
11283 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11284 {
11285 }
11286 #endif
11287
11288 static const struct drm_mode_config_funcs intel_mode_funcs = {
11289         .fb_create = intel_user_framebuffer_create,
11290         .output_poll_changed = intel_fbdev_output_poll_changed,
11291 };
11292
11293 /* Set up chip specific display functions */
11294 static void intel_init_display(struct drm_device *dev)
11295 {
11296         struct drm_i915_private *dev_priv = dev->dev_private;
11297
11298         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11299                 dev_priv->display.find_dpll = g4x_find_best_dpll;
11300         else if (IS_CHERRYVIEW(dev))
11301                 dev_priv->display.find_dpll = chv_find_best_dpll;
11302         else if (IS_VALLEYVIEW(dev))
11303                 dev_priv->display.find_dpll = vlv_find_best_dpll;
11304         else if (IS_PINEVIEW(dev))
11305                 dev_priv->display.find_dpll = pnv_find_best_dpll;
11306         else
11307                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11308
11309         if (HAS_DDI(dev)) {
11310                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11311                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11312                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11313                 dev_priv->display.crtc_enable = haswell_crtc_enable;
11314                 dev_priv->display.crtc_disable = haswell_crtc_disable;
11315                 dev_priv->display.off = haswell_crtc_off;
11316                 dev_priv->display.update_primary_plane =
11317                         ironlake_update_primary_plane;
11318         } else if (HAS_PCH_SPLIT(dev)) {
11319                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11320                 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11321                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11322                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11323                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11324                 dev_priv->display.off = ironlake_crtc_off;
11325                 dev_priv->display.update_primary_plane =
11326                         ironlake_update_primary_plane;
11327         } else if (IS_VALLEYVIEW(dev)) {
11328                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11329                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11330                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11331                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11332                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11333                 dev_priv->display.off = i9xx_crtc_off;
11334                 dev_priv->display.update_primary_plane =
11335                         i9xx_update_primary_plane;
11336         } else {
11337                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11338                 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11339                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11340                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11341                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11342                 dev_priv->display.off = i9xx_crtc_off;
11343                 dev_priv->display.update_primary_plane =
11344                         i9xx_update_primary_plane;
11345         }
11346
11347         /* Returns the core display clock speed */
11348         if (IS_VALLEYVIEW(dev))
11349                 dev_priv->display.get_display_clock_speed =
11350                         valleyview_get_display_clock_speed;
11351         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11352                 dev_priv->display.get_display_clock_speed =
11353                         i945_get_display_clock_speed;
11354         else if (IS_I915G(dev))
11355                 dev_priv->display.get_display_clock_speed =
11356                         i915_get_display_clock_speed;
11357         else if (IS_I945GM(dev) || IS_845G(dev))
11358                 dev_priv->display.get_display_clock_speed =
11359                         i9xx_misc_get_display_clock_speed;
11360         else if (IS_PINEVIEW(dev))
11361                 dev_priv->display.get_display_clock_speed =
11362                         pnv_get_display_clock_speed;
11363         else if (IS_I915GM(dev))
11364                 dev_priv->display.get_display_clock_speed =
11365                         i915gm_get_display_clock_speed;
11366         else if (IS_I865G(dev))
11367                 dev_priv->display.get_display_clock_speed =
11368                         i865_get_display_clock_speed;
11369         else if (IS_I85X(dev))
11370                 dev_priv->display.get_display_clock_speed =
11371                         i855_get_display_clock_speed;
11372         else /* 852, 830 */
11373                 dev_priv->display.get_display_clock_speed =
11374                         i830_get_display_clock_speed;
11375
11376         if (HAS_PCH_SPLIT(dev)) {
11377                 if (IS_GEN5(dev)) {
11378                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11379                         dev_priv->display.write_eld = ironlake_write_eld;
11380                 } else if (IS_GEN6(dev)) {
11381                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11382                         dev_priv->display.write_eld = ironlake_write_eld;
11383                         dev_priv->display.modeset_global_resources =
11384                                 snb_modeset_global_resources;
11385                 } else if (IS_IVYBRIDGE(dev)) {
11386                         /* FIXME: detect B0+ stepping and use auto training */
11387                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11388                         dev_priv->display.write_eld = ironlake_write_eld;
11389                         dev_priv->display.modeset_global_resources =
11390                                 ivb_modeset_global_resources;
11391                 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11392                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11393                         dev_priv->display.write_eld = haswell_write_eld;
11394                         dev_priv->display.modeset_global_resources =
11395                                 haswell_modeset_global_resources;
11396                 }
11397         } else if (IS_G4X(dev)) {
11398                 dev_priv->display.write_eld = g4x_write_eld;
11399         } else if (IS_VALLEYVIEW(dev)) {
11400                 dev_priv->display.modeset_global_resources =
11401                         valleyview_modeset_global_resources;
11402                 dev_priv->display.write_eld = ironlake_write_eld;
11403         }
11404
11405         /* Default just returns -ENODEV to indicate unsupported */
11406         dev_priv->display.queue_flip = intel_default_queue_flip;
11407
11408         switch (INTEL_INFO(dev)->gen) {
11409         case 2:
11410                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11411                 break;
11412
11413         case 3:
11414                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11415                 break;
11416
11417         case 4:
11418         case 5:
11419                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11420                 break;
11421
11422         case 6:
11423                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11424                 break;
11425         case 7:
11426         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11427                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11428                 break;
11429         }
11430
11431         intel_panel_init_backlight_funcs(dev);
11432 }
11433
11434 /*
11435  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11436  * resume, or other times.  This quirk makes sure that's the case for
11437  * affected systems.
11438  */
11439 static void quirk_pipea_force(struct drm_device *dev)
11440 {
11441         struct drm_i915_private *dev_priv = dev->dev_private;
11442
11443         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11444         DRM_INFO("applying pipe a force quirk\n");
11445 }
11446
11447 /*
11448  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11449  */
11450 static void quirk_ssc_force_disable(struct drm_device *dev)
11451 {
11452         struct drm_i915_private *dev_priv = dev->dev_private;
11453         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11454         DRM_INFO("applying lvds SSC disable quirk\n");
11455 }
11456
11457 /*
11458  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11459  * brightness value
11460  */
11461 static void quirk_invert_brightness(struct drm_device *dev)
11462 {
11463         struct drm_i915_private *dev_priv = dev->dev_private;
11464         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11465         DRM_INFO("applying inverted panel brightness quirk\n");
11466 }
11467
11468 struct intel_quirk {
11469         int device;
11470         int subsystem_vendor;
11471         int subsystem_device;
11472         void (*hook)(struct drm_device *dev);
11473 };
11474
11475 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11476 struct intel_dmi_quirk {
11477         void (*hook)(struct drm_device *dev);
11478         const struct dmi_system_id (*dmi_id_list)[];
11479 };
11480
11481 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11482 {
11483         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11484         return 1;
11485 }
11486
11487 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11488         {
11489                 .dmi_id_list = &(const struct dmi_system_id[]) {
11490                         {
11491                                 .callback = intel_dmi_reverse_brightness,
11492                                 .ident = "NCR Corporation",
11493                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11494                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
11495                                 },
11496                         },
11497                         { }  /* terminating entry */
11498                 },
11499                 .hook = quirk_invert_brightness,
11500         },
11501 };
11502
11503 static struct intel_quirk intel_quirks[] = {
11504         /* HP Mini needs pipe A force quirk (LP: #322104) */
11505         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11506
11507         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11508         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11509
11510         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11511         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11512
11513         /* 830 needs to leave pipe A & dpll A up */
11514         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11515
11516         /* Lenovo U160 cannot use SSC on LVDS */
11517         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11518
11519         /* Sony Vaio Y cannot use SSC on LVDS */
11520         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11521
11522         /* Acer Aspire 5734Z must invert backlight brightness */
11523         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11524
11525         /* Acer/eMachines G725 */
11526         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11527
11528         /* Acer/eMachines e725 */
11529         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11530
11531         /* Acer/Packard Bell NCL20 */
11532         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11533
11534         /* Acer Aspire 4736Z */
11535         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11536
11537         /* Acer Aspire 5336 */
11538         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11539 };
11540
11541 static void intel_init_quirks(struct drm_device *dev)
11542 {
11543         struct pci_dev *d = dev->pdev;
11544         int i;
11545
11546         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11547                 struct intel_quirk *q = &intel_quirks[i];
11548
11549                 if (d->device == q->device &&
11550                     (d->subsystem_vendor == q->subsystem_vendor ||
11551                      q->subsystem_vendor == PCI_ANY_ID) &&
11552                     (d->subsystem_device == q->subsystem_device ||
11553                      q->subsystem_device == PCI_ANY_ID))
11554                         q->hook(dev);
11555         }
11556         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11557                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11558                         intel_dmi_quirks[i].hook(dev);
11559         }
11560 }
11561
11562 /* Disable the VGA plane that we never use */
11563 static void i915_disable_vga(struct drm_device *dev)
11564 {
11565         struct drm_i915_private *dev_priv = dev->dev_private;
11566         u8 sr1;
11567         u32 vga_reg = i915_vgacntrl_reg(dev);
11568
11569         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11570         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11571         outb(SR01, VGA_SR_INDEX);
11572         sr1 = inb(VGA_SR_DATA);
11573         outb(sr1 | 1<<5, VGA_SR_DATA);
11574         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11575         udelay(300);
11576
11577         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11578         POSTING_READ(vga_reg);
11579 }
11580
11581 void intel_modeset_init_hw(struct drm_device *dev)
11582 {
11583         intel_prepare_ddi(dev);
11584
11585         intel_init_clock_gating(dev);
11586
11587         intel_reset_dpio(dev);
11588
11589         intel_enable_gt_powersave(dev);
11590 }
11591
11592 void intel_modeset_suspend_hw(struct drm_device *dev)
11593 {
11594         intel_suspend_hw(dev);
11595 }
11596
11597 void intel_modeset_init(struct drm_device *dev)
11598 {
11599         struct drm_i915_private *dev_priv = dev->dev_private;
11600         int sprite, ret;
11601         enum pipe pipe;
11602         struct intel_crtc *crtc;
11603
11604         drm_mode_config_init(dev);
11605
11606         dev->mode_config.min_width = 0;
11607         dev->mode_config.min_height = 0;
11608
11609         dev->mode_config.preferred_depth = 24;
11610         dev->mode_config.prefer_shadow = 1;
11611
11612         dev->mode_config.funcs = &intel_mode_funcs;
11613
11614         intel_init_quirks(dev);
11615
11616         intel_init_pm(dev);
11617
11618         if (INTEL_INFO(dev)->num_pipes == 0)
11619                 return;
11620
11621         intel_init_display(dev);
11622
11623         if (IS_GEN2(dev)) {
11624                 dev->mode_config.max_width = 2048;
11625                 dev->mode_config.max_height = 2048;
11626         } else if (IS_GEN3(dev)) {
11627                 dev->mode_config.max_width = 4096;
11628                 dev->mode_config.max_height = 4096;
11629         } else {
11630                 dev->mode_config.max_width = 8192;
11631                 dev->mode_config.max_height = 8192;
11632         }
11633
11634         if (IS_GEN2(dev)) {
11635                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11636                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11637         } else {
11638                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11639                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11640         }
11641
11642         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11643
11644         DRM_DEBUG_KMS("%d display pipe%s available.\n",
11645                       INTEL_INFO(dev)->num_pipes,
11646                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11647
11648         for_each_pipe(pipe) {
11649                 intel_crtc_init(dev, pipe);
11650                 for_each_sprite(pipe, sprite) {
11651                         ret = intel_plane_init(dev, pipe, sprite);
11652                         if (ret)
11653                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11654                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
11655                 }
11656         }
11657
11658         intel_init_dpio(dev);
11659         intel_reset_dpio(dev);
11660
11661         intel_cpu_pll_init(dev);
11662         intel_shared_dpll_init(dev);
11663
11664         /* Just disable it once at startup */
11665         i915_disable_vga(dev);
11666         intel_setup_outputs(dev);
11667
11668         /* Just in case the BIOS is doing something questionable. */
11669         intel_disable_fbc(dev);
11670
11671         mutex_lock(&dev->mode_config.mutex);
11672         intel_modeset_setup_hw_state(dev, false);
11673         mutex_unlock(&dev->mode_config.mutex);
11674
11675         for_each_intel_crtc(dev, crtc) {
11676                 if (!crtc->active)
11677                         continue;
11678
11679                 /*
11680                  * Note that reserving the BIOS fb up front prevents us
11681                  * from stuffing other stolen allocations like the ring
11682                  * on top.  This prevents some ugliness at boot time, and
11683                  * can even allow for smooth boot transitions if the BIOS
11684                  * fb is large enough for the active pipe configuration.
11685                  */
11686                 if (dev_priv->display.get_plane_config) {
11687                         dev_priv->display.get_plane_config(crtc,
11688                                                            &crtc->plane_config);
11689                         /*
11690                          * If the fb is shared between multiple heads, we'll
11691                          * just get the first one.
11692                          */
11693                         intel_find_plane_obj(crtc, &crtc->plane_config);
11694                 }
11695         }
11696 }
11697
11698 static void
11699 intel_connector_break_all_links(struct intel_connector *connector)
11700 {
11701         connector->base.dpms = DRM_MODE_DPMS_OFF;
11702         connector->base.encoder = NULL;
11703         connector->encoder->connectors_active = false;
11704         connector->encoder->base.crtc = NULL;
11705 }
11706
11707 static void intel_enable_pipe_a(struct drm_device *dev)
11708 {
11709         struct intel_connector *connector;
11710         struct drm_connector *crt = NULL;
11711         struct intel_load_detect_pipe load_detect_temp;
11712
11713         /* We can't just switch on the pipe A, we need to set things up with a
11714          * proper mode and output configuration. As a gross hack, enable pipe A
11715          * by enabling the load detect pipe once. */
11716         list_for_each_entry(connector,
11717                             &dev->mode_config.connector_list,
11718                             base.head) {
11719                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11720                         crt = &connector->base;
11721                         break;
11722                 }
11723         }
11724
11725         if (!crt)
11726                 return;
11727
11728         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11729                 intel_release_load_detect_pipe(crt, &load_detect_temp);
11730
11731
11732 }
11733
11734 static bool
11735 intel_check_plane_mapping(struct intel_crtc *crtc)
11736 {
11737         struct drm_device *dev = crtc->base.dev;
11738         struct drm_i915_private *dev_priv = dev->dev_private;
11739         u32 reg, val;
11740
11741         if (INTEL_INFO(dev)->num_pipes == 1)
11742                 return true;
11743
11744         reg = DSPCNTR(!crtc->plane);
11745         val = I915_READ(reg);
11746
11747         if ((val & DISPLAY_PLANE_ENABLE) &&
11748             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11749                 return false;
11750
11751         return true;
11752 }
11753
11754 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11755 {
11756         struct drm_device *dev = crtc->base.dev;
11757         struct drm_i915_private *dev_priv = dev->dev_private;
11758         u32 reg;
11759
11760         /* Clear any frame start delays used for debugging left by the BIOS */
11761         reg = PIPECONF(crtc->config.cpu_transcoder);
11762         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11763
11764         /* We need to sanitize the plane -> pipe mapping first because this will
11765          * disable the crtc (and hence change the state) if it is wrong. Note
11766          * that gen4+ has a fixed plane -> pipe mapping.  */
11767         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11768                 struct intel_connector *connector;
11769                 bool plane;
11770
11771                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11772                               crtc->base.base.id);
11773
11774                 /* Pipe has the wrong plane attached and the plane is active.
11775                  * Temporarily change the plane mapping and disable everything
11776                  * ...  */
11777                 plane = crtc->plane;
11778                 crtc->plane = !plane;
11779                 dev_priv->display.crtc_disable(&crtc->base);
11780                 crtc->plane = plane;
11781
11782                 /* ... and break all links. */
11783                 list_for_each_entry(connector, &dev->mode_config.connector_list,
11784                                     base.head) {
11785                         if (connector->encoder->base.crtc != &crtc->base)
11786                                 continue;
11787
11788                         intel_connector_break_all_links(connector);
11789                 }
11790
11791                 WARN_ON(crtc->active);
11792                 crtc->base.enabled = false;
11793         }
11794
11795         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11796             crtc->pipe == PIPE_A && !crtc->active) {
11797                 /* BIOS forgot to enable pipe A, this mostly happens after
11798                  * resume. Force-enable the pipe to fix this, the update_dpms
11799                  * call below we restore the pipe to the right state, but leave
11800                  * the required bits on. */
11801                 intel_enable_pipe_a(dev);
11802         }
11803
11804         /* Adjust the state of the output pipe according to whether we
11805          * have active connectors/encoders. */
11806         intel_crtc_update_dpms(&crtc->base);
11807
11808         if (crtc->active != crtc->base.enabled) {
11809                 struct intel_encoder *encoder;
11810
11811                 /* This can happen either due to bugs in the get_hw_state
11812                  * functions or because the pipe is force-enabled due to the
11813                  * pipe A quirk. */
11814                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11815                               crtc->base.base.id,
11816                               crtc->base.enabled ? "enabled" : "disabled",
11817                               crtc->active ? "enabled" : "disabled");
11818
11819                 crtc->base.enabled = crtc->active;
11820
11821                 /* Because we only establish the connector -> encoder ->
11822                  * crtc links if something is active, this means the
11823                  * crtc is now deactivated. Break the links. connector
11824                  * -> encoder links are only establish when things are
11825                  *  actually up, hence no need to break them. */
11826                 WARN_ON(crtc->active);
11827
11828                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11829                         WARN_ON(encoder->connectors_active);
11830                         encoder->base.crtc = NULL;
11831                 }
11832         }
11833         if (crtc->active) {
11834                 /*
11835                  * We start out with underrun reporting disabled to avoid races.
11836                  * For correct bookkeeping mark this on active crtcs.
11837                  *
11838                  * No protection against concurrent access is required - at
11839                  * worst a fifo underrun happens which also sets this to false.
11840                  */
11841                 crtc->cpu_fifo_underrun_disabled = true;
11842                 crtc->pch_fifo_underrun_disabled = true;
11843         }
11844 }
11845
11846 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11847 {
11848         struct intel_connector *connector;
11849         struct drm_device *dev = encoder->base.dev;
11850
11851         /* We need to check both for a crtc link (meaning that the
11852          * encoder is active and trying to read from a pipe) and the
11853          * pipe itself being active. */
11854         bool has_active_crtc = encoder->base.crtc &&
11855                 to_intel_crtc(encoder->base.crtc)->active;
11856
11857         if (encoder->connectors_active && !has_active_crtc) {
11858                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11859                               encoder->base.base.id,
11860                               drm_get_encoder_name(&encoder->base));
11861
11862                 /* Connector is active, but has no active pipe. This is
11863                  * fallout from our resume register restoring. Disable
11864                  * the encoder manually again. */
11865                 if (encoder->base.crtc) {
11866                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11867                                       encoder->base.base.id,
11868                                       drm_get_encoder_name(&encoder->base));
11869                         encoder->disable(encoder);
11870                 }
11871
11872                 /* Inconsistent output/port/pipe state happens presumably due to
11873                  * a bug in one of the get_hw_state functions. Or someplace else
11874                  * in our code, like the register restore mess on resume. Clamp
11875                  * things to off as a safer default. */
11876                 list_for_each_entry(connector,
11877                                     &dev->mode_config.connector_list,
11878                                     base.head) {
11879                         if (connector->encoder != encoder)
11880                                 continue;
11881
11882                         intel_connector_break_all_links(connector);
11883                 }
11884         }
11885         /* Enabled encoders without active connectors will be fixed in
11886          * the crtc fixup. */
11887 }
11888
11889 void i915_redisable_vga_power_on(struct drm_device *dev)
11890 {
11891         struct drm_i915_private *dev_priv = dev->dev_private;
11892         u32 vga_reg = i915_vgacntrl_reg(dev);
11893
11894         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11895                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11896                 i915_disable_vga(dev);
11897         }
11898 }
11899
11900 void i915_redisable_vga(struct drm_device *dev)
11901 {
11902         struct drm_i915_private *dev_priv = dev->dev_private;
11903
11904         /* This function can be called both from intel_modeset_setup_hw_state or
11905          * at a very early point in our resume sequence, where the power well
11906          * structures are not yet restored. Since this function is at a very
11907          * paranoid "someone might have enabled VGA while we were not looking"
11908          * level, just check if the power well is enabled instead of trying to
11909          * follow the "don't touch the power well if we don't need it" policy
11910          * the rest of the driver uses. */
11911         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11912                 return;
11913
11914         i915_redisable_vga_power_on(dev);
11915 }
11916
11917 static bool primary_get_hw_state(struct intel_crtc *crtc)
11918 {
11919         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11920
11921         if (!crtc->active)
11922                 return false;
11923
11924         return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11925 }
11926
11927 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11928 {
11929         struct drm_i915_private *dev_priv = dev->dev_private;
11930         enum pipe pipe;
11931         struct intel_crtc *crtc;
11932         struct intel_encoder *encoder;
11933         struct intel_connector *connector;
11934         int i;
11935
11936         for_each_intel_crtc(dev, crtc) {
11937                 memset(&crtc->config, 0, sizeof(crtc->config));
11938
11939                 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11940
11941                 crtc->active = dev_priv->display.get_pipe_config(crtc,
11942                                                                  &crtc->config);
11943
11944                 crtc->base.enabled = crtc->active;
11945                 crtc->primary_enabled = primary_get_hw_state(crtc);
11946
11947                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11948                               crtc->base.base.id,
11949                               crtc->active ? "enabled" : "disabled");
11950         }
11951
11952         /* FIXME: Smash this into the new shared dpll infrastructure. */
11953         if (HAS_DDI(dev))
11954                 intel_ddi_setup_hw_pll_state(dev);
11955
11956         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11957                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11958
11959                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11960                 pll->active = 0;
11961                 for_each_intel_crtc(dev, crtc) {
11962                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11963                                 pll->active++;
11964                 }
11965                 pll->refcount = pll->active;
11966
11967                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11968                               pll->name, pll->refcount, pll->on);
11969         }
11970
11971         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11972                             base.head) {
11973                 pipe = 0;
11974
11975                 if (encoder->get_hw_state(encoder, &pipe)) {
11976                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11977                         encoder->base.crtc = &crtc->base;
11978                         encoder->get_config(encoder, &crtc->config);
11979                 } else {
11980                         encoder->base.crtc = NULL;
11981                 }
11982
11983                 encoder->connectors_active = false;
11984                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11985                               encoder->base.base.id,
11986                               drm_get_encoder_name(&encoder->base),
11987                               encoder->base.crtc ? "enabled" : "disabled",
11988                               pipe_name(pipe));
11989         }
11990
11991         list_for_each_entry(connector, &dev->mode_config.connector_list,
11992                             base.head) {
11993                 if (connector->get_hw_state(connector)) {
11994                         connector->base.dpms = DRM_MODE_DPMS_ON;
11995                         connector->encoder->connectors_active = true;
11996                         connector->base.encoder = &connector->encoder->base;
11997                 } else {
11998                         connector->base.dpms = DRM_MODE_DPMS_OFF;
11999                         connector->base.encoder = NULL;
12000                 }
12001                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12002                               connector->base.base.id,
12003                               drm_get_connector_name(&connector->base),
12004                               connector->base.encoder ? "enabled" : "disabled");
12005         }
12006 }
12007
12008 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12009  * and i915 state tracking structures. */
12010 void intel_modeset_setup_hw_state(struct drm_device *dev,
12011                                   bool force_restore)
12012 {
12013         struct drm_i915_private *dev_priv = dev->dev_private;
12014         enum pipe pipe;
12015         struct intel_crtc *crtc;
12016         struct intel_encoder *encoder;
12017         int i;
12018
12019         intel_modeset_readout_hw_state(dev);
12020
12021         /*
12022          * Now that we have the config, copy it to each CRTC struct
12023          * Note that this could go away if we move to using crtc_config
12024          * checking everywhere.
12025          */
12026         for_each_intel_crtc(dev, crtc) {
12027                 if (crtc->active && i915.fastboot) {
12028                         intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12029                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12030                                       crtc->base.base.id);
12031                         drm_mode_debug_printmodeline(&crtc->base.mode);
12032                 }
12033         }
12034
12035         /* HW state is read out, now we need to sanitize this mess. */
12036         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12037                             base.head) {
12038                 intel_sanitize_encoder(encoder);
12039         }
12040
12041         for_each_pipe(pipe) {
12042                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12043                 intel_sanitize_crtc(crtc);
12044                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12045         }
12046
12047         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12048                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12049
12050                 if (!pll->on || pll->active)
12051                         continue;
12052
12053                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12054
12055                 pll->disable(dev_priv, pll);
12056                 pll->on = false;
12057         }
12058
12059         if (HAS_PCH_SPLIT(dev))
12060                 ilk_wm_get_hw_state(dev);
12061
12062         if (force_restore) {
12063                 i915_redisable_vga(dev);
12064
12065                 /*
12066                  * We need to use raw interfaces for restoring state to avoid
12067                  * checking (bogus) intermediate states.
12068                  */
12069                 for_each_pipe(pipe) {
12070                         struct drm_crtc *crtc =
12071                                 dev_priv->pipe_to_crtc_mapping[pipe];
12072
12073                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12074                                          crtc->primary->fb);
12075                 }
12076         } else {
12077                 intel_modeset_update_staged_output_state(dev);
12078         }
12079
12080         intel_modeset_check_state(dev);
12081 }
12082
12083 void intel_modeset_gem_init(struct drm_device *dev)
12084 {
12085         struct drm_crtc *c;
12086         struct intel_framebuffer *fb;
12087
12088         mutex_lock(&dev->struct_mutex);
12089         intel_init_gt_powersave(dev);
12090         mutex_unlock(&dev->struct_mutex);
12091
12092         intel_modeset_init_hw(dev);
12093
12094         intel_setup_overlay(dev);
12095
12096         /*
12097          * Make sure any fbs we allocated at startup are properly
12098          * pinned & fenced.  When we do the allocation it's too early
12099          * for this.
12100          */
12101         mutex_lock(&dev->struct_mutex);
12102         for_each_crtc(dev, c) {
12103                 if (!c->primary->fb)
12104                         continue;
12105
12106                 fb = to_intel_framebuffer(c->primary->fb);
12107                 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12108                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
12109                                   to_intel_crtc(c)->pipe);
12110                         drm_framebuffer_unreference(c->primary->fb);
12111                         c->primary->fb = NULL;
12112                 }
12113         }
12114         mutex_unlock(&dev->struct_mutex);
12115 }
12116
12117 void intel_connector_unregister(struct intel_connector *intel_connector)
12118 {
12119         struct drm_connector *connector = &intel_connector->base;
12120
12121         intel_panel_destroy_backlight(connector);
12122         drm_sysfs_connector_remove(connector);
12123 }
12124
12125 void intel_modeset_cleanup(struct drm_device *dev)
12126 {
12127         struct drm_i915_private *dev_priv = dev->dev_private;
12128         struct drm_crtc *crtc;
12129         struct drm_connector *connector;
12130
12131         /*
12132          * Interrupts and polling as the first thing to avoid creating havoc.
12133          * Too much stuff here (turning of rps, connectors, ...) would
12134          * experience fancy races otherwise.
12135          */
12136         drm_irq_uninstall(dev);
12137         cancel_work_sync(&dev_priv->hotplug_work);
12138         /*
12139          * Due to the hpd irq storm handling the hotplug work can re-arm the
12140          * poll handlers. Hence disable polling after hpd handling is shut down.
12141          */
12142         drm_kms_helper_poll_fini(dev);
12143
12144         mutex_lock(&dev->struct_mutex);
12145
12146         intel_unregister_dsm_handler();
12147
12148         for_each_crtc(dev, crtc) {
12149                 /* Skip inactive CRTCs */
12150                 if (!crtc->primary->fb)
12151                         continue;
12152
12153                 intel_increase_pllclock(crtc);
12154         }
12155
12156         intel_disable_fbc(dev);
12157
12158         intel_disable_gt_powersave(dev);
12159
12160         ironlake_teardown_rc6(dev);
12161
12162         mutex_unlock(&dev->struct_mutex);
12163
12164         /* flush any delayed tasks or pending work */
12165         flush_scheduled_work();
12166
12167         /* destroy the backlight and sysfs files before encoders/connectors */
12168         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12169                 struct intel_connector *intel_connector;
12170
12171                 intel_connector = to_intel_connector(connector);
12172                 intel_connector->unregister(intel_connector);
12173         }
12174
12175         drm_mode_config_cleanup(dev);
12176
12177         intel_cleanup_overlay(dev);
12178
12179         mutex_lock(&dev->struct_mutex);
12180         intel_cleanup_gt_powersave(dev);
12181         mutex_unlock(&dev->struct_mutex);
12182 }
12183
12184 /*
12185  * Return which encoder is currently attached for connector.
12186  */
12187 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12188 {
12189         return &intel_attached_encoder(connector)->base;
12190 }
12191
12192 void intel_connector_attach_encoder(struct intel_connector *connector,
12193                                     struct intel_encoder *encoder)
12194 {
12195         connector->encoder = encoder;
12196         drm_mode_connector_attach_encoder(&connector->base,
12197                                           &encoder->base);
12198 }
12199
12200 /*
12201  * set vga decode state - true == enable VGA decode
12202  */
12203 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12204 {
12205         struct drm_i915_private *dev_priv = dev->dev_private;
12206         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12207         u16 gmch_ctrl;
12208
12209         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12210                 DRM_ERROR("failed to read control word\n");
12211                 return -EIO;
12212         }
12213
12214         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12215                 return 0;
12216
12217         if (state)
12218                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12219         else
12220                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12221
12222         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12223                 DRM_ERROR("failed to write control word\n");
12224                 return -EIO;
12225         }
12226
12227         return 0;
12228 }
12229
12230 struct intel_display_error_state {
12231
12232         u32 power_well_driver;
12233
12234         int num_transcoders;
12235
12236         struct intel_cursor_error_state {
12237                 u32 control;
12238                 u32 position;
12239                 u32 base;
12240                 u32 size;
12241         } cursor[I915_MAX_PIPES];
12242
12243         struct intel_pipe_error_state {
12244                 bool power_domain_on;
12245                 u32 source;
12246                 u32 stat;
12247         } pipe[I915_MAX_PIPES];
12248
12249         struct intel_plane_error_state {
12250                 u32 control;
12251                 u32 stride;
12252                 u32 size;
12253                 u32 pos;
12254                 u32 addr;
12255                 u32 surface;
12256                 u32 tile_offset;
12257         } plane[I915_MAX_PIPES];
12258
12259         struct intel_transcoder_error_state {
12260                 bool power_domain_on;
12261                 enum transcoder cpu_transcoder;
12262
12263                 u32 conf;
12264
12265                 u32 htotal;
12266                 u32 hblank;
12267                 u32 hsync;
12268                 u32 vtotal;
12269                 u32 vblank;
12270                 u32 vsync;
12271         } transcoder[4];
12272 };
12273
12274 struct intel_display_error_state *
12275 intel_display_capture_error_state(struct drm_device *dev)
12276 {
12277         struct drm_i915_private *dev_priv = dev->dev_private;
12278         struct intel_display_error_state *error;
12279         int transcoders[] = {
12280                 TRANSCODER_A,
12281                 TRANSCODER_B,
12282                 TRANSCODER_C,
12283                 TRANSCODER_EDP,
12284         };
12285         int i;
12286
12287         if (INTEL_INFO(dev)->num_pipes == 0)
12288                 return NULL;
12289
12290         error = kzalloc(sizeof(*error), GFP_ATOMIC);
12291         if (error == NULL)
12292                 return NULL;
12293
12294         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12295                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12296
12297         for_each_pipe(i) {
12298                 error->pipe[i].power_domain_on =
12299                         intel_display_power_enabled_sw(dev_priv,
12300                                                        POWER_DOMAIN_PIPE(i));
12301                 if (!error->pipe[i].power_domain_on)
12302                         continue;
12303
12304                 error->cursor[i].control = I915_READ(CURCNTR(i));
12305                 error->cursor[i].position = I915_READ(CURPOS(i));
12306                 error->cursor[i].base = I915_READ(CURBASE(i));
12307
12308                 error->plane[i].control = I915_READ(DSPCNTR(i));
12309                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12310                 if (INTEL_INFO(dev)->gen <= 3) {
12311                         error->plane[i].size = I915_READ(DSPSIZE(i));
12312                         error->plane[i].pos = I915_READ(DSPPOS(i));
12313                 }
12314                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12315                         error->plane[i].addr = I915_READ(DSPADDR(i));
12316                 if (INTEL_INFO(dev)->gen >= 4) {
12317                         error->plane[i].surface = I915_READ(DSPSURF(i));
12318                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12319                 }
12320
12321                 error->pipe[i].source = I915_READ(PIPESRC(i));
12322
12323                 if (!HAS_PCH_SPLIT(dev))
12324                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
12325         }
12326
12327         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12328         if (HAS_DDI(dev_priv->dev))
12329                 error->num_transcoders++; /* Account for eDP. */
12330
12331         for (i = 0; i < error->num_transcoders; i++) {
12332                 enum transcoder cpu_transcoder = transcoders[i];
12333
12334                 error->transcoder[i].power_domain_on =
12335                         intel_display_power_enabled_sw(dev_priv,
12336                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12337                 if (!error->transcoder[i].power_domain_on)
12338                         continue;
12339
12340                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12341
12342                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12343                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12344                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12345                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12346                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12347                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12348                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12349         }
12350
12351         return error;
12352 }
12353
12354 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12355
12356 void
12357 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12358                                 struct drm_device *dev,
12359                                 struct intel_display_error_state *error)
12360 {
12361         int i;
12362
12363         if (!error)
12364                 return;
12365
12366         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12367         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12368                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12369                            error->power_well_driver);
12370         for_each_pipe(i) {
12371                 err_printf(m, "Pipe [%d]:\n", i);
12372                 err_printf(m, "  Power: %s\n",
12373                            error->pipe[i].power_domain_on ? "on" : "off");
12374                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
12375                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
12376
12377                 err_printf(m, "Plane [%d]:\n", i);
12378                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
12379                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
12380                 if (INTEL_INFO(dev)->gen <= 3) {
12381                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
12382                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
12383                 }
12384                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12385                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
12386                 if (INTEL_INFO(dev)->gen >= 4) {
12387                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
12388                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
12389                 }
12390
12391                 err_printf(m, "Cursor [%d]:\n", i);
12392                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
12393                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
12394                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
12395         }
12396
12397         for (i = 0; i < error->num_transcoders; i++) {
12398                 err_printf(m, "CPU transcoder: %c\n",
12399                            transcoder_name(error->transcoder[i].cpu_transcoder));
12400                 err_printf(m, "  Power: %s\n",
12401                            error->transcoder[i].power_domain_on ? "on" : "off");
12402                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
12403                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
12404                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
12405                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
12406                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
12407                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
12408                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
12409         }
12410 }