2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54 static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
68 typedef struct intel_limit intel_limit_t;
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_pch_rawclk(struct drm_device *dev)
77 struct drm_i915_private *dev_priv = dev->dev_private;
79 WARN_ON(!HAS_PCH_SPLIT(dev));
81 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
84 static inline u32 /* units of 100MHz */
85 intel_fdi_link_freq(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
89 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
94 static const intel_limit_t intel_limits_i8xx_dac = {
95 .dot = { .min = 25000, .max = 350000 },
96 .vco = { .min = 908000, .max = 1512000 },
97 .n = { .min = 2, .max = 16 },
98 .m = { .min = 96, .max = 140 },
99 .m1 = { .min = 18, .max = 26 },
100 .m2 = { .min = 6, .max = 16 },
101 .p = { .min = 4, .max = 128 },
102 .p1 = { .min = 2, .max = 33 },
103 .p2 = { .dot_limit = 165000,
104 .p2_slow = 4, .p2_fast = 2 },
107 static const intel_limit_t intel_limits_i8xx_dvo = {
108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 908000, .max = 1512000 },
110 .n = { .min = 2, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 4 },
120 static const intel_limit_t intel_limits_i8xx_lvds = {
121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 908000, .max = 1512000 },
123 .n = { .min = 2, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
133 static const intel_limit_t intel_limits_i9xx_sdvo = {
134 .dot = { .min = 20000, .max = 400000 },
135 .vco = { .min = 1400000, .max = 2800000 },
136 .n = { .min = 1, .max = 6 },
137 .m = { .min = 70, .max = 120 },
138 .m1 = { .min = 8, .max = 18 },
139 .m2 = { .min = 3, .max = 7 },
140 .p = { .min = 5, .max = 80 },
141 .p1 = { .min = 1, .max = 8 },
142 .p2 = { .dot_limit = 200000,
143 .p2_slow = 10, .p2_fast = 5 },
146 static const intel_limit_t intel_limits_i9xx_lvds = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 7, .max = 98 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 112000,
156 .p2_slow = 14, .p2_fast = 7 },
160 static const intel_limit_t intel_limits_g4x_sdvo = {
161 .dot = { .min = 25000, .max = 270000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 17, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 10, .max = 30 },
168 .p1 = { .min = 1, .max = 3},
169 .p2 = { .dot_limit = 270000,
175 static const intel_limit_t intel_limits_g4x_hdmi = {
176 .dot = { .min = 22000, .max = 400000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 16, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 5, .max = 80 },
183 .p1 = { .min = 1, .max = 8},
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 10, .p2_fast = 5 },
188 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
189 .dot = { .min = 20000, .max = 115000 },
190 .vco = { .min = 1750000, .max = 3500000 },
191 .n = { .min = 1, .max = 3 },
192 .m = { .min = 104, .max = 138 },
193 .m1 = { .min = 17, .max = 23 },
194 .m2 = { .min = 5, .max = 11 },
195 .p = { .min = 28, .max = 112 },
196 .p1 = { .min = 2, .max = 8 },
197 .p2 = { .dot_limit = 0,
198 .p2_slow = 14, .p2_fast = 14
202 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
203 .dot = { .min = 80000, .max = 224000 },
204 .vco = { .min = 1750000, .max = 3500000 },
205 .n = { .min = 1, .max = 3 },
206 .m = { .min = 104, .max = 138 },
207 .m1 = { .min = 17, .max = 23 },
208 .m2 = { .min = 5, .max = 11 },
209 .p = { .min = 14, .max = 42 },
210 .p1 = { .min = 2, .max = 6 },
211 .p2 = { .dot_limit = 0,
212 .p2_slow = 7, .p2_fast = 7
216 static const intel_limit_t intel_limits_pineview_sdvo = {
217 .dot = { .min = 20000, .max = 400000},
218 .vco = { .min = 1700000, .max = 3500000 },
219 /* Pineview's Ncounter is a ring counter */
220 .n = { .min = 3, .max = 6 },
221 .m = { .min = 2, .max = 256 },
222 /* Pineview only has one combined m divider, which we treat as m2. */
223 .m1 = { .min = 0, .max = 0 },
224 .m2 = { .min = 0, .max = 254 },
225 .p = { .min = 5, .max = 80 },
226 .p1 = { .min = 1, .max = 8 },
227 .p2 = { .dot_limit = 200000,
228 .p2_slow = 10, .p2_fast = 5 },
231 static const intel_limit_t intel_limits_pineview_lvds = {
232 .dot = { .min = 20000, .max = 400000 },
233 .vco = { .min = 1700000, .max = 3500000 },
234 .n = { .min = 3, .max = 6 },
235 .m = { .min = 2, .max = 256 },
236 .m1 = { .min = 0, .max = 0 },
237 .m2 = { .min = 0, .max = 254 },
238 .p = { .min = 7, .max = 112 },
239 .p1 = { .min = 1, .max = 8 },
240 .p2 = { .dot_limit = 112000,
241 .p2_slow = 14, .p2_fast = 14 },
244 /* Ironlake / Sandybridge
246 * We calculate clock using (register_value + 2) for N/M1/M2, so here
247 * the range value for them is (actual_value - 2).
249 static const intel_limit_t intel_limits_ironlake_dac = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 1760000, .max = 3510000 },
252 .n = { .min = 1, .max = 5 },
253 .m = { .min = 79, .max = 127 },
254 .m1 = { .min = 12, .max = 22 },
255 .m2 = { .min = 5, .max = 9 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 225000,
259 .p2_slow = 10, .p2_fast = 5 },
262 static const intel_limit_t intel_limits_ironlake_single_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 1760000, .max = 3510000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 79, .max = 118 },
267 .m1 = { .min = 12, .max = 22 },
268 .m2 = { .min = 5, .max = 9 },
269 .p = { .min = 28, .max = 112 },
270 .p1 = { .min = 2, .max = 8 },
271 .p2 = { .dot_limit = 225000,
272 .p2_slow = 14, .p2_fast = 14 },
275 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 3 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 14, .max = 56 },
283 .p1 = { .min = 2, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 7, .p2_fast = 7 },
288 /* LVDS 100mhz refclk limits. */
289 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 2 },
293 .m = { .min = 79, .max = 126 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
302 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 126 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 42 },
310 .p1 = { .min = 2, .max = 6 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
315 static const intel_limit_t intel_limits_vlv = {
317 * These are the data rate limits (measured in fast clocks)
318 * since those are the strictest limits we have. The fast
319 * clock and actual rate limits are more relaxed, so checking
320 * them would make no difference.
322 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
323 .vco = { .min = 4000000, .max = 6000000 },
324 .n = { .min = 1, .max = 7 },
325 .m1 = { .min = 2, .max = 3 },
326 .m2 = { .min = 11, .max = 156 },
327 .p1 = { .min = 2, .max = 3 },
328 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
331 static void vlv_clock(int refclk, intel_clock_t *clock)
333 clock->m = clock->m1 * clock->m2;
334 clock->p = clock->p1 * clock->p2;
335 if (WARN_ON(clock->n == 0 || clock->p == 0))
337 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
338 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
342 * Returns whether any output on the specified pipe is of the specified type
344 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
346 struct drm_device *dev = crtc->dev;
347 struct intel_encoder *encoder;
349 for_each_encoder_on_crtc(dev, crtc, encoder)
350 if (encoder->type == type)
356 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 struct drm_device *dev = crtc->dev;
360 const intel_limit_t *limit;
362 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
363 if (intel_is_dual_link_lvds(dev)) {
364 if (refclk == 100000)
365 limit = &intel_limits_ironlake_dual_lvds_100m;
367 limit = &intel_limits_ironlake_dual_lvds;
369 if (refclk == 100000)
370 limit = &intel_limits_ironlake_single_lvds_100m;
372 limit = &intel_limits_ironlake_single_lvds;
375 limit = &intel_limits_ironlake_dac;
380 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
382 struct drm_device *dev = crtc->dev;
383 const intel_limit_t *limit;
385 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
386 if (intel_is_dual_link_lvds(dev))
387 limit = &intel_limits_g4x_dual_channel_lvds;
389 limit = &intel_limits_g4x_single_channel_lvds;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
391 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
392 limit = &intel_limits_g4x_hdmi;
393 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
394 limit = &intel_limits_g4x_sdvo;
395 } else /* The option is for other outputs */
396 limit = &intel_limits_i9xx_sdvo;
401 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
403 struct drm_device *dev = crtc->dev;
404 const intel_limit_t *limit;
406 if (HAS_PCH_SPLIT(dev))
407 limit = intel_ironlake_limit(crtc, refclk);
408 else if (IS_G4X(dev)) {
409 limit = intel_g4x_limit(crtc);
410 } else if (IS_PINEVIEW(dev)) {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_pineview_lvds;
414 limit = &intel_limits_pineview_sdvo;
415 } else if (IS_VALLEYVIEW(dev)) {
416 limit = &intel_limits_vlv;
417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
421 limit = &intel_limits_i9xx_sdvo;
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
424 limit = &intel_limits_i8xx_lvds;
425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
426 limit = &intel_limits_i8xx_dvo;
428 limit = &intel_limits_i8xx_dac;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk, intel_clock_t *clock)
436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 if (WARN_ON(clock->n == 0 || clock->p == 0))
440 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
441 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
444 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
446 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449 static void i9xx_clock(int refclk, intel_clock_t *clock)
451 clock->m = i9xx_dpll_compute_m(clock);
452 clock->p = clock->p1 * clock->p2;
453 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
455 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
456 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
459 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
461 * Returns whether the given set of divisors are valid for a given refclk with
462 * the given connectors.
465 static bool intel_PLL_is_valid(struct drm_device *dev,
466 const intel_limit_t *limit,
467 const intel_clock_t *clock)
469 if (clock->n < limit->n.min || limit->n.max < clock->n)
470 INTELPllInvalid("n out of range\n");
471 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
472 INTELPllInvalid("p1 out of range\n");
473 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
474 INTELPllInvalid("m2 out of range\n");
475 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
476 INTELPllInvalid("m1 out of range\n");
478 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
479 if (clock->m1 <= clock->m2)
480 INTELPllInvalid("m1 <= m2\n");
482 if (!IS_VALLEYVIEW(dev)) {
483 if (clock->p < limit->p.min || limit->p.max < clock->p)
484 INTELPllInvalid("p out of range\n");
485 if (clock->m < limit->m.min || limit->m.max < clock->m)
486 INTELPllInvalid("m out of range\n");
489 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
490 INTELPllInvalid("vco out of range\n");
491 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
492 * connector, etc., rather than just a single range.
494 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
495 INTELPllInvalid("dot out of range\n");
501 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
502 int target, int refclk, intel_clock_t *match_clock,
503 intel_clock_t *best_clock)
505 struct drm_device *dev = crtc->dev;
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
511 * For LVDS just rely on its current settings for dual-channel.
512 * We haven't figured out how to reliably set up different
513 * single/dual channel state, if we even can.
515 if (intel_is_dual_link_lvds(dev))
516 clock.p2 = limit->p2.p2_fast;
518 clock.p2 = limit->p2.p2_slow;
520 if (target < limit->p2.dot_limit)
521 clock.p2 = limit->p2.p2_slow;
523 clock.p2 = limit->p2.p2_fast;
526 memset(best_clock, 0, sizeof(*best_clock));
528 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
530 for (clock.m2 = limit->m2.min;
531 clock.m2 <= limit->m2.max; clock.m2++) {
532 if (clock.m2 >= clock.m1)
534 for (clock.n = limit->n.min;
535 clock.n <= limit->n.max; clock.n++) {
536 for (clock.p1 = limit->p1.min;
537 clock.p1 <= limit->p1.max; clock.p1++) {
540 i9xx_clock(refclk, &clock);
541 if (!intel_PLL_is_valid(dev, limit,
545 clock.p != match_clock->p)
548 this_err = abs(clock.dot - target);
549 if (this_err < err) {
558 return (err != target);
562 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
563 int target, int refclk, intel_clock_t *match_clock,
564 intel_clock_t *best_clock)
566 struct drm_device *dev = crtc->dev;
570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
572 * For LVDS just rely on its current settings for dual-channel.
573 * We haven't figured out how to reliably set up different
574 * single/dual channel state, if we even can.
576 if (intel_is_dual_link_lvds(dev))
577 clock.p2 = limit->p2.p2_fast;
579 clock.p2 = limit->p2.p2_slow;
581 if (target < limit->p2.dot_limit)
582 clock.p2 = limit->p2.p2_slow;
584 clock.p2 = limit->p2.p2_fast;
587 memset(best_clock, 0, sizeof(*best_clock));
589 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
591 for (clock.m2 = limit->m2.min;
592 clock.m2 <= limit->m2.max; clock.m2++) {
593 for (clock.n = limit->n.min;
594 clock.n <= limit->n.max; clock.n++) {
595 for (clock.p1 = limit->p1.min;
596 clock.p1 <= limit->p1.max; clock.p1++) {
599 pineview_clock(refclk, &clock);
600 if (!intel_PLL_is_valid(dev, limit,
604 clock.p != match_clock->p)
607 this_err = abs(clock.dot - target);
608 if (this_err < err) {
617 return (err != target);
621 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
622 int target, int refclk, intel_clock_t *match_clock,
623 intel_clock_t *best_clock)
625 struct drm_device *dev = crtc->dev;
629 /* approximately equals target * 0.00585 */
630 int err_most = (target >> 8) + (target >> 9);
633 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
634 if (intel_is_dual_link_lvds(dev))
635 clock.p2 = limit->p2.p2_fast;
637 clock.p2 = limit->p2.p2_slow;
639 if (target < limit->p2.dot_limit)
640 clock.p2 = limit->p2.p2_slow;
642 clock.p2 = limit->p2.p2_fast;
645 memset(best_clock, 0, sizeof(*best_clock));
646 max_n = limit->n.max;
647 /* based on hardware requirement, prefer smaller n to precision */
648 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
649 /* based on hardware requirement, prefere larger m1,m2 */
650 for (clock.m1 = limit->m1.max;
651 clock.m1 >= limit->m1.min; clock.m1--) {
652 for (clock.m2 = limit->m2.max;
653 clock.m2 >= limit->m2.min; clock.m2--) {
654 for (clock.p1 = limit->p1.max;
655 clock.p1 >= limit->p1.min; clock.p1--) {
658 i9xx_clock(refclk, &clock);
659 if (!intel_PLL_is_valid(dev, limit,
663 this_err = abs(clock.dot - target);
664 if (this_err < err_most) {
678 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
679 int target, int refclk, intel_clock_t *match_clock,
680 intel_clock_t *best_clock)
682 struct drm_device *dev = crtc->dev;
684 unsigned int bestppm = 1000000;
685 /* min update 19.2 MHz */
686 int max_n = min(limit->n.max, refclk / 19200);
689 target *= 5; /* fast clock */
691 memset(best_clock, 0, sizeof(*best_clock));
693 /* based on hardware requirement, prefer smaller n to precision */
694 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
695 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
696 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
697 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
698 clock.p = clock.p1 * clock.p2;
699 /* based on hardware requirement, prefer bigger m1,m2 values */
700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
701 unsigned int ppm, diff;
703 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
706 vlv_clock(refclk, &clock);
708 if (!intel_PLL_is_valid(dev, limit,
712 diff = abs(clock.dot - target);
713 ppm = div_u64(1000000ULL * diff, target);
715 if (ppm < 100 && clock.p > best_clock->p) {
721 if (bestppm >= 10 && ppm < bestppm - 10) {
734 bool intel_crtc_active(struct drm_crtc *crtc)
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738 /* Be paranoid as we can arrive here with only partial
739 * state retrieved from the hardware during setup.
741 * We can ditch the adjusted_mode.crtc_clock check as soon
742 * as Haswell has gained clock readout/fastboot support.
744 * We can ditch the crtc->primary->fb check as soon as we can
745 * properly reconstruct framebuffers.
747 return intel_crtc->active && crtc->primary->fb &&
748 intel_crtc->config.adjusted_mode.crtc_clock;
751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757 return intel_crtc->config.cpu_transcoder;
760 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
765 frame = I915_READ(frame_reg);
767 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
768 WARN(1, "vblank wait timed out\n");
772 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @pipe: pipe to wait for
776 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 int pipestat_reg = PIPESTAT(pipe);
784 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
785 g4x_wait_for_vblank(dev, pipe);
789 /* Clear existing vblank status. Note this will clear any other
790 * sticky status fields as well.
792 * This races with i915_driver_irq_handler() with the result
793 * that either function could miss a vblank event. Here it is not
794 * fatal, as we will either wait upon the next vblank interrupt or
795 * timeout. Generally speaking intel_wait_for_vblank() is only
796 * called during modeset at which time the GPU should be idle and
797 * should *not* be performing page flips and thus not waiting on
799 * Currently, the result of us stealing a vblank from the irq
800 * handler is that a single frame will be skipped during swapbuffers.
802 I915_WRITE(pipestat_reg,
803 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805 /* Wait for vblank interrupt bit to set */
806 if (wait_for(I915_READ(pipestat_reg) &
807 PIPE_VBLANK_INTERRUPT_STATUS,
809 DRM_DEBUG_KMS("vblank wait timed out\n");
812 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 u32 reg = PIPEDSL(pipe);
820 line_mask = DSL_LINEMASK_GEN2;
822 line_mask = DSL_LINEMASK_GEN3;
824 line1 = I915_READ(reg) & line_mask;
826 line2 = I915_READ(reg) & line_mask;
828 return line1 == line2;
832 * intel_wait_for_pipe_off - wait for pipe to turn off
834 * @pipe: pipe to wait for
836 * After disabling a pipe, we can't wait for vblank in the usual way,
837 * spinning on the vblank interrupt status bit, since we won't actually
838 * see an interrupt when the pipe is disabled.
841 * wait for the pipe register state bit to turn off
844 * wait for the display line value to settle (it usually
845 * ends up stopping at the start of the next frame).
848 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 if (INTEL_INFO(dev)->gen >= 4) {
855 int reg = PIPECONF(cpu_transcoder);
857 /* Wait for the Pipe State to go off */
858 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
860 WARN(1, "pipe_off wait timed out\n");
862 /* Wait for the display line to settle */
863 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
864 WARN(1, "pipe_off wait timed out\n");
869 * ibx_digital_port_connected - is the specified port connected?
870 * @dev_priv: i915 private structure
871 * @port: the port to test
873 * Returns true if @port is connected, false otherwise.
875 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
876 struct intel_digital_port *port)
880 if (HAS_PCH_IBX(dev_priv->dev)) {
883 bit = SDE_PORTB_HOTPLUG;
886 bit = SDE_PORTC_HOTPLUG;
889 bit = SDE_PORTD_HOTPLUG;
897 bit = SDE_PORTB_HOTPLUG_CPT;
900 bit = SDE_PORTC_HOTPLUG_CPT;
903 bit = SDE_PORTD_HOTPLUG_CPT;
910 return I915_READ(SDEISR) & bit;
913 static const char *state_string(bool enabled)
915 return enabled ? "on" : "off";
918 /* Only for pre-ILK configs */
919 void assert_pll(struct drm_i915_private *dev_priv,
920 enum pipe pipe, bool state)
927 val = I915_READ(reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PLL state assertion failure (expected %s, current %s)\n",
931 state_string(state), state_string(cur_state));
934 /* XXX: the dsi pll is shared between MIPI DSI ports */
935 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
940 mutex_lock(&dev_priv->dpio_lock);
941 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
942 mutex_unlock(&dev_priv->dpio_lock);
944 cur_state = val & DSI_PLL_VCO_EN;
945 WARN(cur_state != state,
946 "DSI PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
949 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
950 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
952 struct intel_shared_dpll *
953 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
955 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
957 if (crtc->config.shared_dpll < 0)
960 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
964 void assert_shared_dpll(struct drm_i915_private *dev_priv,
965 struct intel_shared_dpll *pll,
969 struct intel_dpll_hw_state hw_state;
971 if (HAS_PCH_LPT(dev_priv->dev)) {
972 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
977 "asserting DPLL %s with no DPLL\n", state_string(state)))
980 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
981 WARN(cur_state != state,
982 "%s assertion failure (expected %s, current %s)\n",
983 pll->name, state_string(state), state_string(cur_state));
986 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
987 enum pipe pipe, bool state)
992 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
995 if (HAS_DDI(dev_priv->dev)) {
996 /* DDI does not have a specific FDI_TX register */
997 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
998 val = I915_READ(reg);
999 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1001 reg = FDI_TX_CTL(pipe);
1002 val = I915_READ(reg);
1003 cur_state = !!(val & FDI_TX_ENABLE);
1005 WARN(cur_state != state,
1006 "FDI TX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1009 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1010 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1012 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1019 reg = FDI_RX_CTL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & FDI_RX_ENABLE);
1022 WARN(cur_state != state,
1023 "FDI RX state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1026 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1027 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1029 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1035 /* ILK FDI PLL is always enabled */
1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1040 if (HAS_DDI(dev_priv->dev))
1043 reg = FDI_TX_CTL(pipe);
1044 val = I915_READ(reg);
1045 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1048 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1055 reg = FDI_RX_CTL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1058 WARN(cur_state != state,
1059 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1063 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 int pp_reg, lvds_reg;
1068 enum pipe panel_pipe = PIPE_A;
1071 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1072 pp_reg = PCH_PP_CONTROL;
1073 lvds_reg = PCH_LVDS;
1075 pp_reg = PP_CONTROL;
1079 val = I915_READ(pp_reg);
1080 if (!(val & PANEL_POWER_ON) ||
1081 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1085 panel_pipe = PIPE_B;
1087 WARN(panel_pipe == pipe && locked,
1088 "panel assertion failure, pipe %c regs locked\n",
1092 static void assert_cursor(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1095 struct drm_device *dev = dev_priv->dev;
1098 if (IS_845G(dev) || IS_I865G(dev))
1099 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1100 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
1101 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1103 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1105 WARN(cur_state != state,
1106 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1107 pipe_name(pipe), state_string(state), state_string(cur_state));
1109 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1110 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1112 void assert_pipe(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1121 /* if we need the pipe A quirk it must be always on */
1122 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1125 if (!intel_display_power_enabled(dev_priv,
1126 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1129 reg = PIPECONF(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & PIPECONF_ENABLE);
1134 WARN(cur_state != state,
1135 "pipe %c assertion failure (expected %s, current %s)\n",
1136 pipe_name(pipe), state_string(state), state_string(cur_state));
1139 static void assert_plane(struct drm_i915_private *dev_priv,
1140 enum plane plane, bool state)
1146 reg = DSPCNTR(plane);
1147 val = I915_READ(reg);
1148 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1149 WARN(cur_state != state,
1150 "plane %c assertion failure (expected %s, current %s)\n",
1151 plane_name(plane), state_string(state), state_string(cur_state));
1154 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1155 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1157 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1160 struct drm_device *dev = dev_priv->dev;
1165 /* Primary planes are fixed to pipes on gen4+ */
1166 if (INTEL_INFO(dev)->gen >= 4) {
1167 reg = DSPCNTR(pipe);
1168 val = I915_READ(reg);
1169 WARN(val & DISPLAY_PLANE_ENABLE,
1170 "plane %c assertion failure, should be disabled but not\n",
1175 /* Need to check both planes against the pipe */
1178 val = I915_READ(reg);
1179 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1180 DISPPLANE_SEL_PIPE_SHIFT;
1181 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1182 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1183 plane_name(i), pipe_name(pipe));
1187 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1190 struct drm_device *dev = dev_priv->dev;
1194 if (IS_VALLEYVIEW(dev)) {
1195 for_each_sprite(pipe, sprite) {
1196 reg = SPCNTR(pipe, sprite);
1197 val = I915_READ(reg);
1198 WARN(val & SP_ENABLE,
1199 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1200 sprite_name(pipe, sprite), pipe_name(pipe));
1202 } else if (INTEL_INFO(dev)->gen >= 7) {
1204 val = I915_READ(reg);
1205 WARN(val & SPRITE_ENABLE,
1206 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1207 plane_name(pipe), pipe_name(pipe));
1208 } else if (INTEL_INFO(dev)->gen >= 5) {
1209 reg = DVSCNTR(pipe);
1210 val = I915_READ(reg);
1211 WARN(val & DVS_ENABLE,
1212 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1213 plane_name(pipe), pipe_name(pipe));
1217 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1222 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1248 if ((val & DP_PORT_EN) == 0)
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1266 if ((val & SDVO_ENABLE) == 0)
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1282 if ((val & LVDS_PORT_EN) == 0)
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1363 static void intel_init_dpio(struct drm_device *dev)
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1367 if (!IS_VALLEYVIEW(dev))
1370 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1373 static void intel_reset_dpio(struct drm_device *dev)
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1377 if (!IS_VALLEYVIEW(dev))
1381 * Enable the CRI clock source so we can get at the display and the
1382 * reference clock for VGA hotplug / manual detection.
1384 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1385 DPLL_REFA_CLK_ENABLE_VLV |
1386 DPLL_INTEGRATED_CRI_CLK_VLV);
1389 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1390 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1391 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1392 * b. The other bits such as sfr settings / modesel may all be set
1395 * This should only be done on init and resume from S3 with both
1396 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1398 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1401 static void vlv_enable_pll(struct intel_crtc *crtc)
1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
1408 assert_pipe_disabled(dev_priv, crtc->pipe);
1410 /* No really, not for ILK+ */
1411 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1413 /* PLL is protected by panel, make sure we can write it */
1414 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
1417 I915_WRITE(reg, dpll);
1421 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1422 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1424 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1425 POSTING_READ(DPLL_MD(crtc->pipe));
1427 /* We do this three times for luck */
1428 I915_WRITE(reg, dpll);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg, dpll);
1433 udelay(150); /* wait for warmup */
1434 I915_WRITE(reg, dpll);
1436 udelay(150); /* wait for warmup */
1439 static void i9xx_enable_pll(struct intel_crtc *crtc)
1441 struct drm_device *dev = crtc->base.dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 int reg = DPLL(crtc->pipe);
1444 u32 dpll = crtc->config.dpll_hw_state.dpll;
1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1448 /* No really, not for ILK+ */
1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev) && !IS_I830(dev))
1453 assert_panel_unlocked(dev_priv, crtc->pipe);
1455 I915_WRITE(reg, dpll);
1457 /* Wait for the clocks to stabilize. */
1461 if (INTEL_INFO(dev)->gen >= 4) {
1462 I915_WRITE(DPLL_MD(crtc->pipe),
1463 crtc->config.dpll_hw_state.dpll_md);
1465 /* The pixel multiplier can only be updated once the
1466 * DPLL is enabled and the clocks are stable.
1468 * So write it again.
1470 I915_WRITE(reg, dpll);
1473 /* We do this three times for luck */
1474 I915_WRITE(reg, dpll);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg, dpll);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, dpll);
1482 udelay(150); /* wait for warmup */
1486 * i9xx_disable_pll - disable a PLL
1487 * @dev_priv: i915 private structure
1488 * @pipe: pipe PLL to disable
1490 * Disable the PLL for @pipe, making sure the pipe is off first.
1492 * Note! This is for pre-ILK only.
1494 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1496 /* Don't disable pipe A or pipe A PLLs if needed */
1497 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1500 /* Make sure the pipe isn't still relying on us */
1501 assert_pipe_disabled(dev_priv, pipe);
1503 I915_WRITE(DPLL(pipe), 0);
1504 POSTING_READ(DPLL(pipe));
1507 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1511 /* Make sure the pipe isn't still relying on us */
1512 assert_pipe_disabled(dev_priv, pipe);
1515 * Leave integrated clock source and reference clock enabled for pipe B.
1516 * The latter is needed for VGA hotplug / manual detection.
1519 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1520 I915_WRITE(DPLL(pipe), val);
1521 POSTING_READ(DPLL(pipe));
1524 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1525 struct intel_digital_port *dport)
1529 switch (dport->port) {
1531 port_mask = DPLL_PORTB_READY_MASK;
1534 port_mask = DPLL_PORTC_READY_MASK;
1540 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1541 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1542 port_name(dport->port), I915_READ(DPLL(0)));
1546 * ironlake_enable_shared_dpll - enable PCH PLL
1547 * @dev_priv: i915 private structure
1548 * @pipe: pipe PLL to enable
1550 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1551 * drives the transcoder clock.
1553 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1559 /* PCH PLLs only available on ILK, SNB and IVB */
1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1561 if (WARN_ON(pll == NULL))
1564 if (WARN_ON(pll->refcount == 0))
1567 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1568 pll->name, pll->active, pll->on,
1569 crtc->base.base.id);
1571 if (pll->active++) {
1573 assert_shared_dpll_enabled(dev_priv, pll);
1578 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1579 pll->enable(dev_priv, pll);
1583 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1589 /* PCH only available on ILK+ */
1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1591 if (WARN_ON(pll == NULL))
1594 if (WARN_ON(pll->refcount == 0))
1597 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1598 pll->name, pll->active, pll->on,
1599 crtc->base.base.id);
1601 if (WARN_ON(pll->active == 0)) {
1602 assert_shared_dpll_disabled(dev_priv, pll);
1606 assert_shared_dpll_enabled(dev_priv, pll);
1611 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1612 pll->disable(dev_priv, pll);
1616 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1619 struct drm_device *dev = dev_priv->dev;
1620 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1622 uint32_t reg, val, pipeconf_val;
1624 /* PCH only available on ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1627 /* Make sure PCH DPLL is enabled */
1628 assert_shared_dpll_enabled(dev_priv,
1629 intel_crtc_to_shared_dpll(intel_crtc));
1631 /* FDI must be feeding us bits for PCH ports */
1632 assert_fdi_tx_enabled(dev_priv, pipe);
1633 assert_fdi_rx_enabled(dev_priv, pipe);
1635 if (HAS_PCH_CPT(dev)) {
1636 /* Workaround: Set the timing override bit before enabling the
1637 * pch transcoder. */
1638 reg = TRANS_CHICKEN2(pipe);
1639 val = I915_READ(reg);
1640 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1641 I915_WRITE(reg, val);
1644 reg = PCH_TRANSCONF(pipe);
1645 val = I915_READ(reg);
1646 pipeconf_val = I915_READ(PIPECONF(pipe));
1648 if (HAS_PCH_IBX(dev_priv->dev)) {
1650 * make the BPC in transcoder be consistent with
1651 * that in pipeconf reg.
1653 val &= ~PIPECONF_BPC_MASK;
1654 val |= pipeconf_val & PIPECONF_BPC_MASK;
1657 val &= ~TRANS_INTERLACE_MASK;
1658 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1659 if (HAS_PCH_IBX(dev_priv->dev) &&
1660 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1661 val |= TRANS_LEGACY_INTERLACED_ILK;
1663 val |= TRANS_INTERLACED;
1665 val |= TRANS_PROGRESSIVE;
1667 I915_WRITE(reg, val | TRANS_ENABLE);
1668 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1669 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1672 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1673 enum transcoder cpu_transcoder)
1675 u32 val, pipeconf_val;
1677 /* PCH only available on ILK+ */
1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1680 /* FDI must be feeding us bits for PCH ports */
1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1682 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1684 /* Workaround: set timing override bit. */
1685 val = I915_READ(_TRANSA_CHICKEN2);
1686 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(_TRANSA_CHICKEN2, val);
1690 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1692 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1693 PIPECONF_INTERLACED_ILK)
1694 val |= TRANS_INTERLACED;
1696 val |= TRANS_PROGRESSIVE;
1698 I915_WRITE(LPT_TRANSCONF, val);
1699 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1700 DRM_ERROR("Failed to enable PCH transcoder\n");
1703 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1706 struct drm_device *dev = dev_priv->dev;
1709 /* FDI relies on the transcoder */
1710 assert_fdi_tx_disabled(dev_priv, pipe);
1711 assert_fdi_rx_disabled(dev_priv, pipe);
1713 /* Ports must be off as well */
1714 assert_pch_ports_disabled(dev_priv, pipe);
1716 reg = PCH_TRANSCONF(pipe);
1717 val = I915_READ(reg);
1718 val &= ~TRANS_ENABLE;
1719 I915_WRITE(reg, val);
1720 /* wait for PCH transcoder off, transcoder state */
1721 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1722 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1724 if (!HAS_PCH_IBX(dev)) {
1725 /* Workaround: Clear the timing override chicken bit again. */
1726 reg = TRANS_CHICKEN2(pipe);
1727 val = I915_READ(reg);
1728 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1729 I915_WRITE(reg, val);
1733 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1737 val = I915_READ(LPT_TRANSCONF);
1738 val &= ~TRANS_ENABLE;
1739 I915_WRITE(LPT_TRANSCONF, val);
1740 /* wait for PCH transcoder off, transcoder state */
1741 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1742 DRM_ERROR("Failed to disable PCH transcoder\n");
1744 /* Workaround: clear timing override bit. */
1745 val = I915_READ(_TRANSA_CHICKEN2);
1746 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1747 I915_WRITE(_TRANSA_CHICKEN2, val);
1751 * intel_enable_pipe - enable a pipe, asserting requirements
1752 * @crtc: crtc responsible for the pipe
1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1757 static void intel_enable_pipe(struct intel_crtc *crtc)
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 enum pipe pch_transcoder;
1768 assert_planes_disabled(dev_priv, pipe);
1769 assert_cursor_disabled(dev_priv, pipe);
1770 assert_sprites_disabled(dev_priv, pipe);
1772 if (HAS_PCH_LPT(dev_priv->dev))
1773 pch_transcoder = TRANSCODER_A;
1775 pch_transcoder = pipe;
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv);
1786 assert_pll_enabled(dev_priv, pipe);
1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv,
1792 (enum pipe) cpu_transcoder);
1794 /* FIXME: assert CPU port conditions for SNB+ */
1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1810 * intel_disable_pipe - disable a pipe, asserting requirements
1811 * @dev_priv: i915 private structure
1812 * @pipe: pipe to disable
1814 * Disable @pipe, making sure that various hardware specific requirements
1815 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1817 * @pipe should be %PIPE_A or %PIPE_B.
1819 * Will wait until the pipe has shut down before returning.
1821 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1824 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1830 * Make sure planes won't keep trying to pump pixels to us,
1831 * or we might hang the display.
1833 assert_planes_disabled(dev_priv, pipe);
1834 assert_cursor_disabled(dev_priv, pipe);
1835 assert_sprites_disabled(dev_priv, pipe);
1837 /* Don't disable pipe A or pipe A PLLs if needed */
1838 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1841 reg = PIPECONF(cpu_transcoder);
1842 val = I915_READ(reg);
1843 if ((val & PIPECONF_ENABLE) == 0)
1846 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1847 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1851 * Plane regs are double buffered, going from enabled->disabled needs a
1852 * trigger in order to latch. The display address reg provides this.
1854 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1857 struct drm_device *dev = dev_priv->dev;
1858 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1860 I915_WRITE(reg, I915_READ(reg));
1865 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
1866 * @dev_priv: i915 private structure
1867 * @plane: plane to enable
1868 * @pipe: pipe being fed
1870 * Enable @plane on @pipe, making sure that @pipe is running first.
1872 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1873 enum plane plane, enum pipe pipe)
1875 struct intel_crtc *intel_crtc =
1876 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1880 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1881 assert_pipe_enabled(dev_priv, pipe);
1883 if (intel_crtc->primary_enabled)
1886 intel_crtc->primary_enabled = true;
1888 reg = DSPCNTR(plane);
1889 val = I915_READ(reg);
1890 if (val & DISPLAY_PLANE_ENABLE)
1893 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1894 intel_flush_primary_plane(dev_priv, plane);
1895 intel_wait_for_vblank(dev_priv->dev, pipe);
1899 * intel_disable_primary_hw_plane - disable the primary hardware plane
1900 * @dev_priv: i915 private structure
1901 * @plane: plane to disable
1902 * @pipe: pipe consuming the data
1904 * Disable @plane; should be an independent operation.
1906 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1907 enum plane plane, enum pipe pipe)
1909 struct intel_crtc *intel_crtc =
1910 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1914 if (!intel_crtc->primary_enabled)
1917 intel_crtc->primary_enabled = false;
1919 reg = DSPCNTR(plane);
1920 val = I915_READ(reg);
1921 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1924 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1925 intel_flush_primary_plane(dev_priv, plane);
1926 intel_wait_for_vblank(dev_priv->dev, pipe);
1929 static bool need_vtd_wa(struct drm_device *dev)
1931 #ifdef CONFIG_INTEL_IOMMU
1932 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1938 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1942 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1943 return ALIGN(height, tile_height);
1947 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1948 struct drm_i915_gem_object *obj,
1949 struct intel_ring_buffer *pipelined)
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1955 switch (obj->tiling_mode) {
1956 case I915_TILING_NONE:
1957 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1958 alignment = 128 * 1024;
1959 else if (INTEL_INFO(dev)->gen >= 4)
1960 alignment = 4 * 1024;
1962 alignment = 64 * 1024;
1965 /* pin() will align the object as required by fence */
1969 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1975 /* Note that the w/a also requires 64 PTE of padding following the
1976 * bo. We currently fill all unused PTE with the shadow page and so
1977 * we should always have valid PTE following the scanout preventing
1980 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1981 alignment = 256 * 1024;
1983 dev_priv->mm.interruptible = false;
1984 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1986 goto err_interruptible;
1988 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1989 * fence, whereas 965+ only requires a fence if using
1990 * framebuffer compression. For simplicity, we always install
1991 * a fence as the cost is not that onerous.
1993 ret = i915_gem_object_get_fence(obj);
1997 i915_gem_object_pin_fence(obj);
1999 dev_priv->mm.interruptible = true;
2003 i915_gem_object_unpin_from_display_plane(obj);
2005 dev_priv->mm.interruptible = true;
2009 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2011 i915_gem_object_unpin_fence(obj);
2012 i915_gem_object_unpin_from_display_plane(obj);
2015 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2016 * is assumed to be a power-of-two. */
2017 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2018 unsigned int tiling_mode,
2022 if (tiling_mode != I915_TILING_NONE) {
2023 unsigned int tile_rows, tiles;
2028 tiles = *x / (512/cpp);
2031 return tile_rows * pitch * 8 + tiles * 4096;
2033 unsigned int offset;
2035 offset = *y * pitch + *x * cpp;
2037 *x = (offset & 4095) / cpp;
2038 return offset & -4096;
2042 int intel_format_to_fourcc(int format)
2045 case DISPPLANE_8BPP:
2046 return DRM_FORMAT_C8;
2047 case DISPPLANE_BGRX555:
2048 return DRM_FORMAT_XRGB1555;
2049 case DISPPLANE_BGRX565:
2050 return DRM_FORMAT_RGB565;
2052 case DISPPLANE_BGRX888:
2053 return DRM_FORMAT_XRGB8888;
2054 case DISPPLANE_RGBX888:
2055 return DRM_FORMAT_XBGR8888;
2056 case DISPPLANE_BGRX101010:
2057 return DRM_FORMAT_XRGB2101010;
2058 case DISPPLANE_RGBX101010:
2059 return DRM_FORMAT_XBGR2101010;
2063 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2064 struct intel_plane_config *plane_config)
2066 struct drm_device *dev = crtc->base.dev;
2067 struct drm_i915_gem_object *obj = NULL;
2068 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2069 u32 base = plane_config->base;
2071 if (plane_config->size == 0)
2074 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2075 plane_config->size);
2079 if (plane_config->tiled) {
2080 obj->tiling_mode = I915_TILING_X;
2081 obj->stride = crtc->base.primary->fb->pitches[0];
2084 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2085 mode_cmd.width = crtc->base.primary->fb->width;
2086 mode_cmd.height = crtc->base.primary->fb->height;
2087 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2089 mutex_lock(&dev->struct_mutex);
2091 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2093 DRM_DEBUG_KMS("intel fb init failed\n");
2097 mutex_unlock(&dev->struct_mutex);
2099 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2103 drm_gem_object_unreference(&obj->base);
2104 mutex_unlock(&dev->struct_mutex);
2108 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2109 struct intel_plane_config *plane_config)
2111 struct drm_device *dev = intel_crtc->base.dev;
2113 struct intel_crtc *i;
2114 struct intel_framebuffer *fb;
2116 if (!intel_crtc->base.primary->fb)
2119 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2122 kfree(intel_crtc->base.primary->fb);
2123 intel_crtc->base.primary->fb = NULL;
2126 * Failed to alloc the obj, check to see if we should share
2127 * an fb with another CRTC instead
2129 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
2130 i = to_intel_crtc(c);
2132 if (c == &intel_crtc->base)
2135 if (!i->active || !c->primary->fb)
2138 fb = to_intel_framebuffer(c->primary->fb);
2139 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2140 drm_framebuffer_reference(c->primary->fb);
2141 intel_crtc->base.primary->fb = c->primary->fb;
2147 static int i9xx_update_primary_plane(struct drm_crtc *crtc,
2148 struct drm_framebuffer *fb,
2151 struct drm_device *dev = crtc->dev;
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2154 struct intel_framebuffer *intel_fb;
2155 struct drm_i915_gem_object *obj;
2156 int plane = intel_crtc->plane;
2157 unsigned long linear_offset;
2161 intel_fb = to_intel_framebuffer(fb);
2162 obj = intel_fb->obj;
2164 reg = DSPCNTR(plane);
2165 dspcntr = I915_READ(reg);
2166 /* Mask out pixel format bits in case we change it */
2167 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2168 switch (fb->pixel_format) {
2170 dspcntr |= DISPPLANE_8BPP;
2172 case DRM_FORMAT_XRGB1555:
2173 case DRM_FORMAT_ARGB1555:
2174 dspcntr |= DISPPLANE_BGRX555;
2176 case DRM_FORMAT_RGB565:
2177 dspcntr |= DISPPLANE_BGRX565;
2179 case DRM_FORMAT_XRGB8888:
2180 case DRM_FORMAT_ARGB8888:
2181 dspcntr |= DISPPLANE_BGRX888;
2183 case DRM_FORMAT_XBGR8888:
2184 case DRM_FORMAT_ABGR8888:
2185 dspcntr |= DISPPLANE_RGBX888;
2187 case DRM_FORMAT_XRGB2101010:
2188 case DRM_FORMAT_ARGB2101010:
2189 dspcntr |= DISPPLANE_BGRX101010;
2191 case DRM_FORMAT_XBGR2101010:
2192 case DRM_FORMAT_ABGR2101010:
2193 dspcntr |= DISPPLANE_RGBX101010;
2199 if (INTEL_INFO(dev)->gen >= 4) {
2200 if (obj->tiling_mode != I915_TILING_NONE)
2201 dspcntr |= DISPPLANE_TILED;
2203 dspcntr &= ~DISPPLANE_TILED;
2207 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2209 I915_WRITE(reg, dspcntr);
2211 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2213 if (INTEL_INFO(dev)->gen >= 4) {
2214 intel_crtc->dspaddr_offset =
2215 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2216 fb->bits_per_pixel / 8,
2218 linear_offset -= intel_crtc->dspaddr_offset;
2220 intel_crtc->dspaddr_offset = linear_offset;
2223 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2224 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2226 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2227 if (INTEL_INFO(dev)->gen >= 4) {
2228 I915_WRITE(DSPSURF(plane),
2229 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2230 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2231 I915_WRITE(DSPLINOFF(plane), linear_offset);
2233 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2239 static int ironlake_update_primary_plane(struct drm_crtc *crtc,
2240 struct drm_framebuffer *fb,
2243 struct drm_device *dev = crtc->dev;
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2246 struct intel_framebuffer *intel_fb;
2247 struct drm_i915_gem_object *obj;
2248 int plane = intel_crtc->plane;
2249 unsigned long linear_offset;
2253 intel_fb = to_intel_framebuffer(fb);
2254 obj = intel_fb->obj;
2256 reg = DSPCNTR(plane);
2257 dspcntr = I915_READ(reg);
2258 /* Mask out pixel format bits in case we change it */
2259 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2260 switch (fb->pixel_format) {
2262 dspcntr |= DISPPLANE_8BPP;
2264 case DRM_FORMAT_RGB565:
2265 dspcntr |= DISPPLANE_BGRX565;
2267 case DRM_FORMAT_XRGB8888:
2268 case DRM_FORMAT_ARGB8888:
2269 dspcntr |= DISPPLANE_BGRX888;
2271 case DRM_FORMAT_XBGR8888:
2272 case DRM_FORMAT_ABGR8888:
2273 dspcntr |= DISPPLANE_RGBX888;
2275 case DRM_FORMAT_XRGB2101010:
2276 case DRM_FORMAT_ARGB2101010:
2277 dspcntr |= DISPPLANE_BGRX101010;
2279 case DRM_FORMAT_XBGR2101010:
2280 case DRM_FORMAT_ABGR2101010:
2281 dspcntr |= DISPPLANE_RGBX101010;
2287 if (obj->tiling_mode != I915_TILING_NONE)
2288 dspcntr |= DISPPLANE_TILED;
2290 dspcntr &= ~DISPPLANE_TILED;
2292 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2293 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2295 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2297 I915_WRITE(reg, dspcntr);
2299 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2300 intel_crtc->dspaddr_offset =
2301 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2302 fb->bits_per_pixel / 8,
2304 linear_offset -= intel_crtc->dspaddr_offset;
2306 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2307 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2309 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2310 I915_WRITE(DSPSURF(plane),
2311 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2312 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2313 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2315 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2316 I915_WRITE(DSPLINOFF(plane), linear_offset);
2323 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2325 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2326 int x, int y, enum mode_set_atomic state)
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2331 if (dev_priv->display.disable_fbc)
2332 dev_priv->display.disable_fbc(dev);
2333 intel_increase_pllclock(crtc);
2335 return dev_priv->display.update_primary_plane(crtc, fb, x, y);
2338 void intel_display_handle_reset(struct drm_device *dev)
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_crtc *crtc;
2344 * Flips in the rings have been nuked by the reset,
2345 * so complete all pending flips so that user space
2346 * will get its events and not get stuck.
2348 * Also update the base address of all primary
2349 * planes to the the last fb to make sure we're
2350 * showing the correct fb after a reset.
2352 * Need to make two loops over the crtcs so that we
2353 * don't try to grab a crtc mutex before the
2354 * pending_flip_queue really got woken up.
2357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2359 enum plane plane = intel_crtc->plane;
2361 intel_prepare_page_flip(dev, plane);
2362 intel_finish_page_flip_plane(dev, plane);
2365 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 mutex_lock(&crtc->mutex);
2370 * FIXME: Once we have proper support for primary planes (and
2371 * disabling them without disabling the entire crtc) allow again
2372 * a NULL crtc->primary->fb.
2374 if (intel_crtc->active && crtc->primary->fb)
2375 dev_priv->display.update_primary_plane(crtc,
2379 mutex_unlock(&crtc->mutex);
2384 intel_finish_fb(struct drm_framebuffer *old_fb)
2386 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2387 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2388 bool was_interruptible = dev_priv->mm.interruptible;
2391 /* Big Hammer, we also need to ensure that any pending
2392 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2393 * current scanout is retired before unpinning the old
2396 * This should only fail upon a hung GPU, in which case we
2397 * can safely continue.
2399 dev_priv->mm.interruptible = false;
2400 ret = i915_gem_object_finish_gpu(obj);
2401 dev_priv->mm.interruptible = was_interruptible;
2406 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 unsigned long flags;
2414 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2415 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2418 spin_lock_irqsave(&dev->event_lock, flags);
2419 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2420 spin_unlock_irqrestore(&dev->event_lock, flags);
2426 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2427 struct drm_framebuffer *fb)
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 struct drm_framebuffer *old_fb;
2435 if (intel_crtc_has_pending_flip(crtc)) {
2436 DRM_ERROR("pipe is still busy with an old pageflip\n");
2442 DRM_ERROR("No FB bound\n");
2446 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2447 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2448 plane_name(intel_crtc->plane),
2449 INTEL_INFO(dev)->num_pipes);
2453 mutex_lock(&dev->struct_mutex);
2454 ret = intel_pin_and_fence_fb_obj(dev,
2455 to_intel_framebuffer(fb)->obj,
2457 mutex_unlock(&dev->struct_mutex);
2459 DRM_ERROR("pin & fence failed\n");
2464 * Update pipe size and adjust fitter if needed: the reason for this is
2465 * that in compute_mode_changes we check the native mode (not the pfit
2466 * mode) to see if we can flip rather than do a full mode set. In the
2467 * fastboot case, we'll flip, but if we don't update the pipesrc and
2468 * pfit state, we'll end up with a big fb scanned out into the wrong
2471 * To fix this properly, we need to hoist the checks up into
2472 * compute_mode_changes (or above), check the actual pfit state and
2473 * whether the platform allows pfit disable with pipe active, and only
2474 * then update the pipesrc and pfit state, even on the flip path.
2476 if (i915.fastboot) {
2477 const struct drm_display_mode *adjusted_mode =
2478 &intel_crtc->config.adjusted_mode;
2480 I915_WRITE(PIPESRC(intel_crtc->pipe),
2481 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2482 (adjusted_mode->crtc_vdisplay - 1));
2483 if (!intel_crtc->config.pch_pfit.enabled &&
2484 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2485 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2486 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2487 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2488 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2490 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2491 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2494 ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
2496 mutex_lock(&dev->struct_mutex);
2497 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2498 mutex_unlock(&dev->struct_mutex);
2499 DRM_ERROR("failed to update base address\n");
2503 old_fb = crtc->primary->fb;
2504 crtc->primary->fb = fb;
2509 if (intel_crtc->active && old_fb != fb)
2510 intel_wait_for_vblank(dev, intel_crtc->pipe);
2511 mutex_lock(&dev->struct_mutex);
2512 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2513 mutex_unlock(&dev->struct_mutex);
2516 mutex_lock(&dev->struct_mutex);
2517 intel_update_fbc(dev);
2518 intel_edp_psr_update(dev);
2519 mutex_unlock(&dev->struct_mutex);
2524 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2526 struct drm_device *dev = crtc->dev;
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2529 int pipe = intel_crtc->pipe;
2532 /* enable normal train */
2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 if (IS_IVYBRIDGE(dev)) {
2536 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2537 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2539 temp &= ~FDI_LINK_TRAIN_NONE;
2540 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2542 I915_WRITE(reg, temp);
2544 reg = FDI_RX_CTL(pipe);
2545 temp = I915_READ(reg);
2546 if (HAS_PCH_CPT(dev)) {
2547 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2548 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_NONE;
2553 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2555 /* wait one idle pattern time */
2559 /* IVB wants error correction enabled */
2560 if (IS_IVYBRIDGE(dev))
2561 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2562 FDI_FE_ERRC_ENABLE);
2565 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2567 return crtc->base.enabled && crtc->active &&
2568 crtc->config.has_pch_encoder;
2571 static void ivb_modeset_global_resources(struct drm_device *dev)
2573 struct drm_i915_private *dev_priv = dev->dev_private;
2574 struct intel_crtc *pipe_B_crtc =
2575 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2576 struct intel_crtc *pipe_C_crtc =
2577 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2581 * When everything is off disable fdi C so that we could enable fdi B
2582 * with all lanes. Note that we don't care about enabled pipes without
2583 * an enabled pch encoder.
2585 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2586 !pipe_has_enabled_pch(pipe_C_crtc)) {
2587 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2588 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2590 temp = I915_READ(SOUTH_CHICKEN1);
2591 temp &= ~FDI_BC_BIFURCATION_SELECT;
2592 DRM_DEBUG_KMS("disabling fdi C rx\n");
2593 I915_WRITE(SOUTH_CHICKEN1, temp);
2597 /* The FDI link training functions for ILK/Ibexpeak. */
2598 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2600 struct drm_device *dev = crtc->dev;
2601 struct drm_i915_private *dev_priv = dev->dev_private;
2602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2603 int pipe = intel_crtc->pipe;
2604 u32 reg, temp, tries;
2606 /* FDI needs bits from pipe first */
2607 assert_pipe_enabled(dev_priv, pipe);
2609 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2611 reg = FDI_RX_IMR(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_RX_SYMBOL_LOCK;
2614 temp &= ~FDI_RX_BIT_LOCK;
2615 I915_WRITE(reg, temp);
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2623 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2624 temp &= ~FDI_LINK_TRAIN_NONE;
2625 temp |= FDI_LINK_TRAIN_PATTERN_1;
2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_NONE;
2631 temp |= FDI_LINK_TRAIN_PATTERN_1;
2632 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637 /* Ironlake workaround, enable clock pointer after FDI enable*/
2638 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2639 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2640 FDI_RX_PHASE_SYNC_POINTER_EN);
2642 reg = FDI_RX_IIR(pipe);
2643 for (tries = 0; tries < 5; tries++) {
2644 temp = I915_READ(reg);
2645 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2647 if ((temp & FDI_RX_BIT_LOCK)) {
2648 DRM_DEBUG_KMS("FDI train 1 done.\n");
2649 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2654 DRM_ERROR("FDI train 1 fail!\n");
2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_NONE;
2660 temp |= FDI_LINK_TRAIN_PATTERN_2;
2661 I915_WRITE(reg, temp);
2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_NONE;
2666 temp |= FDI_LINK_TRAIN_PATTERN_2;
2667 I915_WRITE(reg, temp);
2672 reg = FDI_RX_IIR(pipe);
2673 for (tries = 0; tries < 5; tries++) {
2674 temp = I915_READ(reg);
2675 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2677 if (temp & FDI_RX_SYMBOL_LOCK) {
2678 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2679 DRM_DEBUG_KMS("FDI train 2 done.\n");
2684 DRM_ERROR("FDI train 2 fail!\n");
2686 DRM_DEBUG_KMS("FDI train done\n");
2690 static const int snb_b_fdi_train_param[] = {
2691 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2692 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2693 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2694 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2697 /* The FDI link training functions for SNB/Cougarpoint. */
2698 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2700 struct drm_device *dev = crtc->dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 int pipe = intel_crtc->pipe;
2704 u32 reg, temp, i, retry;
2706 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2708 reg = FDI_RX_IMR(pipe);
2709 temp = I915_READ(reg);
2710 temp &= ~FDI_RX_SYMBOL_LOCK;
2711 temp &= ~FDI_RX_BIT_LOCK;
2712 I915_WRITE(reg, temp);
2717 /* enable CPU FDI TX and PCH FDI RX */
2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2721 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2722 temp &= ~FDI_LINK_TRAIN_NONE;
2723 temp |= FDI_LINK_TRAIN_PATTERN_1;
2724 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2729 I915_WRITE(FDI_RX_MISC(pipe),
2730 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2732 reg = FDI_RX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 if (HAS_PCH_CPT(dev)) {
2735 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2738 temp &= ~FDI_LINK_TRAIN_NONE;
2739 temp |= FDI_LINK_TRAIN_PATTERN_1;
2741 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2746 for (i = 0; i < 4; i++) {
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750 temp |= snb_b_fdi_train_param[i];
2751 I915_WRITE(reg, temp);
2756 for (retry = 0; retry < 5; retry++) {
2757 reg = FDI_RX_IIR(pipe);
2758 temp = I915_READ(reg);
2759 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2760 if (temp & FDI_RX_BIT_LOCK) {
2761 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2762 DRM_DEBUG_KMS("FDI train 1 done.\n");
2771 DRM_ERROR("FDI train 1 fail!\n");
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2;
2779 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2781 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2783 I915_WRITE(reg, temp);
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 if (HAS_PCH_CPT(dev)) {
2788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 temp &= ~FDI_LINK_TRAIN_NONE;
2792 temp |= FDI_LINK_TRAIN_PATTERN_2;
2794 I915_WRITE(reg, temp);
2799 for (i = 0; i < 4; i++) {
2800 reg = FDI_TX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2803 temp |= snb_b_fdi_train_param[i];
2804 I915_WRITE(reg, temp);
2809 for (retry = 0; retry < 5; retry++) {
2810 reg = FDI_RX_IIR(pipe);
2811 temp = I915_READ(reg);
2812 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2813 if (temp & FDI_RX_SYMBOL_LOCK) {
2814 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2815 DRM_DEBUG_KMS("FDI train 2 done.\n");
2824 DRM_ERROR("FDI train 2 fail!\n");
2826 DRM_DEBUG_KMS("FDI train done.\n");
2829 /* Manual link training for Ivy Bridge A0 parts */
2830 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2832 struct drm_device *dev = crtc->dev;
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2835 int pipe = intel_crtc->pipe;
2836 u32 reg, temp, i, j;
2838 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2840 reg = FDI_RX_IMR(pipe);
2841 temp = I915_READ(reg);
2842 temp &= ~FDI_RX_SYMBOL_LOCK;
2843 temp &= ~FDI_RX_BIT_LOCK;
2844 I915_WRITE(reg, temp);
2849 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2850 I915_READ(FDI_RX_IIR(pipe)));
2852 /* Try each vswing and preemphasis setting twice before moving on */
2853 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2854 /* disable first in case we need to retry */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2858 temp &= ~FDI_TX_ENABLE;
2859 I915_WRITE(reg, temp);
2861 reg = FDI_RX_CTL(pipe);
2862 temp = I915_READ(reg);
2863 temp &= ~FDI_LINK_TRAIN_AUTO;
2864 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2865 temp &= ~FDI_RX_ENABLE;
2866 I915_WRITE(reg, temp);
2868 /* enable CPU FDI TX and PCH FDI RX */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2872 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2873 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2874 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2875 temp |= snb_b_fdi_train_param[j/2];
2876 temp |= FDI_COMPOSITE_SYNC;
2877 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2879 I915_WRITE(FDI_RX_MISC(pipe),
2880 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2885 temp |= FDI_COMPOSITE_SYNC;
2886 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2889 udelay(1); /* should be 0.5us */
2891 for (i = 0; i < 4; i++) {
2892 reg = FDI_RX_IIR(pipe);
2893 temp = I915_READ(reg);
2894 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2896 if (temp & FDI_RX_BIT_LOCK ||
2897 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2898 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2899 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2903 udelay(1); /* should be 0.5us */
2906 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2911 reg = FDI_TX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2915 I915_WRITE(reg, temp);
2917 reg = FDI_RX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2920 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2921 I915_WRITE(reg, temp);
2924 udelay(2); /* should be 1.5us */
2926 for (i = 0; i < 4; i++) {
2927 reg = FDI_RX_IIR(pipe);
2928 temp = I915_READ(reg);
2929 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2931 if (temp & FDI_RX_SYMBOL_LOCK ||
2932 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2933 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2934 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2938 udelay(2); /* should be 1.5us */
2941 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2945 DRM_DEBUG_KMS("FDI train done.\n");
2948 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2950 struct drm_device *dev = intel_crtc->base.dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 int pipe = intel_crtc->pipe;
2956 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2957 reg = FDI_RX_CTL(pipe);
2958 temp = I915_READ(reg);
2959 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2960 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2961 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2962 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2967 /* Switch from Rawclk to PCDclk */
2968 temp = I915_READ(reg);
2969 I915_WRITE(reg, temp | FDI_PCDCLK);
2974 /* Enable CPU FDI TX PLL, always on for Ironlake */
2975 reg = FDI_TX_CTL(pipe);
2976 temp = I915_READ(reg);
2977 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2978 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2985 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2987 struct drm_device *dev = intel_crtc->base.dev;
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 int pipe = intel_crtc->pipe;
2992 /* Switch from PCDclk to Rawclk */
2993 reg = FDI_RX_CTL(pipe);
2994 temp = I915_READ(reg);
2995 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2997 /* Disable CPU FDI TX PLL */
2998 reg = FDI_TX_CTL(pipe);
2999 temp = I915_READ(reg);
3000 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3005 reg = FDI_RX_CTL(pipe);
3006 temp = I915_READ(reg);
3007 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3009 /* Wait for the clocks to turn off. */
3014 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3016 struct drm_device *dev = crtc->dev;
3017 struct drm_i915_private *dev_priv = dev->dev_private;
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019 int pipe = intel_crtc->pipe;
3022 /* disable CPU FDI tx and PCH FDI rx */
3023 reg = FDI_TX_CTL(pipe);
3024 temp = I915_READ(reg);
3025 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3028 reg = FDI_RX_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~(0x7 << 16);
3031 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3032 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3037 /* Ironlake workaround, disable clock pointer after downing FDI */
3038 if (HAS_PCH_IBX(dev)) {
3039 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3042 /* still set train pattern 1 */
3043 reg = FDI_TX_CTL(pipe);
3044 temp = I915_READ(reg);
3045 temp &= ~FDI_LINK_TRAIN_NONE;
3046 temp |= FDI_LINK_TRAIN_PATTERN_1;
3047 I915_WRITE(reg, temp);
3049 reg = FDI_RX_CTL(pipe);
3050 temp = I915_READ(reg);
3051 if (HAS_PCH_CPT(dev)) {
3052 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3053 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3055 temp &= ~FDI_LINK_TRAIN_NONE;
3056 temp |= FDI_LINK_TRAIN_PATTERN_1;
3058 /* BPC in FDI rx is consistent with that in PIPECONF */
3059 temp &= ~(0x07 << 16);
3060 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3061 I915_WRITE(reg, temp);
3067 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3069 struct intel_crtc *crtc;
3071 /* Note that we don't need to be called with mode_config.lock here
3072 * as our list of CRTC objects is static for the lifetime of the
3073 * device and so cannot disappear as we iterate. Similarly, we can
3074 * happily treat the predicates as racy, atomic checks as userspace
3075 * cannot claim and pin a new fb without at least acquring the
3076 * struct_mutex and so serialising with us.
3078 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3079 if (atomic_read(&crtc->unpin_work_count) == 0)
3082 if (crtc->unpin_work)
3083 intel_wait_for_vblank(dev, crtc->pipe);
3091 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3096 if (crtc->primary->fb == NULL)
3099 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3101 wait_event(dev_priv->pending_flip_queue,
3102 !intel_crtc_has_pending_flip(crtc));
3104 mutex_lock(&dev->struct_mutex);
3105 intel_finish_fb(crtc->primary->fb);
3106 mutex_unlock(&dev->struct_mutex);
3109 /* Program iCLKIP clock to the desired frequency */
3110 static void lpt_program_iclkip(struct drm_crtc *crtc)
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3115 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3118 mutex_lock(&dev_priv->dpio_lock);
3120 /* It is necessary to ungate the pixclk gate prior to programming
3121 * the divisors, and gate it back when it is done.
3123 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3125 /* Disable SSCCTL */
3126 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3127 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3131 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3132 if (clock == 20000) {
3137 /* The iCLK virtual clock root frequency is in MHz,
3138 * but the adjusted_mode->crtc_clock in in KHz. To get the
3139 * divisors, it is necessary to divide one by another, so we
3140 * convert the virtual clock precision to KHz here for higher
3143 u32 iclk_virtual_root_freq = 172800 * 1000;
3144 u32 iclk_pi_range = 64;
3145 u32 desired_divisor, msb_divisor_value, pi_value;
3147 desired_divisor = (iclk_virtual_root_freq / clock);
3148 msb_divisor_value = desired_divisor / iclk_pi_range;
3149 pi_value = desired_divisor % iclk_pi_range;
3152 divsel = msb_divisor_value - 2;
3153 phaseinc = pi_value;
3156 /* This should not happen with any sane values */
3157 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3158 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3159 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3160 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3162 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3169 /* Program SSCDIVINTPHASE6 */
3170 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3171 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3172 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3173 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3174 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3175 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3176 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3177 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3179 /* Program SSCAUXDIV */
3180 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3181 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3182 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3183 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3185 /* Enable modulator and associated divider */
3186 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3187 temp &= ~SBI_SSCCTL_DISABLE;
3188 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3190 /* Wait for initialization time */
3193 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3195 mutex_unlock(&dev_priv->dpio_lock);
3198 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3199 enum pipe pch_transcoder)
3201 struct drm_device *dev = crtc->base.dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3205 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3206 I915_READ(HTOTAL(cpu_transcoder)));
3207 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3208 I915_READ(HBLANK(cpu_transcoder)));
3209 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3210 I915_READ(HSYNC(cpu_transcoder)));
3212 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3213 I915_READ(VTOTAL(cpu_transcoder)));
3214 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3215 I915_READ(VBLANK(cpu_transcoder)));
3216 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3217 I915_READ(VSYNC(cpu_transcoder)));
3218 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3219 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3222 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3227 temp = I915_READ(SOUTH_CHICKEN1);
3228 if (temp & FDI_BC_BIFURCATION_SELECT)
3231 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3232 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3234 temp |= FDI_BC_BIFURCATION_SELECT;
3235 DRM_DEBUG_KMS("enabling fdi C rx\n");
3236 I915_WRITE(SOUTH_CHICKEN1, temp);
3237 POSTING_READ(SOUTH_CHICKEN1);
3240 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3242 struct drm_device *dev = intel_crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3245 switch (intel_crtc->pipe) {
3249 if (intel_crtc->config.fdi_lanes > 2)
3250 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3252 cpt_enable_fdi_bc_bifurcation(dev);
3256 cpt_enable_fdi_bc_bifurcation(dev);
3265 * Enable PCH resources required for PCH ports:
3267 * - FDI training & RX/TX
3268 * - update transcoder timings
3269 * - DP transcoding bits
3272 static void ironlake_pch_enable(struct drm_crtc *crtc)
3274 struct drm_device *dev = crtc->dev;
3275 struct drm_i915_private *dev_priv = dev->dev_private;
3276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277 int pipe = intel_crtc->pipe;
3280 assert_pch_transcoder_disabled(dev_priv, pipe);
3282 if (IS_IVYBRIDGE(dev))
3283 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3285 /* Write the TU size bits before fdi link training, so that error
3286 * detection works. */
3287 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3288 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3290 /* For PCH output, training FDI link */
3291 dev_priv->display.fdi_link_train(crtc);
3293 /* We need to program the right clock selection before writing the pixel
3294 * mutliplier into the DPLL. */
3295 if (HAS_PCH_CPT(dev)) {
3298 temp = I915_READ(PCH_DPLL_SEL);
3299 temp |= TRANS_DPLL_ENABLE(pipe);
3300 sel = TRANS_DPLLB_SEL(pipe);
3301 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3305 I915_WRITE(PCH_DPLL_SEL, temp);
3308 /* XXX: pch pll's can be enabled any time before we enable the PCH
3309 * transcoder, and we actually should do this to not upset any PCH
3310 * transcoder that already use the clock when we share it.
3312 * Note that enable_shared_dpll tries to do the right thing, but
3313 * get_shared_dpll unconditionally resets the pll - we need that to have
3314 * the right LVDS enable sequence. */
3315 ironlake_enable_shared_dpll(intel_crtc);
3317 /* set transcoder timing, panel must allow it */
3318 assert_panel_unlocked(dev_priv, pipe);
3319 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3321 intel_fdi_normal_train(crtc);
3323 /* For PCH DP, enable TRANS_DP_CTL */
3324 if (HAS_PCH_CPT(dev) &&
3325 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3326 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3327 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3328 reg = TRANS_DP_CTL(pipe);
3329 temp = I915_READ(reg);
3330 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3331 TRANS_DP_SYNC_MASK |
3333 temp |= (TRANS_DP_OUTPUT_ENABLE |
3334 TRANS_DP_ENH_FRAMING);
3335 temp |= bpc << 9; /* same format but at 11:9 */
3337 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3338 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3339 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3340 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3342 switch (intel_trans_dp_port_sel(crtc)) {
3344 temp |= TRANS_DP_PORT_SEL_B;
3347 temp |= TRANS_DP_PORT_SEL_C;
3350 temp |= TRANS_DP_PORT_SEL_D;
3356 I915_WRITE(reg, temp);
3359 ironlake_enable_pch_transcoder(dev_priv, pipe);
3362 static void lpt_pch_enable(struct drm_crtc *crtc)
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3369 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3371 lpt_program_iclkip(crtc);
3373 /* Set transcoder timing. */
3374 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3376 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3379 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3381 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3386 if (pll->refcount == 0) {
3387 WARN(1, "bad %s refcount\n", pll->name);
3391 if (--pll->refcount == 0) {
3393 WARN_ON(pll->active);
3396 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3399 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3401 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3402 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3403 enum intel_dpll_id i;
3406 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3407 crtc->base.base.id, pll->name);
3408 intel_put_shared_dpll(crtc);
3411 if (HAS_PCH_IBX(dev_priv->dev)) {
3412 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3413 i = (enum intel_dpll_id) crtc->pipe;
3414 pll = &dev_priv->shared_dplls[i];
3416 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3417 crtc->base.base.id, pll->name);
3422 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3423 pll = &dev_priv->shared_dplls[i];
3425 /* Only want to check enabled timings first */
3426 if (pll->refcount == 0)
3429 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3430 sizeof(pll->hw_state)) == 0) {
3431 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3433 pll->name, pll->refcount, pll->active);
3439 /* Ok no matching timings, maybe there's a free one? */
3440 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3441 pll = &dev_priv->shared_dplls[i];
3442 if (pll->refcount == 0) {
3443 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3444 crtc->base.base.id, pll->name);
3452 crtc->config.shared_dpll = i;
3453 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3454 pipe_name(crtc->pipe));
3456 if (pll->active == 0) {
3457 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3458 sizeof(pll->hw_state));
3460 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3462 assert_shared_dpll_disabled(dev_priv, pll);
3464 pll->mode_set(dev_priv, pll);
3471 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474 int dslreg = PIPEDSL(pipe);
3477 temp = I915_READ(dslreg);
3479 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3480 if (wait_for(I915_READ(dslreg) != temp, 5))
3481 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3485 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3487 struct drm_device *dev = crtc->base.dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 int pipe = crtc->pipe;
3491 if (crtc->config.pch_pfit.enabled) {
3492 /* Force use of hard-coded filter coefficients
3493 * as some pre-programmed values are broken,
3496 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3497 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3498 PF_PIPE_SEL_IVB(pipe));
3500 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3501 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3502 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3506 static void intel_enable_planes(struct drm_crtc *crtc)
3508 struct drm_device *dev = crtc->dev;
3509 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3510 struct drm_plane *plane;
3511 struct intel_plane *intel_plane;
3513 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3514 intel_plane = to_intel_plane(plane);
3515 if (intel_plane->pipe == pipe)
3516 intel_plane_restore(&intel_plane->base);
3520 static void intel_disable_planes(struct drm_crtc *crtc)
3522 struct drm_device *dev = crtc->dev;
3523 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3524 struct drm_plane *plane;
3525 struct intel_plane *intel_plane;
3527 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3528 intel_plane = to_intel_plane(plane);
3529 if (intel_plane->pipe == pipe)
3530 intel_plane_disable(&intel_plane->base);
3534 void hsw_enable_ips(struct intel_crtc *crtc)
3536 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3538 if (!crtc->config.ips_enabled)
3541 /* We can only enable IPS after we enable a plane and wait for a vblank.
3542 * We guarantee that the plane is enabled by calling intel_enable_ips
3543 * only after intel_enable_plane. And intel_enable_plane already waits
3544 * for a vblank, so all we need to do here is to enable the IPS bit. */
3545 assert_plane_enabled(dev_priv, crtc->plane);
3546 if (IS_BROADWELL(crtc->base.dev)) {
3547 mutex_lock(&dev_priv->rps.hw_lock);
3548 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3549 mutex_unlock(&dev_priv->rps.hw_lock);
3550 /* Quoting Art Runyan: "its not safe to expect any particular
3551 * value in IPS_CTL bit 31 after enabling IPS through the
3552 * mailbox." Moreover, the mailbox may return a bogus state,
3553 * so we need to just enable it and continue on.
3556 I915_WRITE(IPS_CTL, IPS_ENABLE);
3557 /* The bit only becomes 1 in the next vblank, so this wait here
3558 * is essentially intel_wait_for_vblank. If we don't have this
3559 * and don't wait for vblanks until the end of crtc_enable, then
3560 * the HW state readout code will complain that the expected
3561 * IPS_CTL value is not the one we read. */
3562 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3563 DRM_ERROR("Timed out waiting for IPS enable\n");
3567 void hsw_disable_ips(struct intel_crtc *crtc)
3569 struct drm_device *dev = crtc->base.dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3572 if (!crtc->config.ips_enabled)
3575 assert_plane_enabled(dev_priv, crtc->plane);
3576 if (IS_BROADWELL(dev)) {
3577 mutex_lock(&dev_priv->rps.hw_lock);
3578 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3579 mutex_unlock(&dev_priv->rps.hw_lock);
3580 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3581 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3582 DRM_ERROR("Timed out waiting for IPS disable\n");
3584 I915_WRITE(IPS_CTL, 0);
3585 POSTING_READ(IPS_CTL);
3588 /* We need to wait for a vblank before we can disable the plane. */
3589 intel_wait_for_vblank(dev, crtc->pipe);
3592 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3593 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3595 struct drm_device *dev = crtc->dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598 enum pipe pipe = intel_crtc->pipe;
3599 int palreg = PALETTE(pipe);
3601 bool reenable_ips = false;
3603 /* The clocks have to be on to load the palette. */
3604 if (!crtc->enabled || !intel_crtc->active)
3607 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3608 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3609 assert_dsi_pll_enabled(dev_priv);
3611 assert_pll_enabled(dev_priv, pipe);
3614 /* use legacy palette for Ironlake */
3615 if (HAS_PCH_SPLIT(dev))
3616 palreg = LGC_PALETTE(pipe);
3618 /* Workaround : Do not read or write the pipe palette/gamma data while
3619 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3621 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3622 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3623 GAMMA_MODE_MODE_SPLIT)) {
3624 hsw_disable_ips(intel_crtc);
3625 reenable_ips = true;
3628 for (i = 0; i < 256; i++) {
3629 I915_WRITE(palreg + 4 * i,
3630 (intel_crtc->lut_r[i] << 16) |
3631 (intel_crtc->lut_g[i] << 8) |
3632 intel_crtc->lut_b[i]);
3636 hsw_enable_ips(intel_crtc);
3639 static void ilk_crtc_enable_planes(struct drm_crtc *crtc)
3641 struct drm_device *dev = crtc->dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 int pipe = intel_crtc->pipe;
3645 int plane = intel_crtc->plane;
3647 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3648 intel_enable_planes(crtc);
3649 intel_crtc_update_cursor(crtc, true);
3651 hsw_enable_ips(intel_crtc);
3653 mutex_lock(&dev->struct_mutex);
3654 intel_update_fbc(dev);
3655 mutex_unlock(&dev->struct_mutex);
3658 static void ilk_crtc_disable_planes(struct drm_crtc *crtc)
3660 struct drm_device *dev = crtc->dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663 int pipe = intel_crtc->pipe;
3664 int plane = intel_crtc->plane;
3666 intel_crtc_wait_for_pending_flips(crtc);
3667 drm_vblank_off(dev, pipe);
3669 if (dev_priv->fbc.plane == plane)
3670 intel_disable_fbc(dev);
3672 hsw_disable_ips(intel_crtc);
3674 intel_crtc_update_cursor(crtc, false);
3675 intel_disable_planes(crtc);
3676 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3679 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3681 struct drm_device *dev = crtc->dev;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684 struct intel_encoder *encoder;
3685 int pipe = intel_crtc->pipe;
3687 WARN_ON(!crtc->enabled);
3689 if (intel_crtc->active)
3692 intel_crtc->active = true;
3694 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3695 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3701 if (intel_crtc->config.has_pch_encoder) {
3702 /* Note: FDI PLL enabling _must_ be done before we enable the
3703 * cpu pipes, hence this is separate from all the other fdi/pch
3705 ironlake_fdi_pll_enable(intel_crtc);
3707 assert_fdi_tx_disabled(dev_priv, pipe);
3708 assert_fdi_rx_disabled(dev_priv, pipe);
3711 ironlake_pfit_enable(intel_crtc);
3714 * On ILK+ LUT must be loaded before the pipe is running but with
3717 intel_crtc_load_lut(crtc);
3719 intel_update_watermarks(crtc);
3720 intel_enable_pipe(intel_crtc);
3722 if (intel_crtc->config.has_pch_encoder)
3723 ironlake_pch_enable(crtc);
3725 for_each_encoder_on_crtc(dev, crtc, encoder)
3726 encoder->enable(encoder);
3728 if (HAS_PCH_CPT(dev))
3729 cpt_verify_modeset(dev, intel_crtc->pipe);
3731 ilk_crtc_enable_planes(crtc);
3734 * There seems to be a race in PCH platform hw (at least on some
3735 * outputs) where an enabled pipe still completes any pageflip right
3736 * away (as if the pipe is off) instead of waiting for vblank. As soon
3737 * as the first vblank happend, everything works as expected. Hence just
3738 * wait for one vblank before returning to avoid strange things
3741 intel_wait_for_vblank(dev, intel_crtc->pipe);
3744 /* IPS only exists on ULT machines and is tied to pipe A. */
3745 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3747 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3751 * This implements the workaround described in the "notes" section of the mode
3752 * set sequence documentation. When going from no pipes or single pipe to
3753 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3754 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3756 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3758 struct drm_device *dev = crtc->base.dev;
3759 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3761 /* We want to get the other_active_crtc only if there's only 1 other
3763 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3764 if (!crtc_it->active || crtc_it == crtc)
3767 if (other_active_crtc)
3770 other_active_crtc = crtc_it;
3772 if (!other_active_crtc)
3775 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3776 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3779 static void haswell_crtc_enable(struct drm_crtc *crtc)
3781 struct drm_device *dev = crtc->dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3784 struct intel_encoder *encoder;
3785 int pipe = intel_crtc->pipe;
3787 WARN_ON(!crtc->enabled);
3789 if (intel_crtc->active)
3792 intel_crtc->active = true;
3794 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3795 if (intel_crtc->config.has_pch_encoder)
3796 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3798 if (intel_crtc->config.has_pch_encoder)
3799 dev_priv->display.fdi_link_train(crtc);
3801 for_each_encoder_on_crtc(dev, crtc, encoder)
3802 if (encoder->pre_enable)
3803 encoder->pre_enable(encoder);
3805 intel_ddi_enable_pipe_clock(intel_crtc);
3807 ironlake_pfit_enable(intel_crtc);
3810 * On ILK+ LUT must be loaded before the pipe is running but with
3813 intel_crtc_load_lut(crtc);
3815 intel_ddi_set_pipe_settings(crtc);
3816 intel_ddi_enable_transcoder_func(crtc);
3818 intel_update_watermarks(crtc);
3819 intel_enable_pipe(intel_crtc);
3821 if (intel_crtc->config.has_pch_encoder)
3822 lpt_pch_enable(crtc);
3824 for_each_encoder_on_crtc(dev, crtc, encoder) {
3825 encoder->enable(encoder);
3826 intel_opregion_notify_encoder(encoder, true);
3829 /* If we change the relative order between pipe/planes enabling, we need
3830 * to change the workaround. */
3831 haswell_mode_set_planes_workaround(intel_crtc);
3832 ilk_crtc_enable_planes(crtc);
3835 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3837 struct drm_device *dev = crtc->base.dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 int pipe = crtc->pipe;
3841 /* To avoid upsetting the power well on haswell only disable the pfit if
3842 * it's in use. The hw state code will make sure we get this right. */
3843 if (crtc->config.pch_pfit.enabled) {
3844 I915_WRITE(PF_CTL(pipe), 0);
3845 I915_WRITE(PF_WIN_POS(pipe), 0);
3846 I915_WRITE(PF_WIN_SZ(pipe), 0);
3850 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3852 struct drm_device *dev = crtc->dev;
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3855 struct intel_encoder *encoder;
3856 int pipe = intel_crtc->pipe;
3859 if (!intel_crtc->active)
3862 ilk_crtc_disable_planes(crtc);
3864 for_each_encoder_on_crtc(dev, crtc, encoder)
3865 encoder->disable(encoder);
3867 if (intel_crtc->config.has_pch_encoder)
3868 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3870 intel_disable_pipe(dev_priv, pipe);
3872 ironlake_pfit_disable(intel_crtc);
3874 for_each_encoder_on_crtc(dev, crtc, encoder)
3875 if (encoder->post_disable)
3876 encoder->post_disable(encoder);
3878 if (intel_crtc->config.has_pch_encoder) {
3879 ironlake_fdi_disable(crtc);
3881 ironlake_disable_pch_transcoder(dev_priv, pipe);
3882 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3884 if (HAS_PCH_CPT(dev)) {
3885 /* disable TRANS_DP_CTL */
3886 reg = TRANS_DP_CTL(pipe);
3887 temp = I915_READ(reg);
3888 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3889 TRANS_DP_PORT_SEL_MASK);
3890 temp |= TRANS_DP_PORT_SEL_NONE;
3891 I915_WRITE(reg, temp);
3893 /* disable DPLL_SEL */
3894 temp = I915_READ(PCH_DPLL_SEL);
3895 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3896 I915_WRITE(PCH_DPLL_SEL, temp);
3899 /* disable PCH DPLL */
3900 intel_disable_shared_dpll(intel_crtc);
3902 ironlake_fdi_pll_disable(intel_crtc);
3905 intel_crtc->active = false;
3906 intel_update_watermarks(crtc);
3908 mutex_lock(&dev->struct_mutex);
3909 intel_update_fbc(dev);
3910 mutex_unlock(&dev->struct_mutex);
3913 static void haswell_crtc_disable(struct drm_crtc *crtc)
3915 struct drm_device *dev = crtc->dev;
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3918 struct intel_encoder *encoder;
3919 int pipe = intel_crtc->pipe;
3920 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3922 if (!intel_crtc->active)
3925 ilk_crtc_disable_planes(crtc);
3927 for_each_encoder_on_crtc(dev, crtc, encoder) {
3928 intel_opregion_notify_encoder(encoder, false);
3929 encoder->disable(encoder);
3932 if (intel_crtc->config.has_pch_encoder)
3933 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3934 intel_disable_pipe(dev_priv, pipe);
3936 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3938 ironlake_pfit_disable(intel_crtc);
3940 intel_ddi_disable_pipe_clock(intel_crtc);
3942 for_each_encoder_on_crtc(dev, crtc, encoder)
3943 if (encoder->post_disable)
3944 encoder->post_disable(encoder);
3946 if (intel_crtc->config.has_pch_encoder) {
3947 lpt_disable_pch_transcoder(dev_priv);
3948 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3949 intel_ddi_fdi_disable(crtc);
3952 intel_crtc->active = false;
3953 intel_update_watermarks(crtc);
3955 mutex_lock(&dev->struct_mutex);
3956 intel_update_fbc(dev);
3957 mutex_unlock(&dev->struct_mutex);
3960 static void ironlake_crtc_off(struct drm_crtc *crtc)
3962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3963 intel_put_shared_dpll(intel_crtc);
3966 static void haswell_crtc_off(struct drm_crtc *crtc)
3968 intel_ddi_put_crtc_pll(crtc);
3971 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3973 if (!enable && intel_crtc->overlay) {
3974 struct drm_device *dev = intel_crtc->base.dev;
3975 struct drm_i915_private *dev_priv = dev->dev_private;
3977 mutex_lock(&dev->struct_mutex);
3978 dev_priv->mm.interruptible = false;
3979 (void) intel_overlay_switch_off(intel_crtc->overlay);
3980 dev_priv->mm.interruptible = true;
3981 mutex_unlock(&dev->struct_mutex);
3984 /* Let userspace switch the overlay on again. In most cases userspace
3985 * has to recompute where to put it anyway.
3990 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3991 * cursor plane briefly if not already running after enabling the display
3993 * This workaround avoids occasional blank screens when self refresh is
3997 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3999 u32 cntl = I915_READ(CURCNTR(pipe));
4001 if ((cntl & CURSOR_MODE) == 0) {
4002 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
4004 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
4005 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
4006 intel_wait_for_vblank(dev_priv->dev, pipe);
4007 I915_WRITE(CURCNTR(pipe), cntl);
4008 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
4009 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
4013 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4015 struct drm_device *dev = crtc->base.dev;
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 struct intel_crtc_config *pipe_config = &crtc->config;
4019 if (!crtc->config.gmch_pfit.control)
4023 * The panel fitter should only be adjusted whilst the pipe is disabled,
4024 * according to register description and PRM.
4026 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4027 assert_pipe_disabled(dev_priv, crtc->pipe);
4029 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4030 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4032 /* Border color in case we don't scale up to the full screen. Black by
4033 * default, change to something else for debugging. */
4034 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4037 #define for_each_power_domain(domain, mask) \
4038 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4039 if ((1 << (domain)) & (mask))
4041 enum intel_display_power_domain
4042 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4044 struct drm_device *dev = intel_encoder->base.dev;
4045 struct intel_digital_port *intel_dig_port;
4047 switch (intel_encoder->type) {
4048 case INTEL_OUTPUT_UNKNOWN:
4049 /* Only DDI platforms should ever use this output type */
4050 WARN_ON_ONCE(!HAS_DDI(dev));
4051 case INTEL_OUTPUT_DISPLAYPORT:
4052 case INTEL_OUTPUT_HDMI:
4053 case INTEL_OUTPUT_EDP:
4054 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4055 switch (intel_dig_port->port) {
4057 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4059 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4061 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4063 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4066 return POWER_DOMAIN_PORT_OTHER;
4068 case INTEL_OUTPUT_ANALOG:
4069 return POWER_DOMAIN_PORT_CRT;
4070 case INTEL_OUTPUT_DSI:
4071 return POWER_DOMAIN_PORT_DSI;
4073 return POWER_DOMAIN_PORT_OTHER;
4077 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4079 struct drm_device *dev = crtc->dev;
4080 struct intel_encoder *intel_encoder;
4081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4082 enum pipe pipe = intel_crtc->pipe;
4083 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4085 enum transcoder transcoder;
4087 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4089 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4090 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4092 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4094 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4095 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4100 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4103 if (dev_priv->power_domains.init_power_on == enable)
4107 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4109 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4111 dev_priv->power_domains.init_power_on = enable;
4114 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4118 struct intel_crtc *crtc;
4121 * First get all needed power domains, then put all unneeded, to avoid
4122 * any unnecessary toggling of the power wells.
4124 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4125 enum intel_display_power_domain domain;
4127 if (!crtc->base.enabled)
4130 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4132 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4133 intel_display_power_get(dev_priv, domain);
4136 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
4137 enum intel_display_power_domain domain;
4139 for_each_power_domain(domain, crtc->enabled_power_domains)
4140 intel_display_power_put(dev_priv, domain);
4142 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4145 intel_display_set_init_power(dev_priv, false);
4148 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4150 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4152 /* Obtain SKU information */
4153 mutex_lock(&dev_priv->dpio_lock);
4154 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4155 CCK_FUSE_HPLL_FREQ_MASK;
4156 mutex_unlock(&dev_priv->dpio_lock);
4158 return vco_freq[hpll_freq];
4161 /* Adjust CDclk dividers to allow high res or save power if possible */
4162 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4167 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4168 dev_priv->vlv_cdclk_freq = cdclk;
4170 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4172 else if (cdclk == 266)
4177 mutex_lock(&dev_priv->rps.hw_lock);
4178 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4179 val &= ~DSPFREQGUAR_MASK;
4180 val |= (cmd << DSPFREQGUAR_SHIFT);
4181 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4182 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4183 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4185 DRM_ERROR("timed out waiting for CDclk change\n");
4187 mutex_unlock(&dev_priv->rps.hw_lock);
4192 vco = valleyview_get_vco(dev_priv);
4193 divider = ((vco << 1) / cdclk) - 1;
4195 mutex_lock(&dev_priv->dpio_lock);
4196 /* adjust cdclk divider */
4197 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4200 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4201 mutex_unlock(&dev_priv->dpio_lock);
4204 mutex_lock(&dev_priv->dpio_lock);
4205 /* adjust self-refresh exit latency value */
4206 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4210 * For high bandwidth configs, we set a higher latency in the bunit
4211 * so that the core display fetch happens in time to avoid underruns.
4214 val |= 4500 / 250; /* 4.5 usec */
4216 val |= 3000 / 250; /* 3.0 usec */
4217 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4218 mutex_unlock(&dev_priv->dpio_lock);
4220 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4221 intel_i2c_reset(dev);
4224 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4229 vco = valleyview_get_vco(dev_priv);
4231 mutex_lock(&dev_priv->dpio_lock);
4232 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4233 mutex_unlock(&dev_priv->dpio_lock);
4237 cur_cdclk = (vco << 1) / (divider + 1);
4242 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4246 * Really only a few cases to deal with, as only 4 CDclks are supported:
4251 * So we check to see whether we're above 90% of the lower bin and
4254 if (max_pixclk > 288000) {
4256 } else if (max_pixclk > 240000) {
4260 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4263 /* compute the max pixel clock for new configuration */
4264 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4266 struct drm_device *dev = dev_priv->dev;
4267 struct intel_crtc *intel_crtc;
4270 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4272 if (intel_crtc->new_enabled)
4273 max_pixclk = max(max_pixclk,
4274 intel_crtc->new_config->adjusted_mode.crtc_clock);
4280 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4281 unsigned *prepare_pipes)
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc;
4285 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4287 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4288 dev_priv->vlv_cdclk_freq)
4291 /* disable/enable all currently active pipes while we change cdclk */
4292 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4294 if (intel_crtc->base.enabled)
4295 *prepare_pipes |= (1 << intel_crtc->pipe);
4298 static void valleyview_modeset_global_resources(struct drm_device *dev)
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4302 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4304 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4305 valleyview_set_cdclk(dev, req_cdclk);
4306 modeset_update_crtc_power_domains(dev);
4309 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314 struct intel_encoder *encoder;
4315 int pipe = intel_crtc->pipe;
4316 int plane = intel_crtc->plane;
4319 WARN_ON(!crtc->enabled);
4321 if (intel_crtc->active)
4324 intel_crtc->active = true;
4326 for_each_encoder_on_crtc(dev, crtc, encoder)
4327 if (encoder->pre_pll_enable)
4328 encoder->pre_pll_enable(encoder);
4330 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4333 vlv_enable_pll(intel_crtc);
4335 for_each_encoder_on_crtc(dev, crtc, encoder)
4336 if (encoder->pre_enable)
4337 encoder->pre_enable(encoder);
4339 i9xx_pfit_enable(intel_crtc);
4341 intel_crtc_load_lut(crtc);
4343 intel_update_watermarks(crtc);
4344 intel_enable_pipe(intel_crtc);
4345 intel_wait_for_vblank(dev_priv->dev, pipe);
4346 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4348 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4349 intel_enable_planes(crtc);
4350 intel_crtc_update_cursor(crtc, true);
4352 intel_update_fbc(dev);
4354 for_each_encoder_on_crtc(dev, crtc, encoder)
4355 encoder->enable(encoder);
4358 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4360 struct drm_device *dev = crtc->dev;
4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4363 struct intel_encoder *encoder;
4364 int pipe = intel_crtc->pipe;
4365 int plane = intel_crtc->plane;
4367 WARN_ON(!crtc->enabled);
4369 if (intel_crtc->active)
4372 intel_crtc->active = true;
4374 for_each_encoder_on_crtc(dev, crtc, encoder)
4375 if (encoder->pre_enable)
4376 encoder->pre_enable(encoder);
4378 i9xx_enable_pll(intel_crtc);
4380 i9xx_pfit_enable(intel_crtc);
4382 intel_crtc_load_lut(crtc);
4384 intel_update_watermarks(crtc);
4385 intel_enable_pipe(intel_crtc);
4386 intel_wait_for_vblank(dev_priv->dev, pipe);
4387 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4389 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
4390 intel_enable_planes(crtc);
4391 /* The fixup needs to happen before cursor is enabled */
4393 g4x_fixup_plane(dev_priv, pipe);
4394 intel_crtc_update_cursor(crtc, true);
4396 /* Give the overlay scaler a chance to enable if it's on this pipe */
4397 intel_crtc_dpms_overlay(intel_crtc, true);
4399 intel_update_fbc(dev);
4401 for_each_encoder_on_crtc(dev, crtc, encoder)
4402 encoder->enable(encoder);
4405 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4407 struct drm_device *dev = crtc->base.dev;
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4410 if (!crtc->config.gmch_pfit.control)
4413 assert_pipe_disabled(dev_priv, crtc->pipe);
4415 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4416 I915_READ(PFIT_CONTROL));
4417 I915_WRITE(PFIT_CONTROL, 0);
4420 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4422 struct drm_device *dev = crtc->dev;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4425 struct intel_encoder *encoder;
4426 int pipe = intel_crtc->pipe;
4427 int plane = intel_crtc->plane;
4429 if (!intel_crtc->active)
4432 for_each_encoder_on_crtc(dev, crtc, encoder)
4433 encoder->disable(encoder);
4435 /* Give the overlay scaler a chance to disable if it's on this pipe */
4436 intel_crtc_wait_for_pending_flips(crtc);
4437 drm_vblank_off(dev, pipe);
4439 if (dev_priv->fbc.plane == plane)
4440 intel_disable_fbc(dev);
4442 intel_crtc_dpms_overlay(intel_crtc, false);
4443 intel_crtc_update_cursor(crtc, false);
4444 intel_disable_planes(crtc);
4445 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
4447 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4448 intel_disable_pipe(dev_priv, pipe);
4450 i9xx_pfit_disable(intel_crtc);
4452 for_each_encoder_on_crtc(dev, crtc, encoder)
4453 if (encoder->post_disable)
4454 encoder->post_disable(encoder);
4456 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4457 vlv_disable_pll(dev_priv, pipe);
4458 else if (!IS_VALLEYVIEW(dev))
4459 i9xx_disable_pll(dev_priv, pipe);
4461 intel_crtc->active = false;
4462 intel_update_watermarks(crtc);
4464 intel_update_fbc(dev);
4467 static void i9xx_crtc_off(struct drm_crtc *crtc)
4471 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4474 struct drm_device *dev = crtc->dev;
4475 struct drm_i915_master_private *master_priv;
4476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4477 int pipe = intel_crtc->pipe;
4479 if (!dev->primary->master)
4482 master_priv = dev->primary->master->driver_priv;
4483 if (!master_priv->sarea_priv)
4488 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4489 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4492 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4493 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4496 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4502 * Sets the power management mode of the pipe and plane.
4504 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_encoder *intel_encoder;
4509 bool enable = false;
4511 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4512 enable |= intel_encoder->connectors_active;
4515 dev_priv->display.crtc_enable(crtc);
4517 dev_priv->display.crtc_disable(crtc);
4519 intel_crtc_update_sarea(crtc, enable);
4522 static void intel_crtc_disable(struct drm_crtc *crtc)
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_connector *connector;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4529 /* crtc should still be enabled when we disable it. */
4530 WARN_ON(!crtc->enabled);
4532 dev_priv->display.crtc_disable(crtc);
4533 intel_crtc->eld_vld = false;
4534 intel_crtc_update_sarea(crtc, false);
4535 dev_priv->display.off(crtc);
4537 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4538 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4539 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4541 if (crtc->primary->fb) {
4542 mutex_lock(&dev->struct_mutex);
4543 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4544 mutex_unlock(&dev->struct_mutex);
4545 crtc->primary->fb = NULL;
4548 /* Update computed state. */
4549 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4550 if (!connector->encoder || !connector->encoder->crtc)
4553 if (connector->encoder->crtc != crtc)
4556 connector->dpms = DRM_MODE_DPMS_OFF;
4557 to_intel_encoder(connector->encoder)->connectors_active = false;
4561 void intel_encoder_destroy(struct drm_encoder *encoder)
4563 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4565 drm_encoder_cleanup(encoder);
4566 kfree(intel_encoder);
4569 /* Simple dpms helper for encoders with just one connector, no cloning and only
4570 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4571 * state of the entire output pipe. */
4572 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4574 if (mode == DRM_MODE_DPMS_ON) {
4575 encoder->connectors_active = true;
4577 intel_crtc_update_dpms(encoder->base.crtc);
4579 encoder->connectors_active = false;
4581 intel_crtc_update_dpms(encoder->base.crtc);
4585 /* Cross check the actual hw state with our own modeset state tracking (and it's
4586 * internal consistency). */
4587 static void intel_connector_check_state(struct intel_connector *connector)
4589 if (connector->get_hw_state(connector)) {
4590 struct intel_encoder *encoder = connector->encoder;
4591 struct drm_crtc *crtc;
4592 bool encoder_enabled;
4595 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4596 connector->base.base.id,
4597 drm_get_connector_name(&connector->base));
4599 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4600 "wrong connector dpms state\n");
4601 WARN(connector->base.encoder != &encoder->base,
4602 "active connector not linked to encoder\n");
4603 WARN(!encoder->connectors_active,
4604 "encoder->connectors_active not set\n");
4606 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4607 WARN(!encoder_enabled, "encoder not enabled\n");
4608 if (WARN_ON(!encoder->base.crtc))
4611 crtc = encoder->base.crtc;
4613 WARN(!crtc->enabled, "crtc not enabled\n");
4614 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4615 WARN(pipe != to_intel_crtc(crtc)->pipe,
4616 "encoder active on the wrong pipe\n");
4620 /* Even simpler default implementation, if there's really no special case to
4622 void intel_connector_dpms(struct drm_connector *connector, int mode)
4624 /* All the simple cases only support two dpms states. */
4625 if (mode != DRM_MODE_DPMS_ON)
4626 mode = DRM_MODE_DPMS_OFF;
4628 if (mode == connector->dpms)
4631 connector->dpms = mode;
4633 /* Only need to change hw state when actually enabled */
4634 if (connector->encoder)
4635 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4637 intel_modeset_check_state(connector->dev);
4640 /* Simple connector->get_hw_state implementation for encoders that support only
4641 * one connector and no cloning and hence the encoder state determines the state
4642 * of the connector. */
4643 bool intel_connector_get_hw_state(struct intel_connector *connector)
4646 struct intel_encoder *encoder = connector->encoder;
4648 return encoder->get_hw_state(encoder, &pipe);
4651 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4652 struct intel_crtc_config *pipe_config)
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655 struct intel_crtc *pipe_B_crtc =
4656 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4658 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4659 pipe_name(pipe), pipe_config->fdi_lanes);
4660 if (pipe_config->fdi_lanes > 4) {
4661 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4662 pipe_name(pipe), pipe_config->fdi_lanes);
4666 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4667 if (pipe_config->fdi_lanes > 2) {
4668 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4669 pipe_config->fdi_lanes);
4676 if (INTEL_INFO(dev)->num_pipes == 2)
4679 /* Ivybridge 3 pipe is really complicated */
4684 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4685 pipe_config->fdi_lanes > 2) {
4686 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4687 pipe_name(pipe), pipe_config->fdi_lanes);
4692 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4693 pipe_B_crtc->config.fdi_lanes <= 2) {
4694 if (pipe_config->fdi_lanes > 2) {
4695 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4696 pipe_name(pipe), pipe_config->fdi_lanes);
4700 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4710 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4711 struct intel_crtc_config *pipe_config)
4713 struct drm_device *dev = intel_crtc->base.dev;
4714 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4715 int lane, link_bw, fdi_dotclock;
4716 bool setup_ok, needs_recompute = false;
4719 /* FDI is a binary signal running at ~2.7GHz, encoding
4720 * each output octet as 10 bits. The actual frequency
4721 * is stored as a divider into a 100MHz clock, and the
4722 * mode pixel clock is stored in units of 1KHz.
4723 * Hence the bw of each lane in terms of the mode signal
4726 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4728 fdi_dotclock = adjusted_mode->crtc_clock;
4730 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4731 pipe_config->pipe_bpp);
4733 pipe_config->fdi_lanes = lane;
4735 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4736 link_bw, &pipe_config->fdi_m_n);
4738 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4739 intel_crtc->pipe, pipe_config);
4740 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4741 pipe_config->pipe_bpp -= 2*3;
4742 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4743 pipe_config->pipe_bpp);
4744 needs_recompute = true;
4745 pipe_config->bw_constrained = true;
4750 if (needs_recompute)
4753 return setup_ok ? 0 : -EINVAL;
4756 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4757 struct intel_crtc_config *pipe_config)
4759 pipe_config->ips_enabled = i915.enable_ips &&
4760 hsw_crtc_supports_ips(crtc) &&
4761 pipe_config->pipe_bpp <= 24;
4764 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4765 struct intel_crtc_config *pipe_config)
4767 struct drm_device *dev = crtc->base.dev;
4768 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4770 /* FIXME should check pixel clock limits on all platforms */
4771 if (INTEL_INFO(dev)->gen < 4) {
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4774 dev_priv->display.get_display_clock_speed(dev);
4777 * Enable pixel doubling when the dot clock
4778 * is > 90% of the (display) core speed.
4780 * GDG double wide on either pipe,
4781 * otherwise pipe A only.
4783 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4784 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4786 pipe_config->double_wide = true;
4789 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4794 * Pipe horizontal size must be even in:
4796 * - LVDS dual channel mode
4797 * - Double wide pipe
4799 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4800 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4801 pipe_config->pipe_src_w &= ~1;
4803 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4804 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4806 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4807 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4810 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4811 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4812 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4813 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4815 pipe_config->pipe_bpp = 8*3;
4819 hsw_compute_ips_config(crtc, pipe_config);
4821 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4822 * clock survives for now. */
4823 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4824 pipe_config->shared_dpll = crtc->config.shared_dpll;
4826 if (pipe_config->has_pch_encoder)
4827 return ironlake_fdi_compute_config(crtc, pipe_config);
4832 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4834 return 400000; /* FIXME */
4837 static int i945_get_display_clock_speed(struct drm_device *dev)
4842 static int i915_get_display_clock_speed(struct drm_device *dev)
4847 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4852 static int pnv_get_display_clock_speed(struct drm_device *dev)
4856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4858 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4859 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4861 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4863 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4865 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4868 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4869 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4871 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4876 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4880 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4882 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4885 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4886 case GC_DISPLAY_CLOCK_333_MHZ:
4889 case GC_DISPLAY_CLOCK_190_200_MHZ:
4895 static int i865_get_display_clock_speed(struct drm_device *dev)
4900 static int i855_get_display_clock_speed(struct drm_device *dev)
4903 /* Assume that the hardware is in the high speed state. This
4904 * should be the default.
4906 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4907 case GC_CLOCK_133_200:
4908 case GC_CLOCK_100_200:
4910 case GC_CLOCK_166_250:
4912 case GC_CLOCK_100_133:
4916 /* Shouldn't happen */
4920 static int i830_get_display_clock_speed(struct drm_device *dev)
4926 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4928 while (*num > DATA_LINK_M_N_MASK ||
4929 *den > DATA_LINK_M_N_MASK) {
4935 static void compute_m_n(unsigned int m, unsigned int n,
4936 uint32_t *ret_m, uint32_t *ret_n)
4938 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4939 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4940 intel_reduce_m_n_ratio(ret_m, ret_n);
4944 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4945 int pixel_clock, int link_clock,
4946 struct intel_link_m_n *m_n)
4950 compute_m_n(bits_per_pixel * pixel_clock,
4951 link_clock * nlanes * 8,
4952 &m_n->gmch_m, &m_n->gmch_n);
4954 compute_m_n(pixel_clock, link_clock,
4955 &m_n->link_m, &m_n->link_n);
4958 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4960 if (i915.panel_use_ssc >= 0)
4961 return i915.panel_use_ssc != 0;
4962 return dev_priv->vbt.lvds_use_ssc
4963 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4966 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4968 struct drm_device *dev = crtc->dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4972 if (IS_VALLEYVIEW(dev)) {
4974 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4975 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4976 refclk = dev_priv->vbt.lvds_ssc_freq;
4977 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4978 } else if (!IS_GEN2(dev)) {
4987 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4989 return (1 << dpll->n) << 16 | dpll->m2;
4992 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4994 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4997 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4998 intel_clock_t *reduced_clock)
5000 struct drm_device *dev = crtc->base.dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 int pipe = crtc->pipe;
5005 if (IS_PINEVIEW(dev)) {
5006 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5008 fp2 = pnv_dpll_compute_fp(reduced_clock);
5010 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5012 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5015 I915_WRITE(FP0(pipe), fp);
5016 crtc->config.dpll_hw_state.fp0 = fp;
5018 crtc->lowfreq_avail = false;
5019 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5020 reduced_clock && i915.powersave) {
5021 I915_WRITE(FP1(pipe), fp2);
5022 crtc->config.dpll_hw_state.fp1 = fp2;
5023 crtc->lowfreq_avail = true;
5025 I915_WRITE(FP1(pipe), fp);
5026 crtc->config.dpll_hw_state.fp1 = fp;
5030 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5036 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5037 * and set it to a reasonable value instead.
5039 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5040 reg_val &= 0xffffff00;
5041 reg_val |= 0x00000030;
5042 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5044 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5045 reg_val &= 0x8cffffff;
5046 reg_val = 0x8c000000;
5047 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5049 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5050 reg_val &= 0xffffff00;
5051 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5053 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5054 reg_val &= 0x00ffffff;
5055 reg_val |= 0xb0000000;
5056 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5059 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5060 struct intel_link_m_n *m_n)
5062 struct drm_device *dev = crtc->base.dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 int pipe = crtc->pipe;
5066 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5067 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5068 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5069 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5072 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5073 struct intel_link_m_n *m_n)
5075 struct drm_device *dev = crtc->base.dev;
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 int pipe = crtc->pipe;
5078 enum transcoder transcoder = crtc->config.cpu_transcoder;
5080 if (INTEL_INFO(dev)->gen >= 5) {
5081 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5082 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5083 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5084 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5086 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5087 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5088 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5089 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5093 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5095 if (crtc->config.has_pch_encoder)
5096 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5098 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5101 static void vlv_update_pll(struct intel_crtc *crtc)
5103 struct drm_device *dev = crtc->base.dev;
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105 int pipe = crtc->pipe;
5107 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5108 u32 coreclk, reg_val, dpll_md;
5110 mutex_lock(&dev_priv->dpio_lock);
5112 bestn = crtc->config.dpll.n;
5113 bestm1 = crtc->config.dpll.m1;
5114 bestm2 = crtc->config.dpll.m2;
5115 bestp1 = crtc->config.dpll.p1;
5116 bestp2 = crtc->config.dpll.p2;
5118 /* See eDP HDMI DPIO driver vbios notes doc */
5120 /* PLL B needs special handling */
5122 vlv_pllb_recal_opamp(dev_priv, pipe);
5124 /* Set up Tx target for periodic Rcomp update */
5125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5127 /* Disable target IRef on PLL */
5128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5129 reg_val &= 0x00ffffff;
5130 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5132 /* Disable fast lock */
5133 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5135 /* Set idtafcrecal before PLL is enabled */
5136 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5137 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5138 mdiv |= ((bestn << DPIO_N_SHIFT));
5139 mdiv |= (1 << DPIO_K_SHIFT);
5142 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5143 * but we don't support that).
5144 * Note: don't use the DAC post divider as it seems unstable.
5146 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5149 mdiv |= DPIO_ENABLE_CALIBRATION;
5150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5152 /* Set HBR and RBR LPF coefficients */
5153 if (crtc->config.port_clock == 162000 ||
5154 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5155 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5159 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5162 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5163 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5164 /* Use SSC source */
5166 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5169 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5171 } else { /* HDMI or VGA */
5172 /* Use bend source */
5174 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5177 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5181 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5182 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5183 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5184 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5185 coreclk |= 0x01000000;
5186 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5188 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5191 * Enable DPIO clock input. We should never disable the reference
5192 * clock for pipe B, since VGA hotplug / manual detection depends
5195 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5196 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5197 /* We should never disable this, set it here for state tracking */
5199 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5200 dpll |= DPLL_VCO_ENABLE;
5201 crtc->config.dpll_hw_state.dpll = dpll;
5203 dpll_md = (crtc->config.pixel_multiplier - 1)
5204 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5205 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5207 mutex_unlock(&dev_priv->dpio_lock);
5210 static void i9xx_update_pll(struct intel_crtc *crtc,
5211 intel_clock_t *reduced_clock,
5214 struct drm_device *dev = crtc->base.dev;
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5218 struct dpll *clock = &crtc->config.dpll;
5220 i9xx_update_pll_dividers(crtc, reduced_clock);
5222 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5223 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5225 dpll = DPLL_VGA_MODE_DIS;
5227 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5228 dpll |= DPLLB_MODE_LVDS;
5230 dpll |= DPLLB_MODE_DAC_SERIAL;
5232 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5233 dpll |= (crtc->config.pixel_multiplier - 1)
5234 << SDVO_MULTIPLIER_SHIFT_HIRES;
5238 dpll |= DPLL_SDVO_HIGH_SPEED;
5240 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5241 dpll |= DPLL_SDVO_HIGH_SPEED;
5243 /* compute bitmask from p1 value */
5244 if (IS_PINEVIEW(dev))
5245 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5247 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5248 if (IS_G4X(dev) && reduced_clock)
5249 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5251 switch (clock->p2) {
5253 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5256 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5259 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5262 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5265 if (INTEL_INFO(dev)->gen >= 4)
5266 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5268 if (crtc->config.sdvo_tv_clock)
5269 dpll |= PLL_REF_INPUT_TVCLKINBC;
5270 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5271 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5272 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5274 dpll |= PLL_REF_INPUT_DREFCLK;
5276 dpll |= DPLL_VCO_ENABLE;
5277 crtc->config.dpll_hw_state.dpll = dpll;
5279 if (INTEL_INFO(dev)->gen >= 4) {
5280 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5281 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5282 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5286 static void i8xx_update_pll(struct intel_crtc *crtc,
5287 intel_clock_t *reduced_clock,
5290 struct drm_device *dev = crtc->base.dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5293 struct dpll *clock = &crtc->config.dpll;
5295 i9xx_update_pll_dividers(crtc, reduced_clock);
5297 dpll = DPLL_VGA_MODE_DIS;
5299 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5300 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5303 dpll |= PLL_P1_DIVIDE_BY_TWO;
5305 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5307 dpll |= PLL_P2_DIVIDE_BY_4;
5310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5311 dpll |= DPLL_DVO_2X_MODE;
5313 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5314 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5315 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5317 dpll |= PLL_REF_INPUT_DREFCLK;
5319 dpll |= DPLL_VCO_ENABLE;
5320 crtc->config.dpll_hw_state.dpll = dpll;
5323 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5325 struct drm_device *dev = intel_crtc->base.dev;
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327 enum pipe pipe = intel_crtc->pipe;
5328 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5329 struct drm_display_mode *adjusted_mode =
5330 &intel_crtc->config.adjusted_mode;
5331 uint32_t crtc_vtotal, crtc_vblank_end;
5334 /* We need to be careful not to changed the adjusted mode, for otherwise
5335 * the hw state checker will get angry at the mismatch. */
5336 crtc_vtotal = adjusted_mode->crtc_vtotal;
5337 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5339 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5340 /* the chip adds 2 halflines automatically */
5342 crtc_vblank_end -= 1;
5344 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5345 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5347 vsyncshift = adjusted_mode->crtc_hsync_start -
5348 adjusted_mode->crtc_htotal / 2;
5350 vsyncshift += adjusted_mode->crtc_htotal;
5353 if (INTEL_INFO(dev)->gen > 3)
5354 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5356 I915_WRITE(HTOTAL(cpu_transcoder),
5357 (adjusted_mode->crtc_hdisplay - 1) |
5358 ((adjusted_mode->crtc_htotal - 1) << 16));
5359 I915_WRITE(HBLANK(cpu_transcoder),
5360 (adjusted_mode->crtc_hblank_start - 1) |
5361 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5362 I915_WRITE(HSYNC(cpu_transcoder),
5363 (adjusted_mode->crtc_hsync_start - 1) |
5364 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5366 I915_WRITE(VTOTAL(cpu_transcoder),
5367 (adjusted_mode->crtc_vdisplay - 1) |
5368 ((crtc_vtotal - 1) << 16));
5369 I915_WRITE(VBLANK(cpu_transcoder),
5370 (adjusted_mode->crtc_vblank_start - 1) |
5371 ((crtc_vblank_end - 1) << 16));
5372 I915_WRITE(VSYNC(cpu_transcoder),
5373 (adjusted_mode->crtc_vsync_start - 1) |
5374 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5376 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5377 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5378 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5380 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5381 (pipe == PIPE_B || pipe == PIPE_C))
5382 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5384 /* pipesrc controls the size that is scaled from, which should
5385 * always be the user's requested size.
5387 I915_WRITE(PIPESRC(pipe),
5388 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5389 (intel_crtc->config.pipe_src_h - 1));
5392 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5393 struct intel_crtc_config *pipe_config)
5395 struct drm_device *dev = crtc->base.dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5400 tmp = I915_READ(HTOTAL(cpu_transcoder));
5401 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5402 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5403 tmp = I915_READ(HBLANK(cpu_transcoder));
5404 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5405 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5406 tmp = I915_READ(HSYNC(cpu_transcoder));
5407 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5408 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5410 tmp = I915_READ(VTOTAL(cpu_transcoder));
5411 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5412 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5413 tmp = I915_READ(VBLANK(cpu_transcoder));
5414 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5415 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5416 tmp = I915_READ(VSYNC(cpu_transcoder));
5417 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5418 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5420 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5421 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5422 pipe_config->adjusted_mode.crtc_vtotal += 1;
5423 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5426 tmp = I915_READ(PIPESRC(crtc->pipe));
5427 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5428 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5430 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5431 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5434 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5435 struct intel_crtc_config *pipe_config)
5437 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5438 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5439 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5440 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5442 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5443 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5444 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5445 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5447 mode->flags = pipe_config->adjusted_mode.flags;
5449 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5450 mode->flags |= pipe_config->adjusted_mode.flags;
5453 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5455 struct drm_device *dev = intel_crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5461 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5462 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5463 pipeconf |= PIPECONF_ENABLE;
5465 if (intel_crtc->config.double_wide)
5466 pipeconf |= PIPECONF_DOUBLE_WIDE;
5468 /* only g4x and later have fancy bpc/dither controls */
5469 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5470 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5471 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5472 pipeconf |= PIPECONF_DITHER_EN |
5473 PIPECONF_DITHER_TYPE_SP;
5475 switch (intel_crtc->config.pipe_bpp) {
5477 pipeconf |= PIPECONF_6BPC;
5480 pipeconf |= PIPECONF_8BPC;
5483 pipeconf |= PIPECONF_10BPC;
5486 /* Case prevented by intel_choose_pipe_bpp_dither. */
5491 if (HAS_PIPE_CXSR(dev)) {
5492 if (intel_crtc->lowfreq_avail) {
5493 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5494 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5496 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5500 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5501 if (INTEL_INFO(dev)->gen < 4 ||
5502 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5503 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5505 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5507 pipeconf |= PIPECONF_PROGRESSIVE;
5509 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5510 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5512 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5513 POSTING_READ(PIPECONF(intel_crtc->pipe));
5516 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5518 struct drm_framebuffer *fb)
5520 struct drm_device *dev = crtc->dev;
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5523 int pipe = intel_crtc->pipe;
5524 int plane = intel_crtc->plane;
5525 int refclk, num_connectors = 0;
5526 intel_clock_t clock, reduced_clock;
5528 bool ok, has_reduced_clock = false;
5529 bool is_lvds = false, is_dsi = false;
5530 struct intel_encoder *encoder;
5531 const intel_limit_t *limit;
5534 for_each_encoder_on_crtc(dev, crtc, encoder) {
5535 switch (encoder->type) {
5536 case INTEL_OUTPUT_LVDS:
5539 case INTEL_OUTPUT_DSI:
5550 if (!intel_crtc->config.clock_set) {
5551 refclk = i9xx_get_refclk(crtc, num_connectors);
5554 * Returns a set of divisors for the desired target clock with
5555 * the given refclk, or FALSE. The returned values represent
5556 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5559 limit = intel_limit(crtc, refclk);
5560 ok = dev_priv->display.find_dpll(limit, crtc,
5561 intel_crtc->config.port_clock,
5562 refclk, NULL, &clock);
5564 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5568 if (is_lvds && dev_priv->lvds_downclock_avail) {
5570 * Ensure we match the reduced clock's P to the target
5571 * clock. If the clocks don't match, we can't switch
5572 * the display clock by using the FP0/FP1. In such case
5573 * we will disable the LVDS downclock feature.
5576 dev_priv->display.find_dpll(limit, crtc,
5577 dev_priv->lvds_downclock,
5581 /* Compat-code for transition, will disappear. */
5582 intel_crtc->config.dpll.n = clock.n;
5583 intel_crtc->config.dpll.m1 = clock.m1;
5584 intel_crtc->config.dpll.m2 = clock.m2;
5585 intel_crtc->config.dpll.p1 = clock.p1;
5586 intel_crtc->config.dpll.p2 = clock.p2;
5590 i8xx_update_pll(intel_crtc,
5591 has_reduced_clock ? &reduced_clock : NULL,
5593 } else if (IS_VALLEYVIEW(dev)) {
5594 vlv_update_pll(intel_crtc);
5596 i9xx_update_pll(intel_crtc,
5597 has_reduced_clock ? &reduced_clock : NULL,
5602 /* Set up the display plane register */
5603 dspcntr = DISPPLANE_GAMMA_ENABLE;
5605 if (!IS_VALLEYVIEW(dev)) {
5607 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5609 dspcntr |= DISPPLANE_SEL_PIPE_B;
5612 if (intel_crtc->config.has_dp_encoder)
5613 intel_dp_set_m_n(intel_crtc);
5615 intel_set_pipe_timings(intel_crtc);
5617 /* pipesrc and dspsize control the size that is scaled from,
5618 * which should always be the user's requested size.
5620 I915_WRITE(DSPSIZE(plane),
5621 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5622 (intel_crtc->config.pipe_src_w - 1));
5623 I915_WRITE(DSPPOS(plane), 0);
5625 i9xx_set_pipeconf(intel_crtc);
5627 I915_WRITE(DSPCNTR(plane), dspcntr);
5628 POSTING_READ(DSPCNTR(plane));
5630 ret = intel_pipe_set_base(crtc, x, y, fb);
5635 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5636 struct intel_crtc_config *pipe_config)
5638 struct drm_device *dev = crtc->base.dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5642 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
5645 tmp = I915_READ(PFIT_CONTROL);
5646 if (!(tmp & PFIT_ENABLE))
5649 /* Check whether the pfit is attached to our pipe. */
5650 if (INTEL_INFO(dev)->gen < 4) {
5651 if (crtc->pipe != PIPE_B)
5654 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5658 pipe_config->gmch_pfit.control = tmp;
5659 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5660 if (INTEL_INFO(dev)->gen < 5)
5661 pipe_config->gmch_pfit.lvds_border_bits =
5662 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5665 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5666 struct intel_crtc_config *pipe_config)
5668 struct drm_device *dev = crtc->base.dev;
5669 struct drm_i915_private *dev_priv = dev->dev_private;
5670 int pipe = pipe_config->cpu_transcoder;
5671 intel_clock_t clock;
5673 int refclk = 100000;
5675 mutex_lock(&dev_priv->dpio_lock);
5676 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5677 mutex_unlock(&dev_priv->dpio_lock);
5679 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5680 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5681 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5682 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5683 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5685 vlv_clock(refclk, &clock);
5687 /* clock.dot is the fast clock */
5688 pipe_config->port_clock = clock.dot / 5;
5691 static void i9xx_get_plane_config(struct intel_crtc *crtc,
5692 struct intel_plane_config *plane_config)
5694 struct drm_device *dev = crtc->base.dev;
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696 u32 val, base, offset;
5697 int pipe = crtc->pipe, plane = crtc->plane;
5698 int fourcc, pixel_format;
5701 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
5702 if (!crtc->base.primary->fb) {
5703 DRM_DEBUG_KMS("failed to alloc fb\n");
5707 val = I915_READ(DSPCNTR(plane));
5709 if (INTEL_INFO(dev)->gen >= 4)
5710 if (val & DISPPLANE_TILED)
5711 plane_config->tiled = true;
5713 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
5714 fourcc = intel_format_to_fourcc(pixel_format);
5715 crtc->base.primary->fb->pixel_format = fourcc;
5716 crtc->base.primary->fb->bits_per_pixel =
5717 drm_format_plane_cpp(fourcc, 0) * 8;
5719 if (INTEL_INFO(dev)->gen >= 4) {
5720 if (plane_config->tiled)
5721 offset = I915_READ(DSPTILEOFF(plane));
5723 offset = I915_READ(DSPLINOFF(plane));
5724 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
5726 base = I915_READ(DSPADDR(plane));
5728 plane_config->base = base;
5730 val = I915_READ(PIPESRC(pipe));
5731 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
5732 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
5734 val = I915_READ(DSPSTRIDE(pipe));
5735 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
5737 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
5738 plane_config->tiled);
5740 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
5741 aligned_height, PAGE_SIZE);
5743 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
5744 pipe, plane, crtc->base.primary->fb->width,
5745 crtc->base.primary->fb->height,
5746 crtc->base.primary->fb->bits_per_pixel, base,
5747 crtc->base.primary->fb->pitches[0],
5748 plane_config->size);
5752 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5753 struct intel_crtc_config *pipe_config)
5755 struct drm_device *dev = crtc->base.dev;
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5759 if (!intel_display_power_enabled(dev_priv,
5760 POWER_DOMAIN_PIPE(crtc->pipe)))
5763 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5764 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5766 tmp = I915_READ(PIPECONF(crtc->pipe));
5767 if (!(tmp & PIPECONF_ENABLE))
5770 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5771 switch (tmp & PIPECONF_BPC_MASK) {
5773 pipe_config->pipe_bpp = 18;
5776 pipe_config->pipe_bpp = 24;
5778 case PIPECONF_10BPC:
5779 pipe_config->pipe_bpp = 30;
5786 if (INTEL_INFO(dev)->gen < 4)
5787 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5789 intel_get_pipe_timings(crtc, pipe_config);
5791 i9xx_get_pfit_config(crtc, pipe_config);
5793 if (INTEL_INFO(dev)->gen >= 4) {
5794 tmp = I915_READ(DPLL_MD(crtc->pipe));
5795 pipe_config->pixel_multiplier =
5796 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5797 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5798 pipe_config->dpll_hw_state.dpll_md = tmp;
5799 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5800 tmp = I915_READ(DPLL(crtc->pipe));
5801 pipe_config->pixel_multiplier =
5802 ((tmp & SDVO_MULTIPLIER_MASK)
5803 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5805 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5806 * port and will be fixed up in the encoder->get_config
5808 pipe_config->pixel_multiplier = 1;
5810 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5811 if (!IS_VALLEYVIEW(dev)) {
5812 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5813 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5815 /* Mask out read-only status bits. */
5816 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5817 DPLL_PORTC_READY_MASK |
5818 DPLL_PORTB_READY_MASK);
5821 if (IS_VALLEYVIEW(dev))
5822 vlv_crtc_clock_get(crtc, pipe_config);
5824 i9xx_crtc_clock_get(crtc, pipe_config);
5829 static void ironlake_init_pch_refclk(struct drm_device *dev)
5831 struct drm_i915_private *dev_priv = dev->dev_private;
5832 struct drm_mode_config *mode_config = &dev->mode_config;
5833 struct intel_encoder *encoder;
5835 bool has_lvds = false;
5836 bool has_cpu_edp = false;
5837 bool has_panel = false;
5838 bool has_ck505 = false;
5839 bool can_ssc = false;
5841 /* We need to take the global config into account */
5842 list_for_each_entry(encoder, &mode_config->encoder_list,
5844 switch (encoder->type) {
5845 case INTEL_OUTPUT_LVDS:
5849 case INTEL_OUTPUT_EDP:
5851 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5857 if (HAS_PCH_IBX(dev)) {
5858 has_ck505 = dev_priv->vbt.display_clock_mode;
5859 can_ssc = has_ck505;
5865 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5866 has_panel, has_lvds, has_ck505);
5868 /* Ironlake: try to setup display ref clock before DPLL
5869 * enabling. This is only under driver's control after
5870 * PCH B stepping, previous chipset stepping should be
5871 * ignoring this setting.
5873 val = I915_READ(PCH_DREF_CONTROL);
5875 /* As we must carefully and slowly disable/enable each source in turn,
5876 * compute the final state we want first and check if we need to
5877 * make any changes at all.
5880 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5882 final |= DREF_NONSPREAD_CK505_ENABLE;
5884 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5886 final &= ~DREF_SSC_SOURCE_MASK;
5887 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5888 final &= ~DREF_SSC1_ENABLE;
5891 final |= DREF_SSC_SOURCE_ENABLE;
5893 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5894 final |= DREF_SSC1_ENABLE;
5897 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5898 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5900 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5902 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5904 final |= DREF_SSC_SOURCE_DISABLE;
5905 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5911 /* Always enable nonspread source */
5912 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5915 val |= DREF_NONSPREAD_CK505_ENABLE;
5917 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5920 val &= ~DREF_SSC_SOURCE_MASK;
5921 val |= DREF_SSC_SOURCE_ENABLE;
5923 /* SSC must be turned on before enabling the CPU output */
5924 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5925 DRM_DEBUG_KMS("Using SSC on panel\n");
5926 val |= DREF_SSC1_ENABLE;
5928 val &= ~DREF_SSC1_ENABLE;
5930 /* Get SSC going before enabling the outputs */
5931 I915_WRITE(PCH_DREF_CONTROL, val);
5932 POSTING_READ(PCH_DREF_CONTROL);
5935 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5937 /* Enable CPU source on CPU attached eDP */
5939 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5940 DRM_DEBUG_KMS("Using SSC on eDP\n");
5941 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5944 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5946 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5948 I915_WRITE(PCH_DREF_CONTROL, val);
5949 POSTING_READ(PCH_DREF_CONTROL);
5952 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5954 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5956 /* Turn off CPU output */
5957 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5959 I915_WRITE(PCH_DREF_CONTROL, val);
5960 POSTING_READ(PCH_DREF_CONTROL);
5963 /* Turn off the SSC source */
5964 val &= ~DREF_SSC_SOURCE_MASK;
5965 val |= DREF_SSC_SOURCE_DISABLE;
5968 val &= ~DREF_SSC1_ENABLE;
5970 I915_WRITE(PCH_DREF_CONTROL, val);
5971 POSTING_READ(PCH_DREF_CONTROL);
5975 BUG_ON(val != final);
5978 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5982 tmp = I915_READ(SOUTH_CHICKEN2);
5983 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5984 I915_WRITE(SOUTH_CHICKEN2, tmp);
5986 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5987 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5988 DRM_ERROR("FDI mPHY reset assert timeout\n");
5990 tmp = I915_READ(SOUTH_CHICKEN2);
5991 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5992 I915_WRITE(SOUTH_CHICKEN2, tmp);
5994 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5995 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5996 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5999 /* WaMPhyProgramming:hsw */
6000 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6004 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6005 tmp &= ~(0xFF << 24);
6006 tmp |= (0x12 << 24);
6007 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6009 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6011 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6013 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6015 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6017 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6018 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6019 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6021 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6022 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6023 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6025 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6028 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6030 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6033 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6035 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6038 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6040 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6043 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6045 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6046 tmp &= ~(0xFF << 16);
6047 tmp |= (0x1C << 16);
6048 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6050 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6051 tmp &= ~(0xFF << 16);
6052 tmp |= (0x1C << 16);
6053 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6055 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6057 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6059 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6061 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6063 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6064 tmp &= ~(0xF << 28);
6066 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6068 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6069 tmp &= ~(0xF << 28);
6071 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6074 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6075 * Programming" based on the parameters passed:
6076 * - Sequence to enable CLKOUT_DP
6077 * - Sequence to enable CLKOUT_DP without spread
6078 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6080 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6086 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6088 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6089 with_fdi, "LP PCH doesn't have FDI\n"))
6092 mutex_lock(&dev_priv->dpio_lock);
6094 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6095 tmp &= ~SBI_SSCCTL_DISABLE;
6096 tmp |= SBI_SSCCTL_PATHALT;
6097 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6102 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6103 tmp &= ~SBI_SSCCTL_PATHALT;
6104 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6107 lpt_reset_fdi_mphy(dev_priv);
6108 lpt_program_fdi_mphy(dev_priv);
6112 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6113 SBI_GEN0 : SBI_DBUFF0;
6114 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6115 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6116 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6118 mutex_unlock(&dev_priv->dpio_lock);
6121 /* Sequence to disable CLKOUT_DP */
6122 static void lpt_disable_clkout_dp(struct drm_device *dev)
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6127 mutex_lock(&dev_priv->dpio_lock);
6129 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6130 SBI_GEN0 : SBI_DBUFF0;
6131 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6132 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6133 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6135 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6136 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6137 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6138 tmp |= SBI_SSCCTL_PATHALT;
6139 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6142 tmp |= SBI_SSCCTL_DISABLE;
6143 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6146 mutex_unlock(&dev_priv->dpio_lock);
6149 static void lpt_init_pch_refclk(struct drm_device *dev)
6151 struct drm_mode_config *mode_config = &dev->mode_config;
6152 struct intel_encoder *encoder;
6153 bool has_vga = false;
6155 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6156 switch (encoder->type) {
6157 case INTEL_OUTPUT_ANALOG:
6164 lpt_enable_clkout_dp(dev, true, true);
6166 lpt_disable_clkout_dp(dev);
6170 * Initialize reference clocks when the driver loads
6172 void intel_init_pch_refclk(struct drm_device *dev)
6174 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6175 ironlake_init_pch_refclk(dev);
6176 else if (HAS_PCH_LPT(dev))
6177 lpt_init_pch_refclk(dev);
6180 static int ironlake_get_refclk(struct drm_crtc *crtc)
6182 struct drm_device *dev = crtc->dev;
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 struct intel_encoder *encoder;
6185 int num_connectors = 0;
6186 bool is_lvds = false;
6188 for_each_encoder_on_crtc(dev, crtc, encoder) {
6189 switch (encoder->type) {
6190 case INTEL_OUTPUT_LVDS:
6197 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6198 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6199 dev_priv->vbt.lvds_ssc_freq);
6200 return dev_priv->vbt.lvds_ssc_freq;
6206 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6208 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 int pipe = intel_crtc->pipe;
6215 switch (intel_crtc->config.pipe_bpp) {
6217 val |= PIPECONF_6BPC;
6220 val |= PIPECONF_8BPC;
6223 val |= PIPECONF_10BPC;
6226 val |= PIPECONF_12BPC;
6229 /* Case prevented by intel_choose_pipe_bpp_dither. */
6233 if (intel_crtc->config.dither)
6234 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6236 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6237 val |= PIPECONF_INTERLACED_ILK;
6239 val |= PIPECONF_PROGRESSIVE;
6241 if (intel_crtc->config.limited_color_range)
6242 val |= PIPECONF_COLOR_RANGE_SELECT;
6244 I915_WRITE(PIPECONF(pipe), val);
6245 POSTING_READ(PIPECONF(pipe));
6249 * Set up the pipe CSC unit.
6251 * Currently only full range RGB to limited range RGB conversion
6252 * is supported, but eventually this should handle various
6253 * RGB<->YCbCr scenarios as well.
6255 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6257 struct drm_device *dev = crtc->dev;
6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260 int pipe = intel_crtc->pipe;
6261 uint16_t coeff = 0x7800; /* 1.0 */
6264 * TODO: Check what kind of values actually come out of the pipe
6265 * with these coeff/postoff values and adjust to get the best
6266 * accuracy. Perhaps we even need to take the bpc value into
6270 if (intel_crtc->config.limited_color_range)
6271 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6274 * GY/GU and RY/RU should be the other way around according
6275 * to BSpec, but reality doesn't agree. Just set them up in
6276 * a way that results in the correct picture.
6278 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6279 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6281 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6282 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6284 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6285 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6287 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6288 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6289 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6291 if (INTEL_INFO(dev)->gen > 6) {
6292 uint16_t postoff = 0;
6294 if (intel_crtc->config.limited_color_range)
6295 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6297 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6298 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6299 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6301 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6303 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6305 if (intel_crtc->config.limited_color_range)
6306 mode |= CSC_BLACK_SCREEN_OFFSET;
6308 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6312 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317 enum pipe pipe = intel_crtc->pipe;
6318 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6323 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6324 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6326 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6327 val |= PIPECONF_INTERLACED_ILK;
6329 val |= PIPECONF_PROGRESSIVE;
6331 I915_WRITE(PIPECONF(cpu_transcoder), val);
6332 POSTING_READ(PIPECONF(cpu_transcoder));
6334 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6335 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6337 if (IS_BROADWELL(dev)) {
6340 switch (intel_crtc->config.pipe_bpp) {
6342 val |= PIPEMISC_DITHER_6_BPC;
6345 val |= PIPEMISC_DITHER_8_BPC;
6348 val |= PIPEMISC_DITHER_10_BPC;
6351 val |= PIPEMISC_DITHER_12_BPC;
6354 /* Case prevented by pipe_config_set_bpp. */
6358 if (intel_crtc->config.dither)
6359 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6361 I915_WRITE(PIPEMISC(pipe), val);
6365 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6366 intel_clock_t *clock,
6367 bool *has_reduced_clock,
6368 intel_clock_t *reduced_clock)
6370 struct drm_device *dev = crtc->dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 struct intel_encoder *intel_encoder;
6374 const intel_limit_t *limit;
6375 bool ret, is_lvds = false;
6377 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6378 switch (intel_encoder->type) {
6379 case INTEL_OUTPUT_LVDS:
6385 refclk = ironlake_get_refclk(crtc);
6388 * Returns a set of divisors for the desired target clock with the given
6389 * refclk, or FALSE. The returned values represent the clock equation:
6390 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6392 limit = intel_limit(crtc, refclk);
6393 ret = dev_priv->display.find_dpll(limit, crtc,
6394 to_intel_crtc(crtc)->config.port_clock,
6395 refclk, NULL, clock);
6399 if (is_lvds && dev_priv->lvds_downclock_avail) {
6401 * Ensure we match the reduced clock's P to the target clock.
6402 * If the clocks don't match, we can't switch the display clock
6403 * by using the FP0/FP1. In such case we will disable the LVDS
6404 * downclock feature.
6406 *has_reduced_clock =
6407 dev_priv->display.find_dpll(limit, crtc,
6408 dev_priv->lvds_downclock,
6416 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6419 * Account for spread spectrum to avoid
6420 * oversubscribing the link. Max center spread
6421 * is 2.5%; use 5% for safety's sake.
6423 u32 bps = target_clock * bpp * 21 / 20;
6424 return DIV_ROUND_UP(bps, link_bw * 8);
6427 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6429 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6432 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6434 intel_clock_t *reduced_clock, u32 *fp2)
6436 struct drm_crtc *crtc = &intel_crtc->base;
6437 struct drm_device *dev = crtc->dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct intel_encoder *intel_encoder;
6441 int factor, num_connectors = 0;
6442 bool is_lvds = false, is_sdvo = false;
6444 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6445 switch (intel_encoder->type) {
6446 case INTEL_OUTPUT_LVDS:
6449 case INTEL_OUTPUT_SDVO:
6450 case INTEL_OUTPUT_HDMI:
6458 /* Enable autotuning of the PLL clock (if permissible) */
6461 if ((intel_panel_use_ssc(dev_priv) &&
6462 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6463 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6465 } else if (intel_crtc->config.sdvo_tv_clock)
6468 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6471 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6477 dpll |= DPLLB_MODE_LVDS;
6479 dpll |= DPLLB_MODE_DAC_SERIAL;
6481 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6482 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6485 dpll |= DPLL_SDVO_HIGH_SPEED;
6486 if (intel_crtc->config.has_dp_encoder)
6487 dpll |= DPLL_SDVO_HIGH_SPEED;
6489 /* compute bitmask from p1 value */
6490 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6492 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6494 switch (intel_crtc->config.dpll.p2) {
6496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6502 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6505 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6509 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6510 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6512 dpll |= PLL_REF_INPUT_DREFCLK;
6514 return dpll | DPLL_VCO_ENABLE;
6517 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6519 struct drm_framebuffer *fb)
6521 struct drm_device *dev = crtc->dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524 int pipe = intel_crtc->pipe;
6525 int plane = intel_crtc->plane;
6526 int num_connectors = 0;
6527 intel_clock_t clock, reduced_clock;
6528 u32 dpll = 0, fp = 0, fp2 = 0;
6529 bool ok, has_reduced_clock = false;
6530 bool is_lvds = false;
6531 struct intel_encoder *encoder;
6532 struct intel_shared_dpll *pll;
6535 for_each_encoder_on_crtc(dev, crtc, encoder) {
6536 switch (encoder->type) {
6537 case INTEL_OUTPUT_LVDS:
6545 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6546 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6548 ok = ironlake_compute_clocks(crtc, &clock,
6549 &has_reduced_clock, &reduced_clock);
6550 if (!ok && !intel_crtc->config.clock_set) {
6551 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6554 /* Compat-code for transition, will disappear. */
6555 if (!intel_crtc->config.clock_set) {
6556 intel_crtc->config.dpll.n = clock.n;
6557 intel_crtc->config.dpll.m1 = clock.m1;
6558 intel_crtc->config.dpll.m2 = clock.m2;
6559 intel_crtc->config.dpll.p1 = clock.p1;
6560 intel_crtc->config.dpll.p2 = clock.p2;
6563 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6564 if (intel_crtc->config.has_pch_encoder) {
6565 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6566 if (has_reduced_clock)
6567 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6569 dpll = ironlake_compute_dpll(intel_crtc,
6570 &fp, &reduced_clock,
6571 has_reduced_clock ? &fp2 : NULL);
6573 intel_crtc->config.dpll_hw_state.dpll = dpll;
6574 intel_crtc->config.dpll_hw_state.fp0 = fp;
6575 if (has_reduced_clock)
6576 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6578 intel_crtc->config.dpll_hw_state.fp1 = fp;
6580 pll = intel_get_shared_dpll(intel_crtc);
6582 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6587 intel_put_shared_dpll(intel_crtc);
6589 if (intel_crtc->config.has_dp_encoder)
6590 intel_dp_set_m_n(intel_crtc);
6592 if (is_lvds && has_reduced_clock && i915.powersave)
6593 intel_crtc->lowfreq_avail = true;
6595 intel_crtc->lowfreq_avail = false;
6597 intel_set_pipe_timings(intel_crtc);
6599 if (intel_crtc->config.has_pch_encoder) {
6600 intel_cpu_transcoder_set_m_n(intel_crtc,
6601 &intel_crtc->config.fdi_m_n);
6604 ironlake_set_pipeconf(crtc);
6606 /* Set up the display plane register */
6607 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6608 POSTING_READ(DSPCNTR(plane));
6610 ret = intel_pipe_set_base(crtc, x, y, fb);
6615 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6616 struct intel_link_m_n *m_n)
6618 struct drm_device *dev = crtc->base.dev;
6619 struct drm_i915_private *dev_priv = dev->dev_private;
6620 enum pipe pipe = crtc->pipe;
6622 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6623 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6624 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6626 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6627 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6628 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6631 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6632 enum transcoder transcoder,
6633 struct intel_link_m_n *m_n)
6635 struct drm_device *dev = crtc->base.dev;
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 enum pipe pipe = crtc->pipe;
6639 if (INTEL_INFO(dev)->gen >= 5) {
6640 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6641 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6642 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6644 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6645 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6646 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6648 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6649 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6650 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6652 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6653 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6654 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6658 void intel_dp_get_m_n(struct intel_crtc *crtc,
6659 struct intel_crtc_config *pipe_config)
6661 if (crtc->config.has_pch_encoder)
6662 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6664 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6665 &pipe_config->dp_m_n);
6668 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6669 struct intel_crtc_config *pipe_config)
6671 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6672 &pipe_config->fdi_m_n);
6675 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6676 struct intel_crtc_config *pipe_config)
6678 struct drm_device *dev = crtc->base.dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6682 tmp = I915_READ(PF_CTL(crtc->pipe));
6684 if (tmp & PF_ENABLE) {
6685 pipe_config->pch_pfit.enabled = true;
6686 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6687 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6689 /* We currently do not free assignements of panel fitters on
6690 * ivb/hsw (since we don't use the higher upscaling modes which
6691 * differentiates them) so just WARN about this case for now. */
6693 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6694 PF_PIPE_SEL_IVB(crtc->pipe));
6699 static void ironlake_get_plane_config(struct intel_crtc *crtc,
6700 struct intel_plane_config *plane_config)
6702 struct drm_device *dev = crtc->base.dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 u32 val, base, offset;
6705 int pipe = crtc->pipe, plane = crtc->plane;
6706 int fourcc, pixel_format;
6709 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6710 if (!crtc->base.primary->fb) {
6711 DRM_DEBUG_KMS("failed to alloc fb\n");
6715 val = I915_READ(DSPCNTR(plane));
6717 if (INTEL_INFO(dev)->gen >= 4)
6718 if (val & DISPPLANE_TILED)
6719 plane_config->tiled = true;
6721 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6722 fourcc = intel_format_to_fourcc(pixel_format);
6723 crtc->base.primary->fb->pixel_format = fourcc;
6724 crtc->base.primary->fb->bits_per_pixel =
6725 drm_format_plane_cpp(fourcc, 0) * 8;
6727 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6728 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6729 offset = I915_READ(DSPOFFSET(plane));
6731 if (plane_config->tiled)
6732 offset = I915_READ(DSPTILEOFF(plane));
6734 offset = I915_READ(DSPLINOFF(plane));
6736 plane_config->base = base;
6738 val = I915_READ(PIPESRC(pipe));
6739 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6740 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6742 val = I915_READ(DSPSTRIDE(pipe));
6743 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6745 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6746 plane_config->tiled);
6748 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6749 aligned_height, PAGE_SIZE);
6751 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6752 pipe, plane, crtc->base.primary->fb->width,
6753 crtc->base.primary->fb->height,
6754 crtc->base.primary->fb->bits_per_pixel, base,
6755 crtc->base.primary->fb->pitches[0],
6756 plane_config->size);
6759 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6760 struct intel_crtc_config *pipe_config)
6762 struct drm_device *dev = crtc->base.dev;
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6766 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6767 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6769 tmp = I915_READ(PIPECONF(crtc->pipe));
6770 if (!(tmp & PIPECONF_ENABLE))
6773 switch (tmp & PIPECONF_BPC_MASK) {
6775 pipe_config->pipe_bpp = 18;
6778 pipe_config->pipe_bpp = 24;
6780 case PIPECONF_10BPC:
6781 pipe_config->pipe_bpp = 30;
6783 case PIPECONF_12BPC:
6784 pipe_config->pipe_bpp = 36;
6790 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6791 struct intel_shared_dpll *pll;
6793 pipe_config->has_pch_encoder = true;
6795 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6796 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6797 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6799 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6801 if (HAS_PCH_IBX(dev_priv->dev)) {
6802 pipe_config->shared_dpll =
6803 (enum intel_dpll_id) crtc->pipe;
6805 tmp = I915_READ(PCH_DPLL_SEL);
6806 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6807 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6809 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6812 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6814 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6815 &pipe_config->dpll_hw_state));
6817 tmp = pipe_config->dpll_hw_state.dpll;
6818 pipe_config->pixel_multiplier =
6819 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6820 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6822 ironlake_pch_clock_get(crtc, pipe_config);
6824 pipe_config->pixel_multiplier = 1;
6827 intel_get_pipe_timings(crtc, pipe_config);
6829 ironlake_get_pfit_config(crtc, pipe_config);
6834 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6836 struct drm_device *dev = dev_priv->dev;
6837 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6838 struct intel_crtc *crtc;
6840 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6841 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6842 pipe_name(crtc->pipe));
6844 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6845 WARN(plls->spll_refcount, "SPLL enabled\n");
6846 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6847 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6848 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6849 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6850 "CPU PWM1 enabled\n");
6851 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6852 "CPU PWM2 enabled\n");
6853 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6854 "PCH PWM1 enabled\n");
6855 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6856 "Utility pin enabled\n");
6857 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6860 * In theory we can still leave IRQs enabled, as long as only the HPD
6861 * interrupts remain enabled. We used to check for that, but since it's
6862 * gen-specific and since we only disable LCPLL after we fully disable
6863 * the interrupts, the check below should be enough.
6865 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
6868 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
6870 struct drm_device *dev = dev_priv->dev;
6872 if (IS_HASWELL(dev)) {
6873 mutex_lock(&dev_priv->rps.hw_lock);
6874 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
6876 DRM_ERROR("Failed to disable D_COMP\n");
6877 mutex_unlock(&dev_priv->rps.hw_lock);
6879 I915_WRITE(D_COMP, val);
6881 POSTING_READ(D_COMP);
6885 * This function implements pieces of two sequences from BSpec:
6886 * - Sequence for display software to disable LCPLL
6887 * - Sequence for display software to allow package C8+
6888 * The steps implemented here are just the steps that actually touch the LCPLL
6889 * register. Callers should take care of disabling all the display engine
6890 * functions, doing the mode unset, fixing interrupts, etc.
6892 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6893 bool switch_to_fclk, bool allow_power_down)
6897 assert_can_disable_lcpll(dev_priv);
6899 val = I915_READ(LCPLL_CTL);
6901 if (switch_to_fclk) {
6902 val |= LCPLL_CD_SOURCE_FCLK;
6903 I915_WRITE(LCPLL_CTL, val);
6905 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6906 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6907 DRM_ERROR("Switching to FCLK failed\n");
6909 val = I915_READ(LCPLL_CTL);
6912 val |= LCPLL_PLL_DISABLE;
6913 I915_WRITE(LCPLL_CTL, val);
6914 POSTING_READ(LCPLL_CTL);
6916 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6917 DRM_ERROR("LCPLL still locked\n");
6919 val = I915_READ(D_COMP);
6920 val |= D_COMP_COMP_DISABLE;
6921 hsw_write_dcomp(dev_priv, val);
6924 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6925 DRM_ERROR("D_COMP RCOMP still in progress\n");
6927 if (allow_power_down) {
6928 val = I915_READ(LCPLL_CTL);
6929 val |= LCPLL_POWER_DOWN_ALLOW;
6930 I915_WRITE(LCPLL_CTL, val);
6931 POSTING_READ(LCPLL_CTL);
6936 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6939 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6942 unsigned long irqflags;
6944 val = I915_READ(LCPLL_CTL);
6946 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6947 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6951 * Make sure we're not on PC8 state before disabling PC8, otherwise
6952 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
6954 * The other problem is that hsw_restore_lcpll() is called as part of
6955 * the runtime PM resume sequence, so we can't just call
6956 * gen6_gt_force_wake_get() because that function calls
6957 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
6958 * while we are on the resume sequence. So to solve this problem we have
6959 * to call special forcewake code that doesn't touch runtime PM and
6960 * doesn't enable the forcewake delayed work.
6962 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6963 if (dev_priv->uncore.forcewake_count++ == 0)
6964 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6965 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
6967 if (val & LCPLL_POWER_DOWN_ALLOW) {
6968 val &= ~LCPLL_POWER_DOWN_ALLOW;
6969 I915_WRITE(LCPLL_CTL, val);
6970 POSTING_READ(LCPLL_CTL);
6973 val = I915_READ(D_COMP);
6974 val |= D_COMP_COMP_FORCE;
6975 val &= ~D_COMP_COMP_DISABLE;
6976 hsw_write_dcomp(dev_priv, val);
6978 val = I915_READ(LCPLL_CTL);
6979 val &= ~LCPLL_PLL_DISABLE;
6980 I915_WRITE(LCPLL_CTL, val);
6982 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6983 DRM_ERROR("LCPLL not locked yet\n");
6985 if (val & LCPLL_CD_SOURCE_FCLK) {
6986 val = I915_READ(LCPLL_CTL);
6987 val &= ~LCPLL_CD_SOURCE_FCLK;
6988 I915_WRITE(LCPLL_CTL, val);
6990 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6991 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6992 DRM_ERROR("Switching back to LCPLL failed\n");
6995 /* See the big comment above. */
6996 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6997 if (--dev_priv->uncore.forcewake_count == 0)
6998 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6999 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7003 * Package states C8 and deeper are really deep PC states that can only be
7004 * reached when all the devices on the system allow it, so even if the graphics
7005 * device allows PC8+, it doesn't mean the system will actually get to these
7006 * states. Our driver only allows PC8+ when going into runtime PM.
7008 * The requirements for PC8+ are that all the outputs are disabled, the power
7009 * well is disabled and most interrupts are disabled, and these are also
7010 * requirements for runtime PM. When these conditions are met, we manually do
7011 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7012 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7015 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7016 * the state of some registers, so when we come back from PC8+ we need to
7017 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7018 * need to take care of the registers kept by RC6. Notice that this happens even
7019 * if we don't put the device in PCI D3 state (which is what currently happens
7020 * because of the runtime PM support).
7022 * For more, read "Display Sequences for Package C8" on the hardware
7025 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7027 struct drm_device *dev = dev_priv->dev;
7030 DRM_DEBUG_KMS("Enabling package C8+\n");
7032 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7033 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7034 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7035 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7038 lpt_disable_clkout_dp(dev);
7039 hsw_disable_lcpll(dev_priv, true, true);
7042 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7044 struct drm_device *dev = dev_priv->dev;
7047 DRM_DEBUG_KMS("Disabling package C8+\n");
7049 hsw_restore_lcpll(dev_priv);
7050 lpt_init_pch_refclk(dev);
7052 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7053 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7054 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7055 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7058 intel_prepare_ddi(dev);
7061 static void snb_modeset_global_resources(struct drm_device *dev)
7063 modeset_update_crtc_power_domains(dev);
7066 static void haswell_modeset_global_resources(struct drm_device *dev)
7068 modeset_update_crtc_power_domains(dev);
7071 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7073 struct drm_framebuffer *fb)
7075 struct drm_device *dev = crtc->dev;
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7078 int plane = intel_crtc->plane;
7081 if (!intel_ddi_pll_select(intel_crtc))
7083 intel_ddi_pll_enable(intel_crtc);
7085 if (intel_crtc->config.has_dp_encoder)
7086 intel_dp_set_m_n(intel_crtc);
7088 intel_crtc->lowfreq_avail = false;
7090 intel_set_pipe_timings(intel_crtc);
7092 if (intel_crtc->config.has_pch_encoder) {
7093 intel_cpu_transcoder_set_m_n(intel_crtc,
7094 &intel_crtc->config.fdi_m_n);
7097 haswell_set_pipeconf(crtc);
7099 intel_set_pipe_csc(crtc);
7101 /* Set up the display plane register */
7102 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
7103 POSTING_READ(DSPCNTR(plane));
7105 ret = intel_pipe_set_base(crtc, x, y, fb);
7110 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7111 struct intel_crtc_config *pipe_config)
7113 struct drm_device *dev = crtc->base.dev;
7114 struct drm_i915_private *dev_priv = dev->dev_private;
7115 enum intel_display_power_domain pfit_domain;
7118 if (!intel_display_power_enabled(dev_priv,
7119 POWER_DOMAIN_PIPE(crtc->pipe)))
7122 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7123 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7125 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7126 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7127 enum pipe trans_edp_pipe;
7128 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7130 WARN(1, "unknown pipe linked to edp transcoder\n");
7131 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7132 case TRANS_DDI_EDP_INPUT_A_ON:
7133 trans_edp_pipe = PIPE_A;
7135 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7136 trans_edp_pipe = PIPE_B;
7138 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7139 trans_edp_pipe = PIPE_C;
7143 if (trans_edp_pipe == crtc->pipe)
7144 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7147 if (!intel_display_power_enabled(dev_priv,
7148 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7151 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7152 if (!(tmp & PIPECONF_ENABLE))
7156 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7157 * DDI E. So just check whether this pipe is wired to DDI E and whether
7158 * the PCH transcoder is on.
7160 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7161 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7162 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7163 pipe_config->has_pch_encoder = true;
7165 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7166 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7167 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7169 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7172 intel_get_pipe_timings(crtc, pipe_config);
7174 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7175 if (intel_display_power_enabled(dev_priv, pfit_domain))
7176 ironlake_get_pfit_config(crtc, pipe_config);
7178 if (IS_HASWELL(dev))
7179 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7180 (I915_READ(IPS_CTL) & IPS_ENABLE);
7182 pipe_config->pixel_multiplier = 1;
7187 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7189 struct drm_framebuffer *fb)
7191 struct drm_device *dev = crtc->dev;
7192 struct drm_i915_private *dev_priv = dev->dev_private;
7193 struct intel_encoder *encoder;
7194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7196 int pipe = intel_crtc->pipe;
7199 drm_vblank_pre_modeset(dev, pipe);
7201 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7203 drm_vblank_post_modeset(dev, pipe);
7208 for_each_encoder_on_crtc(dev, crtc, encoder) {
7209 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7210 encoder->base.base.id,
7211 drm_get_encoder_name(&encoder->base),
7212 mode->base.id, mode->name);
7213 encoder->mode_set(encoder);
7222 } hdmi_audio_clock[] = {
7223 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7224 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7225 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7226 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7227 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7228 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7229 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7230 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7231 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7232 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7235 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7236 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7240 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7241 if (mode->clock == hdmi_audio_clock[i].clock)
7245 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7246 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7250 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7251 hdmi_audio_clock[i].clock,
7252 hdmi_audio_clock[i].config);
7254 return hdmi_audio_clock[i].config;
7257 static bool intel_eld_uptodate(struct drm_connector *connector,
7258 int reg_eldv, uint32_t bits_eldv,
7259 int reg_elda, uint32_t bits_elda,
7262 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7263 uint8_t *eld = connector->eld;
7266 i = I915_READ(reg_eldv);
7275 i = I915_READ(reg_elda);
7277 I915_WRITE(reg_elda, i);
7279 for (i = 0; i < eld[2]; i++)
7280 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7286 static void g4x_write_eld(struct drm_connector *connector,
7287 struct drm_crtc *crtc,
7288 struct drm_display_mode *mode)
7290 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7291 uint8_t *eld = connector->eld;
7296 i = I915_READ(G4X_AUD_VID_DID);
7298 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7299 eldv = G4X_ELDV_DEVCL_DEVBLC;
7301 eldv = G4X_ELDV_DEVCTG;
7303 if (intel_eld_uptodate(connector,
7304 G4X_AUD_CNTL_ST, eldv,
7305 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7306 G4X_HDMIW_HDMIEDID))
7309 i = I915_READ(G4X_AUD_CNTL_ST);
7310 i &= ~(eldv | G4X_ELD_ADDR);
7311 len = (i >> 9) & 0x1f; /* ELD buffer size */
7312 I915_WRITE(G4X_AUD_CNTL_ST, i);
7317 len = min_t(uint8_t, eld[2], len);
7318 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7319 for (i = 0; i < len; i++)
7320 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7322 i = I915_READ(G4X_AUD_CNTL_ST);
7324 I915_WRITE(G4X_AUD_CNTL_ST, i);
7327 static void haswell_write_eld(struct drm_connector *connector,
7328 struct drm_crtc *crtc,
7329 struct drm_display_mode *mode)
7331 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7332 uint8_t *eld = connector->eld;
7333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337 int pipe = to_intel_crtc(crtc)->pipe;
7340 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7341 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7342 int aud_config = HSW_AUD_CFG(pipe);
7343 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7345 /* Audio output enable */
7346 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7347 tmp = I915_READ(aud_cntrl_st2);
7348 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7349 I915_WRITE(aud_cntrl_st2, tmp);
7350 POSTING_READ(aud_cntrl_st2);
7352 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7354 /* Set ELD valid state */
7355 tmp = I915_READ(aud_cntrl_st2);
7356 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7357 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7358 I915_WRITE(aud_cntrl_st2, tmp);
7359 tmp = I915_READ(aud_cntrl_st2);
7360 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7362 /* Enable HDMI mode */
7363 tmp = I915_READ(aud_config);
7364 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7365 /* clear N_programing_enable and N_value_index */
7366 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7367 I915_WRITE(aud_config, tmp);
7369 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7371 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7372 intel_crtc->eld_vld = true;
7374 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7375 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7376 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7377 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7379 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7382 if (intel_eld_uptodate(connector,
7383 aud_cntrl_st2, eldv,
7384 aud_cntl_st, IBX_ELD_ADDRESS,
7388 i = I915_READ(aud_cntrl_st2);
7390 I915_WRITE(aud_cntrl_st2, i);
7395 i = I915_READ(aud_cntl_st);
7396 i &= ~IBX_ELD_ADDRESS;
7397 I915_WRITE(aud_cntl_st, i);
7398 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7399 DRM_DEBUG_DRIVER("port num:%d\n", i);
7401 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7402 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7403 for (i = 0; i < len; i++)
7404 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7406 i = I915_READ(aud_cntrl_st2);
7408 I915_WRITE(aud_cntrl_st2, i);
7412 static void ironlake_write_eld(struct drm_connector *connector,
7413 struct drm_crtc *crtc,
7414 struct drm_display_mode *mode)
7416 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7417 uint8_t *eld = connector->eld;
7425 int pipe = to_intel_crtc(crtc)->pipe;
7427 if (HAS_PCH_IBX(connector->dev)) {
7428 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7429 aud_config = IBX_AUD_CFG(pipe);
7430 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7431 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7432 } else if (IS_VALLEYVIEW(connector->dev)) {
7433 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7434 aud_config = VLV_AUD_CFG(pipe);
7435 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7436 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7438 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7439 aud_config = CPT_AUD_CFG(pipe);
7440 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7441 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7444 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7446 if (IS_VALLEYVIEW(connector->dev)) {
7447 struct intel_encoder *intel_encoder;
7448 struct intel_digital_port *intel_dig_port;
7450 intel_encoder = intel_attached_encoder(connector);
7451 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7452 i = intel_dig_port->port;
7454 i = I915_READ(aud_cntl_st);
7455 i = (i >> 29) & DIP_PORT_SEL_MASK;
7456 /* DIP_Port_Select, 0x1 = PortB */
7460 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7461 /* operate blindly on all ports */
7462 eldv = IBX_ELD_VALIDB;
7463 eldv |= IBX_ELD_VALIDB << 4;
7464 eldv |= IBX_ELD_VALIDB << 8;
7466 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7467 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7470 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7471 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7472 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7473 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7475 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7478 if (intel_eld_uptodate(connector,
7479 aud_cntrl_st2, eldv,
7480 aud_cntl_st, IBX_ELD_ADDRESS,
7484 i = I915_READ(aud_cntrl_st2);
7486 I915_WRITE(aud_cntrl_st2, i);
7491 i = I915_READ(aud_cntl_st);
7492 i &= ~IBX_ELD_ADDRESS;
7493 I915_WRITE(aud_cntl_st, i);
7495 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7496 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7497 for (i = 0; i < len; i++)
7498 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7500 i = I915_READ(aud_cntrl_st2);
7502 I915_WRITE(aud_cntrl_st2, i);
7505 void intel_write_eld(struct drm_encoder *encoder,
7506 struct drm_display_mode *mode)
7508 struct drm_crtc *crtc = encoder->crtc;
7509 struct drm_connector *connector;
7510 struct drm_device *dev = encoder->dev;
7511 struct drm_i915_private *dev_priv = dev->dev_private;
7513 connector = drm_select_eld(encoder, mode);
7517 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7519 drm_get_connector_name(connector),
7520 connector->encoder->base.id,
7521 drm_get_encoder_name(connector->encoder));
7523 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7525 if (dev_priv->display.write_eld)
7526 dev_priv->display.write_eld(connector, crtc, mode);
7529 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7531 struct drm_device *dev = crtc->dev;
7532 struct drm_i915_private *dev_priv = dev->dev_private;
7533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7534 bool visible = base != 0;
7537 if (intel_crtc->cursor_visible == visible)
7540 cntl = I915_READ(_CURACNTR);
7542 /* On these chipsets we can only modify the base whilst
7543 * the cursor is disabled.
7545 I915_WRITE(_CURABASE, base);
7547 cntl &= ~(CURSOR_FORMAT_MASK);
7548 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7549 cntl |= CURSOR_ENABLE |
7550 CURSOR_GAMMA_ENABLE |
7553 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7554 I915_WRITE(_CURACNTR, cntl);
7556 intel_crtc->cursor_visible = visible;
7559 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7561 struct drm_device *dev = crtc->dev;
7562 struct drm_i915_private *dev_priv = dev->dev_private;
7563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564 int pipe = intel_crtc->pipe;
7565 bool visible = base != 0;
7567 if (intel_crtc->cursor_visible != visible) {
7568 int16_t width = intel_crtc->cursor_width;
7569 uint32_t cntl = I915_READ(CURCNTR(pipe));
7571 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7572 cntl |= MCURSOR_GAMMA_ENABLE;
7576 cntl |= CURSOR_MODE_64_ARGB_AX;
7579 cntl |= CURSOR_MODE_128_ARGB_AX;
7582 cntl |= CURSOR_MODE_256_ARGB_AX;
7588 cntl |= pipe << 28; /* Connect to correct pipe */
7590 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7591 cntl |= CURSOR_MODE_DISABLE;
7593 I915_WRITE(CURCNTR(pipe), cntl);
7595 intel_crtc->cursor_visible = visible;
7597 /* and commit changes on next vblank */
7598 POSTING_READ(CURCNTR(pipe));
7599 I915_WRITE(CURBASE(pipe), base);
7600 POSTING_READ(CURBASE(pipe));
7603 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7605 struct drm_device *dev = crtc->dev;
7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7608 int pipe = intel_crtc->pipe;
7609 bool visible = base != 0;
7611 if (intel_crtc->cursor_visible != visible) {
7612 int16_t width = intel_crtc->cursor_width;
7613 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7615 cntl &= ~CURSOR_MODE;
7616 cntl |= MCURSOR_GAMMA_ENABLE;
7619 cntl |= CURSOR_MODE_64_ARGB_AX;
7622 cntl |= CURSOR_MODE_128_ARGB_AX;
7625 cntl |= CURSOR_MODE_256_ARGB_AX;
7632 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7633 cntl |= CURSOR_MODE_DISABLE;
7635 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7636 cntl |= CURSOR_PIPE_CSC_ENABLE;
7637 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7639 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7641 intel_crtc->cursor_visible = visible;
7643 /* and commit changes on next vblank */
7644 POSTING_READ(CURCNTR_IVB(pipe));
7645 I915_WRITE(CURBASE_IVB(pipe), base);
7646 POSTING_READ(CURBASE_IVB(pipe));
7649 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7650 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7653 struct drm_device *dev = crtc->dev;
7654 struct drm_i915_private *dev_priv = dev->dev_private;
7655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7656 int pipe = intel_crtc->pipe;
7657 int x = intel_crtc->cursor_x;
7658 int y = intel_crtc->cursor_y;
7659 u32 base = 0, pos = 0;
7663 base = intel_crtc->cursor_addr;
7665 if (x >= intel_crtc->config.pipe_src_w)
7668 if (y >= intel_crtc->config.pipe_src_h)
7672 if (x + intel_crtc->cursor_width <= 0)
7675 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7678 pos |= x << CURSOR_X_SHIFT;
7681 if (y + intel_crtc->cursor_height <= 0)
7684 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7687 pos |= y << CURSOR_Y_SHIFT;
7689 visible = base != 0;
7690 if (!visible && !intel_crtc->cursor_visible)
7693 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7694 I915_WRITE(CURPOS_IVB(pipe), pos);
7695 ivb_update_cursor(crtc, base);
7697 I915_WRITE(CURPOS(pipe), pos);
7698 if (IS_845G(dev) || IS_I865G(dev))
7699 i845_update_cursor(crtc, base);
7701 i9xx_update_cursor(crtc, base);
7705 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7706 struct drm_file *file,
7708 uint32_t width, uint32_t height)
7710 struct drm_device *dev = crtc->dev;
7711 struct drm_i915_private *dev_priv = dev->dev_private;
7712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7713 struct drm_i915_gem_object *obj;
7718 /* if we want to turn off the cursor ignore width and height */
7720 DRM_DEBUG_KMS("cursor off\n");
7723 mutex_lock(&dev->struct_mutex);
7727 /* Check for which cursor types we support */
7728 if (!((width == 64 && height == 64) ||
7729 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
7730 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
7731 DRM_DEBUG("Cursor dimension not supported\n");
7735 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7736 if (&obj->base == NULL)
7739 if (obj->base.size < width * height * 4) {
7740 DRM_DEBUG_KMS("buffer is to small\n");
7745 /* we only need to pin inside GTT if cursor is non-phy */
7746 mutex_lock(&dev->struct_mutex);
7747 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7750 if (obj->tiling_mode) {
7751 DRM_DEBUG_KMS("cursor cannot be tiled\n");
7756 /* Note that the w/a also requires 2 PTE of padding following
7757 * the bo. We currently fill all unused PTE with the shadow
7758 * page and so we should always have valid PTE following the
7759 * cursor preventing the VT-d warning.
7762 if (need_vtd_wa(dev))
7763 alignment = 64*1024;
7765 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7767 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
7771 ret = i915_gem_object_put_fence(obj);
7773 DRM_DEBUG_KMS("failed to release fence for cursor");
7777 addr = i915_gem_obj_ggtt_offset(obj);
7779 int align = IS_I830(dev) ? 16 * 1024 : 256;
7780 ret = i915_gem_attach_phys_object(dev, obj,
7781 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7784 DRM_DEBUG_KMS("failed to attach phys object\n");
7787 addr = obj->phys_obj->handle->busaddr;
7791 I915_WRITE(CURSIZE, (height << 12) | width);
7794 if (intel_crtc->cursor_bo) {
7795 if (INTEL_INFO(dev)->cursor_needs_physical) {
7796 if (intel_crtc->cursor_bo != obj)
7797 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7799 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7800 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7803 mutex_unlock(&dev->struct_mutex);
7805 old_width = intel_crtc->cursor_width;
7807 intel_crtc->cursor_addr = addr;
7808 intel_crtc->cursor_bo = obj;
7809 intel_crtc->cursor_width = width;
7810 intel_crtc->cursor_height = height;
7812 if (intel_crtc->active) {
7813 if (old_width != width)
7814 intel_update_watermarks(crtc);
7815 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7820 i915_gem_object_unpin_from_display_plane(obj);
7822 mutex_unlock(&dev->struct_mutex);
7824 drm_gem_object_unreference_unlocked(&obj->base);
7828 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7832 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7833 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7835 if (intel_crtc->active)
7836 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7841 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7842 u16 *blue, uint32_t start, uint32_t size)
7844 int end = (start + size > 256) ? 256 : start + size, i;
7845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7847 for (i = start; i < end; i++) {
7848 intel_crtc->lut_r[i] = red[i] >> 8;
7849 intel_crtc->lut_g[i] = green[i] >> 8;
7850 intel_crtc->lut_b[i] = blue[i] >> 8;
7853 intel_crtc_load_lut(crtc);
7856 /* VESA 640x480x72Hz mode to set on the pipe */
7857 static struct drm_display_mode load_detect_mode = {
7858 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7859 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7862 struct drm_framebuffer *
7863 __intel_framebuffer_create(struct drm_device *dev,
7864 struct drm_mode_fb_cmd2 *mode_cmd,
7865 struct drm_i915_gem_object *obj)
7867 struct intel_framebuffer *intel_fb;
7870 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7872 drm_gem_object_unreference_unlocked(&obj->base);
7873 return ERR_PTR(-ENOMEM);
7876 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7880 return &intel_fb->base;
7882 drm_gem_object_unreference_unlocked(&obj->base);
7885 return ERR_PTR(ret);
7888 static struct drm_framebuffer *
7889 intel_framebuffer_create(struct drm_device *dev,
7890 struct drm_mode_fb_cmd2 *mode_cmd,
7891 struct drm_i915_gem_object *obj)
7893 struct drm_framebuffer *fb;
7896 ret = i915_mutex_lock_interruptible(dev);
7898 return ERR_PTR(ret);
7899 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7900 mutex_unlock(&dev->struct_mutex);
7906 intel_framebuffer_pitch_for_width(int width, int bpp)
7908 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7909 return ALIGN(pitch, 64);
7913 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7915 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7916 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7919 static struct drm_framebuffer *
7920 intel_framebuffer_create_for_mode(struct drm_device *dev,
7921 struct drm_display_mode *mode,
7924 struct drm_i915_gem_object *obj;
7925 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7927 obj = i915_gem_alloc_object(dev,
7928 intel_framebuffer_size_for_mode(mode, bpp));
7930 return ERR_PTR(-ENOMEM);
7932 mode_cmd.width = mode->hdisplay;
7933 mode_cmd.height = mode->vdisplay;
7934 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7936 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7938 return intel_framebuffer_create(dev, &mode_cmd, obj);
7941 static struct drm_framebuffer *
7942 mode_fits_in_fbdev(struct drm_device *dev,
7943 struct drm_display_mode *mode)
7945 #ifdef CONFIG_DRM_I915_FBDEV
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7947 struct drm_i915_gem_object *obj;
7948 struct drm_framebuffer *fb;
7950 if (!dev_priv->fbdev)
7953 if (!dev_priv->fbdev->fb)
7956 obj = dev_priv->fbdev->fb->obj;
7959 fb = &dev_priv->fbdev->fb->base;
7960 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7961 fb->bits_per_pixel))
7964 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7973 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7974 struct drm_display_mode *mode,
7975 struct intel_load_detect_pipe *old)
7977 struct intel_crtc *intel_crtc;
7978 struct intel_encoder *intel_encoder =
7979 intel_attached_encoder(connector);
7980 struct drm_crtc *possible_crtc;
7981 struct drm_encoder *encoder = &intel_encoder->base;
7982 struct drm_crtc *crtc = NULL;
7983 struct drm_device *dev = encoder->dev;
7984 struct drm_framebuffer *fb;
7987 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7988 connector->base.id, drm_get_connector_name(connector),
7989 encoder->base.id, drm_get_encoder_name(encoder));
7992 * Algorithm gets a little messy:
7994 * - if the connector already has an assigned crtc, use it (but make
7995 * sure it's on first)
7997 * - try to find the first unused crtc that can drive this connector,
7998 * and use that if we find one
8001 /* See if we already have a CRTC for this connector */
8002 if (encoder->crtc) {
8003 crtc = encoder->crtc;
8005 mutex_lock(&crtc->mutex);
8007 old->dpms_mode = connector->dpms;
8008 old->load_detect_temp = false;
8010 /* Make sure the crtc and connector are running */
8011 if (connector->dpms != DRM_MODE_DPMS_ON)
8012 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8017 /* Find an unused one (if possible) */
8018 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
8020 if (!(encoder->possible_crtcs & (1 << i)))
8022 if (!possible_crtc->enabled) {
8023 crtc = possible_crtc;
8029 * If we didn't find an unused CRTC, don't use any.
8032 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8036 mutex_lock(&crtc->mutex);
8037 intel_encoder->new_crtc = to_intel_crtc(crtc);
8038 to_intel_connector(connector)->new_encoder = intel_encoder;
8040 intel_crtc = to_intel_crtc(crtc);
8041 intel_crtc->new_enabled = true;
8042 intel_crtc->new_config = &intel_crtc->config;
8043 old->dpms_mode = connector->dpms;
8044 old->load_detect_temp = true;
8045 old->release_fb = NULL;
8048 mode = &load_detect_mode;
8050 /* We need a framebuffer large enough to accommodate all accesses
8051 * that the plane may generate whilst we perform load detection.
8052 * We can not rely on the fbcon either being present (we get called
8053 * during its initialisation to detect all boot displays, or it may
8054 * not even exist) or that it is large enough to satisfy the
8057 fb = mode_fits_in_fbdev(dev, mode);
8059 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8060 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8061 old->release_fb = fb;
8063 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8065 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8069 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8070 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8071 if (old->release_fb)
8072 old->release_fb->funcs->destroy(old->release_fb);
8076 /* let the connector get through one full cycle before testing */
8077 intel_wait_for_vblank(dev, intel_crtc->pipe);
8081 intel_crtc->new_enabled = crtc->enabled;
8082 if (intel_crtc->new_enabled)
8083 intel_crtc->new_config = &intel_crtc->config;
8085 intel_crtc->new_config = NULL;
8086 mutex_unlock(&crtc->mutex);
8090 void intel_release_load_detect_pipe(struct drm_connector *connector,
8091 struct intel_load_detect_pipe *old)
8093 struct intel_encoder *intel_encoder =
8094 intel_attached_encoder(connector);
8095 struct drm_encoder *encoder = &intel_encoder->base;
8096 struct drm_crtc *crtc = encoder->crtc;
8097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8099 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8100 connector->base.id, drm_get_connector_name(connector),
8101 encoder->base.id, drm_get_encoder_name(encoder));
8103 if (old->load_detect_temp) {
8104 to_intel_connector(connector)->new_encoder = NULL;
8105 intel_encoder->new_crtc = NULL;
8106 intel_crtc->new_enabled = false;
8107 intel_crtc->new_config = NULL;
8108 intel_set_mode(crtc, NULL, 0, 0, NULL);
8110 if (old->release_fb) {
8111 drm_framebuffer_unregister_private(old->release_fb);
8112 drm_framebuffer_unreference(old->release_fb);
8115 mutex_unlock(&crtc->mutex);
8119 /* Switch crtc and encoder back off if necessary */
8120 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8121 connector->funcs->dpms(connector, old->dpms_mode);
8123 mutex_unlock(&crtc->mutex);
8126 static int i9xx_pll_refclk(struct drm_device *dev,
8127 const struct intel_crtc_config *pipe_config)
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 u32 dpll = pipe_config->dpll_hw_state.dpll;
8132 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8133 return dev_priv->vbt.lvds_ssc_freq;
8134 else if (HAS_PCH_SPLIT(dev))
8136 else if (!IS_GEN2(dev))
8142 /* Returns the clock of the currently programmed mode of the given pipe. */
8143 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8144 struct intel_crtc_config *pipe_config)
8146 struct drm_device *dev = crtc->base.dev;
8147 struct drm_i915_private *dev_priv = dev->dev_private;
8148 int pipe = pipe_config->cpu_transcoder;
8149 u32 dpll = pipe_config->dpll_hw_state.dpll;
8151 intel_clock_t clock;
8152 int refclk = i9xx_pll_refclk(dev, pipe_config);
8154 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8155 fp = pipe_config->dpll_hw_state.fp0;
8157 fp = pipe_config->dpll_hw_state.fp1;
8159 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8160 if (IS_PINEVIEW(dev)) {
8161 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8162 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8164 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8165 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8168 if (!IS_GEN2(dev)) {
8169 if (IS_PINEVIEW(dev))
8170 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8171 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8173 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8174 DPLL_FPA01_P1_POST_DIV_SHIFT);
8176 switch (dpll & DPLL_MODE_MASK) {
8177 case DPLLB_MODE_DAC_SERIAL:
8178 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8181 case DPLLB_MODE_LVDS:
8182 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8186 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8187 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8191 if (IS_PINEVIEW(dev))
8192 pineview_clock(refclk, &clock);
8194 i9xx_clock(refclk, &clock);
8196 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8197 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8200 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8201 DPLL_FPA01_P1_POST_DIV_SHIFT);
8203 if (lvds & LVDS_CLKB_POWER_UP)
8208 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8211 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8212 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8214 if (dpll & PLL_P2_DIVIDE_BY_4)
8220 i9xx_clock(refclk, &clock);
8224 * This value includes pixel_multiplier. We will use
8225 * port_clock to compute adjusted_mode.crtc_clock in the
8226 * encoder's get_config() function.
8228 pipe_config->port_clock = clock.dot;
8231 int intel_dotclock_calculate(int link_freq,
8232 const struct intel_link_m_n *m_n)
8235 * The calculation for the data clock is:
8236 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8237 * But we want to avoid losing precison if possible, so:
8238 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8240 * and the link clock is simpler:
8241 * link_clock = (m * link_clock) / n
8247 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8250 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8251 struct intel_crtc_config *pipe_config)
8253 struct drm_device *dev = crtc->base.dev;
8255 /* read out port_clock from the DPLL */
8256 i9xx_crtc_clock_get(crtc, pipe_config);
8259 * This value does not include pixel_multiplier.
8260 * We will check that port_clock and adjusted_mode.crtc_clock
8261 * agree once we know their relationship in the encoder's
8262 * get_config() function.
8264 pipe_config->adjusted_mode.crtc_clock =
8265 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8266 &pipe_config->fdi_m_n);
8269 /** Returns the currently programmed mode of the given pipe. */
8270 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8271 struct drm_crtc *crtc)
8273 struct drm_i915_private *dev_priv = dev->dev_private;
8274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8275 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8276 struct drm_display_mode *mode;
8277 struct intel_crtc_config pipe_config;
8278 int htot = I915_READ(HTOTAL(cpu_transcoder));
8279 int hsync = I915_READ(HSYNC(cpu_transcoder));
8280 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8281 int vsync = I915_READ(VSYNC(cpu_transcoder));
8282 enum pipe pipe = intel_crtc->pipe;
8284 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8289 * Construct a pipe_config sufficient for getting the clock info
8290 * back out of crtc_clock_get.
8292 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8293 * to use a real value here instead.
8295 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8296 pipe_config.pixel_multiplier = 1;
8297 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8298 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8299 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8300 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8302 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8303 mode->hdisplay = (htot & 0xffff) + 1;
8304 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8305 mode->hsync_start = (hsync & 0xffff) + 1;
8306 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8307 mode->vdisplay = (vtot & 0xffff) + 1;
8308 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8309 mode->vsync_start = (vsync & 0xffff) + 1;
8310 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8312 drm_mode_set_name(mode);
8317 static void intel_increase_pllclock(struct drm_crtc *crtc)
8319 struct drm_device *dev = crtc->dev;
8320 struct drm_i915_private *dev_priv = dev->dev_private;
8321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8322 int pipe = intel_crtc->pipe;
8323 int dpll_reg = DPLL(pipe);
8326 if (HAS_PCH_SPLIT(dev))
8329 if (!dev_priv->lvds_downclock_avail)
8332 dpll = I915_READ(dpll_reg);
8333 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8334 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8336 assert_panel_unlocked(dev_priv, pipe);
8338 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8339 I915_WRITE(dpll_reg, dpll);
8340 intel_wait_for_vblank(dev, pipe);
8342 dpll = I915_READ(dpll_reg);
8343 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8344 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8348 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8350 struct drm_device *dev = crtc->dev;
8351 struct drm_i915_private *dev_priv = dev->dev_private;
8352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8354 if (HAS_PCH_SPLIT(dev))
8357 if (!dev_priv->lvds_downclock_avail)
8361 * Since this is called by a timer, we should never get here in
8364 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8365 int pipe = intel_crtc->pipe;
8366 int dpll_reg = DPLL(pipe);
8369 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8371 assert_panel_unlocked(dev_priv, pipe);
8373 dpll = I915_READ(dpll_reg);
8374 dpll |= DISPLAY_RATE_SELECT_FPA1;
8375 I915_WRITE(dpll_reg, dpll);
8376 intel_wait_for_vblank(dev, pipe);
8377 dpll = I915_READ(dpll_reg);
8378 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8379 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8384 void intel_mark_busy(struct drm_device *dev)
8386 struct drm_i915_private *dev_priv = dev->dev_private;
8388 if (dev_priv->mm.busy)
8391 intel_runtime_pm_get(dev_priv);
8392 i915_update_gfx_val(dev_priv);
8393 dev_priv->mm.busy = true;
8396 void intel_mark_idle(struct drm_device *dev)
8398 struct drm_i915_private *dev_priv = dev->dev_private;
8399 struct drm_crtc *crtc;
8401 if (!dev_priv->mm.busy)
8404 dev_priv->mm.busy = false;
8406 if (!i915.powersave)
8409 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8410 if (!crtc->primary->fb)
8413 intel_decrease_pllclock(crtc);
8416 if (INTEL_INFO(dev)->gen >= 6)
8417 gen6_rps_idle(dev->dev_private);
8420 intel_runtime_pm_put(dev_priv);
8423 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8424 struct intel_ring_buffer *ring)
8426 struct drm_device *dev = obj->base.dev;
8427 struct drm_crtc *crtc;
8429 if (!i915.powersave)
8432 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8433 if (!crtc->primary->fb)
8436 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8439 intel_increase_pllclock(crtc);
8440 if (ring && intel_fbc_enabled(dev))
8441 ring->fbc_dirty = true;
8445 static void intel_crtc_destroy(struct drm_crtc *crtc)
8447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8448 struct drm_device *dev = crtc->dev;
8449 struct intel_unpin_work *work;
8450 unsigned long flags;
8452 spin_lock_irqsave(&dev->event_lock, flags);
8453 work = intel_crtc->unpin_work;
8454 intel_crtc->unpin_work = NULL;
8455 spin_unlock_irqrestore(&dev->event_lock, flags);
8458 cancel_work_sync(&work->work);
8462 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8464 drm_crtc_cleanup(crtc);
8469 static void intel_unpin_work_fn(struct work_struct *__work)
8471 struct intel_unpin_work *work =
8472 container_of(__work, struct intel_unpin_work, work);
8473 struct drm_device *dev = work->crtc->dev;
8475 mutex_lock(&dev->struct_mutex);
8476 intel_unpin_fb_obj(work->old_fb_obj);
8477 drm_gem_object_unreference(&work->pending_flip_obj->base);
8478 drm_gem_object_unreference(&work->old_fb_obj->base);
8480 intel_update_fbc(dev);
8481 mutex_unlock(&dev->struct_mutex);
8483 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8484 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8489 static void do_intel_finish_page_flip(struct drm_device *dev,
8490 struct drm_crtc *crtc)
8492 struct drm_i915_private *dev_priv = dev->dev_private;
8493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8494 struct intel_unpin_work *work;
8495 unsigned long flags;
8497 /* Ignore early vblank irqs */
8498 if (intel_crtc == NULL)
8501 spin_lock_irqsave(&dev->event_lock, flags);
8502 work = intel_crtc->unpin_work;
8504 /* Ensure we don't miss a work->pending update ... */
8507 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8508 spin_unlock_irqrestore(&dev->event_lock, flags);
8512 /* and that the unpin work is consistent wrt ->pending. */
8515 intel_crtc->unpin_work = NULL;
8518 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8520 drm_vblank_put(dev, intel_crtc->pipe);
8522 spin_unlock_irqrestore(&dev->event_lock, flags);
8524 wake_up_all(&dev_priv->pending_flip_queue);
8526 queue_work(dev_priv->wq, &work->work);
8528 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8531 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8533 struct drm_i915_private *dev_priv = dev->dev_private;
8534 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8536 do_intel_finish_page_flip(dev, crtc);
8539 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8541 struct drm_i915_private *dev_priv = dev->dev_private;
8542 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8544 do_intel_finish_page_flip(dev, crtc);
8547 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8549 struct drm_i915_private *dev_priv = dev->dev_private;
8550 struct intel_crtc *intel_crtc =
8551 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8552 unsigned long flags;
8554 /* NB: An MMIO update of the plane base pointer will also
8555 * generate a page-flip completion irq, i.e. every modeset
8556 * is also accompanied by a spurious intel_prepare_page_flip().
8558 spin_lock_irqsave(&dev->event_lock, flags);
8559 if (intel_crtc->unpin_work)
8560 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8561 spin_unlock_irqrestore(&dev->event_lock, flags);
8564 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8566 /* Ensure that the work item is consistent when activating it ... */
8568 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8569 /* and that it is marked active as soon as the irq could fire. */
8573 static int intel_gen2_queue_flip(struct drm_device *dev,
8574 struct drm_crtc *crtc,
8575 struct drm_framebuffer *fb,
8576 struct drm_i915_gem_object *obj,
8579 struct drm_i915_private *dev_priv = dev->dev_private;
8580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8582 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8585 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8589 ret = intel_ring_begin(ring, 6);
8593 /* Can't queue multiple flips, so wait for the previous
8594 * one to finish before executing the next.
8596 if (intel_crtc->plane)
8597 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8599 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8600 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8601 intel_ring_emit(ring, MI_NOOP);
8602 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8603 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8604 intel_ring_emit(ring, fb->pitches[0]);
8605 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8606 intel_ring_emit(ring, 0); /* aux display base address, unused */
8608 intel_mark_page_flip_active(intel_crtc);
8609 __intel_ring_advance(ring);
8613 intel_unpin_fb_obj(obj);
8618 static int intel_gen3_queue_flip(struct drm_device *dev,
8619 struct drm_crtc *crtc,
8620 struct drm_framebuffer *fb,
8621 struct drm_i915_gem_object *obj,
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8627 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8630 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8634 ret = intel_ring_begin(ring, 6);
8638 if (intel_crtc->plane)
8639 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8641 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8642 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8643 intel_ring_emit(ring, MI_NOOP);
8644 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8645 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8646 intel_ring_emit(ring, fb->pitches[0]);
8647 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8648 intel_ring_emit(ring, MI_NOOP);
8650 intel_mark_page_flip_active(intel_crtc);
8651 __intel_ring_advance(ring);
8655 intel_unpin_fb_obj(obj);
8660 static int intel_gen4_queue_flip(struct drm_device *dev,
8661 struct drm_crtc *crtc,
8662 struct drm_framebuffer *fb,
8663 struct drm_i915_gem_object *obj,
8666 struct drm_i915_private *dev_priv = dev->dev_private;
8667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8668 uint32_t pf, pipesrc;
8669 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8672 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8676 ret = intel_ring_begin(ring, 4);
8680 /* i965+ uses the linear or tiled offsets from the
8681 * Display Registers (which do not change across a page-flip)
8682 * so we need only reprogram the base address.
8684 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8685 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8686 intel_ring_emit(ring, fb->pitches[0]);
8687 intel_ring_emit(ring,
8688 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8691 /* XXX Enabling the panel-fitter across page-flip is so far
8692 * untested on non-native modes, so ignore it for now.
8693 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8696 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8697 intel_ring_emit(ring, pf | pipesrc);
8699 intel_mark_page_flip_active(intel_crtc);
8700 __intel_ring_advance(ring);
8704 intel_unpin_fb_obj(obj);
8709 static int intel_gen6_queue_flip(struct drm_device *dev,
8710 struct drm_crtc *crtc,
8711 struct drm_framebuffer *fb,
8712 struct drm_i915_gem_object *obj,
8715 struct drm_i915_private *dev_priv = dev->dev_private;
8716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8717 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8718 uint32_t pf, pipesrc;
8721 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8725 ret = intel_ring_begin(ring, 4);
8729 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8730 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8731 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8732 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8734 /* Contrary to the suggestions in the documentation,
8735 * "Enable Panel Fitter" does not seem to be required when page
8736 * flipping with a non-native mode, and worse causes a normal
8738 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8741 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8742 intel_ring_emit(ring, pf | pipesrc);
8744 intel_mark_page_flip_active(intel_crtc);
8745 __intel_ring_advance(ring);
8749 intel_unpin_fb_obj(obj);
8754 static int intel_gen7_queue_flip(struct drm_device *dev,
8755 struct drm_crtc *crtc,
8756 struct drm_framebuffer *fb,
8757 struct drm_i915_gem_object *obj,
8760 struct drm_i915_private *dev_priv = dev->dev_private;
8761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8762 struct intel_ring_buffer *ring;
8763 uint32_t plane_bit = 0;
8767 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8768 ring = &dev_priv->ring[BCS];
8770 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8774 switch(intel_crtc->plane) {
8776 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8779 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8782 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8785 WARN_ONCE(1, "unknown plane in flip command\n");
8791 if (ring->id == RCS) {
8794 * On Gen 8, SRM is now taking an extra dword to accommodate
8795 * 48bits addresses, and we need a NOOP for the batch size to
8803 * BSpec MI_DISPLAY_FLIP for IVB:
8804 * "The full packet must be contained within the same cache line."
8806 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
8807 * cacheline, if we ever start emitting more commands before
8808 * the MI_DISPLAY_FLIP we may need to first emit everything else,
8809 * then do the cacheline alignment, and finally emit the
8812 ret = intel_ring_cacheline_align(ring);
8816 ret = intel_ring_begin(ring, len);
8820 /* Unmask the flip-done completion message. Note that the bspec says that
8821 * we should do this for both the BCS and RCS, and that we must not unmask
8822 * more than one flip event at any time (or ensure that one flip message
8823 * can be sent by waiting for flip-done prior to queueing new flips).
8824 * Experimentation says that BCS works despite DERRMR masking all
8825 * flip-done completion events and that unmasking all planes at once
8826 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8827 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8829 if (ring->id == RCS) {
8830 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8831 intel_ring_emit(ring, DERRMR);
8832 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8833 DERRMR_PIPEB_PRI_FLIP_DONE |
8834 DERRMR_PIPEC_PRI_FLIP_DONE));
8836 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
8837 MI_SRM_LRM_GLOBAL_GTT);
8839 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
8840 MI_SRM_LRM_GLOBAL_GTT);
8841 intel_ring_emit(ring, DERRMR);
8842 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8844 intel_ring_emit(ring, 0);
8845 intel_ring_emit(ring, MI_NOOP);
8849 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8850 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8851 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8852 intel_ring_emit(ring, (MI_NOOP));
8854 intel_mark_page_flip_active(intel_crtc);
8855 __intel_ring_advance(ring);
8859 intel_unpin_fb_obj(obj);
8864 static int intel_default_queue_flip(struct drm_device *dev,
8865 struct drm_crtc *crtc,
8866 struct drm_framebuffer *fb,
8867 struct drm_i915_gem_object *obj,
8873 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8874 struct drm_framebuffer *fb,
8875 struct drm_pending_vblank_event *event,
8876 uint32_t page_flip_flags)
8878 struct drm_device *dev = crtc->dev;
8879 struct drm_i915_private *dev_priv = dev->dev_private;
8880 struct drm_framebuffer *old_fb = crtc->primary->fb;
8881 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8883 struct intel_unpin_work *work;
8884 unsigned long flags;
8887 /* Can't change pixel format via MI display flips. */
8888 if (fb->pixel_format != crtc->primary->fb->pixel_format)
8892 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8893 * Note that pitch changes could also affect these register.
8895 if (INTEL_INFO(dev)->gen > 3 &&
8896 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
8897 fb->pitches[0] != crtc->primary->fb->pitches[0]))
8900 if (i915_terminally_wedged(&dev_priv->gpu_error))
8903 work = kzalloc(sizeof(*work), GFP_KERNEL);
8907 work->event = event;
8909 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8910 INIT_WORK(&work->work, intel_unpin_work_fn);
8912 ret = drm_vblank_get(dev, intel_crtc->pipe);
8916 /* We borrow the event spin lock for protecting unpin_work */
8917 spin_lock_irqsave(&dev->event_lock, flags);
8918 if (intel_crtc->unpin_work) {
8919 spin_unlock_irqrestore(&dev->event_lock, flags);
8921 drm_vblank_put(dev, intel_crtc->pipe);
8923 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8926 intel_crtc->unpin_work = work;
8927 spin_unlock_irqrestore(&dev->event_lock, flags);
8929 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8930 flush_workqueue(dev_priv->wq);
8932 ret = i915_mutex_lock_interruptible(dev);
8936 /* Reference the objects for the scheduled work. */
8937 drm_gem_object_reference(&work->old_fb_obj->base);
8938 drm_gem_object_reference(&obj->base);
8940 crtc->primary->fb = fb;
8942 work->pending_flip_obj = obj;
8944 work->enable_stall_check = true;
8946 atomic_inc(&intel_crtc->unpin_work_count);
8947 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8949 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8951 goto cleanup_pending;
8953 intel_disable_fbc(dev);
8954 intel_mark_fb_busy(obj, NULL);
8955 mutex_unlock(&dev->struct_mutex);
8957 trace_i915_flip_request(intel_crtc->plane, obj);
8962 atomic_dec(&intel_crtc->unpin_work_count);
8963 crtc->primary->fb = old_fb;
8964 drm_gem_object_unreference(&work->old_fb_obj->base);
8965 drm_gem_object_unreference(&obj->base);
8966 mutex_unlock(&dev->struct_mutex);
8969 spin_lock_irqsave(&dev->event_lock, flags);
8970 intel_crtc->unpin_work = NULL;
8971 spin_unlock_irqrestore(&dev->event_lock, flags);
8973 drm_vblank_put(dev, intel_crtc->pipe);
8979 intel_crtc_wait_for_pending_flips(crtc);
8980 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
8981 if (ret == 0 && event)
8982 drm_send_vblank_event(dev, intel_crtc->pipe, event);
8987 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8988 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8989 .load_lut = intel_crtc_load_lut,
8993 * intel_modeset_update_staged_output_state
8995 * Updates the staged output configuration state, e.g. after we've read out the
8998 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9000 struct intel_crtc *crtc;
9001 struct intel_encoder *encoder;
9002 struct intel_connector *connector;
9004 list_for_each_entry(connector, &dev->mode_config.connector_list,
9006 connector->new_encoder =
9007 to_intel_encoder(connector->base.encoder);
9010 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9013 to_intel_crtc(encoder->base.crtc);
9016 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9018 crtc->new_enabled = crtc->base.enabled;
9020 if (crtc->new_enabled)
9021 crtc->new_config = &crtc->config;
9023 crtc->new_config = NULL;
9028 * intel_modeset_commit_output_state
9030 * This function copies the stage display pipe configuration to the real one.
9032 static void intel_modeset_commit_output_state(struct drm_device *dev)
9034 struct intel_crtc *crtc;
9035 struct intel_encoder *encoder;
9036 struct intel_connector *connector;
9038 list_for_each_entry(connector, &dev->mode_config.connector_list,
9040 connector->base.encoder = &connector->new_encoder->base;
9043 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9045 encoder->base.crtc = &encoder->new_crtc->base;
9048 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9050 crtc->base.enabled = crtc->new_enabled;
9055 connected_sink_compute_bpp(struct intel_connector * connector,
9056 struct intel_crtc_config *pipe_config)
9058 int bpp = pipe_config->pipe_bpp;
9060 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9061 connector->base.base.id,
9062 drm_get_connector_name(&connector->base));
9064 /* Don't use an invalid EDID bpc value */
9065 if (connector->base.display_info.bpc &&
9066 connector->base.display_info.bpc * 3 < bpp) {
9067 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9068 bpp, connector->base.display_info.bpc*3);
9069 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9072 /* Clamp bpp to 8 on screens without EDID 1.4 */
9073 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9074 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9076 pipe_config->pipe_bpp = 24;
9081 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9082 struct drm_framebuffer *fb,
9083 struct intel_crtc_config *pipe_config)
9085 struct drm_device *dev = crtc->base.dev;
9086 struct intel_connector *connector;
9089 switch (fb->pixel_format) {
9091 bpp = 8*3; /* since we go through a colormap */
9093 case DRM_FORMAT_XRGB1555:
9094 case DRM_FORMAT_ARGB1555:
9095 /* checked in intel_framebuffer_init already */
9096 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9098 case DRM_FORMAT_RGB565:
9099 bpp = 6*3; /* min is 18bpp */
9101 case DRM_FORMAT_XBGR8888:
9102 case DRM_FORMAT_ABGR8888:
9103 /* checked in intel_framebuffer_init already */
9104 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9106 case DRM_FORMAT_XRGB8888:
9107 case DRM_FORMAT_ARGB8888:
9110 case DRM_FORMAT_XRGB2101010:
9111 case DRM_FORMAT_ARGB2101010:
9112 case DRM_FORMAT_XBGR2101010:
9113 case DRM_FORMAT_ABGR2101010:
9114 /* checked in intel_framebuffer_init already */
9115 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9119 /* TODO: gen4+ supports 16 bpc floating point, too. */
9121 DRM_DEBUG_KMS("unsupported depth\n");
9125 pipe_config->pipe_bpp = bpp;
9127 /* Clamp display bpp to EDID value */
9128 list_for_each_entry(connector, &dev->mode_config.connector_list,
9130 if (!connector->new_encoder ||
9131 connector->new_encoder->new_crtc != crtc)
9134 connected_sink_compute_bpp(connector, pipe_config);
9140 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9142 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9143 "type: 0x%x flags: 0x%x\n",
9145 mode->crtc_hdisplay, mode->crtc_hsync_start,
9146 mode->crtc_hsync_end, mode->crtc_htotal,
9147 mode->crtc_vdisplay, mode->crtc_vsync_start,
9148 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9151 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9152 struct intel_crtc_config *pipe_config,
9153 const char *context)
9155 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9156 context, pipe_name(crtc->pipe));
9158 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9159 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9160 pipe_config->pipe_bpp, pipe_config->dither);
9161 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9162 pipe_config->has_pch_encoder,
9163 pipe_config->fdi_lanes,
9164 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9165 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9166 pipe_config->fdi_m_n.tu);
9167 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9168 pipe_config->has_dp_encoder,
9169 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9170 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9171 pipe_config->dp_m_n.tu);
9172 DRM_DEBUG_KMS("requested mode:\n");
9173 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9174 DRM_DEBUG_KMS("adjusted mode:\n");
9175 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9176 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9177 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9178 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9179 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9180 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9181 pipe_config->gmch_pfit.control,
9182 pipe_config->gmch_pfit.pgm_ratios,
9183 pipe_config->gmch_pfit.lvds_border_bits);
9184 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9185 pipe_config->pch_pfit.pos,
9186 pipe_config->pch_pfit.size,
9187 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9188 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9189 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9192 static bool encoders_cloneable(const struct intel_encoder *a,
9193 const struct intel_encoder *b)
9195 /* masks could be asymmetric, so check both ways */
9196 return a == b || (a->cloneable & (1 << b->type) &&
9197 b->cloneable & (1 << a->type));
9200 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9201 struct intel_encoder *encoder)
9203 struct drm_device *dev = crtc->base.dev;
9204 struct intel_encoder *source_encoder;
9206 list_for_each_entry(source_encoder,
9207 &dev->mode_config.encoder_list, base.head) {
9208 if (source_encoder->new_crtc != crtc)
9211 if (!encoders_cloneable(encoder, source_encoder))
9218 static bool check_encoder_cloning(struct intel_crtc *crtc)
9220 struct drm_device *dev = crtc->base.dev;
9221 struct intel_encoder *encoder;
9223 list_for_each_entry(encoder,
9224 &dev->mode_config.encoder_list, base.head) {
9225 if (encoder->new_crtc != crtc)
9228 if (!check_single_encoder_cloning(crtc, encoder))
9235 static struct intel_crtc_config *
9236 intel_modeset_pipe_config(struct drm_crtc *crtc,
9237 struct drm_framebuffer *fb,
9238 struct drm_display_mode *mode)
9240 struct drm_device *dev = crtc->dev;
9241 struct intel_encoder *encoder;
9242 struct intel_crtc_config *pipe_config;
9243 int plane_bpp, ret = -EINVAL;
9246 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9247 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9248 return ERR_PTR(-EINVAL);
9251 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9253 return ERR_PTR(-ENOMEM);
9255 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9256 drm_mode_copy(&pipe_config->requested_mode, mode);
9258 pipe_config->cpu_transcoder =
9259 (enum transcoder) to_intel_crtc(crtc)->pipe;
9260 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9263 * Sanitize sync polarity flags based on requested ones. If neither
9264 * positive or negative polarity is requested, treat this as meaning
9265 * negative polarity.
9267 if (!(pipe_config->adjusted_mode.flags &
9268 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9269 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9271 if (!(pipe_config->adjusted_mode.flags &
9272 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9273 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9275 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9276 * plane pixel format and any sink constraints into account. Returns the
9277 * source plane bpp so that dithering can be selected on mismatches
9278 * after encoders and crtc also have had their say. */
9279 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9285 * Determine the real pipe dimensions. Note that stereo modes can
9286 * increase the actual pipe size due to the frame doubling and
9287 * insertion of additional space for blanks between the frame. This
9288 * is stored in the crtc timings. We use the requested mode to do this
9289 * computation to clearly distinguish it from the adjusted mode, which
9290 * can be changed by the connectors in the below retry loop.
9292 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9293 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9294 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9297 /* Ensure the port clock defaults are reset when retrying. */
9298 pipe_config->port_clock = 0;
9299 pipe_config->pixel_multiplier = 1;
9301 /* Fill in default crtc timings, allow encoders to overwrite them. */
9302 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9304 /* Pass our mode to the connectors and the CRTC to give them a chance to
9305 * adjust it according to limitations or connector properties, and also
9306 * a chance to reject the mode entirely.
9308 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9311 if (&encoder->new_crtc->base != crtc)
9314 if (!(encoder->compute_config(encoder, pipe_config))) {
9315 DRM_DEBUG_KMS("Encoder config failure\n");
9320 /* Set default port clock if not overwritten by the encoder. Needs to be
9321 * done afterwards in case the encoder adjusts the mode. */
9322 if (!pipe_config->port_clock)
9323 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9324 * pipe_config->pixel_multiplier;
9326 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9328 DRM_DEBUG_KMS("CRTC fixup failed\n");
9333 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9338 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9343 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9344 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9345 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9350 return ERR_PTR(ret);
9353 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9354 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9356 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9357 unsigned *prepare_pipes, unsigned *disable_pipes)
9359 struct intel_crtc *intel_crtc;
9360 struct drm_device *dev = crtc->dev;
9361 struct intel_encoder *encoder;
9362 struct intel_connector *connector;
9363 struct drm_crtc *tmp_crtc;
9365 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9367 /* Check which crtcs have changed outputs connected to them, these need
9368 * to be part of the prepare_pipes mask. We don't (yet) support global
9369 * modeset across multiple crtcs, so modeset_pipes will only have one
9370 * bit set at most. */
9371 list_for_each_entry(connector, &dev->mode_config.connector_list,
9373 if (connector->base.encoder == &connector->new_encoder->base)
9376 if (connector->base.encoder) {
9377 tmp_crtc = connector->base.encoder->crtc;
9379 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9382 if (connector->new_encoder)
9384 1 << connector->new_encoder->new_crtc->pipe;
9387 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9389 if (encoder->base.crtc == &encoder->new_crtc->base)
9392 if (encoder->base.crtc) {
9393 tmp_crtc = encoder->base.crtc;
9395 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9398 if (encoder->new_crtc)
9399 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9402 /* Check for pipes that will be enabled/disabled ... */
9403 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9405 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9408 if (!intel_crtc->new_enabled)
9409 *disable_pipes |= 1 << intel_crtc->pipe;
9411 *prepare_pipes |= 1 << intel_crtc->pipe;
9415 /* set_mode is also used to update properties on life display pipes. */
9416 intel_crtc = to_intel_crtc(crtc);
9417 if (intel_crtc->new_enabled)
9418 *prepare_pipes |= 1 << intel_crtc->pipe;
9421 * For simplicity do a full modeset on any pipe where the output routing
9422 * changed. We could be more clever, but that would require us to be
9423 * more careful with calling the relevant encoder->mode_set functions.
9426 *modeset_pipes = *prepare_pipes;
9428 /* ... and mask these out. */
9429 *modeset_pipes &= ~(*disable_pipes);
9430 *prepare_pipes &= ~(*disable_pipes);
9433 * HACK: We don't (yet) fully support global modesets. intel_set_config
9434 * obies this rule, but the modeset restore mode of
9435 * intel_modeset_setup_hw_state does not.
9437 *modeset_pipes &= 1 << intel_crtc->pipe;
9438 *prepare_pipes &= 1 << intel_crtc->pipe;
9440 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9441 *modeset_pipes, *prepare_pipes, *disable_pipes);
9444 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9446 struct drm_encoder *encoder;
9447 struct drm_device *dev = crtc->dev;
9449 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9450 if (encoder->crtc == crtc)
9457 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9459 struct intel_encoder *intel_encoder;
9460 struct intel_crtc *intel_crtc;
9461 struct drm_connector *connector;
9463 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9465 if (!intel_encoder->base.crtc)
9468 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9470 if (prepare_pipes & (1 << intel_crtc->pipe))
9471 intel_encoder->connectors_active = false;
9474 intel_modeset_commit_output_state(dev);
9476 /* Double check state. */
9477 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9479 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9480 WARN_ON(intel_crtc->new_config &&
9481 intel_crtc->new_config != &intel_crtc->config);
9482 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9485 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9486 if (!connector->encoder || !connector->encoder->crtc)
9489 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9491 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9492 struct drm_property *dpms_property =
9493 dev->mode_config.dpms_property;
9495 connector->dpms = DRM_MODE_DPMS_ON;
9496 drm_object_property_set_value(&connector->base,
9500 intel_encoder = to_intel_encoder(connector->encoder);
9501 intel_encoder->connectors_active = true;
9507 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9511 if (clock1 == clock2)
9514 if (!clock1 || !clock2)
9517 diff = abs(clock1 - clock2);
9519 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9525 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9526 list_for_each_entry((intel_crtc), \
9527 &(dev)->mode_config.crtc_list, \
9529 if (mask & (1 <<(intel_crtc)->pipe))
9532 intel_pipe_config_compare(struct drm_device *dev,
9533 struct intel_crtc_config *current_config,
9534 struct intel_crtc_config *pipe_config)
9536 #define PIPE_CONF_CHECK_X(name) \
9537 if (current_config->name != pipe_config->name) { \
9538 DRM_ERROR("mismatch in " #name " " \
9539 "(expected 0x%08x, found 0x%08x)\n", \
9540 current_config->name, \
9541 pipe_config->name); \
9545 #define PIPE_CONF_CHECK_I(name) \
9546 if (current_config->name != pipe_config->name) { \
9547 DRM_ERROR("mismatch in " #name " " \
9548 "(expected %i, found %i)\n", \
9549 current_config->name, \
9550 pipe_config->name); \
9554 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9555 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9556 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9557 "(expected %i, found %i)\n", \
9558 current_config->name & (mask), \
9559 pipe_config->name & (mask)); \
9563 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9564 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9565 DRM_ERROR("mismatch in " #name " " \
9566 "(expected %i, found %i)\n", \
9567 current_config->name, \
9568 pipe_config->name); \
9572 #define PIPE_CONF_QUIRK(quirk) \
9573 ((current_config->quirks | pipe_config->quirks) & (quirk))
9575 PIPE_CONF_CHECK_I(cpu_transcoder);
9577 PIPE_CONF_CHECK_I(has_pch_encoder);
9578 PIPE_CONF_CHECK_I(fdi_lanes);
9579 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9580 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9581 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9582 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9583 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9585 PIPE_CONF_CHECK_I(has_dp_encoder);
9586 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9587 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9588 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9589 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9590 PIPE_CONF_CHECK_I(dp_m_n.tu);
9592 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9593 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9594 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9595 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9596 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9597 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9602 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9603 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9604 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9606 PIPE_CONF_CHECK_I(pixel_multiplier);
9608 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9609 DRM_MODE_FLAG_INTERLACE);
9611 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9612 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9613 DRM_MODE_FLAG_PHSYNC);
9614 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9615 DRM_MODE_FLAG_NHSYNC);
9616 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9617 DRM_MODE_FLAG_PVSYNC);
9618 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9619 DRM_MODE_FLAG_NVSYNC);
9622 PIPE_CONF_CHECK_I(pipe_src_w);
9623 PIPE_CONF_CHECK_I(pipe_src_h);
9626 * FIXME: BIOS likes to set up a cloned config with lvds+external
9627 * screen. Since we don't yet re-compute the pipe config when moving
9628 * just the lvds port away to another pipe the sw tracking won't match.
9630 * Proper atomic modesets with recomputed global state will fix this.
9631 * Until then just don't check gmch state for inherited modes.
9633 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9634 PIPE_CONF_CHECK_I(gmch_pfit.control);
9635 /* pfit ratios are autocomputed by the hw on gen4+ */
9636 if (INTEL_INFO(dev)->gen < 4)
9637 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9638 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9641 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9642 if (current_config->pch_pfit.enabled) {
9643 PIPE_CONF_CHECK_I(pch_pfit.pos);
9644 PIPE_CONF_CHECK_I(pch_pfit.size);
9647 /* BDW+ don't expose a synchronous way to read the state */
9648 if (IS_HASWELL(dev))
9649 PIPE_CONF_CHECK_I(ips_enabled);
9651 PIPE_CONF_CHECK_I(double_wide);
9653 PIPE_CONF_CHECK_I(shared_dpll);
9654 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9655 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9656 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9657 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9659 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9660 PIPE_CONF_CHECK_I(pipe_bpp);
9662 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9663 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9665 #undef PIPE_CONF_CHECK_X
9666 #undef PIPE_CONF_CHECK_I
9667 #undef PIPE_CONF_CHECK_FLAGS
9668 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9669 #undef PIPE_CONF_QUIRK
9675 check_connector_state(struct drm_device *dev)
9677 struct intel_connector *connector;
9679 list_for_each_entry(connector, &dev->mode_config.connector_list,
9681 /* This also checks the encoder/connector hw state with the
9682 * ->get_hw_state callbacks. */
9683 intel_connector_check_state(connector);
9685 WARN(&connector->new_encoder->base != connector->base.encoder,
9686 "connector's staged encoder doesn't match current encoder\n");
9691 check_encoder_state(struct drm_device *dev)
9693 struct intel_encoder *encoder;
9694 struct intel_connector *connector;
9696 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9698 bool enabled = false;
9699 bool active = false;
9700 enum pipe pipe, tracked_pipe;
9702 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9703 encoder->base.base.id,
9704 drm_get_encoder_name(&encoder->base));
9706 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9707 "encoder's stage crtc doesn't match current crtc\n");
9708 WARN(encoder->connectors_active && !encoder->base.crtc,
9709 "encoder's active_connectors set, but no crtc\n");
9711 list_for_each_entry(connector, &dev->mode_config.connector_list,
9713 if (connector->base.encoder != &encoder->base)
9716 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9719 WARN(!!encoder->base.crtc != enabled,
9720 "encoder's enabled state mismatch "
9721 "(expected %i, found %i)\n",
9722 !!encoder->base.crtc, enabled);
9723 WARN(active && !encoder->base.crtc,
9724 "active encoder with no crtc\n");
9726 WARN(encoder->connectors_active != active,
9727 "encoder's computed active state doesn't match tracked active state "
9728 "(expected %i, found %i)\n", active, encoder->connectors_active);
9730 active = encoder->get_hw_state(encoder, &pipe);
9731 WARN(active != encoder->connectors_active,
9732 "encoder's hw state doesn't match sw tracking "
9733 "(expected %i, found %i)\n",
9734 encoder->connectors_active, active);
9736 if (!encoder->base.crtc)
9739 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9740 WARN(active && pipe != tracked_pipe,
9741 "active encoder's pipe doesn't match"
9742 "(expected %i, found %i)\n",
9743 tracked_pipe, pipe);
9749 check_crtc_state(struct drm_device *dev)
9751 struct drm_i915_private *dev_priv = dev->dev_private;
9752 struct intel_crtc *crtc;
9753 struct intel_encoder *encoder;
9754 struct intel_crtc_config pipe_config;
9756 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9758 bool enabled = false;
9759 bool active = false;
9761 memset(&pipe_config, 0, sizeof(pipe_config));
9763 DRM_DEBUG_KMS("[CRTC:%d]\n",
9764 crtc->base.base.id);
9766 WARN(crtc->active && !crtc->base.enabled,
9767 "active crtc, but not enabled in sw tracking\n");
9769 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9771 if (encoder->base.crtc != &crtc->base)
9774 if (encoder->connectors_active)
9778 WARN(active != crtc->active,
9779 "crtc's computed active state doesn't match tracked active state "
9780 "(expected %i, found %i)\n", active, crtc->active);
9781 WARN(enabled != crtc->base.enabled,
9782 "crtc's computed enabled state doesn't match tracked enabled state "
9783 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9785 active = dev_priv->display.get_pipe_config(crtc,
9788 /* hw state is inconsistent with the pipe A quirk */
9789 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9790 active = crtc->active;
9792 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9795 if (encoder->base.crtc != &crtc->base)
9797 if (encoder->get_hw_state(encoder, &pipe))
9798 encoder->get_config(encoder, &pipe_config);
9801 WARN(crtc->active != active,
9802 "crtc active state doesn't match with hw state "
9803 "(expected %i, found %i)\n", crtc->active, active);
9806 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9807 WARN(1, "pipe state doesn't match!\n");
9808 intel_dump_pipe_config(crtc, &pipe_config,
9810 intel_dump_pipe_config(crtc, &crtc->config,
9817 check_shared_dpll_state(struct drm_device *dev)
9819 struct drm_i915_private *dev_priv = dev->dev_private;
9820 struct intel_crtc *crtc;
9821 struct intel_dpll_hw_state dpll_hw_state;
9824 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9825 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9826 int enabled_crtcs = 0, active_crtcs = 0;
9829 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9831 DRM_DEBUG_KMS("%s\n", pll->name);
9833 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9835 WARN(pll->active > pll->refcount,
9836 "more active pll users than references: %i vs %i\n",
9837 pll->active, pll->refcount);
9838 WARN(pll->active && !pll->on,
9839 "pll in active use but not on in sw tracking\n");
9840 WARN(pll->on && !pll->active,
9841 "pll in on but not on in use in sw tracking\n");
9842 WARN(pll->on != active,
9843 "pll on state mismatch (expected %i, found %i)\n",
9846 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9848 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9850 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9853 WARN(pll->active != active_crtcs,
9854 "pll active crtcs mismatch (expected %i, found %i)\n",
9855 pll->active, active_crtcs);
9856 WARN(pll->refcount != enabled_crtcs,
9857 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9858 pll->refcount, enabled_crtcs);
9860 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9861 sizeof(dpll_hw_state)),
9862 "pll hw state mismatch\n");
9867 intel_modeset_check_state(struct drm_device *dev)
9869 check_connector_state(dev);
9870 check_encoder_state(dev);
9871 check_crtc_state(dev);
9872 check_shared_dpll_state(dev);
9875 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9879 * FDI already provided one idea for the dotclock.
9880 * Yell if the encoder disagrees.
9882 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9883 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9884 pipe_config->adjusted_mode.crtc_clock, dotclock);
9887 static int __intel_set_mode(struct drm_crtc *crtc,
9888 struct drm_display_mode *mode,
9889 int x, int y, struct drm_framebuffer *fb)
9891 struct drm_device *dev = crtc->dev;
9892 struct drm_i915_private *dev_priv = dev->dev_private;
9893 struct drm_display_mode *saved_mode;
9894 struct intel_crtc_config *pipe_config = NULL;
9895 struct intel_crtc *intel_crtc;
9896 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9899 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
9903 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9904 &prepare_pipes, &disable_pipes);
9906 *saved_mode = crtc->mode;
9908 /* Hack: Because we don't (yet) support global modeset on multiple
9909 * crtcs, we don't keep track of the new mode for more than one crtc.
9910 * Hence simply check whether any bit is set in modeset_pipes in all the
9911 * pieces of code that are not yet converted to deal with mutliple crtcs
9912 * changing their mode at the same time. */
9913 if (modeset_pipes) {
9914 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9915 if (IS_ERR(pipe_config)) {
9916 ret = PTR_ERR(pipe_config);
9921 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9923 to_intel_crtc(crtc)->new_config = pipe_config;
9927 * See if the config requires any additional preparation, e.g.
9928 * to adjust global state with pipes off. We need to do this
9929 * here so we can get the modeset_pipe updated config for the new
9930 * mode set on this crtc. For other crtcs we need to use the
9931 * adjusted_mode bits in the crtc directly.
9933 if (IS_VALLEYVIEW(dev)) {
9934 valleyview_modeset_global_pipes(dev, &prepare_pipes);
9936 /* may have added more to prepare_pipes than we should */
9937 prepare_pipes &= ~disable_pipes;
9940 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9941 intel_crtc_disable(&intel_crtc->base);
9943 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9944 if (intel_crtc->base.enabled)
9945 dev_priv->display.crtc_disable(&intel_crtc->base);
9948 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9949 * to set it here already despite that we pass it down the callchain.
9951 if (modeset_pipes) {
9953 /* mode_set/enable/disable functions rely on a correct pipe
9955 to_intel_crtc(crtc)->config = *pipe_config;
9956 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
9959 * Calculate and store various constants which
9960 * are later needed by vblank and swap-completion
9961 * timestamping. They are derived from true hwmode.
9963 drm_calc_timestamping_constants(crtc,
9964 &pipe_config->adjusted_mode);
9967 /* Only after disabling all output pipelines that will be changed can we
9968 * update the the output configuration. */
9969 intel_modeset_update_state(dev, prepare_pipes);
9971 if (dev_priv->display.modeset_global_resources)
9972 dev_priv->display.modeset_global_resources(dev);
9974 /* Set up the DPLL and any encoders state that needs to adjust or depend
9977 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9978 ret = intel_crtc_mode_set(&intel_crtc->base,
9984 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9985 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9986 dev_priv->display.crtc_enable(&intel_crtc->base);
9988 /* FIXME: add subpixel order */
9990 if (ret && crtc->enabled)
9991 crtc->mode = *saved_mode;
9999 static int intel_set_mode(struct drm_crtc *crtc,
10000 struct drm_display_mode *mode,
10001 int x, int y, struct drm_framebuffer *fb)
10005 ret = __intel_set_mode(crtc, mode, x, y, fb);
10008 intel_modeset_check_state(crtc->dev);
10013 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10015 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10018 #undef for_each_intel_crtc_masked
10020 static void intel_set_config_free(struct intel_set_config *config)
10025 kfree(config->save_connector_encoders);
10026 kfree(config->save_encoder_crtcs);
10027 kfree(config->save_crtc_enabled);
10031 static int intel_set_config_save_state(struct drm_device *dev,
10032 struct intel_set_config *config)
10034 struct drm_crtc *crtc;
10035 struct drm_encoder *encoder;
10036 struct drm_connector *connector;
10039 config->save_crtc_enabled =
10040 kcalloc(dev->mode_config.num_crtc,
10041 sizeof(bool), GFP_KERNEL);
10042 if (!config->save_crtc_enabled)
10045 config->save_encoder_crtcs =
10046 kcalloc(dev->mode_config.num_encoder,
10047 sizeof(struct drm_crtc *), GFP_KERNEL);
10048 if (!config->save_encoder_crtcs)
10051 config->save_connector_encoders =
10052 kcalloc(dev->mode_config.num_connector,
10053 sizeof(struct drm_encoder *), GFP_KERNEL);
10054 if (!config->save_connector_encoders)
10057 /* Copy data. Note that driver private data is not affected.
10058 * Should anything bad happen only the expected state is
10059 * restored, not the drivers personal bookkeeping.
10062 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10063 config->save_crtc_enabled[count++] = crtc->enabled;
10067 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10068 config->save_encoder_crtcs[count++] = encoder->crtc;
10072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10073 config->save_connector_encoders[count++] = connector->encoder;
10079 static void intel_set_config_restore_state(struct drm_device *dev,
10080 struct intel_set_config *config)
10082 struct intel_crtc *crtc;
10083 struct intel_encoder *encoder;
10084 struct intel_connector *connector;
10088 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10089 crtc->new_enabled = config->save_crtc_enabled[count++];
10091 if (crtc->new_enabled)
10092 crtc->new_config = &crtc->config;
10094 crtc->new_config = NULL;
10098 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10099 encoder->new_crtc =
10100 to_intel_crtc(config->save_encoder_crtcs[count++]);
10104 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10105 connector->new_encoder =
10106 to_intel_encoder(config->save_connector_encoders[count++]);
10111 is_crtc_connector_off(struct drm_mode_set *set)
10115 if (set->num_connectors == 0)
10118 if (WARN_ON(set->connectors == NULL))
10121 for (i = 0; i < set->num_connectors; i++)
10122 if (set->connectors[i]->encoder &&
10123 set->connectors[i]->encoder->crtc == set->crtc &&
10124 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10131 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10132 struct intel_set_config *config)
10135 /* We should be able to check here if the fb has the same properties
10136 * and then just flip_or_move it */
10137 if (is_crtc_connector_off(set)) {
10138 config->mode_changed = true;
10139 } else if (set->crtc->primary->fb != set->fb) {
10140 /* If we have no fb then treat it as a full mode set */
10141 if (set->crtc->primary->fb == NULL) {
10142 struct intel_crtc *intel_crtc =
10143 to_intel_crtc(set->crtc);
10145 if (intel_crtc->active && i915.fastboot) {
10146 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10147 config->fb_changed = true;
10149 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10150 config->mode_changed = true;
10152 } else if (set->fb == NULL) {
10153 config->mode_changed = true;
10154 } else if (set->fb->pixel_format !=
10155 set->crtc->primary->fb->pixel_format) {
10156 config->mode_changed = true;
10158 config->fb_changed = true;
10162 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10163 config->fb_changed = true;
10165 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10166 DRM_DEBUG_KMS("modes are different, full mode set\n");
10167 drm_mode_debug_printmodeline(&set->crtc->mode);
10168 drm_mode_debug_printmodeline(set->mode);
10169 config->mode_changed = true;
10172 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10173 set->crtc->base.id, config->mode_changed, config->fb_changed);
10177 intel_modeset_stage_output_state(struct drm_device *dev,
10178 struct drm_mode_set *set,
10179 struct intel_set_config *config)
10181 struct intel_connector *connector;
10182 struct intel_encoder *encoder;
10183 struct intel_crtc *crtc;
10186 /* The upper layers ensure that we either disable a crtc or have a list
10187 * of connectors. For paranoia, double-check this. */
10188 WARN_ON(!set->fb && (set->num_connectors != 0));
10189 WARN_ON(set->fb && (set->num_connectors == 0));
10191 list_for_each_entry(connector, &dev->mode_config.connector_list,
10193 /* Otherwise traverse passed in connector list and get encoders
10195 for (ro = 0; ro < set->num_connectors; ro++) {
10196 if (set->connectors[ro] == &connector->base) {
10197 connector->new_encoder = connector->encoder;
10202 /* If we disable the crtc, disable all its connectors. Also, if
10203 * the connector is on the changing crtc but not on the new
10204 * connector list, disable it. */
10205 if ((!set->fb || ro == set->num_connectors) &&
10206 connector->base.encoder &&
10207 connector->base.encoder->crtc == set->crtc) {
10208 connector->new_encoder = NULL;
10210 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10211 connector->base.base.id,
10212 drm_get_connector_name(&connector->base));
10216 if (&connector->new_encoder->base != connector->base.encoder) {
10217 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10218 config->mode_changed = true;
10221 /* connector->new_encoder is now updated for all connectors. */
10223 /* Update crtc of enabled connectors. */
10224 list_for_each_entry(connector, &dev->mode_config.connector_list,
10226 struct drm_crtc *new_crtc;
10228 if (!connector->new_encoder)
10231 new_crtc = connector->new_encoder->base.crtc;
10233 for (ro = 0; ro < set->num_connectors; ro++) {
10234 if (set->connectors[ro] == &connector->base)
10235 new_crtc = set->crtc;
10238 /* Make sure the new CRTC will work with the encoder */
10239 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10243 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10245 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10246 connector->base.base.id,
10247 drm_get_connector_name(&connector->base),
10248 new_crtc->base.id);
10251 /* Check for any encoders that needs to be disabled. */
10252 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10254 int num_connectors = 0;
10255 list_for_each_entry(connector,
10256 &dev->mode_config.connector_list,
10258 if (connector->new_encoder == encoder) {
10259 WARN_ON(!connector->new_encoder->new_crtc);
10264 if (num_connectors == 0)
10265 encoder->new_crtc = NULL;
10266 else if (num_connectors > 1)
10269 /* Only now check for crtc changes so we don't miss encoders
10270 * that will be disabled. */
10271 if (&encoder->new_crtc->base != encoder->base.crtc) {
10272 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10273 config->mode_changed = true;
10276 /* Now we've also updated encoder->new_crtc for all encoders. */
10278 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10280 crtc->new_enabled = false;
10282 list_for_each_entry(encoder,
10283 &dev->mode_config.encoder_list,
10285 if (encoder->new_crtc == crtc) {
10286 crtc->new_enabled = true;
10291 if (crtc->new_enabled != crtc->base.enabled) {
10292 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10293 crtc->new_enabled ? "en" : "dis");
10294 config->mode_changed = true;
10297 if (crtc->new_enabled)
10298 crtc->new_config = &crtc->config;
10300 crtc->new_config = NULL;
10306 static void disable_crtc_nofb(struct intel_crtc *crtc)
10308 struct drm_device *dev = crtc->base.dev;
10309 struct intel_encoder *encoder;
10310 struct intel_connector *connector;
10312 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10313 pipe_name(crtc->pipe));
10315 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10316 if (connector->new_encoder &&
10317 connector->new_encoder->new_crtc == crtc)
10318 connector->new_encoder = NULL;
10321 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10322 if (encoder->new_crtc == crtc)
10323 encoder->new_crtc = NULL;
10326 crtc->new_enabled = false;
10327 crtc->new_config = NULL;
10330 static int intel_crtc_set_config(struct drm_mode_set *set)
10332 struct drm_device *dev;
10333 struct drm_mode_set save_set;
10334 struct intel_set_config *config;
10338 BUG_ON(!set->crtc);
10339 BUG_ON(!set->crtc->helper_private);
10341 /* Enforce sane interface api - has been abused by the fb helper. */
10342 BUG_ON(!set->mode && set->fb);
10343 BUG_ON(set->fb && set->num_connectors == 0);
10346 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10347 set->crtc->base.id, set->fb->base.id,
10348 (int)set->num_connectors, set->x, set->y);
10350 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10353 dev = set->crtc->dev;
10356 config = kzalloc(sizeof(*config), GFP_KERNEL);
10360 ret = intel_set_config_save_state(dev, config);
10364 save_set.crtc = set->crtc;
10365 save_set.mode = &set->crtc->mode;
10366 save_set.x = set->crtc->x;
10367 save_set.y = set->crtc->y;
10368 save_set.fb = set->crtc->primary->fb;
10370 /* Compute whether we need a full modeset, only an fb base update or no
10371 * change at all. In the future we might also check whether only the
10372 * mode changed, e.g. for LVDS where we only change the panel fitter in
10374 intel_set_config_compute_mode_changes(set, config);
10376 ret = intel_modeset_stage_output_state(dev, set, config);
10380 if (config->mode_changed) {
10381 ret = intel_set_mode(set->crtc, set->mode,
10382 set->x, set->y, set->fb);
10383 } else if (config->fb_changed) {
10384 intel_crtc_wait_for_pending_flips(set->crtc);
10386 ret = intel_pipe_set_base(set->crtc,
10387 set->x, set->y, set->fb);
10389 * In the fastboot case this may be our only check of the
10390 * state after boot. It would be better to only do it on
10391 * the first update, but we don't have a nice way of doing that
10392 * (and really, set_config isn't used much for high freq page
10393 * flipping, so increasing its cost here shouldn't be a big
10396 if (i915.fastboot && ret == 0)
10397 intel_modeset_check_state(set->crtc->dev);
10401 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10402 set->crtc->base.id, ret);
10404 intel_set_config_restore_state(dev, config);
10407 * HACK: if the pipe was on, but we didn't have a framebuffer,
10408 * force the pipe off to avoid oopsing in the modeset code
10409 * due to fb==NULL. This should only happen during boot since
10410 * we don't yet reconstruct the FB from the hardware state.
10412 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10413 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10415 /* Try to restore the config */
10416 if (config->mode_changed &&
10417 intel_set_mode(save_set.crtc, save_set.mode,
10418 save_set.x, save_set.y, save_set.fb))
10419 DRM_ERROR("failed to restore config after modeset failure\n");
10423 intel_set_config_free(config);
10427 static const struct drm_crtc_funcs intel_crtc_funcs = {
10428 .cursor_set = intel_crtc_cursor_set,
10429 .cursor_move = intel_crtc_cursor_move,
10430 .gamma_set = intel_crtc_gamma_set,
10431 .set_config = intel_crtc_set_config,
10432 .destroy = intel_crtc_destroy,
10433 .page_flip = intel_crtc_page_flip,
10436 static void intel_cpu_pll_init(struct drm_device *dev)
10439 intel_ddi_pll_init(dev);
10442 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10443 struct intel_shared_dpll *pll,
10444 struct intel_dpll_hw_state *hw_state)
10448 val = I915_READ(PCH_DPLL(pll->id));
10449 hw_state->dpll = val;
10450 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10451 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10453 return val & DPLL_VCO_ENABLE;
10456 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10457 struct intel_shared_dpll *pll)
10459 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10460 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10463 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10464 struct intel_shared_dpll *pll)
10466 /* PCH refclock must be enabled first */
10467 ibx_assert_pch_refclk_enabled(dev_priv);
10469 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10471 /* Wait for the clocks to stabilize. */
10472 POSTING_READ(PCH_DPLL(pll->id));
10475 /* The pixel multiplier can only be updated once the
10476 * DPLL is enabled and the clocks are stable.
10478 * So write it again.
10480 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10481 POSTING_READ(PCH_DPLL(pll->id));
10485 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10486 struct intel_shared_dpll *pll)
10488 struct drm_device *dev = dev_priv->dev;
10489 struct intel_crtc *crtc;
10491 /* Make sure no transcoder isn't still depending on us. */
10492 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10493 if (intel_crtc_to_shared_dpll(crtc) == pll)
10494 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10497 I915_WRITE(PCH_DPLL(pll->id), 0);
10498 POSTING_READ(PCH_DPLL(pll->id));
10502 static char *ibx_pch_dpll_names[] = {
10507 static void ibx_pch_dpll_init(struct drm_device *dev)
10509 struct drm_i915_private *dev_priv = dev->dev_private;
10512 dev_priv->num_shared_dpll = 2;
10514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10515 dev_priv->shared_dplls[i].id = i;
10516 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10517 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10518 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10519 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10520 dev_priv->shared_dplls[i].get_hw_state =
10521 ibx_pch_dpll_get_hw_state;
10525 static void intel_shared_dpll_init(struct drm_device *dev)
10527 struct drm_i915_private *dev_priv = dev->dev_private;
10529 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10530 ibx_pch_dpll_init(dev);
10532 dev_priv->num_shared_dpll = 0;
10534 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10537 static void intel_crtc_init(struct drm_device *dev, int pipe)
10539 struct drm_i915_private *dev_priv = dev->dev_private;
10540 struct intel_crtc *intel_crtc;
10543 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10544 if (intel_crtc == NULL)
10547 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10549 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10550 for (i = 0; i < 256; i++) {
10551 intel_crtc->lut_r[i] = i;
10552 intel_crtc->lut_g[i] = i;
10553 intel_crtc->lut_b[i] = i;
10557 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10558 * is hooked to plane B. Hence we want plane A feeding pipe B.
10560 intel_crtc->pipe = pipe;
10561 intel_crtc->plane = pipe;
10562 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10563 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10564 intel_crtc->plane = !pipe;
10567 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10568 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10569 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10570 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10572 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10575 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10577 struct drm_encoder *encoder = connector->base.encoder;
10579 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10582 return INVALID_PIPE;
10584 return to_intel_crtc(encoder->crtc)->pipe;
10587 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10588 struct drm_file *file)
10590 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10591 struct drm_mode_object *drmmode_obj;
10592 struct intel_crtc *crtc;
10594 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10597 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10598 DRM_MODE_OBJECT_CRTC);
10600 if (!drmmode_obj) {
10601 DRM_ERROR("no such CRTC id\n");
10605 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10606 pipe_from_crtc_id->pipe = crtc->pipe;
10611 static int intel_encoder_clones(struct intel_encoder *encoder)
10613 struct drm_device *dev = encoder->base.dev;
10614 struct intel_encoder *source_encoder;
10615 int index_mask = 0;
10618 list_for_each_entry(source_encoder,
10619 &dev->mode_config.encoder_list, base.head) {
10620 if (encoders_cloneable(encoder, source_encoder))
10621 index_mask |= (1 << entry);
10629 static bool has_edp_a(struct drm_device *dev)
10631 struct drm_i915_private *dev_priv = dev->dev_private;
10633 if (!IS_MOBILE(dev))
10636 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10639 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10645 const char *intel_output_name(int output)
10647 static const char *names[] = {
10648 [INTEL_OUTPUT_UNUSED] = "Unused",
10649 [INTEL_OUTPUT_ANALOG] = "Analog",
10650 [INTEL_OUTPUT_DVO] = "DVO",
10651 [INTEL_OUTPUT_SDVO] = "SDVO",
10652 [INTEL_OUTPUT_LVDS] = "LVDS",
10653 [INTEL_OUTPUT_TVOUT] = "TV",
10654 [INTEL_OUTPUT_HDMI] = "HDMI",
10655 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
10656 [INTEL_OUTPUT_EDP] = "eDP",
10657 [INTEL_OUTPUT_DSI] = "DSI",
10658 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
10661 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
10664 return names[output];
10667 static void intel_setup_outputs(struct drm_device *dev)
10669 struct drm_i915_private *dev_priv = dev->dev_private;
10670 struct intel_encoder *encoder;
10671 bool dpd_is_edp = false;
10673 intel_lvds_init(dev);
10676 intel_crt_init(dev);
10678 if (HAS_DDI(dev)) {
10681 /* Haswell uses DDI functions to detect digital outputs */
10682 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10683 /* DDI A only supports eDP */
10685 intel_ddi_init(dev, PORT_A);
10687 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10689 found = I915_READ(SFUSE_STRAP);
10691 if (found & SFUSE_STRAP_DDIB_DETECTED)
10692 intel_ddi_init(dev, PORT_B);
10693 if (found & SFUSE_STRAP_DDIC_DETECTED)
10694 intel_ddi_init(dev, PORT_C);
10695 if (found & SFUSE_STRAP_DDID_DETECTED)
10696 intel_ddi_init(dev, PORT_D);
10697 } else if (HAS_PCH_SPLIT(dev)) {
10699 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
10701 if (has_edp_a(dev))
10702 intel_dp_init(dev, DP_A, PORT_A);
10704 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10705 /* PCH SDVOB multiplex with HDMIB */
10706 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10708 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10709 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10710 intel_dp_init(dev, PCH_DP_B, PORT_B);
10713 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10714 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10716 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10717 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10719 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10720 intel_dp_init(dev, PCH_DP_C, PORT_C);
10722 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10723 intel_dp_init(dev, PCH_DP_D, PORT_D);
10724 } else if (IS_VALLEYVIEW(dev)) {
10725 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10726 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10728 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10729 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10732 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10733 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10735 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10736 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
10739 intel_dsi_init(dev);
10740 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10741 bool found = false;
10743 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10744 DRM_DEBUG_KMS("probing SDVOB\n");
10745 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10746 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10747 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10748 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10751 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10752 intel_dp_init(dev, DP_B, PORT_B);
10755 /* Before G4X SDVOC doesn't have its own detect register */
10757 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10758 DRM_DEBUG_KMS("probing SDVOC\n");
10759 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10762 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10764 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10765 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10766 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10768 if (SUPPORTS_INTEGRATED_DP(dev))
10769 intel_dp_init(dev, DP_C, PORT_C);
10772 if (SUPPORTS_INTEGRATED_DP(dev) &&
10773 (I915_READ(DP_D) & DP_DETECTED))
10774 intel_dp_init(dev, DP_D, PORT_D);
10775 } else if (IS_GEN2(dev))
10776 intel_dvo_init(dev);
10778 if (SUPPORTS_TV(dev))
10779 intel_tv_init(dev);
10781 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10782 encoder->base.possible_crtcs = encoder->crtc_mask;
10783 encoder->base.possible_clones =
10784 intel_encoder_clones(encoder);
10787 intel_init_pch_refclk(dev);
10789 drm_helper_move_panel_connectors_to_head(dev);
10792 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10794 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10796 drm_framebuffer_cleanup(fb);
10797 WARN_ON(!intel_fb->obj->framebuffer_references--);
10798 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10802 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10803 struct drm_file *file,
10804 unsigned int *handle)
10806 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10807 struct drm_i915_gem_object *obj = intel_fb->obj;
10809 return drm_gem_handle_create(file, &obj->base, handle);
10812 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10813 .destroy = intel_user_framebuffer_destroy,
10814 .create_handle = intel_user_framebuffer_create_handle,
10817 static int intel_framebuffer_init(struct drm_device *dev,
10818 struct intel_framebuffer *intel_fb,
10819 struct drm_mode_fb_cmd2 *mode_cmd,
10820 struct drm_i915_gem_object *obj)
10822 int aligned_height;
10826 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10828 if (obj->tiling_mode == I915_TILING_Y) {
10829 DRM_DEBUG("hardware does not support tiling Y\n");
10833 if (mode_cmd->pitches[0] & 63) {
10834 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10835 mode_cmd->pitches[0]);
10839 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10840 pitch_limit = 32*1024;
10841 } else if (INTEL_INFO(dev)->gen >= 4) {
10842 if (obj->tiling_mode)
10843 pitch_limit = 16*1024;
10845 pitch_limit = 32*1024;
10846 } else if (INTEL_INFO(dev)->gen >= 3) {
10847 if (obj->tiling_mode)
10848 pitch_limit = 8*1024;
10850 pitch_limit = 16*1024;
10852 /* XXX DSPC is limited to 4k tiled */
10853 pitch_limit = 8*1024;
10855 if (mode_cmd->pitches[0] > pitch_limit) {
10856 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10857 obj->tiling_mode ? "tiled" : "linear",
10858 mode_cmd->pitches[0], pitch_limit);
10862 if (obj->tiling_mode != I915_TILING_NONE &&
10863 mode_cmd->pitches[0] != obj->stride) {
10864 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10865 mode_cmd->pitches[0], obj->stride);
10869 /* Reject formats not supported by any plane early. */
10870 switch (mode_cmd->pixel_format) {
10871 case DRM_FORMAT_C8:
10872 case DRM_FORMAT_RGB565:
10873 case DRM_FORMAT_XRGB8888:
10874 case DRM_FORMAT_ARGB8888:
10876 case DRM_FORMAT_XRGB1555:
10877 case DRM_FORMAT_ARGB1555:
10878 if (INTEL_INFO(dev)->gen > 3) {
10879 DRM_DEBUG("unsupported pixel format: %s\n",
10880 drm_get_format_name(mode_cmd->pixel_format));
10884 case DRM_FORMAT_XBGR8888:
10885 case DRM_FORMAT_ABGR8888:
10886 case DRM_FORMAT_XRGB2101010:
10887 case DRM_FORMAT_ARGB2101010:
10888 case DRM_FORMAT_XBGR2101010:
10889 case DRM_FORMAT_ABGR2101010:
10890 if (INTEL_INFO(dev)->gen < 4) {
10891 DRM_DEBUG("unsupported pixel format: %s\n",
10892 drm_get_format_name(mode_cmd->pixel_format));
10896 case DRM_FORMAT_YUYV:
10897 case DRM_FORMAT_UYVY:
10898 case DRM_FORMAT_YVYU:
10899 case DRM_FORMAT_VYUY:
10900 if (INTEL_INFO(dev)->gen < 5) {
10901 DRM_DEBUG("unsupported pixel format: %s\n",
10902 drm_get_format_name(mode_cmd->pixel_format));
10907 DRM_DEBUG("unsupported pixel format: %s\n",
10908 drm_get_format_name(mode_cmd->pixel_format));
10912 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10913 if (mode_cmd->offsets[0] != 0)
10916 aligned_height = intel_align_height(dev, mode_cmd->height,
10918 /* FIXME drm helper for size checks (especially planar formats)? */
10919 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10922 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10923 intel_fb->obj = obj;
10924 intel_fb->obj->framebuffer_references++;
10926 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10928 DRM_ERROR("framebuffer init failed %d\n", ret);
10935 static struct drm_framebuffer *
10936 intel_user_framebuffer_create(struct drm_device *dev,
10937 struct drm_file *filp,
10938 struct drm_mode_fb_cmd2 *mode_cmd)
10940 struct drm_i915_gem_object *obj;
10942 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10943 mode_cmd->handles[0]));
10944 if (&obj->base == NULL)
10945 return ERR_PTR(-ENOENT);
10947 return intel_framebuffer_create(dev, mode_cmd, obj);
10950 #ifndef CONFIG_DRM_I915_FBDEV
10951 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10956 static const struct drm_mode_config_funcs intel_mode_funcs = {
10957 .fb_create = intel_user_framebuffer_create,
10958 .output_poll_changed = intel_fbdev_output_poll_changed,
10961 /* Set up chip specific display functions */
10962 static void intel_init_display(struct drm_device *dev)
10964 struct drm_i915_private *dev_priv = dev->dev_private;
10966 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10967 dev_priv->display.find_dpll = g4x_find_best_dpll;
10968 else if (IS_VALLEYVIEW(dev))
10969 dev_priv->display.find_dpll = vlv_find_best_dpll;
10970 else if (IS_PINEVIEW(dev))
10971 dev_priv->display.find_dpll = pnv_find_best_dpll;
10973 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10975 if (HAS_DDI(dev)) {
10976 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10977 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10978 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10979 dev_priv->display.crtc_enable = haswell_crtc_enable;
10980 dev_priv->display.crtc_disable = haswell_crtc_disable;
10981 dev_priv->display.off = haswell_crtc_off;
10982 dev_priv->display.update_primary_plane =
10983 ironlake_update_primary_plane;
10984 } else if (HAS_PCH_SPLIT(dev)) {
10985 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10986 dev_priv->display.get_plane_config = ironlake_get_plane_config;
10987 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10988 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10989 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10990 dev_priv->display.off = ironlake_crtc_off;
10991 dev_priv->display.update_primary_plane =
10992 ironlake_update_primary_plane;
10993 } else if (IS_VALLEYVIEW(dev)) {
10994 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10995 dev_priv->display.get_plane_config = i9xx_get_plane_config;
10996 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10997 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10998 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10999 dev_priv->display.off = i9xx_crtc_off;
11000 dev_priv->display.update_primary_plane =
11001 i9xx_update_primary_plane;
11003 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11004 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11005 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11006 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11007 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11008 dev_priv->display.off = i9xx_crtc_off;
11009 dev_priv->display.update_primary_plane =
11010 i9xx_update_primary_plane;
11013 /* Returns the core display clock speed */
11014 if (IS_VALLEYVIEW(dev))
11015 dev_priv->display.get_display_clock_speed =
11016 valleyview_get_display_clock_speed;
11017 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11018 dev_priv->display.get_display_clock_speed =
11019 i945_get_display_clock_speed;
11020 else if (IS_I915G(dev))
11021 dev_priv->display.get_display_clock_speed =
11022 i915_get_display_clock_speed;
11023 else if (IS_I945GM(dev) || IS_845G(dev))
11024 dev_priv->display.get_display_clock_speed =
11025 i9xx_misc_get_display_clock_speed;
11026 else if (IS_PINEVIEW(dev))
11027 dev_priv->display.get_display_clock_speed =
11028 pnv_get_display_clock_speed;
11029 else if (IS_I915GM(dev))
11030 dev_priv->display.get_display_clock_speed =
11031 i915gm_get_display_clock_speed;
11032 else if (IS_I865G(dev))
11033 dev_priv->display.get_display_clock_speed =
11034 i865_get_display_clock_speed;
11035 else if (IS_I85X(dev))
11036 dev_priv->display.get_display_clock_speed =
11037 i855_get_display_clock_speed;
11038 else /* 852, 830 */
11039 dev_priv->display.get_display_clock_speed =
11040 i830_get_display_clock_speed;
11042 if (HAS_PCH_SPLIT(dev)) {
11043 if (IS_GEN5(dev)) {
11044 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11045 dev_priv->display.write_eld = ironlake_write_eld;
11046 } else if (IS_GEN6(dev)) {
11047 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11048 dev_priv->display.write_eld = ironlake_write_eld;
11049 dev_priv->display.modeset_global_resources =
11050 snb_modeset_global_resources;
11051 } else if (IS_IVYBRIDGE(dev)) {
11052 /* FIXME: detect B0+ stepping and use auto training */
11053 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11054 dev_priv->display.write_eld = ironlake_write_eld;
11055 dev_priv->display.modeset_global_resources =
11056 ivb_modeset_global_resources;
11057 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11058 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11059 dev_priv->display.write_eld = haswell_write_eld;
11060 dev_priv->display.modeset_global_resources =
11061 haswell_modeset_global_resources;
11063 } else if (IS_G4X(dev)) {
11064 dev_priv->display.write_eld = g4x_write_eld;
11065 } else if (IS_VALLEYVIEW(dev)) {
11066 dev_priv->display.modeset_global_resources =
11067 valleyview_modeset_global_resources;
11068 dev_priv->display.write_eld = ironlake_write_eld;
11071 /* Default just returns -ENODEV to indicate unsupported */
11072 dev_priv->display.queue_flip = intel_default_queue_flip;
11074 switch (INTEL_INFO(dev)->gen) {
11076 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11080 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11085 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11089 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11092 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11093 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11097 intel_panel_init_backlight_funcs(dev);
11101 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11102 * resume, or other times. This quirk makes sure that's the case for
11103 * affected systems.
11105 static void quirk_pipea_force(struct drm_device *dev)
11107 struct drm_i915_private *dev_priv = dev->dev_private;
11109 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11110 DRM_INFO("applying pipe a force quirk\n");
11114 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11116 static void quirk_ssc_force_disable(struct drm_device *dev)
11118 struct drm_i915_private *dev_priv = dev->dev_private;
11119 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11120 DRM_INFO("applying lvds SSC disable quirk\n");
11124 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11127 static void quirk_invert_brightness(struct drm_device *dev)
11129 struct drm_i915_private *dev_priv = dev->dev_private;
11130 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11131 DRM_INFO("applying inverted panel brightness quirk\n");
11134 struct intel_quirk {
11136 int subsystem_vendor;
11137 int subsystem_device;
11138 void (*hook)(struct drm_device *dev);
11141 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11142 struct intel_dmi_quirk {
11143 void (*hook)(struct drm_device *dev);
11144 const struct dmi_system_id (*dmi_id_list)[];
11147 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11149 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11153 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11155 .dmi_id_list = &(const struct dmi_system_id[]) {
11157 .callback = intel_dmi_reverse_brightness,
11158 .ident = "NCR Corporation",
11159 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11160 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11163 { } /* terminating entry */
11165 .hook = quirk_invert_brightness,
11169 static struct intel_quirk intel_quirks[] = {
11170 /* HP Mini needs pipe A force quirk (LP: #322104) */
11171 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11173 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11174 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11176 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11177 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11179 /* 830 needs to leave pipe A & dpll A up */
11180 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11182 /* Lenovo U160 cannot use SSC on LVDS */
11183 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11185 /* Sony Vaio Y cannot use SSC on LVDS */
11186 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11188 /* Acer Aspire 5734Z must invert backlight brightness */
11189 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11191 /* Acer/eMachines G725 */
11192 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11194 /* Acer/eMachines e725 */
11195 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11197 /* Acer/Packard Bell NCL20 */
11198 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11200 /* Acer Aspire 4736Z */
11201 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11203 /* Acer Aspire 5336 */
11204 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11207 static void intel_init_quirks(struct drm_device *dev)
11209 struct pci_dev *d = dev->pdev;
11212 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11213 struct intel_quirk *q = &intel_quirks[i];
11215 if (d->device == q->device &&
11216 (d->subsystem_vendor == q->subsystem_vendor ||
11217 q->subsystem_vendor == PCI_ANY_ID) &&
11218 (d->subsystem_device == q->subsystem_device ||
11219 q->subsystem_device == PCI_ANY_ID))
11222 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11223 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11224 intel_dmi_quirks[i].hook(dev);
11228 /* Disable the VGA plane that we never use */
11229 static void i915_disable_vga(struct drm_device *dev)
11231 struct drm_i915_private *dev_priv = dev->dev_private;
11233 u32 vga_reg = i915_vgacntrl_reg(dev);
11235 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11236 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11237 outb(SR01, VGA_SR_INDEX);
11238 sr1 = inb(VGA_SR_DATA);
11239 outb(sr1 | 1<<5, VGA_SR_DATA);
11240 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11243 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11244 POSTING_READ(vga_reg);
11247 void intel_modeset_init_hw(struct drm_device *dev)
11249 intel_prepare_ddi(dev);
11251 intel_init_clock_gating(dev);
11253 intel_reset_dpio(dev);
11255 intel_enable_gt_powersave(dev);
11258 void intel_modeset_suspend_hw(struct drm_device *dev)
11260 intel_suspend_hw(dev);
11263 void intel_modeset_init(struct drm_device *dev)
11265 struct drm_i915_private *dev_priv = dev->dev_private;
11268 struct intel_crtc *crtc;
11270 drm_mode_config_init(dev);
11272 dev->mode_config.min_width = 0;
11273 dev->mode_config.min_height = 0;
11275 dev->mode_config.preferred_depth = 24;
11276 dev->mode_config.prefer_shadow = 1;
11278 dev->mode_config.funcs = &intel_mode_funcs;
11280 intel_init_quirks(dev);
11282 intel_init_pm(dev);
11284 if (INTEL_INFO(dev)->num_pipes == 0)
11287 intel_init_display(dev);
11289 if (IS_GEN2(dev)) {
11290 dev->mode_config.max_width = 2048;
11291 dev->mode_config.max_height = 2048;
11292 } else if (IS_GEN3(dev)) {
11293 dev->mode_config.max_width = 4096;
11294 dev->mode_config.max_height = 4096;
11296 dev->mode_config.max_width = 8192;
11297 dev->mode_config.max_height = 8192;
11300 if (IS_GEN2(dev)) {
11301 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11302 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11304 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11305 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11308 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11310 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11311 INTEL_INFO(dev)->num_pipes,
11312 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11314 for_each_pipe(pipe) {
11315 intel_crtc_init(dev, pipe);
11316 for_each_sprite(pipe, sprite) {
11317 ret = intel_plane_init(dev, pipe, sprite);
11319 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11320 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11324 intel_init_dpio(dev);
11325 intel_reset_dpio(dev);
11327 intel_cpu_pll_init(dev);
11328 intel_shared_dpll_init(dev);
11330 /* Just disable it once at startup */
11331 i915_disable_vga(dev);
11332 intel_setup_outputs(dev);
11334 /* Just in case the BIOS is doing something questionable. */
11335 intel_disable_fbc(dev);
11337 mutex_lock(&dev->mode_config.mutex);
11338 intel_modeset_setup_hw_state(dev, false);
11339 mutex_unlock(&dev->mode_config.mutex);
11341 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11347 * Note that reserving the BIOS fb up front prevents us
11348 * from stuffing other stolen allocations like the ring
11349 * on top. This prevents some ugliness at boot time, and
11350 * can even allow for smooth boot transitions if the BIOS
11351 * fb is large enough for the active pipe configuration.
11353 if (dev_priv->display.get_plane_config) {
11354 dev_priv->display.get_plane_config(crtc,
11355 &crtc->plane_config);
11357 * If the fb is shared between multiple heads, we'll
11358 * just get the first one.
11360 intel_find_plane_obj(crtc, &crtc->plane_config);
11366 intel_connector_break_all_links(struct intel_connector *connector)
11368 connector->base.dpms = DRM_MODE_DPMS_OFF;
11369 connector->base.encoder = NULL;
11370 connector->encoder->connectors_active = false;
11371 connector->encoder->base.crtc = NULL;
11374 static void intel_enable_pipe_a(struct drm_device *dev)
11376 struct intel_connector *connector;
11377 struct drm_connector *crt = NULL;
11378 struct intel_load_detect_pipe load_detect_temp;
11380 /* We can't just switch on the pipe A, we need to set things up with a
11381 * proper mode and output configuration. As a gross hack, enable pipe A
11382 * by enabling the load detect pipe once. */
11383 list_for_each_entry(connector,
11384 &dev->mode_config.connector_list,
11386 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11387 crt = &connector->base;
11395 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11396 intel_release_load_detect_pipe(crt, &load_detect_temp);
11402 intel_check_plane_mapping(struct intel_crtc *crtc)
11404 struct drm_device *dev = crtc->base.dev;
11405 struct drm_i915_private *dev_priv = dev->dev_private;
11408 if (INTEL_INFO(dev)->num_pipes == 1)
11411 reg = DSPCNTR(!crtc->plane);
11412 val = I915_READ(reg);
11414 if ((val & DISPLAY_PLANE_ENABLE) &&
11415 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11421 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11423 struct drm_device *dev = crtc->base.dev;
11424 struct drm_i915_private *dev_priv = dev->dev_private;
11427 /* Clear any frame start delays used for debugging left by the BIOS */
11428 reg = PIPECONF(crtc->config.cpu_transcoder);
11429 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11431 /* We need to sanitize the plane -> pipe mapping first because this will
11432 * disable the crtc (and hence change the state) if it is wrong. Note
11433 * that gen4+ has a fixed plane -> pipe mapping. */
11434 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11435 struct intel_connector *connector;
11438 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11439 crtc->base.base.id);
11441 /* Pipe has the wrong plane attached and the plane is active.
11442 * Temporarily change the plane mapping and disable everything
11444 plane = crtc->plane;
11445 crtc->plane = !plane;
11446 dev_priv->display.crtc_disable(&crtc->base);
11447 crtc->plane = plane;
11449 /* ... and break all links. */
11450 list_for_each_entry(connector, &dev->mode_config.connector_list,
11452 if (connector->encoder->base.crtc != &crtc->base)
11455 intel_connector_break_all_links(connector);
11458 WARN_ON(crtc->active);
11459 crtc->base.enabled = false;
11462 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11463 crtc->pipe == PIPE_A && !crtc->active) {
11464 /* BIOS forgot to enable pipe A, this mostly happens after
11465 * resume. Force-enable the pipe to fix this, the update_dpms
11466 * call below we restore the pipe to the right state, but leave
11467 * the required bits on. */
11468 intel_enable_pipe_a(dev);
11471 /* Adjust the state of the output pipe according to whether we
11472 * have active connectors/encoders. */
11473 intel_crtc_update_dpms(&crtc->base);
11475 if (crtc->active != crtc->base.enabled) {
11476 struct intel_encoder *encoder;
11478 /* This can happen either due to bugs in the get_hw_state
11479 * functions or because the pipe is force-enabled due to the
11481 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11482 crtc->base.base.id,
11483 crtc->base.enabled ? "enabled" : "disabled",
11484 crtc->active ? "enabled" : "disabled");
11486 crtc->base.enabled = crtc->active;
11488 /* Because we only establish the connector -> encoder ->
11489 * crtc links if something is active, this means the
11490 * crtc is now deactivated. Break the links. connector
11491 * -> encoder links are only establish when things are
11492 * actually up, hence no need to break them. */
11493 WARN_ON(crtc->active);
11495 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11496 WARN_ON(encoder->connectors_active);
11497 encoder->base.crtc = NULL;
11500 if (crtc->active) {
11502 * We start out with underrun reporting disabled to avoid races.
11503 * For correct bookkeeping mark this on active crtcs.
11505 * No protection against concurrent access is required - at
11506 * worst a fifo underrun happens which also sets this to false.
11508 crtc->cpu_fifo_underrun_disabled = true;
11509 crtc->pch_fifo_underrun_disabled = true;
11513 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11515 struct intel_connector *connector;
11516 struct drm_device *dev = encoder->base.dev;
11518 /* We need to check both for a crtc link (meaning that the
11519 * encoder is active and trying to read from a pipe) and the
11520 * pipe itself being active. */
11521 bool has_active_crtc = encoder->base.crtc &&
11522 to_intel_crtc(encoder->base.crtc)->active;
11524 if (encoder->connectors_active && !has_active_crtc) {
11525 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11526 encoder->base.base.id,
11527 drm_get_encoder_name(&encoder->base));
11529 /* Connector is active, but has no active pipe. This is
11530 * fallout from our resume register restoring. Disable
11531 * the encoder manually again. */
11532 if (encoder->base.crtc) {
11533 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11534 encoder->base.base.id,
11535 drm_get_encoder_name(&encoder->base));
11536 encoder->disable(encoder);
11539 /* Inconsistent output/port/pipe state happens presumably due to
11540 * a bug in one of the get_hw_state functions. Or someplace else
11541 * in our code, like the register restore mess on resume. Clamp
11542 * things to off as a safer default. */
11543 list_for_each_entry(connector,
11544 &dev->mode_config.connector_list,
11546 if (connector->encoder != encoder)
11549 intel_connector_break_all_links(connector);
11552 /* Enabled encoders without active connectors will be fixed in
11553 * the crtc fixup. */
11556 void i915_redisable_vga_power_on(struct drm_device *dev)
11558 struct drm_i915_private *dev_priv = dev->dev_private;
11559 u32 vga_reg = i915_vgacntrl_reg(dev);
11561 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11562 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11563 i915_disable_vga(dev);
11567 void i915_redisable_vga(struct drm_device *dev)
11569 struct drm_i915_private *dev_priv = dev->dev_private;
11571 /* This function can be called both from intel_modeset_setup_hw_state or
11572 * at a very early point in our resume sequence, where the power well
11573 * structures are not yet restored. Since this function is at a very
11574 * paranoid "someone might have enabled VGA while we were not looking"
11575 * level, just check if the power well is enabled instead of trying to
11576 * follow the "don't touch the power well if we don't need it" policy
11577 * the rest of the driver uses. */
11578 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
11581 i915_redisable_vga_power_on(dev);
11584 static bool primary_get_hw_state(struct intel_crtc *crtc)
11586 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
11591 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
11594 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11596 struct drm_i915_private *dev_priv = dev->dev_private;
11598 struct intel_crtc *crtc;
11599 struct intel_encoder *encoder;
11600 struct intel_connector *connector;
11603 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11605 memset(&crtc->config, 0, sizeof(crtc->config));
11607 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
11609 crtc->active = dev_priv->display.get_pipe_config(crtc,
11612 crtc->base.enabled = crtc->active;
11613 crtc->primary_enabled = primary_get_hw_state(crtc);
11615 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11616 crtc->base.base.id,
11617 crtc->active ? "enabled" : "disabled");
11620 /* FIXME: Smash this into the new shared dpll infrastructure. */
11622 intel_ddi_setup_hw_pll_state(dev);
11624 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11625 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11627 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11629 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11631 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11634 pll->refcount = pll->active;
11636 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11637 pll->name, pll->refcount, pll->on);
11640 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11644 if (encoder->get_hw_state(encoder, &pipe)) {
11645 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11646 encoder->base.crtc = &crtc->base;
11647 encoder->get_config(encoder, &crtc->config);
11649 encoder->base.crtc = NULL;
11652 encoder->connectors_active = false;
11653 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11654 encoder->base.base.id,
11655 drm_get_encoder_name(&encoder->base),
11656 encoder->base.crtc ? "enabled" : "disabled",
11660 list_for_each_entry(connector, &dev->mode_config.connector_list,
11662 if (connector->get_hw_state(connector)) {
11663 connector->base.dpms = DRM_MODE_DPMS_ON;
11664 connector->encoder->connectors_active = true;
11665 connector->base.encoder = &connector->encoder->base;
11667 connector->base.dpms = DRM_MODE_DPMS_OFF;
11668 connector->base.encoder = NULL;
11670 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11671 connector->base.base.id,
11672 drm_get_connector_name(&connector->base),
11673 connector->base.encoder ? "enabled" : "disabled");
11677 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11678 * and i915 state tracking structures. */
11679 void intel_modeset_setup_hw_state(struct drm_device *dev,
11680 bool force_restore)
11682 struct drm_i915_private *dev_priv = dev->dev_private;
11684 struct intel_crtc *crtc;
11685 struct intel_encoder *encoder;
11688 intel_modeset_readout_hw_state(dev);
11691 * Now that we have the config, copy it to each CRTC struct
11692 * Note that this could go away if we move to using crtc_config
11693 * checking everywhere.
11695 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11697 if (crtc->active && i915.fastboot) {
11698 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11699 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11700 crtc->base.base.id);
11701 drm_mode_debug_printmodeline(&crtc->base.mode);
11705 /* HW state is read out, now we need to sanitize this mess. */
11706 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11708 intel_sanitize_encoder(encoder);
11711 for_each_pipe(pipe) {
11712 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11713 intel_sanitize_crtc(crtc);
11714 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11717 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11718 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11720 if (!pll->on || pll->active)
11723 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11725 pll->disable(dev_priv, pll);
11729 if (HAS_PCH_SPLIT(dev))
11730 ilk_wm_get_hw_state(dev);
11732 if (force_restore) {
11733 i915_redisable_vga(dev);
11736 * We need to use raw interfaces for restoring state to avoid
11737 * checking (bogus) intermediate states.
11739 for_each_pipe(pipe) {
11740 struct drm_crtc *crtc =
11741 dev_priv->pipe_to_crtc_mapping[pipe];
11743 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11744 crtc->primary->fb);
11747 intel_modeset_update_staged_output_state(dev);
11750 intel_modeset_check_state(dev);
11753 void intel_modeset_gem_init(struct drm_device *dev)
11755 struct drm_crtc *c;
11756 struct intel_framebuffer *fb;
11758 mutex_lock(&dev->struct_mutex);
11759 intel_init_gt_powersave(dev);
11760 mutex_unlock(&dev->struct_mutex);
11762 intel_modeset_init_hw(dev);
11764 intel_setup_overlay(dev);
11767 * Make sure any fbs we allocated at startup are properly
11768 * pinned & fenced. When we do the allocation it's too early
11771 mutex_lock(&dev->struct_mutex);
11772 list_for_each_entry(c, &dev->mode_config.crtc_list, head) {
11773 if (!c->primary->fb)
11776 fb = to_intel_framebuffer(c->primary->fb);
11777 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
11778 DRM_ERROR("failed to pin boot fb on pipe %d\n",
11779 to_intel_crtc(c)->pipe);
11780 drm_framebuffer_unreference(c->primary->fb);
11781 c->primary->fb = NULL;
11784 mutex_unlock(&dev->struct_mutex);
11787 void intel_connector_unregister(struct intel_connector *intel_connector)
11789 struct drm_connector *connector = &intel_connector->base;
11791 intel_panel_destroy_backlight(connector);
11792 drm_sysfs_connector_remove(connector);
11795 void intel_modeset_cleanup(struct drm_device *dev)
11797 struct drm_i915_private *dev_priv = dev->dev_private;
11798 struct drm_crtc *crtc;
11799 struct drm_connector *connector;
11802 * Interrupts and polling as the first thing to avoid creating havoc.
11803 * Too much stuff here (turning of rps, connectors, ...) would
11804 * experience fancy races otherwise.
11806 drm_irq_uninstall(dev);
11807 cancel_work_sync(&dev_priv->hotplug_work);
11809 * Due to the hpd irq storm handling the hotplug work can re-arm the
11810 * poll handlers. Hence disable polling after hpd handling is shut down.
11812 drm_kms_helper_poll_fini(dev);
11814 mutex_lock(&dev->struct_mutex);
11816 intel_unregister_dsm_handler();
11818 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11819 /* Skip inactive CRTCs */
11820 if (!crtc->primary->fb)
11823 intel_increase_pllclock(crtc);
11826 intel_disable_fbc(dev);
11828 intel_disable_gt_powersave(dev);
11830 ironlake_teardown_rc6(dev);
11832 mutex_unlock(&dev->struct_mutex);
11834 /* flush any delayed tasks or pending work */
11835 flush_scheduled_work();
11837 /* destroy the backlight and sysfs files before encoders/connectors */
11838 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11839 struct intel_connector *intel_connector;
11841 intel_connector = to_intel_connector(connector);
11842 intel_connector->unregister(intel_connector);
11845 drm_mode_config_cleanup(dev);
11847 intel_cleanup_overlay(dev);
11849 mutex_lock(&dev->struct_mutex);
11850 intel_cleanup_gt_powersave(dev);
11851 mutex_unlock(&dev->struct_mutex);
11855 * Return which encoder is currently attached for connector.
11857 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11859 return &intel_attached_encoder(connector)->base;
11862 void intel_connector_attach_encoder(struct intel_connector *connector,
11863 struct intel_encoder *encoder)
11865 connector->encoder = encoder;
11866 drm_mode_connector_attach_encoder(&connector->base,
11871 * set vga decode state - true == enable VGA decode
11873 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11875 struct drm_i915_private *dev_priv = dev->dev_private;
11876 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11879 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11880 DRM_ERROR("failed to read control word\n");
11884 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11888 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11890 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11892 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11893 DRM_ERROR("failed to write control word\n");
11900 struct intel_display_error_state {
11902 u32 power_well_driver;
11904 int num_transcoders;
11906 struct intel_cursor_error_state {
11911 } cursor[I915_MAX_PIPES];
11913 struct intel_pipe_error_state {
11914 bool power_domain_on;
11917 } pipe[I915_MAX_PIPES];
11919 struct intel_plane_error_state {
11927 } plane[I915_MAX_PIPES];
11929 struct intel_transcoder_error_state {
11930 bool power_domain_on;
11931 enum transcoder cpu_transcoder;
11944 struct intel_display_error_state *
11945 intel_display_capture_error_state(struct drm_device *dev)
11947 struct drm_i915_private *dev_priv = dev->dev_private;
11948 struct intel_display_error_state *error;
11949 int transcoders[] = {
11957 if (INTEL_INFO(dev)->num_pipes == 0)
11960 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11964 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11965 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11968 error->pipe[i].power_domain_on =
11969 intel_display_power_enabled_sw(dev_priv,
11970 POWER_DOMAIN_PIPE(i));
11971 if (!error->pipe[i].power_domain_on)
11974 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11975 error->cursor[i].control = I915_READ(CURCNTR(i));
11976 error->cursor[i].position = I915_READ(CURPOS(i));
11977 error->cursor[i].base = I915_READ(CURBASE(i));
11979 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11980 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11981 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11984 error->plane[i].control = I915_READ(DSPCNTR(i));
11985 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11986 if (INTEL_INFO(dev)->gen <= 3) {
11987 error->plane[i].size = I915_READ(DSPSIZE(i));
11988 error->plane[i].pos = I915_READ(DSPPOS(i));
11990 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11991 error->plane[i].addr = I915_READ(DSPADDR(i));
11992 if (INTEL_INFO(dev)->gen >= 4) {
11993 error->plane[i].surface = I915_READ(DSPSURF(i));
11994 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11997 error->pipe[i].source = I915_READ(PIPESRC(i));
11999 if (!HAS_PCH_SPLIT(dev))
12000 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12003 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12004 if (HAS_DDI(dev_priv->dev))
12005 error->num_transcoders++; /* Account for eDP. */
12007 for (i = 0; i < error->num_transcoders; i++) {
12008 enum transcoder cpu_transcoder = transcoders[i];
12010 error->transcoder[i].power_domain_on =
12011 intel_display_power_enabled_sw(dev_priv,
12012 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12013 if (!error->transcoder[i].power_domain_on)
12016 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12018 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12019 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12020 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12021 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12022 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12023 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12024 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12030 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12033 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12034 struct drm_device *dev,
12035 struct intel_display_error_state *error)
12042 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12043 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12044 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12045 error->power_well_driver);
12047 err_printf(m, "Pipe [%d]:\n", i);
12048 err_printf(m, " Power: %s\n",
12049 error->pipe[i].power_domain_on ? "on" : "off");
12050 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12051 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12053 err_printf(m, "Plane [%d]:\n", i);
12054 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12055 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12056 if (INTEL_INFO(dev)->gen <= 3) {
12057 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12058 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12060 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12061 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12062 if (INTEL_INFO(dev)->gen >= 4) {
12063 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12064 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12067 err_printf(m, "Cursor [%d]:\n", i);
12068 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12069 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12070 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12073 for (i = 0; i < error->num_transcoders; i++) {
12074 err_printf(m, "CPU transcoder: %c\n",
12075 transcoder_name(error->transcoder[i].cpu_transcoder));
12076 err_printf(m, " Power: %s\n",
12077 error->transcoder[i].power_domain_on ? "on" : "off");
12078 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12079 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12080 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12081 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12082 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12083 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12084 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);