2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
66 static const uint32_t skl_primary_formats[] = {
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
78 static const uint32_t intel_cursor_formats[] = {
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
95 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void chv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
107 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
109 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 int p2_slow, p2_fast;
122 typedef struct intel_limit intel_limit_t;
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_pch_rawclk(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 WARN_ON(!HAS_PCH_SPLIT(dev));
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
369 static const intel_limit_t intel_limits_vlv = {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv = {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
404 .vco = { .min = 4800000, .max = 6700000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
414 needs_modeset(struct drm_crtc_state *state)
416 return drm_atomic_crtc_needs_modeset(state);
420 * Returns whether any output on the specified pipe is of the specified type
422 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
424 struct drm_device *dev = crtc->base.dev;
425 struct intel_encoder *encoder;
427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
428 if (encoder->type == type)
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
440 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
443 struct drm_atomic_state *state = crtc_state->base.state;
444 struct drm_connector *connector;
445 struct drm_connector_state *connector_state;
446 struct intel_encoder *encoder;
447 int i, num_connectors = 0;
449 for_each_connector_in_state(state, connector, connector_state, i) {
450 if (connector_state->crtc != crtc_state->base.crtc)
455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
460 WARN_ON(num_connectors == 0);
465 static const intel_limit_t *
466 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
468 struct drm_device *dev = crtc_state->base.crtc->dev;
469 const intel_limit_t *limit;
471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
472 if (intel_is_dual_link_lvds(dev)) {
473 if (refclk == 100000)
474 limit = &intel_limits_ironlake_dual_lvds_100m;
476 limit = &intel_limits_ironlake_dual_lvds;
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_single_lvds_100m;
481 limit = &intel_limits_ironlake_single_lvds;
484 limit = &intel_limits_ironlake_dac;
489 static const intel_limit_t *
490 intel_g4x_limit(struct intel_crtc_state *crtc_state)
492 struct drm_device *dev = crtc_state->base.crtc->dev;
493 const intel_limit_t *limit;
495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
496 if (intel_is_dual_link_lvds(dev))
497 limit = &intel_limits_g4x_dual_channel_lvds;
499 limit = &intel_limits_g4x_single_channel_lvds;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
502 limit = &intel_limits_g4x_hdmi;
503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
504 limit = &intel_limits_g4x_sdvo;
505 } else /* The option is for other outputs */
506 limit = &intel_limits_i9xx_sdvo;
511 static const intel_limit_t *
512 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
514 struct drm_device *dev = crtc_state->base.crtc->dev;
515 const intel_limit_t *limit;
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
520 limit = intel_ironlake_limit(crtc_state, refclk);
521 else if (IS_G4X(dev)) {
522 limit = intel_g4x_limit(crtc_state);
523 } else if (IS_PINEVIEW(dev)) {
524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
525 limit = &intel_limits_pineview_lvds;
527 limit = &intel_limits_pineview_sdvo;
528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
530 } else if (IS_VALLEYVIEW(dev)) {
531 limit = &intel_limits_vlv;
532 } else if (!IS_GEN2(dev)) {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i9xx_lvds;
536 limit = &intel_limits_i9xx_sdvo;
538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
539 limit = &intel_limits_i8xx_lvds;
540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
541 limit = &intel_limits_i8xx_dvo;
543 limit = &intel_limits_i8xx_dac;
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
556 /* m1 is reserved as 0 in Pineview, n is a ring counter */
557 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
561 if (WARN_ON(clock->n == 0 || clock->p == 0))
563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
569 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
576 clock->m = i9xx_dpll_compute_m(clock);
577 clock->p = clock->p1 * clock->p2;
578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
586 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595 return clock->dot / 5;
598 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
608 return clock->dot / 5;
611 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
617 static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
624 INTELPllInvalid("p1 out of range\n");
625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
626 INTELPllInvalid("m2 out of range\n");
627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
628 INTELPllInvalid("m1 out of range\n");
630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
642 INTELPllInvalid("vco out of range\n");
643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
647 INTELPllInvalid("dot out of range\n");
653 i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
657 struct drm_device *dev = crtc_state->base.crtc->dev;
659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
665 if (intel_is_dual_link_lvds(dev))
666 return limit->p2.p2_fast;
668 return limit->p2.p2_slow;
670 if (target < limit->p2.dot_limit)
671 return limit->p2.p2_slow;
673 return limit->p2.p2_fast;
678 i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
683 struct drm_device *dev = crtc_state->base.crtc->dev;
687 memset(best_clock, 0, sizeof(*best_clock));
689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 if (clock.m2 >= clock.m1)
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
703 i9xx_calc_dpll_params(refclk, &clock);
704 if (!intel_PLL_is_valid(dev, limit,
708 clock.p != match_clock->p)
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
721 return (err != target);
725 pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
730 struct drm_device *dev = crtc_state->base.crtc->dev;
734 memset(best_clock, 0, sizeof(*best_clock));
736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
748 pnv_calc_dpll_params(refclk, &clock);
749 if (!intel_PLL_is_valid(dev, limit,
753 clock.p != match_clock->p)
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
766 return (err != target);
770 g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
775 struct drm_device *dev = crtc_state->base.crtc->dev;
779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
782 memset(best_clock, 0, sizeof(*best_clock));
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
786 max_n = limit->n.max;
787 /* based on hardware requirement, prefer smaller n to precision */
788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
789 /* based on hardware requirement, prefere larger m1,m2 */
790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
798 i9xx_calc_dpll_params(refclk, &clock);
799 if (!intel_PLL_is_valid(dev, limit,
803 this_err = abs(clock.dot - target);
804 if (this_err < err_most) {
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
821 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
831 if (IS_CHERRYVIEW(dev)) {
834 return calculated_clock->p > best_clock->p;
837 if (WARN_ON_ONCE(!target_freq))
840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 return *error_ppm + 10 < best_error_ppm;
858 vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
864 struct drm_device *dev = crtc->base.dev;
866 unsigned int bestppm = 1000000;
867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
871 target *= 5; /* fast clock */
873 memset(best_clock, 0, sizeof(*best_clock));
875 /* based on hardware requirement, prefer smaller n to precision */
876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
880 clock.p = clock.p1 * clock.p2;
881 /* based on hardware requirement, prefer bigger m1,m2 values */
882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
888 vlv_calc_dpll_params(refclk, &clock);
890 if (!intel_PLL_is_valid(dev, limit,
894 if (!vlv_PLL_is_optimal(dev, target,
912 chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
918 struct drm_device *dev = crtc->base.dev;
919 unsigned int best_error_ppm;
924 memset(best_clock, 0, sizeof(*best_clock));
925 best_error_ppm = 1000000;
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 unsigned int error_ppm;
941 clock.p = clock.p1 * clock.p2;
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
946 if (m2 > INT_MAX/clock.m1)
951 chv_calc_dpll_params(refclk, &clock);
953 if (!intel_PLL_is_valid(dev, limit, &clock))
956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
961 best_error_ppm = error_ppm;
969 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
972 int refclk = i9xx_get_refclk(crtc_state, 0);
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
978 bool intel_crtc_active(struct drm_crtc *crtc)
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
985 * We can ditch the adjusted_mode.crtc_clock check as soon
986 * as Haswell has gained clock readout/fastboot support.
988 * We can ditch the crtc->primary->fb check as soon as we can
989 * properly reconstruct framebuffers.
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
995 return intel_crtc->active && crtc->primary->state->fb &&
996 intel_crtc->config->base.adjusted_mode.crtc_clock;
999 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1005 return intel_crtc->config->cpu_transcoder;
1008 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1016 line_mask = DSL_LINEMASK_GEN2;
1018 line_mask = DSL_LINEMASK_GEN3;
1020 line1 = I915_READ(reg) & line_mask;
1022 line2 = I915_READ(reg) & line_mask;
1024 return line1 == line2;
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
1029 * @crtc: crtc whose pipe to wait for
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
1043 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1045 struct drm_device *dev = crtc->base.dev;
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1048 enum pipe pipe = crtc->pipe;
1050 if (INTEL_INFO(dev)->gen >= 4) {
1051 int reg = PIPECONF(cpu_transcoder);
1053 /* Wait for the Pipe State to go off */
1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1056 WARN(1, "pipe_off wait timed out\n");
1058 /* Wait for the display line to settle */
1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1060 WARN(1, "pipe_off wait timed out\n");
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1069 * Returns true if @port is connected, false otherwise.
1071 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1076 if (HAS_PCH_IBX(dev_priv->dev)) {
1077 switch (port->port) {
1079 bit = SDE_PORTB_HOTPLUG;
1082 bit = SDE_PORTC_HOTPLUG;
1085 bit = SDE_PORTD_HOTPLUG;
1091 switch (port->port) {
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1106 return I915_READ(SDEISR) & bit;
1109 static const char *state_string(bool enabled)
1111 return enabled ? "on" : "off";
1114 /* Only for pre-ILK configs */
1115 void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
1125 I915_STATE_WARN(cur_state != state,
1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1130 /* XXX: the dsi pll is shared between MIPI DSI ports */
1131 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1136 mutex_lock(&dev_priv->sb_lock);
1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1138 mutex_unlock(&dev_priv->sb_lock);
1140 cur_state = val & DSI_PLL_VCO_EN;
1141 I915_STATE_WARN(cur_state != state,
1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1145 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1148 struct intel_shared_dpll *
1149 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1153 if (crtc->config->shared_dpll < 0)
1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1165 struct intel_dpll_hw_state hw_state;
1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1172 I915_STATE_WARN(cur_state != state,
1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
1177 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1196 I915_STATE_WARN(cur_state != state,
1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1200 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1203 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
1213 I915_STATE_WARN(cur_state != state,
1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1217 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1220 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 /* ILK FDI PLL is always enabled */
1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1231 if (HAS_DDI(dev_priv->dev))
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1239 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1254 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1257 struct drm_device *dev = dev_priv->dev;
1260 enum pipe panel_pipe = PIPE_A;
1263 if (WARN_ON(HAS_DDI(dev)))
1266 if (HAS_PCH_SPLIT(dev)) {
1269 pp_reg = PCH_PP_CONTROL;
1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1281 pp_reg = PP_CONTROL;
1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1291 I915_STATE_WARN(panel_pipe == pipe && locked,
1292 "panel assertion failure, pipe %c regs locked\n",
1296 static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1299 struct drm_device *dev = dev_priv->dev;
1302 if (IS_845G(dev) || IS_I865G(dev))
1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1307 I915_STATE_WARN(cur_state != state,
1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1311 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1314 void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1328 if (!intel_display_power_is_enabled(dev_priv,
1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1337 I915_STATE_WARN(cur_state != state,
1338 "pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1342 static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1352 I915_STATE_WARN(cur_state != state,
1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
1357 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1360 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1363 struct drm_device *dev = dev_priv->dev;
1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1373 "plane %c assertion failure, should be disabled but not\n",
1378 /* Need to check both planes against the pipe */
1379 for_each_pipe(dev_priv, i) {
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
1390 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1393 struct drm_device *dev = dev_priv->dev;
1397 if (INTEL_INFO(dev)->gen >= 9) {
1398 for_each_sprite(dev_priv, pipe, sprite) {
1399 val = I915_READ(PLANE_CTL(pipe, sprite));
1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1404 } else if (IS_VALLEYVIEW(dev)) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 reg = SPCNTR(pipe, sprite);
1407 val = I915_READ(reg);
1408 I915_STATE_WARN(val & SP_ENABLE,
1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1410 sprite_name(pipe, sprite), pipe_name(pipe));
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SPRITE_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
1420 val = I915_READ(reg);
1421 I915_STATE_WARN(val & DVS_ENABLE,
1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1423 plane_name(pipe), pipe_name(pipe));
1427 static void assert_vblank_disabled(struct drm_crtc *crtc)
1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1430 drm_crtc_vblank_put(crtc);
1433 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1446 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1453 reg = PCH_TRANSCONF(pipe);
1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
1456 I915_STATE_WARN(enabled,
1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
1464 if ((val & DP_PORT_EN) == 0)
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1485 if ((val & SDVO_ENABLE) == 0)
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1501 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1504 if ((val & LVDS_PORT_EN) == 0)
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, int reg, u32 port_sel)
1535 u32 val = I915_READ(reg);
1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1538 reg, pipe_name(pipe));
1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1541 && (val & DP_PIPEB_SELECT),
1542 "IBX PCH dp port still using transcoder B\n");
1545 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1548 u32 val = I915_READ(reg);
1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1551 reg, pipe_name(pipe));
1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1554 && (val & SDVO_PIPE_B_SELECT),
1555 "IBX PCH hdmi port still using transcoder B\n");
1558 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1569 val = I915_READ(reg);
1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 val = I915_READ(reg);
1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1585 static void intel_init_dpio(struct drm_device *dev)
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1589 if (!IS_VALLEYVIEW(dev))
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 static void vlv_enable_pll(struct intel_crtc *crtc,
1606 const struct intel_crtc_state *pipe_config)
1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
1613 assert_pipe_disabled(dev_priv, crtc->pipe);
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1618 /* PLL is protected by panel, make sure we can write it */
1619 if (IS_MOBILE(dev_priv->dev))
1620 assert_panel_unlocked(dev_priv, crtc->pipe);
1622 I915_WRITE(reg, dpll);
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1630 POSTING_READ(DPLL_MD(crtc->pipe));
1632 /* We do this three times for luck */
1633 I915_WRITE(reg, dpll);
1635 udelay(150); /* wait for warmup */
1636 I915_WRITE(reg, dpll);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1641 udelay(150); /* wait for warmup */
1644 static void chv_enable_pll(struct intel_crtc *crtc,
1645 const struct intel_crtc_state *pipe_config)
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1657 mutex_lock(&dev_priv->sb_lock);
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1664 mutex_unlock(&dev_priv->sb_lock);
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674 /* Check PLL is locked */
1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678 /* not sure when this should be written */
1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1680 POSTING_READ(DPLL_MD(pipe));
1683 static int intel_num_dvo_pipes(struct drm_device *dev)
1685 struct intel_crtc *crtc;
1688 for_each_intel_crtc(dev, crtc)
1689 count += crtc->base.state->active &&
1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1695 static void i9xx_enable_pll(struct intel_crtc *crtc)
1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
1702 assert_pipe_disabled(dev_priv, crtc->pipe);
1704 /* No really, not for ILK+ */
1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1707 /* PLL is protected by panel, make sure we can write it */
1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1724 /* Wait for the clocks to stabilize. */
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
1730 crtc->config->dpll_hw_state.dpll_md);
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1735 * So write it again.
1737 I915_WRITE(reg, dpll);
1740 /* We do this three times for luck */
1741 I915_WRITE(reg, dpll);
1743 udelay(150); /* wait for warmup */
1744 I915_WRITE(reg, dpll);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1749 udelay(150); /* wait for warmup */
1753 * i9xx_disable_pll - disable a PLL
1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 * Note! This is for pre-ILK only.
1761 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1770 !intel_num_dvo_pipes(dev)) {
1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1786 POSTING_READ(DPLL(pipe));
1789 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1800 val = DPLL_VGA_MODE_DIS;
1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
1808 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
1816 /* Set PLL en = 0 */
1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
1824 mutex_lock(&dev_priv->sb_lock);
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 mutex_unlock(&dev_priv->sb_lock);
1845 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
1852 switch (dport->port) {
1854 port_mask = DPLL_PORTB_READY_MASK;
1858 port_mask = DPLL_PORTC_READY_MASK;
1860 expected_mask <<= 4;
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1875 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881 if (WARN_ON(pll == NULL))
1884 WARN_ON(!pll->config.crtc_mask);
1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1890 pll->mode_set(dev_priv, pll);
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1902 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908 if (WARN_ON(pll == NULL))
1911 if (WARN_ON(pll->config.crtc_mask == 0))
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll->name, pll->active, pll->on,
1916 crtc->base.base.id);
1918 if (pll->active++) {
1920 assert_shared_dpll_enabled(dev_priv, pll);
1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1928 pll->enable(dev_priv, pll);
1932 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
1943 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
1948 crtc->base.base.id);
1950 if (WARN_ON(pll->active == 0)) {
1951 assert_shared_dpll_disabled(dev_priv, pll);
1955 assert_shared_dpll_enabled(dev_priv, pll);
1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1961 pll->disable(dev_priv, pll);
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1967 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 struct drm_device *dev = dev_priv->dev;
1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1973 uint32_t reg, val, pipeconf_val;
1975 /* PCH only available on ILK+ */
1976 BUG_ON(!HAS_PCH_SPLIT(dev));
1978 /* Make sure PCH DPLL is enabled */
1979 assert_shared_dpll_enabled(dev_priv,
1980 intel_crtc_to_shared_dpll(intel_crtc));
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 pipeconf_val = I915_READ(PIPECONF(pipe));
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 * Make the BPC in transcoder be consistent with
2002 * that in pipeconf reg. For HDMI we must use 8bpc
2003 * here for both 8bpc and 12bpc.
2005 val &= ~PIPECONF_BPC_MASK;
2006 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2007 val |= PIPECONF_8BPC;
2009 val |= pipeconf_val & PIPECONF_BPC_MASK;
2012 val &= ~TRANS_INTERLACE_MASK;
2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2014 if (HAS_PCH_IBX(dev_priv->dev) &&
2015 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2016 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 val |= TRANS_INTERLACED;
2020 val |= TRANS_PROGRESSIVE;
2022 I915_WRITE(reg, val | TRANS_ENABLE);
2023 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2024 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2027 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2028 enum transcoder cpu_transcoder)
2030 u32 val, pipeconf_val;
2032 /* PCH only available on ILK+ */
2033 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035 /* FDI must be feeding us bits for PCH ports */
2036 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2037 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039 /* Workaround: set timing override bit. */
2040 val = I915_READ(_TRANSA_CHICKEN2);
2041 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2042 I915_WRITE(_TRANSA_CHICKEN2, val);
2045 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2048 PIPECONF_INTERLACED_ILK)
2049 val |= TRANS_INTERLACED;
2051 val |= TRANS_PROGRESSIVE;
2053 I915_WRITE(LPT_TRANSCONF, val);
2054 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2055 DRM_ERROR("Failed to enable PCH transcoder\n");
2058 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 struct drm_device *dev = dev_priv->dev;
2064 /* FDI relies on the transcoder */
2065 assert_fdi_tx_disabled(dev_priv, pipe);
2066 assert_fdi_rx_disabled(dev_priv, pipe);
2068 /* Ports must be off as well */
2069 assert_pch_ports_disabled(dev_priv, pipe);
2071 reg = PCH_TRANSCONF(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_ENABLE;
2074 I915_WRITE(reg, val);
2075 /* wait for PCH transcoder off, transcoder state */
2076 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2077 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079 if (!HAS_PCH_IBX(dev)) {
2080 /* Workaround: Clear the timing override chicken bit again. */
2081 reg = TRANS_CHICKEN2(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2084 I915_WRITE(reg, val);
2088 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2092 val = I915_READ(LPT_TRANSCONF);
2093 val &= ~TRANS_ENABLE;
2094 I915_WRITE(LPT_TRANSCONF, val);
2095 /* wait for PCH transcoder off, transcoder state */
2096 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2097 DRM_ERROR("Failed to disable PCH transcoder\n");
2099 /* Workaround: clear timing override bit. */
2100 val = I915_READ(_TRANSA_CHICKEN2);
2101 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2102 I915_WRITE(_TRANSA_CHICKEN2, val);
2106 * intel_enable_pipe - enable a pipe, asserting requirements
2107 * @crtc: crtc responsible for the pipe
2109 * Enable @crtc's pipe, making sure that various hardware specific requirements
2110 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 struct drm_device *dev = crtc->base.dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 enum pipe pipe = crtc->pipe;
2117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 enum pipe pch_transcoder;
2123 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2125 assert_planes_disabled(dev_priv, pipe);
2126 assert_cursor_disabled(dev_priv, pipe);
2127 assert_sprites_disabled(dev_priv, pipe);
2129 if (HAS_PCH_LPT(dev_priv->dev))
2130 pch_transcoder = TRANSCODER_A;
2132 pch_transcoder = pipe;
2135 * A pipe without a PLL won't actually be able to drive bits from
2136 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2140 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2141 assert_dsi_pll_enabled(dev_priv);
2143 assert_pll_enabled(dev_priv, pipe);
2145 if (crtc->config->has_pch_encoder) {
2146 /* if driving the PCH, we need FDI enabled */
2147 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2148 assert_fdi_tx_pll_enabled(dev_priv,
2149 (enum pipe) cpu_transcoder);
2151 /* FIXME: assert CPU port conditions for SNB+ */
2154 reg = PIPECONF(cpu_transcoder);
2155 val = I915_READ(reg);
2156 if (val & PIPECONF_ENABLE) {
2157 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2162 I915_WRITE(reg, val | PIPECONF_ENABLE);
2167 * intel_disable_pipe - disable a pipe, asserting requirements
2168 * @crtc: crtc whose pipes is to be disabled
2170 * Disable the pipe of @crtc, making sure that various hardware
2171 * specific requirements are met, if applicable, e.g. plane
2172 * disabled, panel fitter off, etc.
2174 * Will wait until the pipe has shut down before returning.
2176 static void intel_disable_pipe(struct intel_crtc *crtc)
2178 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2179 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2180 enum pipe pipe = crtc->pipe;
2184 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187 * Make sure planes won't keep trying to pump pixels to us,
2188 * or we might hang the display.
2190 assert_planes_disabled(dev_priv, pipe);
2191 assert_cursor_disabled(dev_priv, pipe);
2192 assert_sprites_disabled(dev_priv, pipe);
2194 reg = PIPECONF(cpu_transcoder);
2195 val = I915_READ(reg);
2196 if ((val & PIPECONF_ENABLE) == 0)
2200 * Double wide has implications for planes
2201 * so best keep it disabled when not needed.
2203 if (crtc->config->double_wide)
2204 val &= ~PIPECONF_DOUBLE_WIDE;
2206 /* Don't disable pipe or pipe PLLs if needed */
2207 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2208 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2209 val &= ~PIPECONF_ENABLE;
2211 I915_WRITE(reg, val);
2212 if ((val & PIPECONF_ENABLE) == 0)
2213 intel_wait_for_pipe_off(crtc);
2216 static bool need_vtd_wa(struct drm_device *dev)
2218 #ifdef CONFIG_INTEL_IOMMU
2219 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2226 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2227 uint64_t fb_format_modifier)
2229 unsigned int tile_height;
2230 uint32_t pixel_bytes;
2232 switch (fb_format_modifier) {
2233 case DRM_FORMAT_MOD_NONE:
2236 case I915_FORMAT_MOD_X_TILED:
2237 tile_height = IS_GEN2(dev) ? 16 : 8;
2239 case I915_FORMAT_MOD_Y_TILED:
2242 case I915_FORMAT_MOD_Yf_TILED:
2243 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2244 switch (pixel_bytes) {
2258 "128-bit pixels are not supported for display!");
2264 MISSING_CASE(fb_format_modifier);
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_format_modifier)
2276 return ALIGN(height, intel_tile_height(dev, pixel_format,
2277 fb_format_modifier));
2281 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2282 const struct drm_plane_state *plane_state)
2284 struct intel_rotation_info *info = &view->rotation_info;
2285 unsigned int tile_height, tile_pitch;
2287 *view = i915_ggtt_view_normal;
2292 if (!intel_rotation_90_or_270(plane_state->rotation))
2295 *view = i915_ggtt_view_rotated;
2297 info->height = fb->height;
2298 info->pixel_format = fb->pixel_format;
2299 info->pitch = fb->pitches[0];
2300 info->fb_modifier = fb->modifier[0];
2302 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 tile_pitch = PAGE_SIZE / tile_height;
2305 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2306 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2307 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2312 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2314 if (INTEL_INFO(dev_priv)->gen >= 9)
2316 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317 IS_VALLEYVIEW(dev_priv))
2319 else if (INTEL_INFO(dev_priv)->gen >= 4)
2326 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327 struct drm_framebuffer *fb,
2328 const struct drm_plane_state *plane_state,
2329 struct intel_engine_cs *pipelined,
2330 struct drm_i915_gem_request **pipelined_request)
2332 struct drm_device *dev = fb->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2335 struct i915_ggtt_view view;
2339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
2343 alignment = intel_linear_alignment(dev_priv);
2345 case I915_FORMAT_MOD_X_TILED:
2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2349 /* pin() will align the object as required by fence */
2353 case I915_FORMAT_MOD_Y_TILED:
2354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2358 alignment = 1 * 1024 * 1024;
2361 MISSING_CASE(fb->modifier[0]);
2365 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2369 /* Note that the w/a also requires 64 PTE of padding following the
2370 * bo. We currently fill all unused PTE with the shadow page and so
2371 * we should always have valid PTE following the scanout preventing
2374 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2375 alignment = 256 * 1024;
2378 * Global gtt pte registers are special registers which actually forward
2379 * writes to a chunk of system memory. Which means that there is no risk
2380 * that the register values disappear as soon as we call
2381 * intel_runtime_pm_put(), so it is correct to wrap only the
2382 * pin/unpin/fence and not more.
2384 intel_runtime_pm_get(dev_priv);
2386 dev_priv->mm.interruptible = false;
2387 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2388 pipelined_request, &view);
2390 goto err_interruptible;
2392 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393 * fence, whereas 965+ only requires a fence if using
2394 * framebuffer compression. For simplicity, we always install
2395 * a fence as the cost is not that onerous.
2397 ret = i915_gem_object_get_fence(obj);
2401 i915_gem_object_pin_fence(obj);
2403 dev_priv->mm.interruptible = true;
2404 intel_runtime_pm_put(dev_priv);
2408 i915_gem_object_unpin_from_display_plane(obj, &view);
2410 dev_priv->mm.interruptible = true;
2411 intel_runtime_pm_put(dev_priv);
2415 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416 const struct drm_plane_state *plane_state)
2418 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2419 struct i915_ggtt_view view;
2422 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2424 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425 WARN_ONCE(ret, "Couldn't get view from plane state!");
2427 i915_gem_object_unpin_fence(obj);
2428 i915_gem_object_unpin_from_display_plane(obj, &view);
2431 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432 * is assumed to be a power-of-two. */
2433 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2435 unsigned int tiling_mode,
2439 if (tiling_mode != I915_TILING_NONE) {
2440 unsigned int tile_rows, tiles;
2445 tiles = *x / (512/cpp);
2448 return tile_rows * pitch * 8 + tiles * 4096;
2450 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2451 unsigned int offset;
2453 offset = *y * pitch + *x * cpp;
2454 *y = (offset & alignment) / pitch;
2455 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset & ~alignment;
2460 static int i9xx_format_to_fourcc(int format)
2463 case DISPPLANE_8BPP:
2464 return DRM_FORMAT_C8;
2465 case DISPPLANE_BGRX555:
2466 return DRM_FORMAT_XRGB1555;
2467 case DISPPLANE_BGRX565:
2468 return DRM_FORMAT_RGB565;
2470 case DISPPLANE_BGRX888:
2471 return DRM_FORMAT_XRGB8888;
2472 case DISPPLANE_RGBX888:
2473 return DRM_FORMAT_XBGR8888;
2474 case DISPPLANE_BGRX101010:
2475 return DRM_FORMAT_XRGB2101010;
2476 case DISPPLANE_RGBX101010:
2477 return DRM_FORMAT_XBGR2101010;
2481 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484 case PLANE_CTL_FORMAT_RGB_565:
2485 return DRM_FORMAT_RGB565;
2487 case PLANE_CTL_FORMAT_XRGB_8888:
2490 return DRM_FORMAT_ABGR8888;
2492 return DRM_FORMAT_XBGR8888;
2495 return DRM_FORMAT_ARGB8888;
2497 return DRM_FORMAT_XRGB8888;
2499 case PLANE_CTL_FORMAT_XRGB_2101010:
2501 return DRM_FORMAT_XBGR2101010;
2503 return DRM_FORMAT_XRGB2101010;
2508 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509 struct intel_initial_plane_config *plane_config)
2511 struct drm_device *dev = crtc->base.dev;
2512 struct drm_i915_gem_object *obj = NULL;
2513 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2514 struct drm_framebuffer *fb = &plane_config->fb->base;
2515 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2516 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 size_aligned -= base_aligned;
2521 if (plane_config->size == 0)
2524 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2531 obj->tiling_mode = plane_config->tiling;
2532 if (obj->tiling_mode == I915_TILING_X)
2533 obj->stride = fb->pitches[0];
2535 mode_cmd.pixel_format = fb->pixel_format;
2536 mode_cmd.width = fb->width;
2537 mode_cmd.height = fb->height;
2538 mode_cmd.pitches[0] = fb->pitches[0];
2539 mode_cmd.modifier[0] = fb->modifier[0];
2540 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2542 mutex_lock(&dev->struct_mutex);
2543 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2545 DRM_DEBUG_KMS("intel fb init failed\n");
2548 mutex_unlock(&dev->struct_mutex);
2550 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2554 drm_gem_object_unreference(&obj->base);
2555 mutex_unlock(&dev->struct_mutex);
2559 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2561 update_state_fb(struct drm_plane *plane)
2563 if (plane->fb == plane->state->fb)
2566 if (plane->state->fb)
2567 drm_framebuffer_unreference(plane->state->fb);
2568 plane->state->fb = plane->fb;
2569 if (plane->state->fb)
2570 drm_framebuffer_reference(plane->state->fb);
2574 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2575 struct intel_initial_plane_config *plane_config)
2577 struct drm_device *dev = intel_crtc->base.dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *i;
2581 struct drm_i915_gem_object *obj;
2582 struct drm_plane *primary = intel_crtc->base.primary;
2583 struct drm_plane_state *plane_state = primary->state;
2584 struct drm_framebuffer *fb;
2586 if (!plane_config->fb)
2589 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2590 fb = &plane_config->fb->base;
2594 kfree(plane_config->fb);
2597 * Failed to alloc the obj, check to see if we should share
2598 * an fb with another CRTC instead
2600 for_each_crtc(dev, c) {
2601 i = to_intel_crtc(c);
2603 if (c == &intel_crtc->base)
2609 fb = c->primary->fb;
2613 obj = intel_fb_obj(fb);
2614 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2615 drm_framebuffer_reference(fb);
2623 plane_state->src_x = plane_state->src_y = 0;
2624 plane_state->src_w = fb->width << 16;
2625 plane_state->src_h = fb->height << 16;
2627 plane_state->crtc_x = plane_state->src_y = 0;
2628 plane_state->crtc_w = fb->width;
2629 plane_state->crtc_h = fb->height;
2631 obj = intel_fb_obj(fb);
2632 if (obj->tiling_mode != I915_TILING_NONE)
2633 dev_priv->preserve_bios_swizzle = true;
2635 drm_framebuffer_reference(fb);
2636 primary->fb = primary->state->fb = fb;
2637 primary->crtc = primary->state->crtc = &intel_crtc->base;
2638 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2639 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2642 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2643 struct drm_framebuffer *fb,
2646 struct drm_device *dev = crtc->dev;
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2649 struct drm_plane *primary = crtc->primary;
2650 bool visible = to_intel_plane_state(primary->state)->visible;
2651 struct drm_i915_gem_object *obj;
2652 int plane = intel_crtc->plane;
2653 unsigned long linear_offset;
2655 u32 reg = DSPCNTR(plane);
2658 if (!visible || !fb) {
2660 if (INTEL_INFO(dev)->gen >= 4)
2661 I915_WRITE(DSPSURF(plane), 0);
2663 I915_WRITE(DSPADDR(plane), 0);
2668 obj = intel_fb_obj(fb);
2669 if (WARN_ON(obj == NULL))
2672 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2674 dspcntr = DISPPLANE_GAMMA_ENABLE;
2676 dspcntr |= DISPLAY_PLANE_ENABLE;
2678 if (INTEL_INFO(dev)->gen < 4) {
2679 if (intel_crtc->pipe == PIPE_B)
2680 dspcntr |= DISPPLANE_SEL_PIPE_B;
2682 /* pipesrc and dspsize control the size that is scaled from,
2683 * which should always be the user's requested size.
2685 I915_WRITE(DSPSIZE(plane),
2686 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2687 (intel_crtc->config->pipe_src_w - 1));
2688 I915_WRITE(DSPPOS(plane), 0);
2689 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2690 I915_WRITE(PRIMSIZE(plane),
2691 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2692 (intel_crtc->config->pipe_src_w - 1));
2693 I915_WRITE(PRIMPOS(plane), 0);
2694 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2697 switch (fb->pixel_format) {
2699 dspcntr |= DISPPLANE_8BPP;
2701 case DRM_FORMAT_XRGB1555:
2702 dspcntr |= DISPPLANE_BGRX555;
2704 case DRM_FORMAT_RGB565:
2705 dspcntr |= DISPPLANE_BGRX565;
2707 case DRM_FORMAT_XRGB8888:
2708 dspcntr |= DISPPLANE_BGRX888;
2710 case DRM_FORMAT_XBGR8888:
2711 dspcntr |= DISPPLANE_RGBX888;
2713 case DRM_FORMAT_XRGB2101010:
2714 dspcntr |= DISPPLANE_BGRX101010;
2716 case DRM_FORMAT_XBGR2101010:
2717 dspcntr |= DISPPLANE_RGBX101010;
2723 if (INTEL_INFO(dev)->gen >= 4 &&
2724 obj->tiling_mode != I915_TILING_NONE)
2725 dspcntr |= DISPPLANE_TILED;
2728 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2730 linear_offset = y * fb->pitches[0] + x * pixel_size;
2732 if (INTEL_INFO(dev)->gen >= 4) {
2733 intel_crtc->dspaddr_offset =
2734 intel_gen4_compute_page_offset(dev_priv,
2735 &x, &y, obj->tiling_mode,
2738 linear_offset -= intel_crtc->dspaddr_offset;
2740 intel_crtc->dspaddr_offset = linear_offset;
2743 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2744 dspcntr |= DISPPLANE_ROTATE_180;
2746 x += (intel_crtc->config->pipe_src_w - 1);
2747 y += (intel_crtc->config->pipe_src_h - 1);
2749 /* Finding the last pixel of the last line of the display
2750 data and adding to linear_offset*/
2752 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2753 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756 I915_WRITE(reg, dspcntr);
2758 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2759 if (INTEL_INFO(dev)->gen >= 4) {
2760 I915_WRITE(DSPSURF(plane),
2761 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2762 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2763 I915_WRITE(DSPLINOFF(plane), linear_offset);
2765 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2769 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2770 struct drm_framebuffer *fb,
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 struct drm_plane *primary = crtc->primary;
2777 bool visible = to_intel_plane_state(primary->state)->visible;
2778 struct drm_i915_gem_object *obj;
2779 int plane = intel_crtc->plane;
2780 unsigned long linear_offset;
2782 u32 reg = DSPCNTR(plane);
2785 if (!visible || !fb) {
2787 I915_WRITE(DSPSURF(plane), 0);
2792 obj = intel_fb_obj(fb);
2793 if (WARN_ON(obj == NULL))
2796 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2798 dspcntr = DISPPLANE_GAMMA_ENABLE;
2800 dspcntr |= DISPLAY_PLANE_ENABLE;
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2805 switch (fb->pixel_format) {
2807 dspcntr |= DISPPLANE_8BPP;
2809 case DRM_FORMAT_RGB565:
2810 dspcntr |= DISPPLANE_BGRX565;
2812 case DRM_FORMAT_XRGB8888:
2813 dspcntr |= DISPPLANE_BGRX888;
2815 case DRM_FORMAT_XBGR8888:
2816 dspcntr |= DISPPLANE_RGBX888;
2818 case DRM_FORMAT_XRGB2101010:
2819 dspcntr |= DISPPLANE_BGRX101010;
2821 case DRM_FORMAT_XBGR2101010:
2822 dspcntr |= DISPPLANE_RGBX101010;
2828 if (obj->tiling_mode != I915_TILING_NONE)
2829 dspcntr |= DISPPLANE_TILED;
2831 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2832 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2834 linear_offset = y * fb->pitches[0] + x * pixel_size;
2835 intel_crtc->dspaddr_offset =
2836 intel_gen4_compute_page_offset(dev_priv,
2837 &x, &y, obj->tiling_mode,
2840 linear_offset -= intel_crtc->dspaddr_offset;
2841 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2842 dspcntr |= DISPPLANE_ROTATE_180;
2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2845 x += (intel_crtc->config->pipe_src_w - 1);
2846 y += (intel_crtc->config->pipe_src_h - 1);
2848 /* Finding the last pixel of the last line of the display
2849 data and adding to linear_offset*/
2851 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2852 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2856 I915_WRITE(reg, dspcntr);
2858 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2859 I915_WRITE(DSPSURF(plane),
2860 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2861 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2862 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2864 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2865 I915_WRITE(DSPLINOFF(plane), linear_offset);
2870 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2871 uint32_t pixel_format)
2873 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2876 * The stride is either expressed as a multiple of 64 bytes
2877 * chunks for linear buffers or in number of tiles for tiled
2880 switch (fb_modifier) {
2881 case DRM_FORMAT_MOD_NONE:
2883 case I915_FORMAT_MOD_X_TILED:
2884 if (INTEL_INFO(dev)->gen == 2)
2887 case I915_FORMAT_MOD_Y_TILED:
2888 /* No need to check for old gens and Y tiling since this is
2889 * about the display engine and those will be blocked before
2893 case I915_FORMAT_MOD_Yf_TILED:
2894 if (bits_per_pixel == 8)
2899 MISSING_CASE(fb_modifier);
2904 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2905 struct drm_i915_gem_object *obj)
2907 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2909 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2910 view = &i915_ggtt_view_rotated;
2912 return i915_gem_obj_ggtt_offset_view(obj, view);
2915 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2917 struct drm_device *dev = intel_crtc->base.dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2920 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2921 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2922 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2923 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2924 intel_crtc->base.base.id, intel_crtc->pipe, id);
2928 * This function detaches (aka. unbinds) unused scalers in hardware
2930 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2932 struct intel_crtc_scaler_state *scaler_state;
2935 scaler_state = &intel_crtc->config->scaler_state;
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use)
2940 skl_detach_scaler(intel_crtc, i);
2944 u32 skl_plane_ctl_format(uint32_t pixel_format)
2946 switch (pixel_format) {
2948 return PLANE_CTL_FORMAT_INDEXED;
2949 case DRM_FORMAT_RGB565:
2950 return PLANE_CTL_FORMAT_RGB_565;
2951 case DRM_FORMAT_XBGR8888:
2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2953 case DRM_FORMAT_XRGB8888:
2954 return PLANE_CTL_FORMAT_XRGB_8888;
2956 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957 * to be already pre-multiplied. We need to add a knob (or a different
2958 * DRM_FORMAT) for user-space to configure that.
2960 case DRM_FORMAT_ABGR8888:
2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2963 case DRM_FORMAT_ARGB8888:
2964 return PLANE_CTL_FORMAT_XRGB_8888 |
2965 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2966 case DRM_FORMAT_XRGB2101010:
2967 return PLANE_CTL_FORMAT_XRGB_2101010;
2968 case DRM_FORMAT_XBGR2101010:
2969 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2970 case DRM_FORMAT_YUYV:
2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2972 case DRM_FORMAT_YVYU:
2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2974 case DRM_FORMAT_UYVY:
2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2976 case DRM_FORMAT_VYUY:
2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2979 MISSING_CASE(pixel_format);
2985 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2987 switch (fb_modifier) {
2988 case DRM_FORMAT_MOD_NONE:
2990 case I915_FORMAT_MOD_X_TILED:
2991 return PLANE_CTL_TILED_X;
2992 case I915_FORMAT_MOD_Y_TILED:
2993 return PLANE_CTL_TILED_Y;
2994 case I915_FORMAT_MOD_Yf_TILED:
2995 return PLANE_CTL_TILED_YF;
2997 MISSING_CASE(fb_modifier);
3003 u32 skl_plane_ctl_rotation(unsigned int rotation)
3006 case BIT(DRM_ROTATE_0):
3009 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010 * while i915 HW rotation is clockwise, thats why this swapping.
3012 case BIT(DRM_ROTATE_90):
3013 return PLANE_CTL_ROTATE_270;
3014 case BIT(DRM_ROTATE_180):
3015 return PLANE_CTL_ROTATE_180;
3016 case BIT(DRM_ROTATE_270):
3017 return PLANE_CTL_ROTATE_90;
3019 MISSING_CASE(rotation);
3025 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3026 struct drm_framebuffer *fb,
3029 struct drm_device *dev = crtc->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032 struct drm_plane *plane = crtc->primary;
3033 bool visible = to_intel_plane_state(plane->state)->visible;
3034 struct drm_i915_gem_object *obj;
3035 int pipe = intel_crtc->pipe;
3036 u32 plane_ctl, stride_div, stride;
3037 u32 tile_height, plane_offset, plane_size;
3038 unsigned int rotation;
3039 int x_offset, y_offset;
3040 unsigned long surf_addr;
3041 struct intel_crtc_state *crtc_state = intel_crtc->config;
3042 struct intel_plane_state *plane_state;
3043 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3044 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3047 plane_state = to_intel_plane_state(plane->state);
3049 if (!visible || !fb) {
3050 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3051 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3052 POSTING_READ(PLANE_CTL(pipe, 0));
3056 plane_ctl = PLANE_CTL_ENABLE |
3057 PLANE_CTL_PIPE_GAMMA_ENABLE |
3058 PLANE_CTL_PIPE_CSC_ENABLE;
3060 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3061 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3062 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3064 rotation = plane->state->rotation;
3065 plane_ctl |= skl_plane_ctl_rotation(rotation);
3067 obj = intel_fb_obj(fb);
3068 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3070 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3073 * FIXME: intel_plane_state->src, dst aren't set when transitional
3074 * update_plane helpers are called from legacy paths.
3075 * Once full atomic crtc is available, below check can be avoided.
3077 if (drm_rect_width(&plane_state->src)) {
3078 scaler_id = plane_state->scaler_id;
3079 src_x = plane_state->src.x1 >> 16;
3080 src_y = plane_state->src.y1 >> 16;
3081 src_w = drm_rect_width(&plane_state->src) >> 16;
3082 src_h = drm_rect_height(&plane_state->src) >> 16;
3083 dst_x = plane_state->dst.x1;
3084 dst_y = plane_state->dst.y1;
3085 dst_w = drm_rect_width(&plane_state->dst);
3086 dst_h = drm_rect_height(&plane_state->dst);
3088 WARN_ON(x != src_x || y != src_y);
3090 src_w = intel_crtc->config->pipe_src_w;
3091 src_h = intel_crtc->config->pipe_src_h;
3094 if (intel_rotation_90_or_270(rotation)) {
3095 /* stride = Surface height in tiles */
3096 tile_height = intel_tile_height(dev, fb->pixel_format,
3098 stride = DIV_ROUND_UP(fb->height, tile_height);
3099 x_offset = stride * tile_height - y - src_h;
3101 plane_size = (src_w - 1) << 16 | (src_h - 1);
3103 stride = fb->pitches[0] / stride_div;
3106 plane_size = (src_h - 1) << 16 | (src_w - 1);
3108 plane_offset = y_offset << 16 | x_offset;
3110 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3111 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3112 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3113 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3115 if (scaler_id >= 0) {
3116 uint32_t ps_ctrl = 0;
3118 WARN_ON(!dst_w || !dst_h);
3119 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3120 crtc_state->scaler_state.scalers[scaler_id].mode;
3121 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3122 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3123 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3124 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3125 I915_WRITE(PLANE_POS(pipe, 0), 0);
3127 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3130 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3132 POSTING_READ(PLANE_SURF(pipe, 0));
3135 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3137 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3138 int x, int y, enum mode_set_atomic state)
3140 struct drm_device *dev = crtc->dev;
3141 struct drm_i915_private *dev_priv = dev->dev_private;
3143 if (dev_priv->fbc.disable_fbc)
3144 dev_priv->fbc.disable_fbc(dev_priv);
3146 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3151 static void intel_complete_page_flips(struct drm_device *dev)
3153 struct drm_crtc *crtc;
3155 for_each_crtc(dev, crtc) {
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157 enum plane plane = intel_crtc->plane;
3159 intel_prepare_page_flip(dev, plane);
3160 intel_finish_page_flip_plane(dev, plane);
3164 static void intel_update_primary_planes(struct drm_device *dev)
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct drm_crtc *crtc;
3169 for_each_crtc(dev, crtc) {
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 drm_modeset_lock(&crtc->mutex, NULL);
3174 * FIXME: Once we have proper support for primary planes (and
3175 * disabling them without disabling the entire crtc) allow again
3176 * a NULL crtc->primary->fb.
3178 if (intel_crtc->active && crtc->primary->fb)
3179 dev_priv->display.update_primary_plane(crtc,
3183 drm_modeset_unlock(&crtc->mutex);
3187 void intel_prepare_reset(struct drm_device *dev)
3189 /* no reset support for gen2 */
3193 /* reset doesn't touch the display */
3194 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3197 drm_modeset_lock_all(dev);
3199 * Disabling the crtcs gracefully seems nicer. Also the
3200 * g33 docs say we should at least disable all the planes.
3202 intel_display_suspend(dev);
3205 void intel_finish_reset(struct drm_device *dev)
3207 struct drm_i915_private *dev_priv = to_i915(dev);
3210 * Flips in the rings will be nuked by the reset,
3211 * so complete all pending flips so that user space
3212 * will get its events and not get stuck.
3214 intel_complete_page_flips(dev);
3216 /* no reset support for gen2 */
3220 /* reset doesn't touch the display */
3221 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3223 * Flips in the rings have been nuked by the reset,
3224 * so update the base address of all primary
3225 * planes to the the last fb to make sure we're
3226 * showing the correct fb after a reset.
3228 intel_update_primary_planes(dev);
3233 * The display has been reset as well,
3234 * so need a full re-initialization.
3236 intel_runtime_pm_disable_interrupts(dev_priv);
3237 intel_runtime_pm_enable_interrupts(dev_priv);
3239 intel_modeset_init_hw(dev);
3241 spin_lock_irq(&dev_priv->irq_lock);
3242 if (dev_priv->display.hpd_irq_setup)
3243 dev_priv->display.hpd_irq_setup(dev);
3244 spin_unlock_irq(&dev_priv->irq_lock);
3246 intel_display_resume(dev);
3248 intel_hpd_init(dev_priv);
3250 drm_modeset_unlock_all(dev);
3254 intel_finish_fb(struct drm_framebuffer *old_fb)
3256 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3257 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3258 bool was_interruptible = dev_priv->mm.interruptible;
3261 /* Big Hammer, we also need to ensure that any pending
3262 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3263 * current scanout is retired before unpinning the old
3264 * framebuffer. Note that we rely on userspace rendering
3265 * into the buffer attached to the pipe they are waiting
3266 * on. If not, userspace generates a GPU hang with IPEHR
3267 * point to the MI_WAIT_FOR_EVENT.
3269 * This should only fail upon a hung GPU, in which case we
3270 * can safely continue.
3272 dev_priv->mm.interruptible = false;
3273 ret = i915_gem_object_wait_rendering(obj, true);
3274 dev_priv->mm.interruptible = was_interruptible;
3279 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3286 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3287 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3290 spin_lock_irq(&dev->event_lock);
3291 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3292 spin_unlock_irq(&dev->event_lock);
3297 static void intel_update_pipe_size(struct intel_crtc *crtc)
3299 struct drm_device *dev = crtc->base.dev;
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301 const struct drm_display_mode *adjusted_mode;
3307 * Update pipe size and adjust fitter if needed: the reason for this is
3308 * that in compute_mode_changes we check the native mode (not the pfit
3309 * mode) to see if we can flip rather than do a full mode set. In the
3310 * fastboot case, we'll flip, but if we don't update the pipesrc and
3311 * pfit state, we'll end up with a big fb scanned out into the wrong
3314 * To fix this properly, we need to hoist the checks up into
3315 * compute_mode_changes (or above), check the actual pfit state and
3316 * whether the platform allows pfit disable with pipe active, and only
3317 * then update the pipesrc and pfit state, even on the flip path.
3320 adjusted_mode = &crtc->config->base.adjusted_mode;
3322 I915_WRITE(PIPESRC(crtc->pipe),
3323 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3324 (adjusted_mode->crtc_vdisplay - 1));
3325 if (!crtc->config->pch_pfit.enabled &&
3326 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3327 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3328 I915_WRITE(PF_CTL(crtc->pipe), 0);
3329 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3330 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3332 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3333 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3336 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 int pipe = intel_crtc->pipe;
3344 /* enable normal train */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
3347 if (IS_IVYBRIDGE(dev)) {
3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3354 I915_WRITE(reg, temp);
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE;
3365 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3367 /* wait one idle pattern time */
3371 /* IVB wants error correction enabled */
3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374 FDI_FE_ERRC_ENABLE);
3377 /* The FDI link training functions for ILK/Ibexpeak. */
3378 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
3384 u32 reg, temp, tries;
3386 /* FDI needs bits from pipe first */
3387 assert_pipe_enabled(dev_priv, pipe);
3389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3391 reg = FDI_RX_IMR(pipe);
3392 temp = I915_READ(reg);
3393 temp &= ~FDI_RX_SYMBOL_LOCK;
3394 temp &= ~FDI_RX_BIT_LOCK;
3395 I915_WRITE(reg, temp);
3399 /* enable CPU FDI TX and PCH FDI RX */
3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3403 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3417 /* Ironlake workaround, enable clock pointer after FDI enable*/
3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420 FDI_RX_PHASE_SYNC_POINTER_EN);
3422 reg = FDI_RX_IIR(pipe);
3423 for (tries = 0; tries < 5; tries++) {
3424 temp = I915_READ(reg);
3425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427 if ((temp & FDI_RX_BIT_LOCK)) {
3428 DRM_DEBUG_KMS("FDI train 1 done.\n");
3429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434 DRM_ERROR("FDI train 1 fail!\n");
3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
3441 I915_WRITE(reg, temp);
3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
3447 I915_WRITE(reg, temp);
3452 reg = FDI_RX_IIR(pipe);
3453 for (tries = 0; tries < 5; tries++) {
3454 temp = I915_READ(reg);
3455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3457 if (temp & FDI_RX_SYMBOL_LOCK) {
3458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3459 DRM_DEBUG_KMS("FDI train 2 done.\n");
3464 DRM_ERROR("FDI train 2 fail!\n");
3466 DRM_DEBUG_KMS("FDI train done\n");
3470 static const int snb_b_fdi_train_param[] = {
3471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3477 /* The FDI link training functions for SNB/Cougarpoint. */
3478 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
3484 u32 reg, temp, i, retry;
3486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3488 reg = FDI_RX_IMR(pipe);
3489 temp = I915_READ(reg);
3490 temp &= ~FDI_RX_SYMBOL_LOCK;
3491 temp &= ~FDI_RX_BIT_LOCK;
3492 I915_WRITE(reg, temp);
3497 /* enable CPU FDI TX and PCH FDI RX */
3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
3500 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3501 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_1;
3504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3509 I915_WRITE(FDI_RX_MISC(pipe),
3510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3526 for (i = 0; i < 4; i++) {
3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530 temp |= snb_b_fdi_train_param[i];
3531 I915_WRITE(reg, temp);
3536 for (retry = 0; retry < 5; retry++) {
3537 reg = FDI_RX_IIR(pipe);
3538 temp = I915_READ(reg);
3539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540 if (temp & FDI_RX_BIT_LOCK) {
3541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542 DRM_DEBUG_KMS("FDI train 1 done.\n");
3551 DRM_ERROR("FDI train 1 fail!\n");
3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
3556 temp &= ~FDI_LINK_TRAIN_NONE;
3557 temp |= FDI_LINK_TRAIN_PATTERN_2;
3559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3563 I915_WRITE(reg, temp);
3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 I915_WRITE(reg, temp);
3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
3584 I915_WRITE(reg, temp);
3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_SYMBOL_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595 DRM_DEBUG_KMS("FDI train 2 done.\n");
3604 DRM_ERROR("FDI train 2 fail!\n");
3606 DRM_DEBUG_KMS("FDI train done.\n");
3609 /* Manual link training for Ivy Bridge A0 parts */
3610 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
3616 u32 reg, temp, i, j;
3618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3620 reg = FDI_RX_IMR(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_RX_SYMBOL_LOCK;
3623 temp &= ~FDI_RX_BIT_LOCK;
3624 I915_WRITE(reg, temp);
3629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630 I915_READ(FDI_RX_IIR(pipe)));
3632 /* Try each vswing and preemphasis setting twice before moving on */
3633 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634 /* disable first in case we need to retry */
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638 temp &= ~FDI_TX_ENABLE;
3639 I915_WRITE(reg, temp);
3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_AUTO;
3644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645 temp &= ~FDI_RX_ENABLE;
3646 I915_WRITE(reg, temp);
3648 /* enable CPU FDI TX and PCH FDI RX */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3653 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3655 temp |= snb_b_fdi_train_param[j/2];
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3659 I915_WRITE(FDI_RX_MISC(pipe),
3660 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3662 reg = FDI_RX_CTL(pipe);
3663 temp = I915_READ(reg);
3664 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3669 udelay(1); /* should be 0.5us */
3671 for (i = 0; i < 4; i++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3676 if (temp & FDI_RX_BIT_LOCK ||
3677 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3683 udelay(1); /* should be 0.5us */
3686 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695 I915_WRITE(reg, temp);
3697 reg = FDI_RX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3701 I915_WRITE(reg, temp);
3704 udelay(2); /* should be 1.5us */
3706 for (i = 0; i < 4; i++) {
3707 reg = FDI_RX_IIR(pipe);
3708 temp = I915_READ(reg);
3709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3711 if (temp & FDI_RX_SYMBOL_LOCK ||
3712 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3718 udelay(2); /* should be 1.5us */
3721 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3725 DRM_DEBUG_KMS("FDI train done.\n");
3728 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3730 struct drm_device *dev = intel_crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = intel_crtc->pipe;
3736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3740 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3741 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3747 /* Switch from Rawclk to PCDclk */
3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp | FDI_PCDCLK);
3754 /* Enable CPU FDI TX PLL, always on for Ironlake */
3755 reg = FDI_TX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3765 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3767 struct drm_device *dev = intel_crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 int pipe = intel_crtc->pipe;
3772 /* Switch from PCDclk to Rawclk */
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3777 /* Disable CPU FDI TX PLL */
3778 reg = FDI_TX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3789 /* Wait for the clocks to turn off. */
3794 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3802 /* disable CPU FDI tx and PCH FDI rx */
3803 reg = FDI_TX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~(0x7 << 16);
3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3812 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3817 /* Ironlake workaround, disable clock pointer after downing FDI */
3818 if (HAS_PCH_IBX(dev))
3819 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3821 /* still set train pattern 1 */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~FDI_LINK_TRAIN_NONE;
3825 temp |= FDI_LINK_TRAIN_PATTERN_1;
3826 I915_WRITE(reg, temp);
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 if (HAS_PCH_CPT(dev)) {
3831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3837 /* BPC in FDI rx is consistent with that in PIPECONF */
3838 temp &= ~(0x07 << 16);
3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840 I915_WRITE(reg, temp);
3846 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3848 struct intel_crtc *crtc;
3850 /* Note that we don't need to be called with mode_config.lock here
3851 * as our list of CRTC objects is static for the lifetime of the
3852 * device and so cannot disappear as we iterate. Similarly, we can
3853 * happily treat the predicates as racy, atomic checks as userspace
3854 * cannot claim and pin a new fb without at least acquring the
3855 * struct_mutex and so serialising with us.
3857 for_each_intel_crtc(dev, crtc) {
3858 if (atomic_read(&crtc->unpin_work_count) == 0)
3861 if (crtc->unpin_work)
3862 intel_wait_for_vblank(dev, crtc->pipe);
3870 static void page_flip_completed(struct intel_crtc *intel_crtc)
3872 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873 struct intel_unpin_work *work = intel_crtc->unpin_work;
3875 /* ensure that the unpin work is consistent wrt ->pending. */
3877 intel_crtc->unpin_work = NULL;
3880 drm_send_vblank_event(intel_crtc->base.dev,
3884 drm_crtc_vblank_put(&intel_crtc->base);
3886 wake_up_all(&dev_priv->pending_flip_queue);
3887 queue_work(dev_priv->wq, &work->work);
3889 trace_i915_flip_complete(intel_crtc->plane,
3890 work->pending_flip_obj);
3893 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3895 struct drm_device *dev = crtc->dev;
3896 struct drm_i915_private *dev_priv = dev->dev_private;
3898 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3899 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3900 !intel_crtc_has_pending_flip(crtc),
3902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3904 spin_lock_irq(&dev->event_lock);
3905 if (intel_crtc->unpin_work) {
3906 WARN_ONCE(1, "Removing stuck page flip\n");
3907 page_flip_completed(intel_crtc);
3909 spin_unlock_irq(&dev->event_lock);
3912 if (crtc->primary->fb) {
3913 mutex_lock(&dev->struct_mutex);
3914 intel_finish_fb(crtc->primary->fb);
3915 mutex_unlock(&dev->struct_mutex);
3919 /* Program iCLKIP clock to the desired frequency */
3920 static void lpt_program_iclkip(struct drm_crtc *crtc)
3922 struct drm_device *dev = crtc->dev;
3923 struct drm_i915_private *dev_priv = dev->dev_private;
3924 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3925 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3928 mutex_lock(&dev_priv->sb_lock);
3930 /* It is necessary to ungate the pixclk gate prior to programming
3931 * the divisors, and gate it back when it is done.
3933 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3935 /* Disable SSCCTL */
3936 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3937 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3941 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3942 if (clock == 20000) {
3947 /* The iCLK virtual clock root frequency is in MHz,
3948 * but the adjusted_mode->crtc_clock in in KHz. To get the
3949 * divisors, it is necessary to divide one by another, so we
3950 * convert the virtual clock precision to KHz here for higher
3953 u32 iclk_virtual_root_freq = 172800 * 1000;
3954 u32 iclk_pi_range = 64;
3955 u32 desired_divisor, msb_divisor_value, pi_value;
3957 desired_divisor = (iclk_virtual_root_freq / clock);
3958 msb_divisor_value = desired_divisor / iclk_pi_range;
3959 pi_value = desired_divisor % iclk_pi_range;
3962 divsel = msb_divisor_value - 2;
3963 phaseinc = pi_value;
3966 /* This should not happen with any sane values */
3967 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3968 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3969 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3970 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3972 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3979 /* Program SSCDIVINTPHASE6 */
3980 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3981 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3982 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3983 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3984 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3985 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3986 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3987 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3989 /* Program SSCAUXDIV */
3990 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3991 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3992 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3993 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3995 /* Enable modulator and associated divider */
3996 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3997 temp &= ~SBI_SSCCTL_DISABLE;
3998 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4000 /* Wait for initialization time */
4003 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4005 mutex_unlock(&dev_priv->sb_lock);
4008 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4009 enum pipe pch_transcoder)
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4015 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4016 I915_READ(HTOTAL(cpu_transcoder)));
4017 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4018 I915_READ(HBLANK(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4020 I915_READ(HSYNC(cpu_transcoder)));
4022 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4023 I915_READ(VTOTAL(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4025 I915_READ(VBLANK(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4027 I915_READ(VSYNC(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4029 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4032 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4037 temp = I915_READ(SOUTH_CHICKEN1);
4038 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4041 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4042 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4044 temp &= ~FDI_BC_BIFURCATION_SELECT;
4046 temp |= FDI_BC_BIFURCATION_SELECT;
4048 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4049 I915_WRITE(SOUTH_CHICKEN1, temp);
4050 POSTING_READ(SOUTH_CHICKEN1);
4053 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4055 struct drm_device *dev = intel_crtc->base.dev;
4057 switch (intel_crtc->pipe) {
4061 if (intel_crtc->config->fdi_lanes > 2)
4062 cpt_set_fdi_bc_bifurcation(dev, false);
4064 cpt_set_fdi_bc_bifurcation(dev, true);
4068 cpt_set_fdi_bc_bifurcation(dev, true);
4077 * Enable PCH resources required for PCH ports:
4079 * - FDI training & RX/TX
4080 * - update transcoder timings
4081 * - DP transcoding bits
4084 static void ironlake_pch_enable(struct drm_crtc *crtc)
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4092 assert_pch_transcoder_disabled(dev_priv, pipe);
4094 if (IS_IVYBRIDGE(dev))
4095 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4097 /* Write the TU size bits before fdi link training, so that error
4098 * detection works. */
4099 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4102 /* For PCH output, training FDI link */
4103 dev_priv->display.fdi_link_train(crtc);
4105 /* We need to program the right clock selection before writing the pixel
4106 * mutliplier into the DPLL. */
4107 if (HAS_PCH_CPT(dev)) {
4110 temp = I915_READ(PCH_DPLL_SEL);
4111 temp |= TRANS_DPLL_ENABLE(pipe);
4112 sel = TRANS_DPLLB_SEL(pipe);
4113 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4117 I915_WRITE(PCH_DPLL_SEL, temp);
4120 /* XXX: pch pll's can be enabled any time before we enable the PCH
4121 * transcoder, and we actually should do this to not upset any PCH
4122 * transcoder that already use the clock when we share it.
4124 * Note that enable_shared_dpll tries to do the right thing, but
4125 * get_shared_dpll unconditionally resets the pll - we need that to have
4126 * the right LVDS enable sequence. */
4127 intel_enable_shared_dpll(intel_crtc);
4129 /* set transcoder timing, panel must allow it */
4130 assert_panel_unlocked(dev_priv, pipe);
4131 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4133 intel_fdi_normal_train(crtc);
4135 /* For PCH DP, enable TRANS_DP_CTL */
4136 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4138 reg = TRANS_DP_CTL(pipe);
4139 temp = I915_READ(reg);
4140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4141 TRANS_DP_SYNC_MASK |
4143 temp |= TRANS_DP_OUTPUT_ENABLE;
4144 temp |= bpc << 9; /* same format but at 11:9 */
4146 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4148 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4151 switch (intel_trans_dp_port_sel(crtc)) {
4153 temp |= TRANS_DP_PORT_SEL_B;
4156 temp |= TRANS_DP_PORT_SEL_C;
4159 temp |= TRANS_DP_PORT_SEL_D;
4165 I915_WRITE(reg, temp);
4168 ironlake_enable_pch_transcoder(dev_priv, pipe);
4171 static void lpt_pch_enable(struct drm_crtc *crtc)
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4178 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4180 lpt_program_iclkip(crtc);
4182 /* Set transcoder timing. */
4183 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4185 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4188 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4189 struct intel_crtc_state *crtc_state)
4191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4192 struct intel_shared_dpll *pll;
4193 struct intel_shared_dpll_config *shared_dpll;
4194 enum intel_dpll_id i;
4196 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4198 if (HAS_PCH_IBX(dev_priv->dev)) {
4199 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4200 i = (enum intel_dpll_id) crtc->pipe;
4201 pll = &dev_priv->shared_dplls[i];
4203 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4204 crtc->base.base.id, pll->name);
4206 WARN_ON(shared_dpll[i].crtc_mask);
4211 if (IS_BROXTON(dev_priv->dev)) {
4212 /* PLL is attached to port in bxt */
4213 struct intel_encoder *encoder;
4214 struct intel_digital_port *intel_dig_port;
4216 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4217 if (WARN_ON(!encoder))
4220 intel_dig_port = enc_to_dig_port(&encoder->base);
4221 /* 1:1 mapping between ports and PLLs */
4222 i = (enum intel_dpll_id)intel_dig_port->port;
4223 pll = &dev_priv->shared_dplls[i];
4224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4225 crtc->base.base.id, pll->name);
4226 WARN_ON(shared_dpll[i].crtc_mask);
4231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4232 pll = &dev_priv->shared_dplls[i];
4234 /* Only want to check enabled timings first */
4235 if (shared_dpll[i].crtc_mask == 0)
4238 if (memcmp(&crtc_state->dpll_hw_state,
4239 &shared_dpll[i].hw_state,
4240 sizeof(crtc_state->dpll_hw_state)) == 0) {
4241 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4242 crtc->base.base.id, pll->name,
4243 shared_dpll[i].crtc_mask,
4249 /* Ok no matching timings, maybe there's a free one? */
4250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4251 pll = &dev_priv->shared_dplls[i];
4252 if (shared_dpll[i].crtc_mask == 0) {
4253 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4254 crtc->base.base.id, pll->name);
4262 if (shared_dpll[i].crtc_mask == 0)
4263 shared_dpll[i].hw_state =
4264 crtc_state->dpll_hw_state;
4266 crtc_state->shared_dpll = i;
4267 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4268 pipe_name(crtc->pipe));
4270 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4275 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4277 struct drm_i915_private *dev_priv = to_i915(state->dev);
4278 struct intel_shared_dpll_config *shared_dpll;
4279 struct intel_shared_dpll *pll;
4280 enum intel_dpll_id i;
4282 if (!to_intel_atomic_state(state)->dpll_set)
4285 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4287 pll = &dev_priv->shared_dplls[i];
4288 pll->config = shared_dpll[i];
4292 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int dslreg = PIPEDSL(pipe);
4298 temp = I915_READ(dslreg);
4300 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4301 if (wait_for(I915_READ(dslreg) != temp, 5))
4302 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4307 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4308 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4309 int src_w, int src_h, int dst_w, int dst_h)
4311 struct intel_crtc_scaler_state *scaler_state =
4312 &crtc_state->scaler_state;
4313 struct intel_crtc *intel_crtc =
4314 to_intel_crtc(crtc_state->base.crtc);
4317 need_scaling = intel_rotation_90_or_270(rotation) ?
4318 (src_h != dst_w || src_w != dst_h):
4319 (src_w != dst_w || src_h != dst_h);
4322 * if plane is being disabled or scaler is no more required or force detach
4323 * - free scaler binded to this plane/crtc
4324 * - in order to do this, update crtc->scaler_usage
4326 * Here scaler state in crtc_state is set free so that
4327 * scaler can be assigned to other user. Actual register
4328 * update to free the scaler is done in plane/panel-fit programming.
4329 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4331 if (force_detach || !need_scaling) {
4332 if (*scaler_id >= 0) {
4333 scaler_state->scaler_users &= ~(1 << scaler_user);
4334 scaler_state->scalers[*scaler_id].in_use = 0;
4336 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4337 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4338 intel_crtc->pipe, scaler_user, *scaler_id,
4339 scaler_state->scaler_users);
4346 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4347 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4349 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4350 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4351 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4352 "size is out of scaler range\n",
4353 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4357 /* mark this plane as a scaler user in crtc_state */
4358 scaler_state->scaler_users |= (1 << scaler_user);
4359 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4360 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4361 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4362 scaler_state->scaler_users);
4368 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4370 * @state: crtc's scaler state
4373 * 0 - scaler_usage updated successfully
4374 * error - requested scaling cannot be supported or other error condition
4376 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4378 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4379 struct drm_display_mode *adjusted_mode =
4380 &state->base.adjusted_mode;
4382 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4383 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4385 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4386 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4387 state->pipe_src_w, state->pipe_src_h,
4388 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
4392 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4394 * @state: crtc's scaler state
4395 * @plane_state: atomic plane state to update
4398 * 0 - scaler_usage updated successfully
4399 * error - requested scaling cannot be supported or other error condition
4401 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4402 struct intel_plane_state *plane_state)
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4406 struct intel_plane *intel_plane =
4407 to_intel_plane(plane_state->base.plane);
4408 struct drm_framebuffer *fb = plane_state->base.fb;
4411 bool force_detach = !fb || !plane_state->visible;
4413 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4414 intel_plane->base.base.id, intel_crtc->pipe,
4415 drm_plane_index(&intel_plane->base));
4417 ret = skl_update_scaler(crtc_state, force_detach,
4418 drm_plane_index(&intel_plane->base),
4419 &plane_state->scaler_id,
4420 plane_state->base.rotation,
4421 drm_rect_width(&plane_state->src) >> 16,
4422 drm_rect_height(&plane_state->src) >> 16,
4423 drm_rect_width(&plane_state->dst),
4424 drm_rect_height(&plane_state->dst));
4426 if (ret || plane_state->scaler_id < 0)
4429 /* check colorkey */
4430 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4431 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4432 intel_plane->base.base.id);
4436 /* Check src format */
4437 switch (fb->pixel_format) {
4438 case DRM_FORMAT_RGB565:
4439 case DRM_FORMAT_XBGR8888:
4440 case DRM_FORMAT_XRGB8888:
4441 case DRM_FORMAT_ABGR8888:
4442 case DRM_FORMAT_ARGB8888:
4443 case DRM_FORMAT_XRGB2101010:
4444 case DRM_FORMAT_XBGR2101010:
4445 case DRM_FORMAT_YUYV:
4446 case DRM_FORMAT_YVYU:
4447 case DRM_FORMAT_UYVY:
4448 case DRM_FORMAT_VYUY:
4451 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4452 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4459 static void skylake_scaler_disable(struct intel_crtc *crtc)
4463 for (i = 0; i < crtc->num_scalers; i++)
4464 skl_detach_scaler(crtc, i);
4467 static void skylake_pfit_enable(struct intel_crtc *crtc)
4469 struct drm_device *dev = crtc->base.dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 int pipe = crtc->pipe;
4472 struct intel_crtc_scaler_state *scaler_state =
4473 &crtc->config->scaler_state;
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4477 if (crtc->config->pch_pfit.enabled) {
4480 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4481 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4485 id = scaler_state->scaler_id;
4486 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4487 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4488 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4489 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4491 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4495 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4497 struct drm_device *dev = crtc->base.dev;
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499 int pipe = crtc->pipe;
4501 if (crtc->config->pch_pfit.enabled) {
4502 /* Force use of hard-coded filter coefficients
4503 * as some pre-programmed values are broken,
4506 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4507 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4508 PF_PIPE_SEL_IVB(pipe));
4510 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4511 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4512 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4516 void hsw_enable_ips(struct intel_crtc *crtc)
4518 struct drm_device *dev = crtc->base.dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4521 if (!crtc->config->ips_enabled)
4524 /* We can only enable IPS after we enable a plane and wait for a vblank */
4525 intel_wait_for_vblank(dev, crtc->pipe);
4527 assert_plane_enabled(dev_priv, crtc->plane);
4528 if (IS_BROADWELL(dev)) {
4529 mutex_lock(&dev_priv->rps.hw_lock);
4530 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4531 mutex_unlock(&dev_priv->rps.hw_lock);
4532 /* Quoting Art Runyan: "its not safe to expect any particular
4533 * value in IPS_CTL bit 31 after enabling IPS through the
4534 * mailbox." Moreover, the mailbox may return a bogus state,
4535 * so we need to just enable it and continue on.
4538 I915_WRITE(IPS_CTL, IPS_ENABLE);
4539 /* The bit only becomes 1 in the next vblank, so this wait here
4540 * is essentially intel_wait_for_vblank. If we don't have this
4541 * and don't wait for vblanks until the end of crtc_enable, then
4542 * the HW state readout code will complain that the expected
4543 * IPS_CTL value is not the one we read. */
4544 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4545 DRM_ERROR("Timed out waiting for IPS enable\n");
4549 void hsw_disable_ips(struct intel_crtc *crtc)
4551 struct drm_device *dev = crtc->base.dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4554 if (!crtc->config->ips_enabled)
4557 assert_plane_enabled(dev_priv, crtc->plane);
4558 if (IS_BROADWELL(dev)) {
4559 mutex_lock(&dev_priv->rps.hw_lock);
4560 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4561 mutex_unlock(&dev_priv->rps.hw_lock);
4562 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4563 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4564 DRM_ERROR("Timed out waiting for IPS disable\n");
4566 I915_WRITE(IPS_CTL, 0);
4567 POSTING_READ(IPS_CTL);
4570 /* We need to wait for a vblank before we can disable the plane. */
4571 intel_wait_for_vblank(dev, crtc->pipe);
4574 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4575 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4577 struct drm_device *dev = crtc->dev;
4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580 enum pipe pipe = intel_crtc->pipe;
4581 int palreg = PALETTE(pipe);
4583 bool reenable_ips = false;
4585 /* The clocks have to be on to load the palette. */
4586 if (!crtc->state->active)
4589 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4590 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4591 assert_dsi_pll_enabled(dev_priv);
4593 assert_pll_enabled(dev_priv, pipe);
4596 /* use legacy palette for Ironlake */
4597 if (!HAS_GMCH_DISPLAY(dev))
4598 palreg = LGC_PALETTE(pipe);
4600 /* Workaround : Do not read or write the pipe palette/gamma data while
4601 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4603 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4604 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4605 GAMMA_MODE_MODE_SPLIT)) {
4606 hsw_disable_ips(intel_crtc);
4607 reenable_ips = true;
4610 for (i = 0; i < 256; i++) {
4611 I915_WRITE(palreg + 4 * i,
4612 (intel_crtc->lut_r[i] << 16) |
4613 (intel_crtc->lut_g[i] << 8) |
4614 intel_crtc->lut_b[i]);
4618 hsw_enable_ips(intel_crtc);
4621 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4623 if (intel_crtc->overlay) {
4624 struct drm_device *dev = intel_crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4627 mutex_lock(&dev->struct_mutex);
4628 dev_priv->mm.interruptible = false;
4629 (void) intel_overlay_switch_off(intel_crtc->overlay);
4630 dev_priv->mm.interruptible = true;
4631 mutex_unlock(&dev->struct_mutex);
4634 /* Let userspace switch the overlay on again. In most cases userspace
4635 * has to recompute where to put it anyway.
4640 * intel_post_enable_primary - Perform operations after enabling primary plane
4641 * @crtc: the CRTC whose primary plane was just enabled
4643 * Performs potentially sleeping operations that must be done after the primary
4644 * plane is enabled, such as updating FBC and IPS. Note that this may be
4645 * called due to an explicit primary plane update, or due to an implicit
4646 * re-enable that is caused when a sprite plane is updated to no longer
4647 * completely hide the primary plane.
4650 intel_post_enable_primary(struct drm_crtc *crtc)
4652 struct drm_device *dev = crtc->dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4655 int pipe = intel_crtc->pipe;
4658 * BDW signals flip done immediately if the plane
4659 * is disabled, even if the plane enable is already
4660 * armed to occur at the next vblank :(
4662 if (IS_BROADWELL(dev))
4663 intel_wait_for_vblank(dev, pipe);
4666 * FIXME IPS should be fine as long as one plane is
4667 * enabled, but in practice it seems to have problems
4668 * when going from primary only to sprite only and vice
4671 hsw_enable_ips(intel_crtc);
4674 * Gen2 reports pipe underruns whenever all planes are disabled.
4675 * So don't enable underrun reporting before at least some planes
4677 * FIXME: Need to fix the logic to work when we turn off all planes
4678 * but leave the pipe running.
4681 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4683 /* Underruns don't raise interrupts, so check manually. */
4684 if (HAS_GMCH_DISPLAY(dev))
4685 i9xx_check_fifo_underruns(dev_priv);
4689 * intel_pre_disable_primary - Perform operations before disabling primary plane
4690 * @crtc: the CRTC whose primary plane is to be disabled
4692 * Performs potentially sleeping operations that must be done before the
4693 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4694 * be called due to an explicit primary plane update, or due to an implicit
4695 * disable that is caused when a sprite plane completely hides the primary
4699 intel_pre_disable_primary(struct drm_crtc *crtc)
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
4707 * Gen2 reports pipe underruns whenever all planes are disabled.
4708 * So diasble underrun reporting before all the planes get disabled.
4709 * FIXME: Need to fix the logic to work when we turn off all planes
4710 * but leave the pipe running.
4713 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4716 * Vblank time updates from the shadow to live plane control register
4717 * are blocked if the memory self-refresh mode is active at that
4718 * moment. So to make sure the plane gets truly disabled, disable
4719 * first the self-refresh mode. The self-refresh enable bit in turn
4720 * will be checked/applied by the HW only at the next frame start
4721 * event which is after the vblank start event, so we need to have a
4722 * wait-for-vblank between disabling the plane and the pipe.
4724 if (HAS_GMCH_DISPLAY(dev)) {
4725 intel_set_memory_cxsr(dev_priv, false);
4726 dev_priv->wm.vlv.cxsr = false;
4727 intel_wait_for_vblank(dev, pipe);
4731 * FIXME IPS should be fine as long as one plane is
4732 * enabled, but in practice it seems to have problems
4733 * when going from primary only to sprite only and vice
4736 hsw_disable_ips(intel_crtc);
4739 static void intel_post_plane_update(struct intel_crtc *crtc)
4741 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742 struct drm_device *dev = crtc->base.dev;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 struct drm_plane *plane;
4746 if (atomic->wait_vblank)
4747 intel_wait_for_vblank(dev, crtc->pipe);
4749 intel_frontbuffer_flip(dev, atomic->fb_bits);
4751 if (atomic->disable_cxsr)
4752 crtc->wm.cxsr_allowed = true;
4754 if (crtc->atomic.update_wm_post)
4755 intel_update_watermarks(&crtc->base);
4757 if (atomic->update_fbc)
4758 intel_fbc_update(dev_priv);
4760 if (atomic->post_enable_primary)
4761 intel_post_enable_primary(&crtc->base);
4763 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4764 intel_update_sprite_watermarks(plane, &crtc->base,
4765 0, 0, 0, false, false);
4767 memset(atomic, 0, sizeof(*atomic));
4770 static void intel_pre_plane_update(struct intel_crtc *crtc)
4772 struct drm_device *dev = crtc->base.dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775 struct drm_plane *p;
4777 /* Track fb's for any planes being disabled */
4778 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4779 struct intel_plane *plane = to_intel_plane(p);
4781 mutex_lock(&dev->struct_mutex);
4782 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4783 plane->frontbuffer_bit);
4784 mutex_unlock(&dev->struct_mutex);
4787 if (atomic->wait_for_flips)
4788 intel_crtc_wait_for_pending_flips(&crtc->base);
4790 if (atomic->disable_fbc)
4791 intel_fbc_disable_crtc(crtc);
4793 if (crtc->atomic.disable_ips)
4794 hsw_disable_ips(crtc);
4796 if (atomic->pre_disable_primary)
4797 intel_pre_disable_primary(&crtc->base);
4799 if (atomic->disable_cxsr) {
4800 crtc->wm.cxsr_allowed = false;
4801 intel_set_memory_cxsr(dev_priv, false);
4805 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4807 struct drm_device *dev = crtc->dev;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 struct drm_plane *p;
4810 int pipe = intel_crtc->pipe;
4812 intel_crtc_dpms_overlay_disable(intel_crtc);
4814 drm_for_each_plane_mask(p, dev, plane_mask)
4815 to_intel_plane(p)->disable_plane(p, crtc);
4818 * FIXME: Once we grow proper nuclear flip support out of this we need
4819 * to compute the mask of flip planes precisely. For the time being
4820 * consider this a flip to a NULL plane.
4822 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4825 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830 struct intel_encoder *encoder;
4831 int pipe = intel_crtc->pipe;
4833 if (WARN_ON(intel_crtc->active))
4836 if (intel_crtc->config->has_pch_encoder)
4837 intel_prepare_shared_dpll(intel_crtc);
4839 if (intel_crtc->config->has_dp_encoder)
4840 intel_dp_set_m_n(intel_crtc, M1_N1);
4842 intel_set_pipe_timings(intel_crtc);
4844 if (intel_crtc->config->has_pch_encoder) {
4845 intel_cpu_transcoder_set_m_n(intel_crtc,
4846 &intel_crtc->config->fdi_m_n, NULL);
4849 ironlake_set_pipeconf(crtc);
4851 intel_crtc->active = true;
4853 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4854 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4856 for_each_encoder_on_crtc(dev, crtc, encoder)
4857 if (encoder->pre_enable)
4858 encoder->pre_enable(encoder);
4860 if (intel_crtc->config->has_pch_encoder) {
4861 /* Note: FDI PLL enabling _must_ be done before we enable the
4862 * cpu pipes, hence this is separate from all the other fdi/pch
4864 ironlake_fdi_pll_enable(intel_crtc);
4866 assert_fdi_tx_disabled(dev_priv, pipe);
4867 assert_fdi_rx_disabled(dev_priv, pipe);
4870 ironlake_pfit_enable(intel_crtc);
4873 * On ILK+ LUT must be loaded before the pipe is running but with
4876 intel_crtc_load_lut(crtc);
4878 intel_update_watermarks(crtc);
4879 intel_enable_pipe(intel_crtc);
4881 if (intel_crtc->config->has_pch_encoder)
4882 ironlake_pch_enable(crtc);
4884 assert_vblank_disabled(crtc);
4885 drm_crtc_vblank_on(crtc);
4887 for_each_encoder_on_crtc(dev, crtc, encoder)
4888 encoder->enable(encoder);
4890 if (HAS_PCH_CPT(dev))
4891 cpt_verify_modeset(dev, intel_crtc->pipe);
4894 /* IPS only exists on ULT machines and is tied to pipe A. */
4895 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4897 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4900 static void haswell_crtc_enable(struct drm_crtc *crtc)
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 struct intel_encoder *encoder;
4906 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4907 struct intel_crtc_state *pipe_config =
4908 to_intel_crtc_state(crtc->state);
4910 if (WARN_ON(intel_crtc->active))
4913 if (intel_crtc_to_shared_dpll(intel_crtc))
4914 intel_enable_shared_dpll(intel_crtc);
4916 if (intel_crtc->config->has_dp_encoder)
4917 intel_dp_set_m_n(intel_crtc, M1_N1);
4919 intel_set_pipe_timings(intel_crtc);
4921 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4922 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4923 intel_crtc->config->pixel_multiplier - 1);
4926 if (intel_crtc->config->has_pch_encoder) {
4927 intel_cpu_transcoder_set_m_n(intel_crtc,
4928 &intel_crtc->config->fdi_m_n, NULL);
4931 haswell_set_pipeconf(crtc);
4933 intel_set_pipe_csc(crtc);
4935 intel_crtc->active = true;
4937 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 if (encoder->pre_enable)
4940 encoder->pre_enable(encoder);
4942 if (intel_crtc->config->has_pch_encoder) {
4943 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4945 dev_priv->display.fdi_link_train(crtc);
4948 intel_ddi_enable_pipe_clock(intel_crtc);
4950 if (INTEL_INFO(dev)->gen == 9)
4951 skylake_pfit_enable(intel_crtc);
4952 else if (INTEL_INFO(dev)->gen < 9)
4953 ironlake_pfit_enable(intel_crtc);
4955 MISSING_CASE(INTEL_INFO(dev)->gen);
4958 * On ILK+ LUT must be loaded before the pipe is running but with
4961 intel_crtc_load_lut(crtc);
4963 intel_ddi_set_pipe_settings(crtc);
4964 intel_ddi_enable_transcoder_func(crtc);
4966 intel_update_watermarks(crtc);
4967 intel_enable_pipe(intel_crtc);
4969 if (intel_crtc->config->has_pch_encoder)
4970 lpt_pch_enable(crtc);
4972 if (intel_crtc->config->dp_encoder_is_mst)
4973 intel_ddi_set_vc_payload_alloc(crtc, true);
4975 assert_vblank_disabled(crtc);
4976 drm_crtc_vblank_on(crtc);
4978 for_each_encoder_on_crtc(dev, crtc, encoder) {
4979 encoder->enable(encoder);
4980 intel_opregion_notify_encoder(encoder, true);
4983 /* If we change the relative order between pipe/planes enabling, we need
4984 * to change the workaround. */
4985 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4986 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4987 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4992 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 int pipe = crtc->pipe;
4998 /* To avoid upsetting the power well on haswell only disable the pfit if
4999 * it's in use. The hw state code will make sure we get this right. */
5000 if (crtc->config->pch_pfit.enabled) {
5001 I915_WRITE(PF_CTL(pipe), 0);
5002 I915_WRITE(PF_WIN_POS(pipe), 0);
5003 I915_WRITE(PF_WIN_SZ(pipe), 0);
5007 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5009 struct drm_device *dev = crtc->dev;
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012 struct intel_encoder *encoder;
5013 int pipe = intel_crtc->pipe;
5016 for_each_encoder_on_crtc(dev, crtc, encoder)
5017 encoder->disable(encoder);
5019 drm_crtc_vblank_off(crtc);
5020 assert_vblank_disabled(crtc);
5022 if (intel_crtc->config->has_pch_encoder)
5023 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5025 intel_disable_pipe(intel_crtc);
5027 ironlake_pfit_disable(intel_crtc);
5029 if (intel_crtc->config->has_pch_encoder)
5030 ironlake_fdi_disable(crtc);
5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 if (encoder->post_disable)
5034 encoder->post_disable(encoder);
5036 if (intel_crtc->config->has_pch_encoder) {
5037 ironlake_disable_pch_transcoder(dev_priv, pipe);
5039 if (HAS_PCH_CPT(dev)) {
5040 /* disable TRANS_DP_CTL */
5041 reg = TRANS_DP_CTL(pipe);
5042 temp = I915_READ(reg);
5043 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5044 TRANS_DP_PORT_SEL_MASK);
5045 temp |= TRANS_DP_PORT_SEL_NONE;
5046 I915_WRITE(reg, temp);
5048 /* disable DPLL_SEL */
5049 temp = I915_READ(PCH_DPLL_SEL);
5050 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5051 I915_WRITE(PCH_DPLL_SEL, temp);
5054 ironlake_fdi_pll_disable(intel_crtc);
5057 intel_crtc->active = false;
5058 intel_update_watermarks(crtc);
5061 static void haswell_crtc_disable(struct drm_crtc *crtc)
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 struct intel_encoder *encoder;
5067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5069 for_each_encoder_on_crtc(dev, crtc, encoder) {
5070 intel_opregion_notify_encoder(encoder, false);
5071 encoder->disable(encoder);
5074 drm_crtc_vblank_off(crtc);
5075 assert_vblank_disabled(crtc);
5077 if (intel_crtc->config->has_pch_encoder)
5078 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5080 intel_disable_pipe(intel_crtc);
5082 if (intel_crtc->config->dp_encoder_is_mst)
5083 intel_ddi_set_vc_payload_alloc(crtc, false);
5085 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5087 if (INTEL_INFO(dev)->gen == 9)
5088 skylake_scaler_disable(intel_crtc);
5089 else if (INTEL_INFO(dev)->gen < 9)
5090 ironlake_pfit_disable(intel_crtc);
5092 MISSING_CASE(INTEL_INFO(dev)->gen);
5094 intel_ddi_disable_pipe_clock(intel_crtc);
5096 if (intel_crtc->config->has_pch_encoder) {
5097 lpt_disable_pch_transcoder(dev_priv);
5098 intel_ddi_fdi_disable(crtc);
5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 if (encoder->post_disable)
5103 encoder->post_disable(encoder);
5105 intel_crtc->active = false;
5106 intel_update_watermarks(crtc);
5109 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5111 struct drm_device *dev = crtc->base.dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
5113 struct intel_crtc_state *pipe_config = crtc->config;
5115 if (!pipe_config->gmch_pfit.control)
5119 * The panel fitter should only be adjusted whilst the pipe is disabled,
5120 * according to register description and PRM.
5122 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5123 assert_pipe_disabled(dev_priv, crtc->pipe);
5125 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5126 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5128 /* Border color in case we don't scale up to the full screen. Black by
5129 * default, change to something else for debugging. */
5130 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5133 static enum intel_display_power_domain port_to_power_domain(enum port port)
5137 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5139 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5141 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5143 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146 return POWER_DOMAIN_PORT_OTHER;
5150 #define for_each_power_domain(domain, mask) \
5151 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5152 if ((1 << (domain)) & (mask))
5154 enum intel_display_power_domain
5155 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5157 struct drm_device *dev = intel_encoder->base.dev;
5158 struct intel_digital_port *intel_dig_port;
5160 switch (intel_encoder->type) {
5161 case INTEL_OUTPUT_UNKNOWN:
5162 /* Only DDI platforms should ever use this output type */
5163 WARN_ON_ONCE(!HAS_DDI(dev));
5164 case INTEL_OUTPUT_DISPLAYPORT:
5165 case INTEL_OUTPUT_HDMI:
5166 case INTEL_OUTPUT_EDP:
5167 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5168 return port_to_power_domain(intel_dig_port->port);
5169 case INTEL_OUTPUT_DP_MST:
5170 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5171 return port_to_power_domain(intel_dig_port->port);
5172 case INTEL_OUTPUT_ANALOG:
5173 return POWER_DOMAIN_PORT_CRT;
5174 case INTEL_OUTPUT_DSI:
5175 return POWER_DOMAIN_PORT_DSI;
5177 return POWER_DOMAIN_PORT_OTHER;
5181 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5183 struct drm_device *dev = crtc->dev;
5184 struct intel_encoder *intel_encoder;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 enum pipe pipe = intel_crtc->pipe;
5188 enum transcoder transcoder;
5190 if (!crtc->state->active)
5193 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5195 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5196 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5197 if (intel_crtc->config->pch_pfit.enabled ||
5198 intel_crtc->config->pch_pfit.force_thru)
5199 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5201 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5202 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5207 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5209 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211 enum intel_display_power_domain domain;
5212 unsigned long domains, new_domains, old_domains;
5214 old_domains = intel_crtc->enabled_power_domains;
5215 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5217 domains = new_domains & ~old_domains;
5219 for_each_power_domain(domain, domains)
5220 intel_display_power_get(dev_priv, domain);
5222 return old_domains & ~new_domains;
5225 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5226 unsigned long domains)
5228 enum intel_display_power_domain domain;
5230 for_each_power_domain(domain, domains)
5231 intel_display_power_put(dev_priv, domain);
5234 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5236 struct drm_device *dev = state->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 unsigned long put_domains[I915_MAX_PIPES] = {};
5239 struct drm_crtc_state *crtc_state;
5240 struct drm_crtc *crtc;
5243 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5244 if (needs_modeset(crtc->state))
5245 put_domains[to_intel_crtc(crtc)->pipe] =
5246 modeset_get_crtc_power_domains(crtc);
5249 if (dev_priv->display.modeset_commit_cdclk) {
5250 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5252 if (cdclk != dev_priv->cdclk_freq &&
5253 !WARN_ON(!state->allow_modeset))
5254 dev_priv->display.modeset_commit_cdclk(state);
5257 for (i = 0; i < I915_MAX_PIPES; i++)
5259 modeset_put_power_domains(dev_priv, put_domains[i]);
5262 static void intel_update_max_cdclk(struct drm_device *dev)
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5266 if (IS_SKYLAKE(dev)) {
5267 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5269 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5270 dev_priv->max_cdclk_freq = 675000;
5271 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5272 dev_priv->max_cdclk_freq = 540000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5274 dev_priv->max_cdclk_freq = 450000;
5276 dev_priv->max_cdclk_freq = 337500;
5277 } else if (IS_BROADWELL(dev)) {
5279 * FIXME with extra cooling we can allow
5280 * 540 MHz for ULX and 675 Mhz for ULT.
5281 * How can we know if extra cooling is
5282 * available? PCI ID, VTB, something else?
5284 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5285 dev_priv->max_cdclk_freq = 450000;
5286 else if (IS_BDW_ULX(dev))
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULT(dev))
5289 dev_priv->max_cdclk_freq = 540000;
5291 dev_priv->max_cdclk_freq = 675000;
5292 } else if (IS_CHERRYVIEW(dev)) {
5293 dev_priv->max_cdclk_freq = 320000;
5294 } else if (IS_VALLEYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 400000;
5297 /* otherwise assume cdclk is fixed */
5298 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5301 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302 dev_priv->max_cdclk_freq);
5305 static void intel_update_cdclk(struct drm_device *dev)
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5309 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311 dev_priv->cdclk_freq);
5314 * Program the gmbus_freq based on the cdclk frequency.
5315 * BSpec erroneously claims we should aim for 4MHz, but
5316 * in fact 1MHz is the correct frequency.
5318 if (IS_VALLEYVIEW(dev)) {
5320 * Program the gmbus_freq based on the cdclk frequency.
5321 * BSpec erroneously claims we should aim for 4MHz, but
5322 * in fact 1MHz is the correct frequency.
5324 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5327 if (dev_priv->max_cdclk_freq == 0)
5328 intel_update_max_cdclk(dev);
5331 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5336 uint32_t current_freq;
5339 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340 switch (frequency) {
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343 ratio = BXT_DE_PLL_RATIO(60);
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347 ratio = BXT_DE_PLL_RATIO(60);
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351 ratio = BXT_DE_PLL_RATIO(60);
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355 ratio = BXT_DE_PLL_RATIO(60);
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359 ratio = BXT_DE_PLL_RATIO(65);
5363 * Bypass frequency with DE PLL disabled. Init ratio, divider
5364 * to suppress GCC warning.
5370 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5375 mutex_lock(&dev_priv->rps.hw_lock);
5376 /* Inform power controller of upcoming frequency change */
5377 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5379 mutex_unlock(&dev_priv->rps.hw_lock);
5382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5387 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389 current_freq = current_freq * 500 + 1000;
5392 * DE PLL has to be disabled when
5393 * - setting to 19.2MHz (bypass, PLL isn't used)
5394 * - before setting to 624MHz (PLL needs toggling)
5395 * - before setting to any frequency from 624MHz (PLL needs toggling)
5397 if (frequency == 19200 || frequency == 624000 ||
5398 current_freq == 624000) {
5399 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5401 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5403 DRM_ERROR("timout waiting for DE PLL unlock\n");
5406 if (frequency != 19200) {
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5416 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417 DRM_ERROR("timeout waiting for DE PLL lock\n");
5419 val = I915_READ(CDCLK_CTL);
5420 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5423 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5426 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427 if (frequency >= 500000)
5428 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5430 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432 val |= (frequency - 1000) / 500;
5433 I915_WRITE(CDCLK_CTL, val);
5436 mutex_lock(&dev_priv->rps.hw_lock);
5437 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438 DIV_ROUND_UP(frequency, 25000));
5439 mutex_unlock(&dev_priv->rps.hw_lock);
5442 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5447 intel_update_cdclk(dev);
5450 void broxton_init_cdclk(struct drm_device *dev)
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5456 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457 * or else the reset will hang because there is no PCH to respond.
5458 * Move the handshake programming to initialization sequence.
5459 * Previously was left up to BIOS.
5461 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5465 /* Enable PG1 for cdclk */
5466 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5468 /* check if cd clock is enabled */
5469 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470 DRM_DEBUG_KMS("Display already initialized\n");
5476 * - The initial CDCLK needs to be read from VBT.
5477 * Need to make this change after VBT has changes for BXT.
5478 * - check if setting the max (or any) cdclk freq is really necessary
5479 * here, it belongs to modeset time
5481 broxton_set_cdclk(dev, 624000);
5483 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5484 POSTING_READ(DBUF_CTL);
5488 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489 DRM_ERROR("DBuf power enable timeout!\n");
5492 void broxton_uninit_cdclk(struct drm_device *dev)
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5496 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5497 POSTING_READ(DBUF_CTL);
5501 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502 DRM_ERROR("DBuf power disable timeout!\n");
5504 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505 broxton_set_cdclk(dev, 19200);
5507 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5510 static const struct skl_cdclk_entry {
5513 } skl_cdclk_frequencies[] = {
5514 { .freq = 308570, .vco = 8640 },
5515 { .freq = 337500, .vco = 8100 },
5516 { .freq = 432000, .vco = 8640 },
5517 { .freq = 450000, .vco = 8100 },
5518 { .freq = 540000, .vco = 8100 },
5519 { .freq = 617140, .vco = 8640 },
5520 { .freq = 675000, .vco = 8100 },
5523 static unsigned int skl_cdclk_decimal(unsigned int freq)
5525 return (freq - 1000) / 500;
5528 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5532 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5535 if (e->freq == freq)
5543 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5545 unsigned int min_freq;
5548 /* select the minimum CDCLK before enabling DPLL 0 */
5549 val = I915_READ(CDCLK_CTL);
5550 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551 val |= CDCLK_FREQ_337_308;
5553 if (required_vco == 8640)
5558 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5560 I915_WRITE(CDCLK_CTL, val);
5561 POSTING_READ(CDCLK_CTL);
5564 * We always enable DPLL0 with the lowest link rate possible, but still
5565 * taking into account the VCO required to operate the eDP panel at the
5566 * desired frequency. The usual DP link rates operate with a VCO of
5567 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568 * The modeset code is responsible for the selection of the exact link
5569 * rate later on, with the constraint of choosing a frequency that
5570 * works with required_vco.
5572 val = I915_READ(DPLL_CTRL1);
5574 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577 if (required_vco == 8640)
5578 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5581 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5584 I915_WRITE(DPLL_CTRL1, val);
5585 POSTING_READ(DPLL_CTRL1);
5587 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5589 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590 DRM_ERROR("DPLL0 not locked\n");
5593 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5598 /* inform PCU we want to change CDCLK */
5599 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600 mutex_lock(&dev_priv->rps.hw_lock);
5601 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5604 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5607 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5611 for (i = 0; i < 15; i++) {
5612 if (skl_cdclk_pcu_ready(dev_priv))
5620 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5622 struct drm_device *dev = dev_priv->dev;
5623 u32 freq_select, pcu_ack;
5625 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5627 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628 DRM_ERROR("failed to inform PCU about cdclk change\n");
5636 freq_select = CDCLK_FREQ_450_432;
5640 freq_select = CDCLK_FREQ_540;
5646 freq_select = CDCLK_FREQ_337_308;
5651 freq_select = CDCLK_FREQ_675_617;
5656 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657 POSTING_READ(CDCLK_CTL);
5659 /* inform PCU of the change */
5660 mutex_lock(&dev_priv->rps.hw_lock);
5661 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662 mutex_unlock(&dev_priv->rps.hw_lock);
5664 intel_update_cdclk(dev);
5667 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5669 /* disable DBUF power */
5670 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671 POSTING_READ(DBUF_CTL);
5675 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676 DRM_ERROR("DBuf power disable timeout\n");
5679 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681 DRM_ERROR("Couldn't disable DPLL0\n");
5683 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5686 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5689 unsigned int required_vco;
5691 /* enable PCH reset handshake */
5692 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5693 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5695 /* enable PG1 and Misc I/O */
5696 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5698 /* DPLL0 already enabed !? */
5699 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5700 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5705 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5706 skl_dpll0_enable(dev_priv, required_vco);
5708 /* set CDCLK to the frequency the BIOS chose */
5709 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5711 /* enable DBUF power */
5712 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5713 POSTING_READ(DBUF_CTL);
5717 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5718 DRM_ERROR("DBuf power enable timeout\n");
5721 /* returns HPLL frequency in kHz */
5722 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5724 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5726 /* Obtain SKU information */
5727 mutex_lock(&dev_priv->sb_lock);
5728 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5729 CCK_FUSE_HPLL_FREQ_MASK;
5730 mutex_unlock(&dev_priv->sb_lock);
5732 return vco_freq[hpll_freq] * 1000;
5735 /* Adjust CDclk dividers to allow high res or save power if possible */
5736 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5741 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5742 != dev_priv->cdclk_freq);
5744 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5746 else if (cdclk == 266667)
5751 mutex_lock(&dev_priv->rps.hw_lock);
5752 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5753 val &= ~DSPFREQGUAR_MASK;
5754 val |= (cmd << DSPFREQGUAR_SHIFT);
5755 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5756 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5757 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5759 DRM_ERROR("timed out waiting for CDclk change\n");
5761 mutex_unlock(&dev_priv->rps.hw_lock);
5763 mutex_lock(&dev_priv->sb_lock);
5765 if (cdclk == 400000) {
5768 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5770 /* adjust cdclk divider */
5771 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5772 val &= ~DISPLAY_FREQUENCY_VALUES;
5774 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5776 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5777 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5779 DRM_ERROR("timed out waiting for CDclk change\n");
5782 /* adjust self-refresh exit latency value */
5783 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5787 * For high bandwidth configs, we set a higher latency in the bunit
5788 * so that the core display fetch happens in time to avoid underruns.
5790 if (cdclk == 400000)
5791 val |= 4500 / 250; /* 4.5 usec */
5793 val |= 3000 / 250; /* 3.0 usec */
5794 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5796 mutex_unlock(&dev_priv->sb_lock);
5798 intel_update_cdclk(dev);
5801 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5803 struct drm_i915_private *dev_priv = dev->dev_private;
5806 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807 != dev_priv->cdclk_freq);
5816 MISSING_CASE(cdclk);
5821 * Specs are full of misinformation, but testing on actual
5822 * hardware has shown that we just need to write the desired
5823 * CCK divider into the Punit register.
5825 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5827 mutex_lock(&dev_priv->rps.hw_lock);
5828 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5829 val &= ~DSPFREQGUAR_MASK_CHV;
5830 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5831 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5832 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5833 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5835 DRM_ERROR("timed out waiting for CDclk change\n");
5837 mutex_unlock(&dev_priv->rps.hw_lock);
5839 intel_update_cdclk(dev);
5842 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5845 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5846 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5849 * Really only a few cases to deal with, as only 4 CDclks are supported:
5852 * 320/333MHz (depends on HPLL freq)
5854 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5855 * of the lower bin and adjust if needed.
5857 * We seem to get an unstable or solid color picture at 200MHz.
5858 * Not sure what's wrong. For now use 200MHz only when all pipes
5861 if (!IS_CHERRYVIEW(dev_priv) &&
5862 max_pixclk > freq_320*limit/100)
5864 else if (max_pixclk > 266667*limit/100)
5866 else if (max_pixclk > 0)
5872 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5877 * - remove the guardband, it's not needed on BXT
5878 * - set 19.2MHz bypass frequency if there are no active pipes
5880 if (max_pixclk > 576000*9/10)
5882 else if (max_pixclk > 384000*9/10)
5884 else if (max_pixclk > 288000*9/10)
5886 else if (max_pixclk > 144000*9/10)
5892 /* Compute the max pixel clock for new configuration. Uses atomic state if
5893 * that's non-NULL, look at current state otherwise. */
5894 static int intel_mode_max_pixclk(struct drm_device *dev,
5895 struct drm_atomic_state *state)
5897 struct intel_crtc *intel_crtc;
5898 struct intel_crtc_state *crtc_state;
5901 for_each_intel_crtc(dev, intel_crtc) {
5902 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5903 if (IS_ERR(crtc_state))
5904 return PTR_ERR(crtc_state);
5906 if (!crtc_state->base.enable)
5909 max_pixclk = max(max_pixclk,
5910 crtc_state->base.adjusted_mode.crtc_clock);
5916 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5918 struct drm_device *dev = state->dev;
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 int max_pixclk = intel_mode_max_pixclk(dev, state);
5925 to_intel_atomic_state(state)->cdclk =
5926 valleyview_calc_cdclk(dev_priv, max_pixclk);
5931 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5933 struct drm_device *dev = state->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 int max_pixclk = intel_mode_max_pixclk(dev, state);
5940 to_intel_atomic_state(state)->cdclk =
5941 broxton_calc_cdclk(dev_priv, max_pixclk);
5946 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5948 unsigned int credits, default_credits;
5950 if (IS_CHERRYVIEW(dev_priv))
5951 default_credits = PFI_CREDIT(12);
5953 default_credits = PFI_CREDIT(8);
5955 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5956 /* CHV suggested value is 31 or 63 */
5957 if (IS_CHERRYVIEW(dev_priv))
5958 credits = PFI_CREDIT_63;
5960 credits = PFI_CREDIT(15);
5962 credits = default_credits;
5966 * WA - write default credits before re-programming
5967 * FIXME: should we also set the resend bit here?
5969 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5972 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5973 credits | PFI_CREDIT_RESEND);
5976 * FIXME is this guaranteed to clear
5977 * immediately or should we poll for it?
5979 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5982 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5984 struct drm_device *dev = old_state->dev;
5985 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5989 * FIXME: We can end up here with all power domains off, yet
5990 * with a CDCLK frequency other than the minimum. To account
5991 * for this take the PIPE-A power domain, which covers the HW
5992 * blocks needed for the following programming. This can be
5993 * removed once it's guaranteed that we get here either with
5994 * the minimum CDCLK set, or the required power domains
5997 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5999 if (IS_CHERRYVIEW(dev))
6000 cherryview_set_cdclk(dev, req_cdclk);
6002 valleyview_set_cdclk(dev, req_cdclk);
6004 vlv_program_pfi_credits(dev_priv);
6006 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6009 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6011 struct drm_device *dev = crtc->dev;
6012 struct drm_i915_private *dev_priv = to_i915(dev);
6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct intel_encoder *encoder;
6015 int pipe = intel_crtc->pipe;
6018 if (WARN_ON(intel_crtc->active))
6021 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6024 if (IS_CHERRYVIEW(dev))
6025 chv_prepare_pll(intel_crtc, intel_crtc->config);
6027 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6030 if (intel_crtc->config->has_dp_encoder)
6031 intel_dp_set_m_n(intel_crtc, M1_N1);
6033 intel_set_pipe_timings(intel_crtc);
6035 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6038 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6039 I915_WRITE(CHV_CANVAS(pipe), 0);
6042 i9xx_set_pipeconf(intel_crtc);
6044 intel_crtc->active = true;
6046 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6048 for_each_encoder_on_crtc(dev, crtc, encoder)
6049 if (encoder->pre_pll_enable)
6050 encoder->pre_pll_enable(encoder);
6053 if (IS_CHERRYVIEW(dev))
6054 chv_enable_pll(intel_crtc, intel_crtc->config);
6056 vlv_enable_pll(intel_crtc, intel_crtc->config);
6059 for_each_encoder_on_crtc(dev, crtc, encoder)
6060 if (encoder->pre_enable)
6061 encoder->pre_enable(encoder);
6063 i9xx_pfit_enable(intel_crtc);
6065 intel_crtc_load_lut(crtc);
6067 intel_enable_pipe(intel_crtc);
6069 assert_vblank_disabled(crtc);
6070 drm_crtc_vblank_on(crtc);
6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 encoder->enable(encoder);
6076 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6078 struct drm_device *dev = crtc->base.dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6081 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6082 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6085 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = to_i915(dev);
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 struct intel_encoder *encoder;
6091 int pipe = intel_crtc->pipe;
6093 if (WARN_ON(intel_crtc->active))
6096 i9xx_set_pll_dividers(intel_crtc);
6098 if (intel_crtc->config->has_dp_encoder)
6099 intel_dp_set_m_n(intel_crtc, M1_N1);
6101 intel_set_pipe_timings(intel_crtc);
6103 i9xx_set_pipeconf(intel_crtc);
6105 intel_crtc->active = true;
6108 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 if (encoder->pre_enable)
6112 encoder->pre_enable(encoder);
6114 i9xx_enable_pll(intel_crtc);
6116 i9xx_pfit_enable(intel_crtc);
6118 intel_crtc_load_lut(crtc);
6120 intel_update_watermarks(crtc);
6121 intel_enable_pipe(intel_crtc);
6123 assert_vblank_disabled(crtc);
6124 drm_crtc_vblank_on(crtc);
6126 for_each_encoder_on_crtc(dev, crtc, encoder)
6127 encoder->enable(encoder);
6130 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6132 struct drm_device *dev = crtc->base.dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
6135 if (!crtc->config->gmch_pfit.control)
6138 assert_pipe_disabled(dev_priv, crtc->pipe);
6140 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6141 I915_READ(PFIT_CONTROL));
6142 I915_WRITE(PFIT_CONTROL, 0);
6145 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 struct intel_encoder *encoder;
6151 int pipe = intel_crtc->pipe;
6154 * On gen2 planes are double buffered but the pipe isn't, so we must
6155 * wait for planes to fully turn off before disabling the pipe.
6156 * We also need to wait on all gmch platforms because of the
6157 * self-refresh mode constraint explained above.
6159 intel_wait_for_vblank(dev, pipe);
6161 for_each_encoder_on_crtc(dev, crtc, encoder)
6162 encoder->disable(encoder);
6164 drm_crtc_vblank_off(crtc);
6165 assert_vblank_disabled(crtc);
6167 intel_disable_pipe(intel_crtc);
6169 i9xx_pfit_disable(intel_crtc);
6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 if (encoder->post_disable)
6173 encoder->post_disable(encoder);
6175 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6176 if (IS_CHERRYVIEW(dev))
6177 chv_disable_pll(dev_priv, pipe);
6178 else if (IS_VALLEYVIEW(dev))
6179 vlv_disable_pll(dev_priv, pipe);
6181 i9xx_disable_pll(intel_crtc);
6185 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6187 intel_crtc->active = false;
6188 intel_update_watermarks(crtc);
6191 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6195 enum intel_display_power_domain domain;
6196 unsigned long domains;
6198 if (!intel_crtc->active)
6201 if (to_intel_plane_state(crtc->primary->state)->visible) {
6202 intel_crtc_wait_for_pending_flips(crtc);
6203 intel_pre_disable_primary(crtc);
6206 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6207 dev_priv->display.crtc_disable(crtc);
6208 intel_disable_shared_dpll(intel_crtc);
6210 domains = intel_crtc->enabled_power_domains;
6211 for_each_power_domain(domain, domains)
6212 intel_display_power_put(dev_priv, domain);
6213 intel_crtc->enabled_power_domains = 0;
6217 * turn all crtc's off, but do not adjust state
6218 * This has to be paired with a call to intel_modeset_setup_hw_state.
6220 int intel_display_suspend(struct drm_device *dev)
6222 struct drm_mode_config *config = &dev->mode_config;
6223 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6224 struct drm_atomic_state *state;
6225 struct drm_crtc *crtc;
6226 unsigned crtc_mask = 0;
6232 lockdep_assert_held(&ctx->ww_ctx);
6233 state = drm_atomic_state_alloc(dev);
6234 if (WARN_ON(!state))
6237 state->acquire_ctx = ctx;
6238 state->allow_modeset = true;
6240 for_each_crtc(dev, crtc) {
6241 struct drm_crtc_state *crtc_state =
6242 drm_atomic_get_crtc_state(state, crtc);
6244 ret = PTR_ERR_OR_ZERO(crtc_state);
6248 if (!crtc_state->active)
6251 crtc_state->active = false;
6252 crtc_mask |= 1 << drm_crtc_index(crtc);
6256 ret = drm_atomic_commit(state);
6259 for_each_crtc(dev, crtc)
6260 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6261 crtc->state->active = true;
6269 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6270 drm_atomic_state_free(state);
6274 /* Master function to enable/disable CRTC and corresponding power wells */
6275 int intel_crtc_control(struct drm_crtc *crtc, bool enable)
6277 struct drm_device *dev = crtc->dev;
6278 struct drm_mode_config *config = &dev->mode_config;
6279 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6281 struct intel_crtc_state *pipe_config;
6282 struct drm_atomic_state *state;
6285 if (enable == intel_crtc->active)
6288 if (enable && !crtc->state->enable)
6291 /* this function should be called with drm_modeset_lock_all for now */
6294 lockdep_assert_held(&ctx->ww_ctx);
6296 state = drm_atomic_state_alloc(dev);
6297 if (WARN_ON(!state))
6300 state->acquire_ctx = ctx;
6301 state->allow_modeset = true;
6303 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6304 if (IS_ERR(pipe_config)) {
6305 ret = PTR_ERR(pipe_config);
6308 pipe_config->base.active = enable;
6310 ret = drm_atomic_commit(state);
6315 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6316 drm_atomic_state_free(state);
6321 * Sets the power management mode of the pipe and plane.
6323 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6325 struct drm_device *dev = crtc->dev;
6326 struct intel_encoder *intel_encoder;
6327 bool enable = false;
6329 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6330 enable |= intel_encoder->connectors_active;
6332 intel_crtc_control(crtc, enable);
6335 void intel_encoder_destroy(struct drm_encoder *encoder)
6337 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6339 drm_encoder_cleanup(encoder);
6340 kfree(intel_encoder);
6343 /* Simple dpms helper for encoders with just one connector, no cloning and only
6344 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6345 * state of the entire output pipe. */
6346 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6348 if (mode == DRM_MODE_DPMS_ON) {
6349 encoder->connectors_active = true;
6351 intel_crtc_update_dpms(encoder->base.crtc);
6353 encoder->connectors_active = false;
6355 intel_crtc_update_dpms(encoder->base.crtc);
6359 /* Cross check the actual hw state with our own modeset state tracking (and it's
6360 * internal consistency). */
6361 static void intel_connector_check_state(struct intel_connector *connector)
6363 if (connector->get_hw_state(connector)) {
6364 struct intel_encoder *encoder = connector->encoder;
6365 struct drm_crtc *crtc;
6366 bool encoder_enabled;
6369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6370 connector->base.base.id,
6371 connector->base.name);
6373 /* there is no real hw state for MST connectors */
6374 if (connector->mst_port)
6377 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6378 "wrong connector dpms state\n");
6379 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6380 "active connector not linked to encoder\n");
6383 I915_STATE_WARN(!encoder->connectors_active,
6384 "encoder->connectors_active not set\n");
6386 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6387 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6388 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6391 crtc = encoder->base.crtc;
6393 I915_STATE_WARN(!crtc->state->enable,
6394 "crtc not enabled\n");
6395 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6396 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6397 "encoder active on the wrong pipe\n");
6402 int intel_connector_init(struct intel_connector *connector)
6404 struct drm_connector_state *connector_state;
6406 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6407 if (!connector_state)
6410 connector->base.state = connector_state;
6414 struct intel_connector *intel_connector_alloc(void)
6416 struct intel_connector *connector;
6418 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6422 if (intel_connector_init(connector) < 0) {
6430 /* Even simpler default implementation, if there's really no special case to
6432 int intel_connector_dpms(struct drm_connector *connector, int mode)
6434 /* All the simple cases only support two dpms states. */
6435 if (mode != DRM_MODE_DPMS_ON)
6436 mode = DRM_MODE_DPMS_OFF;
6438 if (mode == connector->dpms)
6441 connector->dpms = mode;
6443 /* Only need to change hw state when actually enabled */
6444 if (connector->encoder)
6445 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6447 intel_modeset_check_state(connector->dev);
6452 /* Simple connector->get_hw_state implementation for encoders that support only
6453 * one connector and no cloning and hence the encoder state determines the state
6454 * of the connector. */
6455 bool intel_connector_get_hw_state(struct intel_connector *connector)
6458 struct intel_encoder *encoder = connector->encoder;
6460 return encoder->get_hw_state(encoder, &pipe);
6463 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6465 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6466 return crtc_state->fdi_lanes;
6471 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6472 struct intel_crtc_state *pipe_config)
6474 struct drm_atomic_state *state = pipe_config->base.state;
6475 struct intel_crtc *other_crtc;
6476 struct intel_crtc_state *other_crtc_state;
6478 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6479 pipe_name(pipe), pipe_config->fdi_lanes);
6480 if (pipe_config->fdi_lanes > 4) {
6481 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6482 pipe_name(pipe), pipe_config->fdi_lanes);
6486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6487 if (pipe_config->fdi_lanes > 2) {
6488 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6489 pipe_config->fdi_lanes);
6496 if (INTEL_INFO(dev)->num_pipes == 2)
6499 /* Ivybridge 3 pipe is really complicated */
6504 if (pipe_config->fdi_lanes <= 2)
6507 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6509 intel_atomic_get_crtc_state(state, other_crtc);
6510 if (IS_ERR(other_crtc_state))
6511 return PTR_ERR(other_crtc_state);
6513 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6514 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6520 if (pipe_config->fdi_lanes > 2) {
6521 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6522 pipe_name(pipe), pipe_config->fdi_lanes);
6526 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6528 intel_atomic_get_crtc_state(state, other_crtc);
6529 if (IS_ERR(other_crtc_state))
6530 return PTR_ERR(other_crtc_state);
6532 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6533 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6543 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6544 struct intel_crtc_state *pipe_config)
6546 struct drm_device *dev = intel_crtc->base.dev;
6547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6548 int lane, link_bw, fdi_dotclock, ret;
6549 bool needs_recompute = false;
6552 /* FDI is a binary signal running at ~2.7GHz, encoding
6553 * each output octet as 10 bits. The actual frequency
6554 * is stored as a divider into a 100MHz clock, and the
6555 * mode pixel clock is stored in units of 1KHz.
6556 * Hence the bw of each lane in terms of the mode signal
6559 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6561 fdi_dotclock = adjusted_mode->crtc_clock;
6563 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6564 pipe_config->pipe_bpp);
6566 pipe_config->fdi_lanes = lane;
6568 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6569 link_bw, &pipe_config->fdi_m_n);
6571 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6572 intel_crtc->pipe, pipe_config);
6573 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6574 pipe_config->pipe_bpp -= 2*3;
6575 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6576 pipe_config->pipe_bpp);
6577 needs_recompute = true;
6578 pipe_config->bw_constrained = true;
6583 if (needs_recompute)
6589 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6590 struct intel_crtc_state *pipe_config)
6592 if (pipe_config->pipe_bpp > 24)
6595 /* HSW can handle pixel rate up to cdclk? */
6596 if (IS_HASWELL(dev_priv->dev))
6600 * We compare against max which means we must take
6601 * the increased cdclk requirement into account when
6602 * calculating the new cdclk.
6604 * Should measure whether using a lower cdclk w/o IPS
6606 return ilk_pipe_pixel_rate(pipe_config) <=
6607 dev_priv->max_cdclk_freq * 95 / 100;
6610 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6611 struct intel_crtc_state *pipe_config)
6613 struct drm_device *dev = crtc->base.dev;
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6616 pipe_config->ips_enabled = i915.enable_ips &&
6617 hsw_crtc_supports_ips(crtc) &&
6618 pipe_config_supports_ips(dev_priv, pipe_config);
6621 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6622 struct intel_crtc_state *pipe_config)
6624 struct drm_device *dev = crtc->base.dev;
6625 struct drm_i915_private *dev_priv = dev->dev_private;
6626 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6628 /* FIXME should check pixel clock limits on all platforms */
6629 if (INTEL_INFO(dev)->gen < 4) {
6630 int clock_limit = dev_priv->max_cdclk_freq;
6633 * Enable pixel doubling when the dot clock
6634 * is > 90% of the (display) core speed.
6636 * GDG double wide on either pipe,
6637 * otherwise pipe A only.
6639 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6640 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6642 pipe_config->double_wide = true;
6645 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6650 * Pipe horizontal size must be even in:
6652 * - LVDS dual channel mode
6653 * - Double wide pipe
6655 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6656 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6657 pipe_config->pipe_src_w &= ~1;
6659 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6660 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6662 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6663 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6667 hsw_compute_ips_config(crtc, pipe_config);
6669 if (pipe_config->has_pch_encoder)
6670 return ironlake_fdi_compute_config(crtc, pipe_config);
6675 static int skylake_get_display_clock_speed(struct drm_device *dev)
6677 struct drm_i915_private *dev_priv = to_i915(dev);
6678 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6679 uint32_t cdctl = I915_READ(CDCLK_CTL);
6682 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6683 return 24000; /* 24MHz is the cd freq with NSSC ref */
6685 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6688 linkrate = (I915_READ(DPLL_CTRL1) &
6689 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6691 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6692 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6694 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6695 case CDCLK_FREQ_450_432:
6697 case CDCLK_FREQ_337_308:
6699 case CDCLK_FREQ_675_617:
6702 WARN(1, "Unknown cd freq selection\n");
6706 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6707 case CDCLK_FREQ_450_432:
6709 case CDCLK_FREQ_337_308:
6711 case CDCLK_FREQ_675_617:
6714 WARN(1, "Unknown cd freq selection\n");
6718 /* error case, do as if DPLL0 isn't enabled */
6722 static int broxton_get_display_clock_speed(struct drm_device *dev)
6724 struct drm_i915_private *dev_priv = to_i915(dev);
6725 uint32_t cdctl = I915_READ(CDCLK_CTL);
6726 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6727 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6730 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6733 cdclk = 19200 * pll_ratio / 2;
6735 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6736 case BXT_CDCLK_CD2X_DIV_SEL_1:
6737 return cdclk; /* 576MHz or 624MHz */
6738 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6739 return cdclk * 2 / 3; /* 384MHz */
6740 case BXT_CDCLK_CD2X_DIV_SEL_2:
6741 return cdclk / 2; /* 288MHz */
6742 case BXT_CDCLK_CD2X_DIV_SEL_4:
6743 return cdclk / 4; /* 144MHz */
6746 /* error case, do as if DE PLL isn't enabled */
6750 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6752 struct drm_i915_private *dev_priv = dev->dev_private;
6753 uint32_t lcpll = I915_READ(LCPLL_CTL);
6754 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6756 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6758 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6760 else if (freq == LCPLL_CLK_FREQ_450)
6762 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6764 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6770 static int haswell_get_display_clock_speed(struct drm_device *dev)
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 uint32_t lcpll = I915_READ(LCPLL_CTL);
6774 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6776 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6778 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6780 else if (freq == LCPLL_CLK_FREQ_450)
6782 else if (IS_HSW_ULT(dev))
6788 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6790 struct drm_i915_private *dev_priv = dev->dev_private;
6794 if (dev_priv->hpll_freq == 0)
6795 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6797 mutex_lock(&dev_priv->sb_lock);
6798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6799 mutex_unlock(&dev_priv->sb_lock);
6801 divider = val & DISPLAY_FREQUENCY_VALUES;
6803 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6804 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6805 "cdclk change in progress\n");
6807 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6810 static int ilk_get_display_clock_speed(struct drm_device *dev)
6815 static int i945_get_display_clock_speed(struct drm_device *dev)
6820 static int i915_get_display_clock_speed(struct drm_device *dev)
6825 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6830 static int pnv_get_display_clock_speed(struct drm_device *dev)
6834 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6836 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6837 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6839 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6841 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6843 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6846 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6847 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6849 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6854 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6858 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6860 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6863 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6864 case GC_DISPLAY_CLOCK_333_MHZ:
6867 case GC_DISPLAY_CLOCK_190_200_MHZ:
6873 static int i865_get_display_clock_speed(struct drm_device *dev)
6878 static int i85x_get_display_clock_speed(struct drm_device *dev)
6883 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6884 * encoding is different :(
6885 * FIXME is this the right way to detect 852GM/852GMV?
6887 if (dev->pdev->revision == 0x1)
6890 pci_bus_read_config_word(dev->pdev->bus,
6891 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6893 /* Assume that the hardware is in the high speed state. This
6894 * should be the default.
6896 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6897 case GC_CLOCK_133_200:
6898 case GC_CLOCK_133_200_2:
6899 case GC_CLOCK_100_200:
6901 case GC_CLOCK_166_250:
6903 case GC_CLOCK_100_133:
6905 case GC_CLOCK_133_266:
6906 case GC_CLOCK_133_266_2:
6907 case GC_CLOCK_166_266:
6911 /* Shouldn't happen */
6915 static int i830_get_display_clock_speed(struct drm_device *dev)
6920 static unsigned int intel_hpll_vco(struct drm_device *dev)
6922 struct drm_i915_private *dev_priv = dev->dev_private;
6923 static const unsigned int blb_vco[8] = {
6930 static const unsigned int pnv_vco[8] = {
6937 static const unsigned int cl_vco[8] = {
6946 static const unsigned int elk_vco[8] = {
6952 static const unsigned int ctg_vco[8] = {
6960 const unsigned int *vco_table;
6964 /* FIXME other chipsets? */
6966 vco_table = ctg_vco;
6967 else if (IS_G4X(dev))
6968 vco_table = elk_vco;
6969 else if (IS_CRESTLINE(dev))
6971 else if (IS_PINEVIEW(dev))
6972 vco_table = pnv_vco;
6973 else if (IS_G33(dev))
6974 vco_table = blb_vco;
6978 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6980 vco = vco_table[tmp & 0x7];
6982 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6984 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6989 static int gm45_get_display_clock_speed(struct drm_device *dev)
6991 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6994 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6996 cdclk_sel = (tmp >> 12) & 0x1;
7002 return cdclk_sel ? 333333 : 222222;
7004 return cdclk_sel ? 320000 : 228571;
7006 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7011 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7013 static const uint8_t div_3200[] = { 16, 10, 8 };
7014 static const uint8_t div_4000[] = { 20, 12, 10 };
7015 static const uint8_t div_5333[] = { 24, 16, 14 };
7016 const uint8_t *div_table;
7017 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7020 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7022 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7024 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7029 div_table = div_3200;
7032 div_table = div_4000;
7035 div_table = div_5333;
7041 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7044 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7048 static int g33_get_display_clock_speed(struct drm_device *dev)
7050 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7051 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7052 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7053 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7054 const uint8_t *div_table;
7055 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7058 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7060 cdclk_sel = (tmp >> 4) & 0x7;
7062 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7067 div_table = div_3200;
7070 div_table = div_4000;
7073 div_table = div_4800;
7076 div_table = div_5333;
7082 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7085 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7090 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7092 while (*num > DATA_LINK_M_N_MASK ||
7093 *den > DATA_LINK_M_N_MASK) {
7099 static void compute_m_n(unsigned int m, unsigned int n,
7100 uint32_t *ret_m, uint32_t *ret_n)
7102 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7103 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7104 intel_reduce_m_n_ratio(ret_m, ret_n);
7108 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7109 int pixel_clock, int link_clock,
7110 struct intel_link_m_n *m_n)
7114 compute_m_n(bits_per_pixel * pixel_clock,
7115 link_clock * nlanes * 8,
7116 &m_n->gmch_m, &m_n->gmch_n);
7118 compute_m_n(pixel_clock, link_clock,
7119 &m_n->link_m, &m_n->link_n);
7122 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7124 if (i915.panel_use_ssc >= 0)
7125 return i915.panel_use_ssc != 0;
7126 return dev_priv->vbt.lvds_use_ssc
7127 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7130 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7133 struct drm_device *dev = crtc_state->base.crtc->dev;
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7137 WARN_ON(!crtc_state->base.state);
7139 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7141 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7142 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7143 refclk = dev_priv->vbt.lvds_ssc_freq;
7144 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7145 } else if (!IS_GEN2(dev)) {
7154 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7156 return (1 << dpll->n) << 16 | dpll->m2;
7159 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7161 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7164 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7165 struct intel_crtc_state *crtc_state,
7166 intel_clock_t *reduced_clock)
7168 struct drm_device *dev = crtc->base.dev;
7171 if (IS_PINEVIEW(dev)) {
7172 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7174 fp2 = pnv_dpll_compute_fp(reduced_clock);
7176 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7178 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7181 crtc_state->dpll_hw_state.fp0 = fp;
7183 crtc->lowfreq_avail = false;
7184 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7186 crtc_state->dpll_hw_state.fp1 = fp2;
7187 crtc->lowfreq_avail = true;
7189 crtc_state->dpll_hw_state.fp1 = fp;
7193 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7199 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7200 * and set it to a reasonable value instead.
7202 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7203 reg_val &= 0xffffff00;
7204 reg_val |= 0x00000030;
7205 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7207 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7208 reg_val &= 0x8cffffff;
7209 reg_val = 0x8c000000;
7210 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7212 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7213 reg_val &= 0xffffff00;
7214 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7216 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7217 reg_val &= 0x00ffffff;
7218 reg_val |= 0xb0000000;
7219 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7222 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7223 struct intel_link_m_n *m_n)
7225 struct drm_device *dev = crtc->base.dev;
7226 struct drm_i915_private *dev_priv = dev->dev_private;
7227 int pipe = crtc->pipe;
7229 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7230 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7231 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7232 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7235 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7236 struct intel_link_m_n *m_n,
7237 struct intel_link_m_n *m2_n2)
7239 struct drm_device *dev = crtc->base.dev;
7240 struct drm_i915_private *dev_priv = dev->dev_private;
7241 int pipe = crtc->pipe;
7242 enum transcoder transcoder = crtc->config->cpu_transcoder;
7244 if (INTEL_INFO(dev)->gen >= 5) {
7245 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7246 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7247 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7248 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7249 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7250 * for gen < 8) and if DRRS is supported (to make sure the
7251 * registers are not unnecessarily accessed).
7253 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7254 crtc->config->has_drrs) {
7255 I915_WRITE(PIPE_DATA_M2(transcoder),
7256 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7257 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7258 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7259 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7262 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7263 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7264 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7265 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7269 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7271 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7274 dp_m_n = &crtc->config->dp_m_n;
7275 dp_m2_n2 = &crtc->config->dp_m2_n2;
7276 } else if (m_n == M2_N2) {
7279 * M2_N2 registers are not supported. Hence m2_n2 divider value
7280 * needs to be programmed into M1_N1.
7282 dp_m_n = &crtc->config->dp_m2_n2;
7284 DRM_ERROR("Unsupported divider value\n");
7288 if (crtc->config->has_pch_encoder)
7289 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7291 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7294 static void vlv_compute_dpll(struct intel_crtc *crtc,
7295 struct intel_crtc_state *pipe_config)
7300 * Enable DPIO clock input. We should never disable the reference
7301 * clock for pipe B, since VGA hotplug / manual detection depends
7304 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7305 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7306 /* We should never disable this, set it here for state tracking */
7307 if (crtc->pipe == PIPE_B)
7308 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7309 dpll |= DPLL_VCO_ENABLE;
7310 pipe_config->dpll_hw_state.dpll = dpll;
7312 dpll_md = (pipe_config->pixel_multiplier - 1)
7313 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7314 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7317 static void vlv_prepare_pll(struct intel_crtc *crtc,
7318 const struct intel_crtc_state *pipe_config)
7320 struct drm_device *dev = crtc->base.dev;
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322 int pipe = crtc->pipe;
7324 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7325 u32 coreclk, reg_val;
7327 mutex_lock(&dev_priv->sb_lock);
7329 bestn = pipe_config->dpll.n;
7330 bestm1 = pipe_config->dpll.m1;
7331 bestm2 = pipe_config->dpll.m2;
7332 bestp1 = pipe_config->dpll.p1;
7333 bestp2 = pipe_config->dpll.p2;
7335 /* See eDP HDMI DPIO driver vbios notes doc */
7337 /* PLL B needs special handling */
7339 vlv_pllb_recal_opamp(dev_priv, pipe);
7341 /* Set up Tx target for periodic Rcomp update */
7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7344 /* Disable target IRef on PLL */
7345 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7346 reg_val &= 0x00ffffff;
7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7349 /* Disable fast lock */
7350 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7352 /* Set idtafcrecal before PLL is enabled */
7353 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7354 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7355 mdiv |= ((bestn << DPIO_N_SHIFT));
7356 mdiv |= (1 << DPIO_K_SHIFT);
7359 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7360 * but we don't support that).
7361 * Note: don't use the DAC post divider as it seems unstable.
7363 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7364 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7366 mdiv |= DPIO_ENABLE_CALIBRATION;
7367 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7369 /* Set HBR and RBR LPF coefficients */
7370 if (pipe_config->port_clock == 162000 ||
7371 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7372 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7373 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7376 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7379 if (pipe_config->has_dp_encoder) {
7380 /* Use SSC source */
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7387 } else { /* HDMI or VGA */
7388 /* Use bend source */
7390 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7393 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7397 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7398 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7400 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7401 coreclk |= 0x01000000;
7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7404 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7405 mutex_unlock(&dev_priv->sb_lock);
7408 static void chv_compute_dpll(struct intel_crtc *crtc,
7409 struct intel_crtc_state *pipe_config)
7411 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7412 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7414 if (crtc->pipe != PIPE_A)
7415 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7417 pipe_config->dpll_hw_state.dpll_md =
7418 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7421 static void chv_prepare_pll(struct intel_crtc *crtc,
7422 const struct intel_crtc_state *pipe_config)
7424 struct drm_device *dev = crtc->base.dev;
7425 struct drm_i915_private *dev_priv = dev->dev_private;
7426 int pipe = crtc->pipe;
7427 int dpll_reg = DPLL(crtc->pipe);
7428 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7429 u32 loopfilter, tribuf_calcntr;
7430 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7434 bestn = pipe_config->dpll.n;
7435 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7436 bestm1 = pipe_config->dpll.m1;
7437 bestm2 = pipe_config->dpll.m2 >> 22;
7438 bestp1 = pipe_config->dpll.p1;
7439 bestp2 = pipe_config->dpll.p2;
7440 vco = pipe_config->dpll.vco;
7445 * Enable Refclk and SSC
7447 I915_WRITE(dpll_reg,
7448 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7450 mutex_lock(&dev_priv->sb_lock);
7452 /* p1 and p2 divider */
7453 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7454 5 << DPIO_CHV_S1_DIV_SHIFT |
7455 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7456 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7457 1 << DPIO_CHV_K_DIV_SHIFT);
7459 /* Feedback post-divider - m2 */
7460 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7462 /* Feedback refclk divider - n and m1 */
7463 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7464 DPIO_CHV_M1_DIV_BY_2 |
7465 1 << DPIO_CHV_N_DIV_SHIFT);
7467 /* M2 fraction division */
7469 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7471 /* M2 fraction division enable */
7472 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7473 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7474 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7476 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7477 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7479 /* Program digital lock detect threshold */
7480 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7481 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7482 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7483 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7485 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7486 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7489 if (vco == 5400000) {
7490 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7491 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7492 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7493 tribuf_calcntr = 0x9;
7494 } else if (vco <= 6200000) {
7495 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7496 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7497 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7498 tribuf_calcntr = 0x9;
7499 } else if (vco <= 6480000) {
7500 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7501 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7502 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7503 tribuf_calcntr = 0x8;
7505 /* Not supported. Apply the same limits as in the max case */
7506 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7507 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7508 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7511 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7513 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7514 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7515 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7516 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7519 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7520 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7523 mutex_unlock(&dev_priv->sb_lock);
7527 * vlv_force_pll_on - forcibly enable just the PLL
7528 * @dev_priv: i915 private structure
7529 * @pipe: pipe PLL to enable
7530 * @dpll: PLL configuration
7532 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7533 * in cases where we need the PLL enabled even when @pipe is not going to
7536 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7537 const struct dpll *dpll)
7539 struct intel_crtc *crtc =
7540 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7541 struct intel_crtc_state pipe_config = {
7542 .base.crtc = &crtc->base,
7543 .pixel_multiplier = 1,
7547 if (IS_CHERRYVIEW(dev)) {
7548 chv_compute_dpll(crtc, &pipe_config);
7549 chv_prepare_pll(crtc, &pipe_config);
7550 chv_enable_pll(crtc, &pipe_config);
7552 vlv_compute_dpll(crtc, &pipe_config);
7553 vlv_prepare_pll(crtc, &pipe_config);
7554 vlv_enable_pll(crtc, &pipe_config);
7559 * vlv_force_pll_off - forcibly disable just the PLL
7560 * @dev_priv: i915 private structure
7561 * @pipe: pipe PLL to disable
7563 * Disable the PLL for @pipe. To be used in cases where we need
7564 * the PLL enabled even when @pipe is not going to be enabled.
7566 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7568 if (IS_CHERRYVIEW(dev))
7569 chv_disable_pll(to_i915(dev), pipe);
7571 vlv_disable_pll(to_i915(dev), pipe);
7574 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7575 struct intel_crtc_state *crtc_state,
7576 intel_clock_t *reduced_clock,
7579 struct drm_device *dev = crtc->base.dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7583 struct dpll *clock = &crtc_state->dpll;
7585 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7587 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7590 dpll = DPLL_VGA_MODE_DIS;
7592 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7593 dpll |= DPLLB_MODE_LVDS;
7595 dpll |= DPLLB_MODE_DAC_SERIAL;
7597 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7598 dpll |= (crtc_state->pixel_multiplier - 1)
7599 << SDVO_MULTIPLIER_SHIFT_HIRES;
7603 dpll |= DPLL_SDVO_HIGH_SPEED;
7605 if (crtc_state->has_dp_encoder)
7606 dpll |= DPLL_SDVO_HIGH_SPEED;
7608 /* compute bitmask from p1 value */
7609 if (IS_PINEVIEW(dev))
7610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7613 if (IS_G4X(dev) && reduced_clock)
7614 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7616 switch (clock->p2) {
7618 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7621 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7624 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7627 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7630 if (INTEL_INFO(dev)->gen >= 4)
7631 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7633 if (crtc_state->sdvo_tv_clock)
7634 dpll |= PLL_REF_INPUT_TVCLKINBC;
7635 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7636 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7637 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7639 dpll |= PLL_REF_INPUT_DREFCLK;
7641 dpll |= DPLL_VCO_ENABLE;
7642 crtc_state->dpll_hw_state.dpll = dpll;
7644 if (INTEL_INFO(dev)->gen >= 4) {
7645 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7646 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7647 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7651 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7652 struct intel_crtc_state *crtc_state,
7653 intel_clock_t *reduced_clock,
7656 struct drm_device *dev = crtc->base.dev;
7657 struct drm_i915_private *dev_priv = dev->dev_private;
7659 struct dpll *clock = &crtc_state->dpll;
7661 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7663 dpll = DPLL_VGA_MODE_DIS;
7665 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7666 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7669 dpll |= PLL_P1_DIVIDE_BY_TWO;
7671 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7673 dpll |= PLL_P2_DIVIDE_BY_4;
7676 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7677 dpll |= DPLL_DVO_2X_MODE;
7679 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7680 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7681 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7683 dpll |= PLL_REF_INPUT_DREFCLK;
7685 dpll |= DPLL_VCO_ENABLE;
7686 crtc_state->dpll_hw_state.dpll = dpll;
7689 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7691 struct drm_device *dev = intel_crtc->base.dev;
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7693 enum pipe pipe = intel_crtc->pipe;
7694 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7695 struct drm_display_mode *adjusted_mode =
7696 &intel_crtc->config->base.adjusted_mode;
7697 uint32_t crtc_vtotal, crtc_vblank_end;
7700 /* We need to be careful not to changed the adjusted mode, for otherwise
7701 * the hw state checker will get angry at the mismatch. */
7702 crtc_vtotal = adjusted_mode->crtc_vtotal;
7703 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7705 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7706 /* the chip adds 2 halflines automatically */
7708 crtc_vblank_end -= 1;
7710 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7711 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7713 vsyncshift = adjusted_mode->crtc_hsync_start -
7714 adjusted_mode->crtc_htotal / 2;
7716 vsyncshift += adjusted_mode->crtc_htotal;
7719 if (INTEL_INFO(dev)->gen > 3)
7720 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7722 I915_WRITE(HTOTAL(cpu_transcoder),
7723 (adjusted_mode->crtc_hdisplay - 1) |
7724 ((adjusted_mode->crtc_htotal - 1) << 16));
7725 I915_WRITE(HBLANK(cpu_transcoder),
7726 (adjusted_mode->crtc_hblank_start - 1) |
7727 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7728 I915_WRITE(HSYNC(cpu_transcoder),
7729 (adjusted_mode->crtc_hsync_start - 1) |
7730 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7732 I915_WRITE(VTOTAL(cpu_transcoder),
7733 (adjusted_mode->crtc_vdisplay - 1) |
7734 ((crtc_vtotal - 1) << 16));
7735 I915_WRITE(VBLANK(cpu_transcoder),
7736 (adjusted_mode->crtc_vblank_start - 1) |
7737 ((crtc_vblank_end - 1) << 16));
7738 I915_WRITE(VSYNC(cpu_transcoder),
7739 (adjusted_mode->crtc_vsync_start - 1) |
7740 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7742 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7743 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7744 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7746 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7747 (pipe == PIPE_B || pipe == PIPE_C))
7748 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7750 /* pipesrc controls the size that is scaled from, which should
7751 * always be the user's requested size.
7753 I915_WRITE(PIPESRC(pipe),
7754 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7755 (intel_crtc->config->pipe_src_h - 1));
7758 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7759 struct intel_crtc_state *pipe_config)
7761 struct drm_device *dev = crtc->base.dev;
7762 struct drm_i915_private *dev_priv = dev->dev_private;
7763 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7766 tmp = I915_READ(HTOTAL(cpu_transcoder));
7767 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7768 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7769 tmp = I915_READ(HBLANK(cpu_transcoder));
7770 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7771 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7772 tmp = I915_READ(HSYNC(cpu_transcoder));
7773 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7774 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7776 tmp = I915_READ(VTOTAL(cpu_transcoder));
7777 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7778 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7779 tmp = I915_READ(VBLANK(cpu_transcoder));
7780 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7781 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7782 tmp = I915_READ(VSYNC(cpu_transcoder));
7783 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7784 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7786 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7787 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7788 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7789 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7792 tmp = I915_READ(PIPESRC(crtc->pipe));
7793 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7794 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7796 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7797 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7800 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7801 struct intel_crtc_state *pipe_config)
7803 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7804 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7805 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7806 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7808 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7809 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7810 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7811 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7813 mode->flags = pipe_config->base.adjusted_mode.flags;
7814 mode->type = DRM_MODE_TYPE_DRIVER;
7816 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7817 mode->flags |= pipe_config->base.adjusted_mode.flags;
7819 mode->hsync = drm_mode_hsync(mode);
7820 mode->vrefresh = drm_mode_vrefresh(mode);
7821 drm_mode_set_name(mode);
7824 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7826 struct drm_device *dev = intel_crtc->base.dev;
7827 struct drm_i915_private *dev_priv = dev->dev_private;
7832 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7833 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7834 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7836 if (intel_crtc->config->double_wide)
7837 pipeconf |= PIPECONF_DOUBLE_WIDE;
7839 /* only g4x and later have fancy bpc/dither controls */
7840 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7841 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7842 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7843 pipeconf |= PIPECONF_DITHER_EN |
7844 PIPECONF_DITHER_TYPE_SP;
7846 switch (intel_crtc->config->pipe_bpp) {
7848 pipeconf |= PIPECONF_6BPC;
7851 pipeconf |= PIPECONF_8BPC;
7854 pipeconf |= PIPECONF_10BPC;
7857 /* Case prevented by intel_choose_pipe_bpp_dither. */
7862 if (HAS_PIPE_CXSR(dev)) {
7863 if (intel_crtc->lowfreq_avail) {
7864 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7865 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7867 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7871 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7872 if (INTEL_INFO(dev)->gen < 4 ||
7873 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7874 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7876 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7878 pipeconf |= PIPECONF_PROGRESSIVE;
7880 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7881 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7883 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7884 POSTING_READ(PIPECONF(intel_crtc->pipe));
7887 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7888 struct intel_crtc_state *crtc_state)
7890 struct drm_device *dev = crtc->base.dev;
7891 struct drm_i915_private *dev_priv = dev->dev_private;
7892 int refclk, num_connectors = 0;
7893 intel_clock_t clock;
7895 bool is_dsi = false;
7896 struct intel_encoder *encoder;
7897 const intel_limit_t *limit;
7898 struct drm_atomic_state *state = crtc_state->base.state;
7899 struct drm_connector *connector;
7900 struct drm_connector_state *connector_state;
7903 memset(&crtc_state->dpll_hw_state, 0,
7904 sizeof(crtc_state->dpll_hw_state));
7906 for_each_connector_in_state(state, connector, connector_state, i) {
7907 if (connector_state->crtc != &crtc->base)
7910 encoder = to_intel_encoder(connector_state->best_encoder);
7912 switch (encoder->type) {
7913 case INTEL_OUTPUT_DSI:
7926 if (!crtc_state->clock_set) {
7927 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7930 * Returns a set of divisors for the desired target clock with
7931 * the given refclk, or FALSE. The returned values represent
7932 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7935 limit = intel_limit(crtc_state, refclk);
7936 ok = dev_priv->display.find_dpll(limit, crtc_state,
7937 crtc_state->port_clock,
7938 refclk, NULL, &clock);
7940 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7944 /* Compat-code for transition, will disappear. */
7945 crtc_state->dpll.n = clock.n;
7946 crtc_state->dpll.m1 = clock.m1;
7947 crtc_state->dpll.m2 = clock.m2;
7948 crtc_state->dpll.p1 = clock.p1;
7949 crtc_state->dpll.p2 = clock.p2;
7953 i8xx_compute_dpll(crtc, crtc_state, NULL,
7955 } else if (IS_CHERRYVIEW(dev)) {
7956 chv_compute_dpll(crtc, crtc_state);
7957 } else if (IS_VALLEYVIEW(dev)) {
7958 vlv_compute_dpll(crtc, crtc_state);
7960 i9xx_compute_dpll(crtc, crtc_state, NULL,
7967 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7968 struct intel_crtc_state *pipe_config)
7970 struct drm_device *dev = crtc->base.dev;
7971 struct drm_i915_private *dev_priv = dev->dev_private;
7974 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7977 tmp = I915_READ(PFIT_CONTROL);
7978 if (!(tmp & PFIT_ENABLE))
7981 /* Check whether the pfit is attached to our pipe. */
7982 if (INTEL_INFO(dev)->gen < 4) {
7983 if (crtc->pipe != PIPE_B)
7986 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7990 pipe_config->gmch_pfit.control = tmp;
7991 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7992 if (INTEL_INFO(dev)->gen < 5)
7993 pipe_config->gmch_pfit.lvds_border_bits =
7994 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7997 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7998 struct intel_crtc_state *pipe_config)
8000 struct drm_device *dev = crtc->base.dev;
8001 struct drm_i915_private *dev_priv = dev->dev_private;
8002 int pipe = pipe_config->cpu_transcoder;
8003 intel_clock_t clock;
8005 int refclk = 100000;
8007 /* In case of MIPI DPLL will not even be used */
8008 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8011 mutex_lock(&dev_priv->sb_lock);
8012 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8013 mutex_unlock(&dev_priv->sb_lock);
8015 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8016 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8017 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8018 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8019 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8021 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8025 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8026 struct intel_initial_plane_config *plane_config)
8028 struct drm_device *dev = crtc->base.dev;
8029 struct drm_i915_private *dev_priv = dev->dev_private;
8030 u32 val, base, offset;
8031 int pipe = crtc->pipe, plane = crtc->plane;
8032 int fourcc, pixel_format;
8033 unsigned int aligned_height;
8034 struct drm_framebuffer *fb;
8035 struct intel_framebuffer *intel_fb;
8037 val = I915_READ(DSPCNTR(plane));
8038 if (!(val & DISPLAY_PLANE_ENABLE))
8041 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8043 DRM_DEBUG_KMS("failed to alloc fb\n");
8047 fb = &intel_fb->base;
8049 if (INTEL_INFO(dev)->gen >= 4) {
8050 if (val & DISPPLANE_TILED) {
8051 plane_config->tiling = I915_TILING_X;
8052 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8056 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8057 fourcc = i9xx_format_to_fourcc(pixel_format);
8058 fb->pixel_format = fourcc;
8059 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8061 if (INTEL_INFO(dev)->gen >= 4) {
8062 if (plane_config->tiling)
8063 offset = I915_READ(DSPTILEOFF(plane));
8065 offset = I915_READ(DSPLINOFF(plane));
8066 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8068 base = I915_READ(DSPADDR(plane));
8070 plane_config->base = base;
8072 val = I915_READ(PIPESRC(pipe));
8073 fb->width = ((val >> 16) & 0xfff) + 1;
8074 fb->height = ((val >> 0) & 0xfff) + 1;
8076 val = I915_READ(DSPSTRIDE(pipe));
8077 fb->pitches[0] = val & 0xffffffc0;
8079 aligned_height = intel_fb_align_height(dev, fb->height,
8083 plane_config->size = fb->pitches[0] * aligned_height;
8085 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8086 pipe_name(pipe), plane, fb->width, fb->height,
8087 fb->bits_per_pixel, base, fb->pitches[0],
8088 plane_config->size);
8090 plane_config->fb = intel_fb;
8093 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8094 struct intel_crtc_state *pipe_config)
8096 struct drm_device *dev = crtc->base.dev;
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 int pipe = pipe_config->cpu_transcoder;
8099 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8100 intel_clock_t clock;
8101 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8102 int refclk = 100000;
8104 mutex_lock(&dev_priv->sb_lock);
8105 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8106 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8107 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8108 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8109 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8110 mutex_unlock(&dev_priv->sb_lock);
8112 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8113 clock.m2 = (pll_dw0 & 0xff) << 22;
8114 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8115 clock.m2 |= pll_dw2 & 0x3fffff;
8116 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8117 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8118 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8120 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8123 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8124 struct intel_crtc_state *pipe_config)
8126 struct drm_device *dev = crtc->base.dev;
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8130 if (!intel_display_power_is_enabled(dev_priv,
8131 POWER_DOMAIN_PIPE(crtc->pipe)))
8134 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8135 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8137 tmp = I915_READ(PIPECONF(crtc->pipe));
8138 if (!(tmp & PIPECONF_ENABLE))
8141 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8142 switch (tmp & PIPECONF_BPC_MASK) {
8144 pipe_config->pipe_bpp = 18;
8147 pipe_config->pipe_bpp = 24;
8149 case PIPECONF_10BPC:
8150 pipe_config->pipe_bpp = 30;
8157 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8158 pipe_config->limited_color_range = true;
8160 if (INTEL_INFO(dev)->gen < 4)
8161 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8163 intel_get_pipe_timings(crtc, pipe_config);
8165 i9xx_get_pfit_config(crtc, pipe_config);
8167 if (INTEL_INFO(dev)->gen >= 4) {
8168 tmp = I915_READ(DPLL_MD(crtc->pipe));
8169 pipe_config->pixel_multiplier =
8170 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8171 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8172 pipe_config->dpll_hw_state.dpll_md = tmp;
8173 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8174 tmp = I915_READ(DPLL(crtc->pipe));
8175 pipe_config->pixel_multiplier =
8176 ((tmp & SDVO_MULTIPLIER_MASK)
8177 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8179 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8180 * port and will be fixed up in the encoder->get_config
8182 pipe_config->pixel_multiplier = 1;
8184 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8185 if (!IS_VALLEYVIEW(dev)) {
8187 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8188 * on 830. Filter it out here so that we don't
8189 * report errors due to that.
8192 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8194 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8195 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8197 /* Mask out read-only status bits. */
8198 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8199 DPLL_PORTC_READY_MASK |
8200 DPLL_PORTB_READY_MASK);
8203 if (IS_CHERRYVIEW(dev))
8204 chv_crtc_clock_get(crtc, pipe_config);
8205 else if (IS_VALLEYVIEW(dev))
8206 vlv_crtc_clock_get(crtc, pipe_config);
8208 i9xx_crtc_clock_get(crtc, pipe_config);
8213 static void ironlake_init_pch_refclk(struct drm_device *dev)
8215 struct drm_i915_private *dev_priv = dev->dev_private;
8216 struct intel_encoder *encoder;
8218 bool has_lvds = false;
8219 bool has_cpu_edp = false;
8220 bool has_panel = false;
8221 bool has_ck505 = false;
8222 bool can_ssc = false;
8224 /* We need to take the global config into account */
8225 for_each_intel_encoder(dev, encoder) {
8226 switch (encoder->type) {
8227 case INTEL_OUTPUT_LVDS:
8231 case INTEL_OUTPUT_EDP:
8233 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8241 if (HAS_PCH_IBX(dev)) {
8242 has_ck505 = dev_priv->vbt.display_clock_mode;
8243 can_ssc = has_ck505;
8249 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8250 has_panel, has_lvds, has_ck505);
8252 /* Ironlake: try to setup display ref clock before DPLL
8253 * enabling. This is only under driver's control after
8254 * PCH B stepping, previous chipset stepping should be
8255 * ignoring this setting.
8257 val = I915_READ(PCH_DREF_CONTROL);
8259 /* As we must carefully and slowly disable/enable each source in turn,
8260 * compute the final state we want first and check if we need to
8261 * make any changes at all.
8264 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8266 final |= DREF_NONSPREAD_CK505_ENABLE;
8268 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8270 final &= ~DREF_SSC_SOURCE_MASK;
8271 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8272 final &= ~DREF_SSC1_ENABLE;
8275 final |= DREF_SSC_SOURCE_ENABLE;
8277 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8278 final |= DREF_SSC1_ENABLE;
8281 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8282 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8284 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8286 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8288 final |= DREF_SSC_SOURCE_DISABLE;
8289 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8295 /* Always enable nonspread source */
8296 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8299 val |= DREF_NONSPREAD_CK505_ENABLE;
8301 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8304 val &= ~DREF_SSC_SOURCE_MASK;
8305 val |= DREF_SSC_SOURCE_ENABLE;
8307 /* SSC must be turned on before enabling the CPU output */
8308 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8309 DRM_DEBUG_KMS("Using SSC on panel\n");
8310 val |= DREF_SSC1_ENABLE;
8312 val &= ~DREF_SSC1_ENABLE;
8314 /* Get SSC going before enabling the outputs */
8315 I915_WRITE(PCH_DREF_CONTROL, val);
8316 POSTING_READ(PCH_DREF_CONTROL);
8319 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8321 /* Enable CPU source on CPU attached eDP */
8323 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8324 DRM_DEBUG_KMS("Using SSC on eDP\n");
8325 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8327 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8329 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8331 I915_WRITE(PCH_DREF_CONTROL, val);
8332 POSTING_READ(PCH_DREF_CONTROL);
8335 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8337 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8339 /* Turn off CPU output */
8340 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8342 I915_WRITE(PCH_DREF_CONTROL, val);
8343 POSTING_READ(PCH_DREF_CONTROL);
8346 /* Turn off the SSC source */
8347 val &= ~DREF_SSC_SOURCE_MASK;
8348 val |= DREF_SSC_SOURCE_DISABLE;
8351 val &= ~DREF_SSC1_ENABLE;
8353 I915_WRITE(PCH_DREF_CONTROL, val);
8354 POSTING_READ(PCH_DREF_CONTROL);
8358 BUG_ON(val != final);
8361 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8365 tmp = I915_READ(SOUTH_CHICKEN2);
8366 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8367 I915_WRITE(SOUTH_CHICKEN2, tmp);
8369 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8370 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8371 DRM_ERROR("FDI mPHY reset assert timeout\n");
8373 tmp = I915_READ(SOUTH_CHICKEN2);
8374 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8375 I915_WRITE(SOUTH_CHICKEN2, tmp);
8377 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8378 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8379 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8382 /* WaMPhyProgramming:hsw */
8383 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8387 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8388 tmp &= ~(0xFF << 24);
8389 tmp |= (0x12 << 24);
8390 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8392 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8394 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8396 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8398 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8400 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8401 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8402 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8404 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8405 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8406 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8408 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8411 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8413 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8416 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8418 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8421 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8423 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8426 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8428 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8429 tmp &= ~(0xFF << 16);
8430 tmp |= (0x1C << 16);
8431 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8433 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8434 tmp &= ~(0xFF << 16);
8435 tmp |= (0x1C << 16);
8436 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8438 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8440 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8442 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8444 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8446 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8447 tmp &= ~(0xF << 28);
8449 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8451 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8452 tmp &= ~(0xF << 28);
8454 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8457 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8458 * Programming" based on the parameters passed:
8459 * - Sequence to enable CLKOUT_DP
8460 * - Sequence to enable CLKOUT_DP without spread
8461 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8463 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8466 struct drm_i915_private *dev_priv = dev->dev_private;
8469 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8471 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8472 with_fdi, "LP PCH doesn't have FDI\n"))
8475 mutex_lock(&dev_priv->sb_lock);
8477 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8478 tmp &= ~SBI_SSCCTL_DISABLE;
8479 tmp |= SBI_SSCCTL_PATHALT;
8480 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8485 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8486 tmp &= ~SBI_SSCCTL_PATHALT;
8487 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8490 lpt_reset_fdi_mphy(dev_priv);
8491 lpt_program_fdi_mphy(dev_priv);
8495 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8496 SBI_GEN0 : SBI_DBUFF0;
8497 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8498 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8499 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8501 mutex_unlock(&dev_priv->sb_lock);
8504 /* Sequence to disable CLKOUT_DP */
8505 static void lpt_disable_clkout_dp(struct drm_device *dev)
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8510 mutex_lock(&dev_priv->sb_lock);
8512 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8513 SBI_GEN0 : SBI_DBUFF0;
8514 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8515 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8516 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8518 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8519 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8520 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8521 tmp |= SBI_SSCCTL_PATHALT;
8522 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8525 tmp |= SBI_SSCCTL_DISABLE;
8526 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8529 mutex_unlock(&dev_priv->sb_lock);
8532 static void lpt_init_pch_refclk(struct drm_device *dev)
8534 struct intel_encoder *encoder;
8535 bool has_vga = false;
8537 for_each_intel_encoder(dev, encoder) {
8538 switch (encoder->type) {
8539 case INTEL_OUTPUT_ANALOG:
8548 lpt_enable_clkout_dp(dev, true, true);
8550 lpt_disable_clkout_dp(dev);
8554 * Initialize reference clocks when the driver loads
8556 void intel_init_pch_refclk(struct drm_device *dev)
8558 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8559 ironlake_init_pch_refclk(dev);
8560 else if (HAS_PCH_LPT(dev))
8561 lpt_init_pch_refclk(dev);
8564 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8566 struct drm_device *dev = crtc_state->base.crtc->dev;
8567 struct drm_i915_private *dev_priv = dev->dev_private;
8568 struct drm_atomic_state *state = crtc_state->base.state;
8569 struct drm_connector *connector;
8570 struct drm_connector_state *connector_state;
8571 struct intel_encoder *encoder;
8572 int num_connectors = 0, i;
8573 bool is_lvds = false;
8575 for_each_connector_in_state(state, connector, connector_state, i) {
8576 if (connector_state->crtc != crtc_state->base.crtc)
8579 encoder = to_intel_encoder(connector_state->best_encoder);
8581 switch (encoder->type) {
8582 case INTEL_OUTPUT_LVDS:
8591 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8592 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8593 dev_priv->vbt.lvds_ssc_freq);
8594 return dev_priv->vbt.lvds_ssc_freq;
8600 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8602 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8604 int pipe = intel_crtc->pipe;
8609 switch (intel_crtc->config->pipe_bpp) {
8611 val |= PIPECONF_6BPC;
8614 val |= PIPECONF_8BPC;
8617 val |= PIPECONF_10BPC;
8620 val |= PIPECONF_12BPC;
8623 /* Case prevented by intel_choose_pipe_bpp_dither. */
8627 if (intel_crtc->config->dither)
8628 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8630 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8631 val |= PIPECONF_INTERLACED_ILK;
8633 val |= PIPECONF_PROGRESSIVE;
8635 if (intel_crtc->config->limited_color_range)
8636 val |= PIPECONF_COLOR_RANGE_SELECT;
8638 I915_WRITE(PIPECONF(pipe), val);
8639 POSTING_READ(PIPECONF(pipe));
8643 * Set up the pipe CSC unit.
8645 * Currently only full range RGB to limited range RGB conversion
8646 * is supported, but eventually this should handle various
8647 * RGB<->YCbCr scenarios as well.
8649 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8651 struct drm_device *dev = crtc->dev;
8652 struct drm_i915_private *dev_priv = dev->dev_private;
8653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8654 int pipe = intel_crtc->pipe;
8655 uint16_t coeff = 0x7800; /* 1.0 */
8658 * TODO: Check what kind of values actually come out of the pipe
8659 * with these coeff/postoff values and adjust to get the best
8660 * accuracy. Perhaps we even need to take the bpc value into
8664 if (intel_crtc->config->limited_color_range)
8665 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8668 * GY/GU and RY/RU should be the other way around according
8669 * to BSpec, but reality doesn't agree. Just set them up in
8670 * a way that results in the correct picture.
8672 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8673 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8675 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8676 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8678 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8679 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8681 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8682 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8683 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8685 if (INTEL_INFO(dev)->gen > 6) {
8686 uint16_t postoff = 0;
8688 if (intel_crtc->config->limited_color_range)
8689 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8691 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8692 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8693 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8695 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8697 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8699 if (intel_crtc->config->limited_color_range)
8700 mode |= CSC_BLACK_SCREEN_OFFSET;
8702 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8706 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8708 struct drm_device *dev = crtc->dev;
8709 struct drm_i915_private *dev_priv = dev->dev_private;
8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8711 enum pipe pipe = intel_crtc->pipe;
8712 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8717 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8718 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8720 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8721 val |= PIPECONF_INTERLACED_ILK;
8723 val |= PIPECONF_PROGRESSIVE;
8725 I915_WRITE(PIPECONF(cpu_transcoder), val);
8726 POSTING_READ(PIPECONF(cpu_transcoder));
8728 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8729 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8731 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8734 switch (intel_crtc->config->pipe_bpp) {
8736 val |= PIPEMISC_DITHER_6_BPC;
8739 val |= PIPEMISC_DITHER_8_BPC;
8742 val |= PIPEMISC_DITHER_10_BPC;
8745 val |= PIPEMISC_DITHER_12_BPC;
8748 /* Case prevented by pipe_config_set_bpp. */
8752 if (intel_crtc->config->dither)
8753 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8755 I915_WRITE(PIPEMISC(pipe), val);
8759 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8760 struct intel_crtc_state *crtc_state,
8761 intel_clock_t *clock,
8762 bool *has_reduced_clock,
8763 intel_clock_t *reduced_clock)
8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
8768 const intel_limit_t *limit;
8771 refclk = ironlake_get_refclk(crtc_state);
8774 * Returns a set of divisors for the desired target clock with the given
8775 * refclk, or FALSE. The returned values represent the clock equation:
8776 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8778 limit = intel_limit(crtc_state, refclk);
8779 ret = dev_priv->display.find_dpll(limit, crtc_state,
8780 crtc_state->port_clock,
8781 refclk, NULL, clock);
8788 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8791 * Account for spread spectrum to avoid
8792 * oversubscribing the link. Max center spread
8793 * is 2.5%; use 5% for safety's sake.
8795 u32 bps = target_clock * bpp * 21 / 20;
8796 return DIV_ROUND_UP(bps, link_bw * 8);
8799 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8801 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8804 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8805 struct intel_crtc_state *crtc_state,
8807 intel_clock_t *reduced_clock, u32 *fp2)
8809 struct drm_crtc *crtc = &intel_crtc->base;
8810 struct drm_device *dev = crtc->dev;
8811 struct drm_i915_private *dev_priv = dev->dev_private;
8812 struct drm_atomic_state *state = crtc_state->base.state;
8813 struct drm_connector *connector;
8814 struct drm_connector_state *connector_state;
8815 struct intel_encoder *encoder;
8817 int factor, num_connectors = 0, i;
8818 bool is_lvds = false, is_sdvo = false;
8820 for_each_connector_in_state(state, connector, connector_state, i) {
8821 if (connector_state->crtc != crtc_state->base.crtc)
8824 encoder = to_intel_encoder(connector_state->best_encoder);
8826 switch (encoder->type) {
8827 case INTEL_OUTPUT_LVDS:
8830 case INTEL_OUTPUT_SDVO:
8831 case INTEL_OUTPUT_HDMI:
8841 /* Enable autotuning of the PLL clock (if permissible) */
8844 if ((intel_panel_use_ssc(dev_priv) &&
8845 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8846 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8848 } else if (crtc_state->sdvo_tv_clock)
8851 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8854 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8860 dpll |= DPLLB_MODE_LVDS;
8862 dpll |= DPLLB_MODE_DAC_SERIAL;
8864 dpll |= (crtc_state->pixel_multiplier - 1)
8865 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8868 dpll |= DPLL_SDVO_HIGH_SPEED;
8869 if (crtc_state->has_dp_encoder)
8870 dpll |= DPLL_SDVO_HIGH_SPEED;
8872 /* compute bitmask from p1 value */
8873 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8875 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8877 switch (crtc_state->dpll.p2) {
8879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8885 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8888 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8892 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8893 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8895 dpll |= PLL_REF_INPUT_DREFCLK;
8897 return dpll | DPLL_VCO_ENABLE;
8900 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8901 struct intel_crtc_state *crtc_state)
8903 struct drm_device *dev = crtc->base.dev;
8904 intel_clock_t clock, reduced_clock;
8905 u32 dpll = 0, fp = 0, fp2 = 0;
8906 bool ok, has_reduced_clock = false;
8907 bool is_lvds = false;
8908 struct intel_shared_dpll *pll;
8910 memset(&crtc_state->dpll_hw_state, 0,
8911 sizeof(crtc_state->dpll_hw_state));
8913 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8915 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8916 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8918 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8919 &has_reduced_clock, &reduced_clock);
8920 if (!ok && !crtc_state->clock_set) {
8921 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8924 /* Compat-code for transition, will disappear. */
8925 if (!crtc_state->clock_set) {
8926 crtc_state->dpll.n = clock.n;
8927 crtc_state->dpll.m1 = clock.m1;
8928 crtc_state->dpll.m2 = clock.m2;
8929 crtc_state->dpll.p1 = clock.p1;
8930 crtc_state->dpll.p2 = clock.p2;
8933 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8934 if (crtc_state->has_pch_encoder) {
8935 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8936 if (has_reduced_clock)
8937 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8939 dpll = ironlake_compute_dpll(crtc, crtc_state,
8940 &fp, &reduced_clock,
8941 has_reduced_clock ? &fp2 : NULL);
8943 crtc_state->dpll_hw_state.dpll = dpll;
8944 crtc_state->dpll_hw_state.fp0 = fp;
8945 if (has_reduced_clock)
8946 crtc_state->dpll_hw_state.fp1 = fp2;
8948 crtc_state->dpll_hw_state.fp1 = fp;
8950 pll = intel_get_shared_dpll(crtc, crtc_state);
8952 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8953 pipe_name(crtc->pipe));
8958 if (is_lvds && has_reduced_clock)
8959 crtc->lowfreq_avail = true;
8961 crtc->lowfreq_avail = false;
8966 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8967 struct intel_link_m_n *m_n)
8969 struct drm_device *dev = crtc->base.dev;
8970 struct drm_i915_private *dev_priv = dev->dev_private;
8971 enum pipe pipe = crtc->pipe;
8973 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8974 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8975 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8977 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8978 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8979 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8982 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8983 enum transcoder transcoder,
8984 struct intel_link_m_n *m_n,
8985 struct intel_link_m_n *m2_n2)
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
8989 enum pipe pipe = crtc->pipe;
8991 if (INTEL_INFO(dev)->gen >= 5) {
8992 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8993 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8994 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8996 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8997 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8998 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8999 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9000 * gen < 8) and if DRRS is supported (to make sure the
9001 * registers are not unnecessarily read).
9003 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9004 crtc->config->has_drrs) {
9005 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9006 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9007 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9009 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9010 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9011 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9014 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9015 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9016 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9018 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9019 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9020 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9024 void intel_dp_get_m_n(struct intel_crtc *crtc,
9025 struct intel_crtc_state *pipe_config)
9027 if (pipe_config->has_pch_encoder)
9028 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9030 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9031 &pipe_config->dp_m_n,
9032 &pipe_config->dp_m2_n2);
9035 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9036 struct intel_crtc_state *pipe_config)
9038 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9039 &pipe_config->fdi_m_n, NULL);
9042 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9043 struct intel_crtc_state *pipe_config)
9045 struct drm_device *dev = crtc->base.dev;
9046 struct drm_i915_private *dev_priv = dev->dev_private;
9047 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9048 uint32_t ps_ctrl = 0;
9052 /* find scaler attached to this pipe */
9053 for (i = 0; i < crtc->num_scalers; i++) {
9054 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9055 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9057 pipe_config->pch_pfit.enabled = true;
9058 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9059 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9064 scaler_state->scaler_id = id;
9066 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9068 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9073 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9074 struct intel_initial_plane_config *plane_config)
9076 struct drm_device *dev = crtc->base.dev;
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 u32 val, base, offset, stride_mult, tiling;
9079 int pipe = crtc->pipe;
9080 int fourcc, pixel_format;
9081 unsigned int aligned_height;
9082 struct drm_framebuffer *fb;
9083 struct intel_framebuffer *intel_fb;
9085 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9087 DRM_DEBUG_KMS("failed to alloc fb\n");
9091 fb = &intel_fb->base;
9093 val = I915_READ(PLANE_CTL(pipe, 0));
9094 if (!(val & PLANE_CTL_ENABLE))
9097 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9098 fourcc = skl_format_to_fourcc(pixel_format,
9099 val & PLANE_CTL_ORDER_RGBX,
9100 val & PLANE_CTL_ALPHA_MASK);
9101 fb->pixel_format = fourcc;
9102 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9104 tiling = val & PLANE_CTL_TILED_MASK;
9106 case PLANE_CTL_TILED_LINEAR:
9107 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9109 case PLANE_CTL_TILED_X:
9110 plane_config->tiling = I915_TILING_X;
9111 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9113 case PLANE_CTL_TILED_Y:
9114 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9116 case PLANE_CTL_TILED_YF:
9117 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9120 MISSING_CASE(tiling);
9124 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9125 plane_config->base = base;
9127 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9129 val = I915_READ(PLANE_SIZE(pipe, 0));
9130 fb->height = ((val >> 16) & 0xfff) + 1;
9131 fb->width = ((val >> 0) & 0x1fff) + 1;
9133 val = I915_READ(PLANE_STRIDE(pipe, 0));
9134 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9136 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9138 aligned_height = intel_fb_align_height(dev, fb->height,
9142 plane_config->size = fb->pitches[0] * aligned_height;
9144 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9145 pipe_name(pipe), fb->width, fb->height,
9146 fb->bits_per_pixel, base, fb->pitches[0],
9147 plane_config->size);
9149 plane_config->fb = intel_fb;
9156 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9157 struct intel_crtc_state *pipe_config)
9159 struct drm_device *dev = crtc->base.dev;
9160 struct drm_i915_private *dev_priv = dev->dev_private;
9163 tmp = I915_READ(PF_CTL(crtc->pipe));
9165 if (tmp & PF_ENABLE) {
9166 pipe_config->pch_pfit.enabled = true;
9167 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9168 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9170 /* We currently do not free assignements of panel fitters on
9171 * ivb/hsw (since we don't use the higher upscaling modes which
9172 * differentiates them) so just WARN about this case for now. */
9174 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9175 PF_PIPE_SEL_IVB(crtc->pipe));
9181 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9182 struct intel_initial_plane_config *plane_config)
9184 struct drm_device *dev = crtc->base.dev;
9185 struct drm_i915_private *dev_priv = dev->dev_private;
9186 u32 val, base, offset;
9187 int pipe = crtc->pipe;
9188 int fourcc, pixel_format;
9189 unsigned int aligned_height;
9190 struct drm_framebuffer *fb;
9191 struct intel_framebuffer *intel_fb;
9193 val = I915_READ(DSPCNTR(pipe));
9194 if (!(val & DISPLAY_PLANE_ENABLE))
9197 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9199 DRM_DEBUG_KMS("failed to alloc fb\n");
9203 fb = &intel_fb->base;
9205 if (INTEL_INFO(dev)->gen >= 4) {
9206 if (val & DISPPLANE_TILED) {
9207 plane_config->tiling = I915_TILING_X;
9208 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9212 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9213 fourcc = i9xx_format_to_fourcc(pixel_format);
9214 fb->pixel_format = fourcc;
9215 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9217 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9218 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9219 offset = I915_READ(DSPOFFSET(pipe));
9221 if (plane_config->tiling)
9222 offset = I915_READ(DSPTILEOFF(pipe));
9224 offset = I915_READ(DSPLINOFF(pipe));
9226 plane_config->base = base;
9228 val = I915_READ(PIPESRC(pipe));
9229 fb->width = ((val >> 16) & 0xfff) + 1;
9230 fb->height = ((val >> 0) & 0xfff) + 1;
9232 val = I915_READ(DSPSTRIDE(pipe));
9233 fb->pitches[0] = val & 0xffffffc0;
9235 aligned_height = intel_fb_align_height(dev, fb->height,
9239 plane_config->size = fb->pitches[0] * aligned_height;
9241 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9242 pipe_name(pipe), fb->width, fb->height,
9243 fb->bits_per_pixel, base, fb->pitches[0],
9244 plane_config->size);
9246 plane_config->fb = intel_fb;
9249 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9250 struct intel_crtc_state *pipe_config)
9252 struct drm_device *dev = crtc->base.dev;
9253 struct drm_i915_private *dev_priv = dev->dev_private;
9256 if (!intel_display_power_is_enabled(dev_priv,
9257 POWER_DOMAIN_PIPE(crtc->pipe)))
9260 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9261 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9263 tmp = I915_READ(PIPECONF(crtc->pipe));
9264 if (!(tmp & PIPECONF_ENABLE))
9267 switch (tmp & PIPECONF_BPC_MASK) {
9269 pipe_config->pipe_bpp = 18;
9272 pipe_config->pipe_bpp = 24;
9274 case PIPECONF_10BPC:
9275 pipe_config->pipe_bpp = 30;
9277 case PIPECONF_12BPC:
9278 pipe_config->pipe_bpp = 36;
9284 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9285 pipe_config->limited_color_range = true;
9287 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9288 struct intel_shared_dpll *pll;
9290 pipe_config->has_pch_encoder = true;
9292 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9293 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9294 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9296 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9298 if (HAS_PCH_IBX(dev_priv->dev)) {
9299 pipe_config->shared_dpll =
9300 (enum intel_dpll_id) crtc->pipe;
9302 tmp = I915_READ(PCH_DPLL_SEL);
9303 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9304 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9306 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9309 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9311 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9312 &pipe_config->dpll_hw_state));
9314 tmp = pipe_config->dpll_hw_state.dpll;
9315 pipe_config->pixel_multiplier =
9316 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9317 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9319 ironlake_pch_clock_get(crtc, pipe_config);
9321 pipe_config->pixel_multiplier = 1;
9324 intel_get_pipe_timings(crtc, pipe_config);
9326 ironlake_get_pfit_config(crtc, pipe_config);
9331 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9333 struct drm_device *dev = dev_priv->dev;
9334 struct intel_crtc *crtc;
9336 for_each_intel_crtc(dev, crtc)
9337 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9338 pipe_name(crtc->pipe));
9340 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9341 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9342 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9343 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9344 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9345 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9346 "CPU PWM1 enabled\n");
9347 if (IS_HASWELL(dev))
9348 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9349 "CPU PWM2 enabled\n");
9350 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9351 "PCH PWM1 enabled\n");
9352 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9353 "Utility pin enabled\n");
9354 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9357 * In theory we can still leave IRQs enabled, as long as only the HPD
9358 * interrupts remain enabled. We used to check for that, but since it's
9359 * gen-specific and since we only disable LCPLL after we fully disable
9360 * the interrupts, the check below should be enough.
9362 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9365 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9367 struct drm_device *dev = dev_priv->dev;
9369 if (IS_HASWELL(dev))
9370 return I915_READ(D_COMP_HSW);
9372 return I915_READ(D_COMP_BDW);
9375 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9377 struct drm_device *dev = dev_priv->dev;
9379 if (IS_HASWELL(dev)) {
9380 mutex_lock(&dev_priv->rps.hw_lock);
9381 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9383 DRM_ERROR("Failed to write to D_COMP\n");
9384 mutex_unlock(&dev_priv->rps.hw_lock);
9386 I915_WRITE(D_COMP_BDW, val);
9387 POSTING_READ(D_COMP_BDW);
9392 * This function implements pieces of two sequences from BSpec:
9393 * - Sequence for display software to disable LCPLL
9394 * - Sequence for display software to allow package C8+
9395 * The steps implemented here are just the steps that actually touch the LCPLL
9396 * register. Callers should take care of disabling all the display engine
9397 * functions, doing the mode unset, fixing interrupts, etc.
9399 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9400 bool switch_to_fclk, bool allow_power_down)
9404 assert_can_disable_lcpll(dev_priv);
9406 val = I915_READ(LCPLL_CTL);
9408 if (switch_to_fclk) {
9409 val |= LCPLL_CD_SOURCE_FCLK;
9410 I915_WRITE(LCPLL_CTL, val);
9412 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9413 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9414 DRM_ERROR("Switching to FCLK failed\n");
9416 val = I915_READ(LCPLL_CTL);
9419 val |= LCPLL_PLL_DISABLE;
9420 I915_WRITE(LCPLL_CTL, val);
9421 POSTING_READ(LCPLL_CTL);
9423 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9424 DRM_ERROR("LCPLL still locked\n");
9426 val = hsw_read_dcomp(dev_priv);
9427 val |= D_COMP_COMP_DISABLE;
9428 hsw_write_dcomp(dev_priv, val);
9431 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9433 DRM_ERROR("D_COMP RCOMP still in progress\n");
9435 if (allow_power_down) {
9436 val = I915_READ(LCPLL_CTL);
9437 val |= LCPLL_POWER_DOWN_ALLOW;
9438 I915_WRITE(LCPLL_CTL, val);
9439 POSTING_READ(LCPLL_CTL);
9444 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9447 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9451 val = I915_READ(LCPLL_CTL);
9453 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9454 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9458 * Make sure we're not on PC8 state before disabling PC8, otherwise
9459 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9461 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9463 if (val & LCPLL_POWER_DOWN_ALLOW) {
9464 val &= ~LCPLL_POWER_DOWN_ALLOW;
9465 I915_WRITE(LCPLL_CTL, val);
9466 POSTING_READ(LCPLL_CTL);
9469 val = hsw_read_dcomp(dev_priv);
9470 val |= D_COMP_COMP_FORCE;
9471 val &= ~D_COMP_COMP_DISABLE;
9472 hsw_write_dcomp(dev_priv, val);
9474 val = I915_READ(LCPLL_CTL);
9475 val &= ~LCPLL_PLL_DISABLE;
9476 I915_WRITE(LCPLL_CTL, val);
9478 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9479 DRM_ERROR("LCPLL not locked yet\n");
9481 if (val & LCPLL_CD_SOURCE_FCLK) {
9482 val = I915_READ(LCPLL_CTL);
9483 val &= ~LCPLL_CD_SOURCE_FCLK;
9484 I915_WRITE(LCPLL_CTL, val);
9486 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9487 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9488 DRM_ERROR("Switching back to LCPLL failed\n");
9491 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9492 intel_update_cdclk(dev_priv->dev);
9496 * Package states C8 and deeper are really deep PC states that can only be
9497 * reached when all the devices on the system allow it, so even if the graphics
9498 * device allows PC8+, it doesn't mean the system will actually get to these
9499 * states. Our driver only allows PC8+ when going into runtime PM.
9501 * The requirements for PC8+ are that all the outputs are disabled, the power
9502 * well is disabled and most interrupts are disabled, and these are also
9503 * requirements for runtime PM. When these conditions are met, we manually do
9504 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9505 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9508 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9509 * the state of some registers, so when we come back from PC8+ we need to
9510 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9511 * need to take care of the registers kept by RC6. Notice that this happens even
9512 * if we don't put the device in PCI D3 state (which is what currently happens
9513 * because of the runtime PM support).
9515 * For more, read "Display Sequences for Package C8" on the hardware
9518 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9520 struct drm_device *dev = dev_priv->dev;
9523 DRM_DEBUG_KMS("Enabling package C8+\n");
9525 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9526 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9527 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9528 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9531 lpt_disable_clkout_dp(dev);
9532 hsw_disable_lcpll(dev_priv, true, true);
9535 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9537 struct drm_device *dev = dev_priv->dev;
9540 DRM_DEBUG_KMS("Disabling package C8+\n");
9542 hsw_restore_lcpll(dev_priv);
9543 lpt_init_pch_refclk(dev);
9545 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9546 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9547 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9548 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9551 intel_prepare_ddi(dev);
9554 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9556 struct drm_device *dev = old_state->dev;
9557 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9559 broxton_set_cdclk(dev, req_cdclk);
9562 /* compute the max rate for new configuration */
9563 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9565 struct intel_crtc *intel_crtc;
9566 struct intel_crtc_state *crtc_state;
9567 int max_pixel_rate = 0;
9569 for_each_intel_crtc(state->dev, intel_crtc) {
9572 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9573 if (IS_ERR(crtc_state))
9574 return PTR_ERR(crtc_state);
9576 if (!crtc_state->base.enable)
9579 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9581 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9582 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9583 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9585 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9588 return max_pixel_rate;
9591 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9593 struct drm_i915_private *dev_priv = dev->dev_private;
9597 if (WARN((I915_READ(LCPLL_CTL) &
9598 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9599 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9600 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9601 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9602 "trying to change cdclk frequency with cdclk not enabled\n"))
9605 mutex_lock(&dev_priv->rps.hw_lock);
9606 ret = sandybridge_pcode_write(dev_priv,
9607 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9608 mutex_unlock(&dev_priv->rps.hw_lock);
9610 DRM_ERROR("failed to inform pcode about cdclk change\n");
9614 val = I915_READ(LCPLL_CTL);
9615 val |= LCPLL_CD_SOURCE_FCLK;
9616 I915_WRITE(LCPLL_CTL, val);
9618 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9619 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9620 DRM_ERROR("Switching to FCLK failed\n");
9622 val = I915_READ(LCPLL_CTL);
9623 val &= ~LCPLL_CLK_FREQ_MASK;
9627 val |= LCPLL_CLK_FREQ_450;
9631 val |= LCPLL_CLK_FREQ_54O_BDW;
9635 val |= LCPLL_CLK_FREQ_337_5_BDW;
9639 val |= LCPLL_CLK_FREQ_675_BDW;
9643 WARN(1, "invalid cdclk frequency\n");
9647 I915_WRITE(LCPLL_CTL, val);
9649 val = I915_READ(LCPLL_CTL);
9650 val &= ~LCPLL_CD_SOURCE_FCLK;
9651 I915_WRITE(LCPLL_CTL, val);
9653 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9654 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9655 DRM_ERROR("Switching back to LCPLL failed\n");
9657 mutex_lock(&dev_priv->rps.hw_lock);
9658 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9659 mutex_unlock(&dev_priv->rps.hw_lock);
9661 intel_update_cdclk(dev);
9663 WARN(cdclk != dev_priv->cdclk_freq,
9664 "cdclk requested %d kHz but got %d kHz\n",
9665 cdclk, dev_priv->cdclk_freq);
9668 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9670 struct drm_i915_private *dev_priv = to_i915(state->dev);
9671 int max_pixclk = ilk_max_pixel_rate(state);
9675 * FIXME should also account for plane ratio
9676 * once 64bpp pixel formats are supported.
9678 if (max_pixclk > 540000)
9680 else if (max_pixclk > 450000)
9682 else if (max_pixclk > 337500)
9688 * FIXME move the cdclk caclulation to
9689 * compute_config() so we can fail gracegully.
9691 if (cdclk > dev_priv->max_cdclk_freq) {
9692 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9693 cdclk, dev_priv->max_cdclk_freq);
9694 cdclk = dev_priv->max_cdclk_freq;
9697 to_intel_atomic_state(state)->cdclk = cdclk;
9702 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9704 struct drm_device *dev = old_state->dev;
9705 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9707 broadwell_set_cdclk(dev, req_cdclk);
9710 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9711 struct intel_crtc_state *crtc_state)
9713 if (!intel_ddi_pll_select(crtc, crtc_state))
9716 crtc->lowfreq_avail = false;
9721 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9723 struct intel_crtc_state *pipe_config)
9727 pipe_config->ddi_pll_sel = SKL_DPLL0;
9728 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9731 pipe_config->ddi_pll_sel = SKL_DPLL1;
9732 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9735 pipe_config->ddi_pll_sel = SKL_DPLL2;
9736 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9739 DRM_ERROR("Incorrect port type\n");
9743 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9745 struct intel_crtc_state *pipe_config)
9747 u32 temp, dpll_ctl1;
9749 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9750 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9752 switch (pipe_config->ddi_pll_sel) {
9755 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9756 * of the shared DPLL framework and thus needs to be read out
9759 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9760 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9763 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9766 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9769 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9774 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9776 struct intel_crtc_state *pipe_config)
9778 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9780 switch (pipe_config->ddi_pll_sel) {
9781 case PORT_CLK_SEL_WRPLL1:
9782 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9784 case PORT_CLK_SEL_WRPLL2:
9785 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9790 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9791 struct intel_crtc_state *pipe_config)
9793 struct drm_device *dev = crtc->base.dev;
9794 struct drm_i915_private *dev_priv = dev->dev_private;
9795 struct intel_shared_dpll *pll;
9799 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9801 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9803 if (IS_SKYLAKE(dev))
9804 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9805 else if (IS_BROXTON(dev))
9806 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9808 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9810 if (pipe_config->shared_dpll >= 0) {
9811 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9813 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9814 &pipe_config->dpll_hw_state));
9818 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9819 * DDI E. So just check whether this pipe is wired to DDI E and whether
9820 * the PCH transcoder is on.
9822 if (INTEL_INFO(dev)->gen < 9 &&
9823 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9824 pipe_config->has_pch_encoder = true;
9826 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9827 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9828 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9830 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9834 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9835 struct intel_crtc_state *pipe_config)
9837 struct drm_device *dev = crtc->base.dev;
9838 struct drm_i915_private *dev_priv = dev->dev_private;
9839 enum intel_display_power_domain pfit_domain;
9842 if (!intel_display_power_is_enabled(dev_priv,
9843 POWER_DOMAIN_PIPE(crtc->pipe)))
9846 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9847 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9849 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9850 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9851 enum pipe trans_edp_pipe;
9852 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9854 WARN(1, "unknown pipe linked to edp transcoder\n");
9855 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9856 case TRANS_DDI_EDP_INPUT_A_ON:
9857 trans_edp_pipe = PIPE_A;
9859 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9860 trans_edp_pipe = PIPE_B;
9862 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9863 trans_edp_pipe = PIPE_C;
9867 if (trans_edp_pipe == crtc->pipe)
9868 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9871 if (!intel_display_power_is_enabled(dev_priv,
9872 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9875 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9876 if (!(tmp & PIPECONF_ENABLE))
9879 haswell_get_ddi_port_state(crtc, pipe_config);
9881 intel_get_pipe_timings(crtc, pipe_config);
9883 if (INTEL_INFO(dev)->gen >= 9) {
9884 skl_init_scalers(dev, crtc, pipe_config);
9887 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9889 if (INTEL_INFO(dev)->gen >= 9) {
9890 pipe_config->scaler_state.scaler_id = -1;
9891 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9894 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9895 if (INTEL_INFO(dev)->gen == 9)
9896 skylake_get_pfit_config(crtc, pipe_config);
9897 else if (INTEL_INFO(dev)->gen < 9)
9898 ironlake_get_pfit_config(crtc, pipe_config);
9900 MISSING_CASE(INTEL_INFO(dev)->gen);
9903 if (IS_HASWELL(dev))
9904 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9905 (I915_READ(IPS_CTL) & IPS_ENABLE);
9907 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9908 pipe_config->pixel_multiplier =
9909 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9911 pipe_config->pixel_multiplier = 1;
9917 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9919 struct drm_device *dev = crtc->dev;
9920 struct drm_i915_private *dev_priv = dev->dev_private;
9921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9922 uint32_t cntl = 0, size = 0;
9925 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9926 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9927 unsigned int stride = roundup_pow_of_two(width) * 4;
9931 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9942 cntl |= CURSOR_ENABLE |
9943 CURSOR_GAMMA_ENABLE |
9944 CURSOR_FORMAT_ARGB |
9945 CURSOR_STRIDE(stride);
9947 size = (height << 12) | width;
9950 if (intel_crtc->cursor_cntl != 0 &&
9951 (intel_crtc->cursor_base != base ||
9952 intel_crtc->cursor_size != size ||
9953 intel_crtc->cursor_cntl != cntl)) {
9954 /* On these chipsets we can only modify the base/size/stride
9955 * whilst the cursor is disabled.
9957 I915_WRITE(_CURACNTR, 0);
9958 POSTING_READ(_CURACNTR);
9959 intel_crtc->cursor_cntl = 0;
9962 if (intel_crtc->cursor_base != base) {
9963 I915_WRITE(_CURABASE, base);
9964 intel_crtc->cursor_base = base;
9967 if (intel_crtc->cursor_size != size) {
9968 I915_WRITE(CURSIZE, size);
9969 intel_crtc->cursor_size = size;
9972 if (intel_crtc->cursor_cntl != cntl) {
9973 I915_WRITE(_CURACNTR, cntl);
9974 POSTING_READ(_CURACNTR);
9975 intel_crtc->cursor_cntl = cntl;
9979 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9981 struct drm_device *dev = crtc->dev;
9982 struct drm_i915_private *dev_priv = dev->dev_private;
9983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9984 int pipe = intel_crtc->pipe;
9989 cntl = MCURSOR_GAMMA_ENABLE;
9990 switch (intel_crtc->base.cursor->state->crtc_w) {
9992 cntl |= CURSOR_MODE_64_ARGB_AX;
9995 cntl |= CURSOR_MODE_128_ARGB_AX;
9998 cntl |= CURSOR_MODE_256_ARGB_AX;
10001 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10004 cntl |= pipe << 28; /* Connect to correct pipe */
10006 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10007 cntl |= CURSOR_PIPE_CSC_ENABLE;
10010 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10011 cntl |= CURSOR_ROTATE_180;
10013 if (intel_crtc->cursor_cntl != cntl) {
10014 I915_WRITE(CURCNTR(pipe), cntl);
10015 POSTING_READ(CURCNTR(pipe));
10016 intel_crtc->cursor_cntl = cntl;
10019 /* and commit changes on next vblank */
10020 I915_WRITE(CURBASE(pipe), base);
10021 POSTING_READ(CURBASE(pipe));
10023 intel_crtc->cursor_base = base;
10026 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10027 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10030 struct drm_device *dev = crtc->dev;
10031 struct drm_i915_private *dev_priv = dev->dev_private;
10032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10033 int pipe = intel_crtc->pipe;
10034 int x = crtc->cursor_x;
10035 int y = crtc->cursor_y;
10036 u32 base = 0, pos = 0;
10039 base = intel_crtc->cursor_addr;
10041 if (x >= intel_crtc->config->pipe_src_w)
10044 if (y >= intel_crtc->config->pipe_src_h)
10048 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
10051 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10054 pos |= x << CURSOR_X_SHIFT;
10057 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
10060 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10063 pos |= y << CURSOR_Y_SHIFT;
10065 if (base == 0 && intel_crtc->cursor_base == 0)
10068 I915_WRITE(CURPOS(pipe), pos);
10070 /* ILK+ do this automagically */
10071 if (HAS_GMCH_DISPLAY(dev) &&
10072 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10073 base += (intel_crtc->base.cursor->state->crtc_h *
10074 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
10077 if (IS_845G(dev) || IS_I865G(dev))
10078 i845_update_cursor(crtc, base);
10080 i9xx_update_cursor(crtc, base);
10083 static bool cursor_size_ok(struct drm_device *dev,
10084 uint32_t width, uint32_t height)
10086 if (width == 0 || height == 0)
10090 * 845g/865g are special in that they are only limited by
10091 * the width of their cursors, the height is arbitrary up to
10092 * the precision of the register. Everything else requires
10093 * square cursors, limited to a few power-of-two sizes.
10095 if (IS_845G(dev) || IS_I865G(dev)) {
10096 if ((width & 63) != 0)
10099 if (width > (IS_845G(dev) ? 64 : 512))
10105 switch (width | height) {
10120 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10121 u16 *blue, uint32_t start, uint32_t size)
10123 int end = (start + size > 256) ? 256 : start + size, i;
10124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10126 for (i = start; i < end; i++) {
10127 intel_crtc->lut_r[i] = red[i] >> 8;
10128 intel_crtc->lut_g[i] = green[i] >> 8;
10129 intel_crtc->lut_b[i] = blue[i] >> 8;
10132 intel_crtc_load_lut(crtc);
10135 /* VESA 640x480x72Hz mode to set on the pipe */
10136 static struct drm_display_mode load_detect_mode = {
10137 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10138 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10141 struct drm_framebuffer *
10142 __intel_framebuffer_create(struct drm_device *dev,
10143 struct drm_mode_fb_cmd2 *mode_cmd,
10144 struct drm_i915_gem_object *obj)
10146 struct intel_framebuffer *intel_fb;
10149 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10151 drm_gem_object_unreference(&obj->base);
10152 return ERR_PTR(-ENOMEM);
10155 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10159 return &intel_fb->base;
10161 drm_gem_object_unreference(&obj->base);
10164 return ERR_PTR(ret);
10167 static struct drm_framebuffer *
10168 intel_framebuffer_create(struct drm_device *dev,
10169 struct drm_mode_fb_cmd2 *mode_cmd,
10170 struct drm_i915_gem_object *obj)
10172 struct drm_framebuffer *fb;
10175 ret = i915_mutex_lock_interruptible(dev);
10177 return ERR_PTR(ret);
10178 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10179 mutex_unlock(&dev->struct_mutex);
10185 intel_framebuffer_pitch_for_width(int width, int bpp)
10187 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10188 return ALIGN(pitch, 64);
10192 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10194 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10195 return PAGE_ALIGN(pitch * mode->vdisplay);
10198 static struct drm_framebuffer *
10199 intel_framebuffer_create_for_mode(struct drm_device *dev,
10200 struct drm_display_mode *mode,
10201 int depth, int bpp)
10203 struct drm_i915_gem_object *obj;
10204 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10206 obj = i915_gem_alloc_object(dev,
10207 intel_framebuffer_size_for_mode(mode, bpp));
10209 return ERR_PTR(-ENOMEM);
10211 mode_cmd.width = mode->hdisplay;
10212 mode_cmd.height = mode->vdisplay;
10213 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10215 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10217 return intel_framebuffer_create(dev, &mode_cmd, obj);
10220 static struct drm_framebuffer *
10221 mode_fits_in_fbdev(struct drm_device *dev,
10222 struct drm_display_mode *mode)
10224 #ifdef CONFIG_DRM_I915_FBDEV
10225 struct drm_i915_private *dev_priv = dev->dev_private;
10226 struct drm_i915_gem_object *obj;
10227 struct drm_framebuffer *fb;
10229 if (!dev_priv->fbdev)
10232 if (!dev_priv->fbdev->fb)
10235 obj = dev_priv->fbdev->fb->obj;
10238 fb = &dev_priv->fbdev->fb->base;
10239 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10240 fb->bits_per_pixel))
10243 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10252 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10253 struct drm_crtc *crtc,
10254 struct drm_display_mode *mode,
10255 struct drm_framebuffer *fb,
10258 struct drm_plane_state *plane_state;
10259 int hdisplay, vdisplay;
10262 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10263 if (IS_ERR(plane_state))
10264 return PTR_ERR(plane_state);
10267 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10269 hdisplay = vdisplay = 0;
10271 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10274 drm_atomic_set_fb_for_plane(plane_state, fb);
10275 plane_state->crtc_x = 0;
10276 plane_state->crtc_y = 0;
10277 plane_state->crtc_w = hdisplay;
10278 plane_state->crtc_h = vdisplay;
10279 plane_state->src_x = x << 16;
10280 plane_state->src_y = y << 16;
10281 plane_state->src_w = hdisplay << 16;
10282 plane_state->src_h = vdisplay << 16;
10287 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10288 struct drm_display_mode *mode,
10289 struct intel_load_detect_pipe *old,
10290 struct drm_modeset_acquire_ctx *ctx)
10292 struct intel_crtc *intel_crtc;
10293 struct intel_encoder *intel_encoder =
10294 intel_attached_encoder(connector);
10295 struct drm_crtc *possible_crtc;
10296 struct drm_encoder *encoder = &intel_encoder->base;
10297 struct drm_crtc *crtc = NULL;
10298 struct drm_device *dev = encoder->dev;
10299 struct drm_framebuffer *fb;
10300 struct drm_mode_config *config = &dev->mode_config;
10301 struct drm_atomic_state *state = NULL;
10302 struct drm_connector_state *connector_state;
10303 struct intel_crtc_state *crtc_state;
10306 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10307 connector->base.id, connector->name,
10308 encoder->base.id, encoder->name);
10311 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10316 * Algorithm gets a little messy:
10318 * - if the connector already has an assigned crtc, use it (but make
10319 * sure it's on first)
10321 * - try to find the first unused crtc that can drive this connector,
10322 * and use that if we find one
10325 /* See if we already have a CRTC for this connector */
10326 if (encoder->crtc) {
10327 crtc = encoder->crtc;
10329 ret = drm_modeset_lock(&crtc->mutex, ctx);
10332 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10336 old->dpms_mode = connector->dpms;
10337 old->load_detect_temp = false;
10339 /* Make sure the crtc and connector are running */
10340 if (connector->dpms != DRM_MODE_DPMS_ON)
10341 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10346 /* Find an unused one (if possible) */
10347 for_each_crtc(dev, possible_crtc) {
10349 if (!(encoder->possible_crtcs & (1 << i)))
10351 if (possible_crtc->state->enable)
10354 crtc = possible_crtc;
10359 * If we didn't find an unused CRTC, don't use any.
10362 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10366 ret = drm_modeset_lock(&crtc->mutex, ctx);
10369 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10373 intel_crtc = to_intel_crtc(crtc);
10374 old->dpms_mode = connector->dpms;
10375 old->load_detect_temp = true;
10376 old->release_fb = NULL;
10378 state = drm_atomic_state_alloc(dev);
10382 state->acquire_ctx = ctx;
10384 connector_state = drm_atomic_get_connector_state(state, connector);
10385 if (IS_ERR(connector_state)) {
10386 ret = PTR_ERR(connector_state);
10390 connector_state->crtc = crtc;
10391 connector_state->best_encoder = &intel_encoder->base;
10393 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10394 if (IS_ERR(crtc_state)) {
10395 ret = PTR_ERR(crtc_state);
10399 crtc_state->base.active = crtc_state->base.enable = true;
10402 mode = &load_detect_mode;
10404 /* We need a framebuffer large enough to accommodate all accesses
10405 * that the plane may generate whilst we perform load detection.
10406 * We can not rely on the fbcon either being present (we get called
10407 * during its initialisation to detect all boot displays, or it may
10408 * not even exist) or that it is large enough to satisfy the
10411 fb = mode_fits_in_fbdev(dev, mode);
10413 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10414 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10415 old->release_fb = fb;
10417 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10419 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10423 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10427 drm_mode_copy(&crtc_state->base.mode, mode);
10429 if (drm_atomic_commit(state)) {
10430 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10431 if (old->release_fb)
10432 old->release_fb->funcs->destroy(old->release_fb);
10435 crtc->primary->crtc = crtc;
10437 /* let the connector get through one full cycle before testing */
10438 intel_wait_for_vblank(dev, intel_crtc->pipe);
10442 drm_atomic_state_free(state);
10445 if (ret == -EDEADLK) {
10446 drm_modeset_backoff(ctx);
10453 void intel_release_load_detect_pipe(struct drm_connector *connector,
10454 struct intel_load_detect_pipe *old,
10455 struct drm_modeset_acquire_ctx *ctx)
10457 struct drm_device *dev = connector->dev;
10458 struct intel_encoder *intel_encoder =
10459 intel_attached_encoder(connector);
10460 struct drm_encoder *encoder = &intel_encoder->base;
10461 struct drm_crtc *crtc = encoder->crtc;
10462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10463 struct drm_atomic_state *state;
10464 struct drm_connector_state *connector_state;
10465 struct intel_crtc_state *crtc_state;
10468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10469 connector->base.id, connector->name,
10470 encoder->base.id, encoder->name);
10472 if (old->load_detect_temp) {
10473 state = drm_atomic_state_alloc(dev);
10477 state->acquire_ctx = ctx;
10479 connector_state = drm_atomic_get_connector_state(state, connector);
10480 if (IS_ERR(connector_state))
10483 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10484 if (IS_ERR(crtc_state))
10487 connector_state->best_encoder = NULL;
10488 connector_state->crtc = NULL;
10490 crtc_state->base.enable = crtc_state->base.active = false;
10492 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10497 ret = drm_atomic_commit(state);
10501 if (old->release_fb) {
10502 drm_framebuffer_unregister_private(old->release_fb);
10503 drm_framebuffer_unreference(old->release_fb);
10509 /* Switch crtc and encoder back off if necessary */
10510 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10511 connector->funcs->dpms(connector, old->dpms_mode);
10515 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10516 drm_atomic_state_free(state);
10519 static int i9xx_pll_refclk(struct drm_device *dev,
10520 const struct intel_crtc_state *pipe_config)
10522 struct drm_i915_private *dev_priv = dev->dev_private;
10523 u32 dpll = pipe_config->dpll_hw_state.dpll;
10525 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10526 return dev_priv->vbt.lvds_ssc_freq;
10527 else if (HAS_PCH_SPLIT(dev))
10529 else if (!IS_GEN2(dev))
10535 /* Returns the clock of the currently programmed mode of the given pipe. */
10536 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10537 struct intel_crtc_state *pipe_config)
10539 struct drm_device *dev = crtc->base.dev;
10540 struct drm_i915_private *dev_priv = dev->dev_private;
10541 int pipe = pipe_config->cpu_transcoder;
10542 u32 dpll = pipe_config->dpll_hw_state.dpll;
10544 intel_clock_t clock;
10546 int refclk = i9xx_pll_refclk(dev, pipe_config);
10548 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10549 fp = pipe_config->dpll_hw_state.fp0;
10551 fp = pipe_config->dpll_hw_state.fp1;
10553 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10554 if (IS_PINEVIEW(dev)) {
10555 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10556 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10558 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10559 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10562 if (!IS_GEN2(dev)) {
10563 if (IS_PINEVIEW(dev))
10564 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10565 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10567 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10568 DPLL_FPA01_P1_POST_DIV_SHIFT);
10570 switch (dpll & DPLL_MODE_MASK) {
10571 case DPLLB_MODE_DAC_SERIAL:
10572 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10575 case DPLLB_MODE_LVDS:
10576 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10580 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10581 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10585 if (IS_PINEVIEW(dev))
10586 port_clock = pnv_calc_dpll_params(refclk, &clock);
10588 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10590 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10591 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10594 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10595 DPLL_FPA01_P1_POST_DIV_SHIFT);
10597 if (lvds & LVDS_CLKB_POWER_UP)
10602 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10605 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10606 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10608 if (dpll & PLL_P2_DIVIDE_BY_4)
10614 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10618 * This value includes pixel_multiplier. We will use
10619 * port_clock to compute adjusted_mode.crtc_clock in the
10620 * encoder's get_config() function.
10622 pipe_config->port_clock = port_clock;
10625 int intel_dotclock_calculate(int link_freq,
10626 const struct intel_link_m_n *m_n)
10629 * The calculation for the data clock is:
10630 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10631 * But we want to avoid losing precison if possible, so:
10632 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10634 * and the link clock is simpler:
10635 * link_clock = (m * link_clock) / n
10641 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10644 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10645 struct intel_crtc_state *pipe_config)
10647 struct drm_device *dev = crtc->base.dev;
10649 /* read out port_clock from the DPLL */
10650 i9xx_crtc_clock_get(crtc, pipe_config);
10653 * This value does not include pixel_multiplier.
10654 * We will check that port_clock and adjusted_mode.crtc_clock
10655 * agree once we know their relationship in the encoder's
10656 * get_config() function.
10658 pipe_config->base.adjusted_mode.crtc_clock =
10659 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10660 &pipe_config->fdi_m_n);
10663 /** Returns the currently programmed mode of the given pipe. */
10664 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10665 struct drm_crtc *crtc)
10667 struct drm_i915_private *dev_priv = dev->dev_private;
10668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10669 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10670 struct drm_display_mode *mode;
10671 struct intel_crtc_state pipe_config;
10672 int htot = I915_READ(HTOTAL(cpu_transcoder));
10673 int hsync = I915_READ(HSYNC(cpu_transcoder));
10674 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10675 int vsync = I915_READ(VSYNC(cpu_transcoder));
10676 enum pipe pipe = intel_crtc->pipe;
10678 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10683 * Construct a pipe_config sufficient for getting the clock info
10684 * back out of crtc_clock_get.
10686 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10687 * to use a real value here instead.
10689 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10690 pipe_config.pixel_multiplier = 1;
10691 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10692 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10693 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10694 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10696 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10697 mode->hdisplay = (htot & 0xffff) + 1;
10698 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10699 mode->hsync_start = (hsync & 0xffff) + 1;
10700 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10701 mode->vdisplay = (vtot & 0xffff) + 1;
10702 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10703 mode->vsync_start = (vsync & 0xffff) + 1;
10704 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10706 drm_mode_set_name(mode);
10711 void intel_mark_busy(struct drm_device *dev)
10713 struct drm_i915_private *dev_priv = dev->dev_private;
10715 if (dev_priv->mm.busy)
10718 intel_runtime_pm_get(dev_priv);
10719 i915_update_gfx_val(dev_priv);
10720 if (INTEL_INFO(dev)->gen >= 6)
10721 gen6_rps_busy(dev_priv);
10722 dev_priv->mm.busy = true;
10725 void intel_mark_idle(struct drm_device *dev)
10727 struct drm_i915_private *dev_priv = dev->dev_private;
10729 if (!dev_priv->mm.busy)
10732 dev_priv->mm.busy = false;
10734 if (INTEL_INFO(dev)->gen >= 6)
10735 gen6_rps_idle(dev->dev_private);
10737 intel_runtime_pm_put(dev_priv);
10740 static void intel_crtc_destroy(struct drm_crtc *crtc)
10742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10743 struct drm_device *dev = crtc->dev;
10744 struct intel_unpin_work *work;
10746 spin_lock_irq(&dev->event_lock);
10747 work = intel_crtc->unpin_work;
10748 intel_crtc->unpin_work = NULL;
10749 spin_unlock_irq(&dev->event_lock);
10752 cancel_work_sync(&work->work);
10756 drm_crtc_cleanup(crtc);
10761 static void intel_unpin_work_fn(struct work_struct *__work)
10763 struct intel_unpin_work *work =
10764 container_of(__work, struct intel_unpin_work, work);
10765 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10766 struct drm_device *dev = crtc->base.dev;
10767 struct drm_i915_private *dev_priv = dev->dev_private;
10768 struct drm_plane *primary = crtc->base.primary;
10770 mutex_lock(&dev->struct_mutex);
10771 intel_unpin_fb_obj(work->old_fb, primary->state);
10772 drm_gem_object_unreference(&work->pending_flip_obj->base);
10774 intel_fbc_update(dev_priv);
10776 if (work->flip_queued_req)
10777 i915_gem_request_assign(&work->flip_queued_req, NULL);
10778 mutex_unlock(&dev->struct_mutex);
10780 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10781 drm_framebuffer_unreference(work->old_fb);
10783 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10784 atomic_dec(&crtc->unpin_work_count);
10789 static void do_intel_finish_page_flip(struct drm_device *dev,
10790 struct drm_crtc *crtc)
10792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10793 struct intel_unpin_work *work;
10794 unsigned long flags;
10796 /* Ignore early vblank irqs */
10797 if (intel_crtc == NULL)
10801 * This is called both by irq handlers and the reset code (to complete
10802 * lost pageflips) so needs the full irqsave spinlocks.
10804 spin_lock_irqsave(&dev->event_lock, flags);
10805 work = intel_crtc->unpin_work;
10807 /* Ensure we don't miss a work->pending update ... */
10810 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10811 spin_unlock_irqrestore(&dev->event_lock, flags);
10815 page_flip_completed(intel_crtc);
10817 spin_unlock_irqrestore(&dev->event_lock, flags);
10820 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10822 struct drm_i915_private *dev_priv = dev->dev_private;
10823 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10825 do_intel_finish_page_flip(dev, crtc);
10828 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10830 struct drm_i915_private *dev_priv = dev->dev_private;
10831 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10833 do_intel_finish_page_flip(dev, crtc);
10836 /* Is 'a' after or equal to 'b'? */
10837 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10839 return !((a - b) & 0x80000000);
10842 static bool page_flip_finished(struct intel_crtc *crtc)
10844 struct drm_device *dev = crtc->base.dev;
10845 struct drm_i915_private *dev_priv = dev->dev_private;
10847 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10848 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10852 * The relevant registers doen't exist on pre-ctg.
10853 * As the flip done interrupt doesn't trigger for mmio
10854 * flips on gmch platforms, a flip count check isn't
10855 * really needed there. But since ctg has the registers,
10856 * include it in the check anyway.
10858 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10862 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10863 * used the same base address. In that case the mmio flip might
10864 * have completed, but the CS hasn't even executed the flip yet.
10866 * A flip count check isn't enough as the CS might have updated
10867 * the base address just after start of vblank, but before we
10868 * managed to process the interrupt. This means we'd complete the
10869 * CS flip too soon.
10871 * Combining both checks should get us a good enough result. It may
10872 * still happen that the CS flip has been executed, but has not
10873 * yet actually completed. But in case the base address is the same
10874 * anyway, we don't really care.
10876 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10877 crtc->unpin_work->gtt_offset &&
10878 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10879 crtc->unpin_work->flip_count);
10882 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct intel_crtc *intel_crtc =
10886 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10887 unsigned long flags;
10891 * This is called both by irq handlers and the reset code (to complete
10892 * lost pageflips) so needs the full irqsave spinlocks.
10894 * NB: An MMIO update of the plane base pointer will also
10895 * generate a page-flip completion irq, i.e. every modeset
10896 * is also accompanied by a spurious intel_prepare_page_flip().
10898 spin_lock_irqsave(&dev->event_lock, flags);
10899 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10900 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10901 spin_unlock_irqrestore(&dev->event_lock, flags);
10904 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10906 /* Ensure that the work item is consistent when activating it ... */
10908 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10909 /* and that it is marked active as soon as the irq could fire. */
10913 static int intel_gen2_queue_flip(struct drm_device *dev,
10914 struct drm_crtc *crtc,
10915 struct drm_framebuffer *fb,
10916 struct drm_i915_gem_object *obj,
10917 struct drm_i915_gem_request *req,
10920 struct intel_engine_cs *ring = req->ring;
10921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10925 ret = intel_ring_begin(req, 6);
10929 /* Can't queue multiple flips, so wait for the previous
10930 * one to finish before executing the next.
10932 if (intel_crtc->plane)
10933 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10935 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10936 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10937 intel_ring_emit(ring, MI_NOOP);
10938 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10939 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10940 intel_ring_emit(ring, fb->pitches[0]);
10941 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10942 intel_ring_emit(ring, 0); /* aux display base address, unused */
10944 intel_mark_page_flip_active(intel_crtc);
10948 static int intel_gen3_queue_flip(struct drm_device *dev,
10949 struct drm_crtc *crtc,
10950 struct drm_framebuffer *fb,
10951 struct drm_i915_gem_object *obj,
10952 struct drm_i915_gem_request *req,
10955 struct intel_engine_cs *ring = req->ring;
10956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10960 ret = intel_ring_begin(req, 6);
10964 if (intel_crtc->plane)
10965 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10967 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10968 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10969 intel_ring_emit(ring, MI_NOOP);
10970 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10971 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10972 intel_ring_emit(ring, fb->pitches[0]);
10973 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10974 intel_ring_emit(ring, MI_NOOP);
10976 intel_mark_page_flip_active(intel_crtc);
10980 static int intel_gen4_queue_flip(struct drm_device *dev,
10981 struct drm_crtc *crtc,
10982 struct drm_framebuffer *fb,
10983 struct drm_i915_gem_object *obj,
10984 struct drm_i915_gem_request *req,
10987 struct intel_engine_cs *ring = req->ring;
10988 struct drm_i915_private *dev_priv = dev->dev_private;
10989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10990 uint32_t pf, pipesrc;
10993 ret = intel_ring_begin(req, 4);
10997 /* i965+ uses the linear or tiled offsets from the
10998 * Display Registers (which do not change across a page-flip)
10999 * so we need only reprogram the base address.
11001 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11002 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11003 intel_ring_emit(ring, fb->pitches[0]);
11004 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11007 /* XXX Enabling the panel-fitter across page-flip is so far
11008 * untested on non-native modes, so ignore it for now.
11009 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11012 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11013 intel_ring_emit(ring, pf | pipesrc);
11015 intel_mark_page_flip_active(intel_crtc);
11019 static int intel_gen6_queue_flip(struct drm_device *dev,
11020 struct drm_crtc *crtc,
11021 struct drm_framebuffer *fb,
11022 struct drm_i915_gem_object *obj,
11023 struct drm_i915_gem_request *req,
11026 struct intel_engine_cs *ring = req->ring;
11027 struct drm_i915_private *dev_priv = dev->dev_private;
11028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11029 uint32_t pf, pipesrc;
11032 ret = intel_ring_begin(req, 4);
11036 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11037 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11038 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11039 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11041 /* Contrary to the suggestions in the documentation,
11042 * "Enable Panel Fitter" does not seem to be required when page
11043 * flipping with a non-native mode, and worse causes a normal
11045 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11048 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11049 intel_ring_emit(ring, pf | pipesrc);
11051 intel_mark_page_flip_active(intel_crtc);
11055 static int intel_gen7_queue_flip(struct drm_device *dev,
11056 struct drm_crtc *crtc,
11057 struct drm_framebuffer *fb,
11058 struct drm_i915_gem_object *obj,
11059 struct drm_i915_gem_request *req,
11062 struct intel_engine_cs *ring = req->ring;
11063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11064 uint32_t plane_bit = 0;
11067 switch (intel_crtc->plane) {
11069 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11072 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11075 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11078 WARN_ONCE(1, "unknown plane in flip command\n");
11083 if (ring->id == RCS) {
11086 * On Gen 8, SRM is now taking an extra dword to accommodate
11087 * 48bits addresses, and we need a NOOP for the batch size to
11095 * BSpec MI_DISPLAY_FLIP for IVB:
11096 * "The full packet must be contained within the same cache line."
11098 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11099 * cacheline, if we ever start emitting more commands before
11100 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11101 * then do the cacheline alignment, and finally emit the
11104 ret = intel_ring_cacheline_align(req);
11108 ret = intel_ring_begin(req, len);
11112 /* Unmask the flip-done completion message. Note that the bspec says that
11113 * we should do this for both the BCS and RCS, and that we must not unmask
11114 * more than one flip event at any time (or ensure that one flip message
11115 * can be sent by waiting for flip-done prior to queueing new flips).
11116 * Experimentation says that BCS works despite DERRMR masking all
11117 * flip-done completion events and that unmasking all planes at once
11118 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11119 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11121 if (ring->id == RCS) {
11122 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11123 intel_ring_emit(ring, DERRMR);
11124 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11125 DERRMR_PIPEB_PRI_FLIP_DONE |
11126 DERRMR_PIPEC_PRI_FLIP_DONE));
11128 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11129 MI_SRM_LRM_GLOBAL_GTT);
11131 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11132 MI_SRM_LRM_GLOBAL_GTT);
11133 intel_ring_emit(ring, DERRMR);
11134 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11135 if (IS_GEN8(dev)) {
11136 intel_ring_emit(ring, 0);
11137 intel_ring_emit(ring, MI_NOOP);
11141 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11142 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11143 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11144 intel_ring_emit(ring, (MI_NOOP));
11146 intel_mark_page_flip_active(intel_crtc);
11150 static bool use_mmio_flip(struct intel_engine_cs *ring,
11151 struct drm_i915_gem_object *obj)
11154 * This is not being used for older platforms, because
11155 * non-availability of flip done interrupt forces us to use
11156 * CS flips. Older platforms derive flip done using some clever
11157 * tricks involving the flip_pending status bits and vblank irqs.
11158 * So using MMIO flips there would disrupt this mechanism.
11164 if (INTEL_INFO(ring->dev)->gen < 5)
11167 if (i915.use_mmio_flip < 0)
11169 else if (i915.use_mmio_flip > 0)
11171 else if (i915.enable_execlists)
11174 return ring != i915_gem_request_get_ring(obj->last_write_req);
11177 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11179 struct drm_device *dev = intel_crtc->base.dev;
11180 struct drm_i915_private *dev_priv = dev->dev_private;
11181 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11182 const enum pipe pipe = intel_crtc->pipe;
11185 ctl = I915_READ(PLANE_CTL(pipe, 0));
11186 ctl &= ~PLANE_CTL_TILED_MASK;
11187 switch (fb->modifier[0]) {
11188 case DRM_FORMAT_MOD_NONE:
11190 case I915_FORMAT_MOD_X_TILED:
11191 ctl |= PLANE_CTL_TILED_X;
11193 case I915_FORMAT_MOD_Y_TILED:
11194 ctl |= PLANE_CTL_TILED_Y;
11196 case I915_FORMAT_MOD_Yf_TILED:
11197 ctl |= PLANE_CTL_TILED_YF;
11200 MISSING_CASE(fb->modifier[0]);
11204 * The stride is either expressed as a multiple of 64 bytes chunks for
11205 * linear buffers or in number of tiles for tiled buffers.
11207 stride = fb->pitches[0] /
11208 intel_fb_stride_alignment(dev, fb->modifier[0],
11212 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11213 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11215 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11216 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11218 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11219 POSTING_READ(PLANE_SURF(pipe, 0));
11222 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
11224 struct drm_device *dev = intel_crtc->base.dev;
11225 struct drm_i915_private *dev_priv = dev->dev_private;
11226 struct intel_framebuffer *intel_fb =
11227 to_intel_framebuffer(intel_crtc->base.primary->fb);
11228 struct drm_i915_gem_object *obj = intel_fb->obj;
11232 reg = DSPCNTR(intel_crtc->plane);
11233 dspcntr = I915_READ(reg);
11235 if (obj->tiling_mode != I915_TILING_NONE)
11236 dspcntr |= DISPPLANE_TILED;
11238 dspcntr &= ~DISPPLANE_TILED;
11240 I915_WRITE(reg, dspcntr);
11242 I915_WRITE(DSPSURF(intel_crtc->plane),
11243 intel_crtc->unpin_work->gtt_offset);
11244 POSTING_READ(DSPSURF(intel_crtc->plane));
11249 * XXX: This is the temporary way to update the plane registers until we get
11250 * around to using the usual plane update functions for MMIO flips
11252 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11254 struct drm_device *dev = intel_crtc->base.dev;
11255 u32 start_vbl_count;
11257 intel_mark_page_flip_active(intel_crtc);
11259 intel_pipe_update_start(intel_crtc, &start_vbl_count);
11261 if (INTEL_INFO(dev)->gen >= 9)
11262 skl_do_mmio_flip(intel_crtc);
11264 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11265 ilk_do_mmio_flip(intel_crtc);
11267 intel_pipe_update_end(intel_crtc, start_vbl_count);
11270 static void intel_mmio_flip_work_func(struct work_struct *work)
11272 struct intel_mmio_flip *mmio_flip =
11273 container_of(work, struct intel_mmio_flip, work);
11275 if (mmio_flip->req)
11276 WARN_ON(__i915_wait_request(mmio_flip->req,
11277 mmio_flip->crtc->reset_counter,
11279 &mmio_flip->i915->rps.mmioflips));
11281 intel_do_mmio_flip(mmio_flip->crtc);
11283 i915_gem_request_unreference__unlocked(mmio_flip->req);
11287 static int intel_queue_mmio_flip(struct drm_device *dev,
11288 struct drm_crtc *crtc,
11289 struct drm_framebuffer *fb,
11290 struct drm_i915_gem_object *obj,
11291 struct intel_engine_cs *ring,
11294 struct intel_mmio_flip *mmio_flip;
11296 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11297 if (mmio_flip == NULL)
11300 mmio_flip->i915 = to_i915(dev);
11301 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11302 mmio_flip->crtc = to_intel_crtc(crtc);
11304 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11305 schedule_work(&mmio_flip->work);
11310 static int intel_default_queue_flip(struct drm_device *dev,
11311 struct drm_crtc *crtc,
11312 struct drm_framebuffer *fb,
11313 struct drm_i915_gem_object *obj,
11314 struct drm_i915_gem_request *req,
11320 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11321 struct drm_crtc *crtc)
11323 struct drm_i915_private *dev_priv = dev->dev_private;
11324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11325 struct intel_unpin_work *work = intel_crtc->unpin_work;
11328 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11331 if (!work->enable_stall_check)
11334 if (work->flip_ready_vblank == 0) {
11335 if (work->flip_queued_req &&
11336 !i915_gem_request_completed(work->flip_queued_req, true))
11339 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11342 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11345 /* Potential stall - if we see that the flip has happened,
11346 * assume a missed interrupt. */
11347 if (INTEL_INFO(dev)->gen >= 4)
11348 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11350 addr = I915_READ(DSPADDR(intel_crtc->plane));
11352 /* There is a potential issue here with a false positive after a flip
11353 * to the same address. We could address this by checking for a
11354 * non-incrementing frame counter.
11356 return addr == work->gtt_offset;
11359 void intel_check_page_flip(struct drm_device *dev, int pipe)
11361 struct drm_i915_private *dev_priv = dev->dev_private;
11362 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11364 struct intel_unpin_work *work;
11366 WARN_ON(!in_interrupt());
11371 spin_lock(&dev->event_lock);
11372 work = intel_crtc->unpin_work;
11373 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11374 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11375 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11376 page_flip_completed(intel_crtc);
11379 if (work != NULL &&
11380 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11381 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11382 spin_unlock(&dev->event_lock);
11385 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11386 struct drm_framebuffer *fb,
11387 struct drm_pending_vblank_event *event,
11388 uint32_t page_flip_flags)
11390 struct drm_device *dev = crtc->dev;
11391 struct drm_i915_private *dev_priv = dev->dev_private;
11392 struct drm_framebuffer *old_fb = crtc->primary->fb;
11393 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11395 struct drm_plane *primary = crtc->primary;
11396 enum pipe pipe = intel_crtc->pipe;
11397 struct intel_unpin_work *work;
11398 struct intel_engine_cs *ring;
11400 struct drm_i915_gem_request *request = NULL;
11404 * drm_mode_page_flip_ioctl() should already catch this, but double
11405 * check to be safe. In the future we may enable pageflipping from
11406 * a disabled primary plane.
11408 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11411 /* Can't change pixel format via MI display flips. */
11412 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11416 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11417 * Note that pitch changes could also affect these register.
11419 if (INTEL_INFO(dev)->gen > 3 &&
11420 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11421 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11424 if (i915_terminally_wedged(&dev_priv->gpu_error))
11427 work = kzalloc(sizeof(*work), GFP_KERNEL);
11431 work->event = event;
11433 work->old_fb = old_fb;
11434 INIT_WORK(&work->work, intel_unpin_work_fn);
11436 ret = drm_crtc_vblank_get(crtc);
11440 /* We borrow the event spin lock for protecting unpin_work */
11441 spin_lock_irq(&dev->event_lock);
11442 if (intel_crtc->unpin_work) {
11443 /* Before declaring the flip queue wedged, check if
11444 * the hardware completed the operation behind our backs.
11446 if (__intel_pageflip_stall_check(dev, crtc)) {
11447 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11448 page_flip_completed(intel_crtc);
11450 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11451 spin_unlock_irq(&dev->event_lock);
11453 drm_crtc_vblank_put(crtc);
11458 intel_crtc->unpin_work = work;
11459 spin_unlock_irq(&dev->event_lock);
11461 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11462 flush_workqueue(dev_priv->wq);
11464 /* Reference the objects for the scheduled work. */
11465 drm_framebuffer_reference(work->old_fb);
11466 drm_gem_object_reference(&obj->base);
11468 crtc->primary->fb = fb;
11469 update_state_fb(crtc->primary);
11471 work->pending_flip_obj = obj;
11473 ret = i915_mutex_lock_interruptible(dev);
11477 atomic_inc(&intel_crtc->unpin_work_count);
11478 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11480 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11481 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
11483 if (IS_VALLEYVIEW(dev)) {
11484 ring = &dev_priv->ring[BCS];
11485 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11486 /* vlv: DISPLAY_FLIP fails to change tiling */
11488 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11489 ring = &dev_priv->ring[BCS];
11490 } else if (INTEL_INFO(dev)->gen >= 7) {
11491 ring = i915_gem_request_get_ring(obj->last_write_req);
11492 if (ring == NULL || ring->id != RCS)
11493 ring = &dev_priv->ring[BCS];
11495 ring = &dev_priv->ring[RCS];
11498 mmio_flip = use_mmio_flip(ring, obj);
11500 /* When using CS flips, we want to emit semaphores between rings.
11501 * However, when using mmio flips we will create a task to do the
11502 * synchronisation, so all we want here is to pin the framebuffer
11503 * into the display plane and skip any waits.
11505 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11506 crtc->primary->state,
11507 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11509 goto cleanup_pending;
11511 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11512 + intel_crtc->dspaddr_offset;
11515 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11518 goto cleanup_unpin;
11520 i915_gem_request_assign(&work->flip_queued_req,
11521 obj->last_write_req);
11524 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11526 goto cleanup_unpin;
11529 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11532 goto cleanup_unpin;
11534 i915_gem_request_assign(&work->flip_queued_req, request);
11538 i915_add_request_no_flush(request);
11540 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11541 work->enable_stall_check = true;
11543 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11544 to_intel_plane(primary)->frontbuffer_bit);
11545 mutex_unlock(&dev->struct_mutex);
11547 intel_fbc_disable(dev_priv);
11548 intel_frontbuffer_flip_prepare(dev,
11549 to_intel_plane(primary)->frontbuffer_bit);
11551 trace_i915_flip_request(intel_crtc->plane, obj);
11556 intel_unpin_fb_obj(fb, crtc->primary->state);
11559 i915_gem_request_cancel(request);
11560 atomic_dec(&intel_crtc->unpin_work_count);
11561 mutex_unlock(&dev->struct_mutex);
11563 crtc->primary->fb = old_fb;
11564 update_state_fb(crtc->primary);
11566 drm_gem_object_unreference_unlocked(&obj->base);
11567 drm_framebuffer_unreference(work->old_fb);
11569 spin_lock_irq(&dev->event_lock);
11570 intel_crtc->unpin_work = NULL;
11571 spin_unlock_irq(&dev->event_lock);
11573 drm_crtc_vblank_put(crtc);
11578 struct drm_atomic_state *state;
11579 struct drm_plane_state *plane_state;
11582 state = drm_atomic_state_alloc(dev);
11585 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11588 plane_state = drm_atomic_get_plane_state(state, primary);
11589 ret = PTR_ERR_OR_ZERO(plane_state);
11591 drm_atomic_set_fb_for_plane(plane_state, fb);
11593 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11595 ret = drm_atomic_commit(state);
11598 if (ret == -EDEADLK) {
11599 drm_modeset_backoff(state->acquire_ctx);
11600 drm_atomic_state_clear(state);
11605 drm_atomic_state_free(state);
11607 if (ret == 0 && event) {
11608 spin_lock_irq(&dev->event_lock);
11609 drm_send_vblank_event(dev, pipe, event);
11610 spin_unlock_irq(&dev->event_lock);
11618 * intel_wm_need_update - Check whether watermarks need updating
11619 * @plane: drm plane
11620 * @state: new plane state
11622 * Check current plane state versus the new one to determine whether
11623 * watermarks need to be recalculated.
11625 * Returns true or false.
11627 static bool intel_wm_need_update(struct drm_plane *plane,
11628 struct drm_plane_state *state)
11630 /* Update watermarks on tiling changes. */
11631 if (!plane->state->fb || !state->fb ||
11632 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11633 plane->state->rotation != state->rotation)
11636 if (plane->state->crtc_w != state->crtc_w)
11642 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11643 struct drm_plane_state *plane_state)
11645 struct drm_crtc *crtc = crtc_state->crtc;
11646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11647 struct drm_plane *plane = plane_state->plane;
11648 struct drm_device *dev = crtc->dev;
11649 struct drm_i915_private *dev_priv = dev->dev_private;
11650 struct intel_plane_state *old_plane_state =
11651 to_intel_plane_state(plane->state);
11652 int idx = intel_crtc->base.base.id, ret;
11653 int i = drm_plane_index(plane);
11654 bool mode_changed = needs_modeset(crtc_state);
11655 bool was_crtc_enabled = crtc->state->active;
11656 bool is_crtc_enabled = crtc_state->active;
11658 bool turn_off, turn_on, visible, was_visible;
11659 struct drm_framebuffer *fb = plane_state->fb;
11661 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11662 plane->type != DRM_PLANE_TYPE_CURSOR) {
11663 ret = skl_update_scaler_plane(
11664 to_intel_crtc_state(crtc_state),
11665 to_intel_plane_state(plane_state));
11671 * Disabling a plane is always okay; we just need to update
11672 * fb tracking in a special way since cleanup_fb() won't
11673 * get called by the plane helpers.
11675 if (old_plane_state->base.fb && !fb)
11676 intel_crtc->atomic.disabled_planes |= 1 << i;
11678 was_visible = old_plane_state->visible;
11679 visible = to_intel_plane_state(plane_state)->visible;
11681 if (!was_crtc_enabled && WARN_ON(was_visible))
11682 was_visible = false;
11684 if (!is_crtc_enabled && WARN_ON(visible))
11687 if (!was_visible && !visible)
11690 turn_off = was_visible && (!visible || mode_changed);
11691 turn_on = visible && (!was_visible || mode_changed);
11693 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11694 plane->base.id, fb ? fb->base.id : -1);
11696 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11697 plane->base.id, was_visible, visible,
11698 turn_off, turn_on, mode_changed);
11701 intel_crtc->atomic.update_wm_pre = true;
11702 /* must disable cxsr around plane enable/disable */
11703 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11704 intel_crtc->atomic.disable_cxsr = true;
11705 /* to potentially re-enable cxsr */
11706 intel_crtc->atomic.wait_vblank = true;
11707 intel_crtc->atomic.update_wm_post = true;
11709 } else if (turn_off) {
11710 intel_crtc->atomic.update_wm_post = true;
11711 /* must disable cxsr around plane enable/disable */
11712 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11713 if (is_crtc_enabled)
11714 intel_crtc->atomic.wait_vblank = true;
11715 intel_crtc->atomic.disable_cxsr = true;
11717 } else if (intel_wm_need_update(plane, plane_state)) {
11718 intel_crtc->atomic.update_wm_pre = true;
11722 intel_crtc->atomic.fb_bits |=
11723 to_intel_plane(plane)->frontbuffer_bit;
11725 switch (plane->type) {
11726 case DRM_PLANE_TYPE_PRIMARY:
11727 intel_crtc->atomic.wait_for_flips = true;
11728 intel_crtc->atomic.pre_disable_primary = turn_off;
11729 intel_crtc->atomic.post_enable_primary = turn_on;
11733 * FIXME: Actually if we will still have any other
11734 * plane enabled on the pipe we could let IPS enabled
11735 * still, but for now lets consider that when we make
11736 * primary invisible by setting DSPCNTR to 0 on
11737 * update_primary_plane function IPS needs to be
11740 intel_crtc->atomic.disable_ips = true;
11742 intel_crtc->atomic.disable_fbc = true;
11746 * FBC does not work on some platforms for rotated
11747 * planes, so disable it when rotation is not 0 and
11748 * update it when rotation is set back to 0.
11750 * FIXME: This is redundant with the fbc update done in
11751 * the primary plane enable function except that that
11752 * one is done too late. We eventually need to unify
11757 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11758 dev_priv->fbc.crtc == intel_crtc &&
11759 plane_state->rotation != BIT(DRM_ROTATE_0))
11760 intel_crtc->atomic.disable_fbc = true;
11763 * BDW signals flip done immediately if the plane
11764 * is disabled, even if the plane enable is already
11765 * armed to occur at the next vblank :(
11767 if (turn_on && IS_BROADWELL(dev))
11768 intel_crtc->atomic.wait_vblank = true;
11770 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11772 case DRM_PLANE_TYPE_CURSOR:
11774 case DRM_PLANE_TYPE_OVERLAY:
11775 if (turn_off && !mode_changed) {
11776 intel_crtc->atomic.wait_vblank = true;
11777 intel_crtc->atomic.update_sprite_watermarks |=
11784 static bool encoders_cloneable(const struct intel_encoder *a,
11785 const struct intel_encoder *b)
11787 /* masks could be asymmetric, so check both ways */
11788 return a == b || (a->cloneable & (1 << b->type) &&
11789 b->cloneable & (1 << a->type));
11792 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11793 struct intel_crtc *crtc,
11794 struct intel_encoder *encoder)
11796 struct intel_encoder *source_encoder;
11797 struct drm_connector *connector;
11798 struct drm_connector_state *connector_state;
11801 for_each_connector_in_state(state, connector, connector_state, i) {
11802 if (connector_state->crtc != &crtc->base)
11806 to_intel_encoder(connector_state->best_encoder);
11807 if (!encoders_cloneable(encoder, source_encoder))
11814 static bool check_encoder_cloning(struct drm_atomic_state *state,
11815 struct intel_crtc *crtc)
11817 struct intel_encoder *encoder;
11818 struct drm_connector *connector;
11819 struct drm_connector_state *connector_state;
11822 for_each_connector_in_state(state, connector, connector_state, i) {
11823 if (connector_state->crtc != &crtc->base)
11826 encoder = to_intel_encoder(connector_state->best_encoder);
11827 if (!check_single_encoder_cloning(state, crtc, encoder))
11834 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11835 struct drm_crtc_state *crtc_state)
11837 struct drm_device *dev = crtc->dev;
11838 struct drm_i915_private *dev_priv = dev->dev_private;
11839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11840 struct intel_crtc_state *pipe_config =
11841 to_intel_crtc_state(crtc_state);
11842 struct drm_atomic_state *state = crtc_state->state;
11843 int ret, idx = crtc->base.id;
11844 bool mode_changed = needs_modeset(crtc_state);
11846 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11847 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11851 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11852 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11853 idx, crtc->state->active, intel_crtc->active);
11855 if (mode_changed && !crtc_state->active)
11856 intel_crtc->atomic.update_wm_post = true;
11858 if (mode_changed && crtc_state->enable &&
11859 dev_priv->display.crtc_compute_clock &&
11860 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11861 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11868 if (INTEL_INFO(dev)->gen >= 9) {
11870 ret = skl_update_scaler_crtc(pipe_config);
11873 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11880 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11881 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11882 .load_lut = intel_crtc_load_lut,
11883 .atomic_begin = intel_begin_crtc_commit,
11884 .atomic_flush = intel_finish_crtc_commit,
11885 .atomic_check = intel_crtc_atomic_check,
11888 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11890 struct intel_connector *connector;
11892 for_each_intel_connector(dev, connector) {
11893 if (connector->base.encoder) {
11894 connector->base.state->best_encoder =
11895 connector->base.encoder;
11896 connector->base.state->crtc =
11897 connector->base.encoder->crtc;
11899 connector->base.state->best_encoder = NULL;
11900 connector->base.state->crtc = NULL;
11906 connected_sink_compute_bpp(struct intel_connector *connector,
11907 struct intel_crtc_state *pipe_config)
11909 int bpp = pipe_config->pipe_bpp;
11911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11912 connector->base.base.id,
11913 connector->base.name);
11915 /* Don't use an invalid EDID bpc value */
11916 if (connector->base.display_info.bpc &&
11917 connector->base.display_info.bpc * 3 < bpp) {
11918 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11919 bpp, connector->base.display_info.bpc*3);
11920 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11923 /* Clamp bpp to 8 on screens without EDID 1.4 */
11924 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11925 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11927 pipe_config->pipe_bpp = 24;
11932 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11933 struct intel_crtc_state *pipe_config)
11935 struct drm_device *dev = crtc->base.dev;
11936 struct drm_atomic_state *state;
11937 struct drm_connector *connector;
11938 struct drm_connector_state *connector_state;
11941 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11943 else if (INTEL_INFO(dev)->gen >= 5)
11949 pipe_config->pipe_bpp = bpp;
11951 state = pipe_config->base.state;
11953 /* Clamp display bpp to EDID value */
11954 for_each_connector_in_state(state, connector, connector_state, i) {
11955 if (connector_state->crtc != &crtc->base)
11958 connected_sink_compute_bpp(to_intel_connector(connector),
11965 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11967 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11968 "type: 0x%x flags: 0x%x\n",
11970 mode->crtc_hdisplay, mode->crtc_hsync_start,
11971 mode->crtc_hsync_end, mode->crtc_htotal,
11972 mode->crtc_vdisplay, mode->crtc_vsync_start,
11973 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11976 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11977 struct intel_crtc_state *pipe_config,
11978 const char *context)
11980 struct drm_device *dev = crtc->base.dev;
11981 struct drm_plane *plane;
11982 struct intel_plane *intel_plane;
11983 struct intel_plane_state *state;
11984 struct drm_framebuffer *fb;
11986 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11987 context, pipe_config, pipe_name(crtc->pipe));
11989 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11990 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11991 pipe_config->pipe_bpp, pipe_config->dither);
11992 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11993 pipe_config->has_pch_encoder,
11994 pipe_config->fdi_lanes,
11995 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11996 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11997 pipe_config->fdi_m_n.tu);
11998 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11999 pipe_config->has_dp_encoder,
12000 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12001 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12002 pipe_config->dp_m_n.tu);
12004 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12005 pipe_config->has_dp_encoder,
12006 pipe_config->dp_m2_n2.gmch_m,
12007 pipe_config->dp_m2_n2.gmch_n,
12008 pipe_config->dp_m2_n2.link_m,
12009 pipe_config->dp_m2_n2.link_n,
12010 pipe_config->dp_m2_n2.tu);
12012 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12013 pipe_config->has_audio,
12014 pipe_config->has_infoframe);
12016 DRM_DEBUG_KMS("requested mode:\n");
12017 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12018 DRM_DEBUG_KMS("adjusted mode:\n");
12019 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12020 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12021 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12022 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12023 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12024 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12026 pipe_config->scaler_state.scaler_users,
12027 pipe_config->scaler_state.scaler_id);
12028 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12029 pipe_config->gmch_pfit.control,
12030 pipe_config->gmch_pfit.pgm_ratios,
12031 pipe_config->gmch_pfit.lvds_border_bits);
12032 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12033 pipe_config->pch_pfit.pos,
12034 pipe_config->pch_pfit.size,
12035 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12036 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12037 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12039 if (IS_BROXTON(dev)) {
12040 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12041 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12042 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12043 pipe_config->ddi_pll_sel,
12044 pipe_config->dpll_hw_state.ebb0,
12045 pipe_config->dpll_hw_state.ebb4,
12046 pipe_config->dpll_hw_state.pll0,
12047 pipe_config->dpll_hw_state.pll1,
12048 pipe_config->dpll_hw_state.pll2,
12049 pipe_config->dpll_hw_state.pll3,
12050 pipe_config->dpll_hw_state.pll6,
12051 pipe_config->dpll_hw_state.pll8,
12052 pipe_config->dpll_hw_state.pll9,
12053 pipe_config->dpll_hw_state.pll10,
12054 pipe_config->dpll_hw_state.pcsdw12);
12055 } else if (IS_SKYLAKE(dev)) {
12056 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12057 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12058 pipe_config->ddi_pll_sel,
12059 pipe_config->dpll_hw_state.ctrl1,
12060 pipe_config->dpll_hw_state.cfgcr1,
12061 pipe_config->dpll_hw_state.cfgcr2);
12062 } else if (HAS_DDI(dev)) {
12063 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12064 pipe_config->ddi_pll_sel,
12065 pipe_config->dpll_hw_state.wrpll);
12067 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12068 "fp0: 0x%x, fp1: 0x%x\n",
12069 pipe_config->dpll_hw_state.dpll,
12070 pipe_config->dpll_hw_state.dpll_md,
12071 pipe_config->dpll_hw_state.fp0,
12072 pipe_config->dpll_hw_state.fp1);
12075 DRM_DEBUG_KMS("planes on this crtc\n");
12076 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12077 intel_plane = to_intel_plane(plane);
12078 if (intel_plane->pipe != crtc->pipe)
12081 state = to_intel_plane_state(plane->state);
12082 fb = state->base.fb;
12084 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12085 "disabled, scaler_id = %d\n",
12086 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12087 plane->base.id, intel_plane->pipe,
12088 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12089 drm_plane_index(plane), state->scaler_id);
12093 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12094 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12095 plane->base.id, intel_plane->pipe,
12096 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12097 drm_plane_index(plane));
12098 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12099 fb->base.id, fb->width, fb->height, fb->pixel_format);
12100 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12102 state->src.x1 >> 16, state->src.y1 >> 16,
12103 drm_rect_width(&state->src) >> 16,
12104 drm_rect_height(&state->src) >> 16,
12105 state->dst.x1, state->dst.y1,
12106 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12110 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12112 struct drm_device *dev = state->dev;
12113 struct intel_encoder *encoder;
12114 struct drm_connector *connector;
12115 struct drm_connector_state *connector_state;
12116 unsigned int used_ports = 0;
12120 * Walk the connector list instead of the encoder
12121 * list to detect the problem on ddi platforms
12122 * where there's just one encoder per digital port.
12124 for_each_connector_in_state(state, connector, connector_state, i) {
12125 if (!connector_state->best_encoder)
12128 encoder = to_intel_encoder(connector_state->best_encoder);
12130 WARN_ON(!connector_state->crtc);
12132 switch (encoder->type) {
12133 unsigned int port_mask;
12134 case INTEL_OUTPUT_UNKNOWN:
12135 if (WARN_ON(!HAS_DDI(dev)))
12137 case INTEL_OUTPUT_DISPLAYPORT:
12138 case INTEL_OUTPUT_HDMI:
12139 case INTEL_OUTPUT_EDP:
12140 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12142 /* the same port mustn't appear more than once */
12143 if (used_ports & port_mask)
12146 used_ports |= port_mask;
12156 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12158 struct drm_crtc_state tmp_state;
12159 struct intel_crtc_scaler_state scaler_state;
12160 struct intel_dpll_hw_state dpll_hw_state;
12161 enum intel_dpll_id shared_dpll;
12162 uint32_t ddi_pll_sel;
12164 /* FIXME: before the switch to atomic started, a new pipe_config was
12165 * kzalloc'd. Code that depends on any field being zero should be
12166 * fixed, so that the crtc_state can be safely duplicated. For now,
12167 * only fields that are know to not cause problems are preserved. */
12169 tmp_state = crtc_state->base;
12170 scaler_state = crtc_state->scaler_state;
12171 shared_dpll = crtc_state->shared_dpll;
12172 dpll_hw_state = crtc_state->dpll_hw_state;
12173 ddi_pll_sel = crtc_state->ddi_pll_sel;
12175 memset(crtc_state, 0, sizeof *crtc_state);
12177 crtc_state->base = tmp_state;
12178 crtc_state->scaler_state = scaler_state;
12179 crtc_state->shared_dpll = shared_dpll;
12180 crtc_state->dpll_hw_state = dpll_hw_state;
12181 crtc_state->ddi_pll_sel = ddi_pll_sel;
12185 intel_modeset_pipe_config(struct drm_crtc *crtc,
12186 struct intel_crtc_state *pipe_config)
12188 struct drm_atomic_state *state = pipe_config->base.state;
12189 struct intel_encoder *encoder;
12190 struct drm_connector *connector;
12191 struct drm_connector_state *connector_state;
12192 int base_bpp, ret = -EINVAL;
12196 clear_intel_crtc_state(pipe_config);
12198 pipe_config->cpu_transcoder =
12199 (enum transcoder) to_intel_crtc(crtc)->pipe;
12202 * Sanitize sync polarity flags based on requested ones. If neither
12203 * positive or negative polarity is requested, treat this as meaning
12204 * negative polarity.
12206 if (!(pipe_config->base.adjusted_mode.flags &
12207 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12208 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12210 if (!(pipe_config->base.adjusted_mode.flags &
12211 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12212 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12214 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12215 * plane pixel format and any sink constraints into account. Returns the
12216 * source plane bpp so that dithering can be selected on mismatches
12217 * after encoders and crtc also have had their say. */
12218 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12224 * Determine the real pipe dimensions. Note that stereo modes can
12225 * increase the actual pipe size due to the frame doubling and
12226 * insertion of additional space for blanks between the frame. This
12227 * is stored in the crtc timings. We use the requested mode to do this
12228 * computation to clearly distinguish it from the adjusted mode, which
12229 * can be changed by the connectors in the below retry loop.
12231 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12232 &pipe_config->pipe_src_w,
12233 &pipe_config->pipe_src_h);
12236 /* Ensure the port clock defaults are reset when retrying. */
12237 pipe_config->port_clock = 0;
12238 pipe_config->pixel_multiplier = 1;
12240 /* Fill in default crtc timings, allow encoders to overwrite them. */
12241 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12242 CRTC_STEREO_DOUBLE);
12244 /* Pass our mode to the connectors and the CRTC to give them a chance to
12245 * adjust it according to limitations or connector properties, and also
12246 * a chance to reject the mode entirely.
12248 for_each_connector_in_state(state, connector, connector_state, i) {
12249 if (connector_state->crtc != crtc)
12252 encoder = to_intel_encoder(connector_state->best_encoder);
12254 if (!(encoder->compute_config(encoder, pipe_config))) {
12255 DRM_DEBUG_KMS("Encoder config failure\n");
12260 /* Set default port clock if not overwritten by the encoder. Needs to be
12261 * done afterwards in case the encoder adjusts the mode. */
12262 if (!pipe_config->port_clock)
12263 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12264 * pipe_config->pixel_multiplier;
12266 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12268 DRM_DEBUG_KMS("CRTC fixup failed\n");
12272 if (ret == RETRY) {
12273 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12278 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12280 goto encoder_retry;
12283 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
12284 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
12285 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12291 static bool intel_crtc_in_use(struct drm_crtc *crtc)
12293 struct drm_encoder *encoder;
12294 struct drm_device *dev = crtc->dev;
12296 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12297 if (encoder->crtc == crtc)
12304 intel_modeset_update_state(struct drm_atomic_state *state)
12306 struct drm_device *dev = state->dev;
12307 struct intel_encoder *intel_encoder;
12308 struct drm_crtc *crtc;
12309 struct drm_crtc_state *crtc_state;
12310 struct drm_connector *connector;
12313 intel_shared_dpll_commit(state);
12315 for_each_intel_encoder(dev, intel_encoder) {
12316 if (!intel_encoder->base.crtc)
12319 crtc = intel_encoder->base.crtc;
12320 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12321 if (!crtc_state || !needs_modeset(crtc->state))
12324 intel_encoder->connectors_active = false;
12327 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12329 /* Double check state. */
12330 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12331 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
12333 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12335 /* Update hwmode for vblank functions */
12336 if (crtc->state->active)
12337 crtc->hwmode = crtc->state->adjusted_mode;
12339 crtc->hwmode.crtc_clock = 0;
12342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12343 if (!connector->encoder || !connector->encoder->crtc)
12346 crtc = connector->encoder->crtc;
12347 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12348 if (!crtc_state || !needs_modeset(crtc->state))
12351 if (crtc->state->active) {
12352 struct drm_property *dpms_property =
12353 dev->mode_config.dpms_property;
12355 connector->dpms = DRM_MODE_DPMS_ON;
12356 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
12358 intel_encoder = to_intel_encoder(connector->encoder);
12359 intel_encoder->connectors_active = true;
12361 connector->dpms = DRM_MODE_DPMS_OFF;
12365 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12369 if (clock1 == clock2)
12372 if (!clock1 || !clock2)
12375 diff = abs(clock1 - clock2);
12377 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12383 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12384 list_for_each_entry((intel_crtc), \
12385 &(dev)->mode_config.crtc_list, \
12387 if (mask & (1 <<(intel_crtc)->pipe))
12391 intel_compare_m_n(unsigned int m, unsigned int n,
12392 unsigned int m2, unsigned int n2,
12395 if (m == m2 && n == n2)
12398 if (exact || !m || !n || !m2 || !n2)
12401 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12408 } else if (m < m2) {
12415 return m == m2 && n == n2;
12419 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12420 struct intel_link_m_n *m2_n2,
12423 if (m_n->tu == m2_n2->tu &&
12424 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12425 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12426 intel_compare_m_n(m_n->link_m, m_n->link_n,
12427 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12438 intel_pipe_config_compare(struct drm_device *dev,
12439 struct intel_crtc_state *current_config,
12440 struct intel_crtc_state *pipe_config,
12445 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12448 DRM_ERROR(fmt, ##__VA_ARGS__); \
12450 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12453 #define PIPE_CONF_CHECK_X(name) \
12454 if (current_config->name != pipe_config->name) { \
12455 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12456 "(expected 0x%08x, found 0x%08x)\n", \
12457 current_config->name, \
12458 pipe_config->name); \
12462 #define PIPE_CONF_CHECK_I(name) \
12463 if (current_config->name != pipe_config->name) { \
12464 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12465 "(expected %i, found %i)\n", \
12466 current_config->name, \
12467 pipe_config->name); \
12471 #define PIPE_CONF_CHECK_M_N(name) \
12472 if (!intel_compare_link_m_n(¤t_config->name, \
12473 &pipe_config->name,\
12475 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12476 "(expected tu %i gmch %i/%i link %i/%i, " \
12477 "found tu %i, gmch %i/%i link %i/%i)\n", \
12478 current_config->name.tu, \
12479 current_config->name.gmch_m, \
12480 current_config->name.gmch_n, \
12481 current_config->name.link_m, \
12482 current_config->name.link_n, \
12483 pipe_config->name.tu, \
12484 pipe_config->name.gmch_m, \
12485 pipe_config->name.gmch_n, \
12486 pipe_config->name.link_m, \
12487 pipe_config->name.link_n); \
12491 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12492 if (!intel_compare_link_m_n(¤t_config->name, \
12493 &pipe_config->name, adjust) && \
12494 !intel_compare_link_m_n(¤t_config->alt_name, \
12495 &pipe_config->name, adjust)) { \
12496 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12497 "(expected tu %i gmch %i/%i link %i/%i, " \
12498 "or tu %i gmch %i/%i link %i/%i, " \
12499 "found tu %i, gmch %i/%i link %i/%i)\n", \
12500 current_config->name.tu, \
12501 current_config->name.gmch_m, \
12502 current_config->name.gmch_n, \
12503 current_config->name.link_m, \
12504 current_config->name.link_n, \
12505 current_config->alt_name.tu, \
12506 current_config->alt_name.gmch_m, \
12507 current_config->alt_name.gmch_n, \
12508 current_config->alt_name.link_m, \
12509 current_config->alt_name.link_n, \
12510 pipe_config->name.tu, \
12511 pipe_config->name.gmch_m, \
12512 pipe_config->name.gmch_n, \
12513 pipe_config->name.link_m, \
12514 pipe_config->name.link_n); \
12518 /* This is required for BDW+ where there is only one set of registers for
12519 * switching between high and low RR.
12520 * This macro can be used whenever a comparison has to be made between one
12521 * hw state and multiple sw state variables.
12523 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12524 if ((current_config->name != pipe_config->name) && \
12525 (current_config->alt_name != pipe_config->name)) { \
12526 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12527 "(expected %i or %i, found %i)\n", \
12528 current_config->name, \
12529 current_config->alt_name, \
12530 pipe_config->name); \
12534 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12535 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12536 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12537 "(expected %i, found %i)\n", \
12538 current_config->name & (mask), \
12539 pipe_config->name & (mask)); \
12543 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12544 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12545 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12546 "(expected %i, found %i)\n", \
12547 current_config->name, \
12548 pipe_config->name); \
12552 #define PIPE_CONF_QUIRK(quirk) \
12553 ((current_config->quirks | pipe_config->quirks) & (quirk))
12555 PIPE_CONF_CHECK_I(cpu_transcoder);
12557 PIPE_CONF_CHECK_I(has_pch_encoder);
12558 PIPE_CONF_CHECK_I(fdi_lanes);
12559 PIPE_CONF_CHECK_M_N(fdi_m_n);
12561 PIPE_CONF_CHECK_I(has_dp_encoder);
12563 if (INTEL_INFO(dev)->gen < 8) {
12564 PIPE_CONF_CHECK_M_N(dp_m_n);
12566 PIPE_CONF_CHECK_I(has_drrs);
12567 if (current_config->has_drrs)
12568 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12570 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12572 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12573 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12574 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12575 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12576 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12577 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12579 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12580 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12581 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12582 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12583 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12584 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12586 PIPE_CONF_CHECK_I(pixel_multiplier);
12587 PIPE_CONF_CHECK_I(has_hdmi_sink);
12588 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12589 IS_VALLEYVIEW(dev))
12590 PIPE_CONF_CHECK_I(limited_color_range);
12591 PIPE_CONF_CHECK_I(has_infoframe);
12593 PIPE_CONF_CHECK_I(has_audio);
12595 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12596 DRM_MODE_FLAG_INTERLACE);
12598 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12599 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12600 DRM_MODE_FLAG_PHSYNC);
12601 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12602 DRM_MODE_FLAG_NHSYNC);
12603 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12604 DRM_MODE_FLAG_PVSYNC);
12605 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12606 DRM_MODE_FLAG_NVSYNC);
12609 PIPE_CONF_CHECK_I(pipe_src_w);
12610 PIPE_CONF_CHECK_I(pipe_src_h);
12612 PIPE_CONF_CHECK_I(gmch_pfit.control);
12613 /* pfit ratios are autocomputed by the hw on gen4+ */
12614 if (INTEL_INFO(dev)->gen < 4)
12615 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12616 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12618 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12619 if (current_config->pch_pfit.enabled) {
12620 PIPE_CONF_CHECK_I(pch_pfit.pos);
12621 PIPE_CONF_CHECK_I(pch_pfit.size);
12624 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12626 /* BDW+ don't expose a synchronous way to read the state */
12627 if (IS_HASWELL(dev))
12628 PIPE_CONF_CHECK_I(ips_enabled);
12630 PIPE_CONF_CHECK_I(double_wide);
12632 PIPE_CONF_CHECK_X(ddi_pll_sel);
12634 PIPE_CONF_CHECK_I(shared_dpll);
12635 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12636 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12637 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12638 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12639 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12640 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12641 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12642 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12644 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12645 PIPE_CONF_CHECK_I(pipe_bpp);
12647 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12648 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12650 #undef PIPE_CONF_CHECK_X
12651 #undef PIPE_CONF_CHECK_I
12652 #undef PIPE_CONF_CHECK_I_ALT
12653 #undef PIPE_CONF_CHECK_FLAGS
12654 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12655 #undef PIPE_CONF_QUIRK
12656 #undef INTEL_ERR_OR_DBG_KMS
12661 static void check_wm_state(struct drm_device *dev)
12663 struct drm_i915_private *dev_priv = dev->dev_private;
12664 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12665 struct intel_crtc *intel_crtc;
12668 if (INTEL_INFO(dev)->gen < 9)
12671 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12672 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12674 for_each_intel_crtc(dev, intel_crtc) {
12675 struct skl_ddb_entry *hw_entry, *sw_entry;
12676 const enum pipe pipe = intel_crtc->pipe;
12678 if (!intel_crtc->active)
12682 for_each_plane(dev_priv, pipe, plane) {
12683 hw_entry = &hw_ddb.plane[pipe][plane];
12684 sw_entry = &sw_ddb->plane[pipe][plane];
12686 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12689 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12690 "(expected (%u,%u), found (%u,%u))\n",
12691 pipe_name(pipe), plane + 1,
12692 sw_entry->start, sw_entry->end,
12693 hw_entry->start, hw_entry->end);
12697 hw_entry = &hw_ddb.cursor[pipe];
12698 sw_entry = &sw_ddb->cursor[pipe];
12700 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12703 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12704 "(expected (%u,%u), found (%u,%u))\n",
12706 sw_entry->start, sw_entry->end,
12707 hw_entry->start, hw_entry->end);
12712 check_connector_state(struct drm_device *dev)
12714 struct intel_connector *connector;
12716 for_each_intel_connector(dev, connector) {
12717 struct drm_encoder *encoder = connector->base.encoder;
12718 struct drm_connector_state *state = connector->base.state;
12720 /* This also checks the encoder/connector hw state with the
12721 * ->get_hw_state callbacks. */
12722 intel_connector_check_state(connector);
12724 I915_STATE_WARN(state->best_encoder != encoder,
12725 "connector's staged encoder doesn't match current encoder\n");
12730 check_encoder_state(struct drm_device *dev)
12732 struct intel_encoder *encoder;
12733 struct intel_connector *connector;
12735 for_each_intel_encoder(dev, encoder) {
12736 bool enabled = false;
12737 bool active = false;
12738 enum pipe pipe, tracked_pipe;
12740 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12741 encoder->base.base.id,
12742 encoder->base.name);
12744 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12745 "encoder's active_connectors set, but no crtc\n");
12747 for_each_intel_connector(dev, connector) {
12748 if (connector->base.encoder != &encoder->base)
12751 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12754 I915_STATE_WARN(connector->base.state->crtc !=
12755 encoder->base.crtc,
12756 "connector's crtc doesn't match encoder crtc\n");
12759 * for MST connectors if we unplug the connector is gone
12760 * away but the encoder is still connected to a crtc
12761 * until a modeset happens in response to the hotplug.
12763 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12766 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12767 "encoder's enabled state mismatch "
12768 "(expected %i, found %i)\n",
12769 !!encoder->base.crtc, enabled);
12770 I915_STATE_WARN(active && !encoder->base.crtc,
12771 "active encoder with no crtc\n");
12773 I915_STATE_WARN(encoder->connectors_active != active,
12774 "encoder's computed active state doesn't match tracked active state "
12775 "(expected %i, found %i)\n", active, encoder->connectors_active);
12777 active = encoder->get_hw_state(encoder, &pipe);
12778 I915_STATE_WARN(active != encoder->connectors_active,
12779 "encoder's hw state doesn't match sw tracking "
12780 "(expected %i, found %i)\n",
12781 encoder->connectors_active, active);
12783 if (!encoder->base.crtc)
12786 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12787 I915_STATE_WARN(active && pipe != tracked_pipe,
12788 "active encoder's pipe doesn't match"
12789 "(expected %i, found %i)\n",
12790 tracked_pipe, pipe);
12796 check_crtc_state(struct drm_device *dev)
12798 struct drm_i915_private *dev_priv = dev->dev_private;
12799 struct intel_crtc *crtc;
12800 struct intel_encoder *encoder;
12801 struct intel_crtc_state pipe_config;
12803 for_each_intel_crtc(dev, crtc) {
12804 bool enabled = false;
12805 bool active = false;
12807 memset(&pipe_config, 0, sizeof(pipe_config));
12809 DRM_DEBUG_KMS("[CRTC:%d]\n",
12810 crtc->base.base.id);
12812 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12813 "active crtc, but not enabled in sw tracking\n");
12815 for_each_intel_encoder(dev, encoder) {
12816 if (encoder->base.crtc != &crtc->base)
12819 if (encoder->connectors_active)
12823 I915_STATE_WARN(active != crtc->active,
12824 "crtc's computed active state doesn't match tracked active state "
12825 "(expected %i, found %i)\n", active, crtc->active);
12826 I915_STATE_WARN(enabled != crtc->base.state->enable,
12827 "crtc's computed enabled state doesn't match tracked enabled state "
12828 "(expected %i, found %i)\n", enabled,
12829 crtc->base.state->enable);
12831 active = dev_priv->display.get_pipe_config(crtc,
12834 /* hw state is inconsistent with the pipe quirk */
12835 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12836 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12837 active = crtc->active;
12839 for_each_intel_encoder(dev, encoder) {
12841 if (encoder->base.crtc != &crtc->base)
12843 if (encoder->get_hw_state(encoder, &pipe))
12844 encoder->get_config(encoder, &pipe_config);
12847 I915_STATE_WARN(crtc->active != active,
12848 "crtc active state doesn't match with hw state "
12849 "(expected %i, found %i)\n", crtc->active, active);
12851 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12852 "transitional active state does not match atomic hw state "
12853 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12858 if (!intel_pipe_config_compare(dev, crtc->config,
12859 &pipe_config, false)) {
12860 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12861 intel_dump_pipe_config(crtc, &pipe_config,
12863 intel_dump_pipe_config(crtc, crtc->config,
12870 check_shared_dpll_state(struct drm_device *dev)
12872 struct drm_i915_private *dev_priv = dev->dev_private;
12873 struct intel_crtc *crtc;
12874 struct intel_dpll_hw_state dpll_hw_state;
12877 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12878 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12879 int enabled_crtcs = 0, active_crtcs = 0;
12882 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12884 DRM_DEBUG_KMS("%s\n", pll->name);
12886 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12888 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12889 "more active pll users than references: %i vs %i\n",
12890 pll->active, hweight32(pll->config.crtc_mask));
12891 I915_STATE_WARN(pll->active && !pll->on,
12892 "pll in active use but not on in sw tracking\n");
12893 I915_STATE_WARN(pll->on && !pll->active,
12894 "pll in on but not on in use in sw tracking\n");
12895 I915_STATE_WARN(pll->on != active,
12896 "pll on state mismatch (expected %i, found %i)\n",
12899 for_each_intel_crtc(dev, crtc) {
12900 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12902 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12905 I915_STATE_WARN(pll->active != active_crtcs,
12906 "pll active crtcs mismatch (expected %i, found %i)\n",
12907 pll->active, active_crtcs);
12908 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12909 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12910 hweight32(pll->config.crtc_mask), enabled_crtcs);
12912 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12913 sizeof(dpll_hw_state)),
12914 "pll hw state mismatch\n");
12919 intel_modeset_check_state(struct drm_device *dev)
12921 check_wm_state(dev);
12922 check_connector_state(dev);
12923 check_encoder_state(dev);
12924 check_crtc_state(dev);
12925 check_shared_dpll_state(dev);
12928 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12932 * FDI already provided one idea for the dotclock.
12933 * Yell if the encoder disagrees.
12935 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12936 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12937 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12940 static void update_scanline_offset(struct intel_crtc *crtc)
12942 struct drm_device *dev = crtc->base.dev;
12945 * The scanline counter increments at the leading edge of hsync.
12947 * On most platforms it starts counting from vtotal-1 on the
12948 * first active line. That means the scanline counter value is
12949 * always one less than what we would expect. Ie. just after
12950 * start of vblank, which also occurs at start of hsync (on the
12951 * last active line), the scanline counter will read vblank_start-1.
12953 * On gen2 the scanline counter starts counting from 1 instead
12954 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12955 * to keep the value positive), instead of adding one.
12957 * On HSW+ the behaviour of the scanline counter depends on the output
12958 * type. For DP ports it behaves like most other platforms, but on HDMI
12959 * there's an extra 1 line difference. So we need to add two instead of
12960 * one to the value.
12962 if (IS_GEN2(dev)) {
12963 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12966 vtotal = mode->crtc_vtotal;
12967 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12970 crtc->scanline_offset = vtotal - 1;
12971 } else if (HAS_DDI(dev) &&
12972 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12973 crtc->scanline_offset = 2;
12975 crtc->scanline_offset = 1;
12978 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12980 struct drm_device *dev = state->dev;
12981 struct drm_i915_private *dev_priv = to_i915(dev);
12982 struct intel_shared_dpll_config *shared_dpll = NULL;
12983 struct intel_crtc *intel_crtc;
12984 struct intel_crtc_state *intel_crtc_state;
12985 struct drm_crtc *crtc;
12986 struct drm_crtc_state *crtc_state;
12989 if (!dev_priv->display.crtc_compute_clock)
12992 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12995 intel_crtc = to_intel_crtc(crtc);
12996 intel_crtc_state = to_intel_crtc_state(crtc_state);
12997 dpll = intel_crtc_state->shared_dpll;
12999 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13002 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13005 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13007 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13012 * This implements the workaround described in the "notes" section of the mode
13013 * set sequence documentation. When going from no pipes or single pipe to
13014 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13015 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13017 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13019 struct drm_crtc_state *crtc_state;
13020 struct intel_crtc *intel_crtc;
13021 struct drm_crtc *crtc;
13022 struct intel_crtc_state *first_crtc_state = NULL;
13023 struct intel_crtc_state *other_crtc_state = NULL;
13024 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13027 /* look at all crtc's that are going to be enabled in during modeset */
13028 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13029 intel_crtc = to_intel_crtc(crtc);
13031 if (!crtc_state->active || !needs_modeset(crtc_state))
13034 if (first_crtc_state) {
13035 other_crtc_state = to_intel_crtc_state(crtc_state);
13038 first_crtc_state = to_intel_crtc_state(crtc_state);
13039 first_pipe = intel_crtc->pipe;
13043 /* No workaround needed? */
13044 if (!first_crtc_state)
13047 /* w/a possibly needed, check how many crtc's are already enabled. */
13048 for_each_intel_crtc(state->dev, intel_crtc) {
13049 struct intel_crtc_state *pipe_config;
13051 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13052 if (IS_ERR(pipe_config))
13053 return PTR_ERR(pipe_config);
13055 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13057 if (!pipe_config->base.active ||
13058 needs_modeset(&pipe_config->base))
13061 /* 2 or more enabled crtcs means no need for w/a */
13062 if (enabled_pipe != INVALID_PIPE)
13065 enabled_pipe = intel_crtc->pipe;
13068 if (enabled_pipe != INVALID_PIPE)
13069 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13070 else if (other_crtc_state)
13071 other_crtc_state->hsw_workaround_pipe = first_pipe;
13076 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13078 struct drm_crtc *crtc;
13079 struct drm_crtc_state *crtc_state;
13082 /* add all active pipes to the state */
13083 for_each_crtc(state->dev, crtc) {
13084 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13085 if (IS_ERR(crtc_state))
13086 return PTR_ERR(crtc_state);
13088 if (!crtc_state->active || needs_modeset(crtc_state))
13091 crtc_state->mode_changed = true;
13093 ret = drm_atomic_add_affected_connectors(state, crtc);
13097 ret = drm_atomic_add_affected_planes(state, crtc);
13106 static int intel_modeset_checks(struct drm_atomic_state *state)
13108 struct drm_device *dev = state->dev;
13109 struct drm_i915_private *dev_priv = dev->dev_private;
13112 if (!check_digital_port_conflicts(state)) {
13113 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13118 * See if the config requires any additional preparation, e.g.
13119 * to adjust global state with pipes off. We need to do this
13120 * here so we can get the modeset_pipe updated config for the new
13121 * mode set on this crtc. For other crtcs we need to use the
13122 * adjusted_mode bits in the crtc directly.
13124 if (dev_priv->display.modeset_calc_cdclk) {
13125 unsigned int cdclk;
13127 ret = dev_priv->display.modeset_calc_cdclk(state);
13129 cdclk = to_intel_atomic_state(state)->cdclk;
13130 if (!ret && cdclk != dev_priv->cdclk_freq)
13131 ret = intel_modeset_all_pipes(state);
13136 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13138 intel_modeset_clear_plls(state);
13140 if (IS_HASWELL(dev))
13141 return haswell_mode_set_planes_workaround(state);
13147 * intel_atomic_check - validate state object
13149 * @state: state to validate
13151 static int intel_atomic_check(struct drm_device *dev,
13152 struct drm_atomic_state *state)
13154 struct drm_crtc *crtc;
13155 struct drm_crtc_state *crtc_state;
13157 bool any_ms = false;
13159 ret = drm_atomic_helper_check_modeset(dev, state);
13163 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13164 struct intel_crtc_state *pipe_config =
13165 to_intel_crtc_state(crtc_state);
13167 /* Catch I915_MODE_FLAG_INHERITED */
13168 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13169 crtc_state->mode_changed = true;
13171 if (!crtc_state->enable) {
13172 if (needs_modeset(crtc_state))
13177 if (!needs_modeset(crtc_state))
13180 /* FIXME: For only active_changed we shouldn't need to do any
13181 * state recomputation at all. */
13183 ret = drm_atomic_add_affected_connectors(state, crtc);
13187 ret = intel_modeset_pipe_config(crtc, pipe_config);
13191 if (i915.fastboot &&
13192 intel_pipe_config_compare(state->dev,
13193 to_intel_crtc_state(crtc->state),
13194 pipe_config, true)) {
13195 crtc_state->mode_changed = false;
13198 if (needs_modeset(crtc_state)) {
13201 ret = drm_atomic_add_affected_planes(state, crtc);
13206 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13207 needs_modeset(crtc_state) ?
13208 "[modeset]" : "[fastset]");
13212 ret = intel_modeset_checks(state);
13217 to_intel_atomic_state(state)->cdclk =
13218 to_i915(state->dev)->cdclk_freq;
13220 return drm_atomic_helper_check_planes(state->dev, state);
13224 * intel_atomic_commit - commit validated state object
13226 * @state: the top-level driver state object
13227 * @async: asynchronous commit
13229 * This function commits a top-level state object that has been validated
13230 * with drm_atomic_helper_check().
13232 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13233 * we can only handle plane-related operations and do not yet support
13234 * asynchronous commit.
13237 * Zero for success or -errno.
13239 static int intel_atomic_commit(struct drm_device *dev,
13240 struct drm_atomic_state *state,
13243 struct drm_i915_private *dev_priv = dev->dev_private;
13244 struct drm_crtc *crtc;
13245 struct drm_crtc_state *crtc_state;
13248 bool any_ms = false;
13251 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13255 ret = drm_atomic_helper_prepare_planes(dev, state);
13259 drm_atomic_helper_swap_state(dev, state);
13261 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13264 if (!needs_modeset(crtc->state))
13268 intel_pre_plane_update(intel_crtc);
13270 if (crtc_state->active) {
13271 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13272 dev_priv->display.crtc_disable(crtc);
13273 intel_crtc->active = false;
13274 intel_disable_shared_dpll(intel_crtc);
13278 /* Only after disabling all output pipelines that will be changed can we
13279 * update the the output configuration. */
13280 intel_modeset_update_state(state);
13282 /* The state has been swaped above, so state actually contains the
13283 * old state now. */
13285 modeset_update_crtc_power_domains(state);
13287 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13288 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13290 bool modeset = needs_modeset(crtc->state);
13292 if (modeset && crtc->state->active) {
13293 update_scanline_offset(to_intel_crtc(crtc));
13294 dev_priv->display.crtc_enable(crtc);
13298 intel_pre_plane_update(intel_crtc);
13300 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13301 intel_post_plane_update(intel_crtc);
13304 /* FIXME: add subpixel order */
13306 drm_atomic_helper_wait_for_vblanks(dev, state);
13307 drm_atomic_helper_cleanup_planes(dev, state);
13308 drm_atomic_state_free(state);
13311 intel_modeset_check_state(dev);
13316 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13318 struct drm_device *dev = crtc->dev;
13319 struct drm_atomic_state *state;
13320 struct drm_crtc_state *crtc_state;
13323 state = drm_atomic_state_alloc(dev);
13325 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13330 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13333 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13334 ret = PTR_ERR_OR_ZERO(crtc_state);
13336 if (!crtc_state->active)
13339 crtc_state->mode_changed = true;
13340 ret = drm_atomic_commit(state);
13343 if (ret == -EDEADLK) {
13344 drm_atomic_state_clear(state);
13345 drm_modeset_backoff(state->acquire_ctx);
13351 drm_atomic_state_free(state);
13354 #undef for_each_intel_crtc_masked
13356 static const struct drm_crtc_funcs intel_crtc_funcs = {
13357 .gamma_set = intel_crtc_gamma_set,
13358 .set_config = drm_atomic_helper_set_config,
13359 .destroy = intel_crtc_destroy,
13360 .page_flip = intel_crtc_page_flip,
13361 .atomic_duplicate_state = intel_crtc_duplicate_state,
13362 .atomic_destroy_state = intel_crtc_destroy_state,
13365 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13366 struct intel_shared_dpll *pll,
13367 struct intel_dpll_hw_state *hw_state)
13371 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13374 val = I915_READ(PCH_DPLL(pll->id));
13375 hw_state->dpll = val;
13376 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13377 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13379 return val & DPLL_VCO_ENABLE;
13382 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13383 struct intel_shared_dpll *pll)
13385 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13386 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13389 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13390 struct intel_shared_dpll *pll)
13392 /* PCH refclock must be enabled first */
13393 ibx_assert_pch_refclk_enabled(dev_priv);
13395 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13397 /* Wait for the clocks to stabilize. */
13398 POSTING_READ(PCH_DPLL(pll->id));
13401 /* The pixel multiplier can only be updated once the
13402 * DPLL is enabled and the clocks are stable.
13404 * So write it again.
13406 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13407 POSTING_READ(PCH_DPLL(pll->id));
13411 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13412 struct intel_shared_dpll *pll)
13414 struct drm_device *dev = dev_priv->dev;
13415 struct intel_crtc *crtc;
13417 /* Make sure no transcoder isn't still depending on us. */
13418 for_each_intel_crtc(dev, crtc) {
13419 if (intel_crtc_to_shared_dpll(crtc) == pll)
13420 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13423 I915_WRITE(PCH_DPLL(pll->id), 0);
13424 POSTING_READ(PCH_DPLL(pll->id));
13428 static char *ibx_pch_dpll_names[] = {
13433 static void ibx_pch_dpll_init(struct drm_device *dev)
13435 struct drm_i915_private *dev_priv = dev->dev_private;
13438 dev_priv->num_shared_dpll = 2;
13440 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13441 dev_priv->shared_dplls[i].id = i;
13442 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13443 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13444 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13445 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13446 dev_priv->shared_dplls[i].get_hw_state =
13447 ibx_pch_dpll_get_hw_state;
13451 static void intel_shared_dpll_init(struct drm_device *dev)
13453 struct drm_i915_private *dev_priv = dev->dev_private;
13455 intel_update_cdclk(dev);
13458 intel_ddi_pll_init(dev);
13459 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13460 ibx_pch_dpll_init(dev);
13462 dev_priv->num_shared_dpll = 0;
13464 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13468 * intel_prepare_plane_fb - Prepare fb for usage on plane
13469 * @plane: drm plane to prepare for
13470 * @fb: framebuffer to prepare for presentation
13472 * Prepares a framebuffer for usage on a display plane. Generally this
13473 * involves pinning the underlying object and updating the frontbuffer tracking
13474 * bits. Some older platforms need special physical address handling for
13477 * Returns 0 on success, negative error code on failure.
13480 intel_prepare_plane_fb(struct drm_plane *plane,
13481 struct drm_framebuffer *fb,
13482 const struct drm_plane_state *new_state)
13484 struct drm_device *dev = plane->dev;
13485 struct intel_plane *intel_plane = to_intel_plane(plane);
13486 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13487 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13493 mutex_lock(&dev->struct_mutex);
13495 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13496 INTEL_INFO(dev)->cursor_needs_physical) {
13497 int align = IS_I830(dev) ? 16 * 1024 : 256;
13498 ret = i915_gem_object_attach_phys(obj, align);
13500 DRM_DEBUG_KMS("failed to attach phys object\n");
13502 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13506 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13508 mutex_unlock(&dev->struct_mutex);
13514 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13515 * @plane: drm plane to clean up for
13516 * @fb: old framebuffer that was on plane
13518 * Cleans up a framebuffer that has just been removed from a plane.
13521 intel_cleanup_plane_fb(struct drm_plane *plane,
13522 struct drm_framebuffer *fb,
13523 const struct drm_plane_state *old_state)
13525 struct drm_device *dev = plane->dev;
13526 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13531 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13532 !INTEL_INFO(dev)->cursor_needs_physical) {
13533 mutex_lock(&dev->struct_mutex);
13534 intel_unpin_fb_obj(fb, old_state);
13535 mutex_unlock(&dev->struct_mutex);
13540 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13543 struct drm_device *dev;
13544 struct drm_i915_private *dev_priv;
13545 int crtc_clock, cdclk;
13547 if (!intel_crtc || !crtc_state)
13548 return DRM_PLANE_HELPER_NO_SCALING;
13550 dev = intel_crtc->base.dev;
13551 dev_priv = dev->dev_private;
13552 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13553 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13555 if (!crtc_clock || !cdclk)
13556 return DRM_PLANE_HELPER_NO_SCALING;
13559 * skl max scale is lower of:
13560 * close to 3 but not 3, -1 is for that purpose
13564 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13570 intel_check_primary_plane(struct drm_plane *plane,
13571 struct intel_crtc_state *crtc_state,
13572 struct intel_plane_state *state)
13574 struct drm_crtc *crtc = state->base.crtc;
13575 struct drm_framebuffer *fb = state->base.fb;
13576 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13577 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13578 bool can_position = false;
13580 /* use scaler when colorkey is not required */
13581 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13582 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13584 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13585 can_position = true;
13588 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13589 &state->dst, &state->clip,
13590 min_scale, max_scale,
13591 can_position, true,
13596 intel_commit_primary_plane(struct drm_plane *plane,
13597 struct intel_plane_state *state)
13599 struct drm_crtc *crtc = state->base.crtc;
13600 struct drm_framebuffer *fb = state->base.fb;
13601 struct drm_device *dev = plane->dev;
13602 struct drm_i915_private *dev_priv = dev->dev_private;
13603 struct intel_crtc *intel_crtc;
13604 struct drm_rect *src = &state->src;
13606 crtc = crtc ? crtc : plane->crtc;
13607 intel_crtc = to_intel_crtc(crtc);
13610 crtc->x = src->x1 >> 16;
13611 crtc->y = src->y1 >> 16;
13613 if (!crtc->state->active)
13616 if (state->visible)
13617 /* FIXME: kill this fastboot hack */
13618 intel_update_pipe_size(intel_crtc);
13620 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
13624 intel_disable_primary_plane(struct drm_plane *plane,
13625 struct drm_crtc *crtc)
13627 struct drm_device *dev = plane->dev;
13628 struct drm_i915_private *dev_priv = dev->dev_private;
13630 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13633 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13634 struct drm_crtc_state *old_crtc_state)
13636 struct drm_device *dev = crtc->dev;
13637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13639 if (intel_crtc->atomic.update_wm_pre)
13640 intel_update_watermarks(crtc);
13642 /* Perform vblank evasion around commit operation */
13643 if (crtc->state->active)
13644 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
13646 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13647 skl_detach_scalers(intel_crtc);
13650 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13651 struct drm_crtc_state *old_crtc_state)
13653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13655 if (crtc->state->active)
13656 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
13660 * intel_plane_destroy - destroy a plane
13661 * @plane: plane to destroy
13663 * Common destruction function for all types of planes (primary, cursor,
13666 void intel_plane_destroy(struct drm_plane *plane)
13668 struct intel_plane *intel_plane = to_intel_plane(plane);
13669 drm_plane_cleanup(plane);
13670 kfree(intel_plane);
13673 const struct drm_plane_funcs intel_plane_funcs = {
13674 .update_plane = drm_atomic_helper_update_plane,
13675 .disable_plane = drm_atomic_helper_disable_plane,
13676 .destroy = intel_plane_destroy,
13677 .set_property = drm_atomic_helper_plane_set_property,
13678 .atomic_get_property = intel_plane_atomic_get_property,
13679 .atomic_set_property = intel_plane_atomic_set_property,
13680 .atomic_duplicate_state = intel_plane_duplicate_state,
13681 .atomic_destroy_state = intel_plane_destroy_state,
13685 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13688 struct intel_plane *primary;
13689 struct intel_plane_state *state;
13690 const uint32_t *intel_primary_formats;
13693 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13694 if (primary == NULL)
13697 state = intel_create_plane_state(&primary->base);
13702 primary->base.state = &state->base;
13704 primary->can_scale = false;
13705 primary->max_downscale = 1;
13706 if (INTEL_INFO(dev)->gen >= 9) {
13707 primary->can_scale = true;
13708 state->scaler_id = -1;
13710 primary->pipe = pipe;
13711 primary->plane = pipe;
13712 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13713 primary->check_plane = intel_check_primary_plane;
13714 primary->commit_plane = intel_commit_primary_plane;
13715 primary->disable_plane = intel_disable_primary_plane;
13716 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13717 primary->plane = !pipe;
13719 if (INTEL_INFO(dev)->gen >= 9) {
13720 intel_primary_formats = skl_primary_formats;
13721 num_formats = ARRAY_SIZE(skl_primary_formats);
13722 } else if (INTEL_INFO(dev)->gen >= 4) {
13723 intel_primary_formats = i965_primary_formats;
13724 num_formats = ARRAY_SIZE(i965_primary_formats);
13726 intel_primary_formats = i8xx_primary_formats;
13727 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13730 drm_universal_plane_init(dev, &primary->base, 0,
13731 &intel_plane_funcs,
13732 intel_primary_formats, num_formats,
13733 DRM_PLANE_TYPE_PRIMARY);
13735 if (INTEL_INFO(dev)->gen >= 4)
13736 intel_create_rotation_property(dev, primary);
13738 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13740 return &primary->base;
13743 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13745 if (!dev->mode_config.rotation_property) {
13746 unsigned long flags = BIT(DRM_ROTATE_0) |
13747 BIT(DRM_ROTATE_180);
13749 if (INTEL_INFO(dev)->gen >= 9)
13750 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13752 dev->mode_config.rotation_property =
13753 drm_mode_create_rotation_property(dev, flags);
13755 if (dev->mode_config.rotation_property)
13756 drm_object_attach_property(&plane->base.base,
13757 dev->mode_config.rotation_property,
13758 plane->base.state->rotation);
13762 intel_check_cursor_plane(struct drm_plane *plane,
13763 struct intel_crtc_state *crtc_state,
13764 struct intel_plane_state *state)
13766 struct drm_crtc *crtc = crtc_state->base.crtc;
13767 struct drm_framebuffer *fb = state->base.fb;
13768 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13772 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13773 &state->dst, &state->clip,
13774 DRM_PLANE_HELPER_NO_SCALING,
13775 DRM_PLANE_HELPER_NO_SCALING,
13776 true, true, &state->visible);
13780 /* if we want to turn off the cursor ignore width and height */
13784 /* Check for which cursor types we support */
13785 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13786 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13787 state->base.crtc_w, state->base.crtc_h);
13791 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13792 if (obj->base.size < stride * state->base.crtc_h) {
13793 DRM_DEBUG_KMS("buffer is too small\n");
13797 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13798 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13806 intel_disable_cursor_plane(struct drm_plane *plane,
13807 struct drm_crtc *crtc)
13809 intel_crtc_update_cursor(crtc, false);
13813 intel_commit_cursor_plane(struct drm_plane *plane,
13814 struct intel_plane_state *state)
13816 struct drm_crtc *crtc = state->base.crtc;
13817 struct drm_device *dev = plane->dev;
13818 struct intel_crtc *intel_crtc;
13819 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13822 crtc = crtc ? crtc : plane->crtc;
13823 intel_crtc = to_intel_crtc(crtc);
13825 plane->fb = state->base.fb;
13826 crtc->cursor_x = state->base.crtc_x;
13827 crtc->cursor_y = state->base.crtc_y;
13829 if (intel_crtc->cursor_bo == obj)
13834 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13835 addr = i915_gem_obj_ggtt_offset(obj);
13837 addr = obj->phys_handle->busaddr;
13839 intel_crtc->cursor_addr = addr;
13840 intel_crtc->cursor_bo = obj;
13843 if (crtc->state->active)
13844 intel_crtc_update_cursor(crtc, state->visible);
13847 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13850 struct intel_plane *cursor;
13851 struct intel_plane_state *state;
13853 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13854 if (cursor == NULL)
13857 state = intel_create_plane_state(&cursor->base);
13862 cursor->base.state = &state->base;
13864 cursor->can_scale = false;
13865 cursor->max_downscale = 1;
13866 cursor->pipe = pipe;
13867 cursor->plane = pipe;
13868 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13869 cursor->check_plane = intel_check_cursor_plane;
13870 cursor->commit_plane = intel_commit_cursor_plane;
13871 cursor->disable_plane = intel_disable_cursor_plane;
13873 drm_universal_plane_init(dev, &cursor->base, 0,
13874 &intel_plane_funcs,
13875 intel_cursor_formats,
13876 ARRAY_SIZE(intel_cursor_formats),
13877 DRM_PLANE_TYPE_CURSOR);
13879 if (INTEL_INFO(dev)->gen >= 4) {
13880 if (!dev->mode_config.rotation_property)
13881 dev->mode_config.rotation_property =
13882 drm_mode_create_rotation_property(dev,
13883 BIT(DRM_ROTATE_0) |
13884 BIT(DRM_ROTATE_180));
13885 if (dev->mode_config.rotation_property)
13886 drm_object_attach_property(&cursor->base.base,
13887 dev->mode_config.rotation_property,
13888 state->base.rotation);
13891 if (INTEL_INFO(dev)->gen >=9)
13892 state->scaler_id = -1;
13894 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13896 return &cursor->base;
13899 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13900 struct intel_crtc_state *crtc_state)
13903 struct intel_scaler *intel_scaler;
13904 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13906 for (i = 0; i < intel_crtc->num_scalers; i++) {
13907 intel_scaler = &scaler_state->scalers[i];
13908 intel_scaler->in_use = 0;
13909 intel_scaler->mode = PS_SCALER_MODE_DYN;
13912 scaler_state->scaler_id = -1;
13915 static void intel_crtc_init(struct drm_device *dev, int pipe)
13917 struct drm_i915_private *dev_priv = dev->dev_private;
13918 struct intel_crtc *intel_crtc;
13919 struct intel_crtc_state *crtc_state = NULL;
13920 struct drm_plane *primary = NULL;
13921 struct drm_plane *cursor = NULL;
13924 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13925 if (intel_crtc == NULL)
13928 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13931 intel_crtc->config = crtc_state;
13932 intel_crtc->base.state = &crtc_state->base;
13933 crtc_state->base.crtc = &intel_crtc->base;
13935 /* initialize shared scalers */
13936 if (INTEL_INFO(dev)->gen >= 9) {
13937 if (pipe == PIPE_C)
13938 intel_crtc->num_scalers = 1;
13940 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13942 skl_init_scalers(dev, intel_crtc, crtc_state);
13945 primary = intel_primary_plane_create(dev, pipe);
13949 cursor = intel_cursor_plane_create(dev, pipe);
13953 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13954 cursor, &intel_crtc_funcs);
13958 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13959 for (i = 0; i < 256; i++) {
13960 intel_crtc->lut_r[i] = i;
13961 intel_crtc->lut_g[i] = i;
13962 intel_crtc->lut_b[i] = i;
13966 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13967 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13969 intel_crtc->pipe = pipe;
13970 intel_crtc->plane = pipe;
13971 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13972 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13973 intel_crtc->plane = !pipe;
13976 intel_crtc->cursor_base = ~0;
13977 intel_crtc->cursor_cntl = ~0;
13978 intel_crtc->cursor_size = ~0;
13980 intel_crtc->wm.cxsr_allowed = true;
13982 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13983 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13984 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13985 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13987 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13989 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13994 drm_plane_cleanup(primary);
13996 drm_plane_cleanup(cursor);
14001 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14003 struct drm_encoder *encoder = connector->base.encoder;
14004 struct drm_device *dev = connector->base.dev;
14006 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14008 if (!encoder || WARN_ON(!encoder->crtc))
14009 return INVALID_PIPE;
14011 return to_intel_crtc(encoder->crtc)->pipe;
14014 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14015 struct drm_file *file)
14017 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14018 struct drm_crtc *drmmode_crtc;
14019 struct intel_crtc *crtc;
14021 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14023 if (!drmmode_crtc) {
14024 DRM_ERROR("no such CRTC id\n");
14028 crtc = to_intel_crtc(drmmode_crtc);
14029 pipe_from_crtc_id->pipe = crtc->pipe;
14034 static int intel_encoder_clones(struct intel_encoder *encoder)
14036 struct drm_device *dev = encoder->base.dev;
14037 struct intel_encoder *source_encoder;
14038 int index_mask = 0;
14041 for_each_intel_encoder(dev, source_encoder) {
14042 if (encoders_cloneable(encoder, source_encoder))
14043 index_mask |= (1 << entry);
14051 static bool has_edp_a(struct drm_device *dev)
14053 struct drm_i915_private *dev_priv = dev->dev_private;
14055 if (!IS_MOBILE(dev))
14058 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14061 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14067 static bool intel_crt_present(struct drm_device *dev)
14069 struct drm_i915_private *dev_priv = dev->dev_private;
14071 if (INTEL_INFO(dev)->gen >= 9)
14074 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14077 if (IS_CHERRYVIEW(dev))
14080 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14086 static void intel_setup_outputs(struct drm_device *dev)
14088 struct drm_i915_private *dev_priv = dev->dev_private;
14089 struct intel_encoder *encoder;
14090 bool dpd_is_edp = false;
14092 intel_lvds_init(dev);
14094 if (intel_crt_present(dev))
14095 intel_crt_init(dev);
14097 if (IS_BROXTON(dev)) {
14099 * FIXME: Broxton doesn't support port detection via the
14100 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14101 * detect the ports.
14103 intel_ddi_init(dev, PORT_A);
14104 intel_ddi_init(dev, PORT_B);
14105 intel_ddi_init(dev, PORT_C);
14106 } else if (HAS_DDI(dev)) {
14110 * Haswell uses DDI functions to detect digital outputs.
14111 * On SKL pre-D0 the strap isn't connected, so we assume
14114 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
14115 /* WaIgnoreDDIAStrap: skl */
14117 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
14118 intel_ddi_init(dev, PORT_A);
14120 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14122 found = I915_READ(SFUSE_STRAP);
14124 if (found & SFUSE_STRAP_DDIB_DETECTED)
14125 intel_ddi_init(dev, PORT_B);
14126 if (found & SFUSE_STRAP_DDIC_DETECTED)
14127 intel_ddi_init(dev, PORT_C);
14128 if (found & SFUSE_STRAP_DDID_DETECTED)
14129 intel_ddi_init(dev, PORT_D);
14130 } else if (HAS_PCH_SPLIT(dev)) {
14132 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14134 if (has_edp_a(dev))
14135 intel_dp_init(dev, DP_A, PORT_A);
14137 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14138 /* PCH SDVOB multiplex with HDMIB */
14139 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14141 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14142 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14143 intel_dp_init(dev, PCH_DP_B, PORT_B);
14146 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14147 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14149 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14150 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14152 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14153 intel_dp_init(dev, PCH_DP_C, PORT_C);
14155 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14156 intel_dp_init(dev, PCH_DP_D, PORT_D);
14157 } else if (IS_VALLEYVIEW(dev)) {
14159 * The DP_DETECTED bit is the latched state of the DDC
14160 * SDA pin at boot. However since eDP doesn't require DDC
14161 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14162 * eDP ports may have been muxed to an alternate function.
14163 * Thus we can't rely on the DP_DETECTED bit alone to detect
14164 * eDP ports. Consult the VBT as well as DP_DETECTED to
14165 * detect eDP ports.
14167 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14168 !intel_dp_is_edp(dev, PORT_B))
14169 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14171 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14172 intel_dp_is_edp(dev, PORT_B))
14173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
14175 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14176 !intel_dp_is_edp(dev, PORT_C))
14177 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14179 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14180 intel_dp_is_edp(dev, PORT_C))
14181 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
14183 if (IS_CHERRYVIEW(dev)) {
14184 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
14185 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14187 /* eDP not supported on port D, so don't check VBT */
14188 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14189 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
14192 intel_dsi_init(dev);
14193 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14194 bool found = false;
14196 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14197 DRM_DEBUG_KMS("probing SDVOB\n");
14198 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14199 if (!found && IS_G4X(dev)) {
14200 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14201 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14204 if (!found && IS_G4X(dev))
14205 intel_dp_init(dev, DP_B, PORT_B);
14208 /* Before G4X SDVOC doesn't have its own detect register */
14210 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14211 DRM_DEBUG_KMS("probing SDVOC\n");
14212 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14215 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14218 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14219 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14222 intel_dp_init(dev, DP_C, PORT_C);
14226 (I915_READ(DP_D) & DP_DETECTED))
14227 intel_dp_init(dev, DP_D, PORT_D);
14228 } else if (IS_GEN2(dev))
14229 intel_dvo_init(dev);
14231 if (SUPPORTS_TV(dev))
14232 intel_tv_init(dev);
14234 intel_psr_init(dev);
14236 for_each_intel_encoder(dev, encoder) {
14237 encoder->base.possible_crtcs = encoder->crtc_mask;
14238 encoder->base.possible_clones =
14239 intel_encoder_clones(encoder);
14242 intel_init_pch_refclk(dev);
14244 drm_helper_move_panel_connectors_to_head(dev);
14247 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14249 struct drm_device *dev = fb->dev;
14250 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14252 drm_framebuffer_cleanup(fb);
14253 mutex_lock(&dev->struct_mutex);
14254 WARN_ON(!intel_fb->obj->framebuffer_references--);
14255 drm_gem_object_unreference(&intel_fb->obj->base);
14256 mutex_unlock(&dev->struct_mutex);
14260 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14261 struct drm_file *file,
14262 unsigned int *handle)
14264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14265 struct drm_i915_gem_object *obj = intel_fb->obj;
14267 return drm_gem_handle_create(file, &obj->base, handle);
14270 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14271 struct drm_file *file,
14272 unsigned flags, unsigned color,
14273 struct drm_clip_rect *clips,
14274 unsigned num_clips)
14276 struct drm_device *dev = fb->dev;
14277 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14278 struct drm_i915_gem_object *obj = intel_fb->obj;
14280 mutex_lock(&dev->struct_mutex);
14281 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14282 mutex_unlock(&dev->struct_mutex);
14287 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14288 .destroy = intel_user_framebuffer_destroy,
14289 .create_handle = intel_user_framebuffer_create_handle,
14290 .dirty = intel_user_framebuffer_dirty,
14294 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14295 uint32_t pixel_format)
14297 u32 gen = INTEL_INFO(dev)->gen;
14300 /* "The stride in bytes must not exceed the of the size of 8K
14301 * pixels and 32K bytes."
14303 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14304 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14306 } else if (gen >= 4) {
14307 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14311 } else if (gen >= 3) {
14312 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14317 /* XXX DSPC is limited to 4k tiled */
14322 static int intel_framebuffer_init(struct drm_device *dev,
14323 struct intel_framebuffer *intel_fb,
14324 struct drm_mode_fb_cmd2 *mode_cmd,
14325 struct drm_i915_gem_object *obj)
14327 unsigned int aligned_height;
14329 u32 pitch_limit, stride_alignment;
14331 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14333 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14334 /* Enforce that fb modifier and tiling mode match, but only for
14335 * X-tiled. This is needed for FBC. */
14336 if (!!(obj->tiling_mode == I915_TILING_X) !=
14337 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14338 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14342 if (obj->tiling_mode == I915_TILING_X)
14343 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14344 else if (obj->tiling_mode == I915_TILING_Y) {
14345 DRM_DEBUG("No Y tiling for legacy addfb\n");
14350 /* Passed in modifier sanity checking. */
14351 switch (mode_cmd->modifier[0]) {
14352 case I915_FORMAT_MOD_Y_TILED:
14353 case I915_FORMAT_MOD_Yf_TILED:
14354 if (INTEL_INFO(dev)->gen < 9) {
14355 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14356 mode_cmd->modifier[0]);
14359 case DRM_FORMAT_MOD_NONE:
14360 case I915_FORMAT_MOD_X_TILED:
14363 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14364 mode_cmd->modifier[0]);
14368 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14369 mode_cmd->pixel_format);
14370 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14371 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14372 mode_cmd->pitches[0], stride_alignment);
14376 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14377 mode_cmd->pixel_format);
14378 if (mode_cmd->pitches[0] > pitch_limit) {
14379 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14380 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14381 "tiled" : "linear",
14382 mode_cmd->pitches[0], pitch_limit);
14386 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14387 mode_cmd->pitches[0] != obj->stride) {
14388 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14389 mode_cmd->pitches[0], obj->stride);
14393 /* Reject formats not supported by any plane early. */
14394 switch (mode_cmd->pixel_format) {
14395 case DRM_FORMAT_C8:
14396 case DRM_FORMAT_RGB565:
14397 case DRM_FORMAT_XRGB8888:
14398 case DRM_FORMAT_ARGB8888:
14400 case DRM_FORMAT_XRGB1555:
14401 if (INTEL_INFO(dev)->gen > 3) {
14402 DRM_DEBUG("unsupported pixel format: %s\n",
14403 drm_get_format_name(mode_cmd->pixel_format));
14407 case DRM_FORMAT_ABGR8888:
14408 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14409 DRM_DEBUG("unsupported pixel format: %s\n",
14410 drm_get_format_name(mode_cmd->pixel_format));
14414 case DRM_FORMAT_XBGR8888:
14415 case DRM_FORMAT_XRGB2101010:
14416 case DRM_FORMAT_XBGR2101010:
14417 if (INTEL_INFO(dev)->gen < 4) {
14418 DRM_DEBUG("unsupported pixel format: %s\n",
14419 drm_get_format_name(mode_cmd->pixel_format));
14423 case DRM_FORMAT_ABGR2101010:
14424 if (!IS_VALLEYVIEW(dev)) {
14425 DRM_DEBUG("unsupported pixel format: %s\n",
14426 drm_get_format_name(mode_cmd->pixel_format));
14430 case DRM_FORMAT_YUYV:
14431 case DRM_FORMAT_UYVY:
14432 case DRM_FORMAT_YVYU:
14433 case DRM_FORMAT_VYUY:
14434 if (INTEL_INFO(dev)->gen < 5) {
14435 DRM_DEBUG("unsupported pixel format: %s\n",
14436 drm_get_format_name(mode_cmd->pixel_format));
14441 DRM_DEBUG("unsupported pixel format: %s\n",
14442 drm_get_format_name(mode_cmd->pixel_format));
14446 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14447 if (mode_cmd->offsets[0] != 0)
14450 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14451 mode_cmd->pixel_format,
14452 mode_cmd->modifier[0]);
14453 /* FIXME drm helper for size checks (especially planar formats)? */
14454 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14457 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14458 intel_fb->obj = obj;
14459 intel_fb->obj->framebuffer_references++;
14461 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14463 DRM_ERROR("framebuffer init failed %d\n", ret);
14470 static struct drm_framebuffer *
14471 intel_user_framebuffer_create(struct drm_device *dev,
14472 struct drm_file *filp,
14473 struct drm_mode_fb_cmd2 *mode_cmd)
14475 struct drm_i915_gem_object *obj;
14477 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14478 mode_cmd->handles[0]));
14479 if (&obj->base == NULL)
14480 return ERR_PTR(-ENOENT);
14482 return intel_framebuffer_create(dev, mode_cmd, obj);
14485 #ifndef CONFIG_DRM_I915_FBDEV
14486 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14491 static const struct drm_mode_config_funcs intel_mode_funcs = {
14492 .fb_create = intel_user_framebuffer_create,
14493 .output_poll_changed = intel_fbdev_output_poll_changed,
14494 .atomic_check = intel_atomic_check,
14495 .atomic_commit = intel_atomic_commit,
14496 .atomic_state_alloc = intel_atomic_state_alloc,
14497 .atomic_state_clear = intel_atomic_state_clear,
14500 /* Set up chip specific display functions */
14501 static void intel_init_display(struct drm_device *dev)
14503 struct drm_i915_private *dev_priv = dev->dev_private;
14505 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14506 dev_priv->display.find_dpll = g4x_find_best_dpll;
14507 else if (IS_CHERRYVIEW(dev))
14508 dev_priv->display.find_dpll = chv_find_best_dpll;
14509 else if (IS_VALLEYVIEW(dev))
14510 dev_priv->display.find_dpll = vlv_find_best_dpll;
14511 else if (IS_PINEVIEW(dev))
14512 dev_priv->display.find_dpll = pnv_find_best_dpll;
14514 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14516 if (INTEL_INFO(dev)->gen >= 9) {
14517 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14518 dev_priv->display.get_initial_plane_config =
14519 skylake_get_initial_plane_config;
14520 dev_priv->display.crtc_compute_clock =
14521 haswell_crtc_compute_clock;
14522 dev_priv->display.crtc_enable = haswell_crtc_enable;
14523 dev_priv->display.crtc_disable = haswell_crtc_disable;
14524 dev_priv->display.update_primary_plane =
14525 skylake_update_primary_plane;
14526 } else if (HAS_DDI(dev)) {
14527 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14528 dev_priv->display.get_initial_plane_config =
14529 ironlake_get_initial_plane_config;
14530 dev_priv->display.crtc_compute_clock =
14531 haswell_crtc_compute_clock;
14532 dev_priv->display.crtc_enable = haswell_crtc_enable;
14533 dev_priv->display.crtc_disable = haswell_crtc_disable;
14534 dev_priv->display.update_primary_plane =
14535 ironlake_update_primary_plane;
14536 } else if (HAS_PCH_SPLIT(dev)) {
14537 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14538 dev_priv->display.get_initial_plane_config =
14539 ironlake_get_initial_plane_config;
14540 dev_priv->display.crtc_compute_clock =
14541 ironlake_crtc_compute_clock;
14542 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14543 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14544 dev_priv->display.update_primary_plane =
14545 ironlake_update_primary_plane;
14546 } else if (IS_VALLEYVIEW(dev)) {
14547 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14548 dev_priv->display.get_initial_plane_config =
14549 i9xx_get_initial_plane_config;
14550 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14551 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14552 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14553 dev_priv->display.update_primary_plane =
14554 i9xx_update_primary_plane;
14556 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14557 dev_priv->display.get_initial_plane_config =
14558 i9xx_get_initial_plane_config;
14559 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14560 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14561 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14562 dev_priv->display.update_primary_plane =
14563 i9xx_update_primary_plane;
14566 /* Returns the core display clock speed */
14567 if (IS_SKYLAKE(dev))
14568 dev_priv->display.get_display_clock_speed =
14569 skylake_get_display_clock_speed;
14570 else if (IS_BROXTON(dev))
14571 dev_priv->display.get_display_clock_speed =
14572 broxton_get_display_clock_speed;
14573 else if (IS_BROADWELL(dev))
14574 dev_priv->display.get_display_clock_speed =
14575 broadwell_get_display_clock_speed;
14576 else if (IS_HASWELL(dev))
14577 dev_priv->display.get_display_clock_speed =
14578 haswell_get_display_clock_speed;
14579 else if (IS_VALLEYVIEW(dev))
14580 dev_priv->display.get_display_clock_speed =
14581 valleyview_get_display_clock_speed;
14582 else if (IS_GEN5(dev))
14583 dev_priv->display.get_display_clock_speed =
14584 ilk_get_display_clock_speed;
14585 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14586 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14587 dev_priv->display.get_display_clock_speed =
14588 i945_get_display_clock_speed;
14589 else if (IS_GM45(dev))
14590 dev_priv->display.get_display_clock_speed =
14591 gm45_get_display_clock_speed;
14592 else if (IS_CRESTLINE(dev))
14593 dev_priv->display.get_display_clock_speed =
14594 i965gm_get_display_clock_speed;
14595 else if (IS_PINEVIEW(dev))
14596 dev_priv->display.get_display_clock_speed =
14597 pnv_get_display_clock_speed;
14598 else if (IS_G33(dev) || IS_G4X(dev))
14599 dev_priv->display.get_display_clock_speed =
14600 g33_get_display_clock_speed;
14601 else if (IS_I915G(dev))
14602 dev_priv->display.get_display_clock_speed =
14603 i915_get_display_clock_speed;
14604 else if (IS_I945GM(dev) || IS_845G(dev))
14605 dev_priv->display.get_display_clock_speed =
14606 i9xx_misc_get_display_clock_speed;
14607 else if (IS_PINEVIEW(dev))
14608 dev_priv->display.get_display_clock_speed =
14609 pnv_get_display_clock_speed;
14610 else if (IS_I915GM(dev))
14611 dev_priv->display.get_display_clock_speed =
14612 i915gm_get_display_clock_speed;
14613 else if (IS_I865G(dev))
14614 dev_priv->display.get_display_clock_speed =
14615 i865_get_display_clock_speed;
14616 else if (IS_I85X(dev))
14617 dev_priv->display.get_display_clock_speed =
14618 i85x_get_display_clock_speed;
14620 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14621 dev_priv->display.get_display_clock_speed =
14622 i830_get_display_clock_speed;
14625 if (IS_GEN5(dev)) {
14626 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14627 } else if (IS_GEN6(dev)) {
14628 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14629 } else if (IS_IVYBRIDGE(dev)) {
14630 /* FIXME: detect B0+ stepping and use auto training */
14631 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14632 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14633 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14634 if (IS_BROADWELL(dev)) {
14635 dev_priv->display.modeset_commit_cdclk =
14636 broadwell_modeset_commit_cdclk;
14637 dev_priv->display.modeset_calc_cdclk =
14638 broadwell_modeset_calc_cdclk;
14640 } else if (IS_VALLEYVIEW(dev)) {
14641 dev_priv->display.modeset_commit_cdclk =
14642 valleyview_modeset_commit_cdclk;
14643 dev_priv->display.modeset_calc_cdclk =
14644 valleyview_modeset_calc_cdclk;
14645 } else if (IS_BROXTON(dev)) {
14646 dev_priv->display.modeset_commit_cdclk =
14647 broxton_modeset_commit_cdclk;
14648 dev_priv->display.modeset_calc_cdclk =
14649 broxton_modeset_calc_cdclk;
14652 switch (INTEL_INFO(dev)->gen) {
14654 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14658 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14663 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14667 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14670 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14671 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14674 /* Drop through - unsupported since execlist only. */
14676 /* Default just returns -ENODEV to indicate unsupported */
14677 dev_priv->display.queue_flip = intel_default_queue_flip;
14680 intel_panel_init_backlight_funcs(dev);
14682 mutex_init(&dev_priv->pps_mutex);
14686 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14687 * resume, or other times. This quirk makes sure that's the case for
14688 * affected systems.
14690 static void quirk_pipea_force(struct drm_device *dev)
14692 struct drm_i915_private *dev_priv = dev->dev_private;
14694 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14695 DRM_INFO("applying pipe a force quirk\n");
14698 static void quirk_pipeb_force(struct drm_device *dev)
14700 struct drm_i915_private *dev_priv = dev->dev_private;
14702 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14703 DRM_INFO("applying pipe b force quirk\n");
14707 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14709 static void quirk_ssc_force_disable(struct drm_device *dev)
14711 struct drm_i915_private *dev_priv = dev->dev_private;
14712 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14713 DRM_INFO("applying lvds SSC disable quirk\n");
14717 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14720 static void quirk_invert_brightness(struct drm_device *dev)
14722 struct drm_i915_private *dev_priv = dev->dev_private;
14723 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14724 DRM_INFO("applying inverted panel brightness quirk\n");
14727 /* Some VBT's incorrectly indicate no backlight is present */
14728 static void quirk_backlight_present(struct drm_device *dev)
14730 struct drm_i915_private *dev_priv = dev->dev_private;
14731 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14732 DRM_INFO("applying backlight present quirk\n");
14735 struct intel_quirk {
14737 int subsystem_vendor;
14738 int subsystem_device;
14739 void (*hook)(struct drm_device *dev);
14742 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14743 struct intel_dmi_quirk {
14744 void (*hook)(struct drm_device *dev);
14745 const struct dmi_system_id (*dmi_id_list)[];
14748 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14750 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14754 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14756 .dmi_id_list = &(const struct dmi_system_id[]) {
14758 .callback = intel_dmi_reverse_brightness,
14759 .ident = "NCR Corporation",
14760 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14761 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14764 { } /* terminating entry */
14766 .hook = quirk_invert_brightness,
14770 static struct intel_quirk intel_quirks[] = {
14771 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14772 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14774 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14775 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14777 /* 830 needs to leave pipe A & dpll A up */
14778 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14780 /* 830 needs to leave pipe B & dpll B up */
14781 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14783 /* Lenovo U160 cannot use SSC on LVDS */
14784 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14786 /* Sony Vaio Y cannot use SSC on LVDS */
14787 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14789 /* Acer Aspire 5734Z must invert backlight brightness */
14790 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14792 /* Acer/eMachines G725 */
14793 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14795 /* Acer/eMachines e725 */
14796 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14798 /* Acer/Packard Bell NCL20 */
14799 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14801 /* Acer Aspire 4736Z */
14802 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14804 /* Acer Aspire 5336 */
14805 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14807 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14808 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14810 /* Acer C720 Chromebook (Core i3 4005U) */
14811 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14813 /* Apple Macbook 2,1 (Core 2 T7400) */
14814 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14816 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14817 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14819 /* HP Chromebook 14 (Celeron 2955U) */
14820 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14822 /* Dell Chromebook 11 */
14823 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14826 static void intel_init_quirks(struct drm_device *dev)
14828 struct pci_dev *d = dev->pdev;
14831 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14832 struct intel_quirk *q = &intel_quirks[i];
14834 if (d->device == q->device &&
14835 (d->subsystem_vendor == q->subsystem_vendor ||
14836 q->subsystem_vendor == PCI_ANY_ID) &&
14837 (d->subsystem_device == q->subsystem_device ||
14838 q->subsystem_device == PCI_ANY_ID))
14841 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14842 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14843 intel_dmi_quirks[i].hook(dev);
14847 /* Disable the VGA plane that we never use */
14848 static void i915_disable_vga(struct drm_device *dev)
14850 struct drm_i915_private *dev_priv = dev->dev_private;
14852 u32 vga_reg = i915_vgacntrl_reg(dev);
14854 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14855 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14856 outb(SR01, VGA_SR_INDEX);
14857 sr1 = inb(VGA_SR_DATA);
14858 outb(sr1 | 1<<5, VGA_SR_DATA);
14859 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14862 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14863 POSTING_READ(vga_reg);
14866 void intel_modeset_init_hw(struct drm_device *dev)
14868 intel_update_cdclk(dev);
14869 intel_prepare_ddi(dev);
14870 intel_init_clock_gating(dev);
14871 intel_enable_gt_powersave(dev);
14874 void intel_modeset_init(struct drm_device *dev)
14876 struct drm_i915_private *dev_priv = dev->dev_private;
14879 struct intel_crtc *crtc;
14881 drm_mode_config_init(dev);
14883 dev->mode_config.min_width = 0;
14884 dev->mode_config.min_height = 0;
14886 dev->mode_config.preferred_depth = 24;
14887 dev->mode_config.prefer_shadow = 1;
14889 dev->mode_config.allow_fb_modifiers = true;
14891 dev->mode_config.funcs = &intel_mode_funcs;
14893 intel_init_quirks(dev);
14895 intel_init_pm(dev);
14897 if (INTEL_INFO(dev)->num_pipes == 0)
14900 intel_init_display(dev);
14901 intel_init_audio(dev);
14903 if (IS_GEN2(dev)) {
14904 dev->mode_config.max_width = 2048;
14905 dev->mode_config.max_height = 2048;
14906 } else if (IS_GEN3(dev)) {
14907 dev->mode_config.max_width = 4096;
14908 dev->mode_config.max_height = 4096;
14910 dev->mode_config.max_width = 8192;
14911 dev->mode_config.max_height = 8192;
14914 if (IS_845G(dev) || IS_I865G(dev)) {
14915 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14916 dev->mode_config.cursor_height = 1023;
14917 } else if (IS_GEN2(dev)) {
14918 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14919 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14921 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14922 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14925 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14927 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14928 INTEL_INFO(dev)->num_pipes,
14929 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14931 for_each_pipe(dev_priv, pipe) {
14932 intel_crtc_init(dev, pipe);
14933 for_each_sprite(dev_priv, pipe, sprite) {
14934 ret = intel_plane_init(dev, pipe, sprite);
14936 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14937 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14941 intel_init_dpio(dev);
14943 intel_shared_dpll_init(dev);
14945 /* Just disable it once at startup */
14946 i915_disable_vga(dev);
14947 intel_setup_outputs(dev);
14949 /* Just in case the BIOS is doing something questionable. */
14950 intel_fbc_disable(dev_priv);
14952 drm_modeset_lock_all(dev);
14953 intel_modeset_setup_hw_state(dev);
14954 drm_modeset_unlock_all(dev);
14956 for_each_intel_crtc(dev, crtc) {
14957 struct intel_initial_plane_config plane_config = {};
14963 * Note that reserving the BIOS fb up front prevents us
14964 * from stuffing other stolen allocations like the ring
14965 * on top. This prevents some ugliness at boot time, and
14966 * can even allow for smooth boot transitions if the BIOS
14967 * fb is large enough for the active pipe configuration.
14969 dev_priv->display.get_initial_plane_config(crtc,
14973 * If the fb is shared between multiple heads, we'll
14974 * just get the first one.
14976 intel_find_initial_plane_obj(crtc, &plane_config);
14980 static void intel_enable_pipe_a(struct drm_device *dev)
14982 struct intel_connector *connector;
14983 struct drm_connector *crt = NULL;
14984 struct intel_load_detect_pipe load_detect_temp;
14985 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14987 /* We can't just switch on the pipe A, we need to set things up with a
14988 * proper mode and output configuration. As a gross hack, enable pipe A
14989 * by enabling the load detect pipe once. */
14990 for_each_intel_connector(dev, connector) {
14991 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14992 crt = &connector->base;
15000 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15001 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15005 intel_check_plane_mapping(struct intel_crtc *crtc)
15007 struct drm_device *dev = crtc->base.dev;
15008 struct drm_i915_private *dev_priv = dev->dev_private;
15011 if (INTEL_INFO(dev)->num_pipes == 1)
15014 reg = DSPCNTR(!crtc->plane);
15015 val = I915_READ(reg);
15017 if ((val & DISPLAY_PLANE_ENABLE) &&
15018 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15024 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15026 struct drm_device *dev = crtc->base.dev;
15027 struct drm_i915_private *dev_priv = dev->dev_private;
15028 struct intel_encoder *encoder;
15032 /* Clear any frame start delays used for debugging left by the BIOS */
15033 reg = PIPECONF(crtc->config->cpu_transcoder);
15034 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15036 /* restore vblank interrupts to correct state */
15037 drm_crtc_vblank_reset(&crtc->base);
15038 if (crtc->active) {
15039 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15040 update_scanline_offset(crtc);
15041 drm_crtc_vblank_on(&crtc->base);
15044 /* We need to sanitize the plane -> pipe mapping first because this will
15045 * disable the crtc (and hence change the state) if it is wrong. Note
15046 * that gen4+ has a fixed plane -> pipe mapping. */
15047 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15050 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15051 crtc->base.base.id);
15053 /* Pipe has the wrong plane attached and the plane is active.
15054 * Temporarily change the plane mapping and disable everything
15056 plane = crtc->plane;
15057 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15058 crtc->plane = !plane;
15059 intel_crtc_disable_noatomic(&crtc->base);
15060 crtc->plane = plane;
15063 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15064 crtc->pipe == PIPE_A && !crtc->active) {
15065 /* BIOS forgot to enable pipe A, this mostly happens after
15066 * resume. Force-enable the pipe to fix this, the update_dpms
15067 * call below we restore the pipe to the right state, but leave
15068 * the required bits on. */
15069 intel_enable_pipe_a(dev);
15072 /* Adjust the state of the output pipe according to whether we
15073 * have active connectors/encoders. */
15075 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15076 enable |= encoder->connectors_active;
15079 intel_crtc_disable_noatomic(&crtc->base);
15081 if (crtc->active != crtc->base.state->active) {
15083 /* This can happen either due to bugs in the get_hw_state
15084 * functions or because of calls to intel_crtc_disable_noatomic,
15085 * or because the pipe is force-enabled due to the
15087 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15088 crtc->base.base.id,
15089 crtc->base.state->enable ? "enabled" : "disabled",
15090 crtc->active ? "enabled" : "disabled");
15092 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15093 crtc->base.state->active = crtc->active;
15094 crtc->base.enabled = crtc->active;
15096 /* Because we only establish the connector -> encoder ->
15097 * crtc links if something is active, this means the
15098 * crtc is now deactivated. Break the links. connector
15099 * -> encoder links are only establish when things are
15100 * actually up, hence no need to break them. */
15101 WARN_ON(crtc->active);
15103 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15104 WARN_ON(encoder->connectors_active);
15105 encoder->base.crtc = NULL;
15109 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15111 * We start out with underrun reporting disabled to avoid races.
15112 * For correct bookkeeping mark this on active crtcs.
15114 * Also on gmch platforms we dont have any hardware bits to
15115 * disable the underrun reporting. Which means we need to start
15116 * out with underrun reporting disabled also on inactive pipes,
15117 * since otherwise we'll complain about the garbage we read when
15118 * e.g. coming up after runtime pm.
15120 * No protection against concurrent access is required - at
15121 * worst a fifo underrun happens which also sets this to false.
15123 crtc->cpu_fifo_underrun_disabled = true;
15124 crtc->pch_fifo_underrun_disabled = true;
15128 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15130 struct intel_connector *connector;
15131 struct drm_device *dev = encoder->base.dev;
15133 /* We need to check both for a crtc link (meaning that the
15134 * encoder is active and trying to read from a pipe) and the
15135 * pipe itself being active. */
15136 bool has_active_crtc = encoder->base.crtc &&
15137 to_intel_crtc(encoder->base.crtc)->active;
15139 if (encoder->connectors_active && !has_active_crtc) {
15140 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15141 encoder->base.base.id,
15142 encoder->base.name);
15144 /* Connector is active, but has no active pipe. This is
15145 * fallout from our resume register restoring. Disable
15146 * the encoder manually again. */
15147 if (encoder->base.crtc) {
15148 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15149 encoder->base.base.id,
15150 encoder->base.name);
15151 encoder->disable(encoder);
15152 if (encoder->post_disable)
15153 encoder->post_disable(encoder);
15155 encoder->base.crtc = NULL;
15156 encoder->connectors_active = false;
15158 /* Inconsistent output/port/pipe state happens presumably due to
15159 * a bug in one of the get_hw_state functions. Or someplace else
15160 * in our code, like the register restore mess on resume. Clamp
15161 * things to off as a safer default. */
15162 for_each_intel_connector(dev, connector) {
15163 if (connector->encoder != encoder)
15165 connector->base.dpms = DRM_MODE_DPMS_OFF;
15166 connector->base.encoder = NULL;
15169 /* Enabled encoders without active connectors will be fixed in
15170 * the crtc fixup. */
15173 void i915_redisable_vga_power_on(struct drm_device *dev)
15175 struct drm_i915_private *dev_priv = dev->dev_private;
15176 u32 vga_reg = i915_vgacntrl_reg(dev);
15178 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15179 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15180 i915_disable_vga(dev);
15184 void i915_redisable_vga(struct drm_device *dev)
15186 struct drm_i915_private *dev_priv = dev->dev_private;
15188 /* This function can be called both from intel_modeset_setup_hw_state or
15189 * at a very early point in our resume sequence, where the power well
15190 * structures are not yet restored. Since this function is at a very
15191 * paranoid "someone might have enabled VGA while we were not looking"
15192 * level, just check if the power well is enabled instead of trying to
15193 * follow the "don't touch the power well if we don't need it" policy
15194 * the rest of the driver uses. */
15195 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15198 i915_redisable_vga_power_on(dev);
15201 static bool primary_get_hw_state(struct intel_crtc *crtc)
15203 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15205 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15208 static void readout_plane_state(struct intel_crtc *crtc,
15209 struct intel_crtc_state *crtc_state)
15211 struct intel_plane *p;
15212 struct intel_plane_state *plane_state;
15213 bool active = crtc_state->base.active;
15215 for_each_intel_plane(crtc->base.dev, p) {
15216 if (crtc->pipe != p->pipe)
15219 plane_state = to_intel_plane_state(p->base.state);
15221 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15222 plane_state->visible = primary_get_hw_state(crtc);
15225 p->disable_plane(&p->base, &crtc->base);
15227 plane_state->visible = false;
15232 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15234 struct drm_i915_private *dev_priv = dev->dev_private;
15236 struct intel_crtc *crtc;
15237 struct intel_encoder *encoder;
15238 struct intel_connector *connector;
15241 for_each_intel_crtc(dev, crtc) {
15242 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15243 memset(crtc->config, 0, sizeof(*crtc->config));
15244 crtc->config->base.crtc = &crtc->base;
15246 crtc->active = dev_priv->display.get_pipe_config(crtc,
15249 crtc->base.state->active = crtc->active;
15250 crtc->base.enabled = crtc->active;
15252 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15253 if (crtc->base.state->active) {
15254 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15255 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15256 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15259 * The initial mode needs to be set in order to keep
15260 * the atomic core happy. It wants a valid mode if the
15261 * crtc's enabled, so we do the above call.
15263 * At this point some state updated by the connectors
15264 * in their ->detect() callback has not run yet, so
15265 * no recalculation can be done yet.
15267 * Even if we could do a recalculation and modeset
15268 * right now it would cause a double modeset if
15269 * fbdev or userspace chooses a different initial mode.
15271 * If that happens, someone indicated they wanted a
15272 * mode change, which means it's safe to do a full
15275 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15278 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15279 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
15281 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15282 crtc->base.base.id,
15283 crtc->active ? "enabled" : "disabled");
15286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15287 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15289 pll->on = pll->get_hw_state(dev_priv, pll,
15290 &pll->config.hw_state);
15292 pll->config.crtc_mask = 0;
15293 for_each_intel_crtc(dev, crtc) {
15294 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15296 pll->config.crtc_mask |= 1 << crtc->pipe;
15300 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15301 pll->name, pll->config.crtc_mask, pll->on);
15303 if (pll->config.crtc_mask)
15304 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15307 for_each_intel_encoder(dev, encoder) {
15310 if (encoder->get_hw_state(encoder, &pipe)) {
15311 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15312 encoder->base.crtc = &crtc->base;
15313 encoder->get_config(encoder, crtc->config);
15315 encoder->base.crtc = NULL;
15318 encoder->connectors_active = false;
15319 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15320 encoder->base.base.id,
15321 encoder->base.name,
15322 encoder->base.crtc ? "enabled" : "disabled",
15326 for_each_intel_connector(dev, connector) {
15327 if (connector->get_hw_state(connector)) {
15328 connector->base.dpms = DRM_MODE_DPMS_ON;
15329 connector->encoder->connectors_active = true;
15330 connector->base.encoder = &connector->encoder->base;
15332 connector->base.dpms = DRM_MODE_DPMS_OFF;
15333 connector->base.encoder = NULL;
15335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15336 connector->base.base.id,
15337 connector->base.name,
15338 connector->base.encoder ? "enabled" : "disabled");
15342 /* Scan out the current hw modeset state,
15343 * and sanitizes it to the current state
15346 intel_modeset_setup_hw_state(struct drm_device *dev)
15348 struct drm_i915_private *dev_priv = dev->dev_private;
15350 struct intel_crtc *crtc;
15351 struct intel_encoder *encoder;
15354 intel_modeset_readout_hw_state(dev);
15356 /* HW state is read out, now we need to sanitize this mess. */
15357 for_each_intel_encoder(dev, encoder) {
15358 intel_sanitize_encoder(encoder);
15361 for_each_pipe(dev_priv, pipe) {
15362 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15363 intel_sanitize_crtc(crtc);
15364 intel_dump_pipe_config(crtc, crtc->config,
15365 "[setup_hw_state]");
15368 intel_modeset_update_connector_atomic_state(dev);
15370 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15371 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15373 if (!pll->on || pll->active)
15376 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15378 pll->disable(dev_priv, pll);
15382 if (IS_VALLEYVIEW(dev))
15383 vlv_wm_get_hw_state(dev);
15384 else if (IS_GEN9(dev))
15385 skl_wm_get_hw_state(dev);
15386 else if (HAS_PCH_SPLIT(dev))
15387 ilk_wm_get_hw_state(dev);
15389 for_each_intel_crtc(dev, crtc) {
15390 unsigned long put_domains;
15392 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15393 if (WARN_ON(put_domains))
15394 modeset_put_power_domains(dev_priv, put_domains);
15396 intel_display_set_init_power(dev_priv, false);
15399 void intel_display_resume(struct drm_device *dev)
15401 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15402 struct intel_connector *conn;
15403 struct intel_plane *plane;
15404 struct drm_crtc *crtc;
15410 state->acquire_ctx = dev->mode_config.acquire_ctx;
15412 /* preserve complete old state, including dpll */
15413 intel_atomic_get_shared_dpll_state(state);
15415 for_each_crtc(dev, crtc) {
15416 struct drm_crtc_state *crtc_state =
15417 drm_atomic_get_crtc_state(state, crtc);
15419 ret = PTR_ERR_OR_ZERO(crtc_state);
15423 /* force a restore */
15424 crtc_state->mode_changed = true;
15427 for_each_intel_plane(dev, plane) {
15428 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15433 for_each_intel_connector(dev, conn) {
15434 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15439 intel_modeset_setup_hw_state(dev);
15441 i915_redisable_vga(dev);
15442 ret = drm_atomic_commit(state);
15447 DRM_ERROR("Restoring old state failed with %i\n", ret);
15448 drm_atomic_state_free(state);
15451 void intel_modeset_gem_init(struct drm_device *dev)
15453 struct drm_i915_private *dev_priv = dev->dev_private;
15454 struct drm_crtc *c;
15455 struct drm_i915_gem_object *obj;
15458 mutex_lock(&dev->struct_mutex);
15459 intel_init_gt_powersave(dev);
15460 mutex_unlock(&dev->struct_mutex);
15463 * There may be no VBT; and if the BIOS enabled SSC we can
15464 * just keep using it to avoid unnecessary flicker. Whereas if the
15465 * BIOS isn't using it, don't assume it will work even if the VBT
15466 * indicates as much.
15468 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15469 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15472 intel_modeset_init_hw(dev);
15474 intel_setup_overlay(dev);
15477 * Make sure any fbs we allocated at startup are properly
15478 * pinned & fenced. When we do the allocation it's too early
15481 for_each_crtc(dev, c) {
15482 obj = intel_fb_obj(c->primary->fb);
15486 mutex_lock(&dev->struct_mutex);
15487 ret = intel_pin_and_fence_fb_obj(c->primary,
15491 mutex_unlock(&dev->struct_mutex);
15493 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15494 to_intel_crtc(c)->pipe);
15495 drm_framebuffer_unreference(c->primary->fb);
15496 c->primary->fb = NULL;
15497 c->primary->crtc = c->primary->state->crtc = NULL;
15498 update_state_fb(c->primary);
15499 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15503 intel_backlight_register(dev);
15506 void intel_connector_unregister(struct intel_connector *intel_connector)
15508 struct drm_connector *connector = &intel_connector->base;
15510 intel_panel_destroy_backlight(connector);
15511 drm_connector_unregister(connector);
15514 void intel_modeset_cleanup(struct drm_device *dev)
15516 struct drm_i915_private *dev_priv = dev->dev_private;
15517 struct drm_connector *connector;
15519 intel_disable_gt_powersave(dev);
15521 intel_backlight_unregister(dev);
15524 * Interrupts and polling as the first thing to avoid creating havoc.
15525 * Too much stuff here (turning of connectors, ...) would
15526 * experience fancy races otherwise.
15528 intel_irq_uninstall(dev_priv);
15531 * Due to the hpd irq storm handling the hotplug work can re-arm the
15532 * poll handlers. Hence disable polling after hpd handling is shut down.
15534 drm_kms_helper_poll_fini(dev);
15536 intel_unregister_dsm_handler();
15538 intel_fbc_disable(dev_priv);
15540 /* flush any delayed tasks or pending work */
15541 flush_scheduled_work();
15543 /* destroy the backlight and sysfs files before encoders/connectors */
15544 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15545 struct intel_connector *intel_connector;
15547 intel_connector = to_intel_connector(connector);
15548 intel_connector->unregister(intel_connector);
15551 drm_mode_config_cleanup(dev);
15553 intel_cleanup_overlay(dev);
15555 mutex_lock(&dev->struct_mutex);
15556 intel_cleanup_gt_powersave(dev);
15557 mutex_unlock(&dev->struct_mutex);
15561 * Return which encoder is currently attached for connector.
15563 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15565 return &intel_attached_encoder(connector)->base;
15568 void intel_connector_attach_encoder(struct intel_connector *connector,
15569 struct intel_encoder *encoder)
15571 connector->encoder = encoder;
15572 drm_mode_connector_attach_encoder(&connector->base,
15577 * set vga decode state - true == enable VGA decode
15579 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15581 struct drm_i915_private *dev_priv = dev->dev_private;
15582 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15585 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15586 DRM_ERROR("failed to read control word\n");
15590 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15594 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15596 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15598 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15599 DRM_ERROR("failed to write control word\n");
15606 struct intel_display_error_state {
15608 u32 power_well_driver;
15610 int num_transcoders;
15612 struct intel_cursor_error_state {
15617 } cursor[I915_MAX_PIPES];
15619 struct intel_pipe_error_state {
15620 bool power_domain_on;
15623 } pipe[I915_MAX_PIPES];
15625 struct intel_plane_error_state {
15633 } plane[I915_MAX_PIPES];
15635 struct intel_transcoder_error_state {
15636 bool power_domain_on;
15637 enum transcoder cpu_transcoder;
15650 struct intel_display_error_state *
15651 intel_display_capture_error_state(struct drm_device *dev)
15653 struct drm_i915_private *dev_priv = dev->dev_private;
15654 struct intel_display_error_state *error;
15655 int transcoders[] = {
15663 if (INTEL_INFO(dev)->num_pipes == 0)
15666 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15670 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15671 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15673 for_each_pipe(dev_priv, i) {
15674 error->pipe[i].power_domain_on =
15675 __intel_display_power_is_enabled(dev_priv,
15676 POWER_DOMAIN_PIPE(i));
15677 if (!error->pipe[i].power_domain_on)
15680 error->cursor[i].control = I915_READ(CURCNTR(i));
15681 error->cursor[i].position = I915_READ(CURPOS(i));
15682 error->cursor[i].base = I915_READ(CURBASE(i));
15684 error->plane[i].control = I915_READ(DSPCNTR(i));
15685 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15686 if (INTEL_INFO(dev)->gen <= 3) {
15687 error->plane[i].size = I915_READ(DSPSIZE(i));
15688 error->plane[i].pos = I915_READ(DSPPOS(i));
15690 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15691 error->plane[i].addr = I915_READ(DSPADDR(i));
15692 if (INTEL_INFO(dev)->gen >= 4) {
15693 error->plane[i].surface = I915_READ(DSPSURF(i));
15694 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15697 error->pipe[i].source = I915_READ(PIPESRC(i));
15699 if (HAS_GMCH_DISPLAY(dev))
15700 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15703 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15704 if (HAS_DDI(dev_priv->dev))
15705 error->num_transcoders++; /* Account for eDP. */
15707 for (i = 0; i < error->num_transcoders; i++) {
15708 enum transcoder cpu_transcoder = transcoders[i];
15710 error->transcoder[i].power_domain_on =
15711 __intel_display_power_is_enabled(dev_priv,
15712 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15713 if (!error->transcoder[i].power_domain_on)
15716 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15718 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15719 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15720 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15721 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15722 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15723 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15724 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15730 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15733 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15734 struct drm_device *dev,
15735 struct intel_display_error_state *error)
15737 struct drm_i915_private *dev_priv = dev->dev_private;
15743 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15744 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15745 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15746 error->power_well_driver);
15747 for_each_pipe(dev_priv, i) {
15748 err_printf(m, "Pipe [%d]:\n", i);
15749 err_printf(m, " Power: %s\n",
15750 error->pipe[i].power_domain_on ? "on" : "off");
15751 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15752 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15754 err_printf(m, "Plane [%d]:\n", i);
15755 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15756 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15757 if (INTEL_INFO(dev)->gen <= 3) {
15758 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15759 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15761 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15762 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15763 if (INTEL_INFO(dev)->gen >= 4) {
15764 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15765 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15768 err_printf(m, "Cursor [%d]:\n", i);
15769 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15770 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15771 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15774 for (i = 0; i < error->num_transcoders; i++) {
15775 err_printf(m, "CPU transcoder: %c\n",
15776 transcoder_name(error->transcoder[i].cpu_transcoder));
15777 err_printf(m, " Power: %s\n",
15778 error->transcoder[i].power_domain_on ? "on" : "off");
15779 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15780 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15781 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15782 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15783 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15784 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15785 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15789 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15791 struct intel_crtc *crtc;
15793 for_each_intel_crtc(dev, crtc) {
15794 struct intel_unpin_work *work;
15796 spin_lock_irq(&dev->event_lock);
15798 work = crtc->unpin_work;
15800 if (work && work->event &&
15801 work->event->base.file_priv == file) {
15802 kfree(work->event);
15803 work->event = NULL;
15806 spin_unlock_irq(&dev->event_lock);